Digital oscillation apparatus

Abstract: An apparatus that generates a cyclic waveform of op­ tional multiples of clock frequency in a digital signal processing. The apparatus accumulates a data string having a predetermined average value and a constant with an ac­ cumulating circuit which overflows when the data exceeds a dynamic range, thereby to provide cyclic waveform data proportional to the sum of the average value and the con­ stant. Accumulation of the sum of the average value and the constant provides a cyclic waveform of optional multiples of the clock frequency by changing the average value of the data string even if the constant is integer.

Description: The present invention relates to a digital oscillation apparatus that generates waveform data representing a periodic waveform having a desired period. Conventionally, in order to obtain periodic waveform data, an oscillation apparatus that accumulates a specific constant for every clock by use of an adder that overflows when the data exceeds a dynamic range. This apparatus can vary the period of the generated waveform by varying the value of the constant to be accumulated. However, since it cannot select any value for the constant in the integer operation, the period which can be obtained is limited. In IBM Technical Disclosure Bulletin, vol. 22, No. 3, August 1979, pages 975 to 978, there is disclosed an acoustic interactive synthesizer for generating digital sine waves using a recycling shift register which is loaded and controlled by a computer, and for converting the shift register output into the desired analog acoustic signals that are required. Small frequency changes may be produced by using an adder arrangement comprising serial adders which separate the clock frequency division into independent ranges, which are referred to as "course", "fine" and "very fine" frequency controls. The adders are controlled by computer to control the output frequency of a sine wave. An object of the present invention is to provide a digital oscillation apparatus which generates a periodic waveform data whose period is any rational-number multiple of the clock period. This object can be achieved by providing a digital oscillation apparatus for generating a periodic waveform data having a frequency fs, characterized by comprising: data generating means responsive to each clock of a clock signal having a frequency fc for generating a data to generate a data string having a constant total value of R periodically with a period of m clocks so that the average value of each data of the data string generated in response to each clock of the clock signal becomes R/m, where each of R and m is an integer, said data generating means comprising an accumulator responsive to the clock signal for accumulating the value R, an overflow detecting means for detecting an overflow of the accumulator when the accumulated value of the accumulator exceeds the value m, said overflow detecting means normally outputting the value of O and, upon detection of the overflow, outputting the value of 1, and a means responsive to the detection of the overflow by the overflow detecting means for resetting the accumulating value of the accumulator to the value obtained by subtracting the value m from the accumulated value, the output of said overflow detecting means being used as said data string generated by said data generating means; and accumulating means having a dynamic range D, where D is an integer, and being responsive to each clock of the clock signal for accumulating a sum of each data of the data string generated by said data generating means and a constant A, where A is an integer, to obtain an accumulated data until the accumulated data exceeds the dynamic range D and subtracting the dynamic range D from the accumulated data when the accumulated data exceeds the dynamic range D, thereby generating a periodic waveform data having a frequency fs, wherein the values of R, m, A and D satisfy a condition of fs/fc = (A + R/m)/D so that the frequency fs of the period waveform data becomes fs = (A + R/m).fc/D. FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention; FIG. 2 is a waveform diagram showing an output data waveform of the first embodiment of the present invention; FIG 3 is a block diagram showing a configuration of a second embodiment of the present invention; FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention; FIG. 5 is a block diagram showing a configuration of a fourth embodiment of the present invention; FIG. 6 is a waveform diagram showing waveform of data stored in a ROM in the fourth embodiment of the present invention; and FIG. 7 is a block diagram showing a fifth embodiment of the present invention. In FIG. 1, a digital oscillation apparatus comprises an accumulating section 1 and a data generating section 2. The accumulating section 1 is responsive to a clock signal to accumulate a constant A and an output of the data generating section 2 clock by clock. When the output of the data generating section 2 is constantly zero (0), an output waveform data as shown in FIG. 2 is obtained. That is, if the clock period be τ, data increases by A at intervals of τ, and when the data exceeds a dynamic range D, it overflows. As the result, a saw-tooth wave data is obtained. As clear from FIG. 2, if the period of this saw-tooth waveform be T, the following relation holds: T = D·τ/A Supposing that the clock frequency be fc and the saw-tooth wave frequency fs (i.e. fc = 1/τ and fs = 1/T), Eq. (I) can be rewritten as: fs = (A/D) ·fc Thus, by changing the constant A and dynamic range D, the frequency of the saw-tooth waveform can be changed. However, in general, the accumulating section 1 operates in binary notation, and in such event, D becomes an exponentiation of two. Thus, if fs is to be optionally set in accordance with Eq. (2), optional A must be given. However, since A is also an integer, an optional fs cannot be obtained. The data generating section 2 is provided to solve this problem, and functions as follows. The data generating section 2 periodically generates a data string a period of m clocks (m is integer), and the total of the data string in each period is R (R is integer). Thus, the data average is R/m. Because the data having such average value is given to the accumulating section 1 always together with the constant A, the accumulating section is, on the average, equivalent to accumulating A + R/m value every clock. Consequently, substituting A in Eq. (2) for A + R/m gives fs = {(A + R/m)}/D·fc Thus, proper selection of the integers R and m gives an optional frequency fs. Eq. (3) can be also interpreted as follows. In Eq. (3), (A + R/m)/D denotes the ratio of to saw-tooth wave frequency fs to clock frequency fc, and if the ratio is expressed as k/h (where k and h are natural numbers and k/h the irreducible fraction), we obtain k/h = (A + R/m)/D Consequently, if the dynamic range D of the accumulating section 1 and the ratio k/h are given, A, R, and m can be obtained as follows: k·D/h = A + R/m Thus, from Eq. (5), dividing k·D by h gives the quotient A with remainder R, and m is a denominator when k·D/h is reduced. For example, if D = 512, k = 3, and h = 22, from Eq. (5) the left member is 3 x 512/22 = 768/11 = (69 x 11 + 9)/11 Thus, A = 69, R = 9, and m = 11. Now, referring to FIG. 3, the second embodiment of the present invention is described hereunder. In FIG. 3 the accumulating section 3 comprises an adder 10 and a D-flip-flop 11 working as a delay circuit. Because the output of the adder 10 is delayed by one clock with the D-flip-flop 11 and returned to one input of the adder 10, the constant A inputted to another input of the adder 10 is accumulated every clock. The adder 10 overflows when the accumulated valve exceeds D. The adder 10 possesses a carry input, to which the output of the data generating section 4 is inputted. The data generating section 4 of this embodiment comprises an adder 5, an overflow detector 6, a switching circuit 8, a subtraction circuit 7, and a D-flip-flop 9. The adder 5 adds R to the output of the D flip-flop 9. The output of the adder 5 is checked by the overflow detector 6 if it exceeds m, and should it exceed m, the switching circuit 8 switches to its terminal 13 to subtract m from the output of the adder 5 with the subtractor 7. The output of the subtractor 7 is fed to the D-flip-flop 9. The output of the D flip-flop 9 is returned to the adder 5. The overflow detector 6 outputs "1" when detecting overflow and "0" otherwise to the carry input of the adder 10 in the accumulating section 3. Because the above configuration is equivalent to accumulating R in the residual algebraic system with m as module, adding R by m times produces the same result. That is, the output data of the adder 5 has a cycle m, and the overflow detector 6 outputs "1" at the rate of R times to m times. Consequently, the average of m times of outputs of the overflow detector 6 becomes R/m, and adding this signal to the carry input of the adder 10 in the accumulating section 3 can produce equivalent effect to that of the first embodiment. The present embodiment is advantageous in that it can utilize the carry input of the adder 10 because the output of the data generating section 4 is either "0" or "1", that is, 1 bit. Now referring to FIG. 4, the third embodiment is described. In this embodiment, the accumulating section 3 is the same as that of the second embodiment, while the data generating section 20 comprises an m-counter 22 and a ROM 21. The m-counter 22 divides the clock frequency by m. Same as the second embodiment, the data generating section 20 is a circuit to output "1" at the rate of R times to m times. In the present embodiment, the output of the m-counter 22 is given to the address input of ROM 21. ROM 21 stores "1" in R addresses out of m addresses, and "0" in the remaining m-R addresses. This allows the third embodiment to perform the same operation as the first embodiment. Alternatively, if ROM 21 stores in advance a pattern to be obtained at the output of the data generating section 4 of the second embodiment, the third embodiment performs the same operation as the second embodiment. Now, referring to FIG. 5, the fourth embodiment of the present invention is described. This embodiment is realized by adding a ROM 30 and a D/A converter 31 to the first embodiment. The output waveform of the accumulating section 1 is saw-tooth waveform as shown in the first embodiment. Therefore, if sinusoidal data is stored in advance in ROM 30 as shown in FIG. 6 and the output data of the accumulating section 1 is fed to the address input of ROM 30, the output data of ROM 30 becomes a sinusoidal waveform data. It is possible to convert this data with the D/A converter 31 to an analog sine wave. Storing an optional waveform data other than sine wave in ROM 30 allows an optional waveform to be produced. Now, referring to FIG. 7, the fifth embodiment of the present invention is described. This embodiment is realized by adding a D/A converter 32 to the first embodiment, thereby providing an analog saw-tooth waveform.

Claims: A digital oscillation apparatus for generating a periodic waveform data having a frequency fs, characterized by comprising: data generating means (2,4) responsive to each clock of a clock signal having a frequency fc for generating a data to generate a data string having a constant total value of R periodically with a period of m clocks so that the average value of each data of the data string generated in response to each clock of the clock signal becomes R/m, where each of R and m is an integer, said data generating means comprising an accumulator (5,9) responsive to the clock signal for accumulating the value R, an overflow detecting means (6) for detecting an overflow of the accumulator when the accumulated value of the accumulator exceeds the value m, said overflow detecting means normally outputting the value of O and, upon detection of the overflow, outputting the value of 1, and a means (7,8) responsive to the detection of the overflow by the overflow detecting means for resetting the accumulating value of the accumulator to the value obtained by subtracting the value m from the accumulated value, the output of said overflow detecting means being used as said data string generated by said data generating means; and accumulating means (1,3) having a dynamic range D, where D is an integer, and being responsive to each clock of the clock signal for accumulating a sum of each data of the data string generated by said data generating means and a constant A, where A is an integer, to obtain an accumulated data until the accumulated data exceeds the dynamic range D and subtracting the dynamic range D from the accumulated data when the accumulated data exceeds the dynamic range D, thereby generating a periodic waveform data having a frequency fs, wherein the values of R, m, A and D satisfy a condition of fs/fc = (A + R/m)/D so that the frequency fs of the period waveform data becomes fs = (A + R/m).fc/D. A digital oscillation apparatus according to claim 1, wherein said accumulating means (1,3) comprises: delay means (11) for delaying a data inputted thereto by one clock period; and adding means (10) for adding the constant A, an output data of said delay means and, as a carry, the data generated by said data generating means, the added data being fed to said delay means and at the same time being outputted as the accumulated data. A digital oscillation apparatus according to claim 1, further comprising memory means (30) having stored therein data corresponding to a predetermined waveform and receiving the waveform data from said accumulating means (1) as an address data for outputting the stored data to obtain a predetermined periodic waveform data. A digital oscillation apparatus according to claim 3, wherein said memory means (30) has stored therein sinusoidal waveform data. A digital oscillation apparatus according to claim 3, further comprising digital-to-analog conversion means (31) for converting the waveform data from said memory means (30) to an analog waveform signal. A digital oscillation apparatus according to claim 1, further comprising digital-to-analog conversion means (32) for converting the waveform data from said accumulating means (1) to an analog waveform signal.

Inventors: MATSUMOTO TOKIKAZU, MATSUMOTO, TOKIKAZU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: G06F7
IPC codes: G06F1, G06F7, H03B28, H03K25, H03K4