Source electrode driving circuit for matrix type liquid crystal display apparatus

Abstract: A source electrode driving circuit for a matrix type liquid cry­ stal display apparatus is respectively provided in the plurality of a partial source electrode driving circuits to output a sampling sig­ nal into the shift register (11) after counting of the clock signals by the number of the stages of the shift register has been repeated by an externally set number, with an input timing signal as a reference, so that a connection signal between the partial source electrode dri­ ving circuits which causes an image disturbances is not required, with the result of superior display images.

Description: The present invention generally relates to a source electrode driving circuit for a matrix type liquid crystal display apparatus. Generally, a matrix type liquid crystal display apparatus with a switching transistor being added to each of picture elements of the display is used as a display apparatus for a pocket appliance or the like, because a display of high contrast can be achieved by the switching function of the transistor even when a multiplex driving technique for multiline display is used. The matrix type liquid crystal display apparatus has a switching transistor 51-d built in the display picture-element 51-c of the respective intersecting points between the gate electrode 51-a and the source electrode 51-b provided on one base plate of the liquid crystal panel 51 as shown in Fig. 5. There are provided a gate electrode driving circuit 52 for adding to the respective gate electrodes 51-a scanning pulses, which is adapted to sequentially turn on the switching transistors of the respective lines, and a source electrode driving circuit 53 for adding to the respective source electrodes 51-b the voltages corresponding to the varying brightness of the display of the respective picture elements, a controlling circuit 54 for controlling the operations of the gate electrode driving circuit 52, the gate electrode driving circuit 53 and so on. The conventional source electrode driving circuit like this is shown in Fig. 6. The source electrode driving circuit is composed of a sampling hold circuit 62 which is adapted to sample and hold the voltages corresponding to the variable brightness of the respective picture elements from the display signal V, an output buffer circuit 63 which is adapted to simultaneously output into the respective source electrodes 51-b at a timing time T the voltages Q₁, ..., Q n held by the sampling hold circuit 62, a shift register 61 which is adapted to sequentially shift, in accordance with the clock , the sampling signals D for sequentially operating the sampling hold circuit 62 so as to input the outputs q₁, ..., q n into the sampling hold circuit corresponding to each column. As shown in Fig. 7, the display signals V are normally inputted in series for every one picture element. The shift register 61 sequentially shifts the sampling signals D by the clock  to input the outputs q₁, ..., q n into the sampling hold circuit corresponding to each column to sequentially cause it to effect the sampling hold operation, so that the voltages Vi1, ..., Vij, ..., Vin at the moments corresponding to the driving source electrodes among the display signals are held in the sampling hold circuit 62. The held voltages Q₁, ..., Q n are simultaneously outputted into each source electrodes through the output buffer circuit 63 as shown in Fig. 6. In this manner, the voltages corresponding to the varying brightness of the display are applied upon each source electrodes by the source electrode driving circuit to apply the electrodes upon the liquid crystal through the switching transistors, so that the display operation is effected. The conventional source electrode driving circuit is composed of a large scale integrated circuit (LSI) (see also DE-A-3 526 321), as shown in Fig. 8, when the driving electrodes are many in number. In this case, as the above-described sampling hold operation is required to be continuously effected about all the LSIs, the output of the last stage of the shift register circuit 61 of each LSI is adapted to be inputted into the input terminal of the shift register circuit 61 of the next LSI. As the shift register circuit 61 of all the LSIs is adapted to effect, in all, the same operation as that of one shift register circuit, so that the continuous display is provided by the plurality of LSIs. Generally, in the driving circuit for a matrix type liquid crystal display apparatus, digital signals are used with analog signals, with an influence problem that noises are mixed from the digital signals to the analog signals. Particularly, in the use as the display apparatus for a television image display appliance of a small type, high-frequency noises radiated into the air are mixed into the antenna of the appliance itself, in addition to the direct influences through the power wire, signal wire, so as to disturb the display images. Furthermore, as comparatively large current flows at a moment the level of the digital signal varies, linear image disturbances which are synchronized with the digital signals appear on the picture image because of the influences thereof. As a countermeasure against the above-described problem, each digital signal whose level varies while the sampling operation is effected is tried not to be used as much as possible within the source electrode driving circuit. It is considered to add a circuit for removing the high frequency component of the signal in a position as near as possible to the supply end of each digital signal. However, when a plurality of LSIs are connected in concatenated construction in the conventional source electrode driving circuit, the connection signals between the LSIs become necessarily digital signals, whose level varies within the sampling operation period, thus causing such image disturbances as described hereinabove. As the LSIs are often provided normally in high density, it is often that effective noise countermeasures can not be taken against the connection signals near the LSIs. Accordingly, an essential object of the present invention is to provide a source electrode driving circuit for a matrix type liquid crystal display apparatus, wherein partial source electrode driving circuits by, for example, LSIs are connected in a plurality of concatenated relation, the connection signals between the partial source electrode driving circuits, which cause the image disorders, are not required, thus providing the superior display images. In accomplishing these and other objects, according to one preferred embodiment of the present invention, the present invention is characterized in that shift register controlling circuits, each outputting into the shift register the sampling signals, are respectively provided on each partial source electrode driving circuit after the operation for counting the clock signals by the step-number of the shift register has been repeated by the externally set number, with the inputted timing signal as reference, in a source electrode driving circuit for a matrix type liquid crystal display apparatus composed of a plurality of concatenated connection of sampling hold circuits each sampling, holding from the input display signal the voltage corresponding to the variable brightness of the display to be applied to each of the picture elements through a switching element to be added to the respective picture elements of the matrix type liquid crystal display apparatus, of output buffer circuits each outputting to each of the switching elements the voltage held by the sampling hold circuit, partial source electrode driving circuits each including a shift register which sequentially shifts in accordance with the clock signal the sampling signal for sequentially operating the sampling hold circuit. In the above-described construction, the shift register control circuit provided on each partial source electrode driving circuit outputs the sampling signals into the shift register after the operation that the clock signals are counted by the number of stages of the shift register has been repeated by the externally setting number with the inputting timing signal as reference. The shift register sequentially shifts the sampling signal in accordance with the clock signal to sequentially operate the sampling hold circuit. Thus, the sampling hold circuit samples and holds from the input display signal the voltage corresponding to the variable brightness of the display to be applied to each picture element. The output buffer circuit outputs the held voltage into the switching element added to each picture element. Accordingly, the connection signal is not required between each partial source electrode driving circuit, thus causing no noises, so that the images are not disturbed. These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing the circuit construction of each LSI in one embodiment of a source electrode driving circuit of a matrix type liquid crystal display apparatus of the present invention; Fig. 2 is a driving waveform chart for illustrating the circuit operation in the embodiment; Fig. 3 is a diagram showing how a plurality of concatenated LSIs are connected in the embodiment; Fig. 4 is a diagram showing one embodiment of the logical circuit of a shift register control circuit in the embodiment; Fig. 5 is a block diagram showing the circuit construction of the general matrix type liquid crystal display apparatus; Fig. 6 is a block diagram showing the source electrode driving circuit of the conventional matrix type liquid crystal display apparatus; Fig. 7 is a driving wave form chart for illustrating the circuit operation in the conventional embodiment; and Fig. 8 is a block diagram showing the circuit construction in a case where the conventional source electrode driving circuit is composed of a plurality of concatenated LSIs. Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings. Referring now to the drawings, a source electrode driving circuit of the present embodiment has a plurality of concatenated LSIs, as a partial source electrode circuit, each having a shift register circuit 11, a sample hold circuit 12, an output buffer circuit 13 and a shift register control circuit 14. The shift register circuit 11, the sampling hold circuit 12, the output buffer circuit 13 are the same in construction as in the conventional embodiment. The sampling signal D to be inputted into the shift register 11 was inputted from the external portion in the conventional embodiment, but in the present embodiment, the sampling signal is composed by the shift register control circuit 14. The shift register control circuit 14 is composed of a sampling signal generating circuit 15 and a timing selection circuit 16 as shown in Fig. 1. The sampling signal generating circuit 15 generates one sampling signal every time the clocks  are counted by k number with an externally inputted timing signal S as a reference when the number of the stages of the shift register circuit 11 is assumed to be k. The timing selection circuit 16 selects the ℓth (ℓ = 0, 1, 2, ...) signal among a series of sampling signals made by the sampling signal generating circuit 15 through the external setting to input it into the shift register circuit 11. A clock signal  which is the same as the clock signal to be inputted to the shift register 11, and a timing signal S which controls the start position of the sampling operation are inputted, as shown in Fig. 2, into the sampling signal generating circuit 15. And the sampling signal generating circuit 15, immediately after the timing signal S has been inputted, generates one sampling signal C at first, and thereafter the sampling signal C one by one every time the clocks  are counted as many as the stage-number k of the shift register circuit 11 so as to output the sampling signal C into the timing selection circuit 16. The interval tk between the sampling signals C is the same as the time required for the sampling signal to completely shift all the stages of the shift register circuit. Also, the timing selection circuit 16 takes out only the ℓth pulse from among a series of inputted sampling signals C to output it as a sampling signal D into the shift register circuit 11. Namely, as shown in Fig. 3, the sampling signal D₀ is outputted into the shift register 11 in the LSI1 (ℓ=0), the sampling signal D₁ is outputted thereinto in the LSI2 (ℓ=1), the sampling signal D₂ in the LSI3 (ℓ=2). In Fig. 2, D₀, D₁, D₂, D₃ shows the cases of ℓ = 0, 1, 2, 3 respectively among the sampling signal D, with the sampling signals D₁, D₂, D₃ being the same in timing as the connecting signals among the respective LSIs in a case where the number of the stages of the shift register circuits of the respective LSIs in the conventional embodiment shown in Fig. 8 is k. As the connection pulses among a plurality of concatenated LSIs are not required, and the sampling signals which are the same in timing as the connection signals are adapted to be caused by the respective LSIs, the display images are not disturbed by such noise influences as shown in the conventional embodiment, so that superior display images may be provided. The timing signal S is a signal which is varied in level beyond the sampling period. Also, as the timing signal S is made outside the LSI, a circuit for noise countermeasure use may be easily added, thus causing no display-image disturbances. Fig. 4 shows one embodiment of a logical circuit of the shift register control circuit 14. The logical circuit shows a case where the k is 64, the maximum value of the setting value of the ℓ is 3, with the setting of the ℓ being effected by the setting signal ℓ₀ and ℓ₁ of 2 bits. As is clear from the foregoing description, according to the arrangement of the present invention, the source electrode driving circuit for a matrix type liquid crystal display apparatus of the present invention has a plurality of concatenated sampling hold circuits for sampling and holding from the input display signal the voltage corresponding to the variable brightness of the display to be applied to each picture element through the switching element added to each of picture elements of a matrix type liquid crystal display apparatus, output buffer circuit for outputting to each of the switching elements the voltage held by the sampling hold circuit, partial source electrode driving circuit having a shift register which sequentially shifts, in accordance with a clock signal, the sampling signal for sequentially operating the sampling hold circuit. The shift register control circuits provided respectively in the plurality of partial source electrode driving circuits are adapted to output the sampling signal into the shift register after the operation of counting the clock signals by the number of stages of the shift register has been repeated by the number to be externally set, with the inputted timing signal as the reference. Thus, the connection signal between the partial source electrode driving circuits, which causes the image disturbances are not required, thus providing the superior display images. Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims.

Claims: A source electrode driving circuit for a matrix type liquid crystal display device comprising a plurality of sample and hold circuits (12), each said sample and hold circuit having a concatenated connection for sampling and holding from the input display signal the voltage corresponding to the variable brightness of the display to be applied to each of the picture elements, in synchronism with a clock signal, through a switching element, which is connected in series with the respective picture elements of the matrix type liquid crystal display apparatus, each sample and hold circuit further having a respective output buffer circuit (13) outputting to a respective switching element the voltage held by the sample and hold circuit, a shift register (11) which sequentially shifts, in accordance with the clock signal, a sampling signal for sequentially initiating the sampling operation of each of said plurality of sample and hold circuits, and a shift register controlling circuit (14) outputting into the shift register (11) the sampling signal each time after an operation for counting a number of clock pulses corresponding to the number of stages in the shift register has been repeated an externally set number of times, using an input timing signal (S) as reference to control the start position of the sampling operation to said each shift register controlling circuit. The circuit as defined in Claim 1, wherein the sampling signal is composed by the shift register control circuit (14) comprising a sampling signal generating circuit (15) and a timing selection circuit (16), the sampling signal generating circuit generating one sampling signal every k clock pulses using an externally input timing signal as a reference, where k is the number of the stages of the shift register circuit (11), and the timing selection circuit (16) selecting only the lth (l = 0,1,2,...) signal among a series of sampling signals made by the sampling signal generating circuit through the external setting to input said lth (l = 0,1,2,...) signal into the shift register circuit in accordance with the said lth (l = 0,1,2,...) signal number. The circuit as defined in Claim 2, wherein the clock signal which is the same as the clock signal to be input to the shift register (11), and an input timing signal which controls the start position of the sampling operation are input into the sampling signal generating circuit, and the sampling signal generating circuit (15), immediately after the timing signal (S) has been input generates one sampling signal at first, and thereafter the sampling signal one by one, every time k clock signals, are counted so as to output the sampling signal into the timing selection circuit (16), the interval between the sampling signals being the same as the time required for the sampling signal to completely shift all the stages of the shift register circuit (11).

Inventors: TAKEDA MAKOTO, TAKEDA, MAKOTO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1988
Main classification: G09G3
IPC codes: G02F1, H04N3, G09G3