Electronic circuit device for diagnosing status-holding circuits by scanning

Abstract: An electronic circuit device for diagnosing a status-holding circuit by scanning, the device comprising a first plurality of integrated circuits each including a serial scan circuit for receiving serial data, genera­ ting an address value of a target status-holding circuit as parallel data from the received serial data, and selecting the target status-holding circuit having the generated address value, and a second plurality of integrated circuits each including a parallel scan circuit for receiving an address value of a target status-holding circuit as parallel data and selecting the target status-holding circuit having the received address value. Address information received as serial data being used for generating parallel address infor­ mation, and address information received as parallel data being used for generating serial address informa­ tion.

Description: The present invention relates to an electronic circuit device for carrying out a diagnosis of status-holding circuits in the electronic circuit device by scanning. Usually, in the diagnosis of status-holding circuits in an electronic circuit device, a scanning is carried out to read data from status-holding circuits such as latch circuits, flip-flop circuits, and the like, or to write data into these status-holding circuits. In general, in the diagnosis of status-holding circuits in an electronic circuit device, a parallel scanning method in which a scan address is supplied in parallel to a plurality of address signal lines corresponding to the number of bits of a scan address, and a serial scanning method in which a scan address is supplied successively through a signal line to a serial-parallel converter and converted into a parallel scan address and then fed to a status-holding circuit, are used. However, in the parallel scanning method, when a large number of status-holding circuits must be scanned, a large number of address signal lines must be provided for supplying scan addresses; which increased number of address signal lines is disadvantageous. In the serial scanning method, a large amount of hardware is needed for the serial-parallel conversion of scan addresses, and such an increased amount of hardware is also disadvantageous. In particular, as will be explained subsequently in more detail with reference to Figure 3 of the accompanying drawings, JP-61-49698 (Kokoku) discloses an electronic device having a plurality of integrated circuits each comprising blocks of status-holding circuits, and a serial scan circuit comprising a shift register, for receiving serial address data and converting it to parallel address data, and an address decoder for supplying, on the basis of said parallel address data, status-holding circuit selection signals to select one of said status-holding circuits. An object of the present invention is to provide an improved electronic circuit device for diagnosing a status-holding circuit by scanning, in which a parallel scan system and a serial scan system are integrated in an electronic circuit device, and accordingly the design of the hardware of the electronic circuit device is optimized when considering whether a sufficient number of terminal pads is available and whether sufficient space is available for logic circuit elements. Another object of the present invention is to utilize the advantages of both a parallel scan system and a serial scan system to enable an increased number of elements to be included in an integrated circuit, in the cases where an appreciable number of terminal pads and where only a limited number of terminal pads are provided in the integrated circuit. Still another object of the present invention is to integrate a parallel scan system and a serial scan system to increase the freedom of design choice for an electronic circuit device in the form of an integrated circuit. Instead of the conventional design of a large scale integrated circuit device in which unification either to an exclusive use of serial scanning type integrated circuits or an exclusive use of parallel scanning type integrated circuits is carried out, the mixed use of serial scanning type and parallel scanning type integrated circuits according to the present invention makes it possible to mount as many circuit elements as possible on an integrated circuit to fully utilize the space of the integrated circuit under the condition of a given number of terminal pads, so that the limitation in design of the large scale integrated circuit device caused by the exclusive unification of the scanning type is eliminated and the total number of the integrated circuits for the large scale integrated circuit device is reduced. According to a first aspect of the present invention, there is provided an electronic device comprising respective first and second pluralities of integrated circuits, each of which integrated circuits includes a plurality of latch circuits, the said electronic device being connected, when in use, to receive a serially-supplied address signal, denoting the address of a selected one of said latch circuits in one of the said integrated circuits, a scan clock signal, and a shift/count signal, and further comprising: serial-parallel converter means, for converting the said serially-supplied address signal to a parallel address signal corresponding thereto, which serial-parallel converter means comprises a first shifter/counter connected to receive the said serially-supplied address signal, scan clock signal and shift/count signal and operable to generate the corresponding parallel address signal at a set of output terminals thereof by storing said serially-supplied address signal bit by bit, in response to the said scan clock signal, when the shift/count signal is ON, and, when all bits of that address signal have been stored, providing those bits in parallel at respective ones of the said output terminals; first decoder means connected, between the said first shifter/counter and the said second plurality of integrated circuits, for receiving a first part of said parallel address signal, which first part denotes the selected latch circuit, and supplying that first part to each of the said integrated circuits of the second plurality of integrated circuits; and second decoder means connected, between the said first shifter/counter and the said first and second pluralities of integrated circuits, for receiving a second part of said parallel address signal, which second part denotes that one of the said integrated circuits which contains the selected latch circuit, and operable to employ that second part to generate a chip enable signal, which is supplied to the said integrated circuits of the first and second pluralities for enabling that one of the integrated circuits which includes the said selected latch circuit; those integrated circuits of the said first plurality of integrated circuits also including respective serial scan circuits, each serial scan circuit comprising a second shifter/counter, connected to receive the said serially-supplied address signal, said scan clock signal, and said shift/count signal, and third decoder means, connected to respective output terminals of the said second shifter/counter, the said second shifter/counter being operable to generate a second parallel address signal corresponding to that serially-supplied address signal at the said output terminals thereof by storing the said serially-supplied address signal bit by bit, in response to the said scan clock signal, when the shift/count signal is ON, and, when all bits of that input address signal have been stored, to provide those bits in parallel at respective ones of the said output terminals, and said third decoder means being operable to employ the parallel address signal generated by the second shifter/counter to generate a first latch enable signal and to supply that first latch enable signal to the latch circuits of the integrated circuits concerned; and those integrated circuits of the said second plurality of integrated circuits also including respective parallel scan circuits, each connected to receive the said first part of the parallel address signal generated by the said first shifter/counter and comprising fourth decoder means operable to employ that first part to generate a second latch enable signal and to supply that second latch enable signal to the latch circuits of the integrated circuits concerned. According to a second aspect of the present invention, there is provided an electronic device comprising respective first and second pluralities of integrated circuits, each of which integrated circuits includes a plurality of latch circuits, the said electronic device being connected, when in use, to receive a parallel-supplied address signal, denoting the address of a selected one of said latch circuits in one of the said integrated circuits, a first scan clock signal, a parallel scan mode signal, and a latch setting signal, and further comprising: parallel-serial converter means, for converting the said parallel-supplied input address signal to a serial address signal corresponding thereto, which means comprise: an address register connected to receive the said parallel-supplied address signal and first scan clock signal and operable, when the scan clock signal is ON, to store the said parallel-supplied address signal and to provide at a set of output terminals thereof respective bits of said parallel-supplied address signal; a counter connected to receive the said first scan clock signal and parallel scan mode signal and operable, when the parallel scan mode signal is ON, to count, in response to the said scan clock signal, and to produce a count signal representing the value of the counter, a shift signal which is ON when the value of the counter is non-zero, and a counter clock signal representing a second scan clock signal; a first selector connected to receive a first part of said parallel-supplied address signal, which part denotes the selected latch circuit, and the said count signal and operable, in response to successive count signals, to select in turn each bit of said first part of said parallel-supplied input address signal, and thereby output those bits in series as the required serial address signal; and a second selector connected to receive the said latch setting signal, serial address signal and shift signal, and operable, in response to the said shift signal, to select and output the said serial address signal; the electronic device still further comprising: first decoder means connected, between the said address register and the said second plurality of integrated circuits, for receiving the said first part of said parallel-supplied address signal and supplying that first part to each of the said integrated circuits of the second plurality of integrated circuits; and second decoder means connected, between the said address register and the said first and second pluralities of integrated circuits, for receiving a second part of said parallel-supplied address signal, which second part denotes that one of the said integrated circuits which contains the selected latch circuit, and operable to employ that second part to generate a chip enable signal, which is supplied to the said integrated circuits of the first and second pluralities for enabling that one of the integrated circuits which includes the said selected latch circuit; those integrated circuits of the said first plurality also including respective serial scan circuits, each serial scan circuit comprising a second shifter/counter, connected to receive the said serial address signal, the said second scan clock signal, and the said shift signal, and third decoder means, connected to respective output terminals of the said second shifter/counter, the said second shifter/counter being operable to generate a parallel address signal corresponding to that serial address signal at the said output terminals thereof by storing the said serial address signal bit by bit, in response to the said second scan clock signal, when the shift signal is ON, and, when all bits of that address signal have been stored, to provide those bits in parallel at respective ones of the said output terminals, and said third decoder means being operable to employ the parallel address signal generated by the second shifter/counter to generate a first latch enable signal and to supply that first latch enable signal to the latch circuits of the integrated circuits concerned; and those integrated circuits of the said second plurality also including respective parallel scan circuits, each connected to receive the said first part of the parallel-supplied address signal output by the said address register and comprising fourth decoder means operable to employ that first part to generate a second latch enable signal and to supply that latch enable signal to the latch circuits of the integrated circuits concerned. Reference will now be made, by way of example, to the accompanying drawings, in which:- Fig. 1 illustrates in general the scanning for the diagnosis of status-holding circuits in electronic circuit devices in the form of an integrated circuit; Fig. 2 shows a prior art parallel scanning system; Fig. 3 shows a prior art serial scanning system; Fig. 4 shows an electronic circuit device able to diagnose a status-holding circuit by scanning according to an embodiment of the present invention; Fig. 5 shows the structure of the integrated circuits in the device of Fig. 4; Fig. 6 shows the structure of a serial scan circuit in an integrated circuit in the device of Fig. 4; Fig. 7 shows a detailed structure of a serial scan circuit as a portion of an integrated circuit in the device of Fig. 4; Fig. 8 illustrates a model expression of the device of Fig. 4; and Fig. 9 shows an electronic circuit device for diagnosing a status-holding circuit by scanning according to another embodiment of the present invention. Before describing preferred embodiments, prior art arrangements for a diagnosis by scanning are explained with reference to Fig. 1, Fig. 2, and Fig. 3. In general, the scanning for a diagnosis of status-holding circuits in electronic circuit devices in the form of integrated circuits can be as illustrated in Fig. 1. The parallel mode scanning instruction portion instructs a parallel scanning for a sequence of integrated circuits having a plurality of status-holding circuits such as latch circuits. The serial mode scanning instruction portion instructs a serial scanning for a sequence of integrated circuits having a plurality of status-holding circuits such as latch circuits. A prior art parallel scanning system is shown in Fig. 2. The system of Fig. 2 has an integrated circuit (A) which includes an address decoder, a selection circuit, and a plurality of status-holding circuits-1, -2, -3, -4, -5, -6, -7, and -8. Each of the status-holding circuits receives a set signal, a reset signal, and an output signal from the address decoder. The address decoder receives a selection signal through a plurality of status-holding circuit selection signal lines-1, -2, and -3. The number of status-holding circuit selection signal lines is equal to the number of bits which can express a scan address. By supplying the status-holding circuit selection signal lines with a scan address in parallel, the designation of one of the status-holding circuits to be scanned is designated. However, in the system of Fig. 2, the address decoder is provided and, for example, at least 8 scan address signal lines for scanning 256 status-holding circuits must be provided, This increases the number of terminal pads and thus is disadvantageous. A prior art serial scanning system, such as disclosed in JP-61-49698, is shown in Fig. 3. The system of Fig. 3 has an integrated circuit (B) which includes a shift register, an address decoder, an AND gate, a selection circuit, and a plurality of status-holding circuits-1, -2, -3, -4, -5, -6, -7, and -8. Each of the status-holding circuits receives a set signal, a reset signal, and an output signal from the address decoder. The shift register receives input signals, and the output of the shift register is supplied to the address decoder. The shift register has a serial/parallel conversion function. The AND gate receives a set signal, shift/count signal, a clock signal, and an output signal from the address decoder, and delivers a reset signal. In the system of Fig. 3, scan address signals are supplied in series through only one set of input lines (a), (b), and (c). The shift register holds the successively supplied scan address signals. The address decoder receives the output signal of the shift register and generates parallel scan address signals to designate the status-holding circuit to be scanned. However, in the system of Fig. 3, a number of shift registers must be provided exclusively for the scan address holding operation; the number of shift registers being equal to the number of bits which can express a scan address. Also, devices for the serial-parallel conversion of scan addresses must be provided. The increases in the hardware mainly due to shift registers is also disadvantageous, and the present invention is intended to eliminate these disadvantages of the prior art. An electronic circuit device for diagnosing a status-holding circuit by scanning according to an embodiment of the present invention is shown in Fig. 4. In the device of Fig. 4, a plurality of large scale integrated circuits 61, 63, 64, and 66 are provided, each including status-holding circuits such as latch circuits, and a selector 81. The device of Fig. 4 also includes a shifter/counter 21, decoders 311 and 312, an AND gate 41, and distribution circuits 511, 512, 513, and 514. The integrated circuits 66, and 64 are scanned in the serial scan method, the integrated circuits 63, and 61 scanned in the parallel scan method. The shifter/counter 21 receives a status holding circuit setting signal, a shift/count signal, and a scan clock signal. From the shifter/counter 21 output latch address signals S(21-6) S(21-5), S(21-4), and S(21-3) are supplied to the decoder 311, and output scan address signals S(21-2), S(21-1), and S(21-0) are supplied to the decoder 312. The AND gate 41 receives the status holding circuit setting signal, the shift/count signal, the scan clock signal, and, from the decoders 311 and 312 respectively, a signal S(311-0), and a signal S(312-0);the distribution circuit 511 receives the status holding circuit setting signal, the shift/count signal, and the scan clock signal; the distribution circuit 512 receives the output from the AND gate 41; the distribution circuit 513 receives a signal S(311-1); from the decoder 311; and the distribution circuit 514 receives a signal S(312-1) from the decoder 312. It should be noted that, in Fig. 4, respective signal lines S(311-1) and S(312-1) are illustrated as representatives of a plurality of signal lines S(311-1) and S(312-1). Each of the integrated circuits 66 and 64 receives a scan-in signal, the shift/count signal, and the scan clock signal from the distribution circuit 511, and each of the integrated circuits 63 and 61 receives a reset signal from the distribution circuit 512, a chip select signal from the distribution circuit 514, the scan-in signal from the distribution circuit 511, and a parallel scan address signal from the distribution circuit 513. The operation of the device of Fig. 4 will now be explained. The shifter/counter 21 operates as a shifter or a counter in accordance with the shift/count signal. When the shift/count signal is ON and the scan clock signal is ON, the shifter/counter 21 operates as a shifter to shift the content of the status hold circuit setting signal. When the shift/count signal is OFF and the scan clock signal is ON state, the shifter/counter 21 operates as a counter. A scan address of any one of the integrated circuit-6, the integrated circuit-4, the integrated circuit-3, and the integrated circuit-1 for which a scan-in or scan-out is desired, is set in outputs S(21-2), S(21-1), and S(21-0) of the shifter/counter 21, and a latch address of the latch circuits in the integrated circuit-6, -4, -3, and -1 is set in the outputs S(21-6), S(21-5), S(21-4), and S(21-3) of the shifter/counter 21. First, the operation where the target integrated circuit is the integrated circuit-i, and the target latch circuit is the first latch circuit in the integrated circuit-1 is explained as follows. The shift/count signal is made ON, and the integrated circuit scan address, i.e., chip-select, is set so that the signal S(21-0) is 0, the signal S(21-1) is 0, and the signal S(21-2) is 1; the latch address, i.e., parallel scan address, is set so that the signal S(21-3) is 0, the signal S(21-4) is 0, the signal S(21-5) is 0, and the signal S(21-6) is 1; and, the shift/count signal is made OFF. Under the above conditions, if a scan-in operation is to be carried out, the status hold circuit setting signal is made ON, and a rewriting of the latch in the target integrated circuit is carried out. If a scan-out operation is to be carried out, the status hold circuit setting signal is made OFF, the latch in the target integrated circuit is read via a scan-out signal through the selector 81, and the status hold circuit setting signal is distributed to all integrated circuits-6, -4, -3, and -1 as the scan-in signal. The signals S(21-2), S(21-1), and S(21-0) from the shifter/counter 21 are distributed to the integrated circuit-1 and the integrated circuit-3 as the chip-select signal via the signal S(312-1) of the decoder 312, to select a single target integrated circuit, the signals S(21-6), S(21-5), S(21-4), and S(21-3) from the shifter/counter 21 are distributed to the latches in the integrated circuit-1 and -3 as the parallel scan address via the signal S(311-1) of the decoder 311, and the signal S(311-0) of the decoder 311 and the signal S(312-0) of the decoder 312 are distributed to the integrated circuit-1 and -3 as the reset signal generation. Next, the operation where the target integrated circuit is the integrated circuit-6, and the target latch circuit is the eighth latch circuit in the integrated circuit-6 is explained as follows. The signals S(21-6), S(21-5), S(21-4), and S(21-3) from the shifter/counter 21 and the signals from the decoder 311 and the signal from the AND gate 41 exist also in the serial scan circuit 661 (Fig. 6) in the integrated circuit-6. Accordingly, the signals of the shifter/counter 21 in the serial scan circuit 661 corresponding to the signals S(21-6), S(21-5), S(21-4), and S(21-3) are set to "0", "0", "0", and "1", respectively, for the address of the target eighth latch circuit, and a scan-in or scan-out operation is carried out. In the scan-out operation, one data is selected in the selector 81 based on the signal S(312-2) from the decoder 312 and this one data is read. In this connection, the signals S(312-1) and S(312-2) can be unified as a single signal. The structure of the integrated circuits 66, 64, 63, and 61 in the device of Fig. 4 is shown in Fig. 5. Each of the integrated circuits 66 and 64 includes a serial scan circuit and a plurality of latch circuits, and each of the integrated circuits 63 and 61 includes a parallel scan circuit and a plurality of latch circuits. The structure of a serial scan circuit in an integrated circuit in the device of Fig. 4 is shown in Fig. 6. The serial scan circuit includes a shifter/counter 21A, a decoder 311A, an AND gate 41A, a distribution circuit 512A, and a distribution circuit 513A. The detailed structure of a serial scan circuit as a portion of an integrated circuit in the device of Fig. 4 is shown in Fig. 7. The serial scan circuit includes a shift/count register 661a, a chopper circuit 661b, a decoder 661c, a decoder 661d, gates 661e, 661f, 661g, and 661h, and terminal pads PAD-1, PAD-7, PAD-8, PAD-9, and PAD-6. The output signals from the decoder 661d, the gate 661f, and the gate 661g are supplied to the latch circuits LATCH CKT-1 through LATCH CKT-8 in the integrated circuits (A). The PAD-1 receives the chip select signal CHIP SELECT (inverted CHIP SELECT); the PAD-7 receives the scan clock signal SCAN CLOCK ; the PAD-8 receives the scan-in data SCAN-IN DATA ; the PAD-9 receives the shift mode signal SHIFT MODE; and the PAD-6 delivers the scan-out data SCAN-OUT DATA. The decoder 661c receives the block address signal from the shift/count register 661a, and the decoder 661d receives the latch address signal from the shift/count register 661a. It should be noted that, in Fig. 7, the output lines of the decoders 661c and 661d are illustrated per one block as representative of a plurality of the output lines for a plurality of blocks. Also, the output line of the gate 661h is illustrated per one block as representative of a plurality of the output lines for a plurality of blocks. The operation of the device of Fig. 7 will now be explained. When the shift mode signal SHIFT MODE is "1", the shift/count register 661a is operated as a shift register, and the scan-in data SCAN-IN DATA received by the PAD-8 is taken bit by bit into the shift/count register 661a based on the scan clock signal SCAN CLOCK . The block address is registered in the sections R-8, R-9, and R-10, and the latch address is registered in the sections R-11 through R-18. When the shift-mode signal SHIFT MODE is "0", the shift/count register 661a is operated as a counter, and the scan clock signal SCAN CLOCK is counted. Accordingly, the shift/count register 661a first takes the scan-in data, and then operates as a counter, so that the shift/count register 661a carries out successive increments from the scan-in data as the initial value. Where a sequence of numbers is assigned to latch addresses of the latches in each of the blocks, a shift-in of the address of a latch of a block is carried out followed by the increment of this address, and accordingly, the addresses of the following latches are successively generated without a shift-in of the addresses of the following latches from outside. This shows the advantage gained by the provision of the shift/count register 661a. When the chip select signal CHIP SELECT is supplied to the PAD-1, the present integrated circuit (A) is selected. When a shift-in of the block address and the latch address for a latch in the present integrated circuit (A) is carried out, this latch is selected so that an input of data into and a take-out of data from this latch can be carried out. The RESET signal is generated from the gate 661f. The BLOCK SCAN-IN signal is generated from the gate 661g. The output of the gate 661e which receives the signals through the PAD-7, PAD-8, and PAD-9 is supplied to the gates 661f and 661g. The PAD-8 also can be used for receiving the data to be input to the latch. In the device of Fig. 7, the number of pads of the integrated circuit (A) is greatly reduced, and since usually a great number of integrated circuits is used, the thus enabled reduction of the total number of pads is an advantageous affect. From the functional viewpoint, the device of Fig. 4 can be expressed as a model shown in Fig. 8. The model of Fig. 8 is constituted by a plurality of integrated circuits each having a parallel scan circuit and a plurality of status-holding circuits, a plurality of integrated circuits each having a serial scan circuit and a plurality of status-holding circuits, and a serial/parallel conversion circuit and scan distribution circuit which is connected with a serial scan interface. An electronic circuit device for diagnosing a status-holding circuit by scanning according to another embodiment of the present invention is shown in Fig. 9. In the device of Fig. 9, a plurality of large scale integrated circuits 61, 63, 64, and 66, each including status-holding circuits, such as latch circuits, and a selector 82, are provided, The device of Fig. 9 includes parallel-serial conversion means, comprising a parallel scan address register 22, a counter 23, a selector 24 and a selector 25, a decoder 321, a decoder 322, an AND gate 42, and distribution circuits 511, 512, 513, and 514. The integrated circuits 66 and 64 are scanned, in series, and the integrated circuits 63 and 61 are scanned in parallel. The parallel scan address register 22 receives the scan clock signal and a parallel scan address signal. Output signals S(22-6), S(22-5), S(22-4), and S(22-3) are supplied to the decoder 321, and output signals S(22-2), S(22-1), and S(22-0) are supplied to the decoder 322. The counter 23 receives the scan clock signal and a parallel scan mode signal and the selector 24 receives a signal from the counter 23 and the signals S(22-6), S(22-5), S(22-4), and S(22-3). The selector 25 receives the signal from the selector 24 and selects the status holding circuit and is controlled by a control signal from the counter 23. The AND gate 42 receives a signal from the selector 25, the control signal from the counter 23, a counter clock signal from the counter 23, an output signal from the decoder 321, and an output signal from the decoder 322; the distribution circuit 511 receives the signal from the selector 25, the control signal from the counter 23, and the counter clock signal from the counter 23; the distribution circuit 512 receives the output from the AND gate 42; the distribution circuit 513 receives a signal from the decoder 321; and, the distribution circuit 514 receives a signal from the decoder 322. The input signals of the integrated circuits 66, 64, 63, and 61 are similar to those in the device of Fig. 5. The operation of the device of Fig. 9 will now be explained. The parallel scan address having a bit width of, for example, 7 bits, is supplied to the parallel scan address register 22. When the scan clock signal is ON, the parallel scan address register 22 is set. Where a parallel-to-serial conversion is carried out, the counter 23 is operated by the scan clock signal and the parallel scan mode signal. The signals S(22-6), S(22-5), S(22-4), and S(22-3) from the parallel scan address register 22 supplied to the selector 24 are selected by the signal from the counter 23 through the selector 24, the selector 25, and the distribution circuit 511 and are transmitted serially as scan-in signals. The shift signal is made ON when the value of the counter 23 is not zero. The counter clock signal from the counter 23 is distributed as scan clock signals to the integrated circuits which are scanned in series. The counter 23 continues to count up until 4 bit signals S(22-6), S(22-5), S(22-4), and S(22-3) are transmitted, and returns to the value zero when this transmission is completed. Thus, a scan-in operation or a scan-out operation for a single latch circuit in the target integrated circuit which is scanned in series is carried out by the scan-in signal, the shift signal, and the scan clock signal as described above. As a further embodiment of the present invention, it is possible to combine the device of Fig. 4 and the device of Fig. 9.

Claims: An electronic device comprising respective first and second pluralities of integrated circuits (64, 66; 61, 63), each of which integrated circuits (64, 66; 61, 63) includes a plurality of latch circuits (LATCH 1, ..., LATCH 8), the said electronic device being connected, when in use, to receive a serially-supplied address signal, denoting the address of a selected one of said latch circuits (LATCH 1, ..., LATCH 8) in one of the said integrated circuits (64, 66; 61, 63), a scan clock signal, and a shift/count signal, and further comprising: serial-parallel converter means (21), for converting the said serially-supplied address signal to a parallel address signal corresponding thereto, which serial-parallel converter means (21) comprises a first shifter/counter connected to receive the said serially-supplied address signal, scan clock signal and shift/count signal and operable to generate the corresponding parallel address signal at a set of output terminals thereof by storing said serially-supplied address signal bit by bit, in response to the said scan clock signal, when the shift/count signal is ON, and, when all bits of that address signal have been stored, providing those bits in parallel at respective ones of the said output terminals; first decoder means (311) connected, between the said first shifter/counter (21) and the said second plurality of integrated circuits (61, 63), for receiving a first part of said parallel address signal, which first part denotes the selected latch circuit (LATCH 1, ..., LATCH 8), and supplying that first part to each of the said integrated Circuits (61, 63) of the second plurality of integrated circuits; and second decoder means (312) connected, between the said first shifter/counter (21) and the said first and second pluralities of integrated circuits (64, 66; 61, 63), for receiving a second part of said parallel address signal, which second part denotes that one of the said integrated circuits (64, 66; 61, 63) which contains the selected latch circuit (LATCH 1, ..., LATCH 8), and operable to employ that second part to generate a chip enable signal (S(CHIP SELECT)), which is supplied to the said integrated circuits (64, 66; 61, 63) of the first and second pluralities for enabling that one of the integrated circuits (64, 66; 61, 63) which includes the said selected latch circuit (LATCH 1, ..., LATCH 8); those integrated circuits (64, 66) of the said first plurality of integrated circuits including respective serial scan circuits (641, 661), each serial scan circuit comprising a second shifter/counter (661a), connected to receive the said serially-supplied address signal, said scan clock signal, and said shift/count signal, and third decoder means (661d), connected to respective output terminals of the said second shifter/counter (661a), the said second shifter/counter (661a) being operable to generate a second parallel address signal corresponding to that serially-supplied address signal at the said output terminals thereof by storing the said serially-supplied address signal bit by bit, in response to the said scan clock signal, when the shift/count signal is ON, and, when all bits of that input address signal have been stored, to provide those bits in parallel at respective ones of the said output terminals, and said third decoder means (661d) being operable to employ the parallel address signal generated by the second shifter/counter (661a) to generate a first latch enable signal and to supply that first latch enable signal to the latch circuits (LATCH 1, ..., LATCH 8) of the integrated circuits concerned (64, 66); and those integrated circuits (61, 63) of the said second plurality of integrated circuits also including respective parallel scan circuits (611, 631), each connected to receive the said first part of the parallel address signal generated by the said first shifter/counter (21) and comprising fourth decoder means operable to employ that first part to generate a second latch enable signal and to supply that second latch enable signal to the latch circuits (LATCH 1, ..., LATCH 8) of the integrated circuits concerned (61, 63). An electronic device comprising respective first and second pluralities of integrated circuits (64, 66; 61, 63), each of which integrated circuits (64, 66; 61, 63) includes a plurality of latch circuits (LATCH 1, LATCH 8), the said electronic device being connected, when in use, to receive a parallel-supplied address signal, denoting the address of a selected one of said latch circuits (LATCH 1, ..., LATCH 8) in one of the said integrated circuits (64, 66; 61, 63), a first scan clock signal, a parallel scan mode signal, and a latch setting signal, and further comprising: parallel-serial converter means (22 to 25), for converting the said parallel-supplied input address signal to a serial address signal corresponding thereto, which means comprise: an address register (22) connected to receive the said parallel-supplied address signal and first scan clock signal and operable, when the scan clock signal is ON, to store the said parallel-supplied address signal and to provide at a set of output terminals thereof respective bits of said parallel-supplied address signal; a counter (23) connected to receive the said first scan clock signal and parallel scan mode signal and operable, when the parallel scan mode signal is ON, to count, in response to the said scan clock signal, and to produce a count signal representing the value of the counter, a shift signal which is ON when the value of the counter (23) is non-zero, and a counter clock signal representing a second scan clock signal; a first selector (24) connected to receive a first part of said parallel-supplied address signal, which part denotes the selected latch circuit (LATCH 1, LATCH 8), and the said count signal and operable, in response to successive count signals, to select in turn each bit of said first part of said parallel-supplied input address signal, and thereby output those bits in series as the required serial address signal; and a second selector (25) connected to receive the said latch setting signal, serial address signal and shift signal, and operable, in response to the said shift signal, to select and output the said serial address signal; the electronic device still further comprising: first decoder means (321) connected, between the said address register (22) and the said second plurality of integrated circuits (61, 63), for receiving the said first part of said parallel-supplied address signal and supplying that first part to each of the said integrated circuits (61, 63) of the second plurality of integrated circuits; and second decoder means (322) connected, between the said address register (22) and the said first and second pluralities of integrated circuits (64, 66; 61, 63), for receiving a second part of said parallel-supplied address signal, which second part denotes that one of the said integrated circuits (64, 66; 61, 63) which contains the selected latch circuit (LATCH 1, ..., LATCH 8), and operable to employ that second part to generate a chip enable signal (S(CHIP SELECT)), which is supplied to the said integrated circuits (64, 66; 61, 63) of the first and second pluralities for enabling that one of the integrated circuits (64, 66; 61, 63) which includes the said selected latch circuit (LATCH 1, ..., LATCH 8); those integrated circuits (64, 66) of the said first plurality also including respective serial scan circuits (641, 661), each serial scan circuit comprising a second shifter/counter (661a), connected to receive the said serial address signal, the said second scan clock signal, and the said shift signal, and third decoder means (661d), connected to respective output terminals of the said second shifter/counter (661a), the said second shifter/counter (661a) being operable to generate a parallel address signal corresponding to that serial address signal at the said output terminals thereof by storing the said serial address signal bit by bit, in response to the said second scan clock signal, when the shift signal is ON, and, when all bits of that address signal have been stored, to provide those bits in parallel at respective ones of the said output terminals, and said third decoder means (661d) being operable to employ the parallel address signal generated by the second shifter/counter (661a) to generate a first latch enable signal and to supply that first latch enable signal to the latch circuits (LATCH 1, ..., LATCH 8) of the integrated circuits concerned (64, 66); and those integrated circuits (61, 63) of the said second plurality also including respective parallel scan circuits (611, 631), each connected to receive the said first part of the parallel-supplied address signal output by the said address register (22) and comprising fourth decoder means operable to employ that first part to generate a second latch enable signal and to supply that latch enable signal to the latch circuits (LATCH 1, ..., LATCH 8) of the integrated circuits concerned (61, 63). A device as claimed in claim 1 or 2, wherein each of the said serial scan circuits (641, 661) further comprises reset means (661e, 661f) for receiving the said scan clock signal, serial address signal and shift/count signal and generating in dependence thereon a latch reset signal for supply to said latch circuits (LATCH 1, ..., LATCH 8). A device as claimed in claim 3, wherein the said second shifter/counter (661a) is operable, when the shift/count signal is OFF, as a counter to count the scan count signal, and, on the basis of the said serial address signal, to generate addresses of succeeding latch circuits (LATCH 1, ..., LATCH 8).

Inventors: AOKI NAOZUMI, AZUMA ISAO, ISHIDA MIYUKI, AOKI, NAOZUMI, AZUMA, ISAO, ISHIDA, MIYUKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G06F11
IPC codes: G01R31