Semiconductor memory circuit having an improved restoring scheme

Abstract: A dynamic memory circuit which can operate at a high speed and with a reduced amount of current noise is disclosed. The memory circuit includes dynamic type memory cells which necessitate restoring operation for rewritting read out data thereto, a read circuit for performing a read out operation in response to an active level of an externally supplied control signal and a restore circuit for performing the restoring operation in response to change of the externally supplied control signal to its inactive level.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a semiconductor memory circuit and, more particularly to a dynamic type random access memory (DRAM) fabricated on a semiconductor substrate. Description of the Related Art: Dynamic memory circuits have been widely utilized as large capacity semiconductor memories. The dynamic memory circuit is typically constructed in such a manner that one-transistor type memory cells each composed of one transistor and a capacitor are arranged in a matrix form of rows and columns together with word lines and bit lines arranged in rows and columns, respectively. According to the conventional techniques, the number of memory cells connected to one bit line increases as the memory capacity increases. Consequently, a stray capacitance of each bit line increases to give rise to various problems. Firstly, the increased stray capacitance increases the time required to charge the bit lines to a power source potential Vcc or to discharge them to a ground potential when sense amplifiers are activated. If the signals on the bit lines are not amplified sufficiently, i.e., if the charging or discharging thereof are not done sufficiently, it becomes impossible to activate a column selection circuit which connects a selected bit line to a common data line because there is the possibility that, when the common data line is connected to the bit line, the electric charge on the common data line enters the bit line to destroy the stored information. As a result, the outputting of data from an output terminal has to be delayed in order to sufficiently charge or discharge the bit lines, and the operation speed of the memory becomes inferior. Secondary, the increased capacitance of the bit lines causes an increase of the charging and discharging currents, which gives rise to the problems of, for example, the floating of the grounding potential, dropping of the power source potential, occurrence of noise between the bit lines and an increase of the power consumption. A memory as defined in the precharacterising portion of Claim 1 is known from IEEE Journal of Solid-State Circuits, vol. SC-13, no. 5, pages 708-711, Oct. 1978, New York, USA, MEUSBURGER et al.: "An 8mm², 5V 16K Dynamic RAM using a New Memory Cell". SUMMARY OF THE INVENTION It is an object of the present invention to provide a dynamic memory which can operate at a high speed. It is another object of the present invention to provide a dynamic memory in which a peak current caused by restoring data to memory cells is decreased. The dynamic memory according to the present invention is defined in Claim 1. It comprises means for receiving an external control signal having a first level which sets the memory in an active state and a second level which sets the memory in a reset state and dynamic memory cells which require restoring read-out data thereto and is featured in that read-out of data from memory cell or cells is performed in the active state and restoring of data to the memory cell or cells is conducted in the reset state. According to this feature, a time required for the restoring of data to the memory cells is removed in the active state of the memory and therefore an effective period of the active state can be shortened and a current amount required in the active state is reduced. According to a preferred aspect of the present invention, there is provided a dynamic memory comprising means for receiving an external control signal, word lines, bit lines, dynamic memory cells coupled to the word lines and bit lines, sense amplifiers having sense nodes, transfer gates electrically inserted between the bit lines and the sense nodes of the sense amplifiers, means for selecting one of the word lines, and a control circuit responsive to the external signal for controlling the selecting means, the sense amplifiers and the transfer gates. The control circuit enables the selecting means first when the external control signal assumes an active level and then temporarily enabling the transfer gates under the active level of the external control signal. Then, after the transfer gates are disenabled, the sense amplifiers are enabled by the control circuit under the active level of the external control signal. After the external control signal assumes an inactive level, the selecting means and the sense amplifiers have been maintained active for a predetermined period and the transfer gates are again enabled within the above predetermined period to restore read-out data into memory cells. BRIEF DESCRIPTION OF THE DRAWINGS The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein. Fig. 1 is a schematic circuit diagram showing a dynamic memory in the prior art; Fig. 2 is a timing diagram showing an operation of the memory of Fig. 1; Fig. 3 is a schematic circuit diagram of a dynamic memory according to a first embodiment of the present invention; Fig. 4 is a timing diagram showing an operation of the memory of Fig. 3; Fig. 5 is a schematic block diagram of a timing signal generator employed in the memory of Fig. 3; Fig. 6 is a timing diagram showing waveforms of signals in the timing signal generator of Fig. 5; Fig. 7 is a schematic circuit diagram of a dynamic memory according to a second embodiment of the present invention; and Fig. 8 is a timing diagram showing an operation of the memory of Fig. 7: DETAILED DESCRIPTION OF THE INVENTION Prior Art: With reference to Figs. 1 and 2, a typical structure of the conventional dynamic memory will be explained. As shown in Fig. 1, the memory comprises a plurality of memory cells MC each having a memory cell transistor Q M and a capacitor C M connected between the transistor Q M and a fixed potential V f , word lines WL₁ - WL n arranged in rows, a plurality of bit line pairs D₁, D₁ - D N , D N arranged in columns, a CMOS type sense amplifiers SA₁ - SA N provided for the bit line pairs D₁, D₁ - D N , D N , respectively, a pair of common data lines I/O, I/O , a plurality of pairs of column selection transistors QY₁, QY₁ - QY N , QY N connected between the bit line pairs D₁, D₁ - D N , D N and the pair of common data lines I/O, I/O , respectively, a row decoder 20 having decoding units WD₁ - WD n for the word lines WL₁ - WL n , respectively and an output circuit 11. The row decoder 20 receives row address signals ADR and selects one of the word lines WL₁ - WL n in response to a control signal RA. Each of the sense amplifiers SA₁ - SA N includes P-channel MOS transistors QP₁, QP₂ and N-channel MOS transistors Q₁, Q₂, and is connected to a first activation line SAP which is coupled to a P-channel MOS transistor QP₃ controlled by a control signal SEP and a second activation line SAN connected to an N-channel MOS transistor Q₁₀ receiving a control signal SEN. The pairs of column selection transistors QY₁, QY₁ - QY N , QY N are controlled by column decoder signals YSW₁ - YSW N respectively in a known way. The typical operation waveforms of the semiconductor memory shown in Fig. 1 are illustrated in Fig. 2. Before an active operation has been started, the bit lines D₁, D₁ - D N , D N are precharged at, for example, an intermediate electric potential (1/2 Vcc) between the power source potential Vcc and the grounding potential Vcc. After a row address strobe signal RAS becomes active (low) level at a time point t₁, one of the word decoding units WD₁ - WD n , for example, WDi is selected by the row address signal ADR received from the outside. When the control signal RA, which is internally produced from RAS , rises at t₂, the word line WLi moves up, and N-MOS transistors in the memory cells MC are turned on, so that the electric potentials in the bit lines D₁ - D N vary by approximately 200 mV in accordance with the electric charge stored in the memory cell capacitors. In the meantime, the electric potentials in the bit lines D₁ - D N remain in the initial precharge level, i.e. 1/2 Vcc, and a signal representative of the difference between these electric potentials turns into input signals for the sense amplifiers SA₁ - SA N . When the control signals SEN rises with SEP falling at t₃, the sense amplifiers SA₁ - SA N are activated, and the small differential signals inputted into the sense amplifiers are amplified. Consequently, for example, the bit line D₁ drops to the ground potential, and the bit line D₁ rises to the power source potential Vcc. (in the case where a low level is stored in the memory cell MCi₁). In practice, when the word line WLi rises with the information read out on the bit line D₁, the information in the capacitor CM in the memory cell MCi₁ is destroyed by the exchange of electric charge between the capacitor CM thereof and the bit line D₁. Therefore, the sense amplifiers have the functions of amplifying the small signals on the bit lines D₁, D₁ as well as rewriting or restoring the information (called "refreshing") in the memory cell as compensation for the destraction of information. After a column address strobe signal CAS then becomes active (low) level, one of the column decoder signals YSW₁ - YSW N is selected at t₅. For example, YSW₁ is selected and rises, so that the data on the bit lines D₁, D₁ are transferred to the common data line I/O, I/O . The transferred data are amplified by the output circuit 11 and outputted to an output terminal Duct. When RAS becomes inactive (high level) at t₆, the memory enters into a reset period and a precharge signal  p becomes active so that precharge transistors QR₁ - QR N are rendered conducctive at t₇. According to the above conventional techniques, the number of memory cells connected to one bit line increases as the memory capacity increases. Consequently, a stray capacitance C₃₁ of the respective bit lines increases to give rise to various problems. Firstly, the increased stray capacitance C₃₁ increases the time required to charge the bit lines D₁ - D N , D₁ - D N to the power source potential Vcc or to discharge them to the ground potential when the sense amplifiers are activated as mentioned above. If the signals on the bit line pairs D₁, D₁ - D N , D N are not amplified sufficiently, i.e., if the charging and discharging thereof are not done sufficiently, it becomes impossible to activate YSWi and connect the bit lines to the common data lines I/O, I/O because there is the possibility that, when the common data lines are connected to the bit lines, the electric charge in the common data lines enters the bit lines to destroy the information. As a result, the outputting of data from the output terminal Dout is delayed, and the operation speed of the memory becomes inferior. Secondly, the increased capacitance C₃₁ causes an increase of the charging and discharging currents, which gives rise to the problems of, for example, the floating of the grounding potential, dropping of the power source potential, occurrence of noise between the bit lines and an increase of the power consumption. Embodiments of the Invention: With reference to Figs. 3 and 4, the dynamic memory according to one embodiment of the present invention will be explained. In Figs. 3 and 4, elements or portions corresponding to those in Figs. 1 and 2 are denoted by the same or similar references. The memory of the present invention is featured by following two points. The first point is that a plurality of pairs of transfer gate (N-channel) transistors QT₁, QT₁ - QT N , QT N are inserted between the pairs of bit lines D₁, D₁ -D N , D N and a plurality of pairs of sense nodes S₁, S₁ -S N , S N of the sense amplifiers SA₁ - SA N , respectively. The purpose of providing these transfer gates transistors is to separate the stray capacitance C₃₁ of the bit lines and that C₁₁ of sense nodes S₁ - S N from each other when the sense amplifiers are activated so as to increase the operating speed of the sense amplifiers, as explained later. The second point is that a restoring operation is conducted during a reset period when RAS is made inactive under control of the control signals RA′, SEP′, SEN′, TG and  p ′ generated by a timing signal generator 30. A column control circuit 40 generates the signal YSW₁ - YSW N in accordance with column address signals ADC under control of a column strobe signal CAS and RA′. The operation of the memory of Fig. 3 will be explained with reference to Fig. 4. Prior to a time point t₁, a reset period has been introduced and the pairs of bit lines D₁, D₁ - D N , D N and the sense nodes S₁, S₁ - S N , S N have been precharged to a precharge potential Vp (e.g. 1/2 Vcc). At the time point t₁, the row strobe signal RAS is changed to the active level so that the active period TA is introduced into the memory. In response to the activation of RAS , the row address signals ADR are taken in and applied to the row decoder 20. Then at a time point t₂, the control signal RA′ is activated so that one word line, for example, WLi is then selected by the row decoding unit WDi of the decoder 20 on the basis of row address signals ADR. When the electric potential of the selected word line WLi rises, the stored information in the memory cells MC connected to the selected word line WLi appear in the form of small signals in bit line pairs D₁, D₁ - D N , D N , respectively. Since the electric potential of a transfer gate control signal TG is high at this time, the signals on the bit line pairs D₁, D₁ - D N , D N are transferred to sense nodes S₁, S₁ - S N , S N , respectively. The control signal TG is then lowered at a time point t₃ to turn off the transfer gates QT₁, QT₁ - QT N , QT N , and the bit lines D₁, D₁ - D N , D N and the sense nodes S₁, S₁ - S N , S N are electrically separated from each other. Then, at a time point t₄, the control signal SEN′ is raised to lower the line SAN via the transistor Q₁₀ and thereafter the control signal SEP′ is lowered to raise the line SAP so that the sense amplifiers SA₁ - SA N are enabled. Since the sense nodes S₁, S₁ - S N , S N have a far small capacitance C₁₁ as compared to the bit line capacitance C₃₁, the small signal difference between the respective sense node pairs are amplified by the sense amplifiers SA₁ - SA N at a high speed. For example, one sense node S₁, reaches the power source potential Vcc, and the other node S₁ is discharged to the grounding potential. A column address strobe signal CAS falls at a time point t₅, and one pair of the column selection transistors, for example, QY₁ and QY₁ are selected on the basis of column address information given from the outside at a time point t₆ to be conductive by the active level of YSW₁. Consequently, the data at the sense nodes S₁', S₁' are transferred to the pair of common data lines I/O, I/O , and outputted to the point t₇, output terminal D out through an output circuit 11, at a time. At this point in time, the electric potential of the transfer gate control signal TG remains to be low, and the bit lines D₁, D₁ - D N , D N have not yet been amplified. Then, at a time point t₈, RAS and CAS are rendered inactive (high level) so that the reset period TB is introduced to the memory. As a result, the signal YSW₁ is changed to the inactive (low) level so that the pair of column selection transistors QY₁, QY₁ are made non-conductive so that the pair of sense nodes S₁, S₁ are isolated from the common data lines I/O, I/O . Then, at a time point t₉, the transfer gate control signal is raised to render the transfer gate transistors QT₁, QT₁ -QT N , QT N conductive. As a result, the pairs of bit lines D₁, D₁ - D N , D N are electrically connected to the sense amplifiers SA₁ - SA N via the pairs of sense nodes S₁, S₁ -S N , S N , respectively so that the signals on the respective bit lines are amplified by the sense amplifiers SA₁ - SA N and the amplified signals are restored into the memory cells coupled to the selected word line (WLi). Thereafter, the control signal RA′ is lowered to fall the potential of the selected word line WLi. At this time, the refreshing or restoring of the memory cells is completed. Also, the control signals SEN′ and SEP′ are made at their inactive level (low level and high level), respectively and thereafter, the precharge control signal  p ′ is changed to the active (high) level at a time point t₁₀ so that the transistors QR₁ - QR N are made conductive. As a result, the pairs of bit lines and the pairs of sense nodes are set to the precharge level of approximately 1/2 Vcc to complete the reset operation. According to the the present embodiment, the amplified state of the selected sense nodes S₁, S₁ are electrically connected under the isolation of the bit lines D₁, D₁ from the sense S₁, S₁ , the read-out signal can be outputted to the terminal D out before the restoring of the stored data at a high speed as indicated by an arrow A in Fig. 4. Moreover, the restoring of data to the memory cells is conducted during the reset period T B as illustrated by an arrow B after the active period T A . Therefore, the effective length of the active period T A is shortened as viewed from the outside. Thus, a high speed operation can be attained. An example of the timing signal generator 30 in Fig. 3 will be explained with reference to Figs. 5 and 6. As shown in Fig. 5, the timing signal generator 30 includes delay circuits D1 to D7, inverting delay circuits ID₁ and ID₂, inverter circuits IV₁ to IV₁₀, a dummy address buffer 51, NAND gates 52, 54, 55, 56 and 57, a NOR gate 53, and a series circuit of a P-channel MOS transistor QP₅ and N-channel MOS transistors Q51, Q52. An internal signal ₁ is generated from RAS through the delay circuit D₁ and the inverter IV₂ and has the substantially opposite phase to RAS . A control signal AE which is used to enable row address buffers (not shown in Fig. 3), is generated from the delay circuit D₃. The dummy row address buffer 51 receives one of row address signal A i and generates it true and complementary buffered address signals X i , X i when enabled by AE. The buffered address signals X i , X i are applied to the NOR gate 53, and inverter IV₃ and the delay circuit D₄ in cascade and, an internal signal ₂ is generated from the delay circuit D₄. The signal ₂ is generated when the states of X i and X i are established. The internal signals ₁ and ₂ are applied to the NAND gate 54 for generation of RA′ and TG, as illustrated. Internal waveforms of the respective signals are shown in Fig. 6. With reference to Figs. 7 and 8, the memory according to a second embodiment of the present invention will be explained. The present embodiment is featured in that the pairs of bit lines D₁, D₁ - D N , D N are physically divided into pairs of first bit line segments d 1a , d 1a -d Na , d Na and pairs of second bit line segments d 1b , d 1b -d Nb , d Nb , respectively and a plurality pairs of second transfer gate transistors Q' T1 , Q' T 1 - Q' TN , Q' TN are inserted between the pairs of first bit line segments d 1a , d 1a - d Na , d Na and the pairs of second bit line segments d 1b , d 1b - d Nb , d Nb , respectively. The second transfer gate transistors Q' T1 , Q' T1 - Q' TN , Q' TN are controlled by a second transfer gate control signal TG₂. The control signal TG₂ is such a signal that falls in potential in synchronism with the fall of TG and rises after the rise of TG, as illustrated in Fig. 8. The operation of this embodiment is substantially the same as the embodiment of Fig. 3 except following points. Namely, until a time point t a , the active period is introduced to the memory and data at the sense nodes S₁, S₁ are outputtes as D out . At the time point T a , RAS is made inactive so that the reset period is introduced to the memory. Then, the signal TG is raised to make the transfer gate transistors QT₁, QT₁ - QT N , QT N conductive so that the second bit line segments d 1b , d 1b - d Nb , d Nb are electrically connected to the sense amplifiers SA₁ - SA N , respectively. Thus, the levels of the second bit line segments and the memory cells connected thereto are refreshed as illustrated by an arrow C in Fig. 8. Then, at a time point t b , the control signal TG₂ is raised to make the second transfer gate transistors Q' T1 , Q' T1 -Q′ TN , Q′ TN conductive. As a result, the first bit line segements d 1b , d 1b - d Nb , d Nb are electrically connected to the sense amplifiers SA₁ - SA N via the second bit line segments d 1a , d 1a - d Na , d Na , respectively. Thus, the levels of the first bit line segments and the memory cells connected thereto are refreshed, as illustrated by an arrow D. Then, at a time t c , the signals SEN′ and SEP′ are made inactive and the precharge control signal  p ′ is rendered active. As a result, the refreshing operation is completed and the reset of the bit line segments and sense amplifiers are started. According to this embodiment, the bit lines are divided, and the electric charging and discharging are done in a time-divided manner during a refreshing operation, so that the occurrence of noise during such an operation can be prevented. According to the present invention described above, the information in the memory cell is transmitted to the sense nodes during an active period, and the sense nodes and bit lines are thereafter left separated from each other. While the rewriting of the information in the memory cell is done during a reset period. Thus the increasing of the speed of the operation of the sense amplifiers and the reduction of the access time can be achieved. Moreover, it is unnecessary to subject the bit lines having a large stray capacitance to the electric charging and discharging in one period, and the complete separation with respect to time can be effected. Accordingly, the minimization of noise occurring between the bit lines and the reduction of peak current can be attained effectively with ease. Since the charging and discharging of the bit lines having a comparatively large stray capacitance are carried out during a precharge period, it is unnecessary to determine the input level of an external signal, such as an address signal, and the occurrence of a decrease of the power source potential and the floating of the grounding potential, which cause an erroneous operation of the memory to occur, can be greatly reduced.

Claims: A semiconductor memory circuit comprising a plurality of dynamic type memory cells (MC) which necessitate restoring of read-out data for continuing storage of data, means for receiving an external control signal ( RAS ) having an active level (low level) and an inactive level (high level), means (20,SA1-SAN,11,QTI-QTN) for operatively reading data from a selected memory cell without feeding back an amplified signal of the stored data signal read from the selected memory cell to the selected memory cell in response to the active level of said external control signal, characterised by means (TG) for operatively restoring said data read from said selected memory cell into said selected memory cell in response to the inactive level of said external control signal. The semiconductor memory circuit according to claim 1, in which said memory cells are arranged in rows and columns with a pair of bit lines in each column and said reading means includes a sense amplifier (SA1-SAN) having a pair of sense nodes and a pair of transfer gates coupled between the pair of bit lines and the pair of sense nodes, characterized in that said restoring means includes a control circuit generating an internal control signal (TG) which renders the transfer gates conductive during an early part of a first period, non-conductive during the remaining part of the first period and then conductive during a second period.

Inventors: FUJII TAKEO C O NEC CORPORATIO, FUJII, TAKEO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G11C11
IPC codes: G11C11