Method of fabricating insulated gate semiconductor device

Abstract: A method of fabricating an insulating gate semiconductor device comprises the steps of forming insulated gates on an n⁻ layer (12) surface, forming p-well layers (13) in the n⁻ layer using the insulated gates as masks, forming doped films (26) through insulator films (25) located on the side walls of the insulated gates and diffusing the impurities from the doped films (26) into the p-well layers (13) to form n⁺-source layers (15).

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of fabricating a semiconductor device having an insulated gate (hereinafter referred to as an insulated gate semiconductor device) and more particularly to a method for fabricating such a device as is suitable to provide a high current density. The semiconductor device to which the present invention relates has such a structure as shown in Fig. 5. In this figure, 11 is an n + -type or p + -type semiconductor substrate; 12 is an n - -type layer formed on the semiconductor substrate 11 and having a higher resistivity than the semiconductor substrate 11; 13 are a plurality of p + -type wells which extend into the n - -type layer 12 from the surface thereof on the side opposite to the side adjacent to the semiconductor substrate 11; 15 are n + -type sources which extend into the p + -well 13 from the surface thereof; 31 are gate electrodes each formed on the exposed portions of the n - -type layer 12 and p-type well 13 adjacent thereto through a gate oxide film 21; 22 are insulating films each formed so as to cover the gate electrode 31 and a part of the n + -type source layer 15 adjacent thereto; 41 is a drain electrode kept in ohmic contact with the surface of the semiconductor substrate 11 on the side opposite to the side adjacent to the n - -type layer 12; and 42 is a source electrode kept in ohmic contact with the exposed portions of the n + -source layers 15 and of the p-type wells 13 between the n + -source layers and formed so as to extend over the insulating films 22. The semiconductor device as shown is an unipolar device commonly called "MOSFET" in the case where the semiconductor substrate 11 is of n + -type. In operation, if, with the source electrode 42 applied with e.g. OV and the drain electrode 41 applied with a positive potential, a positive potential is applied to the gate electrode 31, an n-type inverted layer is produced in the p-type well layer 13 under the gate electrode 31 and electrons ⊖ flow to the drain electrode 41 through the source electrode 42, the n + -type source layer 15, the n-type inverted layer, the n - -type layer 12 and the n + -type substrate. Thus, current flows from the drain electrode 41 to the source electrode 42, whereby the semiconductor device turns on. Then, if the potential which has been applied to the gate electrode 31 is removed, the p-type inverted layer disappears. Thus, the path of electrons ⊖ is cut off whereby the semiconductor device turns off. On the other hand, in the case where the semiconductor substrate 11 is of p + -type, the semiconductor device as shown in a bi-polar device called a conductivity-modulated MOSFET and IGBT (insulated gate bipolar transistor). In operation, potentials are applied to the source electrode 42 and the drain electrode 41 in the same manner as the case where the semiconductor substrate 11 is p + -type. Now, if a positive potential is applied to the gate electrode 31, electrons flow in the n - -type layer 12. Then, the electrons accelerate the injection of a large amount of holes from the p + -type substrate, thereby producing a large amount of excess carriers in the n - -type layer 12. Thus, the n - -type layer 12 which has been of a higher resistivity exhibits a conductivity of lower resistivity. This is the reason why that semiconductor device is called "conductivity modulated MOSFET", in which the electrons serve as a base current and a pnp transistor consisting of the p + -type substrate 11, the n - -type layer 12 and the p-type well layer 13 is operated. The injected holes flow into the source electrode 42 through the p-type well layer 13 unter the n + -type source layer 15. In order to turn off the conductivity modulated MOSFET, the potential applied to the gate electrode 31 is removed as in the case of the unipolar MOSFET. Then, the path of electrons ⊖ is cut off so that the base current of the pnp transistor is not supplied. Thus, the holes are not injected whereby the current does not flow. The semiconductor device having such a structure as described above has been proposed in USP 4,364,073, USP 4,587,713 and Solid State Electronics 28 No. 3 pp 389 to 297 (1985) "Temperature Behavior of Insulated Gate Transistor Characteristics" by B.J. Baliga, etc. A process of fabricating such a semiconductor device as mentioned above will be explained with reference to Figs. 6A to 6F. First, a n + -type or p + -type semiconductor substrate 11 is prepared and an n - -type 12 is formed on one surface thereof. A stack (insulated gate) of a gate oxide film 21 and a gate electrode 31 are selectively formed on the surface of the n - -type layer 12 on the side opposite to the side adjacent to the semiconductor substrate 11 (Fig. 6A). Using this stack as a mask, boron (B) is ion-implanted in the surface of the n - -type layer 12 where no mask is located thereon, and the substrate is heat-treated to from a p-type well layer 13 (Fig. 6B). A resist film 29 is formed on the p-type well layer 13 surface at the selected location thereof. Using, as a mask, this resist film and the stack of the gate oxide film 21 and the gate electrode 31, arsenic (As) or phosphorus (P) is ion-implanted in the p-type well layer 13 surface at the location where the mask is not present, (Fig. 6C). After the ion-implantation, the resist film 29 is removed and the substrate is heat-treated to form n + -type source layers 15 (Fig. 6D). An insulating film 22 is formed on the stack consisting of the gate oxide film 21 and the gate electrode 31 and on the exposed portions of the p-type well layer 13 and the n + -type source layer 15 (Fig. 6E). A portion of the insulating film 22 located on portions of the n + -type source layers and a portion of the p-type well layer 13 exposed between the n + -layer source layers 15 is selectively removed and a source electrode 42 is formed on the remaining insulating film 22 and on the portions of the n + -type source layers 15 and the p-type well layer 13 exposed by removing the portion of the insulating film 22 (Fig. 6F). The insulating gate semiconductor device fabricated by the process as mentioned above has a disadvantage that it can not provide a high current density. The current density of the semiconductor device having insulated gate as shown in Fig. 5 can be enhanced by providing a larger percentage area occupied by the gate region B in a device unit and a smaller percentage area occupied by the remaining region A. However, in the case where the semiconductor device is fabricated by the process as shown in Figs. 6A to 6F, the area of the region A can not be decreased for the following reason. Namely, if an alignment accuracy of photolithography is 3 µm, size A 1 of the insulating film 22 required to insulate the gate electrode 31 from the source electrode 42, size A 2 required to surely bring the source electrode 42 and the n + -type layers 15 into contact with each other, and size A 3 required to separate the n + -type layers 15 from each other and bring the p-type layer 13 and the source electrode 42 into contact with each other, which depends on the processing accuracy of the resist film 29, are required to be at least 3 µm. Since these sizes must take some allowance considering the safety rates, the entire width (2A 1 + 2A 2 + A 3 ) of the region A reaches 20 to 30 µm, which will occupy 50 % of the device unit. Thus, the percentage of the gate region B can not be further increased, which makes it impossible to enhance the current density. In the case of a conductivity modulated MOSFET using a p + -type substrate, if the width (A 1 + A 2 ) of the n + -type source layer 15 is too large, injected holes ⊕ produce a voltage drop in the p-type well layer 13 due to the lateral resistance R in the p-type well layer 13 under the n + -type layer 15, thereby forward biasing the n + -type source layer 15 and the p-type well layer 13. Thus, an npn transistor consisting of the n + -type source layer 15, the p-type well layer 13 and the n - -type layer 12 is started to operate, thus injecting electrons into the p-type well layer 13 from the n + -type source layer 15. Accordingly, the semiconductor device operates as a pnpn thyristor which includes the pnp transistor consisting of the layers 11, 12 and 13 as mentioned above, and is eventually latched up. Once latched up, the semiconductor device can not be turned off even when the potential applied to the gate electrode 31 is removed, which makes it impossible to control the semiconductor device through the gate. Such a problem also occurs in the unipolar MOSFET when it shifts from the turn-on state thereof to the turn-off state thereof. In order to surely operate the insulated gate semiconductor device, the parasitic transistor effect as mentioned above is desired to be made as small as possible. EP-A-0 179 407 discloses a method of fabricating a DMOS device, comprising the steps of forming selectively two-layer structures on a semiconductor layer of one conductivity type, the two-layer structure consisting of an insulating layer and a gate electrode; forming well layers of the other conductivity type using the two-layer structures as masks; covering a central part of the well layer by an insulating layer, and then forming a polysilicon layer doped with impurities on totally an exposed portion of the well layers, the two-layer structures and the insulating layer; diffusing the impurities of one conductivity type from the polysilicon layer to form source layers in the well layers; covering the two-layer structures by SiO 2 films and forming source electrodes. EP-A-0 083 785 discloses a method of fabricating FET structures, comprising the steps of forming selectively two-layer structures on a P-type substrate, the structure consisting of an N + type polysilicon layer and a SiO 2 layer; forming a SiO 2 film doped with impurities of N-type on side walls of the two-layer structures; diffusing the impurities from the polysilicon layer and the SiO 2 into the substrate to form source layers and drain layers; forming insulating gates between the two-layer structures. An object of the present invention is to provide a method for fabricating an insulated gate semiconductor device having a high current density. Another object of the present invention is to provide a method for fabricating an insulated gate semiconductor device having a high current density with high accuracy. Still another object of the present invention is to provide a method for fabricating an insulated gate semiconductor device with a larger percentage of the area occupied by a gate region in a device unit. A further object of the present invention is to provide an insulated gate semiconductor device with reduced parasitic bipolar transistor effect. Said objects are achieved, according to the present invention, by a method of fabricating a semiconductor device as claimed in claim 1. A further advantageous feature of the invention is claimed in claim 2. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 4 are a process flow diagram showing part of an embodiment of an insulated gate semiconductor device in accordance with the present invention; Fig. 5 is a schematic sectional view of an insulated gate semiconductor device according to the prior art; and Figs. 6A to 6F are a process flow diagram for explaining the insulated gate semiconductor device shown in Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will be explained with reference to the drawings which show an embodiment thereof. Figs. 1 to 4 show a typical embodiment of the present invention, which comprises the following steps (1) Stacks each consisting of three layers of a gate oxide film 21, a gate electrode 31 and an insulating film 22 is selectively formed on the surface of an n - -type layer 12. Using the stacks as a mask, p-type impurities, e.g. boron are ion-implanted in the exposed surface of the n - -type layer 12 (Fig. 1). SiO 2 is used as the gate oxide film 21; impurity-doped poly-silicon is used as the gate electrode 31; and SiO 2 is used as the insulating film 22. The desired method of selectively forming the stack is to form the three-layer structure on the entire surface of the n - -type layer 12 and selectively etch it. Incidentally, as in the prior art, the n - -type layer 12 is formed on a n + or p + -type semiconductor substrate 11. (2) The n - -type layer is heat-treated to activate and diffuse the ion-implanted boron, thereby forming p-type well layers 13 (Fig. 2). (3) Films 26 containing impurities (doped films) are then formed, through insulating films 25 not containing impurities (undoped insulating films), on the stacks each consisting of three layers of the gate oxide film 21, the gate electrode 31 and the insulating film 22. Fig. 3 shows the step of forming the insulating film 25 and the film 26 on each of the side walls of the stack. The insulating film 25 and the film 26 can be formed on the side wall of the stack by forming the undoped insulating film 25 on the entire surface of the stacks and the exposed portions of the p-type well layers 13, anisotropic-dry-etching it, further forming the doped film 26 on the entire surface of the resultant structure and anisotropic-dry-etching it. SiO 2 can be used as the undoped insulating film 25 and phosphosilicate glass or doped poly-silicon can be used as the doped film 26. (4) Fig. 4 shows the step of forming the n + -type source layers 15 by diffusing the impurities in the films 26 into the p-type well layers 13 through heat treatment. The heat treatment is performed at the temperature of approximately 1000°C for the period which is decided in accordance with the selected depth of the n + -type source layers 15. Thereafter, a source electrode is formed on the stacks, the remaining films 26 and the exposed surface of the n + -type source layers 15 and the p-type well layers 13. In this embodiment, the undoped insulating film 25 is located between the gate electrode 31 and the source electrode so that both electrodes can be surely insulated from each other. Also, the doped film 26 which serves as a diffusion source 15 for the n + -type source layer 15 is not required to be electrically insulative so that the conductor such as doped poly-silicon can be used, which assures that the n + -type source layers 15 and the source electrode are kept in contact with each other. Although an n-channel MOSFET has been adoped in the above explanation relative to the embodiment of the present invention, the present invention can also provide the same effects when it is a p-channel MOSFET. As explained above, in accordance with the present invention, (1) an insulated gate semiconductor device which operates at high current densities can be fabricated at high accuracy, and (2) an insulated gate semiconductor device less influenced from the parasitic bipolar transistor effect can be obtained.

Claims: A method of fabricating a vertical insulated gate transistor including: a semiconductor layer of a first conductivity type; well regions (13) of a second conductivity type, opposite to said first conductivity type, formed apart from one another and said well regions having exposed surfaces at a surface of said semiconductor layer (12); source regions (15) of said first conductivity type two thereof formed in each of said well regions and said source regions having exposed surfaces at said surface of said semiconductor layer; insulated gate stacks formed from three layers, a gate oxide layer (21) on said surface of said semiconductor layer, a gate electrode layer (31) on said gate oxide layer, and an insulating layer (22) on said gate electrode layer (31); and a source electrode (42) contacting portions of said exposed surfaces of said well regions (13) and said source regions (15) and extending over said insulated gate stacks, comprising the steps of: forming said insulated gate stacks on said surface of said semiconductor layer (12); forming said well regions (13) by introducing impurities of said second conductivity type into said semiconductor layer (12) using said insulated gate stacks as masks; forming an undoped insulator film (25) on the entire surface on the resultant structure (13) and anisotropic-dry-etching said undoped insulator film (25), so that only side wall portions thereof are left on the side walls of said insulated gate stacks and the remaining portions thereof are completely removed, to thereby form undoped insulator film side wall portions (25) on said side walls of said insulated gate stacks, in contact with the gate oxide layer (21), the gate electrode layer (31), the insulating layer (22) and a part of the exposed portions of said well regions; forming a doped film (26) doped with impurities of said first conductivity type on the entire surface of the resultant structure, and anisotropic-dry-etching said doped film (26), so that only side wall portions thereof are left on said undoped insulator side wall portions and the remaining portions thereof are completely removed, to thereby form doped film side wall portions (26) in contact with said insulator film side wall portions (25) and a part of the exposed portions of said well regions; diffusing said impurities from said doped film side wall portions (26) into said well regions (13) to form said source regions (15) and forming said source electrode (42) kept in ohmic contact with the exposed portions of two corresponding source regions (15) in one of said well regions and said well regions (13), extending over two corresponding insulated gate stacks, and insulated from said gate electrode stacks (31) by said insulator film side wall portions (25). A method according to claim 1, wherein said doped film (26) is formed of polycrystalline silicon doped with said impurities of said first conductivity type.

Inventors: MORI MUTSUHIRO, NAKANO YASUNORI, TANAKA TOMOYUKI, YASUDA YASUMICHI, MORI, MUTSUHIRO, NAKANO, YASUNORI, TANAKA, TOMOYUKI, YASUDA, YASUMICHI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1988
Main classification: H01L21
IPC codes: H01L29, H01L21