Data input circuit having latch circuit

Abstract: A data input circuit (100) provided in a data processing equipment is disclosed. The input circuit includes a timing circuit (10) generating a latch pulse (LE) in asynchronism with a read request (RE) signal generated by a CPU and a latch circuit (6) latching input data in response to the latch pulse. The data latched in the latch circuit is transferred to a data bus (8) in response to the read request signal (RE). The input circuit further includes means responsive to an access by the CPU for delaying the generation of the latch pulse such that the latch pulse is generated after the CPU stops to generate the read request signal. The latch circuit is thereby prevented from latching the input data while the read request signal is generated.

Description: BACKGROUND OF THE INVENTION The present invention relates to a data input circuit provided in a data processing equipment and more particularly to such an input circuit having a latch circuit latching input data in asynchronism with a read request signal generated by a central processing unit called hereinafter "CPU"). A data input circuit is interposed between one or more input terminals and a CPU. It receives the input data at the input terminals, latches the input data and, when CPU generates a read request signal, transfers the latched input data to the CPU in response thereto. Since the CPU generates the read request signal in accordance with programs to be executed, the read request signal is in asynchronism with the input data latching timing. For this reason, there occurs a case where the input circuit latches new input data while the CPU generates the read request signal. In this case, data to be supplied to the CPU is changed during the data read operation of the CPU. An error operation thereby occurs. JP-A-57114939 discloses a input circuit according to the pre-characterizing portion of claim 1. In this input circuit the period of the latch pulse, which commands the latch/buffer circuit to latch the data supplied thereto, is prolonged over the read request signal. Therefore, if this technical concept is applied to an input circuit that has input means inserted between the input terminal and the latch circuit sampling the input signal during the first logic level of a control signal and supplying the sampled signal to the latch circuit during the second logic level of the control signal, any operating cycle period - consisting of a signal sampling period, a signal supplying period and a signal latching period - is prolonged because the signal latching period is always prolonged, too. It is an object of the present invention to provide a data input circuit which overcomes the above mentioned drawbacks. It is an other object of the invention to provide a data input circuit having a latch circuit, which is free from simultaneous occurrence of an input data latching operation and a data output operation. Still another object of the present invention is to provide an input circuit which does not change data to be supplied to a CPU during the data read operation of the CPU. These objects are achieved by an input circuit according to claim 1. The dependent claims are related to further advantages aspects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with accompanying drawings, in which Fig. 1 is a block diagram representative of an embodiment of the present invention; Fig. 2 is a circuit diagram representative of the example of a timing control circuit shown in Fig. 1; Figs. 3A and 3B are timing charts denoting an operation of circuits shown in Figs. 1 and 2. Fig. 4 is a circuit diagram representative of another example of a timing control circuit in Fig. 1; Figs. 5A and 5B are timing charts denoting an operation of circuits shown in Figs. 1 and 4; and Fig. 6 is a block diagram representative of a data processing equipment employing an input circuit of the present invention. DETAILED DESCRIPTION OF THE INVENTION Referring to Fig. 1, an input circuit according to an embodiment of the present invention is shown by a reference numeral 100 and includes eight input terminals 1-0 to 1-7 supplied with input data consisting of eight bits B₀ to B₇. Each bit of the input data has data "1" or data "0", but the potential thereof takes an intermediate level between logic "1" and logic "0" of a data signal treated by a CPU (not shown in Fig. 1). For this reason, the input data cannot be transferred to a data bus 8 as they are. In order to solve this problem, the input circuit 100 has a level convention circuit for converting the intermediate level of each bit of the input data into a logic level required by the CPU. The level convertion circuit includes a resistor ladder circuit 2, a multiplexer 3, a sample-hold (S/H) circuit 4, a comparison circuit 5, and a mode resistor 11. The resistor ladder circuit 2 has a plurality of resistors R connected in series between a reference voltage point V R and a ground point and produces a plurality of reference voltages having levels different from one another, which are in turn supplied to the multiplexer 3. The multiplexer selects one of the reference voltages in response to data stored in the mode registor 11 and supplies the selected reference voltage to an inverting input terminal of each of eight comparators 5-0 to 5-7 in the comparison circuit 5. The data to be stored in the register 11 is set by the CPU via a data bus 8. The sample-hold circuit 4 has a switch and a storage capacitor (both not shown) with respect to each input terminal 1, as well-known in the art, and is controlled by an operating control signal OC. When the signal OC takes a low level, the switch is turned ON to charge the storage capacitor to a level corresponding to the data of each bit. Thus, the level of each bit of the input data is sampled by the circuit 4. When the signal OC takes a high level, the switch is turned OFF to disconnect the storage capacitor from the associated input terminal 1. The input data level is thereby held by the storage capacitor and then supplied to a non-inverting input terminal of the associated one of the comparators 5-0 to 5-7. The multiplexer 3 selects such a reference voltage that takes an intermediate level between data "1" and data "0" of the input data. Thus, each bit of the input data is converted into a level of logic "1" or logic "0" required by the CPU. The data derived from the comparison circuit 5 is supplied to a set of input nodes of a latch circuit 5 which latches the supplied data in response to a latch-enable signal LE. The signal LE is produced just before the operating control signal OC changes to the low level, i.e. just before the data sampling operating starts. The operating control signal OC and the latch-enable signal LE are generated by a timing control circuit 10. Since the input circuit 100 has the comparison circuit 5, it is called a comparator port in a data processing equipment, as shown in Fig. 6. The data processing equipment shown in this figure includes a CPU 110 executing instructions, a clock generator generating a system clock SCL, a program memory (ROM) 130 storing instructions to be executed, a data memory (RAM) 140 storing various data, a plurality of input/output ports 150, and peripheral units 160 having an interrupt control unit, a timer unit, a counter unit, a serial data input/output unit, etc. When an instruction to be executed has information representive of reading of input data supplied to the comparator port 100 (i.e., the input circuit shown in Fig. 1), the CPU 110 generates address information to select the comparator port 100, followed by the generation of a read request signal RE. The comparator port 100 is thereby selected and a bus buffer circuit 7 therein (see Fig. 1) is activated to couple a set of output nodes of the latch circuit 6 to the data bus 8. The data latched in the latch circuit 6 is thus transferred to the data bus 8. The operation speed of the sample-hold circuit 4 and the comparison circuit 5 is relatively slow. Therefore, if the timing control circuit 10 generates the operation control signal OC and the latch-enable signal LE in response to the selection of the input circuit 100, a considerably long time is required to supply the input data to the CPU. In order to overcome the problem, the timing circuit 10 cyclically generates the signals OC and LE in response to a clock signal CLK supplied from the clock generator 120 (Fig. 6). As a result, the input circuit 100 can transfer the input data to the data bus 8 immediately after the CPU 110 selects the input circuit 100. Since the timing circuit 10 cyclically generates the latch-enable signal LE, the latch circuit 6 latches the data from the comparison circuit 5 (i.e., the input data) in asynchronism with the read request signal RE from the CPU 110. Referring to Fig. 2, the timing control circuit 10 includes a divider 20, an output of which is used as the operating control signal OC. The clock signal CLK is supplied via an OR gate 23 to the divider as a division clock signal DCL. Therefore, the level of the operating control signal OC is changed every time when a predetermined number of clock pulses are supplied to the divider 20. The clock signal CLK is further supplied via an inverter 22 to one input terminal of an AND gate 21, the other input terminal of which is supplied with a carry signal from the divider 20, this carry signal being utilized to change the level of the operating control signal OC. The ouput of the AND gate is used as the latch-enable signal LE. Accordingly, the latch-enable signal LE is generated just before the operating control signal OC changes from the high level to the low level, as shown in Fig. 3A. As described above, the high level period of the operating control signal OC is used as a "comparing cycle" and the low level period thereof is used as a "sampling cycle". The output of the comparison circuit 5 is thus latched in the latch circuit 6 just before the sampling cycle starts. Since the generation of the latch-enable signal LE is asynchronous with the generation of the read request signal RE, the latch-enable signal happens to be generated while the read request signal RE is generated. In this case, the data on the data bus 8 is changed to cause a miss-operation of the CPU 110. In order to overcome this drawback, the timing control circuit 10 further includes an address decoder 24 and a flip-flop (F/F) circuit 25 in accordance with the present invention. The decoder 24 is constituted of an AND gate 24-1 supplied with address information. The output of the decoder 24 is supplied to a data input terminal D of the F/F circuit 25 having a clock terminal CK supplied with the clock signal CLK and an output terminal Q connected to a second input terminal of the OR gate 23. When the CPU 110 outputs the address information on the address bus 9 to access the input circuit 100, the decoder 24 decodes the address information and produces a high level output. The F/F circuit 25 produces a high level outut Q. As a result, the output of the OR gate 23 is fixed to the high level, so that the clock signal CLK is prevented from being supplied to the divider 20, as shown in Fig. 3B. The division operation of the divider 20 stops, thereby the operating control signal OC maintaining a high level, as shown in Fig. 3B. The CPU 110 generates the read request signal RE after the generation of the address information. The buffer circuit 7 thereby couples the latch circuit 6 to the data bus 8. Thus, the data in the latch circuit 6 is transferred to the data bus 8. When the CPU 110 catches the data on the data bus 8, it changes the read request signal RE to an inactive level (a low level) and stops to generate the address information. The outputs of the decoder 24 and the F/F circuit 25 are thereby changed to the low level to allow the divider 20 to receive the clock signal CLK. Thus, the divider 20 starts to divide the clock signal CLK, so that the operating control signal OC is changed to the low level and the latch-enable signal LE is generated, as shown in Fig. 3B. The latch circuit 6 latches new input data. Thus, although latch-enable signal LE is generated in asynchronism with the read request signal RE, the signal LE is prevented being generated while the read request signal RE is generated. The timing control circuit 10 can use a divider provided in the pheripheral units 160 (Fig. 6) in place of the divider 20 shown in Fig. 2. A circuit construction for this purpose is shown in Fig. 4 as another embodiment of the present invention. In Fig. 4, a divider 40 is provided in the peripheral units 160, and therefore the clock signal CLK is directly supplied to the divider 40 and one or more outputs are are derived from a predetermined stage of the divider as shown by dotted lines. The output of the divider 40 is supplied to a first input of an OR gate 41, an output of which is used as the operating control signal OC. A second input of the OR gate 41 is supplied with a Q output of an flip-flop (F/F) circuit 27 having a clock terminal CK supplied with the clock signal CLK and a data input terminal D supplied with an output of an AND 46. The first input of the AND gate 46 is supplied with an output of a decoder 48 including an AND gate 48-1 supplied with address information, and the second input thereof is supplied with a carry signal CS from the divider 40 via an OR gate 45, this carry signal CS being used to change the output of the divider 40 from the high level to the low level. The output of the F/F circuit 47 is further supplied to the OR gate, the output of which is supplied to an AND gate 44. The AND gate 44 further receives the clock signal CLK and the output of the decoder 48 via inverters 42 and 43, respectively. The output of the AND gate 44 is used as the latch-enable signal LE. When the CPU 110 does not access the input circuit (comparator port) 100, both of the outputs of the decoder 48 and the F/F circuit 47 take the low level, so that the operating control signal OC changes its level in accordance with a division ratio of the divider 40 and a latch-eable signal LE is generated just before the signal OC changes the high level to the low level, as shown in Fig. 5A. When the CPU 110 generates address information to the address bus 9 to access the input circuit 100, the decoder 48 produces a high level output. At this time, since the clock signal CL is directly supplied to the divider 40, the carry signal CS for changing the output of the divider 40 from the high level to the low level may be derived from the divider 40, as shown in Fig. 5B. However, the high level output of the decoder 48 is inverted by the inverter 43, so that the AND gate 44 receives the low level at one input thereof. Accordingly, the output of AND gate 44 is held to the low level, even if the carry signal CS is derived from the divider 40. No latch-enable signal LE is thereby generated, as shown in Fig. 5B. The carry signal CS derived from the divider 40 is supplied via the OR gate 45 to the AND gate 46, so that the F/F 47 produces a high level output, as shown in Fig. 5B. This high level output is supplied to the OR gate 41. Therefore, the operating control signal OC is maintained to the high level, even when the output of the divider 40 changes to the low level, as shown in Fig. 5B. The CPU also generates the read request signal RE, so that the data latched in the latch circuit 6 is transferred to the data bus 8. Since the high level output of the F/F circuit 47 is fed back to the OR gate 45, the data input D of the F/F circuit 47 receives the high level even when the carry signal CS disappears. When the CPU catches the data on the data bus 8, it changes the read request signal RE to an inactive level changes the read request signal RE to an inactive level and the address information on the address bus 9 to other information. The decoder 48 produces the low level output and the AND gate receives the high level via the inverter 43. Therefore, the latch-enable pulse LE is generated from the AND gate in response to the low level of the clock signal CLK. When the clock signal CLK changes from the low level to the high level, the F/F circuit 47 introduces the low level input and changes its output to the low level. As a result, the output of the OR gate 41 changes to the low level, and the data sampling cycle starts. Also in this embodiment, the latch-enable signal is prevented from being generated simultaneously with the read request signal. Moreover, since the divider 40 continues to operate, it is used in common to a divider provided in the peripheral units 160. The present invention is not limited to the above embodiments, but may be changed and modified without departing from the scope of the invention. For example, the operating control signal OC can be supplied to each of the comparators 5-0 to 5-7 to activate them only during the high level period of the signal OC.

Claims: An input circuit comprising: at least one input terminal (1) supplied with an input signal (B), a latch circuit (6) having at least one input node and at least one output node and latching data at said input node therein in response to a latch pulse (LE), a timing circuit (10) generating said latch pulse, at least one output terminal (8), a buffer circuit (7) receiving a read request signal (RE) and coupling said output node of said latch circuit (6) to said output terminal when said read request signal takes an active level, characterized in that said input circuit further comprises input means (4, 5) coupled between said input terminal and said input node of said latch circuit (6) for sampling said input signal during a first logic level of an operating control signal (OC) and supplying said input node of said latch circuit (6) with said data indicative of the sampled input signal during a second logic level of said operating control signal, and that said timing circuit (10) generates said operating control signal which takes said first and second logic levels alternately in a predetermined cycle, generates said latch pulse for a constant period of time at the end of a period of said second logic level of said operating control signal and prolongs, when said read request signal takes said active level, said period of said second logic level of said operating control signal such that said read request signal changes from said active level to an inactive level before said latch pulse is generated. The input circuit as claimed in claim 1, characterized in that said input means (4, 5) includes a sampled/hold circuit (4) which samples said input signal during said first logic level of said operating control signal and holds and outputs said sampled signal during said second logic level of said operating control signal, and a comparator (5) comparing said sampled input signal held by said sample/hold circuit with a reference level to supply said data to said input node of said latch circuit (6). The input circuit as claimed in claim 1 or 2, characterized in that said timing circuit includes a divider (20, 40) dividing a clock signal (CLK) supplied thereto to generate said operating control signal and an additional control signal, first gate (21, 22) responsive to said clock signal and said additional control signal for generating said latch pulse, and second gate means (23-25) for preventing said clock signal from being supplied to said divider (20, 40) and said first gate means (21, 22) during said inactive level of said request signal.

Inventors: AKASHI MINEO, AKASHI, MINEO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G06F13
IPC codes: G06F15, G06F3, G11C7, G06F13