BIPOLAR TRANSISTOR

Abstract: A so-called graft-base transistor is disclosed. The transistor is formed in an island-shaped region (23) surrounded by an insulating isolation region (22) formed in an epitaxially grown semiconductor layer on a silicon substrate (21). A graft base region (24g) having higher impurity concentration is formed in the island-shaped region (23) remote from the isolation region (22). A surface portion (37) of the island shaped region (23) between the isolation region (22) and the graft base region (24g) is entirely depleted during operation.

Description: This invention relates to a bipolar transistor and more particularly to such bipolar transistor having a so-called graft base region for base contact. As a bipolar transistor with high operating speed and low power consumption, there is known e.g. one as shown in Fig. 5. In this transistor, an n-type semiconductor layer is formed on a p-type semiconductor substrate 1 by, for example, epitaxial growth, and is divided by isolation regions 2, such as of silicon oxide, into several island-shaped regions, such as a region 3. A p-type base region 4 is formed to confront to the surface of the n-type semiconductor layer of this island-shaped region 3, and an n⁺ type emitter region 5 is formed within this base region 4. This base region 4 comprises a base active region 4i at substantially the central portion for achieving the function of the base per se and a so-called graft base region 4g of higher concentration for the base electrode contact. The graft base region 4g is formed by diffusion of the p-type impurities from a base contact electrode 6 of the p⁺ type polycrystal silicon layer, while the base active region 4i is formed by ion implantation of p-type impurities using the base contact electrode 6 as a mask. The emitter region 5 is formed by introduction of n-type impurities from the n⁺ type polycrystal silicon layer 7 which serves as an emitter contact. The inner edge of an insulating layer 8 is used for the emitter diffusion mask. A base electrode 9B formed of such as Al is connected to the base contact electrode 6, while an emitter electrode 9E is connected to the n⁺ type polycrystal silicon layer 7. It is noted that, in this example of Fig. 5, a collector electrode 9C is electrically connected to the island-shaped region 3 of the n-type epitaxial layer used as the collector region through an n⁺ type buried layer 11 and an n⁺ type electrode contact area 12. With the above described so-called graft base type bipolar transistor, it is possible to simplify the manufacturing process through emitter-base self-align and reduce parasitic capacity, while simultaneously minutizing the emitter width or achieving so-called shallow junction. Fig. 6 shows in an enlarged scale the vicinity of the so-called graft base region 4g of the transistor. It may be seen from this figure that there exists a large parasitic capacity C o through a depletion region D p in the vicinity of the bottom surface of the junction impeding high-speed operation. Also, when forming the isolation region 2 by, for example, selective oxidation of the silicon surface, fluctuations are caused in the element size due to so-called bird's beaks generated in the vicinity of the semiconductor surface on the boundary of the area 2 and, above all, such fluctuations in the size are relatively increased when the area occupied by the element is to be decreased to achieve a higher degree of integration, thus impeding the higher degree of integration. With this in view, a bipolar transistor having the structure shown in Fig. 7 has been proposed. Thus a thin insulating layer 14 is formed on the semiconductor surface, and windows are formed in this insulating layer 14 at a prescribed distance from the boundary of the isolation region 2, after which the base contact electrode 6 formed of the aforementioned P⁺ type polycrystal silicon is deposited. This predetermined distance is so set as to be able to avoid the effect of the so-called bird's beak on the boundary of the aforementioned isolation region 2. Since the structure is otherwise the same as that in the above described example of Fig. 5, the corresponding parts are indicated by the same reference numerals and the corresponding description is omitted. The prior art bipolar transistor according to Fig. 7 comprises the following features: a semiconductor substrate; a semiconductor layer on the top surface of said substrate, said layer comprising a collector region encircled by an isolation region; a base region provided in a top portion of said collector region remote from said isolation region; an emitter region provided in the central top portion of said base region, thereby structuring said base region into an active base region between said emitter region and said collector region, and a graft base region surrounding said active base region; an insulating film on the top surface of said semiconductor layer and reaching from said isolation region to said graft base region; and a base contact electrode on said insulating film, said electrode contacting said graft base region. It is possible with the bipolar transistor of Fig. 7 to reduce the base area with higher precision and to reduce the parasitic capacity. However, a depletion region D p exists which encircles the graft base region 4g, as shown in Fig. 8. Therefore, when considering the collector-base capacity there are produced a capacity C o ' on the side of the junction bottom surface, a capacity C s on the side of the junction lateral surface and a capacity C ox formed by the base contact electrode 6 and the collector region (n-type epitaxial layer) 3 through an insulating layer 14, so that the parasitic capacity may become larger than that of the structure of Fig. 5 depending on the size. As a measure to reduce the capacity of the collector-base junction in a bipolar transistor, it is known from US-E-27 045 to provide a region of intrinsic conductivity between the emitter and the base regions, except that part of the collector-base junction which is close to that part of the base region into which carriers are injected from the emitter region. FR-A-2 309 980 describes a bipolar transistor having a groove surrounding the active part. To influence the shape of the electric field close to the groove, a charged insulating film of glass is provided in surface parts of the active region. It is the object of the present invention to provide a bipolar transistor capable of high speed operation. The bipolar transistor of the present invention comprises the above listed features of the transistor of Fig. 7, and it is characterized in that said insulating film is charged in a way to deplete at least a portion close to the surface of the collector region extending between the base region and the isolating region at least during operation of said transistor. In such transistors, the capacity between the collector region and the base electrode is reduced due to a depletion region provided in the collector region below the insulating film which is disposed between the collector region and the base electrode. Due to the reduced capacity, the transistors are capable of high speed operation. The invention will now be explained in detail with reference to embodiments which are illustrated by figures. Fig. 1 is a schematic sectional view showing an embodiment of the present invention; Fig. 2 is a schematic sectional view showing essential parts of the embodiment of Fig. 1 to an enlarged scale; Fig. 3 is a schematic plan view showing an example of the depletion layer forming state according to the prior art; Fig. 4 is a schematic sectional view showing a modified embodiment of the present invention; Figs. 5 to 8 refer to the prior art, wherein Fig. 5 is a schematic sectional view showing the prior art; Fig. 6 is a schematic sectional view showing essential parts of a prior-art example, to an enlarged scale; Fig. 7 is a schematic sectional view showing another prior-art example; and Fig. 8 is a schematic sectional view showing essential parts of the prior-art example of Fig. 7 to an enlarged scale. In the present invention a bipolar transistor is provided in which a base contact region of a higher concentration is disposed between an emitter region and an isolation region and a base electrode is arranged on said base contact region. In operation, a depletion region is provided in the vicinity of the substrate surface between the base contact region and the isolation region. The vicinity of the substrate surface between the base contact region and the isolation region is in the state of depletion, so that the parasitic capacity between the collector and the base is markedly reduced to realize the high speed operation. Fig. 1 is a schematic sectional view showing essential parts of the semiconductor device according to an embodiment of the present invention. Referring to Fig. 1, an n-type semiconductor layer is formed as by epitaxial growth on a p-type semiconductor substrate 21, which layer is isolated into several island-shaped regions, such as region 23, by isolation regions 22, such as of silicon oxide. A p-type base region 24 is formed for facing to the surface of the n-type semiconductor layer of the island-shaped region 23 and an n⁺ type emitter region 25 is formed within this base region 24. This base region 24 is formed by a base active region 24i at substantially the center for achieving the function of the base per se and a so-called graft base region 24g of a higher concentration for the base electrode contact. The graft base region 24g is formed by diffusion of p-type impurities from the base contact electrode 26 made of a p⁺ type polycrystaline silicon layer, while the base active region 24i is formed by ion implantation of p-type impurities with the base contact electrode 26 being used as a mask. The emitter region 25 is formed by introduction of n-type impurities from the n⁺ type polycrystal silicon layer 27 formed for the emitter contact on the insulating layer 28. In addition, there are formed a base electrode 29B of, for example, Al, on the base contact electrode 26, and an emitter electrode 29E on the n⁺ type polycrystal silicon layer 27. It will be noted that, in the example of Fig. 1 the collector electrode 29c is electrically connected to the island-shaped region 23 of the n-type buried layer as the collector region through the n⁺ type buried layer 31 and the n⁺ type electrode contact region 32. It is noted that the base contact electrode 26 of the p⁺ type polycrystal silicon layer is deposited on a thin insulating film 34 formed on a semiconductor surface, and the base contact electrode 26 is contacted with the epitaxially grown layer or the island-shaped region 23 through an opening 35 formed in the insulating layer 34 to effect the above described diffusion of the n-type impurities. In this case, the opening 35 is formed at a position spaced a predetermined distance from the boundary of the isolation region 22 to avoid the effect of the so-called bird's beak otherwise produced on the boundary of the isolation region 22 upon selective oxidation of silicon to form the isolation region to suppress the fluctuations in the dimensional accuracy. Therefore, the graft base region 24g is provided at a predtermined distance from the isolation region 22. According to the present invention, there is provided a region 37 which is to be the depletion region at least during the operation of the element in the vicinity of a portion on the surface of the semiconductor substrate or the surface of the island-shaped region 23 of the aforementioned epitaxial layer lying between the isolation region 22 and the graft base region 24g as the base contact region having higher concentration, more specifically, this region 37 is designed for example as the so-called intrinsic semiconductor region. Such intrinsic semiconductor region 37 may be formed by previously introducing p-type impurities by, for example, ion implantation, in an amount which will cancel the n-type impurities of the aforementioned n-type epitaxial layer. Alternatively, the semiconductor region 37 may be formed to provide the n⁻ or p⁻ type having low impurity concentration so that a state of sufficient depletion may be satisfied in the operating state. Fig. 2 shows in an enlarged scale a portion extending between the graft base region 24g and the isolation region 22 in the operating state, wherein the depletion region D p is formed continuously between the graft base region 24g and the isolation region 22 as the region 37 being depleted completely. At this time, the parasitic capacity C ox' under the thin insulating film 34 is markedly lowered since it is a series connection capacitance of the parasitic capacity C ox of the insulating film 14 of the prior art described above and the capacity of the depletion layer D p . On the other hand, the capacity C s ' at the lateral side portion of the graft base region 24g has its effective depletion layer increased in width so that the capacity C s ' is reduced. It will be noted that, although the parasitic capacity C o ' on the junction bottom surface is approximately same as that of the prior art, it has become possible to reduce the collector-base capacity markedly with the aforementioned capacities C ox ' and C s ' both being reduced. When the region 37 is not provided, even though the depletion layer is widened by the bias voltage being applied between the collector and the base, there remains a portion difficult to be depleted such as at the corners of the island-shaped region 23 that is to be the collector area, as in shown in Fig. 3, so that the parasitic capacity due to it cannot be disregarded. On the contrary, by previously providing the aforementioned intrinsic semiconductor region (which may be n⁻ type p⁻ type region) for promoting the depletion under the operating condition, a depletion layer is formed at the portion on the substrate surface between the graft base region 24 and the isolation region 22 in the vicinity of the island-shaped region 23 throughout the entire area. It will be noted that, for forming the depletion region in the vicinity of the substrate surface extending between the graft base region 24g and the isolation region 22 during the operation, an insulating layer of Al₂O₃ (alumina), for example, having the negative charges Q ss may be provided, as shown in Fig. 4, instead of providing the aforementioned intrinsic (or n⁻ or p⁻ type) semiconductor region 37. In the present embodiment of Fig. 4, the negative charges Q ss are formed in the insulating film 34', so that a depletion layer is apt to be formed in the vicinity of the surface of the island-shaped region 23 below the insulating film 34', so that the entire area between the graft base region 24g and the isolation region 22 in the vicinity of the substrate surface is depleted at least during the operation. The parasitic capacity can naturally be reduced by such depletion of the layer. It is to be noted that the present invention is not limited to the above embodiment, but the p and n conductivity types can be reversed. It will be seen from above that, in the bipolar transistor of the present invention, the vicinity of the substrate surface between the base contact region (graft base region) and the isolation region becomes depleted at least during the operation, such that the parasitic capacity between the collector and the base is markedly reduced to provide for a high speed operation.

Claims: A bipolar transistor comprising: a semiconductor substrate (21); a semiconductor layer on the top surface of said substrate, said layer comprising a collector region (23) encircled by an isolation region (22); a base region (24) provided in a top portion of said collector region remote from said isolation region; an emitter region (25) provided in the central top portion of said base region, thereby structuring said base region into an active base region (24i) between said emitter region and said collector region, and a graft base region (24g) surrounding said active base region; an insulating film (34) on the top surface of said semiconductor layer and reaching from said isolation region to said graft base region; and a base contact electrode (26) on said insulating film, said electrode contacting said graft base region; characterized in that said insulating film (34') is charged in a way to deplete at least a portion close to the surface of the collector region (23) extending between the base region (24) and the isolating region (22) at least during operation of said transistor.

Inventors: KAYANUMA, AKIO
Applicants: SONY CORPORATION
Application year: 1988
Main classification: H01L29
IPC codes: H01L21, H01L29