Coprocessor and method of controlling the same

Abstract: The interface portion of a coprocessor is provided with a FIFO (500) (First-in First-Out) and means for accepting instructions in succession. The pipeline control of the instructions becomes possible in this way, and protocol means (200) associated with a microprocessor is also provided.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a pipeline system, and more particularly to an interface system of a coprocessor well suited to the high-speed processing of a floating-point processor that is the coprocessor of a processor. As stated in "IEEE MICRO," pp. 44 - 54, 1983. 12 by way of example, a coprocessor interface in a prior art is of a system wherein, when one instruction has ended and the next instruction has been sent, a status in the preceding instructions execution of the operation is brought back. Therefore, the instructions are intermittently sent to a coprocessor one by one, and the overhead of the interface is heavy. The prior-art technique does not take the enhancement of the throughput of operations into consideration, and has the problem of a long operating time. SUMMARY OF THE INVENTION: An object of the present invention is to raise the operating speed of a coprocessor by having the acceptance of the coprocessor is instructions pipelined. The object is accomplished by dividing the function of the coprocessor, especially a floating-point processor. More specifically, the interface portion of the coprocessor is provided with a FIFO (First-In First-Out) and means for accepting instructions in succession. Besides, the pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided. By disposing the FIFO in the interface portion of the coprocessor, the microprocessor can send data items to the coprocessor until the FIFO is filled up. The coprocessor has its function divided also to enable the pipeline control. As a result the data items are successively processed at high speed. Therefore, the present invention can execute an operation at high speed, and in claimed in the independent claims. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a diagram of a microcomputer system which includes a coprocessor in an embodiment of the present invention; Fig. 2 is a diagram of an embodiment of the blocks of a floating-point processor according to the present invention; Fig. 3 is a diagram for explaining a format conversion function; Fig. 4 is a timing chart of a command pipeline control according to the present invention; Fig. 5 is a diagram of an embodiment of the internal blocks of a bus control unit; and Figs. 6 - 11 are detailed timing charts of protocols in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS: Now, an embodiment of the present invention will be described with reference to Fig. 1. Shown in Fig. 1 is a floating point arithmetic microcomputer system To perform the floating-point arithmetic, this system has two arithmetic circuits; a CPU (Central Processing Unit) 100 and an FPU (Floating-point Processing Unit) 101. The CPU 100 and the FPU 101 are preferably integrated on semiconductor substrates separate from each other but may be integrated on a single semiconductor substrate as well. Essentially, the CPU 100 processes only data of the integer type and cannot process data of the floating-point type. On the other hand, the FPU 101 can process the data of the floating-point type. A ROM (Read Only Memory) 102 stores a program in which instructions for the two arithmetic circuits of the CPU 100 and the FPU 101 coexist. However, it is the CPU 100 that can decode the instructions. Therefore, the FPU 101 is interfaced at high speed by protocols with the CPU 100. Here, the FPU 101 of the properties described above shall be called the "coprocessor." A RAM (Random Access Memory) 103 holds integer type and floating-point type data. Numeral 104 indicates an address bus for addresses delivered from the CPU 100. Numeral 105 indicates a data bus, and numeral 106 a control bus for controls concerning interfaces. Next, the details of a coprocessor interface will be described by taking the floating-point coprocessor (FPU) 101 as an example. Fig. 2 shows a block diagram of the floating-point coprocessor 101. Numeral 200 indicates a bus control unit (BCU) which executes the coprocessor interface of high speed. Input/output signals connected to the BCU 200 are signals CLK, D31 - D0, , , , R/ , , , CPST2 - CPST0, AT3 - AT0, and A2 - A0. The signal CLK is an externally supplied clock signal serving as the reference of internal operations of the floating-point coprocessor. The signals D31 - D0 are data signals. In the figure, the signal is a chip select signal for selecting the FPU 101. The signal is an address strobe input signal indicating that an address signal exists on the address bus 104. The signal is a data strobe input signal which indicates that a data signal exists on the data bus 105. The signal R/ is an input signal indicating the direction of data transfer. The R/ -signal becomes "1" when the CPU 100 reads data from an external memory, while it becomes "0" when the CPU writes data to the external memory. The signal indicates that data transfer on the data bus 105 has ended. When data is transferred between the CPU 100 and the FPU 101, the signal is output from the FPU 101 to the CPU 100. In addition, when data is transferred between the FPU 101 and the external memory, the signal is input from the external memory to the FPU 101. The signal is a coprocessor data enable signal. Upon lapse of one clock cycle after this signal has been asserted, the FPU 101 outputs a destination operand onto the data bus 105. This signal is applied from the CPU 100 as an output timing recognition signal. The signals CPST2 - CPST0 are signals indicating the internal operation status of the FPU 101. In addition, the signals AT2 - ATO are signals which are output from the CPU 100 and indicate the sort of access. The FPU 101 operates in such a way that the type of control information to be transferred from the CPU 100 is recognized on the basis of these signals. That is, the FPU 101 operates upon receiving the signals AT2 - AT0 from the CPU 100 and returns the signals CPST2 - CPST0 indicating its operating status to the CPU 100, thereby to execute the coprocessor protocol. Table 1 and Table 2 are the decode tables of the signals CPST2 - CPST0 and AT2 - ATO, respectively. The signals A2 - A0 are address data signals which are output from the CPU 100. By decoding a command as described above, the protocol between the CPU 100 and the FPU 101 is controlled and managed. Numeral 201 indicates a format conversion unit (FCU) which converts single-precision data, double-precision data and double-extended-precision data represented in an external format into data in an internal format (double-extended-precision format). Input/output data to or from the FCU 201 is transferred through the BCU 200 as well as a conversion data bus 206. An example of the format conversion operation is shown in Fig. 3. By way of example, when external data stored in the BCU 200 is the single-precision data (having a sign of 1 bit, an exponent of 8 bits, and a mantissa of 23 bits), it is input to the FCU 201 through the converted data bus 206. As shown in Fig. 3, the exponent part of the single-precision data having been input to the FCU 201 has its bias value removed into an exponent of 15 bits in conformity with the specification of IEEE. In addition, a mantissa is set in such a way that the 23 bits are placed close to an upper bit side, and that all the remaining bits are made "0." On the other hand, when data is transferred from the FCU 201 to the BCU 200, the FCU 201 performs a conversion reverse to that of Fig. 3; from the internal format (double-extended-precision format) into a designated external format. Numeral 202 indicates an execution unit (EU) which executes the floating-point arithmetic. The EU 202 receives the converted data in the internal format (double-extended-precision format) from the FCU 201 and via an operation data bus 207. The EU202 then executes a desired operation. It is constructed of an ALU, a register file, a barrel shifter, etc. Numeral 203 indicates a microprogram unit (MAC) for executing a floating-point instruction, and an instruction execution code 209 decoded by and output from the MAC 203 is passed through an instruction decoder 204 into FCU control signals 211 and EU control signals 210, which control the FCU 201 and the EU 202, respectively. Numeral 205 denotes an instruction sequencer (ISC) for controlling the MAC 203. In addition, a command to the ISC 205 is output from the BCU 200 and via an instruction bus 208. The above description concerns the flow of data. Besides, the BCU 200 receives a command output from the CPU 100 and delivers it to the ISC 205. The delivered command is decoded in the ISC 205. Fig. 4 is a timing chart for explaining the pipeline control system of the FPU 101. In this figure, the flows of the executions of the k-th command CMD k through the (k + 3)-th command CMD k+3 are shown. In addition, Fig. 5 shows the internal arrangement of the bus control unit BCU 200. Numeral 500 denotes a FIFO (First-In First-Out) for fetching data on the commands and operands of the data bus 105. During operation, as illustrated in Fig. 4, the k-th command CMD k is fetched in the FIFO 500 under a state 1 ○ in the figure, the k-th source operand OPS k is fetched in the FIFO 500 under a state 2 ○, and the k-th instruction address IAR k is fetched in the FIFO 500 under a state 3 ○. The (k + 1)-th command CMD k+1 , source operand OPS k+1 and instruction address IAR k+1 are successively fetched in the FIFO 500 under states 4 ○, 5 ○ and 6 ○ ; the (k + 2)-th command CMD k+2 , source operand OPS k+2 and instruction address IAR k+2 are similarly done under states 7 ○, 8 ○ and 9 ○ ; and the (k + 3)-th command CMD k+3 , source operand OPS k+3 and instruction address IAR k+3 are similarly done under states , and . The commands, operands and instruction addresses fetched in the FIFO 500 are output to a BCU internal bus 502. Among the data output to the BCU internal bus 502, the commands are input to a protocol execution portion (PTE) 501. The PTE 501 controls and manages protocols and supplies the CPU 100 with the signals CPST2 - CPST0 indicating the internal operation status. In addition, the commands are input to the instruction sequencer 205 through the instruction bus 208. On the other hand, the operands are input to the format conversion unit (FCU) 201 through the BCU internal bus 502 as well as the conversion data bus 206. (For example, under the state 3 ○, the k-th operand OPS k is input to the FCU 201, in which the format conversion is executed.) Subsequently, the data subjected to the format conversion by the FCU 201 is sent to the floating-point execution unit EU 202, which then starts the execution of the k-th command CMD k . Simultaneously with the start of the execution, the fetch of the succeeding (k + 1)-th command CMD k+1 is started. (state 4 ○) By pipeline-controlling the executions of the BCU 200, FCU 201 and EU 202 in this manner, the processed result of the (k - 1)-th command CMD k+1 can be obtained at the end of the state 3 ○, that of the k-th command CMD k at the end of the state 6 ○, that of the (k + 1)-th command CMD k+1 at the end of the state 9 ○, and that of the (k + 2)-th command CMD k+2 at the end of the state . Shown in Fig. 4 is a case where the source operands are fetched from a memory and where destination operands are fetched from a register. Next, Figs. 6 - 11 are diagrams elucidating the executions of protocols. Basic protocols can be broadly classified as follows: (1) Case where an operand out transfer exists, that is, where a succeeding command is accepted in synchronism with an output. (2) Case of an n-term instruction or the like where a burst transfer is impossible. (3) Case of a conditional branch or the like where no command is accepted until the execution of a preceding command ends. (4) Case of a privileged instruction or the like where the command thereof is accepted at any time. (5) Case other than the above cases (1) - (4), where the operand out transfer does not exist. Depending upon these cases (1) - (5), the FPU 101 provides the signals CPST2 - CPST0 and executes the protocol in a bus cycle concerning the FPU 101, subsequent to a command transfer (command transfer protocol), or when informing the CPU 100 of the grant or reservation of the start of the in/out transfer of an operand or the occurrence of any of various exceptions (operand transfer protocol). The command transfer protocols are divided into the following cases: (1) Case where the operand out transfer does not exist. (2) Case where the operand out transfer exists. (3) Case of the conditional branch. (4) Case of FREST. (5) Case of the privileged instruction. Table 3 lists the output statuses of the signals CPST2 - CPST0 (Table 1) in the respective cases. In the command transfer protocols, the following output statuses of the signals CPST2 - CPST0 are used: (1) ACC (Accepted)/TRUE (2) CERR (Command Error) (3) BUSY (4) EXCP (Exception) (5) DTR (Data Transfer Ready)/FALSE In each of the aforementioned cases, the output conditions of the statuses ACC, CERR, BUSY, EXCP and DTR are listed. These conditions correspond to the case of performing the pipeline control, and depend upon the statuses of preceding and current commands. Here, the "preceding command" signifies a command output from the FIFO 500 of the BCU 200. In addition, the "current command" signifies a command currently input to the FIFO 500. The operand transfer protocol is executed in such a way that the FPU 101 handshakes with the CPU 100 in accordance with the DTR status of the signals CPST2 - CPST0 thereof. In the absence of an error in both the preceding command and the current command, when an operand needs to be input, the CPU 100 acknowledges and decides the DTR status of the signals CPST2 - CPST0, and thereafter, the transfer of the operand is started. In addition, the signals CPST2 - CPST0 indicate the BUSY status until the internal status of the FPU 101 gets ready to transfer the next operand. In outputting an operand, the protocol is executed as in the operand input by the handshake of the FPU 101 with the CPU 100 in accordance with the DTR status of the signals CPST2 - CPST0. That is, the start of an operand transfer cycle is granted according to the DTR status. Thereafter, the FPU 101 delivers the BUSY status until its internal status becomes capable of outputting the signals of the DTR status for granting the transfer of the next operand. Now, the timing charts of protocols are shown in Figs. 6 - 11. Timings differ between an operation mode and an addressing mode. Fig. 6 is the detailed timing chart of the monadic and dyadic operations between a register (source) and a register (destination). First, a command CMD on the data bus 105 is fetched in the FIFO 500 of the BCU 200. While an instruction address IAR is further fetched, the BCU 200 decodes the protocol of the command and generates a command transfer protocol in the protocol signals CPST2 - CPST0 in accordance with conditions listed in Table 3. Also, Fig. 6 is the detailed timing chart of a branch instruction. In the operation, a branch command CMD on the data bus 105 is fetched in the FIFO 500 of the BCU 200. While an instruction address IAR is further fetched, the BCU 200 decodes a branch condition, to generate TRUE (ACC) if the condition is true and FALSE (DTR) if it is false, in the protocol signals CPST2 - CPST0 as indicated in Table 3. Fig. 7 is the detailed timing chart of the monadic and dyadic operations between a memory (source) and a register (destination). Since, in this case, the operand(s) of the source is the data of the memory, the source operand(s) on the data bus 105 needs to be fetched. In the operation, a command CMD on the data bus 105 is fetched in the FIFO 500 of the BCU 200. Thereafter, data items in numbers required depending upon the size of the operand(s), the single precision S, the integer I, the double precision D and the double extended precision X are fetched in the FIFO 500 within the BCU 200. In addition, a command transfer protocol is generated as the protocol signals CPST2 - CPST0 in accordance with Table 3. After all the operands of the source have been transferred, an instruction address IAR is fetched in the BCU 200. Fig. 8 is the detailed timing chart of the monadic operation between a memory (source) and a memory (destination) and the dyadic operation between a register (first source) as well as a memory (second source) and a memory (destination). In this case, the operands of the sources are the data of the memory, and the operands of the destination become storing data into the memory, so that the bus cycles of the operands arise twice. In the operation, a command CMD on the data bus 105 is fetched in the FIFO 500 within the BCU 200. Thereafter, in the same manner as in Fig. 7, data items in numbers required depending upon the size of the operands, the single precision S, the integer I, the double precision D and the double extended precision X are fetched in the FIFO 500 within the BCU 200. Besides, a command transfer protocol is generated as the protocol signals CPST2 - CPST0. Since the destination is the memory, the BUSY status is output as the signals CPST2 - CPST0 until the end of the operations. When, upon the end of the operations, the FPU 101 has become ready to transfer data (in accordance with an operand transfer protocol), the status DTR (Data Transfer Ready) is output, and the operand data of the destination is transferred to the memory. Also in this case, the data items in numbers required depending upon the size of the operands, the single precision S, the integer I, the double precision D and the double extended precision X are transferred from the FIFO 500 within the BCU 200. Fig. 9 is the detailed timing chart of the dyadic operation between a memory (source) and a memory (destination). Here, the two operands of the source are the data of the memory, and the operand of the destination also becomes storing data into the memory, so that the bus cycles of the operands arise three times. In the operation, a command CMD on the data bus 105 is fetched in the FIFO 500 of the BCU 200. Thereafter, in the same manner as in Fig. 7, source operand #1 and source operand #2 as data items in numbers required depending upon the size of the operands, the single precision S, the integer I, the double precision D and the double extended precision X are fetched in the FIFO 500 within the BCU 200. Further, an instruction address IAR is fetched. Also in this case, as in Fig. 8, the BUSY status continues to be output as the protocol signals CPST2 - CPST0 until the end of the operation. When, upon the end of the operation, the FPU 101 has become ready to transfer data, the status DTR (Data Transfer Ready) is output according to an operand transfer protocol so as to transfer the operand data of the destination to the memory. Also in this case, the data items in numbers required depending upon the size of the operands, the single precision S, the integer I, the double precision D and the double extended precision X are transferred from the FIFO 500 within the BCU 200. The FPU 101 has data transfer instructions besides operation instructions in the monadic and dyadic forms, etc. The data transfer instructions include an instruction of data transfer (operand in transfer) from the memory to the register of the FPU and an instruction of data transfer (operand out transfer) from the register of the FPU to the memory. Fig. 10 shows the detailed timing chart of a large number of operand in-transfer instructions, while Fig. 11 shows the detailed timing chart of an operand out-transfer instruction. Regarding the n operand in-transfer instructions in Fig. 10, in the same manner as in Fig. 7, data items in numbers required depending upon the size of the operands of sources, the single precision S, the integer I, the double precision D and the double extended precision X are fetched in the FIFO 500 within the BCU 200, while data items are sent to the FCU 201. During the operation, after a command CMD on the data bus 105 is fetched in the FIFO 500 within the BCU 200, the first source operand #1 is fetched, and thereafter, the protocol signals CPST2 - CPST0 output the status DTR (Data Transfer Ready) in accordance with an operand transfer protocol. In the illustrated case, there are n source operands, so that the signals CPST2 - CPST0 output the statuses BUSY and DTR alternately until the transfer of source operand #n ends. Fig. 11 illustrates one operand out-transfer instruction. In the operation, a command CMD on the data bus 105 is fetched in the FIFO 500 within the BCU 200. Thereafter, the BCU 200 fetches an instruction address IAR because a source operand resides in the register of the FPU 101. At that time, the protocol signals CPST2 - CPST0 output a command transfer protocol in accordance with Table 3. Thereafter, the status BUSY is output until the FPU 101 gets ready to transfer an operand. When the FPU has got ready for the transfer, the signals CPST2 - CPST0 outputs the status DTR being an operand transfer protocol, and operand data items OPD1 - OPD3 are delivered onto the data bus 105. Incidentally, although one bus cycle is performed by three clock pulses in the drawings, this is not restrictive. According to the present invention, floating-point arithmetic is functionally divided and is pipeline-controlled, whereby a command pipeline can be realized, so that the overhead of an interface in the floating-point arithmetic can be lessened, thereby enhancing an operating speed. Moreover, protocols are defined between a microprocessor and a floating-point processor, so that disposal at the occurrence of an error is facilitated. The protocols are applicable to coprocessors other than the floating-point processor.

Claims: A coprocessor (101), connected via a bus (104, 105, 106) to a CPU (100) that decodes instructions and processes data, to a ROM (102) that stores the instructions, and to a RAM (103) that holds data, wherein the coprocessor receives instructions and operands in a pipeline control means (200) interfacing with said bus (104, 105, 106), and processes data in response to the instructions and operands being output from said pipeline control means (200), comprising: an internal coprocessor bus (206, 207, 208); protocol executing means (501), receiving instructions and operands being input to said pipeline control means (200), and being connected to said internal coprocessor bus, for executing protocols in response to received instructions sent from the CPU (100) to said coprocessor (101), based on an internal operation status of said coprocessor, said means for executing protocols comprising means for returning an internal operation status of the coprocessor to the CPU; instruction executing means (201, 202), connected to said internal coprocessor bus, for executing the received instructions and operands being output from said pipeline control means independent of said protocol executing means for executing protocols; and said pipeline control means (200) being connected to said bus and said internal coprocessor bus so performing pipeline control of said protocol executing means and said instruction executing means. The coprocessor of claim 1, wherein said pipeline control means (200) comprises a FIFO memory (500), said FIFO memory (500) receiving said instructions and operands for the coprocessor (101). The processor of claim 1, wherein said protocol executing means (501) comprises: means for receiving first signals (AT0, ..., AT2) indicating a type of an access desired by said CPU; and means for judging the receipt of instructions and operands based on said first signals. A coprocessor (101) connected, via a bus (104, 105, 106), to a CPU (100) that decodes instructions and processes data, to a ROM (102) for storing the instructions, and to a RAM (103) for holding data, wherein the coprocessor (101) receives floating-point arithmetic instructions and operands in a pipeline control means (200) interfacing with said bus and processes data in response to the floating-point arithmetic instructions and operands being output from said pipeline control means (200), the coprocessor (101) comprising: an internal coprocessor bus; said pipeline control means (200) connected to the bus (104, 105, 106) and an internal coprocessor bus (206, 208); a protocol execution unit (501), receiving instructions and operands being input to said pipeline control means (200), and being connected to said coprocessor internal bus (206, 208), said protocol execution unit (501) judging the receipt of floating-point arithmetic instructions and operands, sent from the CPU (100) to said coprocessor (101) and received by said pipeline control means (200), and executing protocols in response to received instructions based on an internal operation status of said coprocessor (101), and returning the internal operation status of the coprocessor (101) to the bus (106) for transmission to said CPU (100); an instruction sequencer (205), connected to said coprocessor internal bus (208), controlling a sequence of the floating-point arithmetic instructions received by said pipeline control means (200); a format conversion unit (201), connected to said coprocessor internal bus (206), converting the operands received by said pipeline control means (200) to an internal format; an execution unit (202) connected to said instruction sequencer and said format conversion unit (201), said execution unit (202) executing the floating-point arithmetic instructions based on the operands converted to the internal format independent of an operation of said protocol execution unit (501). The coprocessor of claim 4, wherein said pipeline control means (200) comprises a FIFO memory (500), said FIFO memory (500) receiving said floating-point arithmetic instructions and operands from the processor (100). The coprocessor of claim 4, wherein said protocol execution unit (501): receives first signals (AT0, AT2) indicating a type of access desired by said CPU; and judges the receipt of the instructions and operands based on the first signals. A method of controlling a coprocessor (101) connected, via a bus (104, 105, 106), to a CPU (100) that decodes instructions and processes data, to a ROM (102) that stores the instructions, and to a RAM (103) that holds data, wherein the coprocessor (101) receives instructions and operands in a pipeline control means (200) interfacing with said bus, and processes data corresponding to the instructions and operands being output from said pipeline control means (200), the method being executed within the coprocessor, and comprising judging the receipt of instructions and operands being input to said pipeline control means (200), and executing protocols in response to the instructions based on an internal operation status of said coprocessor; returning an indication of the internal operation status of the coprocessor to said CPU; executing the instructions and operands being output from said pipeline control means (200) independent of said judging step; so performing a pipeline control of said judging step and said executing step. A microcomputer system comprising a ROM (102) storing instructions, a RAM (103) storing data operands, a CPU (100) decoding instructions from said ROM (102) and processing integer type data, a coprocessor (101) receiving floating-point arithmetic instructions decoded by the CPU (100) and processing floating point data, an address bus (104), a data bus (105) and a control bus (106), each of the buses being connected to the ROM (102), the CPU (100), the RAM (103) and the coprocessor (101), said coprocessor comprising: a pipeline control means (200) interfacing with the data bus (105) and receiving commands and operands from the data bus, an internal bus (206, 208) coupled to said pipeline control means, and a protocol execution unit (501) coupled to said internal bus (206, 208) and receiving commands and operands being input to said pipeline control means (200), said protocol execution unit (501) producing signals indicating an internal status of the coprocessor (101) and executing protocols in response to the received commands based on said internal status; an instruction sequencer (205), coupled to said internal bus and receiving said commands from said pipeline control means (200); a format conversion unit (201), coupled to said internal bus (206), receiving data from said pipeline control means (200) and converting said received data to a desired internal format; a microprogram unit (203), coupled to said instruction sequencer (205) and producing an instruction execution code; an instructions decoder (204) coupled to said microprogram unit (203) and decoding said instruction execution code; and an execution unit (202) coupled to said format conversion unit (201) and said instruction decoder (204) and executing a decoded instruction execution code with data converted into said desired internal format.

Inventors: ASAI TAKESHI, KAJIWARA HISASHI, KIDA HIROYUKI, MORINAGA SHIGEKI, NAKAGAWA NORIO, OHBA MAMORU, TATEZAKI JUNICHI, WATABE MITSURU, ASAI, TAKESHI, KAJIWARA, HISASHI, KIDA, HIROYUKI, MORINAGA, SHIGEKI, NAKAGAWA, NORIO, OHBA, MAMORU, TATEZAKI, JUNICHI, WATABE, MITSURU
Applicants: HITACHI ENG CO LTD, HITACHI LTD, HITACHI ENGINEERING CO., LTD., HITACHI, LTD.
Application year: 1988
Main classification: G06F9
IPC codes: G06F9, G06F15, G06F7