Microprocessor having a word data memory

Abstract: A microprocessor having a word data memory has a CPU data bus, an address register, an incrementer, a first byte data memory circuit, a second byte data memory circuit, a data input switching circuit and a data output switching circuit. The address register stores all the bit information of an address on the CPU data bus in response to a latching signal. The incrementer receives an address specifying signal as well as a logical product. The first byte data memory circuit receives a logical addition. The second byte data memory circuit receives an address specifying output. The data input switching circuit selectively transfers both word writing and byte writing data into the first and second byte data memory circuits. The data output switching circuit selectively provides data of the first and second byte data memory means onto the higher bit lines and the lower bit lines.

Description: The invention relates to a microprocessor in accordance with the precharacterizing part of claim 1. In prior art microprocessors, in order to improve the access processing to a CPU, the word data memory may be stored with program data arranged in a word order that lower bytes or upper bytes are stored at even number addresses while upper bytes or lower bytes are stored at odd number addresses. However, when the top lower byte (or the top upper byte) of data is stored in an odd number address, the CPU has to perform addressing twice and to access separately the lower bytes and the upper bytes. The two time memory accessing results in slow process operation. GB-A-2 047 926 discloses a prior art memory access system, wherein a memory includes two independently accessible modules which may be accessed singly for a singly byte or together for two bytes. This known memory access system includes an adder which adds 1 to address data. Reading/writing of data into the memory and from the memory is respectively carried out by detecting whether data to be read or written is in byte or word form and whether the address data is even or odd. The prior art document does not describe a timing when address data and read or write data are transferred. Further, a read/write instruction is provided only via one signal line. Therefore, read or write operation is decided by the signal level "1" or "0" of one signal. According to figure 4, the known document describes a memory access system having common signal lines which transfer both address data and read/write data and only one signal line which transfers both a read instruction signal and a write instruction signal. Upon input of the read instruction signal, address data is transferred with the condition that read data is output to the signal line. Therefore, there arises the possibility of mixing read data and address data both on the signal line. Further, upon input of the write instruction signal there arises the possibility that address data is erroneously written in the data memories. A further known memory system is disclosed by EP-A-0 076 155. This known memory system includes an adder circuit which adds "1" to the address data when the latter is odd. The selection which data memory of two memories is used for a read or write operation is carried out by detecting whether read or write data is in byte form or in word form and whether address data is even or odd. Similarly to the cited GB-A-2 047 926, the EP-A-0 076 155 does not disclose a timing scheme when address data and read/write data are transferred. Further, read/write operation is instructed by one signal and address data and read/write data are separately transferred from an address bus and a data bus respectively. The object of the present invention is to provide a microprocessor of the type mentioned in the precharacterizing part of claim 1 which makes it possible to arrange program data without taking account of memory address; Further, the proposed microprocessor should be arranged so that word data memories can provide a high processing speed. To solve the above object, a microprocessor is provided as claimed in claim 1. Dependant claims 2 and 3 characterize advantageous developments thereof. The objects stated above and other objects of the invention are set forth more particularly in the following detailed description and in the accompanying drawings, of which: Figure 1 is a block diagram showing general features of a microprocessor according to the present invention; Figures 2A and 2B are a detailed logic diagram showing the microprocessor of Figure 1; and Figure 3A, 3B and 3C are timing charts for explaining operation of the microprocessor shown in Figures 2A and 2B. DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment according to the present invention will be explained with reference to the accompanying drawings. (GENERAL EXPLANATION OF FEATURES IN STRUCTURE) Figure 1 shows major elements of the microprocessor of the invention. In Figure 1, the microprocessor includes a word data bus (or CPU bus) 10 as well as an address register 20, for example, a RAM address latching circuit, in which all the bit information constituting an address on the CPU bus are stored in response to an address latching signal. First and second byte data memories 70 and 80 comprise a word data memory, the second byte data memory receiving an address specifying signal which is formed of all the remaining bit information except the first bit sent from the address register 20. An incrementer 30 receives an address specifying signal in addition to the logical product of a word/byte specifying signal and the first bit from the address register 20. The incrementer 30 also provides as an address the logical addition of the logical product and an address specifying data to the first byte memory 70. A data memory input/output control signal generator 300 generates an input control signal which transfer selectively word writing data or byte writing data on the CPU bus 10 by higher and lower byte units to the first or second byte data memories 70 and 80. The generator 300 also produces an output control signal to transfer selectively data stored in the first and second byte data memories 70 and 80 to upper and lower bit lines of the CPU bus 10. An input circuit 400 selectively transfers the writing data on the CPU bus 10 by the upper and lower byte units to the first byte data memory 70 and to the second byte data memory 80. An output circuit 500 provides alternatel.y the data read from both the first byte data memory 70 or the second byte data memory 80 by the lower byte and upper byte unites. (DETAILED CIRCUIT CONNECTIONS) A detailed circuit configuration of a microprocessor according to the present invention will be described with reference to Figures 2A and 2B. In Figure 1 and Figures 2A and 2B, the same numerals represent the same elements. In Figures 2A and 2B, the CPU buses 0 through 15 transmit data processed in the CPU. The address register 20 stores as a data memory specifying address all the bit information on the CPU buses 0 to 15 with an occurrence of an address latching signal 21. The output signals Q₀ to Q₁₅ are, for example, a 16 bit information sent from the address register 20. The output signals 23 are all the remaining bit information except the first bit from the address register 20 and act as a base of address to specify the data memories 70 and 80. An output signal 24, or the first bit information Q₀ from the address register 20, is supplied to the data memory input/output control signal generator 300 and may be used as a data input switching signal, a data memory data output signal, a data address generating signal, etc. for the data memory 70 and 80. An inverter gate 25 provides an inverted signal Q₀ or 26 of an output signal Q₀ or 24. The incrementer (or adder) 30 for example, a + 1 incrementer receives the signals Q₁ through Q₁₅ as well as a logical product signal (also referred to an incremental signal or a +1 addition signal) 42 of the output signal Q₀ and a word/byte specifying signal 91 from the data memory input/output control signal generator 300. An address signal 31 is the output signals S₀ through S₁₄ from the incrementer 30 and specifies a lower byte data memory 70. A clock signal 90 is supplied to the data input/output control circuit 300 and is used as a synchronous clock for writing the memory data. A word/byte signal 91 specifies whether a data width for the data memory 70 or 80 used to process the CPU is in byte (ex. 8 bit) or word (ex. 16 bit). A writing signal 92 is provided to the data input/output control circuit 300 in a data writing operation to the data memory 70 or 80. A reading signal 93 is supplied to the data output circuit 500 in reading data out of the data memories 70 and 80. In the input/output control signal generator 300, a logical circuit 40 is, for example, a two input AND gate 41 and provides a +1 addition signal 42 to the incrementer 30 when it receives a word/byte signal 91 and an output signal Q₀ (or 24) from the address register 20. A logical circuit 50 is formed of, for example, two-input OR gates 51 and 53 and outputs both a lower byte data memory specifying signal 52 and a upper byte data memory specifying signal 54 in response to the word/byte signal 91, the address register output Q₀ and the inverter signal Q₀. A logical circuit 60 is formed of, for example, two-input AND gates 61 and 63 and provides, in response to the signals 52 and 54 and a writing signal 92, a control signal 62 for inputting or writing data into the lower byte data memory 70 and a control signal 64 for inputting or writing data into the upper byte data memory 80. The first byte data memory 70, which is a lower byte data memory in this embodiment, is a part of the word data memory to store byte data. The second byte data memory 80, which is an upper byte data memory in this embodiment, is the remaining portion of the word data memory to store byte data. A logical circuit 71 is, for example, a two-input AND gate, and provides a writing signal to the lower byte data memory 70 when it receives a lower byte writing signal 62 and a clock signaL 90. A logical circuit 81 is of, for example, a two-input NAND gate. When both a writing signal 64 and a clock signal 90 are inputted to the circuit 81, a writing signal 82 is output to the second byte data memory 80. In a data input circuit 400, a logical circuit 100 inputs into the lower byte data memory 70 the lower byte data D₀ to D₇ selected among the data D₀ to D₁₅ written on the CPU bus 10. A three state circuit 101 to transmit the written data from the logical circuit 100 to the lower byte data memory bus 102. An inverter gate 45 switches the data input operation to the byte data memory and outputs an inverted signal 46 of a control signal 24 for specifying data output to a data memory. An arithmetic logical circuit 200 inputs to the upper byte data memory 80 the upper byte data D ₈ to D₁₅ by selectively switching the lower byte data and the upper byte data loaded on the CPU bus 10. A three state gate 201 transmits the written data from the circuit 200 to the upper byte data memory bus 202. As seen from the above explanation, the data switching circuit 400 comprises inverter gates 25 and 45, logical circuits 40, 50, 60, 71, 81, 100 and 200, and three state gates 101 and 201. However, the structure of the circuit 400 should not be restricted to the present embodiment and it will be possible to realize various modifications thereof. Next, a data output switching circuit 500 will be explained. A three state gate 103 transmits the data read from the lower byte data memory 70 to the CPU buses 0 to 7. A three state gate 104 transmits the data read from the lower byte data memory 70 to the CPU buses 8 to 15. The inverter 45 outputs an inverted signal 46. A logical circuit 105 is, for example, a two-input NAND gate and provides a switching signal 106 to the three gate circuit 103 in response to both a reading signal 93 and the reversed signal 46 of the output signal Q₀ from the address register 20. A two-input NAND gate circuit 107 as a logical circuit outputs a switching signal 108 to a three state gate 104 when it receives a reading signal 93 and an output signal Q₀ of the address register 20. A three state gate 203 transmits the data read from the upper byte data memory 80 to the CPU buses 0 to 7. A three state gate 204 sends the data read from the upper byte data memory 80 to the CPU buses 8 to 15. A logical circuit 205 is, for example, a two input AND gate and outputs a switching signal 206 to the three state gate 203 in response to a reading signal 93 and an inverted signal 46 of the output signal Q₀ from the address register 20. A logical circuit 207 is, for example, a two input AND gate and provides a switching signal 208 to the three state gate 204 when a reading signal 93 and the output signal Q₀ of the address register 20 are input to the circuit 207. As understood the above description, the data output switching circuit of the embodiment comprises the logical circuits 105, 107, 205 and 207, the three state circuits 103, 104, 203 and 204, and the inverter 45. OPERATION An operation of the embodiment according to the present invention will be explained with reference to timing charts shown in Figures 3A to 3C. Figures 3A through 3C include letters A, B and C showing machine cycles, W/B=1 meaning word selection, and W/B=0 meaning byte selection. A0=1 means odd number address selecting operation and A0=0 means even number address selection operation and S0, S1 and S2 represent timings in machine cycles of CPU. For example, the machine cycle A shows writing and reading operations to the data memory 70 or 80 of a word (for example, of a width of 16 bits) in which the head address is of odd number. The machine cycle B shows the writing and reading operations to the byte data memory 70 or 80 including word data (for example, a width of 16 bits) each in which the head address is of even number. The machine cycle C shows writing and reading operations to the byte data memory 70 or 80 including words (for example, a width of 8 bits) each in which the head address is of odd number. The machine cycle D shows the writing and reading operations to the byte data memory including byte data (for example, a width of 8 bits) each in which the head address is of odd number. Figures in the brackets of Figures 3A to 3C are reference numerals seen in Figures 2A and 2B. Now,let us assume that the data memories stored data seen in the following Table I. The machine cycle A seen in Figures 3A, 3B and 3C, is the operational mode that a word data (of a width of 16 bits) is written into or read out of an address in a head odd number address (for example, 0007H). In the state S₀, the data memory specifying address 1110000000000000 is loaded to the CPU buses 0 to 15 , and the address register 20 outputs the address data 0007H when it receives an address latching signal 21 in a later portion of the state S₀. The address register 20, for example, provides an address signal 23 which specifies the address 0003H of the upper byte data memory 80. The incrementer 30 produces an addition signal of an increment signal (or +1 addition signal) 42 and an address signal 23 to specify an address of the lower byte data memory 70. In this case, since it receives both a word/bite specifying signal 91 of "1" and a signal 24 (or the first bit information Q₀ of the address register 20) of "1", the logical circuit 40 produces an increment signal of a logical "1". The incrementer 30 generates to the lower byte data memory 70 an address of the +1 addition signal plus the address for the upper byte data memory being the remaining bit information Q₁ to Q₁₅. Therefore, the lower byte data memory 70 is specified to the address of 1 + 0003H = 0004H. In the state S₁, the data 1111100010101001 (or 951FH in hexadecimal notation expressed from the upper bit order) for writing are loaded onto the CPU buses 0 to 15. In the word data preceded by an odd number address, the byte data at the head address take the lower place and the following byte data at the following address (or the head address plus 1) take the upper place. For example, the data 951F consist of 95H taking the upper place and 1FH taking the lower place. The 1FH data are stored in the upper byte data memory 80 while the 95H data are stored in the lower byte data memory 70. When the logical circuit 300 receives an data switching signal LA (or 24) of a "1" level in the later part of the state S₀, the logical circuit 100 transfers the 95H data on the CPU buses 0 to 15 into the lower byte data memory 70 during the state S₁. While the logical circuit 200, which receives an input switching signal HA (or 24) of a "1" level in the later part of the state S₀, transfers the 1FH data on the CPU buses 0 to 15 to the upper byte data memory 80 during the state S₁. When the gate switching signals 62 and 64 become a "1" level during the state S₁, the three state gates 101 and 201 load the 95H data on the CPU buses 8 to 15 into the lower byte memory buses 0 to 7 (or 102) and the 1F data of the CPU buses 0 to 7 into the upper byte data memory buses 0 to 7 (or 202), respectively. When the clock signal 90 turns "0" to "1" in the later part of the state S₁ and both the lower byte writing signal WML (or 72) and the upper byte writing signal WMH (or 82) turns "1" to "0", the data are stored in the arrangement shown in the following Table II. Byte Address Byte Data Word Address Upper Byte Data Lower Byte Data 0000H 00H 0000H 00H 00H 0001H 00H 0002H 00H 0002H 00H 00H 0003H 00H 0004H 00H 0004H 00H 00H 0005H 00H 0006H 00H 0006H 1FH 00H 0007H 1FH 0008H 95H 0008H 00H 95H 0009H As seen in the Table II, in byte address arrangement of the 951FH data, the 1FH data are stored in the 0007H address and the 95H data are stored in the 0008H address. On the other hand, in word address arrangement of the 951FH data, the 1FH data are stored in the 0006 address of the upper byte data memory 80 and the 95H data are stored in the 0008 address of the lower byte data address 70. When the reading signal 93 becomes a "1" level in the state S₂, the data which has been written in the state S₁ in the address specified during the state S₀ are loaded onto the CPU buses 0 to 15. In case word data (of 16 bits) of a head odd number address are read, the byte data at the head address takes the lower place and the byte data at the following address takes the upper place. During the state S₂, the upper byte memory 80 provides the data onto the CPU buses 0 to 15 , when the reading data output signal OHB (or 208) is at a "1" level. The lower byte data memory 70 provides the data onto the CPU buses 8 to 15 when the data reading output signal OLB (or 108) becomes "1" level. Therefore, the CPU buses 0 to 15 are in 1111100010101001. Next, an operation for reading and writing word data (of 16 bits) into an address preceded by even number address during the machine cycle B will be explained. In the state S₀ of the machine cycle B, the data memory specifying address 0000000000000000 are supplied onto the CPU buses 0 to 15 . When the address register 20 receives the address latching signal 21 in the later part of the state S₀ it outputs the data 0000H as an output signal 22. Also the data 0000H as an address signal 23 (or output bits Q₁ to Q₁₅ ) are output to specify the upper byte data memory 80. The incrementer 30 receives both an incremental signal (or +1 addition signal) 42 from the control signal generator 300 and an address signal 23 from the address register 20 to output an addition signal which is the address data for specifying the lower byte data memory 70. When the word/byte specifying signal 91 is a "1" level and the first bit position information Q₀ or the output signal 24 from the register 20 is in a "0" level, the incremental signal 42 to the incrementer 30 becomes a "0" level. As a result, the lower byte data memory 70 is specified to the same address 0000H as that of the upper byte data memory 80. In the state S₁, the CPU buses 0 to 15 are supplied with the writing data 0101101011001010 (or 535AH in Hexadecimal notation expressed from the upper bit order). In the word data preceded by even addresses, the lower byte data take the lower position and the upper byte data take the upper position. When the logical circuit 100 receives a data switching signal LB or 46 of a "1" level, it transfers the data 5AH of the CPU data buses 0 to 7 to the lower byte memory buses 0 to 7 (or 102). On the other hand, the logical circuit 200 receives a data switching signal HB 46 of a "1" level, it sends the data 53H of the CPU data buses 8 to 15 into the upper byte memory bus 0 to 7 (202). In the later part of the state S₁, when the clock signal turns "0" to "1" and the lower and upper byte data memory writing signals WML (or 72) and WMH (or 82) turn "1" to "0", respectively, the data are written in the byte data memories 70 and 80 in the arrangement as shown in Table III. Byte Address Byte Data Word Address Upper Byte Data Lower Byte Data 0000H 5AH 0000H 53H 5AH 0001H 53H 0002H 00H 0002H 00H 00H 0003H 00H 0004H 00H 0004H 00H 00H 0005h 00H 0006h 00H 0006H 1FH 00H 0007H 1FH 0008H 95H 0008H 00H 95H 0009H 00H As seen in the Table III, in byte address arrangement of the 535AH data, the 5AH data are stored in the address 0001H while the 53H data are stored in the address 0001H. In word address arrangement of the 535AH data, the 5AH data are stored in the address 000H of the lower byte data memory 70, while the 53H data are stored in the address 0000H of the upper byte data memory 80. In the state S₂, when the reading signal 93 turns to "1", the data written during the state S₁ into the address specified during the state S₀ are loaded onto the CPU data buses 0 to 15. In case word data (of 16 bits) of the head even number address are read out, the content of the lower byte data memory 70 occupies the lower position of the word specifying address, while the content of the upper byte data memory 80 occupies the upper position thereof. In the state S₂, when the data output signal OLA (or 106) is in "1", the lower byte data memory 70 provides readout data onto the CPU data buses 0 to 7. Since the data output signal OAH (or 206) is in "1", the upper byte data memory 80 provides readout data onto the CPU data buses 8 to 15. Therefore, the CPU data buses 0 to 15 are in 0101101011001010. Next, it will be expressed that byte (8 bits) data are written into a head odd number address in the machine cycle C. In the state S₀ of the machine cycle C, the address data 1001000000000000 are provided onto the CPU data buses 0 to 15 to specify the data memory. When the address register 20 receives an address latching signal 21 during the later part of the state S₀, it outputs data 0009H. The address signal 23 specifies the address 0004H which is a specifying address for the upper byte data memory 80. The specifying address for the lower byte data memory 70 is an addition value of the increment signal (or +1 addition signal) 42 and the address signal 23. The word/byte specifying signal 91 is in "0" to perform a byte processing and the incrementer 30 receives an increment signal 42 of "0". For this reason, the lower byte data memory 70 is specified to the same address of 0004H as that of the upper byte data memory 80. In the state S₁, the CPU data buses 0 to 15 are provided with the writing data of 0101010111111111 (or 0FFAAHH in Hexadecimal notation). In this case, the data OFFAAH on the CPU data buses 8 to 15 are "1''s which are obtained by precharging the CPU data buses 0 to 15. When byte data are written into the byte data memory 70 or 80, it is stored in only a specified byte data memory address, but an unspecified byte data memory address. When the logical circuit 50 receives a word/byte specifying signal 91 of "0" the first bit signal Q₀ (or 24) of "1" from the address register 20 becomes valid. The OR gate 53 receives the first bit signal Q₀ and the output signal 54 selects the upper byte data memory 80. The logical circuit 200 also receives the bit signal 24 of "1" so that the OAAH data on the CPU data buses 0 to 7 are loaded onto the upper byte data memory buses 0 to 7 (or 202). In the later part of the state S₁, when the clock signal 90 turns "0" to "1", the writing signal WMH (or 82) goes "1" to "0". The data are written into the upper byte data memory 80 in the arrangement as seen in the following Table IV. Byte Address Byte Data Word Address Upper Byte Data Lower Byte Data 0000H 5AH 0000H 53H 5AH 0001H 53H 0002H 00H 0002H 00H 00H 0003H 00H 0004H 00H 0004H 00H 00H 0005H 00H 0006H 00H 0006H 1FH 00H 0007H 1FH 0008H 95H 0008H AAH 95H 0009H AAH As seen in the Table IV, the 0AAH data are stored in the byte address 0009H and the OAAH data are stored in the upper byte date memory 80. In the state S₂, when the reading signal 93 turns to "1", the data written during the state S₁ into the address specified during the state S₀ are read out to the CPU data buses 0 to 7 . In a byte data reading operation, the byte data in a specified address are read out onto the CPU data buses 0 to 7 and the content in a byte specifying address of the byte data memory 70 are read out onto the CPU data buses 8 to 15 . When the three state gate 208 receives a data output signal OHB (or 208) in the state S₂, the upper byte data memory 80 outputs the read data onto the CPU data buses 0 to 7. When the three state gate 108 receives a data output signal OLB (or 108), the lower byte data memory 70 provides the read data onto the CPU data buses 8 to 15 . As a result, the bit information on the CPU data buses 0 to 15 becomes 0101010110101001. Next, the reading and writing operations of byte (8 bits) data into an address preceded by an even address will be explained based on the machine cycle D. When the address data 0110000000000000 occur on the CPU data buses 0 to 15 in the state S₀ of the machine cycle C and an address latching signal 21 is input to the address register 20 in the later part of the stated S₀, the address register 20 provides the data 0006H. The address signal 23 represents the data 0003H and specifies the upper byte data memory 80. The addressing for the lower byte data memory 70 is determined an addition value of an increment signal 42 and an address signal 23. In this case, the word/byte signal is "0" because of the byte processing so that the address specifying the lower byte data memory 70 is 0003H which is the same as that of upper byte data memory 80. In the state S₁, the writing data 10100101111111111 which is referred to OFFA5H in Hexadecimal notation are supplied onto the CPU data buses 0 to 15. In this case, the data on the CPU data buses 0 to 15 are "1" levels which are obtained by precharging the data buses 0 to 15 . In the byte data writing operation, the data are stored into the byte data memory 70 or 80 corresponding to a specified address and new data are not stored into the unspecified byte data memory 80 or 70. The output signal Q₀ becomes valid since the data memory selection circuit 50 receives a word/bite specifying signal 91 of "0". The gate 51 outputs a signal Q₀ of "1" to select the lower byte data memory 70. On the other hand, the gate 53 outputs a signal of "0" but it does not select the upper byte data memory 80. In the state S₁, the logical circuit 100 transfers through the three state gate 101 the data on the CPU data buses 0 to 7 selected by the selection signal 46 from the inverter 45 to the bus 102 of the lower byte data memory 70. In the later part of the state S₁, when the clock signal changes from "1" to "0" and then the writing signal WML (or 72) changes from "1" to "0", the data in arrangement seen in the following Table V are stored in the lower byte data memory 70. Byte Address Byte Data Word Address Upper Byte Data Lower Byte Data 0000 5AH 0000H 53H 5AH 0001 53H 0002 00H 0002H 00H 00H 0003 00H 0004 00H 0004H 00H 00H 0005 00H 0006 A5H 0006H 1FH A5H 0007 1FH 0008 95H 0008H AAH 95H 0009 AAH As seen from the Table V, the A5H data are stored into the byte address 0006 which corresponds to the word address of 0006H in the lower byte data memory 70. In the state S₂, when the reading signal 93 is "1", the data written during the state S₁ in the address specified during the state S₀ are read onto the CPU data buses 0 to 7. In the byte data reading operation, the CPU data buses 0 to 7 receives the byte data read from a specified address while the CPU data buses 8 to 15 receives the content from a word address as a byte specifying address of the byte data memory 70 or 80. Therefore, the data output signal OLA (or 106) becomes "1"in the state S₂ so that the data read out onto the CPU data buses 0 to 7. Then the data output signal OHA (or 206) changes into "1", the upper byte data memory 80 outputs the read data onto the CPU data buses 8 to 15. As a result, the CPU data buses 0 to 15 are in 1010010111111000. As described above, the microprocessor according to the present invention includes a word data memory which comprises an upper byte data memory and an lower byte data memory. The improved microprocessor also has an incrementer which produces an address for specifying the lower byte data memory and which enable an access operation by only one time addressing. The microprocessor of this invention is applicable to CPU memory systems which require high speed processing.

Claims: A microprocessor comprising a CPU-data bus (10) having lower n-bit data lines (0-7) and higher n-bit data lines (8-15) for transmitting data (writing or reading data) and an address information consisting of a first bit (D₀) having a first and second signal level and address specifying data (D₁-D₁₅), wherein first data consist of 2n-bits and second data consist of n-bits, an address register (20) for storing all bits of said address information on said data bus (10) in response to a first level of an address latching signal (21) having said first and second signal level, a first logical circuit (40) for receiving a word/byte switching signal (91) which indicates the number of bits of writing data or reading data of said first or second data, respectively, and for receiving said firt bit (D₀) stored in said address register (20), and outputting an incrementing signal when said word/byte switching signal (91) has a level indicating said first data and said first bit (D₀) has said second level, an incrementer (30) receiving said address specifying data (D₁-D₁₅; A₀-A₁₄) and incrementing said address specifying data (D₁-D₁₅) in response to said incrementing signal, a first data memory circuit (70) forming a first byte-portion of a word data memory and receiving said second address specifying data (A₀-A₁₄; D₁-D₁₅) received from said incrementer (30) and storing a first byte part of said first data or all of said second data at an address specified by said second address specifying data, a second data memory circuit (80) forming a remaining byte-portion of said word data memory and receiving said address specifying data (A₀-A₁₄; D₁-D₁₅) received from said address register (20) and storing a remaining byte part of said first data or all of said second data at an address specified by said address specifying data, a second logical circuit (25, 50, 60, 71; 81) for receiving a writing signal (92), said first bit (D₀) and said word/byte switching signal (91), wherein said first and second memory circuits (70, 80) being activated and being supplied with said address specifying data (D₁-D₁₅; A₀-A₁₄) when said word/byte switching signal (91) has a level indicating said first data, said first bit (D₀) has said first level and the writing signal (92) is activated, said first and second memory circuits (70, 80) being activated and said second memory circuit (80) being supplied with said address specifying data (D₁-D₁₅; A₀-A₁₄), said first memory circuit (70) being supplied with incremented address specifying data (D₁-D₁₅; A₀-A₁₄) when said word/byte switching signal (91) has a level indicating said first data, said first bit (D₀) has said second level and the writing signal (92) is activated, said first memory circuit (70) being activated and being supplied with said address specifying data (D₁-D₁₅; A₀-A₁₄) when said word/byte switching signal (91) has a level indicating said second data, said first bit (D₀) has said first level, and the writing signal (92) is activated, said second memory circuit (80) being activated and being supplied with said address specifying data (D₁-D₁₅; A₀-A₁₄) when said word/byte switching signal (91) has a level indicating said second data, said first bit (D₀) has said second level and the writing signal (92) is activated, a data input control circuit (400) for selectively transmitting said first or said second data on said lower and higher bit data lines to said first and second data memory circuits (70, 80) in response to the signal level of said first bit (D₀), wherein said data input control circuit (400) enables to write data into said first and second data memory circuits (70, 80) in response to the result produced by the second logical circuit, a data output control circuit (500) for selectively supplying data from said first and second data memory circuit (70, 80) to said lower and said higher bit data lines in response to the signal level of said first bit (D₀) and the activating of a reading signal (93), wherein said data output control circuit (500) enables to supply data from said first and second data memory circuits (70, 80) when said reading signal (93) is activated, wherein said first level of said address latching signal (21) is transmitted at least one clock period before said first level of said writing signal (92) or said first level of said reading signal (93), characterized in that the microprocessor further comprises a writing signal line for transferring a writing signal (92) having a first and second signal level, wherein the first signal level of the writing signal (92) corresponds to the activated writing signal (92), and a reading signal line for transferring a reading signal (93) having a first and second signal level, wherein the first signal level of the reading signal (93) corresponds to the activated reading signal (93) wherein said writing and reading signals (92, 93) have their second level when said address latching signal (21) has its first level, whereby said data input control circuit (400) and said data output control circuit (500) are disabled, and said first level of said address latching signal (21), said first level of said writing signal (92) and said first level of said reading signal (93) are sequentially transmitted in correspondence to a first, second and third clock period, respectively. A microprozessor according to claim 1, characterized in that the data input control circuit (400) comprises a first logical means (100) connected to the CPU data bus (10) for selectively transmitting the lower bit data loaded on the CPU data bus (10), first gating means (101) connected to the first logical means (100) and to the first data memory circuit (70) for transmitting the lower bit data from the first logical means (100) to the first data memory circuit (70), a second logical circuit (200) connected to the CPU data bus (10) for transmitting the higher bit data loaded on the CPU data bus (10) and second gating means (201) connected to the second logical means (200) and to the second data memory circuit (80) for selectively transmitting the higher bit data from the second logical circuit (200) to the second data memory circuit (80). A microprocessor according to claim 1, characterized in that the data output control circuit (500) comprises a first gating means (103) connected to the first data memory circuit (70) for transmitting the lower bit data to the CPU data bus (10) and a second gating means (203) connected to the second data memory circuit (80) for transmitting the higher bit data to the CPU data bus (10).

Inventors: YOKOUCHI HIROSHI, YOKOUCHI, HIROSHI, YOKOUCHI, HIROSHI C/O OKI ELECTRIC IND.CO.,LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1988
Main classification: G06F12
IPC codes: G06F15, G06F12