Image signal processor

Abstract: An image signal processor which comprises a memory device (9) for storing an image signal representative of a picture during one field period; an operating unit (18) for generating a READ-OUT command necessary to read out contents stored in the memory device from the memory device; a selector (SW 1) for selectively switching the memory device (9) between a WRITE-IN READY condition and a READ-OUT READY condition; and a switching control unit (5) for generating a control signal necessary to control the switching operation of the selector(SW 1). The switching control unit is adapted to receive the READ-OUT command and a vertical synchronizing signal included in a composite video signal. The selector performs the switching operation in synchronism with the initial vertical synchronizing signal applied immediately after the READ-OUT command has been inputted.

Description: BACKGROUND OF THE INVENTION (Field of the Invention) The present invention generally relates to an image signal processor and, more particularly, to the image signal processor of a type used in connection with a video output device such as, for example, television receiver set, video tape player (VTR) or video camera for storing a video signal outputted from the video output device and for subsequently writing the stored video signal in a graphic memory in a personal computer in the form of a still or frozen picture. (Description of the Prior Art) With the advent of widespread use of semiconductor memories, numerous image signal processors of the type referred to above have been proposed and made commercially available. When the image signal descriptive of one frozen picture is read in the personal computer through the image signal processor, an operator of the personal computer can perform an image analysis of the frozen picture or an image processing such as enlargement or reduction of the frozen picture, or extraction or highlighting of one or more portions of the frozen. According to the prior art, the image signal processor is provided with a memory device for the storage of a digitized image signal. When a WRITE-IN control signal or a READ-OUT control signal is supplied to the memory device, the image signal can be inputted to or outputted from the memory device, respectively. Generally in the prior art image signal processor, when the image signal stored in the memory device is desired to be read out from the memory device for the transfer to the personal computer, the following process takes place. Specifically, after the image signal representative of one frozen picture has been written in the memory device in the image signal processor, the image signal processor issues to the personal computer a signal notifying the personal computer that the image signal has been stored in the memory device. The personal computer subsequently interrogate the image signal processor if the image signal stored in the memory device can be read out from the memory device. The image signal processor so interrogated then issues to the personal computer a READY signal notifying the personal computer that the image signal in the memory device is ready to be read out therefrom. After this interrogation, the image signal is transferred onto the personal computer. The image signal so read out from the memory device is then stored in an internal graphic memory in the personal computer. According to the prior art, in order for the image signal stored in the memory device to be transferred onto the personal computer, a plurality of interrogations has to be made between the image signal processor and the personal computer, requiring a relatively long time to complete the transfer of the image signal to the personal computer. US-A-4361849 discloses a video disc vari-speed playback system including a video disc player having two fields of buffer storage for implementing special effects. A video signal recovered from a disc record is directed into respective ones of the buffer storages for subsequent replay in particular sequences. A fixed memory device, containing a plurality of sequences of preprogrammed data words, each sequence defining a particular player function, controls the operable mode of the respective buffer storages. The preprogrammed sequences are addressed by a binary counter responsive to the vertical synchronization components of the signal recovered from the disc record. SUMMARY OF THE INVENTION Accordingly, the present invention has been devised with a view to substantially eliminating the above discussed problems inherent in the prior art image signal processors and has for its essential object to provide an improved image signal processor of a type capable of transferring at high speed the image signal stored in the memory device. In order to accomplish these objects, the present invention provides an improved image signal processor with the features of appended claim 1. In the image signal processor according to the present invention, when the image signal stored in the memory means is to be read out from the memory means by the operating means, the READ-OUT command is supplied from the operating means to the switching control means. The switching control means is adapted to receive the vertical synchronizing signal included in the composite video signal supplied to the image signal processor. Accordingly, when the READ-OUT command is supplied from the operating means to the switching control means, the control signal can be outputted from the switching control means in synchronism with the initial vertical synchronizing pulse applied immediately after the READ-OUT command has been inputted. The control signal outputted from the switching control means in this way is applied to the switching means to control the switching operation performed by the switching means. In response to the control signal, the switching means selectively bring the memory means into the WRITE-IN READY condition and the READ-OUT READY condition. Accordingly, in the image signal processor according to the present invention, it is possible to selectively bring the memory means into the WRITE-IN READY condition and the READ-OUT READY condition in synchronism with the vertical synchronizing signal included in the input composite video signal by causing the operating means to apply the READ-OUT command. Also, since the outputting of the READ-OUT command from the operating means is sufficient for the memory means to be brought into the READ-OUT READY condition, the image signal stored in the memory means can be read out therefrom at high speed. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become clear from the following description taken in conjunction with preferred embodiments thereof with reference to the accompanying drawings, in which like parts are designated by like reference numerals and in which: Fig. 1 is a schematic circuit block diagram showing an image signal processor according to a first embodiment of the present invention; Fig. 2 is a timing chart used to explain the operation of a field memory device used in the image signal processor during the WRITE-IN mode; Fig. 3 is a timing chart used to explain the operation of the field memory device during the READ-OUT mode; Fig. 4 is a timing chart used to explain the operation of a selector switch used in the image signal processor; Fig. 5 is a timing chart illustrating a READ-OUT control signal outputted from a READ-OUT control circuit used in the image signal processor. DETAILED DESCRIPTION OF THE EMBODIMENTS A. Still Picture Data Write/Read System: Referring first to Fig. 1, there is illustrated a circuit block diagram of a still picture read/write system 1. The system 1 shown therein includes an input terminal 2 adapted to be connected with a video output device, for example, a television receiver set or a video tape player, and to which a composite video signal is applied from the video output device, and a connector 4 adapted to be connected with an address bus and a data bus of a personal computer 3. The composite video signal inputted to the input terminal 2 is fed to a luminance signal separator 6 operable to separate from a luminance signal Y which is in turn applied to a color difference signal demodulator 7 to provide B-Y, R-Y and G-Y color difference signals. Both of the luminance signal Y from the luminance signal separator 6 and the three color difference signals from the color difference signal demodulator 7 are subsequently fed to a color difference/primary color converter 8 operable to convert the color difference signals into three primary color signals, that is, B, R and G signals, which are representative of the three primary colors, blue, red and green. The primary color signals are in turn supplied to a field memory device 9 by which the primary color signals are digitized for the storage therein in the form of a still picture corresponding to one field. The field memory device 9 includes three field memories 10, 11 and 12 for the respective B, R and G signals, each of said field memories 10 to 12 employing a serial access input and output system. Each of the field memories 10 to 12 is of a memory construction having 320 rows by 700 columns, a memory area of a size enough to accommodate one picture, a one-line buffer memory area and a row address counter. Each of these field memories 10 to 12 when applied with a serial clock signal as will be described later is incrementally shifted a memory cell in a direction parallel to the columns and, when applied with an increment pulse signal, shifted one line in a direction parallel to the row. For the purpose of the description of the preferred embodiment of the present invention, each memory cell of each of the field memories 10 to 12 is assumed to be capable of storing one bit. The composite video signal applied to the input terminal 2 is also supplied to a sync separator 13 operable to separate horizontal and vertical synchronizing signals from the composite video signal. The outputs from the sync separator 13 is supplied to the color difference signal demodulator 7 for clamping and also to a WRITE-IN control circuit 14. The vertical synchronizing signal separated from the composite video signal by the sync separator 13 is also applied to a control signal generator 15 as will be described later. The WRITE-IN control circuit 14 is adapted to receive through a divider 17 a clock signal which has been generated from a WRITE-IN clock signal oscillator 16 having an oscillating frequency of, for example, 28.636 MHZ. The WRITE-IN control circuit 14 is operable to synthesize a plurality of WRITE-IN control signals on the basis of the synchronizing signals, outputted from the sync separator 13 and the clock signal generated from the clock signal oscillator 16. These WRITE-IN control signals are supplied to the field memory device 9 through a READ-OUT/WRITE-IN mode selector switch SW1. The B, R and G signals outputted from the color converter 8 are digitized and written in the field memory 9 on the basis of the WRITE-IN control signals. The details of the WRITE-IN operation will be described later. B. Still Picture Data Reading The system 1 has an address bus B1 and a data bus B2 adapted to be connected with the address bus and the data bus of the personal computer 3 through the connector 4. Output signals from the personal computer 3 are supplied through the respective buses B1 and B2 to a READ-OUT control circuit 18 and also to the control signal generator 15. The READ-OUT control circuit 18 is also adapted to receive from the personal computer 3 via the connector 4 a clock signal having a frequency of, for example, 4 MHz which is used within the domain of the personal computer 3. The READ-OUT control circuit 18 is operable to synthesize a plurality of READ-OUT control signals on the basis of the outputs from the personal computer 3 and the clock signal. These READ-OUT control signals are supplied to the field memory device 9 through a READ-OUT/WRITE-IN mode selector switch SW1. When these READ-OUT control signals are supplied to the field memory device 9, B, R and G color data stored in the respective field memories 10 to 12 associated respectively with the B, R and G signals are sequentially outputted to a primary color signal selector switch SW2. The primary color signal selector switch SW2 is controlled by a switching control signal supplied from the personal computer 3 to sequentially output blue color data, red color data and green color data in a specific order, for example, in the order specified above, to a serial/parallel converter 19. The serial/parallel converter 19 is operable to convert each of the color data into a respective parallel data which is in turn outputted to the personal computer 3 through the data bus B2 for the storage in a graphic memory (not shown) built in the personal computer 3. After the image signal is so stored in the graphic memory in the manner as hereinabove described, the image can be processed by operating the personal computer 3 in a usual manner well known to those skilled in the art. Fig. 2 illustrates a timing chart used to explain the operation of the field memory device 9. Fig. 2(1) illustrates a waveform of a portion of the composite video signal corresponding to one horizontal scanning period 1H. A time span between timing t0 and timing t1 represents a horizontal blanking period, and a time span T1 between timing t1 and timing t2 represents a duration of a video signal carrying picture information. (See, Fig. 2(2)). In the illustrated instance, a serial clock signal SC such as shown in Fig. 2(3) is applied to the field memory device 9 to which the composite video signal of the waveform described above is supplied. Therefore, during a WRITE-IN period Tw within the duration T1 of the video signal, the analog video signal is digitized and written in the field memory device 9 in the form of a serial data. Hereinafter, the READ-OUT operation of the field memory device 9 will bed described. The B, R and G color data written, i.e., stored, in the field memory device 9 are supplied to the personal computer 3 through the data bus B2. The B, R and G color data written in the respective field memories 10 to 12 associated respectively with the B, R and G signals are sequentially switched by the selector switch SW2 in the order of the blue color data followed by the red color data followed by the green color data and are in turn outputted to the data bus in the personal computer 3 after having been converted by the serial/parallel converter 19 into parallel color data. More specifically, when the data written in the field memory device 9 are to be read out, the converter 19 converts the data, serially supplied from the field memory 10 for the B signal, from the very beginning of such serially transmitted data into 8-bit parallel data which are then outputted to the personal computer 3. When all the blue color data written in the field memory 10 have been read out in this manner, 8-bit data are read out from the very beginning of the field memory 11 for the R signal. Similarly, 8-bit data are read out from the very beginning of the field memory 12 for the G signal. After all of the color data stored in the field memory device 9 have been completely read out in this way, the reading of one still picture is completed. (See Fig. 3). It is eventually pointed out that the reason for the employment of such a reading method is because the data bus in the personal computer 3 has only 8-bit capacity. Fig. 4 illustrates a timing chart used to explain the principle of operation of the system in the illustrated instance. Referring to Fig. 4 in combination with Figs. 1 to 3, the operation of the selector switch SW1 will now be described. The selection between the READ-OUT mode and the WRITE-IN mode in the image signal processor 1 is accomplished by the selector switch SW1. More specifically, when the selector switch SW1 is in position to set the processor in the WRITE-IN mode, the WRITE-IN control signals outputted from the WRITE-IN control circuit 14 are suppled to the field memory device 9. On the other hand, when the selector switch SW1 is moved to set the processor in the READ-OUT mode (on the side of the personal computer 3), the READ-OUT signals outputted from the READ-OUT control circuit 18 are supplied to the field memory device 9. When the selector switch SW1 is in position to set the processor in the READ-OUT mode, the READ-OUT control circuit 18 supplies six types of READ-OUT control signals including, for example, a READ-OUT/WRITE-IN operation control signal RAS, the previously mentioned serial clock signal SC, a refresh controls signal REF, an enable signal WE, an increment signal INC and a row reset signal RCR, as shown by (1) to (6) in Fig. 5, respectively, to the field memory device 9 through the selector switch SW1 so that the data stored in the field memory device 9 can be read out therefrom. By way of example, during a period between timing ts and timing tn shown in Fig. 5, the red color data for each still picture are read out from the field memory 11 for the R signal. During a period between timing ta and timing tb, the red data for one row are serially read out in response to the serial clock signal SC and the refresh control signal REF. The switching operation of the selector switch SW1 is controlled by a switching control signal A outputted from the control signal generator 15. More specifically, when the switching control signal A is in a low level state, the WRITE-IN mode is established, but when it is in a high level state, the READ-OUT mode is established. (See the waveform (3) shown in Fig. 4). The control signal generator 15 comprises, for example, a D-type flip-flop and is operable to output not only the control signal A, but also a clock switching signal used to control the cycle of division of the divider 17. As hereinbefore described, the vertical synchronizing signal V outputted from the sync separator 13 is applied to the control signal generator 15. (See the waveform (2) shown in Fig. 4). Assuming that the processor 1 is set in the WRITE-IN mode, and in the event that a command necessary to set the processor 1 in the READ-OUT mode is generated from the personal computer 3, a high level control signal D is supplied from the personal computer 3 to the control signal generator 15. By way of example, when the control signal D is rendered to be in a high level state at a timing t0 as shown by the waveform (1) in Fig. 4, the switching control signal A is set up to a high level state in response to the set-up of one of the vertical synchronizing pulses V, which has been applied immediately after the set-up of the control signal D to the high level state, the high level state of the switching control signal A being maintained subsequently. As the switching control signal A is so set up to the high level state, the selector switch SW1 is brought in position to set the processor 1 in the READ-OUT mode, thereby permitting the data in the field memories 10 to 12 to be read out sequentially. More specifically, during a period from a timing t2 to a timing t3 shown in Fig. 4, the blue color data are first supplied to the personal computer 3. During a subsequent period from the timing t3 to a timing t4, and during a period from the timing t4 to a timing t5, the red color data and the green color data are successively and sequentially supplied to the personal computer 3, respectively. In this way, at the timing t5, the still picture data for one still picture which have been written in the field memory device 9 are completely read out from the field memory device 9 and transferred to the personal computer 3. As hereinabove described, the switching between the WRITE-IN and READ-OUT modes can be accomplished when the control signal D issued from the personal computer 3 is brought in a high level state. The timing at which this switching is effected is synchronized with the set-up of one of the vertical synchronizing pulses which is applied immediately after the control signal D has been brought in the high level state. Specifically, the switching onto the READ-OUT mode is carried out during a vertical blanking period TB as shown in the waveform (7) in Fig. 4. Upon the completion of the read-out of the image signal, the personal computer 3 causes the control signal D to be brought in a low level at a timing t6 wherefore the switching control signal A, which is an output from the control signal generator 15, is brought in a low level state in response to the set-up of another one of the vertical synchronizing pulses V which is applied immediately thereafter, i.e., at a timing t7 shown in Fig. 4, causing the selector switch SW1 to set the processor 1 in the WRITE-IN mode. It is to be noted that the timing t7 is immediately after the color data in the field memory device 9 have been read out from the field memory device 9, no data is written in the field memory device 9. Accordingly, after the timing t7, the image signal subsequently inputted can be written again in the field memory device 9 in the form of a still picture. The reason that the switching onto the READ-OUT mode is carried out during the vertical blanking period TB is for the purpose that the video signal corresponding to one picture can be accurately read out. If this switching is not effected during the vertical blanking period TB, it may happen that the picture being reproduced on a screen will be switched over to a different picture without being completely reproduced. The time required to complete the read-out of one picture is determined by the timing at which the control signal D from the personal computer 3 is brought in the high level state. More specifically, since the start and end of the period during which the information read-out is carried out lie within the time span between the neighboring vertical blanking periods, a wait time occurs before and after the read-out operation. In any event, in the illustrated instance, the time required to complete the information read-out may be 0.2 second on an average. The time required to complete the write-in operation which takes place when the processor 1 is set in the WRITE-IN mode corresponds to one field period, that is, 1/60 second. As hereinbefore described, upon the completion of the read-out operation, the processor 1 is switched onto the WRITE-IN mode to permit the color data corresponding to one still picture to be again written in the field memory device 9. Also, the timing at which the processor 1 is switched onto the WRITE-IN mode is carried out during the vertical blanking period. Accordingly, the personal computer 3 can render the control signal D to be in a high level state at any timing. More specifically, regardless of when the personal computer 3 generates a command required to bring the control signal D into the high level state, the color data corresponding to one still picture can be always read out accurately. Moreover, the switching of the image signal processor 1 onto the READ-OUT mode can be reliably accomplished without interrogations being carried out such as in the prior art processor. Accordingly, the still picture represented by the video signal can be written at high speed in the graphic memory device built in the personal computer. As hereinbefore described, in the image signal processor according to the present invention, when the memory means is desired to be brought in the READ-OUT READY condition, it can be accomplished merely by causing the operating means to output the READ-OUT command. Accordingly, the necessity of the interrogation to be frequently done between the processor and the operating means such as required in the prior art processor can be minimized, and the read-out operation of the memory means can be carried out at high speed. Moreover, since the timing at which the switching between the WRITE-IN and READ-OUT modes takes place in synchronism with the vertical synchronizing signal and without relying on the timing at which the READ-OUT command is issued, the video signal corresponding to one field period can be always read ou accurately.

Claims: An image signal processor for storing a video signal outputted from a video output device and for transferring the stored video signal to a personal computer, comprising: input means (6, 7, 8) for receiving a composite video signal, said composite video signal having a vertical synchronizing signal; memory means (9) for storing a plurality of image signals representative of a picture during one field period of said composite video signal; read operating means (18) for generating READ-OUT control signals necessary to read out said plurality of image signals stored in said memory means in response to a READ-OUT command signal received from said personal computer; write operating means (13, 14, 16) for generating WRITE-IN control signals necessary to write said plurality of image signals into said memory means; switching means (SW1), operatively connected to said read operating means and said write operating means for receiving said READ-OUT control signals and said WRITE-IN control signals and for selecting either said WRITE-IN control signals or said READ-OUT control signals to be outputted to said memory means; and switching control means (15) for generating a control signal (A) to control the selection of said switching means; said switching control means receiving said READ-OUT command signal and said vertical synchronizing signal and producing said control signal (A) in synchronism with the initial vertical synchronizing signal received immediately after reception of said READ-OUT command signal. An image signal processor according to claim 1, wherein said input means comprises: luminance signal separating means (6) for separating said composite video signal into a luminance signal and a color signal; color difference signal demodulating means (7) for developing first, second and third color difference signals from said color signal; and primary color converting means (8) for converting said first, second, and third color difference signals into first, second, and third primary color signals. An image signal processor according to claim 2, wherein said memory means comprises first, second, and third field memories (10, 11, 12) for storing said first, second, and third primary color signals, respectively. An image processor according to claim 2, wherein said write operating means comprises: a WRITE-IN clock signal oscillator (16) for developing a clock signal; synch separating means (13) for developing synchronizing signals in response to said luminance signal from said luminance signal separating means; and a WRITE-IN control circuit (14) for generating said WRITE-IN control signals in response to said clock signal and said synchronizing signals. A method for storing a video signal outputted from a video output device in an image signal processor and for transferring the stored video signal to a personal computer, comprising the steps of: receiving a composite video signal, said composite video signal having a vertical synchronizing signal; storing a plurality of image signals representative of a picture during one field period of said composite video signal in a memory (9); generating READ-OUT control signals for controlling a reading out of said plurality of image signals stored in said memory in response to a READ-OUT command signal received from said personal computer; generating WRITE-IN control signals for controlling a writing of said plurality of image signals into said memory; selecting either the READ-OUT control signals or the WRITE-IN control signals to be applied to the memory through a switch (SW1), and causing the selection of the READ-OUT control signals to take place in synchronism with the initial vertical synchronizing signal received immediately after reception of said READ-OUT command signal from said personal computer.

Inventors: ABUMI TAKAO, ABUMI, TAKAO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1988
Main classification: H04N1
IPC codes: H04N5, H04N1