Digital phase-locked loop system

Abstract: A digital phase-locked loop system having an oscillator (4) which generates a clock signal of a stationary frequency, a frequency divider (7) which frequency-divides the clock signal to produce a phase-locked loop clock signal, a phase difference detector (304, 305) which detects a phase difference between an input signal and the phase-locked loop clock signal and outputs a phase difference detection signal, and a frequency dividing rate setting means (5, 6) to set a frequency dividing rate corresponding to the phase difference in response to the phase difference detection signal and apply the rate to the frequency divider (7). Frequency division constant setting means (12) to supply a predetermined frequency dividing rate to the frequency divider (7); and frequency dividing rate switching means (11) to supply the frequency divider (7) with an output from the frequency dividing rate setting means (5, 6) in response to the phase difference detecting signal when the phase difference is detected and to supply the frequency divider (7) with an output from the frequency dividing constant setting means (12).

Description: BACKGROUND OF THE INVENTION This invention relates to a digital phase-locked loop system in which a phase-locked loop (PLL) is composed of digital circuit elements. Many types of digital phase-locked loop systems have been released recently. These digital phase-locked loop systems have a phase-locked loop composed of digital circuit elements. In comparison with analog type systems, such digital type systems have advantages that scatter due to parts used is insignificant and that desired characteristics can be obtained without necessity of adjustment. Generally, on the other hand, in digital phase-locked loop systems, an output from a stationary oscillator is frequency-divided and outputted as an output from the loop, and therefore the phase-locked loop can be operated only by input frequencies in the range below one several-tenth of a maximum frequency for operating a logical circuit element incorporated therein. Furthermore, if the input frequency is increased, a frequency-dividing rate becomes smaller, resulting in rougher quantization and worse loop characteristics. Especially in digital phase-locked loop systems utilizing input frequencies in the range of a fraction of a highest operating frequency of the logical circuit element, influence of characteristics of the logical circuit element itself, especially influence of delay characteristic, is significant as well as the influence of the quantization error and thus, adoption of a complicated circuit composition is difficult. A digital phase-locked loop system having the features defined in the preamble of appended claims 1 and 4 is known from the US patent US-A-4,538,119. Fig. 18 shows an example of a similar phase-locked loop system, having also the features of the preamble of appended claim 1, for operating at a fraction (1/N, N: a positive integer) of a frequency of a traditional stationary oscillator (OSC) 4. Phase difference between input signal PBSG and phase-locked loop clock signal PLLCK is detected as counted value of a counter 1. Clock pulse MCK which is an output of the stationary oscillator 4 is shown in Fig. 19 (1), input signal PBSG in Fig. 19 (2), and phase-locked loop clock signal PLLCK in Fig. 19 (3). Signal Q A from an output terminal Q of the D-type flip-flop 3 is shown in Fig. 22 (4). Clock pulse MCK, input signal PBSG, and output signal Q A of a D-type flip-flop 3 are applied to an AND gate G1 and an output of the AND gate G1 is supplied to a clock input terminal CK of the counter 1. Output signal CNTOUT of the counter 1 is shown in Fig. 19 (5). Output signal U of a frequency divider 7 is applied to a clock input terminal CK of a D-type flip-flop 8 and is also applied to the clock input terminal CK of the D-type flip-flop 3 through an inversion circuit N1 and then drawn out as phase-locked loop clock signal PLLCK. Output of an AND gate G2 is applied to the counter 1 and register 5 as reset signal RESET. The reset signal RESET is as shown in Fig. 19 (6). In Fig. 19, there exists a phase difference in the time interval between a step-up edge "a" of the input signal PBSG and a step-up edge "b" of the phase-locked loop clock signal PLLCK and this time interval is counted by the counter 1. The input signal PBSG, output signal Q A from the D-type flip-flop 3 which latches the input signal PBSG at the step-up or leading edge of the phase-locked loop clock signal PLLCK, and clock pulses MCK from the stationary oscillator 4 are applied to the AND gate G1 before the clock input into the counter 1, by which the counter 1 provided with the output of the AND gate 1 counts the time between the edges a -b. The counter 1 counts the pulses from the AND gate G1 until reset signal RESET from the other AND gate G2 is inputted. Output from a terminal Q of the D type flip-flop 8 which latches the output from a terminal Q of the D type flip-flop 3 at the step-up edge of the signal U and the output from the terminal Q of the D type flip-flop 3 are applied to the AND gate G2 and the signal CNTOUT which represents the counted value of the counter 1 is latched by the register 5 at the step-up edge of the reset signal RESET from the AND gate G2. Then the counter 1 is reset in response to the reset signal RESET and set at the step-up edge the next input signal PBSG, and the next counting operation is started. Phase difference signal I outputted from the register 5 is shown in Fig. 19 (7), which is applied to a decoder 6 and decoded. Load signal E outputted by the decoder 6 is as shown in Fig. 19 (8), which signal is loaded in the frequency divider 7 as a frequency dividing rate for the frequency divider 7. In this way, the clock pulse MCK from the stationary oscillating circuit 4 is frequency-divided by a value represented by the phase difference signal I indicative of the difference between the input signal APBSG and phase-locked loop clock signal PLLCK, and then a frequency dividing rate of the frequency divider 7 generating the phase-locked loop clock signal APLLCK is changed to another one, so that phases of the input signal PBSG and phase-locked loop clock signal PLLCK are kept so as to agree with each other. The frequency dividing rate of the frequency divider 7 is N when the phases of the input signal PBSG and phase-locked loop clock signal PLLCK agree, and the rate becomes N + 1 or N - 1 depending on the degree of the phase difference so that the phases agree with each other. For instance, the decoder 6 at N = 8 functions to decode to load signal E for the frequency divider 7 to obtain the frequency dividing rate of the frequency divider 7 corresponding to the phase difference signal I. The frequency divider 7 gets loaded with the load signal E representing the frequency dividing rate applied from the decoder 6 in response to load clock signal F. This load clock signal F is generated as shown in Fig. 19 (9) by the logical circuit 9 when the output signal U of the frequency divider 7 represents a specified value. In Fig. 19, where N = 8, and since phase difference exists between the time points a and b, load signal E representing frequency division ratio 9 is applied to the frequency divider 7 from the decoder 6 at the time point c, and the phase difference is corrected to zero at the time point d. According to the prior art as shown in Figs. 18 and 19, when the input signal APBSG has a constant cycle as shown in Fig. 19, a normal operation is possible. However, when the input signal PBSG has a modulated waveform as shown in Fig. 20 (1), the cycle of the input signal PBSG changes to longer or shorter one. The phase-locked loop clock signal PLLCK at this time is shown in Fig. 20 (2). When phase difference is caused to it, it may be corrected by the length of the cycle of the input signal PBSG. Fig. 20 (3) shows the output signal Q A of the D type flip-flop 3, Fig. 20 (4) shows the output signal CNTOUT of the counter 1, Fig. 20 (5) shows the reset signal RESET, Fig. 20 (6) shows the phase difference signal I outputted by the register 5, Fig. 20 (7) shows the load signal E representing a frequency dividing rate of the decoder 6, and Fig. 20 (8) shows the load clock signal F from the logical circuit 9. In this Fig. 20, the phase difference at the point of time al is corrected at the points of time b1, c1, and d1 in the same way and therefore the phase becomes reversed in polarity at the point of time b1 which gives adverse influence on the phase-locked loop characteristics. SUMMARY OF THE INVENTION It is the object of the invention to provide a digital phase-locked loop system which is arranged to correct the frequency dividing rate of a frequency divider even then properly when the cycle of the input signal changes, so that the phase of the output signal of the system agrees with that of the input signal. This object is solved by the digital phase-locked loop systems according to the teachings of appended independent claims 1 and 4, respectively. It is the common technical, inventive concept of these two systems that they comprise a frequency dividing rate switching means, switching between two different frequency dividing rates. According to the first aspect of the invention, the frequency divider is supplied by said switching means at first with a first frequency dividing rate corresponding to a detected phase difference, and is then supplied with a second frequency dividing rate which is either a constant value or a value outputted by a frequency dividing rate adjusting means. According to the second aspect of the invention, the frequency divider is supplied by the switching means with one of two frequency dividing rates in dependence of one of two speed modes of the input signal. When the cycle of the input signal changes not due to a frequency change, but due to a change in the pulse width and the pulse interval, then the digital phase-locked loop system functions as follows: it sets a frequency dividing rate by the output from the frequency dividing rate setting means when a phase difference occurs, corrects this frequency dividing rate once or more by a predetermined number of times, and thereafter gives a predetermined frequency division constant from a frequency division constant setting means, such as the frequency division rate at normal time, to the frequency divider so that the frequency divider rate is not corrected. This enables the system to minimize the deviation of phases between the input signal and the phase-locked loop clock signal. When the phase changes because of frequency changes, even wide frequency changes, a frequency dividing rate corresponding to the phase difference between the input signal and the phase-locked loop clock signal is set by the frequency dividing rate setting means and the frequency divider is operated according to it. Such a frequency dividing rate setting means can count the time interval between a leading edge of the input signal and a leading edge of the phase-locked loop clock signal and set the frequency dividing rate. The frequency dividing rate adjusting means detects changes in the minimum repetitive frequency of the input signal PBSG by shifting with the clock signal from the oscillator, for instance, and determines the frequency dividing rate based on the frequency components of this input signal. The frequency dividing rate switching means first operates the frequency divider in accordance with the frequency dividing rate which is set by the frequency dividing rate setting means when a phase difference is detected, and then operates the same at the frequency dividing rate which is set by the frequency dividing rate adjusting means. Therefore, a simple composition can cope with wide changes in frequencies of input signals with favorable characteristics without significant deviation in phase between the input signals and phase-locked loop clock signals, and it can prevent unlocking of the phase-locked loop. Phase changes may also arise when it is necessary to cope with at least two types of input signals reproduced in different speed modes. In this case, the arrangement is, according to claim 4, such that when a phase difference detection signal is provided, the phase difference detection signal is decoded by one of at least two decoders and loaded as a frequency dividing rate value of the frequency divider which generates the phase-locked loop clock. Here, the decoder actually being used is switched according to the speed mode of the input signal to the other one having different decoding characteristics. For instance, at DAT, a decoder is selected that makes much correction of the frequency dividing rate when the phase deviation amount is large, but little correction when the phase deviation amount is small in normal mode for usual reproduction, and a decoder to correct the frequency dividing rate approximately in proportion to the phase deviation amount is selected in a search mode due to large fluctuation of speed. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: Fig. 1 is a block diagram of a first embodiment of this invention; Fig. 2 is a waveform diagram to explain the operation of the embodiment as shown in Fig. 1; Fig. 3 is a block diagram of a second embodiment of this invention; Figs. 4 and 5 are waveform diagrams showing the input signal PBSG and output signal of shift registers 12 and 13; Figs. 6, 7, and 8 are waveform diagrams to explain operation of the embodiment as shown in Fig. 3; Fig. 9 is a block diagram showing electrical composition of a phase-locked loop system of a third embodiment of this invention; Figs. 10 and 11 are timing charts showing signal waveform at each part of the said system; Fig. 12 is an electrical circuit diagram of a vote taker; Figs. 13, 14, and 15 are timing charts showing signal waveform at each part to explain the operation of the third embodiment; Fig. 16 is a circuit diagram showing a fourth embodiment of a digital phase-locked loop system according to this invention; Fig. 17 is a timing chart showing the operation of the said system; Fig. 18 is a block diagram of a prior art digital phase-locked loop system; and Figs. 19 and 20 are waveform diagrams to explain operation of the digital phase-locked loop system shown in Fig. 18. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS (First embodiment) A first embodiment of this invention will be described below referring to Figs. 1 and 2. Fig. 1 is a block diagram of this embodiment. In the figure, clock pulse MCK from the stationary oscillator 4 is generated as shown in Fig. 2 (1) and input to the AND gate G1. Input signal PBSG has a waveform as shown in Fig. 2 (2), is applied to the input terminal D of the D type flip-flop 3 as well as to the AND gate G1. The D type flip-flop 3 draws the logical value which was applied to the input terminal D when phase-locked loop clock signal PLLCK was input to the clock input terminal CK to the output terminal Q and signal Q A is output from the inverting output terminal Q . This output signal Q A of the D type flip-flop 3 is applied to the AND gate G1. The output of the AND gate G1 is input to the counter 1. The output signal Q A of the D type flip-flop 3 is as shown in Fig. 2 (4). The counter 1 counts the pulses applied through the AND gate G1 and the counted value is applied to the register 5 as output signal CNTOUT as shown in Fig. 2 (5). Output signal U of the frequency divider 7 is drawn out as phase-locked loop clock signal PLLCK through the inverting circuit N1 and input to the clock input terminal CK of another D type flip-flop 8 at the same time. Signal of the output terminal Q of the D type flip-flop 3 is input to the input terminal D of the D type flip-flop 8 and applied to the AND gate G2 also. Signal from the output terminal Q of the D type flip-flop 8 is also applied to the AND gate G2. Output of the AND gate G2 is input as reset signal RESET of the counter 1 and applied to the register 5 at the same time. The register 5 stores output signal CNTOUT of the counter 1 when the output of the AND gate G2 is input and draws out phase difference signal I to the decoder 6. Reset signal RESET which is output from the AND gate G2 is as shown in Fig. 2 (6) and phase difference signal I of the register 5 is shown in Fig. 2 (7). The phase difference signal I of the register 5 is input to the decoder 6. Output E of the decoder 6 is as shown in Fig. 2 (8). The output U of the frequency divider 7 is applied to the logical circuit 9. The logical circuit 9 draws out the load clock signal F which has waveform as shown in Fig. 2 (9). The frequency divider 7 receives the load signal G representing frequency dividing rate when the load clock signal F is input, frequency-divides the clock pulse MCK from the stationary oscillator 4 and draws out the signal U. The decoder 6 decodes a value obtained by counting the clock pulses MCK from the stationary oscillator 4 for the time from the step-up edge of the input signal PBSG to the step-up edge of the phase-locked loop clock signal PLLCK and applies decoded data to the frequency divider 7 through the data switching circuit 11. The load signal G representing frequency dividing rate applied to the frequency divider 7 from the data changer 11 is shown in Fig. 2 (10). Frequency dividing rate is also shown in Fig. 2 (10). RS flip-flop 10 is set by the output of the AND gate G2 and reset by the load clock signal F from the logical circuit 9. Signal H from the output terminal Q of this RS flip-flop 10 is as shown in Fig. 2 (11) and applied to the data switching circuit or data changer 11. The data switching circuit 11 applies the output E from the decoder 6 to the frequency divider 7 as load signal G representing frequency dividing rate when the signal H is high level and applies signal representing frequency dividing rate of a predetermined constant N from the constant setting circuit 12 to the frequency divider 7 as load signal G when the signal H is low level. Constant N is "8" in this embodiment for instance. When phase difference occurs between the step-up edge a2 of the input signal PBSG and the step-up edge b2 of the phase-locked loop clock signal PLLCK during operation, clock pulse MCK from the stationary oscillating circuit 4 is input to the counter 1 through the AND gate G1 and counted and its output signal CNTOUT is applied to the register 5. As the output signal U of the frequency divider 7 steps up and input to the D type flip-flop 8, step-up waveform of the reset signal RESET is obtained from the AND gate G2, and by the waveform output "3" of the counter 1 is stored in the register 5, phase difference signal D of the register 5 is applied to the decoder 6, and output E representing frequency dividing rate "9" is drawn out from the decoder 6. The RS flip-flop 10 draws out high level signal H in response to the reset signal RESET from the AND gate G2. Therefore, the data switching circuit 11 is applied with the output E from the decoder 6 as load signal G of the frequency divider 7 and loaded in the frequency divider 7 at the point of time c2 shown in Fig. 2 (9) according to the load clock signal F from the logical circuit 9. The frequency divider 7 conduct frequency dividing operation at the frequency dividing rate "9" in this way. The R-S flip-flop 10 is reset at the point of time c2 at the step-down edge of the load clock signal F from the logical circuit 9. Therefore, the data switching circuit 11 applies the signal presenting constant N from the constant setting circuit 12 to the frequency divider 7 as load signal G. At the time points d2 and e2 when load clock signal F of the logical circuit 9 is drawn out, constant N is loaded to the frequency divider 7 and frequency dividing operation at N is conducted. As described above, after reset signal RESET is applied from the AND gate 2, frequency dividing rate "9" to correct the phase difference signal I representing phase difference from the register 5 is loaded in the frequency divider 7 for the tine until the time point c2 and in the time points thereafter, frequency dividing rate N (= 8) when the phase difference between the signal PBSG and PLLCK is "8" as expected is loaded. This reduces phase difference between f2 at the step-up edge of the input signal PBSG and g2 at the step-up edge of the phase-locked loop clock signal PLLCK as far as possible and reversion of phase is prevented. In the above described embodiment, the system is composed so that output E from the decoder 6 is loaded to the frequency divider 7 only once when phase difference occurs caused between input signal PBSG and phase-locked loop clock signal PLLCK. As another embodiment, it may be composed so that RS flip-flop 10 is reset after plural number of load clock signal F of the logical circuit 9 are generated, output E of the decoder 6 is loaded to the frequency divider 7 predetermined multiple number of times, and then load signal G from the data switching circuit 11 is loaded to the frequency divider 7. As described above, according to this embodiment, frequency dividing rate corresponding to the phase difference between input signal and phase-locked loop clock signal is set and loaded to the frequency divider from frequency dividing rate changing circuit and thereafter a predetermined frequency dividing rate value from the frequency dividing rate constant setting means is set to the frequency divider, and therefore increase of phase difference is prevented, phase of the phase-locked loop clock signal coincides with that of input signal and characteristics of the phase-locked loop system is improved. Composition of this embodiment is relatively simple and therefore can be operated sufficiently near the limit of response speed of logical circuit components. (Second embodiment) A second embodiment of this invention will be described below referring to Figs. 3 to 8. Fig. 3 is a general block diagram of this embodiment. This embodiment is partially similar to the composition shown in Fig. 1. Therefore parts of this embodiment corresponding to the composition of the embodiment are indicated with a reference mark and the explanation is omitted. Notable in this embodiment is that two shift registers 20 and 13 are provided to detect frequency components of the input signal PBSG based on the clock pulse MCK of the stationary oscillator 4. The input signal PBSG is input to the data input terminal D of these shift registers 20 and 13 respectively. The input signal PBSG is applied to the clock input terminal CK for the shift register 20 on one side and to the clock input terminal CK through the inverting circuit N2 to other shift register 13. These shift registers 20 and 13 count the number of clock pulses input to the clock input terminal CK during the term while high-level signal is being applied to the data input terminal D and shift the input signal PBSG in succession. The waveform of the clock pulse MCK from the stationary oscillator 4 is shown in Fig. 4 (1) and the waveform of the input signal PBSG in Fig. 4 (2). Assuming the output of the 7th cell of the shift register 20 to be AQ7, output of the 8th cell to be AQ8, the output of the 9th cell to be AQ9, and the output of the 10th cell to be AQ10, they are shown in Fig. 4 (3, (5), (7), and (9) respectively. Assuming the output of the 7th cell of the shift register 13 to be BQ7, output of the 8th cell to be BQ8, and output of the 9th cell to be BQ9, they are shown in Fig. 4 (4), (6) and (8) respectively. Output of the shift registers 12 and 13 are collectively shown by the reference marks AQ and BQ respectively. These outputs are applied to the latch circuit 14. Clock pulse MCK from the stationary oscillator 4 is inverted by the inverting circuit N3 and input to the clock input terminal CK of the latch circuit 14 and the output AQ and BQ of the shift registers 12 and 13 are respectively latched based on this clock input signal. The numeral assigned to the input signal PBSG in Fig. 4 (2) indicates the number of clock signals from the stationary oscillator 4, that is the length of the high-level term. The signals latched by the latch circuit 14 vary, as shown in Table 1 below according to the number of clock pulses 7 - 9 and 2T of the stationary oscillator 4 in the length of term where the input signal PBSG is at high level by 0.5 step. This result corresponds to frequencies of the input signal PBSG. Here T is the number of pulses of the clock signal, "8" from the stationary oscillator 4, which is the expected cycle value of the input signal PBSG. Fig. 5 (1) - (9) show the signal waves corresponding respectively to Fig. 4 (1) - (9). Fig. 5 shows a a case that the phase of the input signal PBSG (refer to Fig. 5 (2)) is deviated from the input signal PBSG in Fig. 4 (refer to Fig. 4 (2)). Length of PBSG 7 7.5 8 8.5 9 2T Shift register 12 13 12 13 12 13 12 13 12 13 12 13 AQ7 1 1 1 1 1 1 1 1 1 1 1 1 BQ7 1 1 1 1 1 1 1 1 1 1 1 1 AQ8 0 0 1 0 1 1 1 1 1 1 1 1 BQ8 0 0 0 1 1 1 1 1 1 1 1 1 AQ9 0 0 0 0 1 0 1 1 1 1 1 1 BQ9 0 0 0 0 0 1 1 1 1 1 1 1 AQ10 0 0 0 0 0 0 0 0 1 1 1 1 A1 0 1 0 1 0 - A2 0 0 1 1 0 - A3 0 0 0 0 1 - K 0 0 0 0 0 1 The input signal PBSG is digitally modulated and include those of twice or 3 times the expected cycle T. The above described embodiment shows a case of 2T in maximum cycle. The decoder 15 applies 3 bits in total, output B1, B2, and B3, in response to the output of the latch circuit 14 and applies the output K suitable to the cycle of 2T or more to OR gate 16. The output of the inverting circuit N3 is also applied to this OR gate 16 through the line 30. The output of the OR gate 16 is input to the clock input terminal CK of the latch circuit 17. The latch circuit 17 latches the output B1, B2, and B3 of the decoder 15 only when the output K is logical "0", that is, only when the term of high level of the input signal PBSG is between the number of pulses 7 - 9 of the stationary oscillator 4. This enables to prevent malfunction when the term of high level of the input signal PBSG is more than 2T. The Output A11, A12, and A13 from the latch circuit 17 correspond respectively to the output A1, A2, and A3 of the decoder 15 and are input to the read only memory (ROM) 19. Now another signal A10 is output from the output terminal Q of the T type flip-flop (TFF) 18 and input to the read only memory 19. The load clock signal F from the logical circuit 9 is applied to the T type flip-flop 18 also and the T type flip-flop 18 inverts the logical state of the signal of the output terminal Q every time of receiving the load clock signal F. This read only memory 19 receives the previously described signals A10 - A13 as address signal, draws out the output R of 4 bits from the output terminal Q, and applies it to the data switching circuit 11. Contents of the read only memory 19 are shown in Table 2. A3 A2 A1 A0 Output R of ROM19 Cycle of PBSG 0 0 0 0 9 7 0 0 0 1 0 0 1 0 8 7.5 0 0 1 1 9 0 1 0 0 8 8 0 1 0 1 0 1 1 0 7 8.5 0 1 1 1 8 1 0 0 0 7 9 1 0 0 1 The output R of the read only memory 19 varies according to the input. Such state is shown in Figs. 6 - 8. Fig. 6 (1) shows the waveform of the clock pulse MCK of the stationary oscillator 4, Fig. 6 (2) shows the waveform of the input signal PBSG, and Fig. 6 (3) shows the waveform of the phase-locked loop clock signal PLLCK. The output signal Q A of the D type flip-flop 3 is shown in Fig. 6 (4) and the output CNTOUT of the counter 1 is shown in Fig. 6 (5). The reset signal RESET from the AND gate G2 is shown in Fig. 6 (6). The phase difference signal D of the register 5 is shown in Fig. 6 (7) and the output E of the decoder 6 is shown in Fig. 6 (8). The load clock signal F of the logical circuit 9 is shown in Fig. 6 (9). The signal H from the output terminal Q of the RS flip-flop 10 is shown in Fig. 6 (11). When this signal H is at high level, the output E of the decoder 6 is loaded to the frequency divider 7 as load signal G, and when the output H is at low level, the data switching circuit 11 loads the output R of the read only memory 19 to the frequency divider 7 as load signal G. The load signal G is shown in Fig. 6 (10). Fig. 7 (1) - (11) and Fig. 8 (1) - (11) correspond to each waveform of above described Fig. 6 (1) - (11). Thus, in the case of Fig. 6 where the cycle of the input signal PBSG is 7.5 times the clock pulse MCK of the stationary oscillator 4, the output R of the read only memory 19 outputs alternately "8" and "9" as load signal G. When the cycle of the input signal PBSG is 7 times the clock pulse MCK of the stationary oscillator 4, the output R of the read only memory 19 is "9" as shown in Fig. 7, which is drawn out as the load signal G. When the cycle of the input signal PBSG is 8.5 times the clock pulse MCK of the stationary oscillator 4, the output R of the read only memory 19 is "7" and "8" alternately as shown in Fig. 8, which is drawn out as the load signal G. In this way, in Figs. 6-8, when the phase deviation between the step-up edge of the input signal PBSG and step-up edge of the phase-locked loop clock signal PLLCK, a4 - b4, a5 - b5, and a6 - b6 is at the time point c4, d4, e4; c5, d5, e5; and c6, d6, e6 of step-down edge of the load clock signal F of the logical circuit 9,the frequency dividing rate of the load signal G can be changed, and therefore phase deviation does not occur at the time points f4, f5, and f6. As described above, even though the cycle of the input signal PBSG varies between 7 to 9 times the clock pulse MCK from the stationary oscillator 4, phase-locked loop rock range is remarkably improved to the variation of the frequencies of the input signal PBSG within the range and unlocking is prevented. In the above-described embodiment, 2 shift registers 12 and 13 are used and accuracy of the frequency detection of the input signal PBSG could be increased to one-half of the clock pulse MCK of the stationary oscillator 4. By increasing the number of the shift registers 12 and 13, it is possible to improve the measuring accuracy of the input signal PBSG. In the above described embodiment, the output of the read only memory 19 is drawn out alternately as "8" and "9", and "7" and "8", in order to make the frequency of the input signal PBSG 7.5 or 8.5 times the clock pulse MCK of the stationary oscillator 4. By drawing out the output of the read only memory 19 in other mode as another embodiment of this invention, locking corresponding to the cycle of the input signal PBSG becomes possible corresponding to the cycle of the input signal PBS. As described above, according to this invention, frequency dividing rate corresponding to the phase difference between input signal and phase-locked loop clock signal is set by the frequency dividing rate changing circuit, and then frequency dividing rate corresponding to frequency components of the input signal is determined and the frequency divider is operated under the frequency dividing rate adjusting means. Therefore, even though an input signal varies and drifts in a wide range, phase-locked loop can be locked at favorable characteristics, phase deviation between input signal and phase-locked loop clock signal can be prevented, with simple composition. (Third embodiment) A third embodiment of this invention is shown referring to Figs. 9 to 15. Fig. 9 is a block diagram showing electrical composition of the digital PLL system 101 of this embodiment similar to the composition of the first and second embodiments as shown in Figs. 1 and 3 respectively. Figs. 10 and 11 are timing charts showing waveforms of signals at each part. Operation of this embodiment is described below referring to Figs. 9, 10, and 11. One of the features of this embodiment is that a plural number of shift registers 116 and 117 are provided to detect the frequency components of the input signal PBSG based on the clock pulse MCK of the stationary oscillator 102. The input signal PBSG is input to the data input terminal d of the said shift registers 116 and 117 respectively through line L1. The waveform shown in Fig. 10 (1) shows the waveform of the clock signal MCK output from the stationary oscillator 102. The input signal PBSG input to the first shift register 116 is shifted in succession by the clock signal MCK as shown in Fig. 10 (2). The input signal PBSG input to the second shift register 117 is shifted in succession at the timing of the negative phase clock signal M C K when the said clock signal MCK is inverted by the inverter 115 as shown in Fig. 11 (1). The shift output AQ and BQ output in succession after being shifted in this way are input to the data input terminal da and db of the latch circuit 118 separately and latched at the timing at the step-down edge of the said input signal PBSG. Assuming the output corresponding to 7th to 10th of the first shift register 116 respectively to be AQ7 - AQ10, output AQ7 - AQ10 of the first shift register 116 are shown in Fig. 10 (3), (5), (7) and (9), and, assuming the output corresponding to 7th to 9th of the second shift register 117 respectively to be BQ7 - BQ9, the output BQ7 - BQ9 of the second shift register 117 are shown in Fig. 10 (4), (6) and (8). Figure 0, 1, 2, 3, .... attached to the waveform of the input signal PBSG in Fig. 10 (2) show the number counted by the said clock signal MCK during the term when the input signal PBSG is at high level, that is the length of high level term of the input signal PBSG. Signals latched to the latch circuit 118 vary in 0.5 steps to the counted Nos. 7 - 9 and 2T by the said clock signal MCK while the input signal PBSG is at high level, as shown in table 3, according to the length during the high level term of the input signal PBSG and the result corresponds to the frequency of the input signal PBSG. Length of PBSG 7 7.5 8 8.5 9 2T Shift register 12 13 12 13 12 13 12 13 12 13 12 13 AQ7 1 1 1 1 1 1 1 1 1 1 1 1 BQ7 1 1 1 1 1 1 1 1 1 1 1 1 AQ8 0 0 1 0 1 1 1 1 1 1 1 1 BQ8 0 0 0 1 1 1 1 1 1 1 1 1 AQ9 0 0 0 0 1 0 1 1 1 1 1 1 BQ9 0 0 0 0 0 1 1 1 1 1 1 1 AQ10 0 0 0 0 0 0 0 0 1 1 1 1 A1 0 1 0 1 0 - A2 0 0 1 1 0 - A3 0 0 0 0 1 - K 0 0 0 0 0 1 Fig. 11 (1) - (9) show the waveforms corresponding to those in Fig. 10 (1) - (9) in which the phase of the input signal PBSG is deviated from that shown in Fig. 10. The input signal PBSG is digital modulated and those twice and three times those 1 cycle T are also included. This embodiment shows a case of 2T. The decoder 119 applies 3 bits of output A1, A2, and A3 respectively and separately to the shift register 122, 123, and 124 in response to the output of the latch circuit 118 and applies the signal K corresponding to the cycle 2T or more to the OR gate 121, and the OR gate 121 prepares shift clock signal SCK by the logical summation of the said signal K and clock signal MCK inverted by the inverter 120. A1, A2 and A3 output to the shift register 122, 123, and 124 are shifted only when the signal K output from the said decoder 119 is 0, that is, only when the term at high level of the input signal PBSG is 7 - 9 as shown in Table 3, whereby preventing malfunction in the section more than 2T in cycle. The decode output A1, A2, and A3 of the said decoder 119 shifted by the shift register 122 are input to vote takers 125, 126, and 127 respectively. Here, the vote takers 125 - 127 are realized by a plural number of NAND gates shown in Fig. 12, for instance, and outputs values occupying 2 of 3 inputs as shown in the truth table in Table 4, by which decoded values of the said decoder 119 can be detected more accurately. C B A Q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 The load data signal R to determine the frequency dividing rate of the frequency divider 103 is prepared by decoding the output A10 of the T flip-flop circuit 129 which conducts toggle operation by the output A11, A12, and A13 from the vote takers 125, 126, and 127 and load clock signal F output from the logical circuit 113, by the read only memory (referred to as ROM hereafter). In other words, addresses of the ROM128 are designated by the output A11, A12 and A13 of the vote takers 125, 126, and 127, and the output A of the T flip-flop circuit 129 and the output Q of the ROM 128 is input to the data changer 112 as load data signal R. Contents of the ROM128 are as shown in Table 5. According to the input of the ROM128, the load data signal R, which is its output, varies. The condition of the variation is shown in Figs. 13, 14, and 15. A13 A12 A11 A10 Output R of ROM128 Cycle of PBSG 0 0 0 0 9 7 0 0 0 1 0 0 1 0 8 7.5 0 0 1 1 9 0 1 0 0 8 8 0 1 0 1 0 1 1 0 7 8.5 0 1 1 1 8 1 0 0 0 7 9 1 0 0 1 Fig. 13 (1) shows the waveform of the clock signal MCK which is the output of the stationary oscillator 102, Fig. 13 (2) shows the waveform of the input signal PBSG, and Fig. 13 (3) shows the waveform of the PLL clock signal PLLCK. The output Q A of the first D-FF circuit 105 is shown in Fig. 13 (4) and the output CNTOUT of the counter 107 is shown in Fig. 13 (5). The reset signal RST output from the AND gate 110 is shown in Fig. 13 (6), and the waveform of the output signal I of the register 108 is shown in Fig. 13 (7). The waveform of the output signal E of the decoder 111 is shown in Fig. 13 (8), output signal F of the logical circuit 113 in Fig. 13 (9), and the control signal H output from the flip-flop circuit 114 is shown in Fig. 13 (11). When the control signal H is at high level, the data changer 112 inputs the data of the output signal E of the decoder 111 to the frequency divider 103 as load signal G and when the control signal H is at low level, inputs the output signal R of the ROM 128 to the frequency divider 103 as load signal G. The waveform of the load signal G is as shown in Fig. 13 (10). Fig. 14 (1)-(11) and Fig. 15 (1)-(11) correspond to above described each waveform in Fig. 13 (1)-(11). In this way, in the case as shown in Fig. 13 when the cycle of the input signal PBSG is 7.5 times the clock pulse MCK which is the output of the stationary oscillator 102, the output R of the ROM 128 outputs "8" and "9" alternately and apply them to the frequency divider 103 through the data changer 112 as load signal G. When the cycle of the input signal PBSG is 7 times the clock pulse MCK which is the output of the stationary oscillator 102, the output R of the ROM 128 is "9" as shown in Fig. 14, which is input to the frequency divider 103 as the load signal G. When the cycle of the input signal PBSG is 7.5 times the clock pulse MCK which is the output of the stationary oscillator 102 as shown in Fig. 15, the load data signal R which is the output of the ROM 128 outputs "7" and "8" alternately and applies them to the frequency divider 103 through the data changer 112 as the load signal G. In this way, in Figs. 13 - 15, at the time points c4, d4, e4; c5, d5, e5; c6, d6, e6 at which the phase deviation in a4 - b4, a5 - b5, and a6 - b6 between the step-up edge of the input signal PBSG and the step-up edge of PLL clock signal PLLCK, is the output signal F of the logical circuit 113, the frequency dividing rate of the load signal G can be set and therefore phase devication does not occur at time point of f4, f5, and f6. Thus, even if the input signal PBSG is applied up to the cycle 7 - 9 of the clock signal MCK from the stationary oscillator 102 shown in Figs. 10 and 11, the lock range of PLL is remarkably improved and unlocking is prevented to the variation of the frequency of the input signal PBSG in that range. In the above-described embodiment, two shift registers 116 and 117 are used and the frequency detecting accuracy of the input signal PBSG can be increased to a half of the clock signal MCK of the stationary oscillator 102 by them. By increasing the number of the shift registers, the detecting accuracy of the input signal PBSG can be further improved. In the above described embodiment, the output of the ROM 128 is drawn out alternately as "8", "9", and "7", "8", in order to make the frequency of the input signal PBSG 7.5 or 8.5 times the clock signal MCK of the stationary oscillator 102. By drawing out the output of the ROM 128 in other mode as another embodiment of this invention, locking can be effected under individual control corresponding to the cycle of the input signal PBSG. As described above, according to this embodiment, since a frequency dividing rate corresponding to phase difference between input signal and PLL clock signal is set by the frequency dividing rate setting circuit and then the frequency dividing rate corresponding to the frequency components of the input signal is set by the frequency dividing rate adjusting means, such a phase locked loop (PLL) system can be realized that locking of the PLL can be done with favorable characteristics even if the input signal varies in wide range and drifts, even for input signals of high speed near the limit of the processing speed of the logical circuit and even though the circuit composition is simple. (Fourth embodiment) A fourth embodiment of this invention is described below referring to Figs. 16 and 17. Fig. 16 is a circuit diagram showing a digital PLL system according to this embodiment, and Fig. 17 is a timing chart showing operation of this circuit. The digital PLL system of this embodiment is used to read signals reproduced in the normal mode and search mode in DAT, etc. In Fig. 16, reproduced signal PBSG is input to the D-flip-flop 201, latched there at the step-up edge of the reproducing clock PLLCK input to the clock terminal (CK) and input to the AND gate 202 together with the inversion output ( Q A) of the D flip-flop 201. Basic clock MCK output from the stationary oscillator 203 has been input to this AND gate 202 and logical product of the 3 input signals, PBSG, Q A, and MCK, is obtained. This logical product is made the clock input to the counter 204. Then, the counter 204 counts the phase difference between the reproducing signal PBSG and reproducing PLL clock PLLCK (term from the step-up edge 5 of PBSG to the step-up edge 6 of PLLCK in Fig. 17) with the basic clock MCK as the unit. Logical product of the Q output of the D flip-flop 207 which latches the Q output of the said D flip-flop 201 at the step-up edge of the signal of PLLCK inverted again ( PLLCK ) and the Q output of the said D flip-flop 201 is obtained by the AND gate 208. This logical product (called RESET signal) becomes clock of the register 209 which latches the output CNTOUT of the said counter 204. This clock becomes the RESET signal to the counter 204 at the same time, the counter 204 is reset by this RESET signal, and the next counting operation is started from the step-up edge 5 of the next PBSG. In the register 209, the said CNTOUT is latched synchronously with the step-up edge of the RESET signal. The said PLLCK is made PLLCK by the inverter 214. The value latched to the register 209 is obtained by counting the phase difference between the said PLLCK and PBSG with MCK as the unit and the value (D) is input to the first and second decoders 210a and 210b respectively. Either output of the signal E1, E2 decoded by these decoders 210a, and 210b is selected by the data changer 211 and loaded to the frequency divider 212 as a frequency dividing rate of the frequency divider 212 generating PLLCK. In this embodiment, the data changer 211 selects the first decoder 210a at the time of normal reproduction and the second decoder 210b at the time of search by normal/search switching signal N/S. The data load to the frequency divider 212 is synchronous with the clock (F) output from the logical circuit 213 when the output of the frequency divider 212 becomes a specified value. The first decoder 210a decodes the output of 5 - B when the said register output (D) varies to 0 - F in hexadecimal indication. The decoding features correct the frequency dividing rate of the said frequency divider 212 remarkably when the phase deviation is large (D near 0 or F) but correct it very little when the phase deviation is small (D near 8). On the other hand, the second decoder 210b decodes the output of 6 - A when the said register output D varies to 0 - F in hexadecimal indication. The decoding features correct the frequency dividing rate of the said frequency divider 212 approximately in proportion to the phase deviation. Table 6 shows the relation between the first decoder output (E1) and second decoder output (E2) to the said register output (D). As described above, first and second decoders 210a and 210b have decoding characteristics as shown in Table 6 and the register output (D) changes 1 - 3 - 4 and E1 changes 5 - 6 - 7, while E2 changes 6 - 6 - 7, in the timing chart of Fig. 17. It is because E1 and E2 have different values though the register output (D) is the same [1] in Table 6 that the initial values of E1 and E2 are different [5] and [6]. Block error rate and lock range at normal time which show the reproducing characteristics of the reproducing signal of DAT using the digital PLL system composed as described above were measured as shown in Table 7. According to Table 7, the lock error rate of the first decoder 210a is about 10 -4 and can be sufficiently used practically but that of the second decoder 210b is about 10 -3 , worse than the former by 1 digit. However, the block error rate with which index and other codes can be read at the time of search is about 10 -2 . When the range to which the tape speed variation is allowed at the block error rate of about 10 -2 , that is the lock range, is measured, the lock range is only about ±2% if the first decoder 210a is selected but extends to about ±3.5% if the second decoder 210b is selected, which cannot be adapted to the PLL circuit of the search mode. Thus, only by selecting the decoder and switching to it, PLL circuit adaptable to both the normal and search modes is obtained. As described above, according to this embodiment, PLL circuit which can be adapted to both modes by switching the decoders can be composed for a reproducing system provided with different speed modes. In addition, since the circuit composition is simple, the signal delay is a little and raises no problem for practical use even when operated near the speed limit of the logical circuit.

Claims: A digital phase-locked loop system comprising: an oscillator (4; 102) which generates a clock signal of a stationary frequency; a frequency divider (7; 103) to frequency-divide the clock signal generated by the oscillator (4; 102) and to produce a phase-locked loop clock signal; a phase difference detecting means (1, 3, 8; 107, 105, 109) to detect the phase difference between an input signal and the phase-locked loop clock signal, and to output a phase difference detection signal; and a frequency dividing rate setting means (5, 6; 108; 111) to set a first frequency dividing rate corresponding to the phase difference as indicated by the phase difference detecting signal; characterized by a frequency division value setting means (12; 13 - 20; 115 129) to supply a second frequency dividing rate to the frequency divider (7; 103); and a frequency dividing rate switching means (11; 112) to supply the frequency divider (7; 103) at first with the output from the frequency dividing rate setting means (5, 6; 108, 112) in response to the phase difference detection signal when a phase difference is detected, and then to supply the frequency divider (7; 103) with the output signal from the frequency dividing value setting means (12; 13 - 20). A system according to claim 1, wherein said frequency division value setting means (12) is arranged to supply a predetermined frequency dividing rate as said second frequency dividing rate. A system according to claim 1, wherein said frequency division value setting means is arranged as a frequency dividing rate adjusting means (13 - 20; 115 - 129) to detect frequency components of the input signal in response to the output signal of the oscillator (4; 102), and to set such a second frequency dividing rate that the phases of the input signal and the phase-locked loop clock signal coincide with each other. A digital phase-locked loop system comprising: an oscillator (203) which generates a clock signal of a stationary frequency; a frequency divider (212) to frequency-divide the clock signal generated by the oscillator (203) and to produce a phase-locked loop clock signal; a phase difference detecting means (204, 201, 207) to detect the phase difference between an input signal and the phase-locked loop clock signal, and to output a phase difference detection signal; and a first frequency dividing rate setting means (209, 210a) to set a first frequency dividing rate corresponding to the phase difference as indicated by the phase difference detecting signal; characterized by a second frequency dividing rate setting means (210b) to set a second frequency dividing rate; whereby said first and second frequency dividing rate setting means each include a decoder (210a, 210b), said decoders having different decode characteristics depending on the magnitude of the phase difference detection signal; and a frequency dividing rate switching means (211) to select either one of the two types of decoders (210a, 210b) according to a speed mode of the input signal.

Inventors: HIROSHI II, MATSUOKA HIROYUKI, SUDOH KENGO, MATSUOKA, HIROYUKI, SUDOH, KENGO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1988
Main classification: H03L7
IPC codes: H03L7