TIMING CONTROL FOR DISPLAY SYSTEM

Abstract: A CRT display control system includes an access controller (38) for controlling a central processing unit (10) and a display controller (24) for a display device (16) to alternately access a refresh memory (20). The access controller (38) includes a clock synchronizer (42, 44) for recovering synchronization of both the clock (MCLK1) for the central processing unit (10) and the clock (MCLK2) for the display controller (24) automatically when a synchronizing error occurs between the clocks. When an error occurs, the clock synchronizer (42, 44) detects the error and inhibits the display controller (24) from accessing the refresh memory (20) but allows the central processing unit (10) to access the memory (20) during the time for recovering synchronization.

Description: TIMING CONTROL FOR DISPLAY SYSTEM _> Technical Field This invention relates to display systems of the kind including a display device, clock generating means adapted to generate a basic clock pulse train, memory means adapted to store data to be displayed, central processing means, display control means and switch means coupled to said central processing means, said display control means, and said memory means and adapted to select access to said memory means from said central processing means or from said display control means. The invention has a particular application to cathode ray tube (CRT) display systems for use with computers, point-of-sale (POS) terminals or other data processing devices. Background Art In a conventional cathode ray tube (CRT) display device, it is generally known that it is necessary to repeatedly refresh the screen on the CRT, normally on the order of 50-60 times per second, in order to maintain a continuously displayed state and in the manner wherein a controller sequentially reads out all addresses in a refresh memory. In addition, it is also necessary to access the refresh memory from the central processing unit (CPU) for any modification of the screen-displayed content and for other purposes. In one known access method, referred to as the synchronous access method, one half of the time the CPU is allowed to access the refresh memory and the other half of the time the display controller (DC) is allowed to access the refresh memory in an alternating arrangement. In order to avoid flashing or flickering on the screen, a system clock can be employed in a manner so as to access the memory from the central processing unit during the time when the system clock is at a low level, and to access the memory from the display controller during the time when the system clock is at a high level. In the alternating arrangement of the CPU and the display controller (DC), it is seen that no competitive accessing occurs. Furthermore, one character clock period can be halved to access the refresh memory. In other words, the refresh memory is accessed in one half of the time required to display one character. Accordingly, in order to avoid associated problems, it is necessary that high speed elements which are operable in one half of the time and which are required for the operation of conventional elements should be used for the refresh memory and for any peripheral circuits thereof. A one-chip (packaged IC) CPU, a one-chip display controller (DC) , and a one-chip memory, which devices or elements operate at a relatively high speed, are commercially available at relatively low cost. However, a display system using the synchronous access method in which a one-chip central processing unit (CPU) and a one-chip display controller (DC) are employed can be subject to a problem in the operation of the system if the one-chip CPU prepares its own system clock therewithin and the one-chip display controller also prepares its own memory clock therewithin. In the CPU, such memory clock is similar to the system clock in that it is a clock for controlling the timing of accessing the refresh memory, so that such clock is hereinafter referred to as the system clock. The CPU and the display controller (DC) are so constructed as to access the refresh memory, respectively, when each of their own system clocks is high. Accordingly, if operation is initialized so that the system clocks are 180: out of phase with each other simultaneous accessing of the refresh memory by the CPU and the display controller is avoided. However, since the clocks are generated independently of each other within the CPU and the display controller, respectively, one of the system clocks may be inverted by reason of the influence of electrostatic discharge noise and the like. For example, noise may occur in the display controller such that only the system clock of the display controller is inverted. This system clock will again be inverted at the next rising edge of the basic clock, so that the CPU clock becomes in phase with the display controller clock. As a result, the access timings of the CPU and the display controller (DC) coincide with each other. The coincidence of both system clocks can thus cause a problem that neither the CPU nor the display controller can access the refresh memory. Disclosure of the Invention It is an object of the present invention to provide a display system of the kind specified, wherein the aforementioned problem is alleviated. Therefore, according to the present invention, there is provided a display system of the kind specified, characterized in that said central processing means is responsive to said basic clock pulse train to generate a first system clock signal, in that said display control means is responsive to said basic clock pulse train to generate a second system clock signal which is 180: out of phase with said first clock signal, and by access control means adapted to control operation of said switch means and including phase shift detection means adapted to detect a phase shift condition between said first and second system clock signals and in response to such detection, to control said switch means to switch and maintain access to said memory means from said central processing means for a predetermined time period to enable correction of said phase shift condition. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Figs. 1A and IB, taken together, constitute a block diagram illustrating the diagrammatic structure of the display system according to the present invention; Fig. 2 is a timing diagram showing the time of access to the refresh memory of the display system; Fig. 3 is a diagram illustrating a phase shift between the system clocks of the central processing unit and of the display controller; Figs. 4A and 4B, taken together, constitute a logic diagram of the access control unit of Figs. 1A and IB and show the arrangement and relationship between the control unit and the peripheral elements thereof; and Fig. 5 is a timing chart of the operation of the logic diagram shown in Figs. 4A and 4B. Best Mode for Carrying Out the Invention Figs. 1A and IB constitute a block diagram illustrating the diagrammatic structure of an embodiment of the present invention wherein 10 is a central processing unit or CPU section using a basic clock signal MCLK as the reference or basic clock signal on line 12 generated by a basic clock generator 14. The CPU or central processing unit section 10 is normally positioned outside a display device or display section 16 and constitutes a single or one- chip device essentially including therein a microprocessor, ROM, RAM, and a counter for generating a system clock signal on line 18 designated as MCLK1. A single or one-chip device which includes the just mentioned items is available from Hitachi, Ltd. as No. HD6301 derived from the Motorola 6800 CPU series. The CPU section 10 is operated such that display data is input thereinto by means of a keyboard (not shown). The CPU section 10 writes the data thus received into a refresh memory 20, or the CPU section reads out display data which is in the refresh memory 20 and transmits such display data to other places (not shown). The refresh memory 20 is adapted to store the data written thereinto by the CPU section 10 and required to be transmitted to the display section 16. The refresh memory 20 functions mainly (90% or more of the time) to read out the display data in order to refresh the display on a CRT screen (not shown) of the display section 16. In this regard, the refresh memory 20 is normally set so as to read out an address designated as an address bus 22 unless a write signal is received from the CPU section 10. A display controller 24 is adapted to cyclically read out the display data from the refresh memory ' 20 in order to refresh the display on the CRT screen of the display section 16. The display controller 24 is a single or one-chip device essentially including therein various circuits for refreshing operations and a counter (not shown) for generating a system clock signal 26 designated as MCLK2. A single or one-chip device used as the display controller 24 and including the just mentioned circuits is available from Hitachi, Ltd. as a liquid crystal display element timing controller No. HD63645F. The display data thus read out from the refresh memory 20 by the display controller 24 is sent on a data bus 28 from the refresh memory 20 to the display section 16. The display section 16 includes a display screen (not shown) along with a character generator (not shown), a vertical/horizontal synchronous circuit, and a CRT or liquid crystal display (LCD) to display the display data received from the refresh memory 20 via the data bus 28 onto the display screen. Switching means 30 is adapted to selectively switch the connection between the address bus 22 and an address bus 32 to the connection between the address bus 22 and an address bus 34 or vice versa. The address bus 32 and the address bus 34 are coupled as inputs to the switching means 30 from the CPU section 10 and from the display controller 24, respectively. The switching means 30 operates so as to connect either the address bus 32 or the address bus 34 with the address bus 22 in accordance with a select-signal sent on line 36 from an access controlling section 38 (Fig. IB). Numeral 38 denotes the access controlling section which is adapted to control the access of the CPU section 10 and the display controller 24 to the refresh memory 20. The access controlling section 38 essentially consists of a switch controlling section 40, a phase shift detecting section 42 and a phase shift correcting section 44. The switch controlling section 40 switches the select signal on line 36 to coincide with either the system clock MCLK1 signal on line 18 or the system clock MCLK2 signal on line 26 in order to change the connection of the address buses 32 and 34 to coincide with the access timings of the CPU section 10 and of the display controller section 24. In the present embodiment the system clock MCLK2 on line 26 is selected as the clock to coincide with the select signal on line 36. The select signal is sent on line 36 from the switch controlling section 40 to the switching means 30 to change the connection between either the address buses 22 and 32 or the address buses 22 and 34. The select signal on line 36 is also sent to a bus driver 47 to enable the bus driver 47 only in those situations when the CPU section 10 accesses the refresh memory 20. The phase shift detecting section 42 (Fig. IB) monitors whether or not a phase shift occurs between the system clocks MCLK1 and MCLK2. When a phase shift is detected, the phase shift detecting section 42 outputs a detection signal on line 46 to the switch controlling section 40, and also outputs a start signal of phase shift correction on line 48, respectively, to the phase shift correcting section 44, to the switch controlling section 40 and to the display controller 24. The switch controlling section 40 actuates the switching means 30 by means of the select signal on line 36 in a manner such that only the address bus 32 from the CPU section 10 is connected with the address bus 22 in response to seeing the detection signal on line 46 from the phase shift detecting section 42. The phase shift correcting section 44 corrects the phase shift in response to the start signal of phase shift correction on line 48 from the detecting section 42. The basic clock generator 14 (Fig. 1A) is adapted to output the basic clock MCLK to the CPU section 10, to the display controller 24 and to the access controlling section 38 (Fig. IB). The CPU section 10 and the display controller 24, respectively, prepare or initialize their own system clocks MCLK1 and MCLK2 in accordance with the basic clock MCLK. In the operation of the present invention, the system clock signals MCLK1 and MCLK2 are initialized by the CPU section 10- and the display controller 24, respectively, so as to be 180° out of phase with each other, as shown by the timing diagram in Fig. 5. The CPU section 10 and the display controller 24 access the refresh memory 20 in accordance with their own system clocks MCLKl and MCLK2. When the system clocks MCLKl and MCLK2 are prepared, the switch controlling section 40 in the access controlling section 38 (Fig. IB) outputs the select signal on line 36 which goes either to a high signal or to a low signal in synchronism with the system clock MCLK2. The select signal thus output on line 36 by the switch controlling section 40 is transmitted to the switching means 30. The switching means 30 selects either the address bus 32 or the address bus 34 in accordance with the high or the low select signal transmitted on line 36 and connects the bus thus selected to the address bus 22. In this embodiment, when the select signal on line 36 is high, the address bus 34 from the display controller 24 is connected to the address bus 22. When the select signal on line 36 is low, the address bus 32 from the CPU section 10 is connected to the address bus 22. The select signal on line 36 is also transmitted to the bus driver 47 to enable the bus driver 47 only when the select signal is low. It is now assumed that display data is sent from an external device (not shown) through a bus 49 to the CPU section 10 in order to display the data on the screen (not shown) of the display section 16 or to change the displayed contents on the screen. When the system clock MCLKl is high, the CPU section 10 sends a write signal on line 50 to the refresh memory 20 and sends the display data on a data bus 52 coupling the CPU section 10 and the bus driver 47. In the normal state, when the system clock MCLKl is high, the select signal on line 36 is low, so that the address bus 32 of the CPU section 10 is connected to the address bus 22 by the switching means 30. At that time, the bus driver 47 is enabled with the low select signal on line 36. Accordingly, the display data on the data bus 52 is written into an address, designated by the address bus 32, within the refresh memory 20. Next, the refreshing operation of the display on the screen by the display controller 24 will be described. The refreshing operation is performed by cyclically reading out the display data from the refresh memory 20 by means of the display controller 24. The display controller 24 reads out the display data for one screen at a rate of about 50 to 60 times per second in order to refresh the display on the screen. The display controller 24 accesses the refresh memory 20 when the system clock MCLK2 is high. The select signal on line 36 is also high when the system clock MCLK2 is high, so that the address bus 34 of the display controller 24 is connected to the address bus 22 by the switching means 30. Since the select signal 36 is high, the bus driver 47 is disabled and hence the data bus 52 is disconnected from the data bus 28 of the refresh memory 20. A data bus 56 connects the bus driver 47 and the data bus 28. As has been described above, the refresh memory 20 continuously executes the data reading operation unless the write signal on line 50 is sent to the refresh memory 20 from the CPU section 10. Accordingly, the display data in the refresh memory 20 is read out from an address designated by the address bus 34. The display data thus read out is sent on the data bus 28 to the display section 16 to be displayed on the display screen (not shown). The system clock MCLK2 also is input into the display section 16. The display section 16 displays the data received from the data bus 28 on the screen only when the system clock MCLK2 is high, so that the display of the data on the data bus 28 can be avoided when the CPU section 10 writes or reads data from the refresh memory 20. Next, the operation of a phase shift occurrence will be described. The phase shift detecting section 42 of the access controlling section 38 (Fig. IB), into which the system clocks MCLKl and MCLK2 are input, monitors whether or not a phase shift occurs. When a phase shift occurs, the phase shift detecting section 42 detects the occurrence of the phase shift and sends the detecting signal on line 46 to the switch controlling section 40. When the select signal on line 36 goes low, upon the receipt of the detection signal on line 46 from the phase shift detecting section 42, the switching means 30 connects the address bus 32 of the CPU section 10 to the address bus 22 to enable the bus driver 47. Simultaneously therewith, the phase shift detecting section 42 generates a start signal of phase shift correction on line 48 to the phase shift correcting section 44, to the switch controlling section 40 and to the display controller 24. The switch controlling section 40 keeps the select signal on line ' 36 low during the time it receives the start signal of phase shift correction on line 48. Accordingly, after the detection of the phase shift, access to the refresh memory 20 is possible only from the CPU section 10. The display controller 24 (Fig. 1A) receives the start signal of phase shift correction on line 48 to start the operation for the phase shift correction. The phase shift correcting section 44 generates a start signal of system clock MCLK2 on line 54 at the time of rising of the system clock MCLKl when a predetermined period of time has passed after the receipt of the start signal of phase shift correction on line 48. The start signal of clock MCLK2 is sent on line 54 to the phase shift detecting section 42 which stops outputting the start signal of phase shift correction on line 48 after receipt of the start signal of clock MCLK2. When the outputting of the start signal of phase shift correction on line 48 stops, the switch controlling section 40 turns to a state wherein the select signal on line 36 can be changed in accordance with the system clock MCLK2. Also, when the outputting of the start signal of phase shift correction on line 48 stops, the display controller 24 causes the system clock MCLK2 to start in the high state. The start signal of clock MCLK2 on line 54 goes high at the time of falling of MCLKl, so that the system clock MCLK2 is started at the time when the system clock MCLK2 is 180ψ out of phase with the system clock MCLKl. The switch controlling section 40 then switches the select signal on line 36 in accordance with the system clock MCLK2. Thus, the phase shift between the system clocks MCLKl and MCLK2 is corrected and the phase shift correcting operation is completed. It is seen that during the phase shift correcting operation, it is possible to access the refresh memory 20 from the CPU section 10, so that any display data which is input from an external device can be correctly written into the refresh memory 20. Fig. 2 is a timing diagram which illustrates a one-character clock period and the time of access of the refresh memory 20 by the CPU section 10 and alternately by the display controller 24. Fig. 3 is a diagram which illustrates a phase shift between the system clock MCLKl of the CPU section 10 and the system clock MCLK2 of the display controller 24. The basic clock MCLK and the CPU system clock MCLKl are shown in normal pattern and state of condition. The display controller system clock MCLK2 is shown in a normal state until a phase shift is detected at Point A and the continuity of access is interrupted. Fig. 3 also illustrates time of access by the CPU section 10 and alternately by the display controller 24 during the normal state. During the erroneous state, the CPU section 10 provides access to the refresh memory 20 until the phase shift is corrected. Next, the monitoring of the synchronous state between the system clocks MCLKl and MCLK2 from the CPU section 10 and the display controller 24, and the detection and correction of out-of-synchronism of both system clocks will be described in detail with reference to Figs. 4A, 4B and 5. Figs. 4A and 4B provide a diagram showing the relationship between the logic of an embodiment of the access controlling section 38 in Figs. 1A and IB and the constituent elements within the single chip display controller 24 and the peripheral devices thereof. Fig. 5 is a timing chart illustrating the operation of the circuits shown in Figs. 4A and 4B. In Fig. 4A, the display controller 24 consists of an address controller 60 and a clock controlling section 62. The address controller 60 includes various controlling circμits (not shown) for the refreshing operation. When the refresh memory 20 is connected with the address buses 34 and 22, the address controller 60 operates so as to read out the display data in the refresh memory 20 while automatically counting up the addresses one by one to refresh the display. The clock controlling section 62 consists of a counter or the like in which the frequency of the basic clock MCLK is divided to generate the system clock MCLK2. In this embodiment, and for the convenience of explanation, only a flip- flop 64 and a voltage source 66 are shown as the clock controlling section 62. Also in this embodiment, the frequency of the system clock MCLKl of the CPU section 10 is set to a value corresponding to half the frequency of the basic clock MCLK. In this regard the output Q/ (to be read as Q bar) and the input D of the flip-flop 64 are connected with each other in order to set the frequency of the system clock MCLK2 of the display controller 24 to the value corresponding to half the frequency of the basic clock MCLK. As shown in Fig. 4B, the access controlling section 38 consists of an exclusive OR gate 68 to monitor the synchronous state between the " clocks MCLKl and MCLK2, a pair of flip-flops 70 and 72, and an AND gate 74 to control the switching operation of the address buses 32 and 34. The access controlling section 38 also includes a counter 76 to prepare a predetermined period of time suitable for the correction of the out-of-synchronism condition, a pair of flip-flops 78 and 80 to prepare the timing for the correction, and a pair of inverters 82 and 84. First, the operation of the access controlling section 38 when both system clocks MCLKl and MCLK2 are in a normal state 180° out of phase with each other will be described. In Fig. 5, the basic clock MCLK is illustrated in continuous manner in the .normal state and in the erroneous state. The system clock MCLKl (Fig. 5) of the CPU section 10 and the system clock MCLK2 of the display controller 24, which clocks are 180° out of phase with each other, are input to the exclusive OR gate 68 (Fig. 4B) . An inverted clock of the CPU system clock MCLKl is designated MCLKl/ (to be read as MCLKl bar). A detection signal on line 86, designated as XOR in Fig. 5, which signal is output from the exclusive OR gate 68, is sent to AND gate 74 in the high state. The start signal of phase shift correction on line 48, designated as Q2/ (to be read as Q2 bar in Fig. 5), is applied to the AND gate 74 in a high state so that the select signal on line 36 which is output from the AND gate 74 goes either to high or low depending on the state of the system clock MCLK2 of the display controller 24. System clock MCLK2 is another input into the AND gate 74. As an example, when the system clock MCLK2 of the display controller 24 is high, the select signal on line 36 goes high, so that the display controller 24 accesses the refresh memory 20 to cyclically refresh the display on the screen of the display section 16. When the system clock MCLK2 of the display controller 24 is low, the select signal on line 36 goes low during which time the CPU section 10 can access the refresh memory 20, as required, to rewrite the display data in the refresh memory 20. Thus, the CPU section 10 and the display controller 24 can alternately access the refresh memory 20 in synchronism with the system clock MCLK2. The detection and correction of the phase shift which occurs between the clock MCLKl of the CPU section 10 and the clock MCLK2 of the display controller 24 will now be described. It is assumed that either one of the system clocks, MCLKl or MCLK2, which are prepared and based on the basic clock MCLK, is selected for the operation. Assume, for example, the system clock MCLK2 is inverted due to electrostatic noise or the like at the.point A in Fig. 5 and hence the phase shift occurs between both clocks. The exclusive OR gate 68 (Fig. 4B) which monitors the synchronous state of both clocks immediately provides that the detection signal on line 86 goes low (point B in Fig. 5) and outputs the same to the AND gate 74. As a result, the select signal on line 36 which- is output from the AND gate 74 goes low regardless of the state of the clock MCLK2 (point C in Fig. 5), which makes the CPU section 10 accessible to the refresh memory 20. An output Ql/ (to be read as Ql bar) of the flip-flop 70 goes high (point E in Fig. 5) in synchronism with the rising of the basic clock MCLK (point D in Fig. 5) in response to the receipt of the low detection signal on line 46 applied to the flip-flop 70. At that time, a D input of the flip- flop 72 is high so that the flip-flop 72 outputs on line 48 the low start signal of phase shift correction Q2/, as shown at point F in Fig. 5, in synchronism with the rising of the output Ql/ from the flip-flop 70. The low start signal on line 48 of phase shift correction Q2/ directly resets the flip-flop 64 of the display controller 24 to keep the clock MCLK2 at high (point G in Fig. 5). The low start signal on line 48 of phase shift correction Q2/ is also applied to the AND gate 74 to keep the select signal on line 36 at low (point H in Fig. 5). Such state of the select signal on line 36 wherein only the CPU section 10 can access the refresh memory 20 is maintained until the out-of-synchronism condition is corrected. Further, the counter 76 counts up predetermined numbers in synchronism with the falling of the basic clock MCLK by the low start signal on line 48 of phase shift correction Q2/ and thereafter outputs a high Q Q signal through a Q- output of the counter 76 (point I in Fig. 5). The flip-flop 78 provides a Q3 signal at a Q output to go high (point J in Fig. 5). In synchronism with the rising of the QQ signal and with the high Q3 signal, the flip-flop 80 provides a start signal of MCLK2, designated as Q4/ (to be read as Q4 bar in Fig. 5), to go low (point L in Fig. 5) in synchronism with the rising (point K in Fig. 5) of the inverted signal, designated as MCLKl/ (to be read as MCLKl bar), of the system clock MCLKl which is applied through inverter 84. The low start signal of MCLK2, designated as Q4/, directly resets the flip-flop 72 and provides the start signal of phase shift correction Q2/ to go high (point M in Fig. 5). With the high start signal of phase shift correction Q2/, the flip-flop 64 within the display controller 24 goes into a state that is operable in accordance with the basic clock MCLK. Accordingly, the flip flop 64 goes low in synchronism with the rising of the next basic clock MCLK (point P in Fig. 5). With the high start signal of phase shift correction Q2/, all of the three inputs of the AND gate 74 go high, so that the high select signal is output on line 36 from the AND gate 74 (point R in Fig. 5). After the select signal changes in accordance with the clock MCLK2, both clocks are kept in the synchronous state. The detection and correction of the phase shift between both clocks is performed in the above mentioned manner. Further, the counter 76 is cleared by the high start signal of phase shift correction Q2/ which is sent thereto on line 48. In addition, the flip-flop 78 is directly reset by the signal Q2/ which is inverted to low by the inverter 82. The low signal Q3 outputs through output Q of flip-flop 78 to an input D of the flip- flop 80. The start signal Q4/ of MCLK2 which is output from the flip-flop 80 goes high (Fig. 5, point T) in synchronism with the rising (Fig. 5, point S) of the inverted signal of the clock MCLKl which is inverted by the inverter 84. This high start signal Q4/ of MCLK2 releases the reset state of the flip-flop 72. In the above mentioned manner, the access controlling section 38 completely returns to its normal state to monitor the synchronous state of both clocks. Although in this embodiment, the state in which the system clock MCLK2 of the display controller 24 is inverted from low to high to cause the out-of- synchronism condition has been described, the out-of- synchronism condition can be corrected in the same manner as above when either one of the clocks, MCLKl or MCLK2, is inverted to cause the phase shift. Also, in this embodiment, the appropriate period of the phase shift correction is defined so as to correspond to the length of an 8-cycle basic clock MCLK. However, the number of counters can be increased in accordance with the extent of the electrostatic discharge noise or the like so as to extend the period to a value corresponding to the length of a 64-cycle or a 128-cycle basic clock. It is thus seen that herein shown and described is a CRT display device in a character display system that provides for correction of phase shift between two system clocks.

Claims: CLAIMS : 1. A display system, including a display device (16), clock generating means (14) adapted to generate a basic clock pulse train, memory means (20) adapted to store data to be displayed, central processing means (10), display control means (24) and switch means (30) coupled to said central processing means (10), said display control means (24), and said memory means (20) and adapted to select access to said memory means (20) from said central processing means (10) or from said display control means (24), characterized in that said central processing means (20) is responsive to said basic clock pulse train to generate a first system clock signal (MCLKl), in that said display control means (24) is responsive to said basic clock pulse train to generate a second system clock signal (MCLK2) which is 180° out of phase with said first clock signal (MCLKl), and by access control means (38) adapted to control operation of said switch means (30) and including phase shift detection means (42) adapted to a detect phase shift condition between said first and second system clock signals (MCLKl, MCLK2) and in response to such detection, to control said switch means (30) to switch and maintain access to said memory means (20) from said central processing means (10) for a predetermined time period to enable correction of said phase shift condition. 2. A display system according to claim 1, characterized in that said clock generating means (14) is coupled directly to said central processing means (10), to said display control means (24), and to said access control means (38). 3. A display system according to claim 1, characterized in that said display device (16) includes a cathode ray tube, and in that said memory means includes a refresh memory (20) adapted to store read and write data to be displayed on said cathode ray tubes. 4. A display system according to claim 1, characterized in that said access control means (38) includes switch control means responsive to said second system clock signal (MCLK2) to control said switch means (3) to switch memory means access from display control means (24) to said central processing means (10) . 5. A display system according to claim 1, characterized in that said access control means (38) includes a phase shift detecting section (42) and a phase shift correcting section (44) operable during said predetermined time period when said central processing means (10) is accessing said memory means (20). 6. A display system according to claim 1, characterized by driver means (47) coupled to said memory means (20), to said display device (16) to said central processing means (10) and to said access control means (38) and operative during said predetermined time period to enable said central processing means (10) to access said memory means (20). 7. A display system according to claim 6, characterized by a first address bus (32) coupling said central processing means (10) to said memory means (20), a second address bus (34) coupling said display control means (24) to said memory means (20), a third address bus (22) coupling said switch means (30) to said memory means (20), a first, data bus (28) coupling said memory means (20) to sai display device (16), and a second data bus (52) coupling said central processing means (10) to said driver means (47), and in that said driver means (47) is coupled to said memory means (20) and to said first data bus (28).

Inventors: AKAZAWA MASARU, UTSUMI MASASHI, AKAZAWA, MASARU, UTSUMI, MASASHI
Applicants: NCR CO, NCR CORPORATION
Application year: 1988
Main classification: G09G1
IPC codes: G09G1, G09G5