Programmable logic device

Abstract: A programmable logic device includes an input/output buffer (23), a logic array (26, 29), switches (24) for switching signal lines provided between the logic array and the input/output buffer and feedback lines between an input and output of the logic array so as to alter the logic operation. Switching operations of the switches such as an open/close operation and a selection operation, are determined by contents stored in a plurality of non-volatile memory elements (31) arranged like a matrix which are provided for the respective switches. The contents of the memory elements are read out and stored in registers. The contents of the non-volatile memory elements stored in the registers are applied to control terminals of the switches.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a programmable logic device, and in particular to a programmable logic device comprising input/output buffer means for passing an input signal and an output signal from and to an external circuit, logic array means for performing a logic operation on a signal applied thereto; and switching means including switches for switching signal lines provided between the logic array means and the input/output buffer means and feedback lines between an input and and output of the logic array means, so as to alter the said logic operation; matrix means comprising a plurality of non-volatile memory elements arranged like a matrix being provided for the respective switches, a memory content stored in each of the non-volatile memory elements being used for controlling a switching operation of a corresponding switch. EP-A-0 055 348 discloses a reprogrammable logic system, having these features, using a PLA, in which the PLA and registers are real located when an interrupt rest occurs or an instruction by the operator is input. It comprises writable transistors which form an OR array, an AND array, a main storage mechanism, a load storage mechanism and a load directory. The object of this prior art is to rewrite the contents of the logic array during the time a control function is being executed. IEEE JOURNAL OF SOLID STATE CIRCUITS, vol. SC-21, No. 5, October 1986, pages 766-774 discloses erasable programmable logic devices that configure themselves at power-up. However, these devices neither show nor suggest reading means for selectively transferring control information to a corresponding one of a plurality of the register means via the common bus in response to the detection signal, and they neither show nor suggest verify means. A programmable logic array device such as a programmable logic array device (hereafter simply referred to PLA device) or programmable array logic (PAL device) has switches and programmable non-volatile memory elements such as erasable and programmable read only memory cells (hereafter simply referred to as EPROM cells). Switches are used for opening and closing a signal line or for selecting one of signals. Each of the switches is controlled in accordance with a storage content of the corresponding programmable non-volatile memory element. The programmable non-volatile memory elements and the switches construct a control circuit block which establishes and alters logic connections such as a signal input/output connection and an internal feedback connection. Such a control circuit block is hereafter referred to as a macro-cell. In general, the programmable logic array device includes a plurality of macro-cells. Conventionally, for each of the non-volatile memory elements, there is provided a write-in circuit, a read-out circuit and a power source switching circuit which is used for selectively supplying the write-in and read-out circuits with a power source voltage. In general, these circuits are made up of metal oxide semiconductor transistors (hereafter simply referred to as MOS transistors). In particular, the write-in circuit and the power source switching circuit must be constructed by MOS transistors having a high-voltage resistant ability. The conventional programmable logic device including the above macro-cell has the following disadvantages. First, in order that the programmable logic device has an increased number of switches to thereby enhance functions thereof, a semiconductor chip having a greatly increased surface area must be used. This is because a write-in circuit, read-out circuit and power source switching circuit must be provided for each of the non-volatile memory element, and particularly the write-in circuit and the power source switching circuit are constructed by high-voltage resistant MOS transistors. Secondly, a test checking whether or not the write-in circuit and read-out circuit operate correctly, must be carried out for each of the non-volatile memory elements. Therefore, a long time is taken to test the device. SUMMARY OF THE INVENTION Accordingly, a general object of the present invention is to provide a novel and useful programmable logic device in which the above disadvantages are eliminated. A more specific object of the present invention is to provide a programmable logic device which has a considerably increased number of switches without using an increased size of a semiconductor chip to thereby provide expanded functions of the device. Another object of the present invention is to provide a programmable logic device in which the time taken to test the programmable logic device can be shortened. The above objects of the present invention are achieved by the features of claim 1. Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS.1A and 1B show a symbol and a circuit of a switch, respectively, which may form part of a macro-cell; FIGS.2A and 2B show a symbol and a circuit of another switch, respectively, which may form part of a macro-cell; FIG.3 is a circuit diagram of write-in, read-out and power source switching circuits which are provided for each of the non-volatile memory elements for controlling corresponding switches contained in a conventional programmable logic device; FIG.4 is a block diagram of a PLD suitable for incorporating the present invention; FIG.5 is a view showing how to combine FIGS.5A and 5B; FIGS.5A and 5B are block diagrams of a power-on load circuit shown in FIG.4 according to the present invention; FIGS.6(A) through 6(k) show signal waveforms at different portions in the arrangement of FIGS.5A and 5B; FIG.7A is a circuit diagram of a 5-to-20 decoder 53 shown in FIG.5A; FIG.7B is a circuit diagram of a 3-to-2 decoder 54 shown in FIG.5A; FIG.8 is a circuit diagram of an EPROM matrix 56 shown in FIG.5A; FIG.9 is a circuit diagram of a multiplexer 57 and a sense amplifier 58 shown in FIG.5A; FIG.10 is a circuit diagram of a write-in pulse generator 76 shown in FIG.5A; FIG.11A is a circuit diagram of a macro-cell 24 shown in FIG.4; FIG.11B is a circuit diagram of a part of each of the registers 81 to 83 shown in FIG.11A; FIG.12 is a circuit diagram of a comparator 75 shown in FIG.5B; FIG.13 is a circuit diagram of a repetition control circuit 41 shown in FIG.5B; FIG.14A shows circuits which may be provided in the macro-cell 24 shown in FIG.4; FIG.14B shows a circuit which may be provided in the macro-cell 24 shown in FIG.4; FIG.14C shows a circuit which may be provided in an input/output buffer 23 shown in FIG.4; FIG.14D shows a circuit of a feedback input buffer 25 shown in FIG.4; and FIG.15 is a plan view of an example of a semiconductor chip of the programmable logic device according to the present invention. DETAILED DESCRIPTION To facilitate the understanding of the present invention, a description is given of a conventional programmable logic device with reference to FIGS.1A and 1B, 2A and 2B, and 3. In general, a macro-cell contains switches such as a switch shown in FIGS.1A and 1B for opening or closing a signal line A-B, and a switch shown in FIGS.2A and 2B for selecting one of two signal line A-C and B-C. The conventional macro-cell has a programmable non-volatile memory element such as an EPROM cell provided for each of the switches. The non-volatile memory elements are used for controlling respective switches. Each of the switches is connected to corresponding write-in, read-out, and power source switching circuits as shown in FIG.3. In FIG.3, a MOS transistor Q12 which is an EPROM cell, serves as a programmable non-volatile memory element. MOS transistors Q1 to Q6 constitute a power source switching circuit. A write-in circuit is made up of MOS transistors Q7 to Q11 and an OR circuit 12. A read-out circuit is made up of MOS transistors Q13 through Q17. When a write enable signal XWE supplied to terminals 10 and 11 from a central processing unit (not shown: hereafter simply referred to as CPU), for example, is kept at a low level, the MOS transistor Q5 is allowed to conduct. Then, the memory element Q12 can be supplied with a write-in-use power source voltage Vpp (12 volts, for example). On the other hand, when the write enable signal XWE is kept at a high level, the MOS transistor Q6 is allowed to conduct, so that the MOS transistor Q12 can be provided with a normal power source voltage Vcc (5 volts, for example). When both the write enable signal XWE and a fuse cut signal XFC which are applied to terminals 13 and 14, respectively, are kept at the low level, the MOS transistor Q11 is allowed to conduct, so that the write-in-use power source voltage Vpp can be supplied to the EPROM cell Q12. Thereby, an excessive current is allowed to flow through the EPROM cell Q12, and a datum can be written therein. After the datum is written into the EPROM cell Q12, the source and drain thereof is kept electrically disconnected. In this state, the potential at a point A is kept high due to the function of the MOS transistor Q14, and therefore the potential at a terminal 15 is kept low. On the other hand, when the datum has not been written into the EPROM cell Q12, or in other words the EPROM cell Q12 is kept in conduction, the potential at the point A is kept low, and therefore the potential at the terminal 15 is kept high. A change of the potential at the terminal 15 is supplied, as a control signal, to a control terminal of a corresponding switch (not shown in FIG.2). However, the above conventional programmable logic device has the aforementioned disadvantages. The present invention intends to overcome the disadvantages. A description is given of a preferred embodiment of the present invention. Referring to FIG.4, signals applied to input/output terminals 20₁ to 20 n (external input signals) are supplied from an external circuit such as a CPU (not shown) to a macro-cell 24 through an input/output buffer 23. Signals supplied from the macro-cell 24 are supplied to an AND array 26 through a feedback input buffer 25. The signal from the macro-cell 24 is the signal from the input/output buffer 23 or a signal supplied from an OR array 29 through a sense amplifier 30 (a feedback signal). The AND array 26 is also supplied with clock signals CLK1 and CLK2 which are applied to terminals 21 and 22, respectively and which pass through an input buffer 27. Output signals of the AND array 26 are supplied through cube lines to a sense amplifier/driver 28, where amplifiers the output signals of the AND array 26. Amplified output signals are supplied to the OR array 29. Output signals of the OR array 29 are supplied to the macro-cell 24 through the sense amplifier 30, at which the output signals of the OR array 29 are separated into feedback signals and external output signals. The external output signals are supplied to the external circuit through the input/output buffer 23 and input/output terminals 20₁ and 20 n . The macro-cell 24 is supplied with the clock signals CLK1 and CLK2 supplied from the input buffer 27 and supplied with a set signal SET and a clear signal CLR which are supplied from the sense amplifier 30. The macro-cell 24 contains switches as shown in FIGS.14A through 14D as well as a write-in and read-out circuit shown in FIGS.11A and 11B which are used in common to all the switches contained in the macro-cell 24. A power-on load circuit 31 includes non-volatile memory elements which are arranged like a matrix. The non-volatile memory elements are associated with the respective switches of the macro-cell 24. That is, each of the switches of the macro-cell 24 is controlled by the corresponding non-volatile memory element. As described in detail later, at the time of turning power ON, states of the non-volatile memory elements are read out and are then loaded into registers provided in the write-in circuit of the macro-cell 24. The contents of the registers are supplied to the switches, so that states of the switches can be controlled. FIGS.5A and 5B are block diagrams showing a structure of the power-on load circuit 31. Referring to FIGS.5A and 5B, a power-on reset pulse generator 40 generates a detection signal POR as shown in FIG.6(A) when detecting power ON. The detection signal POR is supplied to a repetition control circuit 41. The repetition control circuit 41 generates a control signal POLCLR as shown in FIG.6(B) in response to the application of the detection signal POR. The control signal POLCLR is supplied to a source clock generator 43 provided in a clock generator 42. The source clock generator 43 repetitively generates a source clock signal ICKS when the control signal POLCLR is kept at the low level, and supplies T-type flip-flops 44 and 45 with the source clock signal ICKS. The flip-flop 44 is cleared by a rising edge of the control signal POLCLR, and is thereafter triggered by a rising edge of the source clock signal ICKS. When triggered, the flip-flop 44 generates a clock signal ICK1 shown in FIG.6(C). The clock signal ICK1 is supplied to an address generator 48 through a buffer 46. The flip-flop 45 is cleared by the rising edge of the control signal POLCLR, and is thereafter triggered by a trailing edge of the source clock signal ICKS. When triggered, the flip-flop 45 generates a clock signal ICK2 shown in FIG.6(D) which lags behind the clock signal ICK1 by 90°. The clock signal ICK2 is then supplied to the repetition control circuit 41 and an access control circuit 52 through a buffer 47. The clock signal ICK1 is used for defining timing of reading out contents of an EPROM matrix 56 provided in a non-volatile memory matrix part 55, and the clock signal ICK2 is used for defining timing of writing the read-out content into the registers provided in the macro-cell 24. A ternary counter 49 provided in the address generator 48 is cleared by the rising edge of the control signal POLCLR, and then increments in synchronism with the rise of the clock signal ICK1. The ternary counter 49 produces addresses consisting of two bits CY0 and CY1. A 20-ary counter 50, which receives the address signal CY1 at a carry-in terminal thereof, is cleared by the control signal POLCLR. Thereafter only when the counted value of the ternary counter 49 becomes equal to "2", the 20-ary counter 50 counts up in synchronism with the rise of the clock signal ICK1, and produces addresses consisting of 5 bits CX0 to CX4. The address signals CY0 and CY1 are supplied to a multiplexer 51a, and the address signals CX0 to CX4 are supplied to a multiplexer 51b. The multiplexer 51a is also supplied with write-in address signals A0 and A1 from the CPU (not shown), and the multiplexer 51b is also supplied with write-in address signals A2 to A6. The selected address signals from the multiplexers 51a and 51b are supplied to a 5-to-20 decoder 53 and a 2-to-3 decoder 54, respectively, both of which are contained in the access control circuit 52. The multiplexers 51a and 51b select the address signals supplied from the counters 49 and 50, respectively, when a switching signal POLBUSY (described later) is kept at the low level. Then data can be written into the EPROM matrix 56 through a sense amplifier and a 21-to-7 multiplexer 57. On the other hand, when the switching signal POLBUSY is kept at the high level, the contents can be read out from the EPROM matrix 56. The 5-to-20 decoder 53 contains 20 circuits, each of which is shown in FIG.7A. Referring to FIG.7A, a depletion type MOS transistor Q20 functions as a load resistor. Gates of n-channel MOS transistors Q21 to Q25 connected as shown are supplied with the address signals CX0 to CX4 or inverted address signals thereof through terminals 53a to 53e, respectively. A drain output of the MOS transistor Q21 is delivered to an output terminal 53f through an inverter which is made up of MOS transistors Q26 and Q27. The output terminal 53f in each of the 20 circuits is connected to a corresponding word line of the EPROM matrix 56. That is, 20 word line selecting signals R0 to R19 derived from the 5-to-20 decoder 53 are supplied to the corresponding word lines of the EPROM matrix 56. The word line selecting signals R0 to R19 sequentially select one of the 20 word lines of the EPROM matrix 56. The word line selecting signal R0 is shown in FIG.6 (E). The 2-to-3 decoder 54 contains 3 circuits, each of which is shown in FIG.7B. Referring to FIG.7B, a depletion type MOS transistor Q30 functions as a load resistor. Gates of MOS transistors Q31 and Q32 are supplied with the address signals CY0 and CY1 or inverted address signals thereof. A drain output of a MOS transistor Q31 is supplied to an output terminal 54c through an inverter which is composed of MOS transistors Q34 and Q35. In this manner, the decoder 54 generates column gate signals C0 to C2 as shown in FIGS.6(F) through 6(H). The column gate signals C0 to C2 are supplied to the 21-to-7 multiplexer 57 provided in the non-volatile memory cell matrix part 55. As shown in FIG.8, the non-volatile memory cell matrix part 55 is made up of the EPROM matrix 56, the multiplexer 57 and the sense amplifier 58. The EPROM matrix 56 includes 20 word lines 60₁ to 60₂₀, 21 bit lines 61₁ to 61₂₁, and 20 x 21 number of EPROM cells 62 which are provided at intersecting points of the word lines 60₁ to 60₂₀ and bit lines 61₁ to 61₂₁. The word lines 60₁ to 60₂₀ are connected to the decoder 53, and the bit lines 61₁ to 61₂₁ are connected to the multiplexer 57. In the multiplexer 57, the 21 bit lines are divided into 7 blocks each consisting of 3 bit lines. The multiplexer 57 selects the first bit line of each of the 7 blocks when the column gate signal C0 is supplied thereto. The multiplexer 57 selects the second bit line of each block when the column gate signal C1 is supplied thereto. When the column gate signal C2 is supplied to the multiplexer 57, it selects the third bit line of each block. FIG.9 shows an essential part of the multiplexer 57 and the sense amplifier 58. Referring to FIG.9, terminals 65a to 65c are connected to the bit lines 61₁ to 61₃, respectively. The column gate signals C0 to C2 are supplied, through terminals 66a to 66c, to gates of MOS transistors Q40 th Q42, respectively which constructs the multiplexer 57. Sources of the MOS transistors Q40 to Q42 are connected in common to a write-in buffer 67 and the drain of a MOS transistor Q43. The write-in buffer 67 is supplied through terminals 68a and 68b with the write enable signal WE and a one-bit write-in datum, respectively, which may be supplied from the CPU, for example. The write-in buffer 67 is activated only when the datum is written into one of the EPROM cells 62 provided in the EPROM matrix 56. The one-bit write-in datum is supplied to one of the bit lines 61₁ to 61₃ which is selected by the column gate signals C0 to C2. The MOS transistor Q43 is supplied, through a terminal 69, with the inverted signal of the control signal POLCLR. The MOS transistor Q43 is allowed to conduct only at the time of the power-on loading operation. A MOS transistor Q45 is supplied, through a terminal 70, with a bias voltage V BS (approximately 2 volts). MOS transistors Q44 and Q46 are of the depletion type, and function as load resistors. A signal that passes through the MOS transistor Q43 passes through the MOS transistors Q45 and 47 and through an inverter consisting of MOS transistors Q48 and Q49. An output of the inverter is applied, as a read-out datum D0, to a terminal 71. The multiplexer 57 and the sense amplifier 58 are constructed by 7 circuits, each of which is illustrated in FIG.9. The read-out signal consisting of 7 bits D0 to D6 derived from the multiplexer 57 are supplied, through the sense amplifier 58, to a comparator 75 shown in FIG.5B and also to the macro-cell 24 through a terminal 74. The write-in pulse generator 76 is constructed by 3 AND gates 76a to 76c, as shown in FIG.10. The AND GATES 76a to 76c are supplied with the column gate signals C0 to C2 from the decoder 54, respectively, and also with the clock signal ICK2 supplied from the buffer 47. The write-in pulse generator 76 generates a write-in pulse signal consisting of 3 bits WE0 to WE2 as shown in FIG.6(I) through 6(K), which are fed to the macro-cell 24 through a terminal 77. The word line selecting signals R0 to R19 are supplied to the macro-cell 24 via a terminal 78. FIG.11A shows an essential part of a write-in and read-out circuit constructed in the macro-cell 24. Referring to FIG.11A, the read-out signals D0 to D6 are supplied to registers 81 to 83 through a terminal 80 which is connected to the terminal 74 shown in FIG.5B. AND circuits 86a to 86c are supplied with the word selecting signal R0 applied to a terminal 84 connected to the terminal 78, and are supplied with the write-in pulse signals WE0 to WE2 applied to terminals 85a to 85c, respectively, which are connected to the terminal 77. The AND circuits 86a to 86c generate write enable signals WES, which are supplied to the registers 81 to 83, respectively. A circuit portion which is formed in each of the registers 81 to 83 and which is provided for each of the bits D0 to D6, is constructed as shown in FIG.11B. Referring to FIG.11B, MOS transistors Q51 and Q52 are allowed to conduct when the write enable signal WE is applied to a terminal 87 which corresponds to one of the terminals 81 to 83. When the MOS transistors Q51 and Q52 are held in conduction, the one-bit datum Di passing through a terminal 88 is latched by a latch circuit composed of inverters 89 to 91. A latched one-bit datum is always supplied through a terminal 93 to the corresponding switch formed in the macro-cell 24. The latched datum Di obtained at the terminal 93 for each of the bits D0 to D6 in each of the registers 81 to 83 is supplied, as a control signal, to the corresponding switch formed in the macro-cell 24. The datum Vi obtained at a terminal 92 provided for each of the bits D0 to D6, is supplied as a verify datum to the comparator 75 through the terminal 79 shown in FIG.5B. The macro-cell 24 contains 20 circuits, one of which is shown in FIG.11B. The comparator 75 has a circuit configuration shown in FIG.12. Exclusive-OR circuits 100₁ to 100₇ compare the read-out data D0 to D6 applied to terminals 101₁ to 101₇ with the verify data V0 to V6 applied to terminals 102₁ to 102₇, respectively. Outputs of the exclusive-OR circuits 100₁ to 100₇ are supplied to an OR circuit 103. The OR circuit 103 produces a verify fail signal F held at the high level in the cases other than a case when the read-out data D0 to D7 completely coincide with the verify data V0 to V7, respectively. The verify fail signal F is supplied to the repetition control circuit 41 shown in FIG.5B through a terminal 104. The repetition control circuit 41 is constructed as shown in FIG.13. Referring to FIG.13, a RS type flip-flop 111 is reset by the detection signal POR supplied from the power-on reset generator 40 through a terminal 110. An output signal POLBUSY of the flip-flop 111 is supplied to an OR circuit 112 and also to the multiplexers 51a and 51b shown in FIG.5A. When the signal POLBUSY is kept at the low level, the multiplexers 51a and 51b select the address signals derived from the counters 49 and 50, respectively. The OR circuit 112 produces the control signal POLCLR. The control signal POLCLR is supplied through a terminal 113 to the source clock generator 43, the flip-flops 44 and 45, the counters 49 and 50, and the sense amplifier 58 shown in FIG.5A. Additionally, the control signal POLCLR sets a JK-type flip-flop 114, and clears a D-type flip-flop 115. After reset, the flip-flop 114 is cleared by an output of an AND circuit 119, which performs an AND operation for the word selecting signal R0, the column gate signal C0 and the clock signal ICK2. After that, the flip-flop 114 is set in synchronism with the clock signal ICK1 supplied through a terminal 120 when the verify fail signal F supplied from the comparator 75 through a terminal 121 is kept at the low level. When the verify fail signal F is changed over to the high level, a Q -terminal output of the flip-flop 114 is switched to the low level and is supplied to a D-terminal of the flip-flop 115. The flip-flop 115 latches the Q -terminal output of the flip-flop 114 after all the memory contents of the EPROM matrix 56 are loaded to the macro-cell 24 and the word selecting signal R0 is applied thereto again. The flip-flop 115 latches the high level when all the memory contents of the EPROM matrix 56 have been correctly loaded to the macro-cell 24 in the previous loading operation. Therefore the Q-terminal output of the flip-flop 115 is switched to the high level. Hence, the control signal POLCLR is switched to the high level. Then the power-on load circuit 31 is kept inactive. At this time, the Q-terminal output of the flip-flop 111 is supplied to the flip flops 114 and 115 via the OR circuit 112, and thereby the flip-flop 115 is cleared. On the other hand, when an error occurs in the previous loading operation, the flip-flop 115 latches the low level. Therefore, the states of the flip-flop 111 and the flip-flop 115 are not changed. The macro-cell 24 includes circuits as shown in FIGS.14A through 14D, for example. Signals OR1 and OR2 which are supplied from the sense amplifier 30 shown in FIG.4, are applied to terminals 130a and 130b of the macro-cell 24, respectively. Terminals 131a through 131u are supplied with the corresponding control signals (21 bits) which are supplied from the registers 81 to 83 through the terminals 81a, 82a and 83a shown in FIG.11A. Each of the switches 141 to 144, and 146 to 155 selects a signal applied to a terminal 'a' when the corresponding control signal is kept at the high level. On the other hand, when the control signal is kept at the low level, the each of the switches 141 to 144 and 146 to 155 selects a signal applied to a terminal 'b'. Similarly, switches 145, 156 and 157 select one signal out of the signals applied to the terminals 'a', 'b' and 'c', and 'a' to 'd', and 'a' to 'h', respectively, depending on a corresponding 2-bit or 3-bit control signal applied thereto. For example, the switch 145 selects one out of the signals OR2, XOR and IN, depending on the 2-bit control signal applied to the terminals 131e and 131f. In FIG.14A, set signals such as SETA and SETB, and clear signals such as CLRA and CLRB are supplied from the sense amplifier 30. A tri-state buffer 160 shown in FIG.14B constructs a part of the input/output buffer 23 shown in FIG.4. When an output enable signal OE supplied from the OR array 29 through the sense amplifier 30, is kept at the low level, the tri-state buffer 160 produces no output signal. On the other hand, when the control signal OE is kept at the high level, the tri-state buffer 160 passes an output of the switch 131p. A terminal 161 connected to the tri-state buffer 160 corresponds to one of the terminals 20₁ to 20 n shown in FIG.4. A circuit shown in FIG.14C functions as an input buffer portion provided in the input/output buffer 23. The illustrated circuit comprises an OR circuit 165 and an inverter 166. An input signal is supplied to a terminal which is one of the terminals 20₁ to 20 n from the external circuit (not shown). FIG.14D shows an arrangement of a feedback input buffer portion formed in the input/output buffer 25 shown in FIG.4. The switch 157 receives the signals as shown in FIG.14D. For example, when the input terminal 'a' is brought into contact with the output terminal in accordance with the control signals applied to the terminals 131s, 131t and 131u, the signal OR1 supplied from the OR array 29 is fed back to the AND array 26. For example, when the input terminal 'f' is selected, the input data IN from the external circuit is supplied to the AND array 26. FIG.15 is a schematic plan view of an example of a semiconductor chip of the programmable logic device according to the present invention. On a semiconductor chip 200, there are provided a plurality of macro-cells 24, the AND array 26, the OR array 29 and the EPROM matrix 56. According to the present invention, the programmable non-volatile memory elements used for controlling the switches are arranged like a matrix, and therefore they can be formed so as to be grouped in an arbitrary area of the semiconductor chip as shown in FIG.15. Therefore, the degree of freedom of design of layout of patterns can be facilitated. Further, the write-in and read-out circuit is provided in common to the plurality of non-volatile memory elements for controlling the switches. Therefore, expanded functions can be obtained with ease. For example, a conventional programmable logic device having 24 pins such as EP600 manufactured by Altera, has approximately 100 switches. On the other hand, the present invention makes it possible to provide a programmable logic device of the 24-pin type having 200 to 300 switches or over.

Claims: A programmable logic device comprising input/output buffer means (23) for passing an input signal and an output signal from and to an external circuit; logic array means (26, 29) for performing a logic operation on a signal applied thereto; and switching means (24) including switches (141 - 157) for switching signal lines provided between the logic array means and the input/output buffer means and feedback lines between an input and and output of the logic array means, so as to alter the said logic operation; matrix means (56) comprising a plurality of non-volatile memory elements (62) arranged like a matrix being provided for the respective switches, a memory content stored in each of the non-volatile memory elements being used for controlling a switching operation of a corresponding switch; characterized by read-out means (40, 42, 48, 52, 53, 54 57, 58) for reading out the contents of the plurality of non-volatile memory elements; and a plurality of register means (81 - 83) for storing the contents of the non-volatile memory elements (62) read out by the read-out means; the switching means and plurality of register means being separately disposed on a chip and the read-out means and plurality of register means being connected to each other by a common bus; and in that the read-out means responds to a detecting signal, and selectively transfers control information to a corresponding one of the plurality of register means via the common bus; and in that the read-out means comprises detecting means (40) for detecting power-ON of the device and for generating the said detection signal, whereby when the detecting means (40) detects the power-ON and generates the detection signal, the read-out means sends the contents of the plurality of non-volatile memory elements (62) to the plurality of register means (81 - 83), and in that switching operations of the switches (141 - 157) are controlled by the contents of the plurality of non-volatile memory elements stored in the plurality of register means, and by verify means (41, 75) for verifying whether the contents of the non-volatile memory elements which are read out from the plurality of register means (81 - 83) coincide with the contents of the plurality of non-volatile memory elements (62) which are read out therefrom and for controlling the read-out means, based on a verified result, so as to read out the contents of the plurality of non-volatile memory elements, starting from a predetermined beginning non-volatile memory element out of the plurality of non-volatile memory elements. A programmable logic device as claimed in claim 1, characterized in that the read-out means comprises clock generating means (42) for generating a clock signal, address generating means (48, 53, 54) for generating an address to be supplied to the plurality of non-volatile memory elements, and sense amplifier means (58) for amplifying and supplying the read-out contents of the plurality of non-volatile memory elements to the plurality of register means. A programmable logic device as claimed in either of claims 1 or 2, characterized in that the device further comprises write-in means (51a, 51b, 67) for writing data into the plurality of non-volatile memory elements. A programmable logic device as claimed in any of claims 1 to 3, characterized in that the plurality of register means (81- 83) comprises a plurality of registers (81 - 83) for storing contents of corresponding plurality of non-volatile memory elements. A programmable logic device as claimed in claim 4, characterized in that the device further comprises means (76) for generating a write enable signal which enables one of the plurality of registers in response to a part of an address supplied to the plurality of non-volatile memory means from the read-out means. A programmable logic device as claimed in claim 2, characterized in that the clock generating means generates a first clock signal (ICK1) and a second clock signal (ICK2) which lags behind the first clock signal by 90°, and in that the address generating means (48) supplies the plurality of non-volatile memory elements arranged like the matrix with the address in synchronism with the first and clock signals (ICK1 and ICK2). A programmable logic device as claimed in any of claims 1 to 6, characterized in that the plurality of non-volatile memory elements (62) comprises electrically programmable random access memory cells. A programmable logic device as claimed in claim 2, characterized in that the matrix means comprises word lines (60₁ - 60₂₀) and bit lines (61₁ - 61₂₁) between which the plurality of non-volatile memory elements are connected, and in that the word lines are coupled with the address generating means (48, 53, 54) and the bit lines are coupled with the sense amplifier means (58). A programmable logic device as claimed in claim 2, characterized in that the read-out means further comprises multiplexer means (57) for multiplexing the contents of the plurality of non-volatile memory elements, the multiplexed contents being supplied to the sense amplifier means.

Inventors: ITANO KIYOSHI, SHIMBAYASHI KOHJI, ITANO, KIYOSHI, SHIMBAYASHI, KOHJI
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1988
Main classification: H03K19
IPC codes: G06F7, H03K19