METHOD FOR MAKING CAPACITORS IN CMOS AND NMOS PROCESSES

Abstract: In this process for making capacitors in CMOS processes, the upper plate (22) of the capacitors is obtained through an appropriate masking step, also used, alone or together with further successive steps, for the definition of the gate regions of the transistors, and the lower plate (20) of the capacitors is defined exploiting one of the masks (30', 30'') used for the definition of the upper plate or of the source-­ drain regions of the complementary transistors, allowing thereby the manufacture of capacitors with few masking steps.

Description: The present invention relates to a method for making capacitors in CMOS and NMOS processes as defined in the claims. As is known, Complementary Metal Oxide Silicon (CMOS) technology has been playing, for a few years, an important role in the integrated-circuit industry, by virtue of its substantially nil quiescent-state power consumption, as well as of its high switching speed, its compatibility with bipolar devices and its immunity to radiations. However, CMOS circuits are intrinsically less dense and more complicated than MOS integrated circuits which employ a single type of transistors. In fact, an NMOS structure typically requires, for its production, the deposition of seven layers using five masking steps, while a CMOS structure requires the deposition of twelve layers by means of ten masking steps. In particular, a currently used method for making CMOS devices including capacitors comprises forming, in a substrate with a first conductivity type, of a well of the opposite conductivity type by means of an appropriate masking step, definition (delimitation) of the active areas by means of an appropriate mask, implant and diffusion of appropriate ions for the definition of the insulation regions at junctions between regions with opposite conductivity type, field oxidation, for the obtainment of an intermediate structure, as shown for example in figure 1, comprising a substrate including an active region in which a transistor is to be provided and a region in which at least one capacitor is to be formed, and furthermore comprising a well with opposite conductivity in which the complementary transistor is to be produced. Subsequently, starting from this structure, a gate oxidation step, leading to the formation of an oxide layer, a masking step for the adjustment of the threshold, in which the region of the well remains uncovered for implanting boron ions, deposition of a first polysilicon layer, doping thereof by deposition of POCl₃, a masking step on the first polysilicon layer for the definition of the lower plate of the capacitor and of the gate regions of the complementary transistors are carried out. Then a structure similar to the intermediate one illustrated in figure 3 is obtained, showing the polysilicon portions constituting the gate of the complementary transistors and the lower plate of the capacitor. Subsequently the polysilicon is surface oxidated, a second polysilicon layer is deposited, the rear polysilicon is etched away, doping POCl₃ is further deposited, a further masking step covering only the region of the capacitor is carried out for the definition of the upper plate of said capacitor, with subsequent etching of the uncovered regions of the second polysilicon layer. Accordingly, a structure formed by the intermediate structure of figure 1 surmounted by the gate regions of the complementary transistors and by the capacitor formed by the two polysilicon layers, separated by an oxide layer is obtained. Then a further masking step is performed for the definition of the source-drain regions of the well, then the uncovered gate oxide is etched away, arsenic is implanted, the mask is removed and the surface is reoxidized. A further masking step is then performed for the definition of the source and drain regions of the transistor (S) in the substrate, with subsequent boron implant through the oxide covering the substrate. Then the masking layer is removed and the source and drain regions in the well and in the substrate are diffused. The process then continues with deposition of insulating layers of Vapox (Vapour deposited oxide) and BPSG (Boron Phosphorus Sylicon Glass), with reflow, then opening of the contacts, deposition of the metal layer, the metal mask (with etching), the deposition of final P-Vapox and the pad mask. In US-A-4 577 390 a similar technique is employed to form capacitors in a CMOS structure. The dielectric layer is formed from a composite oxide/nitride film. Accordingly, for making the capacitor and the CMOS transistors, five masks are necessary, and precisely a first mask for the adjustment of the threshold, a second mask for the definition of the lower plate of the capacitor and of the gate regions of the transistors, a third mask for the definition of the upper plate of the capacitor, a fourth mask for forming the source and drain regions in the well, and a fifth mask for forming the source and drain regions in the substrate. However, in view of the relatively high cost of each masking step, the need is felt to modify the known production process so as to reduce the number of production steps, in particular of masking steps and of used masks. Accordingly, the aim of the present invention is to provide a method for making capacitors in CMOS and NMOS processes which entails reduction of the production steps and in particular of the masking steps required for the manufacture of said devices. Within this aim, a particular object of the present invention is to provide a method which reduces the problems of registration of the successive masks used during this method. Still another object of the present invention is to provide a method which comprises process steps which are already known per se and used in the manufacture of integrated devices, so as to allow the use of machines commonly used in the electronics industry. Not least object of the present invention is to provide a method for making devices having electric characteristics comparable or actually improved with respect to those of devices produced according to known processes. The indicated aim, the mentioned objects and others which will become apparent hereinafter are achieved by a method for making capacitors in CMOS and NMOS processes according to the invention, as indicated in the accompanying claims. The characteristics and advantages of the invention will become apparent from the description of preferred but not exclusive embodiments, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figures 1 to 11 are sectional perspective views of a semiconductor wafer at different steps of a first embodiment of the method according to the invention; and figures 12 to 16 are views, similar to the previous ones, to illustrate further making steps corresponding to those shown in figures 5 to 10 according to a different embodiment of the inventive method. Reference should initially be made to figure 1, illustrating an intermediate structure including a substrate 1 with N-type conductivity with orientation [100] and 2.5-3 Ω/cm resistivity, in which a P-well 2 is formed. In the structure of figure 1 the N⁺-regions 3 (doped with phosphorus) and the P⁺-regions 4 (doped with boron) have already been formed The portions of field oxide 5, surrounding the active region indicated at 10 in the substrate and the active region 12 in the well 2 and covering the region 11 on which one or more capacitors are to be formed are furthermore visible. The surface of the structure of figure 1 is covered by a gate oxide layer 6 having a thickness equal to 65 nm (650 Å). Starting from the structure of figure 1, similarly to the prior art, a threshold adjustment mask is deposited, as illustrated in figure 2. As can be seen, the mask 15 covers the entire surface of the intermediate structure except the window 16 at the well 2. Then boron ions are implanted, as symbolized in figure 2 by the arrows 17, for the adjustment of the threshold. Then the resist layer constituting the mask 15 is removed and a first layer of polysilicon with thickness of 450 nm (4500 Å) is deposited, as indicated in figure 3 by the layer 20. Then, always in a known manner, doping POCl₃ is deposited so as to obtain a resistance V/I mono = 3-4 Ω . Differently from the prior art, which comprised at this stage the deposition of a first mask for the definition of the lower plate of the capacitor and of the gate regions, according to the invention the surface of the polysilicon layer 20 is oxidized and a second polysilicon layer with thickness equal to 450 nm (4500 Å) is then deposited. The structure illustrated in figure 4 is thus obtained, with the oxide layer 21 being superimposed on the first polysilicon layer 20 and the second polysilicon layer 22 superimposed on the oxide layer 21. Then the polysilicon is etched away in the rearward regions in a known manner, and thereafter doping by means of POCl₃ is carried out to obtain resistance V/I mono = 3-4 Ω . A masking step is then performed for the removal of portions of the second polysilicon layer. The mask shown in figure 5 is thus obtained, constituted by the resist portion 23′ covering the layer 22 at the region in which the gate of the N-channel transistor is to be formed inside the P-well, by the portion 23″, covering the layer 22 at the gate of the P-channel transistor to be formed in the substrate 1, and by the portion 23‴, connected to 23″, at the capacitor. Then the uncovered portions of the polysilicon layer 22 and the portions, consequently left uncovered, of the oxide layer 21 are etched away; subsequently the mask 23 is removed. Thus the structure illustrated in figure 6 is obtained, wherein above the first polysilicon layer 20 gate regions 21′ and 21″ and capacitor regions 21‴, remained from the oxide layer, and the corresponding portions 22′ 22″ and 22‴ of the second polysilicon layer are visible. Then the mask 25 for the definition of the source and drain regions in the well 2 is deposited, as shown in figure 7. As can be seen, said mask, which is identical to the one for threshold adjustment shown in figure 2, has a window 26 at the well 2. Then the uncovered regions of the polysilicon 20 are etched away, with simultaneous removal also of the portion 22′, and then the uncovered gate oxide (layer 21′) is also etched away, with removal of the uncovered regions of the oxide 6. Thus the structure of figure 8 is obtained, wherein 6′ and 6″ indicate the remaining portions of the first oxide layer, and 20′ and 20″ indicate the remaining portions of the first polysilicon layer, respectively at the well 2 and at the further parts of the device. Then arsenic is implanted, as symbolised in figure 8 by the arrows 28. Then the resist constituting the mask 25 is removed and the surface is reoxidized, with the obtainment of a layer 27 which covers the entire surface of the involved structure, as shown in figure 9. Then a further masking step is performed for the obtainment of the source-drain mask of the substrate, as shown in figure 10, wherein the portion 30′ of the mask covering the well region 2 and the portion 30″ which covers the region of the capacitor are visible. This mask has a window (indicated in the figure at 31) which leaves uncovered the surface of the structure at the active area of the substrate and at the field oxide region surrounding the capacitor. Then the uncovered portions of the oxide layer 27 and the portions, thus uncovered, of the first polysilicon layer 20″ are etched away, with simultaneous removal also of the remaining portion 22′ of the second polysilicon layer. Then boron is implanted through the oxide layer 6″ for the obtainment of the source and drain regions of the transistor formed in the substrate. By removing the masking resist, and possibly by performing a further oxidation step, the structure of figure 11 is thus obtained, with an oxide layer 35 covering the entire face of the structure including the substrate 1, the well 2, the insulations 3 and 4, the field oxide regions 5, the source and drain regions 33, 34 and the polysilicon gate regions 20′ and 20‴. Then the further known steps for forming the passivation layers and the metal layers follow. As can be observed, in practice, according to the embodiment shown in the preceding figures, for making the capacitor and the complementary transistors only four masks are sufficient, and precisely the mask 15 (figure 2) for threshold adjustment, the mask 23′-23‴ (figure 5) for the definition of the upper plate of the capacitor and of the regions, in the upper polysilicon layer 22, overlying the portions of the first polysilicon layer 20 in which the gate regions are to be formed, the mask (figures 7 and 8) for source and drain regions in the well 2, and the mask 30′-30‴ (figure 10) for source and drain regions in the substrate 1 and the definition of the lower plate of the capacitor. Essentially, the mask for the source and drain regions in the substrate is employed for the definition of the second plate of the capacitor, thus eliminating the specific masking step provided for this purpose according to the prior art. Figures 12 to 16 are successive views of a semiconductor structure during different capacitor production steps, according to another embodiment of the method shown with reference to figures 1 to 11. More in particular, this embodiment comprises process steps identical to those shown for the previous example up to obtain the structure of figure 5, which comprises the two polysilicon layers, interleaved by an oxide layer, deposited above the substrate and the mask 23′-23‴ at the regions in which the capacitor and the gate regions are to be formed. According to this embodiment, after etching the upper polysilicon layer and the interposed oxide, the lower polysilicon layer is etched using the same mask. The structure of figure 12 is thus obtained, wherein the elements corresponding to the previously shown embodiment have been indicated by the same reference numerals increased by 100. In the figure, the N-type substrate 101, the P-well 102, the insulations 103 and 104, the field oxide regions 105, the oxide layer 106, the first polysilicon portions 120′, 120″ and 120‴ respectively defining the gate of the transistor to be formed in the well 102, the gate of the transistor to be formed in the substrate 101 and the lower plate of the capacitor, the oxide portions 121′, 121″ and 121‴ and the second polysilicon layer portions 122′, 122″ and 122‴, arranged exactly overlying the remaining portions of the first polysilicon layer are visible. Then a masking step is performed for the obtainment of the mask 125 shown in figure 13. Said mask, identical to the threshold adjustment mask 15, has a window 126 at the well 102, as shown in figure 13. Then the uncovered second polysilicon layer portion 122′, is etched away, obtaining the structure visible in figure 14. The oxide 121′ is then etched, arsenic is implanted to form the source and drain regions of the transistor in the well 102, the masking resist layer 125 is removed and the surface is reoxidized, obtaining the structure shown in figure 15, in which the layers 133 accommodating the implanted arsenic ions, and the oxide layer 127 which covers the entire surface are visible. Then the mask for the source and drain regions in the substrate, made of the resist layer 130 shown in figure 16, is deposited. Said mask, having a window 131 at the active region of the substrate, thus allows a successive implant of boron ions through the oxide layer 127. Subsequently, if desired, the uncovered oxide 127 and the polysilicon are etched, removing the portion 122″. Then the mask 130 is removed and, if necessary, a further reoxidation of the surface is performed. As can be seen from figures 12 to 16, according to this different embodiment the mask defining the upper plate of the capacitor and adapted to define the gate regions of the complementary transistors (by virtue of the selectivity of the oxide and polysilicon etchings) has been used for the definition of the lower plate of the capacitor. In this case, too, the method therefore requires one masking step less than the prior art. The method allows numerous other variations, not illustrated in detail. In particular the fact is stressed that though in the first embodiment the mask for the source and drain regions in the substrate has been used for the definition of the lower plate of the capacitor, and though, in the second embodiment, the mask defining the upper plate of the capacitor is used for the same purpose, an embodiment is conceivable in which the mask used to form the source and drain regions in the well is employed for the definition of the lower plate of the capacitor by appropriately configuring the employed masks. Furthermore the steps for obtaining the source and drain regions within the well and within the substrate may be performed in the inverse sequence, this possibly being even advantageous in order to save oxide etching and reoxidation steps, by virtue of the possibility of implanting the boron ions through an oxide layer. It is furthermore possible to produce capacitors by directly employing the polysilicon lines defining the gate regions of the complementary transistors. In this case the obtained capacitors do not have the square shape illustrated in the figures, but are manufactured by making use of the considerable length of the polysilicon lines above the field oxide regions. In this manner a considerable saving of space and therefore an increase in the density of the device are obtained, which advantage is particularly appreciated in view of the current trend towards miniaturization. As is apparent from the preceding description, the invention fully achieves the intended aim and objects. In particular, by employing one of said masks, it is possible to reduce the number of masking steps, thus reducing the costs of the finished device. The fact should furthermore be stressed that the method according to the invention allows the elimination of the registration errors of the mask of the second polysilicon layer used to produce the upper plate of the capacitors, which risk is present in the method according to the prior art. The invention thus conceived is susceptible to numerous modifications and variations. In particular, besides the possibilities already illustrated above, the fact is stressed that the reoxidation steps may be replaced with the deposition of oxides such as TEOS (Tetraethylorthosilicate) or ONO (Oxide-Nitride-Oxide). The method according to the invention, typically illustrated for a CMOS process with P-well, may furthermore also be applied to CMOS processes in a P-type substrate with N-well by appropriately modifying the sequence of the steps and the implanted ion species, or even to NMOS processes of the type with double polysilicon layer in which the second polysilicon layer is used only for the capacitor plates, by employing again either the mask which defines the upper plate of the capacitor or the mask for patterning the gate regions in order to pattern the lower capacitor plate. The fact is furthermore stressed that the thicknesses and the dopings of the polysilicon layers indicated in the preceding description are merely by way of example. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: A method for making capacitors in CMOS processes, comprising : a first step of depositing a first semiconductor layer (20,120) on a semiconductor substrate (1,101) having a first conductivity type, having at least one active region (10) wherein a first MOS transistor is to be formed, said substrate (1,101) accommodating at least one well (2,102) of a second conductivity type, wherein a second MOS transistor is to be formed, and said substrate (1,101) being partially covered by field oxide and gate oxide layers (5,6,105), a second step of growing an insulating layer (21,121) on said first semiconductor layer, a third step of depositing a second semiconductor layer (22,122) on said insulating layer (21,121), the steps of masking said second semiconductor layer with a first mask (23) covering portions defining a second plate of said capacitors (122"') and gate regions of said first and second transistors, removing portions of said second semiconductor layer not covered by said first mask, masking said semiconductor layers with a second mask (25,125) having at least one first window (26,126) above said well, carrying out a first implantation of ions through said first window to form source and drain regions of said first conductivity type, masking said semiconductor layers with a third mask (30,130) having at least one second window (31,131) above said active region of said substrate, carrying out a second ion implantation through said second window to form source and drain regions of said second conductivity type, using at least one of said first, second and third masks for removing delimitation portions of said first semiconductor layer (20) extending beyond the region covered by said second capacitor plate, thereby defining said first capacitor plate (120"'). A method according to claim 1, characterized in that said third mask (30) is used for removing said delimitation portions. A method according to claims 1 and 2, characterized, after said steps of deposition of said first semiconductor layer (20), growth of said insulating layer, deposition of said second semiconductor layer (22), first masking (23) of said second layer, removal of portions of said second layer, by the steps of: applying said second mask (25), removing portions of said first layer above said well (2), carrying out said first ion implantation (28), applying said third mask (30) having windows (31) above said active region (10) of said substrate (1) and said delimitation portions of said first layer, removing portions of said first layer exposed by said windows, and carrying out said second ion implantation. A method according to claim 1, characterized in that said second mask is used for removing said delimitation portions of said first semiconductor layer. A method according to claims 1 and 4, characterized, after said steps of deposition of said first semiconductor layer, growth, deposition of said second semiconductor layer, first masking of said second layer, removal of portions of said second layer, by the steps of: applying said second mask having windows above said well and said delimitation portions of said first layer, removing portions of said first semiconductor layer exposed by said windows, carrying out said first ion implantation, applying said third mask, removing exposed portions of said first semiconductor layer above said active region, and carrying out said second ion implantation. A method according to claim 3 or 5, characterized in that a step of removal of exposed portions of said insulating layer (21) is carried out immediately after said step of removal of portions of said second layer (22). A method according to claim 3 or 5, characterized in that a step of removal of exposed portions of said insulating layer (21) is carried out immediately after applying said second mask. A method according to claim 3 or 5, characterized in that application of said second mask (25), said first removal of portions of said first semiconductor layer (20) and said first implantation (28) are carried out before said steps of applying said third mask (30), second removal of portions of said first semiconductor layer and second implantation. A method according to claim 3 or 5, characterized in that said application of said third mask, said second removal of exposed portions of said first semiconductor layer and said second implantation are carried out before said steps of applying said second mask, first removal of exposed portions of said first semiconductor layer and said first implantation. A method according to claim 1, characterized in that said first mask (23) is used for removing said delimitation portions of said first semiconductor layer. A method according to claims 1 and 10, characterized, after said steps of deposition of said first semiconductor layer (20), growth of said insulating layer (21), deposition of said second semiconductor layer (22), application of said first mask (23) to said second layer, removal of exposed portions of said second layer (22), by the steps of: removal of exposed portions of said insulating layer (21), removal of exposed portions of said first semiconductor layer (20), application of said second mask (125), said first ion implantation, application of said third mask (130) and said second ion implantation (140). A method according to claim 11, characterized in that said steps of applying said second mask (125) and of first ion implantation are carried out before said steps of applying said third mask (130) and of second ion implantation (140). A method according to claims 11 and 12, characterized, after application of said second mask, by the steps of removal of exposed portions (122′) of said second layer, removal of exposed portions of said insulating layer (121′) and any exposed portions of said insulating layer (106) covering said well (102) prior to said first ion implantation. A method according to claim 11, characterized in that said steps of applying said third mask and of second ion implantation are carried out before said steps of applying said second mask and of first ion implantation. A method for making capacitors in NMOS processes, comprising the steps of: a first step of depositing a first semiconductor layer on a semiconductor substrate having active regions wherein NMOS transistors are to be formed and being partially covered by field oxide and gate oxide layers, a second step of growing an insulating layer on said first semiconductor layer, a third step of depositing a second semiconductor layer, the steps of masking said semiconductor layer with a first mask covering portions defining a second plate of said capacitors and gate regions of said transistors, removing portions of said second semiconductor layer not covered by said first mask, masking said first semiconductor layer with a second mask having at least one window above said active region, implanting ions through said window to form source and drain regions in said active region, using at least one of said first and second masks for removing delimitation portions of said first semiconductor layer extending beyond the region covered by said first capacitor plate, thereby defining the first capacitor plate.

Inventors: MAZZALI, STEFANO
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L27, H01G4