Inductive data communicating apparatus

Abstract: A first device (1) and a second device (2) can be communicated by an electromagnetic coupling. Data to be transmitted from the first device to the second device is converted into pulse signals of different duty ratios in accordance with the H or L level of the transmission data. Further, the oscillation of an oscillator (15) of the first device is intermittently performed in accordance with the H/L level of the pulse signal. Switching elements (39, 40) are provided for a resonance circuit (30) provided in the second device. When data is transmitted from the second device to the first device, the switching elements are turned on or off in accordance with the data. Thus, the electromagnetic coupling is intermittently performed. The oscillator of the first device at that time intermittently executes the oscillation at a third duty ratio.

Description: The present invention relates to a data communicating apparatus for communicating data between first and second devices which are contactlessly closely arranged or approached to each other by using an induction electromagnetic field and to an oscillator which is used in the communicating apparatus and transmits data by intermittently performing the oscillation. Hitherto, for instance, as shown in JP-A-62-63050, there has been proposed a data transmitting apparatus in which a data storing device to store tool data is provided for a tool shank or the like of a machine tool, the data is serially transmitted and written from a data input/output apparatus into the data storing device, or the content written is read out. In such a data transmitting apparatus, the data communication between the data input/output apparatus and the data storing device is performed by using predetermined high frequency signals by frequency shift keying (FSK) modulating those high frequency signals. However, according to the conventional data transmitting apparatus, each of the data storing device and data input/output apparatus needs a PLL circuit or the like to demodulate the FSK signal, so that a large electric power consumption is required. There is a case where an AC voltage induced from the data input/output (I/O) apparatus is rectified and the data storing device uses the resultant rectified voltage as a power source. In such a case, if the electric power consumption is large, the data communication cannot be performed unless the induced voltage is high, so that there is a drawback such that a distance at which the data communication can be performed is short. On the other hand, when the data storing device has a battery, there is a drawback such that the life of the battery is short. The applicant of the present invention has already proposed a system (not published yet) in which in order to reduce the electric power consumption of the data storing device, when data is transmitted from the data storing device to the data I/O apparatus, a resonance frequency of a resonance circuit is discontinuously changed on the basis of the transmission data. In such a case, although the electric power consumption of the data storing device can be reduced, since a communication range is determined by a coupling coefficient between the data storing device and the data I/O apparatus, there is a drawback such that even if an output from the data I/O apparatus is enlarged, the communication distance cannot be increased. On the other hand, as shown in Fig. 16, there has been known a Colpits oscillator which is an LC type oscillator to transmit a signal by the electromagnetic induction and transmits a signal by intermittently performing the oscillation. In the diagram, a collector of a transistor Tr₁ is connected to one end of an LC resonance circuit 51 consisting of a coil L₁ and capacitors C₂₁ and C₂₂. A feedback resistor R₂₁ is connected between a middle point of the coils C₂₁ and C₂₂ and an emitter of the transistor Tr₁. The emitter of the transistor Tr₁ is connected to the ground through an emitter resistor R₂₂. A predetermined DC voltage is applied to one end of the resonance circuit 51. A middle point of resistors R₂₃ and R₂₄ to divide the power source voltage is connected to the base of the transistor Tr₁. A predetermined voltage is applied as a bias to the base of the Tr₁ and the base is connected to the ground by a capacitor C₂₃ in an AC manner. An FET 52 for switching is provided to intermittently apply and shut off the terminal voltage of the base of the Tr₁. The FET 52 is intermittently turned on/off in accordance with an input signal and the base of the oscillating transistor Tr₁ is connected to the ground or a predetermined bias voltage is applied thereto. Thus, as shown in Figs. 17a and 17b, the oscillation can be intermittently performed in correspondence to the input voltage which is applied to the FET 52. However, in such an oscillator, since the base voltage of the Oscillating transistor is controlled and the oscillation is started and stopped, the leading time of the oscillation is slow and the trailing time thereof is also slow, so that even if the supply of the input signal is stopped, the attenuating vibration remains and the amplitude gradually decreases. Thus, there is a drawback such that the oscillation cannot be intermittently performed at a high speed and a data transmission speed cannot be set to a high speed. An inductive data communication apparatus according to the preambles of claims 1 and 4 is known from FR-A-2 500 944. An oscillator according to the preamble of claim 6 is also known from FR-A-2 500 944. The present invention is made in consideration of the foregoing problems in the conventional data transmitting apparatus and it is a technical subject of the invention to enlarge a communication distance by mutually transmitting a transmission signal by using a carrier of a predetermined frequency and by improving a transmission/reception efficiency. Another object of the invention is to make the oscillator of the second device unnecessary. Still another object of the invention is to improve the S/N ratio upon data transmission. Still another object of the invention is to provide an apparatus which can perform the full-duplex data communication by using a carrier of a predetermined frequency. The invention is made in consideration of the foregoing problems of the conventional oscillator and it is a technical subject of the invention to enable the oscillation to be started and stopped in an extremely short time in response to an input signal. According to the invention, the above objects are accomplished by an inductive data communicating apparatus as defined in claim 1. According to the present invention having the above feature, in the first device, the oscillation of the oscillator is intermittently performed at a predetermined period and the duty ratio is changed upon transmission, thereby allowing the binary signal to be transmitted to the second device. In the second device, by detecting the signal transmitted and discriminating on the basis of the predetermined threshold level, the transmission pulse signal is demodulated. Further, the original transmission data signal is demodulated on the basis of the duty ratio of that signal. When data is transmitted from the second device to the first device, in the first device, the oscillation of the oscillator is intermittently performed by the predetermined third duty ratio and the switching elements which are provided for the resonance circuit of the second device are intermittently turned on/off in response to the transmission data signal at the stop of the oscillation, thereby controlling the reverberation obtained in the resonance circuit of the first device. The first device generates the reception gate signal of the stop period of the oscillation on the basis of the transmission pulse signal which is given to the oscillator and fetches only the reverberation by the reception gate signal, thereby detecting the reverberation. The signal is sampled at a predetermined timing of the reception gate signal and given to the first comparator and discriminated on the basis of the predetermined threshold level, thereby demodulating the transmission signal which is derived from the second device. As described above, according to the invention, the half-duplex data transmission of serial data is executed between the first and second devices by using the electromagnetic coupling. Since the data demodulating means of the second device demodulates the signal on the basis of the pulse width, there is no need to use a PLL circuit or the like and the circuit arrangement is relatively simple and the electric power consumption is small. Therefore, when the electric power for the second device is obtained from the first device, the transmission distance can be set to a long distance because of the small electric power consumption. When data is transmitted from the second device to the first device since the reverberation of the signal obtained from the first device is controlled on the basis of the transmission data, if an oscillation output which is given from the first device to the second device is set to a large value, the reverberation level can be raised in association with it. Therefore, since the resonance signal of the reverberation derived from the first device also increases, the data transmission distance can be enlarged. On the other hand, since the resonance frequency of the resonance circuit provided for each of the first and second devices is set to be substantially coincident with the oscillating frequency of the oscillator, there are advantages such that the high efficient data transmission can be performed and the S/N ratio can be also improved. The second device in the data communicating apparatus according to the invention further has a clock discriminating circuit for discriminating an oscillation signal obtained in the second resonance circuit on the basis of a comparison signal of the second comparator and for shaping the discriminated oscillation signal; and above data demodulating means for demodulating the transmission data signal by the transmission pulse signals of the first and second duty ratios on the basis of an output of the second comparator and a clock signal of the clock discriminating circuit upon reception of the data from the first device. According to the invention, in the clock discriminating circuit, the oscillation signal of the oscillator obtained from the first device is shaped to form a clock, the duty ratio is discriminated on the basis of the clock signal, and thereby demodulating the original transmission data signal. Therefore, a clock generator is unnecessary in the second device and the circuit construction is simplified. The first device in the data communicating apparatus according to the invention further has: resonance control means which is connected in parallel with the first resonance circuit and which has a series connection circuit comprising a resistor and an analog switch that is turned on/off by the reception gate signal and which controls Q of the first resonance circuit. When data is transmitted from the second device to the first device, the oscillator of the first device is intermittently driven. When the oscillator is driven, Q of the first resonance circuit is reduced on the basis of an output of the reception gate signal generator and only when the reverberation is received, Q is raised, so that only the reverberation can be accurately detected in the second resonance circuit. Therefore, data can be transmitted from the second device to the first device at a high S/N ratio. According to the invention, the above objects are further accomplished by an inductive data communicating apparatus as defined in claim 4. According to the invention having the above feature, the first device always generates a transmission pulse of the first or second duty ratio on the basis of the transmission data. Upon data transmission, the duty ratio is changed by the transmission data and the oscillation of the oscillator is intermittently performed and the data is transmitted to the second device. The second device detects the transmitted signal and discriminates by the predetermined threshold level, thereby demodulating the transmission pulse signal. Further, the original transmission data signal is demodulated on the basis of the duty ratio of the signal. When data is transmitted from the second device to the first device, in the first device, the oscillation of the oscillator is intermittently performed on the basis of the transmission pulse signal of the first or second duty ratio of an arbitrary data series. When the oscillation is stopped, the switching elements which are provided for the resonance circuit of the second device are turned on or off in accordance with the transmission data signal, thereby controlling the reverberation derived in the resonance circuit of the first device. The first device generates a reception gate signal for the period of time when the oscillation of the oscillator stops and takes out only the reverberation by the reception gate signal and detectes the reverberation. The detected signal is sampled at a predetermined timing of the reception gate signal and given to the first comparator and discriminated on the basis of the predetermined threshold level, thereby demodulating the transmission signal transmitted from the second device. According to the invention, the data transmission can be performed between the first and second devices by using the electromagnetic coupling. When data is transmitted from the second device to the first device, the data transmission is executed by transmitting an arbitrary signal from the first device, so that the full-duplex data transmission can be executed by changing the transmission signal of the first device by the transmission data. Therefore, by sequentially transmitting the data which were mutually transmitted from the other device, the transmission content can be checked every bit. According to the invention, there is further provided an oscillator used in a data communicating apparatus to transmit a signal by the intermittent oscillation, as defined in claim 6. According to the invention having the above feature, the switching element is serially connected to the resonance circuit and the intermittent oscillation is controlled by the switching element. Since a current is directly supplied to the resonance circuit from a power source by closing the switching element, the leading edge can be made sharp. By opening the switching element, the charges in the capacitor of the resonance circuit are discharged through the transistor, so that the oscillation is stopped in an extremely short time. Therefore, according to the invention, the leading time of the oscillation and the stop time of the oscillation can be made extremely fast. Therefore, if the invention is applied to the oscillator of the data communicating apparatus for transmitting a signal by the intermittent oscillation, there are advantages such that the data transmission can be performed at a high speed and the signal transmission can be accurately executed. In the drawings: Fig. 1 is a block diagram showing a whole arrangement of an article identifying system according to an embodiment of a data communicating apparatus of the present invention; Fig. 2 is a block diagram showing an arrangement of a write/read control unit; Fig. 3 is a block diagram showing an arrangement of an ID unit; Figs. 4a to 4g are time charts showing waveforms in respective sections when data is transmitted from the write/read control unit to the ID unit; Figs. 5a to 5ℓ are time charts showing waveforms in respective sections when a signal is transmitted from the ID unit to the write/read control unit; Fig. 6 is a block diagram showing an arrangement of another example of the ID unit; Fig. 7 is a circuit diagram showing a detailed construction of a clock discriminating circuit and its peripheral circuits; Fig. 8 is a block diagram showing another example of the write/read control unit; Figs. 9a to 9m are time charts showing waveforms in respective sections when a signal is transmitted from the ID unit to the write/read control unit; Figs. 10a to 11ℓ show further another embodiment; Figs. 10a to 10g are time charts showing waveforms in respective sections when data is transmitted from the write/read control unit to the ID unit; Figs. 11a to 11ℓ are time charts showing waveforms in respective sections when a signal is transmitted from the ID unit to the write/read control unit; Fig. 12 is a circuit diagram of an oscillator according to an embodiment of the invention; Figs. 13a to 13e are waveform diagrams showing waveforms in respective sections at the start of the oscillation; Figs. 14a to 14d are diagrams showing a current direction of the oscillator; Figs. 15a and 15b are diagrams showing an oscillating state to an oscillation control signal; Fig. 16 is a circuit diagram showing an example of a conventional oscillator; and Figs. 17a and 17b are waveform diagrams showing an oscillation output to a control signal. Fig. 1 is a block diagram showing a whole arrangement of an article identifying system to which a data communicating apparatus according to an embodiment of the present invention is applied. In the diagram, the data communicating apparatus has a write/read control unit 1 as a first device and an ID unit 3 as a second device which is attached to an article 2 or the like. In general, the write/read control unit 1 is fixedly provided and when an article is moved, the ID unit 3 attached to the article 1 approaches the write/read control unit 1. The write/read control unit 1 has first and second coils L₁ and L₂ at positions where the first and second coils can face the ID unit 3 when the ID unit 3 appraoches to the unit 1. The ID unit 3 has a third coil L₃ at a position where the third coil can face the first and second coils. For instance, the write/read control unit 1 is further connected to an upper control unit 4. After the control unit 4 transmitted a transmission control signal CT to the write/read control unit 1, the control unit sends transmission data SD and reads reception data RD which is obtained from the write/read control unit 1. As shown in a detailed block diagram of Fig. 2, the write/read control unit 1 has a clock generator 11 to generate a predetermined clock signal, a time controller 12 to generate a timing signal on the basis of the clock signal, and a transmission pulse generator 13. When the transmission control signal CT is given from the upper control unit 4, the time controller 12 sends a transmission/reception switching signal to the transmission pulse generator 13 and a reception gate generator 14. After the transmission control signal CT was sent, the control unit 4 transmits the transmission data SD to the transmission pulse generator 13. When the transmission/reception switching signal from the time controller 12 indicates the transmission mode, the transmission pulse generator 13 counts the clocks generated from the clock generator 11 for a predetermined period of time and generates a transmission pulse signal having a first or second duty ratio (e.g., 30% or 70%) in accordance with the transmission data SD at a predetermined period of time An output of the transmission pulse generator 13 is input to an oscillator 15. When the transmission/reception switching signal indicates the reception mode, the generator 13 generates a transmission pulse signal of a third duty ratio (for instance, 50%). The oscillator 15 oscillates a signal of a predetermined frequency only when the transmission pulse signal is given from the transmission pulse generator 13. An oscillation output of the oscillator 15 is supplied to the first coil L₁ for transmission through an amplifier 16. The write/read control unit 1 also has the second coil L₂ for reception. A capacitor C₁ is connected in parallel with the coil L₂, thereby constructing a first resonance circuit 17 which resonates with the oscillating frequency of the oscillator 15. An induced voltage developed across the first resonance circuit 17 is applied to an amplifier 18. The amplifier 18 amplifies the induced voltage and gives an output to a detecting circuit 20 through an analog switch 19. When the transmission/reception switching signal generated from the time controller 12 indicates the reception mode, the reception gate generator 14 generates a reception gate signal which is delayed by a predetermined time corresponding to, e.g., one clock from the trailing edge of the transmission pulse. The reception gate signal is given as a gate signal to the analog switch 19. The clock signal of the clock generator 11 and reception gate signal of the reception gate generator 14 is also given to a sampling signal generator 21. The generator 21 gives a signal of a predetermined timing of the reception gate signal, for instance, a signal of one clock just before the trailing edge as a sampling signal to a sample and hold circuit 22. The detecting circuit 20 detects the signal obtained through the analog switch 19, thereby obtaining an integration signal or its envelope signal. The detection signal is input to the sample and hold circuit 22. The sample and hold circuit 22 holds the input signal on the basis of the sampling signal. An output of the sample and hold (S/H) circuit 22 is input to a first comparator 23. The comparator 23 obtains a binary signal by discriminating the signal held on the basis of a predetermined threshold level. An output of the comparator 23 is input as the reception signal RD to the upper control unit 4. As shown in Fig. 3, the ID unit 3 has a second resonance circuit 30 consisting of a coil L₃ and a capacitor C₂ provided on the surface which faces the write/read control unit 1. An induced voltage across the second resonance circuit 30 is given to a detecting circuit 31. The detecting circuit 31 detects the input signal and its output is given to a second comparator 32. A predetermined threshold level is set in the comparator 32. The detection output is discriminated by the predetermined threshold level. An output of the comparator 32 is given to both of a counter 33 and a digital comparator 34. The counter 33 is reset by a leading edge of the output of the comparator 32. The counter 33 counts the clock signals from a clock generator 35 which are input when the output (transmission pulse) of the comparator 32 is held at the H level. A count value is given to the digital comparator 34. The digital comparator 34 compares the count value of the counter 33 with a predetermined value at the timing of the trailing edge of the output of the comparator 32, thereby obtaining the "L" or "H" level output depending on whether the count value exceeds the predetermined value or not. An output of the digital comparator 34 is input to a memory control unit 36. A memory 37 serving as memory means of the ID unit 3 is connected to the memory control unit 36. Signals which are transmitted from the write/read control unit 1 are data and command. The memory control unit 36 writes the given data into the memory 37 or reads out the data from the memory 37 on the basis of the command. An output of the memory control unit 36 is given to a reverberation control pulse generator 38. On the basis of the transmission data to be transmitted to the write/read control unit 1 which was read out of the memory 37 by the memory control unit 36 at the timing when the output of the comparator 32 is at the L level, the reverberation control pulse generator 38 generates a reverberation control pulse of a predetermined width when the transmission data is at the L level. FETs 39 and 40 as switching elements are connected through resistors between both ends of the resonance circuit 30 and the ground, respectively. The FETs 39 and 40 function to connect both ends of the resonance circuit 30 to the ground on the basis of the reverberation control pulse from the generator 38, respectively. In the embodiment, the ID unit 3 has a battery 41 as shown in the diagram and a power source is supplied from the battery 41 to each section. The counter 33, digital comparator 34, and clock generator 35 construct data demodulating means for discriminating the transmission data SD on the basis of the output of the comparator 32 having the first or second duty ratio, that is, the transmission pulse signal which is given from the write/read control unit 1. The reverberation control pulse generator 38 and FETs 39 and 40 as the switching elements for connecting both ends of the resonance circuit 30 to the ground construct reverberation control means for controlling the reverberation of the resonance circuit 30. The operation of the embodiment will now be described with reference to time charts. First, when a signal is transmitted from the write/read control unit 1 to the ID unit 3, the transmission control signal CT is sent from the upper control unit 4 to the time controller 12. Thus, the time controller 12 gives the transmission/reception switching signal to the transmission pulse generator 13. After that, as shown in Fig. 4a, the signal of the transmission data SD (for instance, "HLLH" as shown in the diagram) is sent from the upper control unit 4 to the transmission pulse generator 13. Thus, as shown in Fig. 4b, the transmission pulse generator 13 generates the transmission pulse signal of the first or second duty ratio which corresponds to the H or L logic level of the transmission data and is different from each other at a predetermined period T from times t₁, t₃, t₅ and t₆. The oscillation of the oscillator 15 is intermittently performed by the transmission pulse signal as shown in Fig. 4c. Therefore, when the ID unit 3 approaches, as shown in Fig. 4d, a signal of a predetermined amplitude is obtained across the resonance circuit 30 for the driving time of the oscillator 15, that is, for the time intervals from t₁ to t₂, t₃ to t₄, etc. and the signal is attenuated after that. The signal is then detected by the detecting circuit 31 and compared by the comparator 32 on the basis of the predetermined threshold level. Therefore, the same signal as the transmission pulse signal as shown in Fig. 4e is obtained by the comparator 32. The signal is input to the counter 33 and digital comparator 34. When the counting operation is started from time t₁, a count value larger than a predetermined value is obtained in the counter 33 at the time point t₂ when the output of the comparator 32 trails (the transmission pulse of the first duty ratio corresponding to the H level is obtained). When the counting operation is started from time t₃, a count value lower than the predetermined value is derived in the counter 33 at the time point t₄ (the transmission pulse of the second duty ratio corresponding to the L level is obtained). Therefore, the digital comparator 34 discriminates the count value at times t₂ and t₄ and outputs a signal indicative of the result of the discrimination to the memory control unit 36 at a timing which is delayed by one period T than the transmission data SD as shown in Fig. 4f. In this manner, the data can be transmitted from the write/read control unit 1 to the ID unit 3. Different from the FSK signal, since the signal of a predetermined frequency is merely intermittently supplied or shut off, by making the resonance frequency of the resonance circuit 30 coincide with the oscillating frequency of the oscillator 15, the high efficient data transmission can be performed. By increasing the output of the oscillator 15 of the write/read control unit 1, the voltage level induced in the ID unit 3 rises, so that the communication distance can be enlarged by the oscillation output. Next, when data is transmitted from the ID unit 3 to the write/read control unit 1, the transmission/reception switching signal of the time controller 12 of the write/read control unit 1 is switched to the reception mode. The transmission pulse generator 13 generates the transmission pulse signal of a predetermined period T having a predetermined third duty ratio of, e.g., 50% as shown in Fig. 5a. Thus, since the oscillation of the oscillator 15 is periodically intermittently performed, an oscillation signal as shown in Fig. 5b is transferred from the coil L₁ to the ID unit 3. Therefore, the comparator 32 outputs a read clock signal of the duty ratio of 50% as shown in Fig. 5c. On the basis of the read clock signal, the data signal is read out of the memory 37 by the memory control unit 36. Fig. 5d shows an example of the signal in the case where the data read out by the memory control unit 36 is "HLHL". The data signal is input to the reverberation control pulse generator 38. Only when the logic level of the data signal is at the L level, the generator 38 generates a reverberation control pulse of a predetermined width as shown in Fig. 5e at the time point of the trailing edge of the output signal of the comparator 32. The FETs 39 and 40 are turned on by the reverberation control pulse signal. Therefore, when the FETs 39 and 40 are in the off state (the data signal is at the H level), an attenuation signal is caused in the resonance circuit 30 as shown after time t₉ and the like in Fig. 5f. However, since both ends of the resonance circuit 30 are connected to the ground after time t₁₁ when the FETs 39 and 40 are turned on (the data signal is at the L level), a reverberation hardly occurs in the resonance circuit 30 of the ID unit 3. On the other hand, although the signal induced in the resonance circuit 17 by the driving of the coil L₁ of the write/read control unit 1 has a predetermined high amplitude level for the time intervals from t₈ to t₉, t₁₀ to t₁₁, etc. when the oscillator 15 is driven, the reverberation of a low level remains in correspondence to the reverberation of the resonance circuit 30 of the ID unit 3 for the subsequent time intervals from t₉ to t₁₀, t₁₁ to t₁₂, etc.. For a predetermined time interval shorter than the time interval at which the transmission pulse is at the L level, the reception gate signal which is set to the H level as shown in Fig. 5h is generated from the reception gate signal generator 14. The signal induced in the resonance circuit 17 is supplied to the detecting circuit 20 through the analog switch 19 which is closed only for the period of time corresponding to the H level reception gate signal. Just before the reception gate signal trails, as shown in Fig. 5k, the sampling signal is given to the sample and hold circuit 22 and the output of the detecting circuit 20 is sampled and held. Therefore, the output of the S/H circuit 22 is discriminated by the comparator 23 on the basis of the threshold level, so that a signal as shown in Fig. 5ℓ, that is, the memory read signal of Fig. 5d is transferred to the write/read control unit 1 with a delay time of only the transmission period T. In the embodiment, the counter to count the clocks and the digital comparator have been used as the data demodulating means of the ID unit 3. However, various constructions for demodulating the pulse width into the binary signal can be also used. For instance, the data demodulating means can be constructed by an integrating circuit to integrate the signal obtained in the comparator and a comparator to discriminate the integration output by a predetermined threshold level. Although the embodiment shows an example in which an internal battery has been provided as a power source of the ID unit 3, a rectifying and smoothing circuit is connected to the resonance circuit 30 of the ID unit 3 and a DC voltage which is derived from the resonance circuit can be supplied as a power source to each block. In such a case, it is preferable to construct in a manner such that in order to make the average periods of the transmission pulses constant, the transmission data SD which is given from the control unit 4 is further Manchester encoded and the Manchester encoded signal, that is, the "HL" signal with respect to the H logic level or the "LH" signal with regard to the L logic level is given as transmission data to the transmission pulse generator 13, thereby transmitting the transmission data. With this method, although the data transmitting speed becomes 1/2 as compared with the case where the transmission data SD is not Manchester encoded, the average value of the driving times of the oscillator 14 does not fluctuate depending on the time and the oscillation signal of a predetermined average value is given. Consequently, the data transmission can be performed without fluctuating the DC voltage of the ID unit 3. An example in which the clock generator 35 (Fig. 3) is omitted from the ID unit 3 will now be described. Fig. 6 shows a modification of the ID unit 3. In the diagram, the same parts and components as those shown in Fig. 3 are designated by the same reference numerals and their descriptions are omitted. The induced voltage across the second resonance circuit 30 is given to the detecting circuit 31 and a diode bridge 43. The diode bridge 43 full-wave rectifies the induced voltage obtained in the resonance circuit 30 and gives to a voltage regulator 44. The voltage regulator 44 smoothes the rectified voltage and supplies as a constant voltage to each block in the ID unit 3. As mentioned above, a predetermined threshold level is set in the comparator 32. The detection output is discriminated by the threshold level. The output of the comparator 32 is given to a clock discriminating circuit 42, the counter 33, and the digital comparator 34. As shown in the diagram, an input terminal of the clock discriminating circuit 42 is connected to one end of the resonance circuit 30. When the transmission pulse is given, the clock of the oscillating frequency obtained in the resonance circuit 30 is detected by the circuit 42. The clock signal is input to the counter 33. The counter 33 counts the clock signal. A count value of the counter 33 is given to the digital comparator 34 as mentioned above. A detailed construction of the clock discriminating circuit 42 will now be described with reference to Fig. 7. As shown in Fig. 7, one end of the resonance circuit 30 is connected to an input terminal of a buffer amplifier 42a through a parallel connection circuit of a resistor R₁ and a diode D₁ of the clock discriminating circuit 42. A pull-up resistor R₂ is connected between an input terminal of the buffer amplifier 42a and a power source terminal. A clamping diode D₂ is connected between the pull-up resistor R₂ and an output terminal of the comparator 32. When the output of the comparator 32 is at the L level, the diode D₂ fixes an input signal of the buffer amplifier 42a to an almost zero level. The resistor R₁ is provided so as not to reduce the amplitude of the signal of the resonance circuit 30 during that period of time. On the other hand, the diode D₁ is provided to make the input signal of the buffer amplifier 42a quickly trail, a time constant due to an input capacitance of the buffer amplifier 42a and the resister R₁ is set to a small value, and thereby preventing that Q of the resonance circuit 30 largely decreases. The diode D₂ is turned off for a time interval from t₁ to t₂ when the output signal of the comparator 32 is at the H level. A signal of a predetermined amplitude shown in Fig. 4d is given to the buffer amplifier 42a through the resistor R₁. The clock signal is extracted as shown in Fig. 4g and given to the counter 33 and counted. In the embodiment, the oscillation signal obtained from the write/read control unit is rectified and used as a power source of the ID unit 3. Therefore, as mentioned above, it is preferable to construct in a manner such that the transmission data SD which is given from the control unit 4 is further Manchester encoded such that the average periods of the transmission pulse become constant, and the Manchester encoded signal is given as transmission data to the transmission pulse generator 13, thereby transmitting the transmission data. An explanation will now be made with respect to a modification of the write/read control unit 1 which can improve the S/N ratio in the data transmission from the ID unit 3 to the write/read control unit 1. Fig. 8 shows the modification of the write/read control unit 1. In the diagram, the same parts and components as those shown in Fig. 2 are designated by the same reference numerals and their descriptions are omitted. A series circuit of a resistor R₁₁ and an analog switch 26 is connected across the resonance circuit 17 consisting of the coil L₂ and capacitor C₁. Diodes D₁₁ and D₁₂ are connected in the opposite directions to both ends of the resonance circuit 17 in order to limit the amplitude of the signal to a constant value. The analog switch 26 is driven by an inverter 24 to invert the output of the reception gate signal generator 14 and switches the Q of the resonance circuit 17 to a state (Q dump state) in which the resistor R₁₁ is connected and a state in which the resistor R₁₁ is not connected. The output across the resonance circuit 17 is given to the amplifier 18. As mentioned above, the reception gate signal generated from the reception gate signal generator 14 is inverted and given as a control signal to the analog switch 26. The reception gate signal is also input to the analog switch 19 through an on-delay timer 25 having a micro delay time. The resistor R₁₁ and analog switch 26 provided in parallel for the resonance circuit 17 construct resonance control means for controlling the Q of the resonance circuit 17. The operation to transmit data from the ID unit 3 to the write/read control unit 1 will now be described with reference to Figs. 9a to 9m. Figs. 9a to 9m except Fig. 9h are substantially the same as Figs. 5a to 5ℓ. When data is transmitted from the ID unit 3 to the write/read control unit 1, the transmission/reception switching signal of the time controller 12 of the write/read control unit 1 is first switched to the reception mode. The transmission pulse generator 13 generates a transmission pulse signal of a predetermined period T of the predetermined third duty ratio of, e.g., 50% as shown in Fig. 9a. Thus, the oscillation of the oscillator 15 is periodically intermittently performed, so that an oscillation signal as shown in Fig. 9b is transferred from the coil L₁ to the ID unit 3. Therefore, the comparator 32 outputs a read clock signal of a duty ratio of 50% as shown in Fig. 9c. On the basis of the read clock signal, the data signal is read out of the memory 37 by the memory control unit 36. Fig. 9d shows an example of a signal in the case where the "HLHL" signal is read out by the memory control unit 36. The data signal is input to the reverberation control pulse generator 38. Only when the logic level of the data signal is at the L level, the generator 38 generates a reverberation control pulse of a predetermined width as shown in Fig. 9e at a time point of the trailing edge of the output signal of the comparator 32. The FETs 39 and 40 are turned on by the reverberation control pulse signal. Therefore, when the FETs 39 and 40 are in the off state (the data signal is at the H level), an attenuation signal occurs in the resonance circuit 30 as shown after time t₉ and the like in Fig. 9f. However, after time t₁₁ when the FETs 39 and 40 are turned on (the data signal is at the L level), both end of the resonance circuit 30 is connected to the ground, so that a reverberation hardly occurs in the resonance circuit 30 of the ID unit 3. On the other hand, in the write/read control unit 1, a reception gate signal as shown in Fig. 9g is generated from the reception gate signal generator 14. The inverted output of the reception gate signal as shown in Fig. 9h is input to the analog switch 26 of the resonance circuit 17. Therefore, the resistor R₁₁ is connected to the resonance circuit 17 for the time intervals from t₈ to t₁₃ and from t₁₀ to t₁₄ and the Q is dumped, so that the Q is set to a low value. For time interval from t₁₃ to t₁₀, since the resistor R₁₁ is not connected, the Q of the resonance circuit 17 is high and the reverberation caused in the resonance circuit 30 can be easily detected. The analog switch 19 is closed with a predetermined micro delay time than time t₁₃. Consequently, as shown in Figs. 9i and 9j, the reverberation can be induced across the resonance circuit 17 for a time interval from t₁₃ to t₁₀ and the signal is supplied to the detecting circuit 22 through the analog switch 19. Just before the signal as shown in Figs. 9k and 9ℓ is extinguished, the sampling signal is given to the sample and hold circuit 22. Therefore, since the output of the S/H circuit 22 is discriminated by the comparator 23 on the basis of the threshold level, a signal as shown in Fig. 9m is output from the comparator 23. That is, a memory read signal similar to the signal of Fig. 9d is delayed by only the transmission period T and transferred to the write/read control unit 1. An explanation will now be made with respect to an embodiment of an apparatus which can perform the full-duplex data transmission between the write/read control unit 1 and the ID unit 3. Although the circuit arrangements shown in Figs. 1 to 3 are used as they are, the operation differs as will be explained hereinbelow. Only the different points will be described. In Fig. 2, the upper control unit 4 converts the transmission signal into a modified biphase code, which will be explained hereinlater, and gives as the transmission data SD to the transmission pulse generator 13. When the transmission/reception switching signal obtained from the time controller 12 indicates the transmission mode, the transmission pulse generator 13 counts the clocks from the clock generator 11 and generates a transmission pulse signal of the first or second duty ratio such that the duty ratio is set to 7 : 5 when the transmission data SD is at the H level and 3:5 when it is at the L level. The output is given to the oscillator 15. The oscillator 15 oscillates a signal of a predetermined frequency only when the transmission pulse signal is given from the transmission pulse generator 13. The oscillation output is given through the amplifier 16 to the first coil L₁ for transmission. In Fig. 3, the digital comparator 34 compares the count value of the counter 33 with a predetermined count value in response to the leading edge of the output of the comparator 32 and obtains the L or H output depending on whether the count value exceeds the predetermined count value or not. The counter 33, digital comparator 34, and clock generator 35 construct data demodulating means for discriminating the transmission data SD on the basis of the count value of the counter 33, that is, the transmission pulse signal which is given from the write/read control unit 1. The operation of the embodiment will now be described with reference to time charts of Figs. 10a to 10g and 11a to 11ℓ. When a signal is transmitted from the write/read control unit 1 to the ID unit 3, the transmission control signal CT is sent from the upper control unit 4 to the time controller 12. Thus, the time controller 12 supplies the transmission/reception switching signal to the transmission pulse generator 13. Thereafter, the transmission data SD as a modified biphase code shown in Fig. 10b is given from the upper control unit 4 in correspondence to transmission data shown in Fig. 10a. The transmission data SD is a signal which changes to "HL" when the transmission data is at the "0" logic level and to "LH" when the transmission data is at the "1" logic level. It is assumed that the time interval of the H level and the time interval of the L level change at a ratio of 3 : 2. The transmission data SD is given to the transmission pulse generator 13. Accordingly, the transmission pulse generator 13 generates transmission pulses having the first and second duty ratios of the ratios of 7 : 5 and 3 : 5 for the time intervals from t₂₁ to t₂₃ and from t₂₃ to t₂₅ corresponding to the transmission data "HL" as shown in Fig. 10c. The oscillation of the oscillator 15 is intermittently executed by the transmission pulse signal generated as shown in Fig. 10d. Therefore, when the ID unit 3 approaches, a signal of a predetermined amplitude which will be attenuated later is derived across the resonance circuit 30 as shown in Fig. 10e for the driving period of time of the oscillator 15, that is, for the time intervals from t₂₁ to t₂₂, t₂₃ to t₂₄, t₂₅ to t₂₆, etc. The signal is detected by the detecting circuit 31 and compared with a predetermined threshold level. Thus, the same signal as a transmission pulse signal as shown in Fig. 10f is derived from the comparator 32. The signal is then given to the counter 33 and digital comparator 34. When the counting operation is started from time t₂₁, a count value larger than the predetermined value is obtained in the counter 33 at the time point t₂₂ when the output of the comparator 32 trails. When the counting operation is started from time t₂₃, a count value lower than the predetermined value is obtained at the time point t₂₄. Consequently, the digital comparator 34 discriminates the count value at times t₂₂ and t₂₄ and outputs the same signal as the transmission data at a timing which is delayed by one period than the transmission data SD as shown in Fig. 10g. In this manner, data can be transmitted from the write/read control unit 1 to the ID unit 3. Since the transmission pulse of the duty ratio of 7 : 5 for the H level of the transmission data SD and the duty ratio of 3 : 5 for the L level of the transmission data SD is used, the time intervals when the oscillator 15 outputs the oscillation output largely differ such as 7 : 3. Thus, the discrimination can be certainly executed without confusing those time intervals and the correct reception data can be derived. Next, when data is transmitted from the ID unit 3 to the write/read control unit 1, the transmission/reception switching signal of the time controller 12 of the write/read control unit 1 is switched to the reception mode. The transmission pulse generator 13 alternately generates the transmission pulse signals of the first and second duty ratios corresponding to arbitrary transmission data, e.g., "HLHL ..." as shown in Fig. 11a. Thus, since the oscillation of the oscillator 15 is periodically intermittently executed, an oscillation signal as shown in Fig. 11b is transferred from the coil L₁ to the ID unit 3. Therefore, the comparator 32 outputs a read clock signal corresponding to the transmission pulse as shown in Fig. 11c. The data signal is read out of the memory 37 by the memory control unit 36 on the basis of the read clock signal. Fig. 11d shows an example of the signal in the case where the signal read out by the memory control unit 36 is "HLLHL ..." and the signal is input to the reverberation control pulse generator 38. The generator 38 outputs a reverberation control pulse of a predetermined width as shown in Fig. 11e in response to the trailing edge of the output signal of the comparator 32 when the logic level of the read signal is at the L level. The reverberation control pulse signal is given to the FETs 39 and 40 and the FETs are turned on. Therefore, when the FETs 39 and 40 are in the off state, an attenuation signal occurs in the resonance circuit 30 as shown at time interval after time t₂₉, etc. in Fig. 11f. However, since both ends of the resonance circuit 30 are connected to the ground after time t₃₁ when the FETs 39 and 40 are turned on, a reverberation hardly occurs in the resonance circuit 30 of the ID unit 3. On the other hand, the signal obtained in the resonance circuit 17 of the write/read control unit 1 has a predetermined high amplitude level for the time intervals from t₂₈ to t₂₉, t₃₀ to t₃₁, etc. when the oscillator 15 is driven. However, the reverberation of a low level remains or does not remian in dependence on the presence or absence of the reverberation in the resonance circuit 30 of the ID unit 3 for the subsequent time intervals from t₂₉ to t₃₀, t₃₁ to t₃₂, etc.. The reception gate signal is generated from the reception gate signal generator 14 as shown in Fig. 11h at a predetermined period shorter than the period when the transmission pulse is at the L level. The reverberation signal is supplied to the detecting circuit 20 through the analog switch 19 which is closed for only the period of time when the reception gate signal is generated. Just before the reception gate signal trails, the sampling signal is input to the sample and hold circuit 22 as shown in Fig. 11k. Since the output of the S/H circuit 22 is compared with the threshold value by the comparator 23, a signal as shown in Fig. 11ℓ, that is, a memory read signal similar to the signal of Fig. 11d is delayed by the transmission period and the delayed signal is transferred to the write/read control unit 1. In the embodiment, the operation in the case of alternately performing the data transmission between the ID unit 3 and the write/read control unit 1 has been described. However, when data is transmitted from the ID unit 3 to the control unit 1, as shown in Fig. 11a, the transmission pulse can be also formed on the basis of the actual transmission data to be transmitted from control unit 1 to ID unit 3, so that the data transmission between the ID unit 3 and the write/read control unit 1 can be simultaneously performed by the full-duplex communication. Consequently, when data is transmitted from the write/read control unit 1, by returning the data received by the ID unit from the ID unit 3 with the delay time of one period, the data is checked and the data transmission can be certainly accomplished. In a manner similar to the above, even when transmitting data from the ID unit 3, by immediately returning the received data from the write/read control unit 1, the reliability in the data transmission can be improved. In the embodiment, when data is transmitted from the write/read control unit 1 to the ID unit 3, the data is transmitted by using the modified Manchester code. However, the transmission signal can be also directly transmitted as transmission data. In such a case, data can be transmitted at a high speed as compared with the case where the Manchester code is used. A preferred practical example of the oscillator 15 (including the amplifier 16) will now be described as a last example. Fig. 12 is a circuit diagram showing an oscillator which is used as the oscillator 15. In the diagram, the same parts and components as those in the conventional apparatus shown in Fig. 16 are designated by the same reference numerals. Even in the embodiment, the resonance coil L₁ and capacitors C₂₁ and C₂₂ are also provided and construct the resonance circuit 51. One end of the resonance circuit 51 is connected to the collector of the transistor Tr₁. The middle point of the capacitors C₂₁ and C₂₂ is connected to the emitter of the transistor Tr₁ through the resistor R₂₁. The emitter resistor R₂₂ is connected between the emitter and the ground. A voltage dividing circuit consisting of biasing resistors R₂₃ and R₂₄ is connected to the base of the transistor Tr₁. A capacitor C₂₃ to connect the base to the ground in a high frequency manner is connected between the base and the ground in a manner similar to the conventional apparatus mentioned before. In the embodiment, a switching element consisting of an FET 53 is arranged between the coil L₁ and the capacitor C₂₁ in the resonance circuit 51 as shown in the diagram. A drain of the FET 53 is connected to the coil L₁ and a source is connected to both of the capacitor C₂₁ and the power source side. A resistor R₂₅ is connected between the gate and source of the FET 53. An FET 54 whose source is connected to the ground is provided as a switching element to turn on or off the FET 53. A drain of the FET 54 is connected to a gate of the FET 53 through a resistor R₂₆. A gate of the FET 54 is connected to a signal input terminal for intermittently executing the oscillation. The operation of the embodiment will now be described. First, as shown in Fig. 13a, by giving an H level oscillation control signal to the gate of the FET 54 at time t₄₁, the FET 54 is turned on and the FET 53 is also made conductive. Thus, since a predetermined voltage is applied to the base of the transistor Tr₁, the transistor Tr₁ is soon turned on and a collector current flows through the transistor Tr₁. At this time, of the current flowing through the FET 53 shown as a switch in Fig. 14a and the coil L₁, a current I₁ passes through the capacitors C₂₂ and C₂₁ and is refluxed in the resonance circuit 51, a current I₂ flows into the collector of the transistor Tr₁ and flows as a resonance current to the resonance circuit 51 through the resistor R₂₁ and capacitor C₂₁ and a current I₃ passes through the transistor Tr₁ and resistor R₂₂ and flows to the ground. Therefore, as shown in Figs. 13b and 13c, the collector voltage of the transistor Tr₁ suddenly rises and the emitter voltage also increases. Although the transistor Tr₁ is turned off at time t₄₂ when the emitter voltage exceeds the base voltage, the current flowing through the coil L₁ of the resonance circuit 51 becomes the current I₁ which is circulated through the capacitors C₂₂ and C₂₁ and a current I₄ flowing through the capacitor C₂₂, resistor R₂₁, and emitter resistor R₂₂ as shown in Fig. 14b, so that the collector potential and emitter potential of the transistor Tr₁ sebsequently rise as shown in Figs. 13b and 13c. When the collector voltage reaches the level which is about twice as the power source voltage, the direction of the current flowing through the resonance circuit 51 is inverted. As shown in Fig. 14c, a current I₅ flows to the coil L₁ through the capacitors C₂₁ and C₂₂ from the power source. A current I₆ also flows through the capacitor C₂₁ and resistors R₂₁ and R₂₂. As shown in Fig. 13d, the emitter voltage of the transistor Tr₁ gradually decreases due to the voltage drop at the middle point of the capacitors C₂₁ and C₂₂. The transistor Tr₁ is again turned on at time t₄₃ when the emitter voltage is lower than the base voltage. Thus, in addition to the currents I₅ and I₆, a current I₇ flows through the capacitors C₂₁ and C₂₂, transistor Tr₁, and emitter resistor R₂₂ as shown in Fig. 14d and the vibration energy is applied to the capacitors C₂₁ and C₂₂. The current I₆ flowing from the capacitor C₂₁ through the resistors R₂₁ and R₂₂ decreases and the current I₇ increases, thereby reducing the collector voltage as shown in Fig. 13b. After the capacitors C₂₁ and C₂₂ were completely charged, the current direction is again reversed. As shown in Fig. 14a, the current flows from the power source through the coil L₁ to the capacitors C₂₂ and C₂₁ and transistor Tr₁ and the operating mode is returned to the original operation. Therefore, the oscillation rises at the maximum amplitude just after the switching element was turned on. The oscillation can be started at an extremely high speed. When the oscillation is stopped, the gate signal of the FET 54 as shown in Fig. 13a is set to the L level. Thus, since the FETs 54 and 53 are turned off, the current flowing through the resonance circuit 51 is shut off. If the FET 53 is turned off for the time interval when the transistor Tr₁ is in the ON state, none of the currents I₁, I₂, and I₅ flows through the resonance circuit 51, so that the charges in the capacitors C₂₁ and C₂₂ are immediately discharged through the transistor Tr₁ and the oscillation is stopped. If the FET 53 is turned off for the time interval when the transistor Tr₁ is in the OFF state, the transistor Tr₁ is once turned on when the emitter voltage of the transistor Tr₁ decreases. However, since the charges in the capacitors C₂₁ and C₂₂ are similarly discharged at that time, the oscillation is soon stopped. Consequently, when the gate input signal of the FET 54 is set to the L level, the oscillation is stopped within one period of the oscillation. Thus, as shown in Figs. 15a and 15b, the oscillation is intermittently executed in correspondence to the gate input of the FET 54. If the foregoing oscillator is used as the oscillator 15 in Fig. 2 or 8, when the oscillation of the oscillator is intermittently executed in accordance with the transmission pulses and the data transmission is executed, the oscillation is rapidly started or stopped, so that the data transmission speed can be improved. On the other hand, since the amplitude value of the oscillation does not gradually decrease, a possibility of the occurrence of the malfunction can be reduced. Since the foregoing communicating apparatus obtains the data signal from the ID unit 3 by using the reverberation during the stop of the oscillation, the reception mode can be soon set just after the oscillation of the oscillator was stopped. Therefore, the reliability in the data transmission can be also improved. Although the embodiment has been described with respect to the Colpits oscillator, the invention can be also applied to a Hartley oscillator by using a capacitor in place of the coil L₁ of the oscillator and by using a coil having a middle point tap in place of the two capacitors C₂₁ and C₂₂.

Claims: An inductive data communicating apparatus for performing a half-duplex data transmission of serial data between a first device (1) and a second device (3), wherein said first device (1) comprises: an oscillator (15) which has a first coil (L₁) arranged on a surface which can face said second device (3), transmission pulse generating means (13) for generating transmission pulse signals of a predetermined period and for giving the transmission pulse signal of the predetermined period to said oscillator to intermittently perform the oscillation, a first resonance circuit (17) having a resonance frequency that is substantially equal to an oscillating frequency of said oscillator, a detecting circuit (20) for detecting an electromagnetic induction signal obtained in said first resonance circuit, and said second device (3) comprises: a second resonance circuit (30) which has a resonance frequency that is substantially equal to the oscillating frequency of said oscillator of said first device and which includes a third coil (L₃) arranged on the surface that can face said first device, and a detecting circuit (31) to detect a signal obtained in said second resonance circuit, characterized by said transmission pulse generating means (13) generating the transmission pulse signals with a first and a second duty ratio in correspondence to a transmission data signal upon data transmission and a predetermined third duty ratio upon data reception, said first resonance circuit including a second coil (L₂) arranged on the surface that can face the second device (3), said first device (1) further comprising: reception gate signal generating means (14) for receiving a signal corresponding to a transmission pulse of said transmission pulse generating means (13) and for generating a reception gate signal having a timing in the stop phase of said oscillator, said detecting circuit (20) detecting the electromagnetic induction signal obtained in said first resonance circuit for a time when the reception gate signal of said reception gate signal generating means is given, a sample and hold circuit (22) to sample an output of said detecting circuit at a predetermined timing of the reception gate signal, and a first comparator (23) to discriminate a signal held by said sample and hold circuit on the basis of predetermined threshold level, said second device (3) further comprising: a second comparator (32) for reproducing the transmission pulse signal by discriminating a detection output of said detecting circuit by a predetermined threshold level, data demodulating means (33, 34, 35) for demodulating the transmission data signal by the transmission pulse signals having the first and second duty ratios on the basis of an output of said second comparator upon reception of the data from said first device, and reverberation control means (38) which has switching elements (39, 40) connected between said second resonance circuit and the ground for controlling a reverberation that is caused in said second resonance circuit by turning on/off said switching elements in correspondence to the transmission data at the timing for the stop of the oscillation of said oscillator on the basis of the transmission pulse signal of the third duty ratio which is derived from said second comparator upon data transmission to said first device. An apparatus according to claim 1, wherein said second device further has: a clock discriminating circuit (42) for discriminating an oscillation signal obtained in said second resonance circuit on the basis of a comparison signal of said second comparator and for shaping the discriminated oscillation signal; and said data demodulating means for demodulating the transmission data signal by the transmission pulse signals of the first and second duty ratios on the basis of an output of said second comparator and a clock signal of said clock discriminating circuit upon reception of the data from said first device. An apparatus according to claim 1, wherein said first device further has: resonance control means which is connected in parallel with said first resonance circuit and which has a series connection circuit comprising a resistor (R₁₁) and an analog switch (26) that is turned on/off by the reception gate signal and which controls Q of said first resonance circuit. An inductive data communicating apparatus for performing a data transmission of serial data between a first device (1) and a second device (3), wherein said first device (1) comprises: an oscillator (15) which has a first coil (L₁) arranged on a surface that can face said second device (3), transmission pulse generating means (13) for generating transmission pulse signals and for giving the transmission pulse signal to said oscillator to cause said oscillator to intermittently perform the oscillation, a first resonance circuit (17) having a resonance frequency that is substantially equal to an oscillating frequency of said oscillator, a detecting circuit (20) for detecting an electromagnetic induction signal obtained in said first resonance circuit, and said second device (3) comprises: a second resonance circuit (30) which has a resonance frequency that is substantially equal to an oscillating frequency of said oscillator of said first device and includes a third coil (L₃) arranged on the surface that can face said first device, a detecting circuit (31) to detect a signal obtained in said second resonance circuit, characterized by said transmission pulse generating means (13) continously generating the transmission pulse signals with a first or second duty ratio, switching said first and second duty ratios in correspondence to the transmission data signal upon data transmission, said first resonance circuit (17) including a second coil (L₂) arranged on the surface that can face said second device, said first device further comprising: reception gate signal generating means (14) for receiving a signal corresponding to a transmission pulse of said transmission pulse generating means and for generating a reception gate signal having a timing in the stop phase of the oscillation of said oscillator, said detecting circuit (20) detecting the electromagnetic induction signal obtained in said first resonance circuit for a time when the reception gate signal is given by said reception gate signal generating means, a sample and hold circuit (22) to sample an output of said detecting circuit at a predetermined timing of the reception gate signal, and a first comparator (23) to discriminate a signal held by said sample and hold circuit on the basis of a predetermined threshold level, said second device (3) further comprising: a second comparator (32) to reproduce the transmission pulse signal by discriminating the detection output on the basis of a pretermined threshold level, data demodulating means (33, 34, 35) for demodulating the transmission data signal by the transmission pulse signals having the first and second duty ratios on the basis of an output of the second comparator upon reception of the data from said first device, and reverberation control means (38) which has switching elements (39, 40) connected between said second resonance circuit and the ground for controlling a reverberation caused in said second resonance circuit by turnig on/off said switching elements in correspondence to the transmission data at the timing for the stop of the oscillation of said oscillator on the basis of the transmission pulse signal derived from said second comparator upon data transmission to said first device. An apparatus according to claim 4, wherein said oscillator (15) of said first device has: a parallel resonance circuit (51) comprising resonance elements (L₁, C₂₁, C₂₂) including a coil and capacitor; a transistor (Tr₁) whose collector is connected to one end of said parallel resonance circuit and which is fed back to a base from a middle point provided for the resonance elements of said resonance circuit; and a switching element (53) which is arranged between the coil and the capacitors of said resonance circuit for opening or closing said resonance circuit, and wherein the oscillation is intermittently performed by said switching element. An oscillator used in a data communicating apparatus to transmit a signal by intermittently executing an oscillation, said oscillator having: a parallel resonance circuit (51) comprising resonance elements (L₁, C₂₁, C₂₂) including a coil and capacitor; and a transistor (Tr₁) whose collector is connected to one end of said parallel resonance circuit , characterized in that the transistor (Tr₁) is fed back to an emitter from a middle point provided for the resonance elements of said resonance circuit, wherein a switching element (53) to open or close said resonance circuit is provided between the coil (L₁) and the capacitor (C₂₁) of said resonance circuit, and the oscillation is intermittently executed by said switching element (53).

Inventors: FUJISAKA HISATO OMRON TATEISI, HIRAO IICHI OMRON TATEISI ELEC, MIYAKE RYOICHI OMRON TATEISI E, MORIKAWA KAZUNORI OMRON TATEIS, FUJISAKA, HISATO OMRON TATEISI ELECTRONICS CO., HIRAO, IICHI OMRON TATEISI ELECTRONICS CO., MIYAKE, RYOICHI OMRON TATEISI ELECTRONICS CO., MORIKAWA, KAZUNORI OMRON TATEISI ELECTRONICS CO.
Applicants: OMRON TATEISI ELECTRONICS CO, OMRON TATEISI ELECTRONICS CO.
Application year: 1988
Main classification: H04B5
IPC codes: G06K19, H04B5, G06K7