Apparatus and method for performing a shift operation in a multiplier array circuit

Abstract: In floating point opertaions, it is necessary to align the fractions of the exponents before addition or subtraction operations can be executed. This fraction alignment is performed by a shifting operation, typically using dedicated apparatus such as a barrel shifter. While the dedicated apparatus provides high performance in the execution of the shifting operation, this performance is accomplished by reserving a portion of the substrate area to apparatus implementation. To avoid the use of dedicated apparatus, the shifting operation is performed in a multiplier unit, according to the present invention, by entering the number to be shifted in the multiplicand register of the multiplier unit while entering appropriate control signals in the multiplier register. In this manner, a shifting operation can be performed without dedicated apparatus and with minor impact on performance.

Description: This invention relates generally to data processing systems and, more particularly, to apparatus for performing floating point operations. The floating point format, in which a number is represented by a (binary) number or fraction with the decimal point in a predetermined position and a number representing the argument of an exponent, has the advantage that the range of numbers capable of being represented by in a given storage space is greatly expanded. However, in order to add or subtract two numbers in the floating point format, the fractions of the two numbers must first be aligned so that the decimal point is in the appropriate (aligned) position during the operation. A difference is determined between the two number exponent arguments and the difference is used to control the shifting (alignment) of the number fractions. In the related art, the barrel shifter is typically employed to provide the shifting operation. The barrel shifter provides a crossbar switch between the elements of two buses, control signals determining the element of the first bus coupling the element of the second bus. (The barrel shifter is described in Chapter 5, "Introduction to VLSI Systems" by Carver Mead and Lynn Conway, Addison-Wesley Publishing Company (1980).) Although this type of shifting apparatus provides high performance, the number of switches (i.e., transistor gate elements) between the two buses requires a large amount of substrate area when implemented using integrated circuit techniques. A need has therefore been felt for a technique that would permit an alignment (shifting) operation of a binary number that does not involve dedicated apparatus and which does not have an unacceptable impact on performance. A binary shift of a number N by n bit positions gives the same result as the product of the number N and 2 n . Therefore, as disclosed in Patent Abstracts of Japan, Vol. 10, No. 215 (P-481) [2271], 26 July 1986; & JP-A-61 052741 (NEC Corp.) 15.03.1986, a vector multiplier can be used to perform either multiplication or binary shifting. The shift designation signal (n) is input to a shift multiplier generating circuit which generates the shift multiplier (2 n ) by setting a prescribed bit location to logical 1 corresponding to the shift designation signal ( n ), and by setting the other bits to logical 0. A two-input multiplexer selects either the shift multiplier (2 n ) for a shift operation or a mantissa for a multiplication operation, and outputs the selection to one input of the vector multiplier. Although the shift multiplier generating circuit and the multiplexer permits the vector multiplier to perform either a multiply operation or a shift operation, the multiply operation in this case requires an additional delay equal to the delay of the multiplexer, and the shift operation requires a further additional delay equal to the delay of the shift multiplier generating circuit. Parallel multiplier arrays are known that use a series of stages of carry/save adder units. As disclosed in European Patent Application 0,206,762, for example, an array of carry/save adder units implements the method attributed to Booth and has the virtue of working properly on positive and negative, fractional and integer numbers represented in two's complement notation. A particular variant of Booth's method operates on two adjacent bit positions of the multiplier at every generation of an intermediate product. This variant provides a two-fold improvement in speed; first from the multiple shifts preceding generation of the intermediate product, and second from the two-bit look-ahead. To implement this variant, each stage of carry/save adder units receives control signals encoding information from bit positions (2*i)-1, 2*i and (2*i)+1 of the multiplier word. In this manner, each stage of carry/save adder units can form an intermediate sum and carry based on zero times, one times, or two times the multiplicand or the two's complement of the multiplicand word. A similar parallel multiplier array is described in European Patent Application 0,098,685. In this case, however, each stage of carry/save adder units forms an intermediate sum and carry based only on two times, one times, or zero times the multiplicand, or one times the two's complement of the multiplicand. In the present invention, a series of stages of carry/save adder units (251, 253, 255, 257) are operative during a multiply operation for performing a multiplication of a multi-bit multiplicand signal by a multi-bit multiplier signal to generate a multi-bit product signal. The series of stages of carry/save adder units includes a first stage of carry/save adder units (251) having a multi-bit input receiving said multi-bit multiplicand signal and a multi-bit output providing a first intermediate sum, a plurality of intermediate stages of carry/save adder units (253, 255) each having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units and having a multi-bit output applying an intermediate sum to a following one of the stages of carry/save adder units, and a final stage of carry/save adder units (257) having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units (255) and having a multi-bit output providing said multi-bit product signal. Each intermediate sum is shifted a predetermined number of bit positions in being applied to said following one of the stages of carry/save adder units, and each stage of carry/save adder units is responsive to control signals for adding zero, the multiplicand, the multiplicand shifted by one bit position, or the complement of the multiplicand. An encoding circuit (261, 262, 263, 264) is associated with each stage of carry/save adder units, and has multiplication control logic (FIG. 3) operative during a multiply operation for generating the control signals in response to three consecutive bits of the multiplier signal. The present invention is characterized by further including shift control logic operative during a shift operation for generating the control signals for each of the stages of carry/save adder units in response to a multi-bit shift quantity signal and for applying the control signals for each of the stages of carry/save adder units directly from the shift control logic to each of the stages of carry/save adder units, the shift control logic controlling the stages of carry/save adder units to perform an addition of the multi-bit multiplicand or the multi-bit multiplicand shifted by one bit position in a selected one of the stages of carry/save adder units and to perform an addition of zero in the other ones of the stages of carry/save adder units, whereby the multi-bit multiplicand, shifted by a number of bit positions specified by the multi-bit shift quantity signal, appears at the multi-bit output of the final stage of carry/save adder units. Therefore the multiplicand can be shifted by a specified number of bit positions with minor impact on performance while eliminating dedicated shift apparatus. For shifting operations involving large shifts, multiple passes can be used through the series of stages of carry/save adder units. These and other features of the present invention will be understood upon reading of the following description, along with the drawings. FIG. 1 illustrates the input signals and the output signals of the carry/save adder unit according to the present invention. FIG. 2 is a block diagram of a multiplier unit capable of implementing the present invention. FIG. 3 illustrates derivation of the control signals for the 2-bit retirement algorithm as used in the preferred embodiment. Figure 4 illustrates the control signals applied to the carry/save adder unit stages to shift a data signal group from one to eight positions according to the present invention. Referring now to Fig. 1, the input and output signals of the carry/save adder unit 10 for the n th bit position of a carry/save adder unit stage of the present invention is shown. The carry/save adder unit receives a CARRY IN (0; n+1) and a SUM IN (0; n+2) signal. The 0 value designates the signal applied to the first carry/save adder stage for the initial operation involving the multiplicand register, while the n+1 and n+2 values designate bit positions for a prior carry/save adder unit stage which applies these input signals to carry/save adder unit 10. The select circuit 10A, in response to the "times 2" control signal, applies the signal stored in multiplicand register bit position (n-1), MULTIPLICAND IN (n-1), to the carry/save adder unit 10. Otherwise, the signal stored in the multiplicand register bit position (n), MULTIPLICAND IN (n), is applied to carry/save adder unit 10. As a result of the three logic signals and control signals (to be described below) being applied to the carry/save adder unit 10, a CARRY OUT (n) signal and a SUM OUT (n) signal are generated. Referring now to Fig. 2, a block diagram of a multiplier unit (or apparatus), capable of using the present invention, is shown. The multiplier unit includes a multiplicand register 250 and a multiplier register 260. The signals stored in each bit of the multiplicand register 250 can be applied to input terminals of select circuits 251A associated with the first carry/save adder unit stage 251, select circuits 253A associated with the second carry/save adder unit stage 253, select circuits 255A associated with the third carry/save adder unit stage 255 and select circuits 257A associated with the fourth carry/save adder unit stage. The select circuits 251A, 253A, 255A and 257A perform the function illustrated by 10A in Fig. 1 and apply either the signal from the bit positions of the multiplicand register to either the equivalent bit positions of the carry/save adder unit stage or to the equivalent bit positions plus one of the carry/save adder unit stage (equivalent to a multiplication by two). The state of "times 2" control signal (cf. Fig. 1) determines which multiplicand register bit position signal is applied to the carry/save adder unit stage bit position. The electrical coupling between the multiplicand register 250 and the select circuits 251A, 253A, 255A and 257A and the associated carry/save adder unit stages 251, 253, 255 and 257 is illustrated by conducting element 210 for the 7 th multiplicand register bit position and for the 6 th (i.e., n-1) multiplicand register bit position. The output signal of each carry/save adder unit stage is a quantity related to the partial sum of the multiplication. The divergence of the output signals of a carry/save adder unit stage from the true partial product is the result of maintaining the carry signals separate from the sum signals. This separation eliminates the potentially slow combining operation after each carry/save adder unit stage. The look-ahead technique that incorporates the third bit, in addition to the two bits operating on the multiplicand signals (via the carry/save adder stage), provides for the combination of the carry and sum signals in all but the final carry/save adder unit stage. The quantity stored by the fourth (and potentially final) carry/save unit stage 257 is the final result of the multiplication operation. The signals from the fourth carry/save adder unit array 257 are applied to input terminals of the master/slave latch unit stage 249 without bit position shift as illustrated by path 225. However, prior to storing the data group at the output terminals of master/slave latch unit stage 249 in the result register 270, the carry bits must be combined with the sum bits of the partial product. This combining operation is performed in carry/sum combining network 259 after shifting the output signals one position to the right as illustrated by path 230 in Fig. 2. Round-off and sticky bit unit 258 is provided to implement an algorithm compensating for a round-off error in the multiplication operation or to retain information concerning signals removed from the purview of the data processing by the shifting operation. After the combining of the partial sum with the unassimilated carry signals has taken place in the carry/sum combining network 259, the resulting quantity is stored in the result register 270 without shifting as illustrated by path 235 in Fig. 2. In the multiplication unit illustrated in Fig. 2, the apparatus is arranged to perform multiplication involving the two remaining least significant bits of the multiplier register 260 that have not yet been applied to signals of the multiplicand register 250. This procedure is referred to as a two bit retirement (i.e., of the multiplier) algorithm. As a result, the partial sum signals are shifted two positions (to the right) between successive carry/save adder unit stages, while the carry signals are shifted one position to the right. This shifting is illustrated by the arrow 221 from the 3 rd bit position of the first carry/save adder unit stage 251 to the 2 nd bit position (for the carry signal) of second carry/save adder unit stage 253 and by the arrow 222 from the 3 rd bit position of first carry/save adder unit stage 251 to the 1 st bit position (for the partial sum) of the second carry/save adder unit stage 253. Because of the shifting of the partial sums between carry/save adder unit stages, the round-off and sticky bit units 252, 254, 256 and 258 are included to implement strategies minimizing the loss of information resulting from removal of data signals from the signal bit field manipulated by the data processing system. To provide for greater bit position shifts than are possible by a single transit through the multiplier unit (i.e., seven bit position shifts in the apparatus of Fig. 2), apparatus is provided for multiple passes through the multiplier unit. In order to provide multiple passes through multiplier unit, the CARRY OUT and SUM OUT signals from the master/slave latch unit stage are applied to the first carry/save adder unit stage 251 by the electrical coupling illustrated by path 240. The CARRY OUT signal is shifted to the right by one position in this signal transfer, while the SUM OUT signal is shifted two positions to the right, thus maintaining the typical intercarry/save adder unit stage transfer procedure of the multiplier unit. The presence of this path permits shifts of eight bit positions or more to be accommodated by the present invention. The use of the master/slave latch unit stage 249 prevents possible race conditions from occurring when the shifted data signal group is returned to the first carry/save adder unit stage, the signals groups being isolated by the strobing of the signal groups into the slave portion of the latch units. Fig. 2 also illustrates the procedure for implementing the two bit retirement algorithm. The two least significant bits of the multiplier register not previously combined with the multiplicand register plus the next most significant bit are applied to encoding apparatus 261. Based on these signals, the encoding apparatus 261 applies control signals to the first carry/save adder unit stage 251. Referring to Fig. 3, the relationship of the group of signals in the multiplier register to the operation performed on the signals of the multiplicand register and to the control signals for the carry/save adder unit stage is shown for the preferred embodiment. The carry/save adder units can perform multiplication using three control functions. The first function, termed ZERO in Fig. 3, passes the partial product through the carry/save adder unit stage without any operation other than the intercarry/save adder unit stage shift operation being performed thereon. The second function, referred to as ADD in Fig. 3, adds or subtracts one times the signals of the multiplicand register to the partial product applied to the carry/save adder unit stage receiving the control signals. In the preferred embodiment, a logic "1" control signal indicates the addition operation while the logic "0" control signal indicates the subtraction operation. The third function, referred to as SHIFT in Fig. 3, adds 2 times the signals of the multiplicand register to the partial product applied to the carry/save adder unit stage. This "2 times" control function is implemented by select circuit 10A in Fig. 1 and by select circuits 251A, 253A, 255A and 257A in Fig. 2. Thus, when the multiplier register includes a signal group 000, no operation is performed on the partial product, so the control signal group applied to the carry/save adder unit stage is ZERO=1, ADD=- and SHIFT=-. When the group of signals from the multiplier register is 001, the operation on the partial product is an add one times the multiplicand to the partial product and the control signals applied to the carry/save adder unit stage are ZERO=0, ADD=1 and SHIFT=0. Similarly, each group of signals XXX in the multiplier register results in a predetermined group of ZERO, ADD and SHIFT control signals. Referring next to Fig. 4, the control signals required to provide a zero to eight bit position shifting operation, according to the present invention, is shown. When a zero bit position shift is desired, then the control signals ZERO=1, ADD=- and SHIFT=- are applied to the first, second and third carry/save adder unit stage. Thus the signals from the multiplicand register are not operated on in the first three carry/save adder unit stages and the partial product applied to the fourth carry/save adder unit stage is zero. The fourth carry/save unit stage adds one times the multiplicand to the (zero) partial product and shifts the result of the addition (i.e., the contents of the multiplicand register) one position to the left. The left shifting operation is to compensate for the final one position right shift prior to storage of the signal group into the result register. In order to provide a one bit position shift operation, the control signal group ZERO=1, ADD=- and SHIFT=- are applied to the first, second and third carry/save adder unit stage. The control signals ZERO=0, ADD=1 and SHIFT=0 are applied to the fourth carry/save adder unit stage. These groups of control signals cause a zero partial sum to be applied to the fourth carry/save adder array and one times the contents of the multiplicand register to be added to the (zero) partial sum. Because of the one bit position shifting operation prior to the signal group storage into the result register, the contents of the multiplicand register are shifted one position to the right. Fig. 4 illustrates the control signals that will result in zero to seven bit position shifts to the right. The intercarry/save adder unit stage shift of two bit positions and the shift of one bit position prior to storage in the register occurring in the carry/save adder unit stage following the insertion of the contents on the multiplicand register into one of the carry/save adder unit stages. When the control signals ZERO=1, ADD=- and SHIFT=- are applied to all four carry/save adder unit stages, then the signals of the original multiplicand register are applied to the first carry/save adder stage 251 shifted eight positions to the right. The use of carry/save adders to implement the multiply operation eliminates the potentially slow ripple carry operation required for the combination of partial sums of the operation. Only after the final carry/save adder unit stage do the carry signals have to be combined with the associated partial product to provide the result in the multiplier unit. Similarly, the retirement algorithm, by which more than one of the multiplier signals is combined with the multiplicand signals in the carry/save adder unit stage, reduces the number of stages required to perform the operation at the cost of increased complexity of the carry/save adder units. In the present invention, the inherent capability of the multiplier unit to perform a shift operation is used to perform a controllable shift operation. The functions of the carry/save adder unit, without additional apparatus, can provide the operational capability. Therefore, the appropriate signals can be placed in the multiplier register to provide the appropriate control signals to the carry/save adder unit stages. Thus the shifting operation requires only the capability to translate the desired bit position shift quantity into signals that can be entered into the control register or can be applied directly to the carry/save adder unit stages. Because the multiplier unit is implemented for high performance, the shift operation performed in the multiplier unit is relatively fast. In the preferred embodiment, when multiplication operations involving larger data signal groups than can be accommodated by the multiplicand register is to be executed, a wrap-around procedure is employed. The wrap-around procedure is accompanied by a two position shift to the right. This wrap-around shift must be taken into account when shifting operations greater than seven bit positions (i.e., in the example used herein) are required. As illustrated in Fig. 2 and Fig. 4, a complete pass through the multiplier unit by a signal group after which the signal group is reintroduced to the first carry/save adder stage involves an eight position shift, while a pass through the multiplier unit involving signals that are entered in the result register 270 can involve zero to seven bit position shifts. The master/slave latch unit 249 can apply signals to both the carry/sum combining network 259 and to the first carry, save adder unit stage 251. In this manner, multiple passes through the multiplier unit can be accommodated. Although the present invention has been discussed in terms of a two bit retirement procedure, it will be clear that the technique of the present invention can be applied to retirement procedures involving different numbers of bits. Similarly, the present invention has been illustrated for eight bit position fields. It will be clear that the length of the data field, and consequently the registers, can be of different lengths without departing from the invention.

Claims: An apparatus having a series of stages of carry/save adder units (251, 253, 255, 257) operative during a multiply operation for performing a multiplication of a multi-bit multiplicand signal by a multi-bit multiplier signal to generate a multi-bit product signal, said series of stages of carry/save adder units including a first stage of carry/save adder units (251) having a multi-bit input receiving said multi-bit multiplicand signal and a multi-bit output providing a first intermediate sum, a plurality of intermediate stages of carry/save adder units (253, 255) each having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units and having a multi-bit output applying an intermediate sum to a following one of the stages of carry/save adder units, and a final stage of carry/save adder units (257) having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units (255) and having a multi-bit output providing said multi-bit product signal, each intermediate sum being shifted a predetermined number of bit positions in being applied to said following one of the stages of carry/save adder units, each stage of carry/save adder units being responsive to control signals for adding zero, the multiplicand, the multiplicand shifted by one bit position, or the complement of the multiplicand, and said apparatus having an encoding circuit (261, 262, 263, 264) associated with each stage of carry/save adder units, each encoding circuit having multiplication control logic operative during a multiply operation for generating said control signals in response to three consecutive bits of said multiplier signal, characterized in that: said apparatus further includes shift control logic operative during a shift operation for generating said control signals for each of said stages of carry/save adder units in response to a multi-bit shift quantity signal and for applying said control signals for each of said stages of carry/save adder units directly from said shift control logic to each of said stages of carry/save adder units, said shift control logic controlling said stages of carry/save adder units to perform an addition of the multi-bit multiplicand or the multi-bit multiplicand shifted by one bit position in a selected one of said stages of carry/save adder units and to perform an addition of zero in the other ones of said stages of carry/save adder units, whereby the multi-bit multiplicand, shifted by a number of bit positions specified by said multi-bit shift quantity signal, appears at said multi-bit output of said final stage of carry/save adder units. The apparatus of Claim 1, further characterized in that each stage of carry/save adder units includes, for each carry/save adder unit (10), a selector circuit (10A) for selecting an input signal from an associated bit position of said multiplicand signal and a signal from a neighboring bit position of said multiplicand signal, and each of said carry/save adder units provides a sum output signal and a carry output signal in response to a carry input signal, a sum input signal and a selector circuit output signal, and wherein each intermediate sum signal of each intermediate stage of carry/save adder units includes the sum output signals and the carry output signals of the carry/save adder units of said each intermediate stage of carry/save adder units. The apparatus of Claim 2, further characterized in that said apparatus includes a combining network (259) for combining the sum output signals and the carry output signals from the carry/save adder units in said final stage of carry/save adder units. The apparatus of any of Claims 1 to 3, further characterized in that said apparatus includes a one bit position shifting apparatus (230) for shifting the multi-bit product signal of said final stage of carry/save adder units (257) by one bit position. The apparatus of any of Claims 1 to 4, further characterized in that said apparatus includes multiple pass means (240, 249) connecting said multi-bit output of said final stage of carry/save adder units to said first stage of carry/save adder units for passing multi-bit signals through said stages of carry/save adder units a plurality of times. The apparatus of any of Claims 1 to 5, further characterized in that said multiple-pass means includes a stage of latches (249). The apparatus of any of Claims 1 to 6, further characterized in that said apparatus includes round-off and sticky bit units (252, 254, 256, 258) interconnected with said stages of carry/save adder units. A method of operating a series of stages of carry/save adder units (251, 253, 255, 257), said stages of carry/save adder units being operated to multiply a multi-bit multiplicand signal by a multi-bit multiplier signal to generate a multi-bit product signal, said stages of carry/save adder units including a first stage of carry/save adder units (251) having a multi-bit input receiving said multi-bit multiplicand signal and a multi-bit output providing a first intermediate sum, a plurality of intermediate stages of carry/save adder units (253, 255) each having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units and having a multi-bit output applying an intermediate sum to a following one of the stages of carry/save adder units, and a final stage of carry/save adder units (257) having a multi-bit input receiving an intermediate sum from the output of a previous one of the stages of carry/save adder units (253) and having a multi-bit output providing said multi-bit product signal, each intermediate sum being shifted a predetermined number of bit positions in being applied to said following one of the stages of carry/save adder units, each stage of carry/save adder units being responsive to respective control signals for adding zero, the multiplicand, the multiplicand shifted by one bit position, or the complement of the multiplicand, and an encoder unit having an encoding circuit (261, 262, 263, 264) associated with each carry/save adder unit, wherein said multiply operation is performed by generating, for each of said stages of carry/save adder units, said control signals in response to three consecutive bits of said multiplier signal, characterized in that: said method further includes operating said stages of carry/save adder units to a perform a shift operation by generating said control signals for each of said stages of carry/save adder units in shift control logic in response to a multi-bit shift quantity signal, and applying said control signals for each of said stages of carry/save adder units directly from said shift control logic to each of said stages of carry/save adder units, said shift control logic controlling said stages of carry/save adder units to perform an addition of the multi-bit multiplicand or of the multi-bit multiplicand shifted by one bit position in a selected one of said stages of carry/save adder units and to perform an addition of zero in the other ones of said stages of carry/save adder units, whereby the multi-bit multiplicand, shifted by a number of bit positions specified by said multi-bit shift quantity signal, is obtained from said multi-bit output of said final stage of said carry/save adder units (257). The method of Claim 8, further characterized in that said method includes shifting the multi-bit product signal of said final stage of carry/save adder units (257) by one bit position. The method of Claim 8 or Claim 9, further characterized in that said method includes passing multi-bit signals from said output of said final stage of carry/save adder units to said first stage of carry/save adder units to pass said multi-bit signals through said stages of carry/save adder units a plurality of times.

Inventors: MCLELLAN EDWARD J, WOLRICH GILBERT M, YODLOWSKI ROBERT A J, MCLELLAN, EDWARD J., WOLRICH, GILBERT M., YODLOWSKI, ROBERT A.J.
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1988
Main classification: G06F5
IPC codes: G06F7, G06F5