SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A DC TEST FUNCTION

Abstract: An integrated circuit for receiving an input signal and producing an output signal includes a set/reset circuit (1) operatively connected to an internal main circuit (52) and being set in response to a first signal (S₁) and reset in response to a second signal (S₂) in a normal mode; an output buffer circuit (12), connected to the set/reset circuit (1) for producing the output signal in response to an output of the set/reset circuit (1); and a control circuit (71), connected between the internal main circuit (52) and the set/reset circuit (1). The control circuit (71) receives the first signal (S₁), a reset signal for initializing the internal main circuit (52), the second signal (S₂), and a first test signal (V OLX ) during a DC test mode and the control circuit (71) resets the set/reset circuit (1) in response to the receipt of the reset signal regardless of the second signal (S₂) and sets the set/reset circuit (1) in response to the receipt of the first test signal (V OLX ) regardless of the reset signal and the first signal (S₁).

Description: The present invention relates to a semiconductor integrated circuit having a DC test function, and more particularly to a semiconductor integrated circuit able to test the DC characteristics without a deterioration of the AC characteristics. In general, a method of testing a large scale integrated circuit (LSI) device consists of inputting a test pattern or signal to an LSI device under test, comparing an output value from the LSI device to determine whether or not a function of the LSI device is faulty, and measuring analogue-values of an input/output voltage or current and the like. In US-A-4,546,472, a method of testing integrated circuits is disclosed in which no dedicated test signal pins are required. This is achieved by applying the signals to invoke the test to the input reset pin and the normal functioning output pins. A DC characteristic test and an AC characteristic test are used in the same way for a small scale integrated circuit (SSI) or a medium scale integrated circuit (MSI), based on the test method used for an LSI. The DC characteristic test measures the voltage of external terminals, which are an input terminal and a power source terminal, of an LSI device or the DC current passing through the external terminals in a known DC testing method, and the AC characteristic test measures a propagation delay time between input/output terminals, a transition duration of the output waveform, a set-up time of the input waveform, a holding time, the minimum clock pulse width, and the maximum clock frequency or the like. In the prior art large scale integrated circuit (LSI) device provided with a DC test circuit, a first test circuit and a second test circuit are arranged between an internal main circuit and an output buffer circuit, and the DC test of an LSI device is effected by using these test circuits. But, in the conventional LSI device having the above structure, a deterioration of the AC characteristics occurs due to the delay caused by the DC test circuit. One of the AC characteristics is a propagation delay time between an input terminal and an output terminal, and when a signal is applied to an input pin or terminal in synchronization with a predetermined clock signal, the delay of a signal output from an output pin can be measured by the AC test as a propagation delay time within an LSI device. When a first and second test circuit are included a signal is delayed by passing through gates of the first and second test circuits; i.e., the signal is delayed due to factors other than the essential function of the interior logic of the LSI device, and the AC characteristics deteriorate. In these circumstances, the LSI appears to be faulty in having an unacceptably large delay but this occurs only when the device is under test with the first and second circuits in operation. According to this invention an integrated circuit for receiving an input signal and producing an output signal comprising: an internal main circuit for carrying out various logic operations in accordance with the input signal and producing a first signal and second signal; a set/reset circuit, operatively connected to the internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to the set/reset circuit, for producing the output signal in response to an output of the set/reset circuit; and testing means for generating predetermined output signals during testing; characterised in that the testing means comprises a control circuit connected between the internal main circuit and the set/reset circuit, for receiving the first signal, a reset signal for initializing the internal main circuit, and a first test signal, further characterised in that, during a first DC test mode, the control circuit sets the set/reset circuit in response to the receipt of the first test signal regardless of the first signal and the reset signal for initializing the internal main circuit and during the second DC test mode, the control circuit resets the set/reset circuit in response to a receipt of the reset signal regardless of the second signal. An advantage of the present invention is the provision of a semiconductor integrated circuit device able to test the DC characteristics without the deterioration of the AC characteristics, by incorporating the DC test conditions into a hardware reset condition, a reset condition or the like produced from an internal logic block. In the circuit according to the present invention, a hardware-reset is effected prior to a DC test and the set/reset circuit is held at a reset state, the output buffer circuit at an initialisation state, and further, a gate-ON signal is not output. When a first DC test which brings an output pin or terminal to a LOW level state, is effected by applying a first test signal V OLX , a signal equivalent to the set condition signal is supplied to the set/reset circuit and the output of the set/reset circuit is brought to a set state i.e. HIGH level, and on the other hand, a gate of the output buffer circuit is opened to bring the output pin to a LOW level state. When a second DC test which brings an output pin to a HIGH level state, is effected by applying a second test signal V OH , a gate of the output buffer circuit is opened under a hardware-reset condition, a signal equivalent to the reset condition signal is input to the output buffer circuit, and the output pin is brought to a HIGH Level state. Accordingly, during either the first or second DC tests, a test signal is incorporated into one of a set condition and a reset condition, and therefore, a DC test circuit does not interfere with the AC characteristics of an LSI device and these characteristics are not deteriorated. A particular example of an integrated circuit in accordance with this invention will now be described and contrasted with the prior art with reference to the accompanying drawings; in which:- Figure 1 is a circuit diagram showing a main part of a prior art semiconductor integrated circuit; Figure 2 is a timing chart of a normal operation and a DC operation of Figure 1; Figure 3 is a circuit diagram showing an embodiment of an integrated circuit device in accordance with the present invention; Figure 4 shows waveforms of the signals of a normal operation and a DC operation of Figure 3; and, Figure 5 shows waveforms of the signals of the outputs of inverters 8, 20, 49 and a terminal 21 in Figures 1 and 3. Before describing the preferred embodiment, a prior art semiconductor integrated circuit will be described with reference to Figures 1 and 2. On of the DC tests of an LSI chip forcibly brings an output pin under test to a logical HIGH level state, a logical LOW level state, or a high impedance (Z) state. To carry out such a DC test, conventionally on an LSI device a DC test circuit is provided, as shown in Figure 1, for example. The integrated circuit of Figure 1 is constituted by an internal main circuit 52, a set/reset circuit 1, testing circuits 11 and 13, an output buffer 12, input pins 51, a reset pin 54, test pins 55, 55¹, 56, 57 and output pins 21. In Figure 1 reference numeral 1 denotes a set/reset circuit constituted by NOR gates 1 and 4 which form a set/reset flip-flop 2, abbreviated as S-R FF, AND gates 5 and 6, and an OR gate 7. An input signal is input to an internal main circuit 52 through input pins 51 and processed. Internal signals S₁ and S₂ as shown in Figure 2, that is, the outputs of the internal main circuit 52 are output to output pins 21 through a set/reset circuit 1, a first testing circuit 11 and an output buffer 12. If the internal main circuit 52 is constituted by a set of complicated logic circuits, it takes too long to set a state of output pin 21 by an input signal given to at least one of input pins 51. Thus, at a time of DC test, an output of an inverter 8 and a signal G C pass through a first testing circuits 11 and a second testing circuit 13 just as it is, respectively. On the other hand, at a time of DC test, regardless of the state of the internal main circuit 52, the state of the output pins 21 can be set to a HIGH state, a LOW state or a high impedance (Z) state. For example, all of output pins 21 can be set to a HIGH state, a LOW state or a high impedance state. The S-R FF 2 is set by the internal signals S₁ and reset by the internal signal S₂. The internal main circuit 52 is initialized by the hardware reset signal H-RESET. The internal signal S₂ or the hardware reset signal (H-RESET) at a RESET PIN 54 is input to the AND gate 5 through the OR gate 7, and each of the above-noted signals is output to the S-R FF 2 in synchronization with a clock . On the other hand, the internal signal S₁ is input to the AND gate 6 and the internal signal S₁ also output to the S-R FF 2 in synchronization with the clock . An output of the set/reset circuit 1 is inverted by an inverter 8, the inverted signal is sent to an output buffer circuit 12 through a first test circuit 11, and further, an output of a second that circuit 13 is input to the output buffer circuit 12. The first test circuit 11 is constituted by P-channel MOS transistors 14 to 16, referred to as PMOS hereinafter, and N-channel MOS transistors (NMOS) 17 to 19. A test signal V OH , which denotes that HIGH is active, is input to gates of the PMOS 14, and NMOS 19 and a test signal V OLX , which denotes that LOW is active, is input to gates of the NMOS 18 and PMOS 16. When the test signal V OH or V OLX is active, regardless of the level of the signal output from the set/reset circuit 1, an output terminal 21 of the LSI device is forcibly brought to a HIGH level state or a LOW level state to effect a DC test. The first test circuit 11 is a circuit which brings to set forcibly a state of the output pin 21 to a HIGH or LOW level state. When a test signal V OH or V OLX is input, a first testing circuit 11, regardless of a signal output from the set/reset circuit 1, outputs an HIGH level or an LOW level signal to the output buffer circuit 12 through an inverter 20. The output buffer circuit 12 is formed by a NAND gate 31, a NOR gate 32, an inverter 33, a PMOS 34, and an NMOS 35, and buffer-amplifies an input signal to output same to an output terminal. The second testing circuit 13 is a circuit which sets forcibly a state of the output pin 21 to a high impedance state (Z). On the other hand, a second test circuit 13 is formed by PMOS's 41 to 43, NMOS's 44 to 47, and an inverter 48, and a gate-ON signal G on is input to a gate of a PMOS 41, a gate control signal G C is input to each gate of a PMOS 42 and an NMOS 44, where both gates are connected to each other, and a gate-OFF signal G OFF is input to a gate of an NMOS 45 through an inverter 48. The second test circuit 13 controls the output buffer circuit 12, i.e., determines whether or not the output buffer circuit 12 is enabled. In this case, signals G ON and G OFF are employed for a DC test and a signal G C is used during a normal operation. During a normal operation, i.e., when a DC test is not effected, the signals G ON and G OFF are in an LOW level state and only a signal G C is valid. The signal G C is a gate control signal during a normal operation, and when the signal G C is active, i.e. in a HIGH level active, i.e. in a HIGH level state, an output level of an inverter 20 appears at an output terminal 21 as it is. When the signal G C is inactive, i.e. in a LOW level state, the output pin 21 is in a high impedance state (Z) of a three-state condition. During a DC test, when a signal G OFF becomes active, where HIGH is active, an output of inverter 49 is in a LOW level, and the output of inverter 49 is in a HIGH level state when the signal G OFF is in a LOW level state and G ON is in a HIGH level state. Namely, when the signal G ON is in a HIGH level state and the signal G OFF is in an LOW level state, a buffer function of the output buffer circuit 12 is active, and when the signal G OFF is in a HIGH state, the buffer function is inactive. When the output buffer circuit 12 is active, an output of the inverter 20 appears directly at an output terminal 21, and when the output buffer circuit 12 is inactive, an output pin 21 is in a high impedance (Z) state. Figure 2 shows the waveforms of the signals in a main parts of in Fig. 1. Based on the receipt of an external clock, a clock  is produced with a time delay, and accordingly, a normal operation and a DC operation of the LSI device are carried out. An internal signal S1 is followed by an internal signal S₂ and an output of an inverter 20 is delayed by a time delay δ ₄. In Fig. 2, in a normal operation, the condition is as follow. V OH = LOW, L OLX = HIGH G ON = LOW, G OFF = LOW In response to the clock , an internal signal S₁, an internal signal S₂, an output of an inverter 20, a gate control signal G C , and a signal at an output terminal 21 are shown, respectively. In a DC test operation, when a signal V OLX is in an HIGH level state and a gate-OFF signal G OFF is in a LOW a level state, the waveform of signals V OH and G ON and an output signal at an output terminal 21 are as shown as the first waveforms. When a signal V OH is in an LOW level state, a signal G OFF is in an LOW level state and a signal G ON is the same as above, and the waveform of the signals V OLX and an output signal at a terminal 21 are shown as the second waveforms. In a high impedance (Z) state, i.e. HIGH impedance, G ON is the same as above and the waveform of G OFF is slightly delayed at the leading edge, compared with that of the V OLX . The output of an inverter 49 is in an LOW level state, and therefore, the output of the LSI device is in a high impedance (Z) state as shown in the third waveforms. A semiconductor integrated circuit having a DC test function according to an embodiment of the present invention is shown in Fig. 3. The waveforms of the signals in the essential blocks in Fig. 3 are shown in Fig. 4. In Fig. 3 an LSI device is constituted by an internal main circuit 52 (for example, a microprocessor, a PMA controller, a peripheral controller, etc.) output buffer 12, input pins 81, output pins 21, and test pins 82 and 83. The output buffer 12 has a PMOS 34, a NMOS 35, a NAND gate 31, a NOR gate 32, and an inverter 33, the internal main circuit 52 carries out a variety of logical operations to deliver of setting and resetting condition signals to the output buffer, and on the other hand, is supplied with a hardware reset signal (H-RESET) signal from the reset pin 84 during a hardware resetting period. In this case, setting or resetting is an operation in which the data is stored temporarily in register or the like in internal logic circuits and after a lapse of a predetermined time a HIGH-active signal synchronized with the clock signal  is delivered. The hardware resetting is a resetting for forcibly resetting the logic circuit in the LSI device, for example, a resetting by an initialization. Normally, for a DC test, the hardware is reset to initialize all elements, and the DC test is started in this condition. The command signal for hardware resetting is H-RESET, which is supplied to the internal main circuit 52 and output buffer 52 from outside via the reset pin 84. Further, the internal main circuit 52 supplies a gate control signal G c to control the output buffer circuit 12. The gate control signal G c is effective when V OLX which is first DC test signal, and V OH which is second DC test signal are inactive in the condition shown in Fig. 3. On the other hand, the test pins 82 and 83 are provided to receive the first test signal V OLX and second test signal V OH when a DC test is carried out. Signals V OLX and V OH may be supplied from the mode register-1 and mode register-2 without providing test pins 82 and 83. The mode register-1 delivers signals V OLX and mode register-2 delivers signal V OH in accordance with commands from the internal main circuit 52. As shown in Fig. 3, the internal signal S₂ is supplied from the internal main circuit 52 to the OR gate 7 to which an output from the AND gate 58 is supplied from the OR gate 7. The AND gate 58 is supplied with signals H-RESET and V OLX , and allows the H-RESET signal which is HIGH-active to pass when the V OLX signal is at HIGH level. Namely, when the first DC test with the signal level at the output pin 21 at LOW level is not made (when V OLX = HIGH), a hardware reset can be applied. The V OLX signal is inverted by the inverter 62 and supplied to the OR gate 59, and is supplied to the OR gate 60 through the inverter 61. The OR gate 59 is supplied with the internal signal S₁. This OR gate 59 will set the set/reset circuit 1 when internal signal S₁ or an LOW-active V OLX signal. The set/reset circuit 1 provides an HIGH-level signal when the setting internal signal S₁, is supplied or V OLX signal is at LOW level, and delivers an LOW-level signal when supplied with the internal signal S₂ or H-RESET signal. Therefore, the V OLX signal for a DC test is one of the signals input to the set/reset circuit 1. It should be noted that the set/reset circuit operation is based on the clock . The above-mentioned AND gate 58, OR gate 59, and inverter 62 together form control circuit 71. The output signal from the set/reset circuit 1 is supplied via the inverter 8 to the output buffer circuit 12, which buffer-amplifies the signal level of the set/reset circuit 1 and delivers an inverted level signal to the output pin 21. Further, the output buffer 12 is supplied with a signal from the OR gate 60 which is supplied with a test signal V OH , gate control signal GATE ON condition and the output of the inverter 61. The gate control signal is such that unless a test is made, the gate of the output buffer 12 is opened to permit a normal signal from the set/reset circuit 1 to be passed. When a test is made, the gate control signal is not effective, so that the above-mentioned normal signal cannot be passed as it is. Therefore, when an HIGH-level signal is delivered from the OR gate 60, the gates 31, 32 of the output buffer 12 are opened and the output level of the inverter 8 is passed as it is to the output pin 21. When an LOW-level signal is delivered from the OR gate 60, the gate of the output buffer 12 is closed so that the output pin 21 is at a high impedance (Z) level. The above-mentioned OR gate 60 and inverter 61 together form a gate signal generating means 72. The operation of the LSI device of Fig. 3 will be described below. First , the operation in the normal mode will be described. When in the normal mode, test signals V OH is fixed in a LOW level state and V OLX is fixed in a HIGH level state. According to the internal logic of the internal main circuit 52 or a signal from the input pin 81, the LSI device 50 follows the normal logical request with the generation of a signal having a predetermined level. More particularly, the internal main circuit 52 generates the internal signals S₁ and S₂, and this command signal S₁ and S₂ are delivered to the set/reset circuit 1. On the other hand, the internal main circuit 52 supplies gate control signal G C to the OR gate 60. When the gate control signal G C becomes HIGH-active, the output buffer 12 permits the output signal from the inverter 8 to be passed. When an HIGH-active signal S₂ is delivered from the internal main circuit 52, this internal signal S₂ is is supplied to the AND gate 5 via the OR gate 7. Synchronously with the clock , the AND gate 5 passes the HIGH-active internal signal S₁ from the OR gate 7 to the S-R FF 2 which, in turn, generates an LOW-level signal. This LOW-level signal is supplied through the inverter 8 to the output buffer 12. Thus, the NAND gate 31 is supplied with a HIGH-level signal, but since the NAND gate 31 is supplied with an HIGH-level signal as a GATE ON condition from the OR gate 60, the output from the NAND gate 31 is at LOW-level and the PMOS 34 is turned ON. Also, one of the input terminals of the NOR gate 32 is supplied with the HIGH-level signal from the inverter 8, and at the other terminal thereof, is supplied with an HIGH-level signal from the inverter 33, which has been inverted to LOW-Level by the inverter 33, so that the output is at LOW-Level and NMOS 35 is turned OFF. As a result, the output pin 21 is charged by a High-level power source V cc so that the output pin 21 is at HIGH level, i.e. HIGH-level signal is delivered. Thus, the output pin 21 is at HIGH- level for a resetting condition. As another example, when the internal main circuit 52 delivers, for example, an HIGH-active internal signal S₁, the condition output is supplied through the OR gate 59 to the set/reset circuit 1 which, in turn, generates an HIGH-level signal in synchronization with the clock  and delivers an LOW-level signal through the inverter 8 to the output buffer 12. Thus, according to the logic opposite to that for internal signal S₂, the output of the NAND gate 31 becomes HIGH and the output of the NOR gate 32 also becomes HIGH, so that the PMOS 34 is turned OFF and the NMOS 35 is turned ON. As a result, the potential at the output pin 21 drops to the ground potential, and thus the output pin 21 is at LOW-level, an LOW-level signal is delivered. As a further example, the internal main circuit 52 commands a high impedance (Z), for example, as one of three states, from time to time. The condition in this case is such that a command is issued to prevent the GATE ON conditions from being effective when in the normal mode (namely, the signals V OLX and V OH are all inactive). Therefore, the GATE ON condition becomes inactive, i.e. LOW Level, so that all of the three signals input to the OR gate 60 are brought to the LOW-level and supplied to the output buffer 12. Thus, in the output circuit 12, the output from the NAND gate 31 is at HIGH level and the output from the NOR gate 32 is at LOW Level , regardless of the level of the signal from the inverter 8, so that both the PMOS 34 and NMOS 35 are turned OFF, with the result that the output pin 21 is at a high impedance (Z) level, at which the impedance is high. The AC test is made in such a normal condition to measure the propagation delay time between, for example, the aforementioned input and output pins or terminals, and the set-up time, and the like. Since an interposed test circuit is not provided, no delay of set-up occurs in response to a clock, which would occur if a test circuit is provided, and thus it is possible to avoid a degradation of the AC characteristics. The quality of the LSI devices can be thus improved for the users. Second, the operation in the DC test mode will be described. First, an external HIGH-active H-RESET signal is applied to the reset pin 74. At this time, the V OLX signal is HIGH-inactive while V OH signal is LOW-inactive, and the signal G C is LOW-inactive. Namely, all the signals are initialized to be inactive. When an H-RESET signal is applied, the internal logic of the internal main circuit 52 is reset to the initial state. On the other hand, the H-RESET signal is supplied via the AND gate 58 to the set/reset circuit 1, which will be reset, so that an HIGH-level signal is supplied to the output buffer 12. Thus, one of the input terminals of the NAND gate 31 and NOR gate 32, respectively, is at the HIGH-level. Since the output of the OR gate 60 is at the LOW-Level at this time, the other input terminal of the NAND gate 31 is also at the LOW-level and the other input terminal of the NOR gate 32 becomes HIGH. Hence, the output pin 21 has a high impedance as in the case of a high impedance (Z) as one of three states, i.e., an initialization is attained. The DC test is made during the above-mentioned hardware resetting period. Namely, in the first DC test, an LOW-active V OLX signal is applied to the test pin 82. After inversion by the inverter 62 to the H level, this V OLX signal is delivered to the set/reset circuit 1 through the OR gage 59, and therefore, the set/reset circuit 1 is brought to a state as if it were supplied with an HIGH-level signal for a setting condition, and the output of this set/reset circuit 1 is at HIGH level and is supplied to the output buffer 12 through the inverter 8. On the other hand, an Low-level V OLX signal is applied to the AND gate 58 at this time so that the H-RESET signal cannot pass through the AND gate 58. Therefore, the setting and resetting conditions are simultaneously supplied to the set/reset circuit 1, and the set/reset circuit 1 will not oscillate. After coming to the HIGH level as inverted by the inverter 61, the V OLX signal is supplied to the output buffer 12 through the OR gate 60. Therefore, the gate of the output buffer 12 is opened so that the aforementioned LOW-level signal from the set/reset circuit 1 is accepted by the output buffer 12, the output of which, namely, the output pin 21 is at the LOW-level , and thus the first DC test is effected. In the second DC test with the output pin 21 at the H level, an HIGH-active V OH signal is supplied to the test pin 83. This V OH signal is supplied to the output buffer 12 through the OR gate 60 so that the signal levels at the other inputs of the NAND gate 31 and NOR gate 32, respectively, in the output buffer 12 are changed. Namely, the signal level at one of the inputs of the NAND gate 31 is HIGH and that at the other input is changed from LOW to HIGH, but the output of the NAND gate 31 is at LOW-Level . The signal level at one of the inputs of the NOR gate 32 is LOW and that at the other input is changed from LOW to HIGH, so that the output of the NOR gate 32 is changed from HIGH to LOW and the NMOS 35 is turned OFF. Thus, the output pin 21 is at the HIGH level, and the second DC test is made. As described above, by supplying a V OLX signal when a first DC test is to be effected, the state wherein the set/reset circuit 1 is forcibly kept in the reset state by the hardware resetting signal H-RESET is cancelled, and due to this V OLX signal, a signal equivalent to the setting condition is supplied to the set/reset circuit 1. The output of the set/reset circuit 1 becomes HIGH, i.e. set state, and the gate of the output buffer 12 is opened so that the output of the output buffer 12 is at the LOW-level . Consequently, the V OLX signal is simply one of the conditions for setting the set/reset circuit 1, and since a test circuit is not included as in the prior art, between the set/reset circuit 1 and output buffer 12, the AC characteristics are not degraded. By turning the V OLX signal OFF and the V OH signal ON when the second DC test is to be made, the gate of the output buffer 12 is opened in a state wherein the set/reset circuit 1 is in the reset condition due to the H-RESET signal, a signal equivalent to the internal signal S₂ is supplied to the output buffer 12, the output of which is at HIGH level. Therefore, the V OH signal is simply one of the gate control signals for the output buffer 12 and the AC characteristics will not be degraded as in the abovementioned case. As a result, the AC characteristics of the LSI device can be improved and the quality of the operation of the device can be enhanced. When the signals V OLX and V OH are made inactive during a hardware resetting, a signal of a high impedance (Z) is obtained at the output pin 21. Figure 4 shows waveforms for illustrating a normal operation and a DC operation of Fig. 3. In Fig. 4, if a series of external clocks and clocks  are given, a normal operation and a DC operation are described responsive to them. The normal operation is as follows. V OH = LOW, V OLX = HIGH, H-RESET = LOW If a SET condition signal and a RESET condition signal are given, the output of an inverter 8, a gate-ON condition signal and the output of terminal 21 are shown responsive to the SET and RESET signals. The output of the inverter 8 produces a predetermined time delay δ ₀ to a clock . Further, responsive to the gate-ON condition signal, the output of the LSI output terminal 21 is shown as high impedance (Z), HIGH level (H), LOW level (L), HIGH level (H), high impedance (Z), and so on as shown in the figure in case of an AC standard. If a H-RESET signal is given, HIGH and LOW outputs and high impedance output are obtained as follows. (a) In the case of HIGH output V OLX = HIGH, From H-RESET and V OLX , OR gate 7 is ON, The output of an inverter 8 is HIGH, which is determined by an OR gate 60. (b) In the case of LOW output V OH = LOW, The output of AND gate 58 is LOW, and RESET condition = LOW, OR gate 7 is not HIGH. (c) In the case of high impedance (Z) output V OLX = HIGH, V OH = LOW, The output of OR gate 60 is in a LOW state and the output buffer 12 is not active. Figure 5 shows waveforms for illustrating the outputs of the inverters 8, 20, 49 and the terminal 21 in Figs. 1 and 3. Responsive to a series of external clocks and clocks , the outputs of the inverter 8 in Fig. 1 and Fig. 3, the output of the OR gate 60 in Fig. 3, the output of the terminal 21 in Fig. 3, the outputs of inverters 20 and 49 in Fig. 1 and the output of the terminal 21 in Fig. 1 are shown in the figure. In Fig. 5, AC standard of Fig. 3 and Fig. 1 are shown, comparing the AC standard of Fig. 1 with that of Fig. 3, the delay of the signal at the output terminal of Fig. 1 being delayed by the amount of the DC test circuits and inverters.

Claims: An integrated circuit for receiving an input signal and producing output signal comprising: an internal main circuit (52) for carrying out various logic operations in accordance with the input signal and producing a first signal (S₁) and second signal (S₂); a set/reset circuit (1), operatively connected to the internal main circuit (52), being set in response to the first signal (S₁) and reset in response to the second signal (S₂) in a normal mode; an output buffer circuit (12), connected to the set/reset circuit (1), for producing the output signal in response to an output of the set/reset circuit (1); and testing means for generating predetermined output signals during testing; characterised in that the testing means comprises a control circuit (71) connected between the internal main circuit (52) and the set/reset circuit (1), for receiving the first signal (S₁), a reset signal for initializing the internal main circuit (52), and a first test signal (V OLX ), further characterised in that, during a first DC test mode, the control circuit (71) sets the set/reset circuit (1) in response to the receipt of the first test signal (V OLX ) regardless of the first signal (S₁) and the reset signal for initializing the internal main circuit (52), and during the second DC test mode, the control circuit (71) resets the set/reset circuit (1) in response to a receipt of the reset signal regardless of the second signal (S₂). An integrated circuit according to claim 1, wherein the output buffer circuit comprises a three state buffer circuit (12), and the internal main circuit (52) produces a gate control signal (G C ) to control the three state buffer circuit (12). An integrated circuit according to claim 2, wherein the integrated circuit further comprises a gate signal generator (72), connected between the internal main circuit (52) and the three state buffer circuit (12) and receiving the gate control signal (G C ) and a second test signal (V OH ) and making the three state buffer (12) active in response to the receipt of the second test signal (V OH ) regardless of the gate control signal (G C ) during the DC test modes.

Inventors: HIDA, HIDENORI, IINO, HIDEYUKI
Applicants: FUJITSU DEVICES INC, FUJITSU LIMITED
Application year: 1988
Main classification: G01R31
IPC codes: H01L27, G01R31, H01L21