PRE-DRIVE CIRCUIT

Abstract: A MOS FET (Q1) of a switching circuit (1) is turned on/off, controlled by a pre-drive circuit (2) via a pulse transformer (T). For switching on, a drive transistor (Q2) on the primary side (P1) of the pulse transformer is turned on, which generates a voltage on the secondary side (51). This charges the gate (G) of the MOS FET (Q1) to the positive side and turns on the switch. For switching off, the drive transistor (Q2) is turned off and the gate (Q) is discharged via a current flow (IE). The MOS FET (Q1) is switched off when the gate voltage becomes zero. The gate voltage further drops until it reaches a negative level determined by a zener diode (ZD3), when another FET (Q3) is switched off, further current flow (IE) is prevented.

Description: This invention relates to a pre-drive circuit suitable to be used in a switching regulator, a DC-DC converter or the like. A pre-drive circuit, one example of which is shown in Fig. 3, is widely known and is adapted to turn the current that flows into the primary side of a pulse transformer on and off, apply the pulses generated on the secondary side of the transformer to a MOS-type field-effect transistor (hereinafter referred to as a "FET") for power, and exercise control to turn a load current on and off by the power FET. In accordance with the conventional circuit shown in Fig. 3, the secondary side of a pulse transformer T is connected directly to the gate and source of a power FET Q1, and the power FET Q1 is subjected to turn-on/turn-off control by using a drive transistor Q2 connected to the primary side of the pulse transformer T. The power FET used in this pre-drive circuit naturally has a large electrostatic capacity (input capacity) as seen from the gate since the current controlled is large. In Fig. 3, a switching circuit 1 subjects a current supplied from a power supply PS to a load L to turn-on/turn-off control by means of the power FET Q1. This circuit is connected to the pre-drive circuit 2. When the transistor Q2 for switching is turned on, the gate of the power FET Q1 is charged to the positive side by the voltage whose polarity is indicated by the solid line, so that the power FET Q1 is turned on. When the switching transistor Q2 is turned off in order to turn off the power FET Q1, the charge stored in the gate of the power FET Q1 becomes a current I E , which is indicated by the broken line, and is discharged into the secondary coil of the pulse transformer T. With further charging on the negative side, the power FET Q1 is turned off. ZD1 and ZD2 denote protective Zener diodes which limit the voltage applied to the gate of the power FET Q1 so that this voltage will not become excessive. When the power FET Q1 is turned off after being turned on in the conventional pre-drive circuit of the type described above, it is necessary to preset the magnetic flux of the pulse transformer T to an initial value and charge the gate to a voltage on the negative side required to turn off the power FET Q1. Therefore, the larger the input capacity of the power FET Q1, the shorter the elapsed time from turn-on to turn-off of the power FET Q1 and the greater the change in gate voltage with respect to time, the larger must be the current I E which flows through the path comprising the source and gate of the power FET Q1. Accordingly, the core of the pulse transformer T is required to be correspondingly large. In the end, the energy charged in the gate of the power FET Q1 is lost. Consequently, it is meaningless to charge the gate into an unnecessary voltage region beyond the negative voltage that turns off the power FET Q1, and merely increasing the driving power lowers the efficiency of the driving power. As set forth above, it is necessary that the magnetic flux of the power transformer be rapidly reset to an initial value for the next drive cycle. However, since the gate of the power FET Q1 is charged and connected directly to the secondary side of the pulse transformer T, as mentioned above, time is required for the electric charge resulting from the charging operation to discharge, so that the flux of the pulse transformer T cannot be rapidly reset to the initial value. Consequently, when high-speed switching is made to take place, there is a time delay for the discharge of the abovementioned electric charge and, hence, normal operation cannot be achieved. The present invention has been devised in view of the foregoing points and its object is to provide a pre-drive circuit for controlling the turn-on/turn-off of a power FET via a pulse transformer, wherein the influence of an electric charge which accumulates in the gate input capacity of the power FET is mitigated, thereby enabling operation at a low driving power and preventing a decline in performance at high-speed switching. Prior disclosures of pre-drive circuits have been made for example in JP-A-61-177815, JP-A-61-16620 and GB-A-2 109 194. In particular, the first of these three documents discloses a pre-drive circuit according to the preamble of the attached claim 1, but without the characterising features thereof and therefore without the advantages provided by these features. According to the present invention there is provided a pre-drive circuit for a first MOS-type FET, operable to transmit to the gate of the FET a pulsed signal applied to a switching element which renders intermittent a current flowing through a primary side of a pulse transformer, the FET thereby being turn-on/turn-off controlled in dependence upon said pulsed signal by control pulses generated on a secondary side of the pulse transformer, which is connected to the gate of the FET thereby to render current intermittent in a load of the FET, there being coupled between the pulse transformer secondary side and the FET an interrupting means operable for interrupting the connection therebetween, with a detecting means being coupled to the interrupting means for rendering it operational in response to a predetermined negative voltage across the gate and the source of the FET, characterised in that the pulse transformer primary side and the switching element therefor are coupled to a single polarity voltage source so that the control pulses generated in the pulse transformer secondary side by the switching element have only a single polarity also, switching-off of the FET is achieved by switching off the switching element, thereby allowing the charge which has accumulated in the gate of the FET to be drawn off through a current path comprising the interrupting means, the pulse transformer secondary side and the FET itself, and when the voltage across the gate and the source of the FET as a result drops beyond said predetermined negative voltage, the detecting means causes the interrupting means to operate thereby to interrupt said current path thus preventing any further negative increase in the FET gate voltage, there being coupled to the primary side of the pulse transformer, diode dissipating means for dissipating magnetic energy left in the pulse transformer when the interrupting means operates as aforesaid. According to the invention, when the MOS-type field-effect transistor is switched from the turned-on state to the turned-off state, the voltage across the gate and source of the MOS-type field-effect transistor exceeds a set value and makes a transition to the negative side. When this occurs, the MOS-type field-effect transistor and the secondary side of the pulse transformer are cut off from each other by the interrupting means, thereby preventing the gate from being charged to a region of an unnecessary negative voltage. Brief Description of the Drawings Fig. 1 is a circuit diagram illustrating a pre-drive circuit embodying the present invention, as well as peripheral circuitry; Fig. 2 is a circuit diagram illustrating a second embodiment of the present invention; and Fig. 3 is a circuit diagram of a pre-drive circuit according to the prior art. An embodiment of the present invention will now be described with reference to the drawings. Fig. 1 is a pre-drive circuit illustrating a first embodiment of the present invention. The switching circuit 1 to be driven by the pre-drive circuit 2 is illustrated in simplified form and has a power FET Q1 turned on or turned off by a control signal from the pre-drive circuit. The source terminal of the power FET Q1 is connected to the source terminal of a power FET Q3 constituting a first control circuit. The drain terminal of the FET Q3 is connected to one end of the secondary coil S1 of the pulse transformer T. The other end of the secondary coil is connected to the gate terminal of the power FET Q1 via a current limiting resistor R1, and to the gate terminal of the FET Q3 via a Zener diode ZD3. A diode D1 is connected across the source and drain of the FET Q3 in such a manner that the conduction direction is from the source to the drain. A series circuit comprising a diode D2 and a Zener diode D4 is connected in parallel with the primary side of the pulse transformer T. A power supply V1 is connected to the collector of a drive transistor Q2 via a primary coil P1 of the pulse transformer T. The emitter of this transistor is connected to ground. The circuit arrangement is such that a control signal Si enters the base of the drive transistor Q2. When the drive transistor Q2 is turned on in order to turn on the power FET Q1, a voltage having a polarity in the direction of the arrow indicated by the solid line in Fig. 1 is produced in the secondary coil S1 of the pulse transformer T. As a result of this voltage, the gate of the power FET Q1 is charged via the current-limiting resistor R1 and the diode D1 provided across the drain and source of the FET Q3 in the first control circuit; hence, the power FET Q1 is turned on. When the transistor Q2 is turned off in order to change the power FET Q1 from the turned-on state to the turned-off state, the electric charge which has accumulated in the gate of the power FET Q1 flows through a path composed of the current limiting resistor R1, the secondary coil S1 of pulse transformer T, the FET Q3 and the power FET Q1. Thus, the charge which has accumulated in the gate of the power FET Q1 is drawn off, thereby lowering the gate voltage. When the gate voltage attains a value near 0 V, the power FET Q1 is turned off. When the gate voltage drops further to the negative side and eventually surpasses a set voltage decided by the Zener voltage of the Zener diode ZD3, the electric charge at the gate of the control FET Q3 is drawn off via the Zener diode ZD3, so that the voltage across the gate and source of the FET Q3 becomes approximately 0 V and the FET Q3 is placed in the cut-off state, thereby interrupting the path of the current I E . Accordingly, the gate voltage of the power FET Q1 will increase no further on the negative side. The output voltage of the pulse transformer T which grows larger on the negative side is impressed upon the circuit composed of the diode D2 and Zener diode ZD4 and connected in parallel with the primary side of the pulse transformer T, whereby the magnetic energy left in the core of the pulse transformer T is dissipated. When the magnetic energy is released, the flux of the pulse transformer T is reset to the initial value and the terminal voltage rapidly become 0 V. The current-limiting resistor R1 limits switching which is faster than necessary by limiting the current which flows into or out of the gate of the power FET Q1, and thus functions to suppress the generation of noise or surge voltage. In the foregoing embodiment as described above, when the drive transistor Q2 is turned from on to off in order to turn the power FET Q1, which is used as a switching element, from on to off, the first control circuit is operated in such a manner that the gate of the power FET Q1 will not be charged into an unnecessary voltage region. Owing to the circuit composed of the diode D2 and Zener diode ZD4 provided on the primary side of the pulse transformer T, the flux of the pulse transformer T is rapidly reset to the initial value for the next drive cycle. A second embodiment of the invention will now be described with reference to Fig. 2. This embodiment differs from the first in that the pulse transformer T has a second primary coil P2, and it that there is provided a control circuit for controlling this primary coil. The rest of the circuitry is the same as that of the first embodiment. These portions are indicated by the same reference characters in Figs. 1 and 2 and a description thereof is deleted. In Fig. 2, the pulse transformer T is provided with the second primary coil P2. One end of the coil P2 is connected to the drain terminal of a control FET Q4, the source whereof is grounded. Applied to the gate of the FET Q4 is an input signal -Si, described below. The other end of the second primary coil P2 is connected to the source of the FET Q4 and, at the same time, to ground, via a diode D3. This other end of the second primary coil P2 of pulse transformer T is connected to the power supply V1 via the diode D2. Connected to the base of the drive transistor Q2 and the gate of the controller FET Q4 is a signal output transistor Q5 of a control circuit 3 which supplies the aforementioned base and gate with signals Si, -Si of opposite phase. A base resistor R2 is connected to the base of the driver transistor S2, and a resistor R3 is connected to the gate of the FET Q4. When the power FET Q1 serving as the switching element is turned off by the driver transistor Q2 after having been turned on in the circuit of the second embodiment described above, the FET Q4 for control is turned on at the same time that the drive transistor Q2 is turned off. When the FET Q4 attains the turned-on state, the second primary coil P2 of the pulse transformer T passes a current through the path composed of the diode D3 and control FET Q4, whereby the terminal voltage of the pulse transformer is rapidly brought to 0 V. As a result of this operation, the electric charge which has accumulated on the gate of the power FET Q1 is drawn off, so that the gate voltage quickly 0 V and the power FET Q1 is turned off. Thereafter, operation up to the point at which the FET Q3 is cut off is the same as in the first embodiment. After the FET Q3 has attained the cut-off state, the output voltage of the pulse transformer T which increases on the negative side is clamped to the power supply V1 via the diodes D2, D4. When the magnetic energy is subsequently dissipated, the magnetic flux of the pulse transformer T is reset to the initial value to prepare for the next drive cycle, as in the case of the first embodiment. In accordance with the present invention, there is provided a pre-drive circuit for subjecting a power FET to turn-on/turn-off control via a pulse transformer, wherein the influence of the input capacity of the power FET is diminished to decrease drive power and reduce the size of the pulse transformer, and wherein a decline in performance that would otherwise be caused by the input capacity at the time of high-speed switching can be reduced.

Claims: A pre-drive circuit (2) for a first MOS-type FET (Q1), operable to transmit to the gate of the FET (Q1) a pulsed signal (Si) applied to a switching element (Q2) which renders intermittent a current flowing through a primary side (P1) of a pulse transformer (T), the FET (Q1) thereby being turn-on/turn-off controlled in dependence upon said pulsed signal by control pulses generated on a secondary side (S1) of the pulse transformer (T), which is connected to the gate of the FET (Q1) thereby to render current intermittent in a load (L) of the FET (Q1), there being coupled between the pulse transformer secondary side (S1) and the FET (Q1) an interrupting means (Q3) operable for interrupting the connection therebetween, with a detecting means (ZD3) being coupled to the interrupting means (Q3) for rendering it operational in response to a predetermined negative voltage across the gate and the source of the FET (Q1), characterised in that the pulse transformer primary side (P1) and the switching element (Q2) therefor are coupled to a single polarity voltage source so that the control pulses generated in the pulse transformer secondary side (S1) by the switching element (Q2) have only a single polarity also, switching-off of the FET (Q1) is achieved by switching off the switching element (Q2), thereby allowing the charge which has accumulated in the gate of the FET (Q1) to be drawn off through a current path comprising the interrupting means (Q3), the pulse transformer secondary side (S1) and the FET (Q1) itself, and when the voltage across the gate and the source of the FET (Q1) as a result drops beyond said predetermined negative voltage, the detecting means (ZD3) causes the interrupting means (Q3) to operate thereby to interrupt said current path thus preventing any further negative increase in the FET gate voltage, there being coupled to the primary side (P1,P2) of the pulse transformer (T) diode dissipating means (D2 and ZD4, D3 and Q4) for dissipating magnetic energy left in the pulse transformer (T) when the interrupting means (Q3) operates as aforesaid. A pre-drive circuit (2) according to claim 1, characterised in that the interrupting means (Q3) is a second MOS-type field-effect transistor. A pre-drive circuit (2) according to claim 2, characterized in that a diode (D1) which operates as a current path when the first MOS-type field-effect transistor (Q1) is driven from the turned-off state to the turned-on state is connected in parallel with a drain and source of said second MOS-type field effect transistor (Q3). A pre-drive circuit (2) according to claim 2 or 3, characterized in that said detecting means (ZD3) comprises a Zener diode connected across a gate of said second MOS-type field effect transistor (Q3) and the secondary side (S1) of the pulse transformer (T). A pre-drive circuit (2) according to claim 1, 2, 3 or 4, characterized in that a resistor (R1) for limiting current is provided across the secondary side (S1) of the pulse transformer (T) and the first MOS-type field-effect transistor (Q1). A pre-drive circuit (2) according to claim 1, 2, 3, 4 or 5, characterized in that the primary side (P1, P2) of the pulse transformer (T) is provided with a second primary coil (P2) and a second switching element (Q4) connected in parallel with said second primary coil (P2), and when the first MOS-type field-effect transistor (Q1) is operated to change from the turned-on state to the turned-off state, said second switching element (Q4) is turned on to short-circuit the second primary coil (P2).

Inventors: NAKAMURA SHIGEO, YAIRO OSAMU, NAKAMURA, SHIGEO, YAIRO, OSAMU
Applicants: FANUC LTD, FANUC LTD.
Application year: 1988
Main classification: H03K17
IPC codes: H03K17