DYNAMIC RANDOM ACCESS MEMORY WITH A SELF-REFRESHING FUNCTION

Abstract: Dynamic random access memory with a self-refreshing function, in which an error correction means (12,13) for detecting and correcting an error of data in the memory cells during refreshing action of the memory cell data is provided, and the clock period of the clock generator (15) for clock control of refreshing and error correcting action is made variable, and the clock period of the clock generator is kept in the vicinity of the maximum value depending on the pause time of the memory cell depending on the error detection signal (EDS) generated at the time of error correction by the error correction means. According to this construction, if the pause time of the memory cell is changed significantly depending on the manufacturing process condition, refreshing operation can be effected at a period near the maximum depending on the pause time, so that the self-refreshing current may be decreased. Besides, if the pause time varies depending on the change in the operating condition or characteristic changes due to the time passing, the clock period values according to such changings, so that it is possible to operate always in the maximum self-­ refreshing period depending on the conditions, without causing malfunction in refreshing operation.

Description: Background of the Invention This invention relates to a dynamic random access memory with a self-refreshing function. As a large capacity memory device, a dynamic random access memory (DRAM) using one MOS transistor and one capacitor to compose a memory cell is advantageous and general. In this kind of memory device, electric charge is stored in the capacitor, and the written information is judged to be 0 or 1 of binary notation depending on whether this charge is present or absent, but when let stand for a long time, the stored charge decreases due to leak current of the capacitor, and the written information may be lost. Therefore, before the stored charge is decreased under a predetermined level, the information is read out from the capacitor, and the same information is written again to the capacitor in order to prevent the information from disappearance. This operation is called refreshing. However, in conventional dynamic random access memory devices, it is indispensable to keep refreshing even when the information is neither read out from the capacitor nor written to the capacitor by supplying address signals and clock signals to the memory device. Such refresh function is performed by external circuits, and therefore, the memory system tends to be complicated. Recently, in order to simplify the memory system, it has been proposed to perform refreshing by internal circuits which are fabricated to the memory device (for example, Nikkei Electronics, No. 215, p. 167, 1979; No. 418, p. 167, 1987). This system is called self-refreshing function. A conventional self-refreshing function of dynamic random access memory device is described below. A block diagram of a conventional dynamic random access memory device is shown in Fig. 7, in which a memory cell matrix 21 has plurality of memory cells of m rows × n columns. A row line selection circuit 22 selects any one of the row lines of the memory cell matrix 21. Absence-refreshing amplifier 23 refreshes the memory cells corresponding to the row line selected by the row line selection circuit 22. A self-refreshing clock generator 24 is self-excited in a predetermined period, and generates a series of self-refreshing clock pulses. A control clock generator 25 generates a series of control clock pulses in synchronism with the self-refreshing clock pulses. A refreshing address counter 26 stores the refreshing address. The self-refreshing action of the dynamic random access memory device shown in Fig. 7 is as follows. First, by the control clock synchronized with the self-refreshing clock, memory cells corresponding to the row line address specified by the refreshing address counter 26 and selected by the row line selection circuit 22 are refreshed. Afterwards, the refreshing address counter 26 is incremented by 1 bit within 1 refreshing period. When this operation is repeated continuously, all memory cells are completely refreshed by executing self-refreshing in m periods in a memory device having a memory cell matrix of m row lines × n columns. The self-refreshing clock generator 24 generates a series of clock pulses by dividing the oscillator output having a predetermined period. Accordingly, the self-refreshing period is, once determined, not changed significantly although varying somewhat depending on the temperature condition or the deviation of supply voltage. The mean current consumption in self-refreshing is nearly inversely proportional to the period of self-refreshing clock. In order to decrease the current consumption, it is better to set longer the period of the self-refreshing clock. However, if this period is set longer than the value of dividing the pause time T H to the memory cell by the number of row lines m of the memory cell matrix, it is impossible to refresh all memory cells within the pause time T H . Still more, the pause time T H decreases to about half when the ambient temperature is raised by 10°C, and it also varies significantly depending on the manufacturing process condition. Therefore, in order to execute the self-refreshing operation correctly, it is necessary to set the self-refreshing clock period in a shorter period with a sufficient safe margin, which, to the contrary, makes it difficult to decrease the current consumption. It is hence difficult, in the dynamic random access memories having the conventional self-refreshing function, to achieve the mutually contradictory purposes of decrease of current consumption in self-refreshing and improvement of precision in the self-refreshing action. EP-A- 0.212.547 discloses a memory device having a circuit for detecting and correcting errors during refresh periods. EP-A-0.176.203 discloses a refresh control circuit having a leakage current monitor circuit for controlling the refresh period in order to minimise power consumption. Summary of the Invention Embodiments of this invention present a dynamic random access memory realizing both decrease of current consumption and enhancement of precision of self-refreshing action, by keeping the self-refreshing period always in the vicinity of the maximum value where malfunction may not occur even when the pause time of the memory cell fluctuates or when the environmental temperature varies. The invention is defined in claims 1 and 9. This invention may be briefly summarized as a dynamic random access memory which comprises a memory cell matrix having a plurality of memory cells arranged in a matrix, row line selection circuit and column selection circuit for selecting any one of the row lines and columns of said memory cell matrix, a sense refreshing amplifier for reading out and refreshing any one of the memory cells selected among said memory cell matrix, an error correction circuit for detecting and correcting an error of data in said selected memory cell, address counter means for storing the address of the memory cell to be corrected, a self-refreshing clock generator with a variable clock period, and a control clock generator for supplying control clock pulses to said address counter means, row line selection circuit, column selection circuit, sense refreshing amplifier and error correction circuit by receiving the self-refreshing clock from said self-refreshing clock generator, whereby the clock period of said self-refreshing clock generator is varied by the error detection signal delivered from said error correction circuit when said error correction circuit corrects an error. According to this constitution, if an error occurs in the data being read out because the period T R is too long while executing self-refreshing in a certain period T R , the self-refreshing period T R may be shortened by the error detection signal delivered from the error correction circuit. Besides, if the self-refreshing period T R is sufficiently shorter than the value calculated based on the pause time T H of the memory cell, when error does not occur for many periods, the period T R may be extended by the absence of error detection signal delivered from the error correction circuit for many periods. By thus controlling the self-refreshing clock period T R by the error detection signal delivered from the error correction circuit, this period T R may be kept in the vicinity of the maximum value suitable for the actual pause time of the memory cell, so that the current consumption of the self-refreshing operation may be decreased. Other features and advantages of the present invention will be apparent from the following description and accompanying drawings. Brief Description of the Drawings Fig. 1 is a block diagram showing a self-refreshing circuit of a dynamic random access memory according to one of the embodiments of this invention; Fig. 2 is a block diagram showing the structure of a self-refreshing clock generator in Fig. 1; Fig. 3 is a circuit diagram of a dividing ratio control circuit in Fig. 2; Fig. 4 is a circuit diagram of a dividing circuit in Fig. 2; Fig. 5 is a circuit diagram of a counter circuit in Fig. 1; Fig. 6 is a timing chart to explain the operation of the dividing ratio control circuit in Fig. 3; and Fig. 7 is a block diagram of a conventional self-refreshing circuit. Detailed Description of the Invention Referring now to the drawings, one of the embodiments of this invention is described below. Fig. 1 is a block diagram showing a dynamic random access memory device in one embodiment of this invention, in which a memory cell matrix 21, a row line selection circuit 22, a sense refreshing amplifier 23, and a control clock generator 25 are the same as those of the conventional circuit shown in Fig. 7, substantially. A refreshing address counter 26 stores the row line address to be refreshed. An error correction address counter 13 is synchronized with the refreshing address counter 26 and stores the column address to be corrected. Row line selection circuit 22 selects any one of the lines of the memory cell matrix 21 for refreshing selected memory cells, and column selection circuit 11 selects any one of the columns of the memory cell matrix for correcting selected memory cells. Error detection circuit 12 detects the error of the data read out from the memory cells by the self refreshing amplifier 23 and rewrites the correct data to the memory cells, and then, generates an error detection signal EDS when the error correction is executed. A counter circuit 14 receives a carry signal RCC from the error correction address counter 13, and is reset by the error detection signal EDS delivered from the error correction circuit 12. The clock period of the self-refreshing clock generator 15 is varied by the error detection signal EDS from the error correction circuit 12 or the control signal PDS from the counter circuit 14. Numerals 16, 17 are control signal lines of error detection signal EDS and control signal PDS. Fig. 2 is a block diagram showing a detailed structure of the self-refreshing clock generator 15. The self-refreshing clock generator 15 is composed of monostable multivibrator 31 which is self-excited, a dividing circuit 32 for dividing the output signal of the monostable multivibrator, and a dividing ratio control circuit 33 for varying the dividing ratio of the dividing circuit 32 depending on the error detection signal EDS and control signal PDS supplied from control signal lines 16, 17. The circuit diagram of the dividing ratio control circuit 33 is shown in Fig. 3. The dividing ratio control circuit 33 is composed of a binary up/down counter which is comprised of T-flip-flops 41, 45, RS-flip-flop 42 and peripheral logic circuits thereof, a decoder 43 for decoding the outputs Q1, Q2 of the T-flip-flops 41, 45 and generating output signals A, B, C, D, and two AND gates 44, 44′ for controlling signals EDSG, PDSG depending on the signals EG, PG generated based on the state of said binary up/down counter outputs Q1, Q2. The dividing circuit 32 is, as shown in Fig. 4, composed of four T-flip-flops 51 to 54, and five NAND gates 55 to 59. The input signal CLK from the monostable multivibrator shown in Fig. 2 is fed into an input terminal of the T-flip-flop 51 of the first stage, and its output Q1 is fed into an input terminal of the T-flip-flop 52 of the second stage. Similarly, the Q2 output of the second stage T-flip-flop 52 is fed into an input terminal of the T-flip-flop 53 of the third stage. The NAND gate 55 receives the input signal CLK and an output signal A of the dividing ratio control circuit 33, and the NAND gates 56 to 58 respectively receive the outputs Q1 to Q3 of T-flip-flops 51 to 53, and output signals B to D of the dividing ratio control circuit 33, and the outputs of all NAND gates 55 to 58 are fed into the NAND gate 59. In consequence, the output of the NAND gate 59 is fed into an input terminal of the T-flip-flop 54 of the final stage, and its output Q4 is supplied into the control clock generator 25 shown in Fig. 1 as a self-refreshing clock SRC. The circuit diagram of counter circuit 14 is shown in Fig 5. The counter circuit 14 is composed of a binary counter having a cascade connection of N T-flip-flops 61. Receiving a carry signal RCC coming from MSB (Most Significant Bit) of the error correction address counter shown in Fig. 1, all T-flip-flops 61 are reset by the error detection signal EDS from the error correction circuit 12 shown in Fig. 1. The QN output of the T-flip-flop 61 of the final stage is applied to the self-refreshing clock generator 15 in Fig. 1 as the control signal (counter output) PDS. Below is explained the operation of the self-refreshing circuit of the dynamic random access memory of this embodiment composed as stated above. The self-excited self-refreshing clock generator 15 generates a self-refreshing clock SRC of period T R . This period T R varies with the error detection signal EDS from the error correction circuit 12 and the counter output PDS from the counter circuit 14. Within this one period T R , self-refreshing action is done as follows. First, the memory cells corresponding to a row line specified by the refreshing address counter 26 and selected by the row line selection circuit 22 are simultaneously refreshed (read and written again) by the sense refreshing amplifier 23. At the same time, one memory cell specified by the error correction address counter 13 and selected by the column selection circuit 11 is selected. Said selected memory cell is one of the memory cells corresponding to a row line selected by the row line selection circuit 22. The data read out from the selected memory cell is judged by the error correction circuit 12 judged if correct or wrong, and if wrong, correct data is written again, and an error detection signal EDS is generated. Afterwards the refreshing address counter 26 is incremented, and the row line address to be refreshed is set in the next refreshing cycle. Suppose the memory cell matrix 21 is composed of m row lines by n columns, refreshing of all memory cells is over in m periods of said self-refreshing cycle, and correction of errors of all memory cells is over in m × n periods. Incidentally, the operation of the self-refreshing clock generator 15 is as follows. This self-refreshing clock generator 15 includes a self-excited clock generator (the monostable multivibrator 31 in this embodiment), and the dividing ratio of the output of the monostable multivibrator can be changed from 1/2 to 1/16 depending on the error detection signal EDS and counter output PDS, so that the period may be varied according to these signals EDS, PDS. When the counter output PDS falls, the dividing ratio becomes 1/2 times, and when the error detection signal EDS falls, the dividing ratio becomes 2 times. However, if the fall of the counter output PDS is entered more than four times, the minimum dividing radio does not become smaller than 1/6. Similarly, when the fall of error detection signal EDS is entered more than four times, the dividing ratio will not become more than 1/2. Therefore, if the period of the output CLK of the monostable multivibrator 31 in Fig. 2 is 100 µs, the self-refreshing clock SRC from the dividing circuit 32 is any one of 200 µs (minimum period), 400 µs, 800 µs, and 1600 µs (maximum period), and at every one fall of counter output PDS, it changes 2 times (to the maximum of 1600 µs), and every one fall of error detection signal EDS, it changes 1/2 times (to the minimum of 200 µs). The operation timing of the dividing ratio control circuit 33 shown in Fig. 3 is shown in Fig. 6. Signal EG works to prevent the fall of the error detection signal EDS from being fed into the T-flip-flop functioning as a down counter when the outputs Q1, Q2 of two T-flip-flops 41, 45 are 0 in binary notation, so that the outputs Q1, Q2 may not be inverted to 1. Similarly, signal PG works to prevent the fall of the counter output PDS from being fed into the T-flip-flop functioning as an up counter when the outputs Q1, Q2 of T-flip-flops 41, 45 are both 1 in binary notation, so that the outputs Q1, Q2 may not be inverted to 0. These outputs Q1, Q2 are decoded by the decoder 43, and dividing ratio control signals A, B, C, D are obtained. One of these dividing ratio control signals is always 1 in binary notation, while others are 0, and the dividing ratio of the dividing circuit 32 in Fig. 4 is determined. For example, when signal B is binary 1, and others are binary 0, the output Q1 of the T-flip-flop 51 is entered in the T input of the T-flip-flop 54, so that the dividing ratio is 1/4. When signal A is binary 1, the dividing ratio is 1/2, and when D is 1, it is 1/16. In this way, the period T R of self-refreshing clock varies with the error detection signal EDS and counter output PDS. An error detection signal EDS occurs when there is an error in the data during self-refreshing cycle. Therefore, while executing self-refreshing in a certain period T R , every time an error occurs, T R decreases to half. On the other hand, the counter output PDS is the output of dividing the carry signal RCC coming from the MSB of the error correction address counter 13 by the counter shown in Fig. 5. Therefore, supposing the number of stages of the counter circuit 14 to be N, as far as there is no error in the data being read out in the period of m × n × 2 N , the counter output PDS rises once and falls once. Accordingly, if there is no error in the data for a period of m × n × 2 N , the period T R becomes 2 times longer. Thus, in this embodiment, since the self-refreshing clock period T R can be controlled by the error detection signal EDS and counter output PDS, self-refreshing can be executed in the period T R , suited to the actual value of the pause time T H of the memory cell. For example, when the ambient temperature decreases by 10°C and the pause time T H doubles, the counter output PDS is generated, and the self-refreshing period is also increased twice. In this way, if the pause time T H varies, self-refreshing action can be executed always at a value close to the maximum value of the period T R , so that the current consumption may be reduced greatly as compared with that of the conventional fixed period type. Besides, in the conventional method, since the refreshing clock period T R was determined at the upper limit of the operating temperature range, malfunctions occurred if exceeding that temperature in this embodiment, by contrast, since the refreshing clock period T R changes to become shorter, and there is no risk of malfunction, and it is possible to extend the upper limit of the operating temperature range without increasing the self-refreshing current at the temperature in usual operation. In this embodiment, meanwhile, the dividing ratio of self-refreshing clock is set at 1/2 k (where k is 1, 2, 3, 4), but the change of the dividing ratio may be set finer by increasing the number of stages of flip-flop or extending the range of dividing ratio. Besides, the control signal PDS is generated by the counter circuit 14, but it may be also generated by the timer circuit which delivers a signal when error does not occur for a predetermined period. In the above-mentioned embodiment, the clock period of self-refreshing clock is varied by using the error detection signal generated from the error correction circuit 12. However, for simplifying the circuit structures, it is also possible as one embodiment that in place of error correction circuit 12 in the forgoing embodiment, using just an error detection circuit which generates an error detection signal, the period of self-refreshing clock is varied by using this error detection signal from the error detection circuit. The effect of current decrease at the time of self-refreshing is also achieved in this embodiment. And in this embodiment, the error correction may be made by an external error correction circuit. Thus, according to this invention, by installing a self-refreshing clock generator capable of varying the period by the control signal generated in the error correction circuit, self-refreshing can be executed in a self-refreshing period close to the maximum depending on the actual pause time value even if the pause time of the memory cell varies significantly depending on the manufacturing process condition, so that the current consumption in the self-refreshing time can be decreased. Or even if the operating conditions change or the pause time of the memory cell should vary, it is possible to operate in the maximum self-refreshing period always depending on the conditions. What is more, the upper limit of the operating temperature condition can be heightened without increasing the self-refreshing current at the ordinary operating temperature.

Claims: 1. A dynamic random access memory with a self-refreshing function comprising: a memory cell matrix (21) having a plurality of memory cells arranged in a matrix form; row line selection circuit (22) and column selection circuit (11) for selecting any one of the row and column of said memory cell matrix; a sense refreshing amplifier (23) for reading out the data in the memory cells in said memory cell matrix selected by said row line selection circuit and writing data again into the same memory cells for refreshing; an error correction circuit (12) for detecting and correcting an error in the data in the memory cell among said memory cells selected by said line selection circuit; address counter means (26, 13) for storing the address of the row and column of the memory cell to be refreshed and corrected; a self-refreshing clock generator (15) with a variable clock period; a control clock generator (25) for receiving a self-refreshing clock from said self-refreshing clock generator, and supplying a series of control clock pulses to said address counter means, row line selection circuit, column selection circuit, sense refreshing amplifier and error correction circuit; and control means (14) for controlling the clock period of said self-refreshing clock generator by an error detection signal (EDS) delivered from said error correction circuit when said error correction circuit corrects an error so as to keep said clock period in the vicinity of the maximum value of the pause time of said memory cell. 2. A dynamic random access memory with a self-refreshing function according to claim 1, wherein said control means (14) controls so as to shorten the clock period of said self-refreshing clock generator every time said error detection signal is generated, and to extend the clock period of said self-refreshing clock generator when there is no error in the data being read out for a predetermined period. 3. A dynamic random access memory with a self-refreshing function according to claim 1, wherein said control means (14) contains a counter circuit (14) which counts by the carry signal (RCC) coming out from said address counter means (13) storing said column address and is reset by the error detection signal (EDS) from said error correction circuit (12), and the clock period of said self-refreshing clock generator (15) is varied by said error detection signal (EDS) and the output signal (PDS) of said counter circuit. 4. A dynamic random access memory with a self-refreshing function according to claim 3, wherein said self-refreshing clock generator (15) is composed of a self-excited clock generation source (31), a dividing circuit (32) for dividing the clock frequency from said clock generation source, and a dividing ratio control circuit (33) for controlling the dividing ratio of said dividing circuit by said error detection signal (EDS) and the output signal (PDS) of said counter circuit. 5. A dynamic random access memory with a self-refreshing function according to claim 4, wherein the dividing ratio of the dividing circuit (32) of said self-refreshing clock generator (15) is increased every time said error detection signal (EDS) is generated, and the dividing ratio of said dividing circuit is decreased by the output (PDS) of said counter circuit (14). 6. A dynamic random access memory with a self-refreshing function according to claim 1, wherein said control means contains a timer circuit for generating an output at a predetermined timing, and the clock period of said self-refreshing clock generator (15) is varied by said error detection signal (EDS) and the output signal of said timer circuit. 7. A dynamic random access memory with a self-refreshing function according to claim 6, wherein said self-refreshing clock generator (15) is composed of a self-excited clock generation source (31), a dividing circuit (32) for dividing the output from said clock generation source, and a dividing ratio control circuit (33) for controlling the dividing ratio of said dividing circuit by said error detection signal (EDS) and the output signal of said timer circuit. 8. A dynamic random access memory with a self-refreshing function according to claim 7, wherein the dividing ratio of the dividing circuit (32) of said self-refreshing clock generator (15) is increased every time said error detection signal (EDS) is generated, and the dividing ratio of said dividing circuit is decreased by the output signal of said timer circuit. 9. A dynamic random access memory with a self-refreshing function comprising: a memory cell matrix (21) having a plurality of memory cells arranged in a matrix form; refreshing means (23) for reading and rewriting the data of a memory cells in said memory cell matrix; error detection means for detecting an error in data in said memory cell during refreshing action by said refreshing means; clock generating means (15, 25) with a variable clock period for supplying clock pulses to said refreshing means and error detection means; and control means (14) for controlling the clock period of said clock generating means by an error detection signal generated by said error detection means, so as to keep said clock period in the vicinity of the maximum value of the pause time of said memory cell. 10. A dynamic random access memory with a refreshing function according to claim 9, and further comprising error correction means for correcting an error in data in said memory cell during refreshing action by said refreshing means (23), wherein the control means (14) is adapted for controlling the clock period of the clock generating means (15) by an error detection signal generated at the time of error correction by said error correction means. 11. A dynamic random access memory with a refreshing function according to claim 9 or 10, wherein said control means (14) controls so as to shorten the clock period of said clock generating means every time said error detection signal is generated, and to extend the clock period of said clock generating means when there is no error in the data being read out for a predetermined period.

Inventors: OHSAWA, AKIRA 3A-316, 151-30, NINOMARU-CHO
Applicants: MATSUSHITA ELECTRONICS CORPORATION
Application year: 1988
Main classification: G11C11
IPC codes: G11C11, G11C29