Thin film active matrix and addressing circuitry therefor

Abstract: In a matrix display device, such as an LCD-TV, supply of data signals to each one of an array of display elements is controlled by respective switching means in response to applied switching signals. Novel addressing circuitry is provided to achieve redundancy and avoid improper charge levels on non-selected switching means.

Description: The invention relates to a display device comprising a plurality of display elements arranged in an array of rows and columns, each of which display elements comprises opposed electrodes with electro-optical material therebetween and is associated with switching means operable to control the application of data signals to the display element via column conductors in response to switching signals being applied thereto via row conductors, addressing circuitry being provided to apply the data signals and the switching signals to their respective column and row conductors, the addressing circuitry for at least one of the row and column conductors including one primary transistor connected to one end of the even-numbered conductors and one primary transistor connected to the opposite end of the odd-numbered conductors. A display device of this kind is suitable for displaying alphanumerical and video information using for the electro-optical layer materials like liquid crystal and electrophoretic suspensions. A display device of the type mentioned above is described in EP-A-197 551. In the device shown the conductors of one type e.g. the row conductors are divided into groups while each conductor is provided with a primary transistor at both ends. If one of the conductors is broken a non-broken conductor is chosen to function as a redundant path during selection of the other conductors within the same group of conductors. A disadvantage of this device is that it is determined after completing the display device by inspecting an image on the screen which columns need to function as a redundant path. Apart from the laborious visual inspection the timing of the addressing circuitry has to be adapted dependent on the distribution of broken conductors. Furthermore a detour circuit, which has to drive the primary transistors at both ends of a column simultaneously has to be provided, which detour circuitry itself may cause extra yield problems. An object of the invention is to provide a novel redundancy scheme that will protect against line breaks without introducing the need of adjustment afterwards. To this end a device according to the invention is characterized in that one supplemental transistor is connected to each of the primary transistors for simultaneously supplying the same signals to a conductor and the next adjacent conductor. The device according to the invention provides redundancy to correct for line defects and requires no additional row or column lines or detour lines, and only one additional transistor for each row or column. Thus, a considerable saving in space requirements and complexity is achieved with only a modest increase in the additional number of components required. This feature is obtained by e.g. interconnecting the inputs of two TFTs, and connecting the outputs to respective adjacent row or column lines from one side of the matrix and doing the same thing on the opposite side with the next two adjacent row or column lines. In this way, if a conductor is broken, part of it will be addressed correctly, while the other part will be addressed by the information of the next column. In EP-A-0 236 167 redundancy is obtained by interconnecting the end parts of the conductors by means of resistances. The use of resistances restricts the material of the conductors in fact to low-ohmic metals like aluminium. Moreover the broken part of a conductor is now provided with a voltage determined by the information in the two adjacent conductors. A preferred embodiment uses a matrix configuration in which the address drivers are oriented in each section of neighbouring driver TFTs, such that all sources are interconnected. This arrangement, allows the reduction of external interconnections using the redundancy scheme described above. The active transistors, which include the pixel transistors, the address and selection drivers, are formed as TFTs, typically on a transparent substrate such as glass, using, for example, amorphous silicon or polysilicon technology. While II-VI compound semiconductors can also be used, polysilicon TFTs are preferred because in the smaller sizes required for projection TV applications, they exhibit a higher mobility and a lower photosensitivity. Embodiments of an active matrix device in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows schematically in simplified block form a conventional liquid crystal matrix display device employing a column and row array of display elements each of which is associated with respective switching means; Figure 2 shows diagrammatically a schematic illustrating double matrix addressing for a device of the type illustrated in Fig. 1 wherein the row and column addressing circuitry is divided up into multiple sections; Figures 3(a), 3(b) and 3(c) are schematics showing video preprocessors and their logical timing diagrams for column loading for a device of the type illustrated in Fig. 2; Figure 4 is a schematic showing one form of column addressing; Figure 5 is a schematic illustrating the addition of redundancy for the column lines in accordance with the invention; Figures 6(a) and 6(b) are schematics illustrating row addressing; Figure 7 is a schematic illustrating the addition of redundancy for the row lines in accordance with the invention; Figure 8 is a schematic illustrating the row scanning in accordance with the invention; Referring to Figure 1, a matrix display device which is suitable for displaying TV pictures comprises an active matrix addressed liquid crystal display panel 10 which consist of m rows (1 to m) with n horizontally arranged display elements 12 (1 to n) in each row. Only a few of the display elements are shown for simplicity. Each display element 12 has associated therewith a switching means 11 which serves to control the application of data signal voltages to the display element. The switching means 11 associated with all display elements 12 in a respective row are controlled via a common row conductor 14 which is supplied with a switching signal and to which the switching means are connected at points 22. The switching means 11 associated with all display elements 12 in a respective column are connected at points 23 to a common column conductor 15 to which data signal voltages for the display elements concerned are supplied. Thus there are m row conductors 14 and n column conductors 15, the two sets of conductors extending at right angles to one another. Outputs from the switching means 11 are connected to an electrode 16 of their respective display elements carried on a surface of a substrate of the device together with the conductors 14 and 15 and the switching means 11. A counter electrode 17 common to all display elements is carried on another surface of the substrate or on another substrate parallel to, and spaced from, this one substrate surface with, for example, TN liquid crystal material disposed therebetween. The one or the opposing substrates,which may be of glass, are provided with polarizer and analyzer layers in conventional manner. The liquid crystal material modulates light transmitted as by projection through the display elements according to the voltage applied thereacross, with each display element, defined by a respective electrode associated with a switching means on one substrate, an opposing portion of the common electrode on the other substrate and liquid crystal material therebetween, being operable to vary light transmission through the thus-produced panel in accordance with a drive voltage applied across its respective electrodes. The device is driven on a row at a time basis by scanning the row conductors 14 sequentially with a switching signal so as to turn on all the switching means in each row in turn and applying data signals to the column conductors for each row of display elements in turn as appropriate and in synchronism with the switching signals so as to build up a complete display picture. In the case of a TV display, these data signals comprise video information signals with each row of display elements being provided with video information signals corresponding to a TV line. Using one row at a time addressing, each switching means 11 of the addressed row is switched on for a time of, for example, TL, the active line time, during which the video information signals are transferred from the column conductors 15 to the display elements 12. Following row addressing and the termination of the switching signal, the switching means 11 of the row turn off, thereyby isolating the display elements from the conductors 15 and ensuring that the applied charge is stored on the display elements. The display elements stay in the state into which they were driven, determined by the applied data signal, until the next time the switching means are addressed, in case of non-interlaced scanning in the next field period. This implies that the data storage time is usually equal to the field time. The row conductors are addressed with switching signals by a control circuit 20 supplied with regular timing pulses. Video information (data) signals are supplied to the column conductors 15 from a control circuit 21. The circuit 21 is supplied with video signals and timing pulses in synchronism with row scanning and provides serial to parallel conversion appropriate to the row at a time addressing of the panel 10. Odd and even rows, and odd and even columns, are usually driven from opposite sides of the panel in order to reduce the number of connections from the control circuitry 20, 21 to the display 10 per millimeter. The addressing circuitry of blocks 20 and 21 has been realized by using the same TFT technology used to make the TFT pixel drivers 11 for the LCD matrix. Moreover, a row/column matrix scheme is used in the addressing circuitry that is similar to the row/column matrix scheme of the panel in order to reduce the number of connections to a level that can be conveniently made on these small area matrix arrays without adding additional processing steps. This is illustrated in Fig. 2, which also shows, schematically, that the addressing matrices 20, 21 can be uniformly distributed on the substrate around the periphery of the display array 10 in a manner that will not require excessive real estate or substrate area, yet will achieve minimizing the number of required connections. Fig. 2 shows the active (LCD) matrix 10 using double-matrix addressing. An addressing scheme is preferred in which both odd and even columns and odd and even rows are driven from opposite sides of the active matrix. In the examples to be given, a 480 x 640 active matrix will be used, but it will be understood that the invention is not limited thereto. The 320 odd columns in Fig. 2 are addressed from above, and the 320 even columns are addressed from below. Similarly, the 240 odd rows are addressed from the left and the 240 even rows from the right. The odd and even columns are both driven by (16x20) addressing matrices with 16 sections each controlling 20 columns. This thus requires 20 common column input signal lines for each side, labelled V o (1) ... V o (20) and V e (1) ... V e (20), V meaning the video signal inputs, the subscript "o" odd and the subscript "e" even. Each column input signal line is connected to one corresponding column of each section. In operation, the original incoming video signal has to be converted to a signal v(LC) suitable to drive the liquid crystal panel. The converted video signal is divided up into the 40 appropriate signals which when applied to the column input signal lines V o (1) ... V o (20) and V e (1) ... V e (20), will give the correct column signals at 15. This is accomplished with a known preprocessor 40, e.g. with two 1x20 video-multiplexers as off-substrate ICs. This preprocessor can be as simple as two 40-cell analog memories like known sample and hold circuits, with appropriate read/write facilities as illustrated in Figure 3(a). The normal TV line signal v(LC) is acquired and sampled over 40 successive intervals and the results stored in a 40-cell memory SH| B . In the example, this takes 40x40ns = 1.6 µs. While the next 40 intervals are acquired, sampled and stored in the other 40-cell memory SH| A , the contents of SH| B is connected by switch 95 to the V o (1) ... V o (20) and V e (1) ... V e (20) lines. In Figs. 3(a), 3(b) and 3(c), the legend video → A signifies the acquisition time of a known sample/hold circuit, the legend A → panel indicates the time during which the sampled signal is supplied to the LCD panel, A and B representing the sample/hold circuitry. A preprocessor with two 40-cell memories requires cells with a small signal-acquisition time (40ns for progressive scanning), as illustrated in Fig. 3(a). This can be circumvented by using, as illustrated in Fig. 3(b), three 40-cell memories, with each 40-cell memory going through an acquisition mode, an acquisition/sample/hold mode, and a hold mode, with the modes of the three 40-cell memories being always different. Another more efficient circuit is illustrated in Fig. 3(c) without the need of additional memory. As will be observed in the logical timing diagrams for the Fig. 3(c) embodiment, the acquisition time of the sample and hold mode has been increased by decreasing the time that the sample and hold is connected to the panel. By this novel approach, the problem is simplified of providing sufficiently fast, cost-effective, off-substrate ICs to perform the necessary video multiplexing. As will be noted, the acquisition time for each sample and hold has been significantly increased with only a small reduction in the time available to pass the signals to the panel. In the illustrative example, reducing the signal to panel connection time from, say, 1.6 µs to 1.4 µs results in an acquisition time increase for SH| A (1) and SH| B (1) by a factor of about 6 (from 40 nS to 240 nS). A small penalty that results is a certain dead time, as illustrated, in which no signals are being transferred to the panel when switch 95 is at the unconnected terminal, in contrast to the embodiments of Figs. 3(a) and 3(b). The circuitry needed to implement this embodiment is straightforward, cost-effective and well within the skill of the artisan. If the preprocessor also contains two digital line stores with at least 640 cells each to realize the preferred non-interlaced scanning, any desired pattern of video signals can be simultaneously outputted by appropriate addressing of the line storage cells to the column selector lines via the two or three 40-cell analog, or digital, memories. The video signals that are outputted from the preprocessor onto the column selector lines V o (1) ... V o (20) and V e (1) ... V e (20) are chosen depending upon the addressing circuitry. In the instance illustrated in Fig. 2, the active line time TL/number of columns n x number of incoming video signals (for a progressive scan TV signal, 26 µS/ 640 columns x 40 ≅ 1.6 µS.) determines the maximum time interval each set of signals for a section sits on the column selector lines. With the circuitry illustrated where each line V is connected to the column lines by way of a column driver 30 whose gates for each section are interconnected and terminate at a control input C o (1) ... C o (16) and C e (1) ... C e (16), then the signal sequence is as follows. At T₁, the first 40 video signals appear on lines V, C o (1) and C e (1) are turned ON, C o (2) ... C o (16) and C e (2) ... C e (16) remain OFF for 1.6 µS, and the video signals are passed into the matrix. At time T₂, the next 40 video signals appear on lines V, C o (2) and C e (2) are turned ON (the remaining control lines remain off), and the next set of signals are passed on to the matrix. At the end of 26 µS, one line of the matrix can be activated. In this arrangement, columns 1...40 are assigned to section 1, column 41..80 to section 2, and so on. The "travelling-one" signal needed for C o (1) ... C o (16) and C e (1) ... C e (16) when the video-multiplexers shown in Figs. 3(a) and 3(b) are used is depicted in Fig. 9 (later explained more fully). In the present case the pulse duration is 1.6 µs and the pulse train starts at the beginning of the active line. These signals can be generated with a section scanner consisting of a 16 bit shift register that is started by the positive-going transition of h , and that is clocked at intervals of 1.6 µs. For the video-multiplexer given in Fig. 3(c), the C o (1) ... C o (16) and C e (1) ... C e (16) signals have to be gated during the intervals that no proper video signals are available (during the dead times). To reduce the number of connections to the substrate even further, this section scanner could be integrated on the substrate using the same thin-film technology. This will be discussed in more detail when the circuitry needed for the row drivers is described. The actual application of the video signals to the pixels can be done in one of two ways: by first loading the line of signals into intermediate column capacitors during the 26 µS, and then loading the pixel-capacitors with the charge on the column capacitors during the 6 µS horizontal flyback interval Tf, which means the row is selected during this 6 µS interval, or having the signals pass directly into the pixels during the 26 µS TL, which means the row is selected during the latter interval. A preference exists to the two step process of first loading intermediate capacitors during active line time and then loading the pixels during flyback because it reduces the speed requirements for the 307,200 pixel TFTs. A phase lock loop 90 (see Fig. 2) generates a clock signal with a period, in this case, of 40 ns that is locked to the horizontal and vertical synchronization pulses H and V of the incoming video signal. Appropriate timing circuitry 90 also derives H sync and V sync pulses from the clock (clk) signal. The addressing matrix arrangement for the rows is similar, the m = 480 rows being divided, for example, into 16 sections of 15 rows, each fed from opposite matrix sides. In this case, corresponding rows in each section are connected to the row driver lines indicated by S o (1) ... S o (15) and S e (1) ... S e (15) by way of individual transistors 32, whose gates within a section are commonly connected to control lines g o (1) ... g o (16) and g e (1) ... g e (16). Row 1 is selected by turning ON g o (1) and S o (1), row 2 by turning on g e (1) and S e (1), row 31 by turning on g o (2) and S o (1), and so on, for progressive scanning, which is preferred; if interlaced scanning is desired, then of course a frame of the odd rows can be first activated followed by a frame of the even rows. What is necessary for one column addressing mode and for the row addressing scheme is the ability to store voltage values (charge) over some interval. Each of the row and column lines have associated therewith a natural or parasite capacitance that can be used for this purpose. If it proves insufficient, an additional capacitor is easily added by thin film technology to be connected between each driver transistor 30,32 and the matrix 10, and ground. A different orientation of the driver transistors is preferred in which, instead of the gates, their sources are commonly connected for each section of neighbouring driver transistors, as this lends itself to incorporation of a novel redundancy scheme to increase yield. A schematic of the latter, but without redundancy, is illustrated in Fig. 4 in which the row-lines are not drawn. This figure shows 16 column selector lines C(1) ... C(16) at opposite sides, in the center the alternate arrangement of column lines 15 for two corresponding sections, at the left two columns lines 15′ from the previous corresponding sections, and at the right two columns lines 15″ from the next corresponding sections. In this instance,each of the column selector lines is connected to corresponding gates of column driver transistors 30, the drains of which are connected to their respective column lines 15. The source electrodes of all the transistors 30 for one section are interconnected for the top group to a common terminal labelled V o (k), and for the bottom group to a common terminal labelled V e (k), where k varies from 1..20. In the adjacent sections, the selector lines are connected to the gates of the corresponding column driver transistors 30′ and 30″. For this system to operate properly, for the redundancy scheme described below, the signals appearing on the upper and lower horizontal lines are sequential control pulses for 0.8 µS each which turn on one transistor 30,30′,30″ in each section. So assuming the two sections fully illustrated are the third and fourth sections, including column lines 33..64, the two sections on the left cover column lines 1..32, and the two sections on the right column lines 65..96, etc;then when C o (1) is ON (all the remaining C o (2) ... C o (16) and C e (1) ... C e (16) being OFF), the column drivers for lines 1, 33, 65 ... are activated. Now the video signal introduced at V o (k) for the second section must be the 33rd sample, and for V o (k+1) at the next section on the right must be the 65th sample, and so on. This is easily obtained by suitable programming of the preprocessor. On the next 0.8 µS, C e (1) is ON (all the remaining C o (1) ... C o (16) and C e (2) ... C e (16) being OFF), the video on the set of video lines V e (k) simultaneously applied must contain the 2nd, 34th, and 66th samples, etc. Otherwise, the operation is the same as for Fig. 2. Fig. 4 illustrates the supplemental and/or parasitic capacitors 35 associated with each column line, though only a few are shown. According to the present invention a redundancy scheme is provided to increase the yield of devices manufactured which may contain breaks or interruptions in the row or column electrodes of the active matrix. This is accomplished by addressing each active row or column from opposite ends with circuitry which applies the data signals for each row or column also to an adjacent row or column. Should a row or column conductor be interrupted due to a processing defect, each remaining row or column part conductor of the broken line will nevertheless receive either the correct data for that row or column, or the data for the previous row or column, which usually differs by only a small amount from the correct data and the resulting artifact will thus be barely perceptible, if at all, by an observer. The redundancy scheme of the invention is illustrated in Fig. 5 for only a few of the column lines, with the same reference numerals used as in Fig. 4 for corresponding elements. If one compares Figs. 4 and 5, it will be evident that one additional transistor 37 per column line has been added. Now consider the lines labelled l₃..l₅. Line l₃ is connected as before to the drain of the original or primary drive transistor 30₃, whose gate is commonly connected with the gate of supplemental transistor 37₃ whose drain is connected to column l₄, the next succeeding column line. Similarly, l₄ is driven at the bottom from primary transistor 30₄, whose supplemental transistor 37₄ drain is connected to line 5. When a selection control line C is turned ON, it turns ON not only the primary driver connected to a column line, but also the supplemental driver connected to the next higher-numbered column line. Thus, when a video signal is applied to V(k), two adjacent column lines contain the same signal. Moreover, each column line, except for the first in each section, is driven from opposite sides. Thus, if a line break occurs in an odd-numbered column line (except for the first in each section), video signals will be displayed on the line part above the break that will be correct, and the line part below the break will display the video signals of the previous adjacent column. If a break occurs in an even-numbered line, the line part below the break will display the correct video information and the part above the break the video information of the previous adjacent column. This slightly displaced information would be hardly noticeable to the user. If the redundancy scheme of Fig. 5 were not present, then no pixels could be activated below breaks in odd-numbered columns and above breaks in even-numbered columns. A missing line is a much more noticeable defect than a set of slightly displaced pixels. If no breaks are present, then each column but 1, 33, 65 first receives the video signal of the previous adjacent column and then, during the next part of the line scan, this wrong, but highly correlated information is overwritten by the right video signals, which is then stored for a frame time interval. The redundancy scheme shown thus protects 620 out of the 640 columns against line defects and driver transistor opens. For driver transistor shorts, suitable laser erasure of the shorted transistor would be necessary to convert the short to an open/break which is protected by this redundancy scheme. If this would not be done, a line-defect would be visible. The scheme does not protect against defects in the pixel transistors 11. The row addressing scheme is in certain respects similar to that for the columns, and is illustrated in two versions in Fig. 6. The rows are divided up into 16 sections of 15 rows each, using the same matrix technique for the connections to the row driver transistors 32. The required storage capacitor for each row is schematically illustrated at 39 only for the lowest rows but are present at all the rows, i.e., each row would contain its own capacitance. One section of rows is illustrated, the other sections being similar. Corresponding drivers 32 in each section are connected to the vertically-shown row selection lines common to all sections. In the version depicted in Fig. 6(b), each row selector line S(j) is connected to the source of the transistor 32 whose drain is connected to one of the 15 row lines 14 in that section. All the gates of the transistors 32 in the same section are interconnected and pass to a terminal g(k). There are 16 terminals g(k), one for each section. The rows are consecutive in each section; thus section 1 will handle rows 1..15, section 2 rows 16..30, etc. In the modified version depicted in Fig. 6(a), the same basic geometry exists, except now, the row selection lines g(1)..g(15) are connected each to one gate of the drivers 32, and the same source electrodes of all the drivers 32 in each section are interconnected to a terminal S(k), where again k varies from 1..16. Both versions allow incorporation of the same redundancy scheme used for the columns, illustrated schematically in Fig. 7 for four rows. The only requirement is that the control signals S and g for all driver TFTs are realized in such a way that any two driver TFTs connected to the same row are not activated (given a low impedance) simultaneously. The first row is M 2ℓ-1 , the second row M 2ℓ , etc. The normal or primary row driver transistors are indicated by 32 and the supplemental transistors by 40. Note that the sources of the primary 32 and the supplemental 40 transistors are interconnected. The gates of the primary 32 and supplemental 40 transistors for each pair of rows are also interconnected, but the drains are connected to adjacent rows, each of which is thus fed from opposite sides. The active pixels, consisting of elements 11 and 12, are shown as rectangles 41 connected to each row. The column lines are not drawn. Operation is as follows. Each row in turn is selected by applying an ON pulse to terminals S′(2ℓ-1) and g′(2ℓ-1), s′(2ℓ) and g′(2ℓ), etc., in sequence for, for example, the active line time TL. Alternatively, the pixel loading can occur during horizontal flyback time Tf. In either event, both the primary transistor 32₁ is turned ON, and due to the parallel connections, supplemental transistor 40₂ is also turned on. This means that the incoming video line is loaded into both the M 2ℓ-1 and M 2ℓ pixels, 41₁, 41₂. During the second line time, g′(2ℓ-1) is turned OFF and S′(2ℓ) and g′(2ℓ) turned ON, turning on transistors 32₂ and 40₃. This loads the next incoming video line into the pixels 41₂, 41₃ of rows M 2ℓ and M 2ℓ+1 . In the absence of line breaks, this second loading into row M₂ ℓ overwrites the previous (slightly incorrect) information so that line M 2ℓ now displays the correct video. Line M 2ℓ+1 displays the line M 2ℓ video, until it in turn is overwritten during the third cycle, and so on. So the viewer sees essentially a correct display. Redundancy for line breaks or driver transistor opens is achieved by the provision of the supplemental driver 40 for the next row, but receiving the source and gate signals for the previous row, thus addressing two adjacent lines at a time instead of only one. In case of a line break or open driver, illustrated in line M 2ℓ at 42, the pixels 41₂ to the left of the break will contain the line M 2ℓ-1 video, since, due to the break, they are not overwritten during the second cycle. The pixels 41₂ to the right of the break will contain the correct video. Instead of no information at all in the pixels to the left of the break, they now contain the highly correlated information of the previous row. This artifact will be hardly noticeable to the viewer.

Claims: A matrix display device comprising a plurality of display elements (12) arranged in an array of rows and columns, each of which display elements comprises opposed electrodes (16, 17) with electro-optical material therebetween and is associated with switching means (11) operable to control the application of data signals to the display element (12) via a set of column conductors (15) in response to switching signals being applied thereto via a set of row conductors (14), addressing circuitry (20, 21) being provided to apply the data signals and the switching signals to their respective column and row conductors, the addressing circuitry (20, 21) for at least one of the sets of row and column conductors including primary transistors (30, 32) connected at one end of the array to the even-numbered conductors and primary transistors (30, 32) connected at the opposite end of the array to the odd-numbered conductors, characterized in that a supplemental transistor (37, 40) is connected to each of the primary transistors (30, 32) for simultaneously supplying the same signals to a conductor and the next adjacent conductor. A matrix display device according to Claim 1, characterized in that the primary (30) and supplemental transistors (37) have source, drain and gate electrodes, the drain of each primary transistor is connected to a conductor and the drain of each supplemental transistor associated with each primary transistor is connected to the next adjacent conductor, means interconnecting the sources of the primary and their associated supplemental transistors, and means interconnecting the gates of the primary and their associated supplemental transistors. A matrix display device according to claim 1 further characterized in that the addressing circuitry for at least one sub-set of row and column conductors comprises an addressing matrix having first and second line sets and a plurality of driver transistors (30,32) each having source, drain, and gate electrodes connected such that the drains are each respectively connected to one of the conductors, the gates are correspondingly connected to lines in the first line set and the sources are commonly connected to one line in the second line set, and in that the switching signals are coupled to one line set of the first and second line sets and the data signals are coupled to the line set of said first and second line sets other than the one line set.

Inventors: DUWAER ARNE LEX, DUWAER, ARNE LEX
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1988
Main classification: G09G3
IPC codes: G09G3, G02F1