MEMORY UNIT

Abstract: A memory unit includes a dual port memory (15) provided with a RAS input terminal and a WB/WE input terminal adapted to receive a RAS clock signal and a bit select clock signal, respectively. A first signal generator (17) generates the RAS clock signal and the bit select write signal at a timing at which the dual port memory (15) performs the normal write operation, whereas the bit select write operation is carried out in response to clock signals supplied from a second signal generator (18) at another timing. A selective one of the first and second signal generators (17,18) is made operative in response to at least one bit mode-specifying data supplied from CPU (11). Both of the first and second signal generators receive a continuous signal from CPU so that they are in a position to send the signals of different timings to the dual port memory responsive to the mode-specifying data.

Description: This invention relates to a memory unit utilizing memory means adapted to perform a bit select write operation on data stored in a predetermined storage area and a newly transferred data and to store the operation results in said predetermined storage area. In conventional memory units, when a data already stored in a certain address and a newly entered data are to be subjected to, for instance, an OR operation, to store the results in said certain address, a central processing unit (CPU) operates to read the data stored in the certain address, to perform OR operation between this data and the new data and to send the results back to the certain address. This means that CPU has to issue at least three commands, making it difficult to reduce the time required for the operation. In order to solve this problem, there has been proposed to use a memory element which is operated such that a so-called bit select write operation is performed on a data existing in said pre-selected storage area with respect to a new data, said operation being effected directly on said pre-selected storage area to store the results in the same area. Such a memory element is known as a dual port memory. Access to the dual port memory for the normal write operation and the bit select write operation can be achieved through the respective input terminals, one for the normal write operation being in general referred to as a row strobe address input terminal (RAS terminal) and the other for the bit select write operation as a write per bit control/ write enable input terminal (WB/WE terminal). Setting the dual port memory to the normal write mode is accomplished by setting the WB/WE clock signal (write clock signal) sent from CPU to the WB/WE terminal to a high level at the trailing edge of the RAS clock signal which is likewise sent from CPU to the RAS terminal. In contrast, when the write clock signal is set to a low level at the trailing edge of the RAS clock signal, the dual port memory is switched to the bit select write mode. In this arrangement, however, it has also been necessary to provide the CPU with different kind of commands for switching the mode of the dual port memory, which is a bar to a development of faster processing operations. It is therefore an object of this invention to provided a memory unit capable of operating a given processing operation in a satisfactorily fast fashion. According to an aspect of this invention there is provided a memory unit comprising a memory element operated in response to a RAS clock signal and a bit select clock signal to selectively perform a normal write operation for storing data in a given storage area thereof or a bit select write operation for operating on data stored in a predetermined storage area thereof with respect to a newly supplied data to store the results in the same storage area where the data has been stored; wherein the RAS clock signal and the bit select clock signal are supplied to said memory element at a first timing whereat said memory element performs the normal write operation and the RAS clock signal and the bit select clock signal are supplied to said memory element at a second timing whereat said memory element performs the bit select write operation characterized in that a first timing signal generator is provided for supplying to said memory element the RAS and bit select clock signals at said first timing; a second timing signal generator is provided for supplying to said memory element the RAS and bit select clock signals at said second timing; control means are provided for generating said data and address data including at least one bit data assigned to specify either the normal write operation and the bit select write operation; and data select means are provided operated in response to said at least one bit data to send a write command signal to a selective one of said first and second timing signal generators to effect a corresponding one of operational modes of said memory element. According to a second aspect the present invention provides a method of controlling a dual port memory including a random access memory operable in a normal write operation for storing data in a given storage area thereof or a bit select write operation for operating on data stored in a predetermined storage area thereof with respect to a newly supplied data to store the results in the same predetermined storage area where the data was stored, comprising the steps of generating an RAS clock signal and a bit select clock signal and supplying them to the dual port memory at first or second relative timings; the dual port memory operating in the normal write mode in response to said first relative timing and the bit select mode in response to said second relative timing; characterized by the step of generating address data including a first word for addressing the random access memory and a second word for specifying either the normal write operation or bit select operation. Thus with the invention the memory unit has a central processing unit which has no need to give different commands for switching function of a dual port memory between the normal write mode and the bit select write mode. The invention also provides data processing apparatus incorporating such a memory unit. The invention will be further described by way of non-limitative example with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a memory unit embodying the invention; Fig. 2 is an explanatory view illustrating the dual port memory used for the memory unit of Fig. 1; and Fig. 3(a) and 3(b) are time chart of RAS clock signal and write clock signal for selecting between the normal write mode and the bit select write mode of the dual port memory. Referring to Fig. 1, a central processing unit 11 (which is simply referred to as CPU hereinlater) is provided with a program memory 12 storing a control program and a work memory 13 for temporarily storing the operation results of CPU 11 to perform operations in accordance with the control program. CPU 11 sends to a dual port memory 15 via a data bus 14 address data to be written into the memory 15. The address data as a whole accommodates more than 16 bits, including 8 bits of column address data, 8 bits of row address data and at least one bit higher than these 16 bits used as a data for specifying either the normal write mode or the bit select write mode. In this embodiment, when this additional one bit is "0", it is considered as specifying the normal write mode, while the bit "1" represents the bit select write mode. The dual port memory 15 includes a random access memory (RAM) 15a and a serial access memory (SAM) 15b, as shown in Fig.2. RAM 15a consisits of a memory cell array of 256 X 1024 bits, the storage area of which is divided into row addresses and column addresses. The row addresses range from 0 to 255 and the column addresses for each row address cover 0 to 255 with four bits assigned to each column. A certain storage area is selected in accordance with a row address data and column address data supplied from CPU 11. The mode-specifying bit is entered into the memory 15 as an address data. Although a virtual storage area is provided for RAM 15a of the memory 15, the said one bit is nullified by a built-in address controller (not shown) as it is located at an address higher than 16 bits. SAM 15b accommodates 1 X 1024 bits to retain a 1 X 1024 bit data (1-frame data) stored in each column address per row address within RAM 15a. The dual port memory 15 is provided with a RAS terminal and a WB/WE terminal. The memory is set to the normal write mode when, as shown in Fig. 3(a), write clock signal CL₂ output at WB/WE terminal is at a high level at the trailing edge of RAS clock signal received at the RAS terminal. On the other hand, it is set to the bit select write mode when write clock signal CL₂ is at a low level at the trailing edge of RAS clock signal CL₁, as shown in Fig. 3(b). A chip selector 16 serving as a data selecting means receives via the data bus 14 the mode-specifying one bit data. When the mode-specifying one bit data is "0", it determines the normal write mode to be selected and sends a drive control signal to a normal write mode signal generator circuit 17. With the mode-specifying one bit data of "1", on the other hand, the chip selector 16 is operated to select the bit select write mode to send a drive control signal to a bit select write signal generating circuit 18. The normal write signal generator 17 responds to the drive control signal from the chip selector 16 and the write control signal from CPU 11 to generate the RAS clock signal CL₁ and the write clock signal CL₂ at the RAS terminal and WB/WE terminal of the dual port memory 15 respectively, to thereby set the memory to the normal write mode. The bit select write signal generator 18 likewise responds to the drive control signal and the write control signal to generate the RAS clock signal CL₁ and the write clock signal CL₂ at the RAS terminal and WB/WE terminal of the dual port memory 15 respectively, to thereby set the memory to the bit select write mode. This mode may be used, for example, in a character memory for composition of characters other than those preset in the memory to be printed. For example, the symbol representing unit of Japanese currency "¥" is compounded of "Y" and "=", and "Ä" is of "A" and "¨". A bold-faced character can be prepared also in the bit select write mode by printing the same character twice or more at slightly different points of the printing paper. The operation of the memory unit arranged as explained above will be described below. Now suppose that the data should be written in the area defined by row addresses 0 to 255 and column addresses 0 to 255 of RAM 15a of the dual port memory 15. CPU 11 transfers column address data and row address data to the dual port memot memory 15 via data bus 14, while sending a write control signal to the normal write signal generator 17 and the bit select write signal generator 18. At this time, CPU 11 sets the mode-specifying one bit data to "0". With the address specified in RAM 15a in accordance with the column and row address data, the chip selector 16 determines the normal write mode to be selected in response to the mode-specifying one bit data of "0" and thus feeds a drive control signal to the normal write signal generator 17. The normal write signal generator 17 then sends a RAS clock signal CL₁ to the RAS input terminal and also a write clock signal CL₂ to the WB/WE input terminal in response to the drive control signal and write control signal to thereby set the dual port memory 15 to the normal write mode. The dual port memory 15 is thus set to a normal write mode in accordance with the clock signals CL₁ and CL₂, and writes the data transferred from CPU 11 into the addresses specified by the respective address data. Now supposed an OR operation is performed on the data stored at a given address within the row addresses of 0 to 255 and the column addresses of 0 to 255 and a new data transferred from CPU 11, and the result of operation is writen into the specified address. The operation procedures are described as follows. CPU 11 transfers the column and row address data to be operated to the dual port memory 15 via data bus 14, while feeding a write control signal to the signal generators 17 and 18 as described earlier. At this time, the mode-specifying one bit data sent from CPU 11 is "1". The address within RAM 15a is specified by the column and row address data, while the chip selector 16 determines that the bit select write mode has been selected because the one bit data is "1" to generate a drive control signal at the bit select write signal generator 18. The bit select write signal generator 18 delivers RAS clock signal CL₁ to the RAS input terminal and write clock signal CL₂ to the WB/WE input terminal in response to the drive control signal and write control signal so as to set the dual port memory 15 to the bit select write mode. The dual port memory 15 is thus set to the bit select write mode in accordance with clock signals CL₁ and CL₂ received from the bit select write signal generator 18. It then performs OR operations on the data transferred from CPU 11 and the data stored in the address specified above and stores the operation results in the same address. For instance, the operation result stored in the specified address is "1, 0, 1, 1", when the data stored in the specified address is "1, 0, 1, 0" and the data transferred from CPU 11 is "1, 0, 0, 1". According to this embodiment, therefore, one bit of address data is assigned as a data for specifying either the normal write mode or a bit select write mode and the chip selector 16 determines the mode selected. Thus, selected one of the signal generators 17 and 18 is operated in response to a signal from the chip selector 16 to output RAS clock signal CL₁ and write clock signal CL₂. Accordingly, CPU 11 has only to deliver the write control signal to the normal write signal generator 17 and the bit select write signal generator 18. As a result, it is not necessary to reset mode every time the write mode is changed, obviating time loss to achieve a faster operation processing. It should be understood that this invention be not limited to a specific embodiment thereof illustrated herein. For instance, the mode-specifying one bit data can be replaced by any one of 8 row address bits (the highest bit, for example) or at a given bit of column address data.

Claims: A memory unit comprising a memory element (15) operated in response to a RAS clock signal and a bit select clock signal to selectively perform a normal write operation for storing data in a given storage area thereof or a bit select write operation for operating on data stored in a predetermined storage area thereof with respect to a newly supplied data to store the results in the same storage area where the data has been stored; wherein the RAS clock signal and the bit select clock signal are supplied to said memory element (15) at a first timing whereat said memory element (15) performs the normal write operation and the RAS clock signal and the bit select clock signal are supplied to said memory element (15) at a second timing whereat said memory element (15) performs the bit select write operation characterized in that a first timing signal generator (17) is provided for supplying to said memory element (15) the RAS and bit select clock signals at said first timing; a second timing signal generator (18) is provided for supplying to said memory element (15) the RAS and bit select clock signals at said second timing; control means (11) are provided for generating said data and address data including at least one bit data assigned to specify either the normal write operation and the bit select write operation; and data select means (16) are provided operated in response to said at least one bit data to send a write command signal to a selective one of said first (17) and second (18) timing signal generators to effect a corresponding one of operational modes of said memory element (15). A memory unit according to claim 1 wherein said first timing signal generator (17) is made operative to allow said memory element (15) to perform the normal write operation when the bit select clock signal is at a high level at a trailing edge of the RAS clock signal, while said second timing signal generator (18) is made operative to allow said memory element (15) to perform the bit select write operation when the bit select clock signal is at a low level at a trailing edge of the RAS clock signal. A memory unit according to claim 1 or 2, wherein said memory element (15) comprises a dual port memory (15) provided with first and second input terminals adapted to receive the RAS clock signal and the bit select clock signal, respectively. A memory unit according to any one of the preceding claims wherein the memory element (15) comprises a random access memory (15a) and a serial access memory (15b). A memory unit according to claim 4 wherein said address data comprises 16 bits for addressing the random access memory (15a) and one bit specifying the write operation to be performed at the specified address. A memory unit according to any one of the preceding claims wherein said first and second timing signal generators (17,18) are continuously supplied with a signal from a C.P.U. (11). A memory unit according to claim 6 wherein said C.P.U. (11) comprises said control means (11). Data processing apparatus including a memory unit according to any one of the preceding claims. A method of controlling a dual port memory including a random access memory operable in a normal write operation for storing data in a given storage area thereof or a bit select write operation for operating on data stored in a predetermined storage area thereof with respect to a newly supplied data to store the results in the same predetermined storage area where the data was stored, comprising the steps of generating an RAS clock signal and a bit select clock signal and supplying them to the dual port memory at first or second relative timings; the dual port memory operating in the normal write mode in response to said first relative timing and the bit select mode in response to said second relative timing; characterized by the step of generating address data including a first word for addressing the random access memory and a second word for specifying either the normal write operation or bit select operation. A method according to claim 9 wherein said first word comprises 16 bits and said second word comprises a single bit.

Inventors: HATTORI, TOMOAKI C/O BROTHER KOGYO K.K.
Applicants: BROTHER KOGYO KABUSHIKI KAISHA
Application year: 1988
Main classification: G11C7
IPC codes: G06F12, G11C7, G11C8, G06F13