Method of manufacturing a field-effect transistor having a junction gate

Abstract: In a method of manufacturing a GaAsFET, an insu­ lating film (16) used as a mask for implanting ions (Zn⁺) to form a gate region (25) is used as a mask for sputtering a material of a gate electrode (20). Consequently, the gate electrode (20) is formed to be aligned with the gate region (25). A GaAsFET in which the gate electrode (20) can be stably positioned with respect to the small gate region (25) with a high degree of accuracy and which is suitable for high frequency applications can be manufactured.

Description: The present invention relates to a method of manufacturing a semiconductor device comprising the steps of: implanting Si ions in a III-V group compound semiconductor substrate and forming a first ion-implantation layer of N- type on a major surface layer of said substrate; forming a first insulating film on the major surface of said substrate; forming a second insulating film having an opening portion on said first insulating film; forming an opening portion in said first insulating film by selective etching using said second insulating film as a mask; implanting Zn ions in said first ion-implantation layer through said opening portion of said second insulating film and forming a second ion-implantation layer of p- type in a surface layer thereof; forming, on the major surface of said structure, while said second insulating film remains, conductor layers in which at least a layer thereof contacting said semiconductor substrate is either a refractory metal layer or a layer containing a refractory metal; removing said second insulating film to remove said conductor layer portion formed thereon, thereby forming an electrode so that only said conductor layer portion exposed in said opening portion of said second insulating film and formed on said substrate remains; and annealing said structure to activate said first and second ion-implantation layers. Such a method is known from JP-A-57 178 374. A known example of a field effect semiconductor device using a III - V Group compound semiconductor as a substrate is a GaAsFET (GaAs field effect transistor). Examples of the GaAsFET are a MES (metal semiconductor) FET and a J-FET (junction type). A so-called MES type FET using a Schottky barrier gate is widely used because its manufacturing process is simple. Junction barrier height B of the J-FET is as high as 1 V or more. Therefore, a sufficient operation margin can be obtained for a normally-off type J-FET. In addition, since either an N or P channel can be manufactured by selecting an impurity to be ion-implanted, a complementary circuit can be arranged. The type of J-FET varies in accordance with a formation type of a gate region. That is, the J-FET has a variety of types such as a diffusion junction type, an ion-implantation junction type, and an epitaxial growth junction type. In any of the above types, however, it is difficult to perform micropatterning of a gate portion as compared with the MES type, and a micropatterning technique for the J-FET has not been developed yet. That is, in a conventional technique, a gate region is formed in a semiconductor substrate, and then a gate electrode is positioned on the gate region by mask alignment. Thereafter, the gate electrode is formed by a lift-off method or etching. Alternatively, the gate electrode is formed not directly on the gate region but on a region electrically connected to the gate region. In this case, the gate region is a small region. This is because mutual conductance gm as a performance factor of a semiconductor device is proportional to W (channel width)/L (channel length) and therefore W must be increased and L must be decreased in order to increase the value of gm. Since the gate region is a small region, it is very difficult for current techniques to stably position the gate electrode on the small region with high accuracy by mask alignment, resulting in a very poor yield. In addition, when the gate electrode is formed on the region electrically connected to the gate region, a gate resistance is increased by a resistance of this region. For this reason, as an operation frequency is increased, a noise factor (NF) is increased and a gain is reduced. Therefore, this method is not preferable as a method of manufacturing a gate portion of a high frequency FET. As described above, in the method of positioning a gate electrode with respect to a gate region by mask alignment, the manufacturing yield is very poor. In the method of connecting a gate electrode with a gate region through a region connected to the gate region, a high frequency performance is degraded. The present invention has been made in consideration of the above situation and has as its object to provide a method of manufacturing a semiconductor device, which can stably position a gate electrode with respect to a small gate region with high accuracy and can manufacture a semiconductor device suitable for high frequency applications. According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of implanting Si ions in a III-V group compound semiconductor substrate and forming a first ion-implantation layer of N-type on a major surface layer of said substrate; forming a first insulating film on the major surface of said substrate; forming a second insulating film having an opening portion on said first insulating film; forming an opening portion in said first insulating film by selective isotropic etching using said second insulating film as a mask; implanting Zn ions in said first ion-implantation layer through said opening portion of said second insulating film and forming a second ion-implantation layer of P-type in a surface layer thereof; forming, on the major surface of said structure, while said second insulating film remains, conductor layers in which at least a layer thereof contacting said semiconductor substrate is either a refractory metal layer or a layer containing a refractory metal; removing said second insulating film to remove said conductor layer portion formed thereon, so that only said conductor layer portion exposed in said opening portion of said second insulating film and formed on said substrate remains, thereby forming an electrode, which does not completely cover the portion of the substrate exposed by said opening portion of said first insulating layer; implanting Zn impurity ions in said first ion-implantation layer using said electrode and said first insulating film as masks; and annealing said structure to activate said first and second ion-implantation layers. According to the methods of the present invention, the insulating film used as a mask during ion-implantation for forming the gate region can be used as a mask for sputtering the gate electrode material. Therefore, the gate electrode can be formed in self-alignment with the gate region. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1F are sectional views showing the structures of the device formed in manufacturing steps of a known method; and Figs. 2A to 2G are sectional views showing the structures of the device formed in manufacturing steps of a method according to an embodiment of the present invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figs. 1A to 1F are sectional views showing the structures of the device formed in manufacturing steps according to a known method of manufacturing an ion-implantation J-FET (junction type field effect transistor). Process 1 (Fig. 1A) Si is selectively ion-implanted in a major surface of GaAs substrate 10. At this time, ion-implantation is performed in prospective source and drain formation regions under conditions that acceleration voltage V ac is 180 KeV and dosage Q d is 5 × 10¹³/cm², thereby forming ion-implantation layers 11 and 12. In addition, ion-implantation is performed in a prospective channel formation region under conditions that acceleration voltage V ac is 100 KeV and dosage Q d is 3 × 10¹²/cm², thereby forming ion-implantation layer 13. Process 2 (Fig. 1B) SiO₂ film 14 is formed on the entire major surface of substrate 10 to have a thickness of 500 nm (5,000 Å) by CVD (chemical vapor deposition), and photoresist film 16 having opening portion 15 at a position corresponding to a gate region is formed on SiO₂ film 14. Subsequently, film 14 is etched by an isotropic etching technique using film 16 as a mask and an NH₄F solution, thereby forming opening portion 17 in film 14. Thereafter, Zn⁺ is ion-implanted in layer 13 through opening portions 15 and 17 under conditions that acceleration voltage V ac is 80 KeV and dosage Q d is 1 × 10¹⁵/cm², thereby forming ion-implantation layer 18 in layer 13. Process 3 (Fig. 1C) Conductor layer 19 is formed on the entire major surface of the structure of the device. Conductor layer 19 comprises a 100 nm (1,000-Å) thick lower TiW layer and a 500 nm (5,000-Å) thick upper Au layer, which are formed in an Ar gas atmosphere by a sputtering process. The TiW layer is formed on film 16 and the Au layer is formed on the TiW layer. At this time, TiW and Au are sputtered on layer 13 through opening portion 15 of film 16 and opening portion 17 of film 14, thereby forming conductor layer 19A on layer 13. Materials other than TiW and Au may be used, as long as an ohmic contact between the layer formed of the materials and the gate region is not degraded, even when the layers are annealed in the following step. For example, a single layer containing a refractory metal such as a WN layer or a WSi layer may be used. Alternatively, a bi-layered structure having a lower WN layer contacting GaAs substrate 10 and an upper Au layer may be used. That is, any kind of layer may be used in place of the above layer of this embodiment as long as the layer contacting substrate 10 is made of a refractory metal. Process 4 (Fig. 1D) By removing film 16, layer 19 formed on film 16 is simultaneously removed. That is, layer 19 is removed by a so-called "lift off" method. As a result, only layer 19A remains formed on layer 13 to form gate electrode 20. Process 5 (Fig. 1E) After film 14 is removed, PSG film 21 is formed by the CVD process on the entire major surface of the structure to have a thickness of 500 nm (5,000 Å). Thereafter, the structure is annealed for 15 minutes in an Ar gas at 800°C to activate the ion-implanted impurity, thereby forming N⁺-type source and drain regions 22 and 23, N-type channel region 24, and P-type gate region 25. By way of this annealing process, electrode 20 is formed in ohmic contact with region 25. Process 6 (Fig. 1F) Openings are formed in film 21 at positions corresponding to regions 22 and 23 to communicate with regions 22 and 23. Source and drain leading electrodes 25 and 27 each comprising a 200 nm (2,000-Å) thick lower AuGe film containing 5% of Ge and a 100 nm (1,000-Å) thick upper Au film are formed in the openings of film 21 by, e.g., a lift-off method. Thereafter, the structure is annealed at 400°C for three minutes to form an ohmic contact between source region 22 and source leading electrode 26 and an ohmic contact between drain region 23 and drain leading electrode 27. Following this annealing process, source and drain electrodes 28 and 29 are formed on source and drain leading electrodes 26 and 27, respectively, by, e.g., a lift-off method. Source and drain electrodes 28 and 29 may be a superposed structure composed of a Ti layer - Pt layer - Au layer. In this way, the J-FET is completed. In the FET manufactured by such a method, gate electrode 20 is in direct contact with gate region 25. Therefore, a gate resistance can be sufficiently reduced, and a noise factor and a gain at a high frequency is not degraded. In addition, since gate region 25 and gate electrode 20 are formed through opening portion 15 in photoresist film 16 by ion-implantation and sputtering, gate region 25 and gate electrode 20 are in self-alignment with each other. For this reason, even if region 25 is formed to occupy a small area, a positional deviation is not generated between region 25 and electrode 20, resulting in a high manufacturing yield. In the above method after gate electrode 20 has been formed, the structure is annealed to form source and drain regions 22 and 23 and channel and gate regions 24 and 25. During this annealing process, the impurity in ion-implantation layer 18 is activated and gate region 25 is formed to extend in the lateral direction. Since region 25 extends in the lateral direction, there is almost no possibility of gate electrode 20 contacting channel region 24. Figs. 2A to 2G are sectional views of the structures formed in manufacturing steps according to an embodiment in which the present invention is applied to a method of manufacturing an ion-implantation J-FET (junction type field effect transistor). Process 1 (Fig. 2A) Si is selectively ion-implanted in a major surface of GaAs substrate 10. At this time, ion-implantation is performed in prospective source and drain formation regions under conditions that acceleration voltage V ac is 180 KeV and dosage Q d is 5 × 10¹³/cm², thereby forming ion-implantation layers 11 and 12. In addition, ion-implantation is performed in a prospective channel formation region under conditions that acceleration voltage V ac is 100 KeV and dosage Q d is 3 × 10¹²/cm², thereby forming ion-implantation layer 13. Process 2 (Fig. 2B) SiO₂ film 14 is formed by a CVD process (chemical vapor deposition) on the entire major surface of substrate 10 to have a thickness of 500 nm (5,000-Å), and photoresist film 16 having opening portion 15 at a position corresponding to a gate region is formed thereon. Subsequently, film 14 is etched by an isotropic etching technique using film 16 as a mask and an NH₄F solution, thereby forming opening portion 17 in film 14. Thereafter, Zn⁺ is ion-implanted in layer 13 through opening portions 15 and 17 under conditions that acceleration voltage V ac is 80 KeV and dosage Q d is 1 × 10¹⁵/cm², thereby forming ion-implantation layer 18 in layer 13. Process 3 (Fig. 2C) Conductor layer 19 is formed on the entire major surface of the structure of the device. Conductor layer 19 comprises a 100 nm (1,000-Å) thick lower TiW layer and a 500 nm (5,000-Å) thick upper Au layer, which are formed in an Ar gas atmosphere by a sputtering technique. The TiW layer is formed on film 16 and the Au layer is formed on the TiW layer. At this time, TiW and Au are sputtered onto layer 13 through opening portion 15 of film 16 and through opening portion 17 of film 14, thereby forming conductor layer 19A on layer 13. Materials other than TiW and Au may be used, as long as an ohmic contact between the layer formed of the materials and the gate region is not degraded, even when the layers are annealed in the following step. For example, a single layer containing a refractory metal such as a WN layer or a WSi layer may be used. Alternatively, a bi-layered structure of a lower WN layer which is in contact with GaAs substrate 10 and an upper Au layer may be used. That is, any kind of layer may be used in place of the above layer of this embodiment as long as the layer contacting substrate 10 is made of a refractory metal. Process 4 (Fig. 2D) By removing film 16, layer 19 formed on film 16 is simultaneously removed. That is, layer 19 is removed by a so-called "lift off" method. As a result, only layer 19A formed on layer 13 remains to form gate electrode 20. Process 5 (Fig. 2E) Zn⁺ is ion-implanted again in substrate 10 using film 14 and electrode 20 as masks under conditions that acceleration voltage V ac is 80 KeV and dosage Q d is 1 × 10¹⁵/cm², thereby enlarging layer 18. Process 6 (Fig. 2F) After film 14 is removed, PSG film 21 is formed by the CVD process on the entire major surface of the structure to a thickness of 500 nm (5,000-Å). Thereafter, the structure is annealed in an Ar gas at 800°C for 15 minutes to activate the ion-implanted impurity, thereby forming N⁺-type source and drain regions 22 and 23, N-type channel region 24, and P-type gate region 25. By way of this annealing process, electrode 20 is formed in ohmic contact with region 25. Process 7 (Fig. 2G) Openings are formed in film 21 at positions corresponding to regions 22 and 23 to communicate with regions 22 and 23. Source and drain leading electrodes 26 and 27 each comprising a 200 nm (2,000-Å) thick lower AuGe film containing 5% of Ge and 100 nm (1,000-Å) thick upper Au film are formed in the openings of film 21 by, e.g., a lift-off method. Thereafter, the structure is annealed at 400°C for three minutes to form an ohmic contact between source region 22 and source leading electrode 26 and an ohmic contact between drain region 23 and drain leading electrode 27. Following this annealing process, source and drain electrodes 28 and 29 are formed on source and drain leading electrodes 26 and 27, respectively, by, e.g., a lift-off method. Source and drain electrodes 28 and 29 may be a superposed structure composed of a Ti layer - Pt layer - Au layer. In this way, the J-FET is completed. In the FET manufactured by the method according to this embodiment, gate electrode 20 directly contacts gate region 25. Therefore, a gate resistance can be sufficiently reduced, and a noise factor and a gain at a high frequency is not degraded. In addition, since gate region 25 and gate electrode 20 are formed through opening portion 15 in photoresist film 16, by ion-implantation and sputtering, gate region 25 and gate electrode 20 are in self-alignment with each other. For this reason, even if region 25 is formed to occupy a small region, a positional deviation is not generated between region 25 and electrode 20, resulting in a high manufacturing yield. In this embodiment, process 5 described with reference to Fig. 2E is added to the method described above with reference to Figs. 1A to 1F. That is, after gate electrode 20 is formed in process 4 (Fig. 2D), Zn⁺ is again ion-implanted in substrate 10 using film 14 and electrode 20 as masks under the conditions that acceleration voltage V ac is 80 KeV and dosage Q d is 1 x 10¹⁵/cm² in process 5 (Fig. 2E). Therefore, layer 18 which is to serve as gate region 25 is larger than that in the method shown in Figs. 1A to 1E. Since region 25 is enlarged in the lateral direction with respect to electrode 20, electrode 20 is prevented from contacting channel region 24. That is, conductor layer 19A which constitutes gate electrode 20 is formed by a sputtering process. At this time, since a sputtering direction of a conductor layer material is offset by a set angle range of a target, layer 19A may be formed to be larger than a predetermined size, although this is very rare. Even in this case, according to the embodiment shown in Figs. 2A to 2G, gate electrode 20 is prevented from contacting channel region 24 since gate region 25 is enlarged in the lateral direction with respect to electrode 20. As has been described above, according to the present invention, an FET in which a gate electrode can be positioned with respect to a small gate region with high accuracy and which is suitable for high frequency applications can be manufactured.

Claims: A method of manufacturing a semiconductor device, comprising the steps of: implanting Si ions in a III-V group compound semiconductor substrate (10) and forming a first ion-implantation layer (11 - 13) of N-type on a major surface layer of said substrate; forming a first insulating film (14) on the major surface of said substrate; forming a second insulating film (16) having an opening portion (15) on said first insulating film; forming an opening portion (17) in said first insulating film by selective isotropic etching using said second insulating film as a mask; implanting Zn ions in said first ion-implantation layer through said opening portion of said second insulating film and forming a second ion-implantation layer (18) of P-type in a surface layer thereof; forming, on the major surface of said structure, while said second insulating film remains, conductor layers (19, 19A) in which at least a layer thereof contacting said semiconductor substrate is either a refractory metal layer or a layer containing a refractory metal; removing said second insulating film to remove said conductor layer portion (19) formed thereon, so that only said conductor layer portion (19A) exposed in said opening portion of said second insulating film and formed on said substrate remains, thereby forming an electrode (20), which does not completely cover the portion of the substrate exposed by said portion (17) of said first insulating layer; implanting Zn impurity ions in said first ion-implantation layer (13) using said electrode (20) and said first insulating film (14) as masks; and annealing said structure to activate said first and second ion-implantation layers. A method according to claim 1, characterized in that said step of implanting Si impurity ions in said substrate (10) to form said first ion-implantation layer (11-13) on the major surface layer of said substrate is performed by implanting the impurity ions twice with different acceleration energies and dosages. A method according to claim 1 or 2 characterized in that said method of forming said opening portion (17) in said first insulating film (14) is performed by isotropic etching. A method according to any preceding claim, characterized in that said step of depositing said conductor layers (19, 19A) is performed by sputtering. A method according to any preceding claim, characterized in that said second insulating film (16) comprises a photosensitive resin film.

Inventors: INOUE KAZUHIKO C O PATENT DIVI, INOUE, KAZUHIKO C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L29