Counter

Abstract: A counter which is capable of performing a high-speed operation, through utilization of radix-N, for example radix-2, Signed-Digit redundancy representation, with a certain delay time of operation regardless of an increase in the desired count value. The counter comprises an initial value generator (17); a preset circuit (2) for presetting an initial value calculated by the initial value generator; an adder circuit (1) formed by plural digits of radix-N Signed-Digit adders, each including an adder, a transfer digit generator and an interim sum generator; and a circuit for detecting an overflow at a specified digital position.

Description: The present invention relates to a counter. To facilitate a better understanding of the present invention, a description will be given of a binary counter which is most commonly and widely used in the implementation of a logic circuit or similar one in an electronic computer or the like. A conventional high-speed binary counter includes a synchronous counter formed by D flip-flops, as shown in Fig. 4. The counting operation of this counter starts with presetting therein an initial value according to a count number, followed by count-up operation counter until it detects an overflow. Reference numeral 41 indicates binary counters and 42 initial value registers. Where a desired count value is between 0 and 2 n+1 - 1, (n + 1) flip-flops are connected and, in order to cause a digit i-th from the least significant one to perform a synchronous operation, it is necessary to detect the state in which digits less significant than the i-th digit are all 1s. Accordingly, the counting operation of the conventional system needs the AND of n+1 control signals for count-up control of the most significant digit. A CMOS (complementary MOS) circuit is usually employed for forming a large scale integrated circuit of small power dissipation, but the maximum fan-in limit of the CMOS circuit is as small as 5 or so. The prior art system includes a circuit of a large fan-in, and hence inevitably adopts a multi-stage configuration therefore, leading to the defect that the operating speed of the conventional high-speed counter decreases with an increase in the count value. "Modern Electronic Circuits Reference Manual", J. Markus, McGraw-Hill, 1980, page 239, circuit "Calculator/Counter" discloses a National MM5736 calculator chip the normal arithmetic functions of which are preserved while providing counting capability. When a reset switch is pushed the calculator is cleared, when it is released a 1 is entered in the calculator. In count mode, each input pulse adds 1 to the sum in the calculator. EP-A-0 029 706 discloses an arithmetic circuit with overflow detection capability in consecutive addition or subtraction operations on data represented in two's complement-fixed point notation. "Halbleiter-Schaltungs-Technik", U. Tietze and Ch. Schenk, 5th Edition, Springer Verlag, Berlin Heidelberg New York, 1980, pages 505 and 506, discloses a presettable counter which produces an output signal when the number of input pulses reaches a preselected value. An initial value P=Z max - M is loaded into the counter. After M pulses, Z max is reached and the output signal produced. Transactions of the IECE of Japan, Vol. E 69, No. 4, April 1986, pages 261 to 263 (see also below) discloses a radix-2 Signed-Digit adder circuit formed by plural radix-2 Signed-Digit adders, each including an adder, a transfer digit generator and an interim sum generator. According to the present invention there is provided a counter comprising:- an initial value generator operable to calculate an initial value to be preset; a presetting circuit for presetting the initial value; a radix-2 Signed-Digit adder circuit operable to count up from the preset initial value, each up-count involving the addition of +1 at the least significant digital position, the adder circuit being formed by a plurality of digits of radix-2 Signed-Digit adders, each including an adder, a transfer digit generator and an interim sum generator; and a circuit for detecting an overflow at a specified digital position, wherein the initial value generator obtains a value ϑ k at which overflow would occur at the specified digital position, being the kth digital position, if the counter were counted up from zero, in accordance with the following equations: ϑ 2j+1 = (2 2j+1 + 3j + 1)/3 where k=2j+1 ϑ 2j+2 = (2 2j+2 + 3j + 5)/3 where k=2j+2 j being 0 or a positive integer, and further supplies to the preset circuit as initial value the result of subtraction of A from ϑ k in that radix-2 Signed-Digit representation that does not contain any "-1" valued bits, where ϑ k-1 <= A <= ϑ k and where A is the desired count value at which overflow at the selected kth digital position is to occur. An embodiment of the present invention can provide a counter which permits a high-speed counting operation to be implemented within a certain period of time, without dependence on the count value, using radix-2 Signed-Digit redundancy representation and radix-2 Signed-Digit adders for each digit of the counter. The radix-2 Signed-Digit adder is capable of performing a parallel addition without carry-propagation, permitting an addition in a certain period of time, regardless of an addend and an augend. That is, the radix-2 Signed-Digit adder performs an addition without carry-propagation, by the following two steps of operation. (1) In the first step, a transfer digit and an interim sum digit, which are interim values, are generated so that a carry propagation from lower digital position maybe eliminated at an i-th digital position, and these values are set in accordance with the carry classification of the (i - 1)th digital position. (2) In the second step, the transfer digit from the (i - 1)th digital position and the interim digit at the i-th digital position are added together, obtaining a final sum. Since no carry-propagation occurs at this time, a high-speed addition can be achieved regardless of the digit length. The two steps of operation mentioned above can be performed in parallel for each digit, as shown in Fig. 2. The generation of the interim sum digit and the transfer digit requires carry classification (= c) from the lower adjacent digital position, that is, from the (i - 1)th digital position (see T. Nakanishi, H. Yamauchi and H. Yoshimura, "CMOS Radix-2 Signed-Digit Adder by Binary Code Representation", The Transactions of the IECE of Japan, Vol. E 69, No. 4, April 1986, pp. 261-263). Based on the value in the lower adjacent digital position, the carry classification c detects the case +1 transfer digit never occurs (indicated by c = 1) and the case -1 transfer digit never occurs (indicated by c = 0). In the i-th digital position the transfer digit and the interim sum digit are generated based on the carry classification. The carry classification c is generated following the logic shown below in Table 1. The table shows that where at least either one of an addend and an augend is -1, c = 1 because the +1 transfer never occurs owing to the addition of the addend and the augend in the i-th digital position and that, for other combinations of the addend and the augend, c = 0 because the -1 transfer never occurs. The carry classification thus obtained is provided to higher adjacent digital position, i.e. the (i -1)th digital position. Next, Table 2 shows a rule of addition according to which the transfer digit and the interim sum digit are derived from the addend and the augend in the i-th digital position, based on the carry classification c from the (i -1)th digital position. That is, in the cases where the sum of the addend and the augend in the i-th digital position is 0 [i.e. where (addend, augend) = (0, +1) or (-1, 0)], the transfer digit and the interim sum digit are both set to 0s because no carry propagation from the (i - 1)th digital position occurs. In Table 2,  indicates that the carry classification c from the (i - 1)th digital position may be either 1 or 0, and this means that the transfer digit and the interim sum digit do not depend on the carry classification c. In the case where the sum of the addend and the augend is -1 [i.e. where (addend, augend) = (0, -1) or (-1, 0)], the transfer digit and the interim sum digit are generated according to the carry classification c; namely, when c = 0, the transfer digit is set to 0 and the interim sum digit to -1, and when c = 1, the transfer digit is set to -1 and the interim sum digit to +1. In other words, when the sum of the addend and the augend is -1, one of the two kinds of generation logic by which the transfer digit and the interim sum digit are set to 0 and -1 or -1 and +1, respectively, is chosen according to the carry classification c, thereby preventing the occurrence of the -1 carry propagation from the i-th digital position when the transfer digit from the (i - 1)th digital position and the interim sum digit in the i-th digital position are added together. In the cases where the sum of the addend and the augend is +1 [i.e. where (addend, augend) = (0, -1) or (-1, 0)] the transfer digit and the interim sum digit are generated according to the carry classification c from the (i - 1)th digital position; namely, when c = 1, the transfer digit is set to 0 and the interim sum digit to +1, and when c = 0, the transfer digit is set to +1 and the interim sum digit to -1. In other words, when the sum of the addend and the augend is +1, one of the two kinds of generation logic by which the transfer digit and the interim sum digit are set to 0 and +1 or +1 and -1 is chosen according to the carry classification c from the (i - 1)th digital position, thereby preventing the occurrence of the +1 carry propagation from the i-th digital position when the transfer digit from the (i - 1)th digital position and the interim sum digit in the i-th digital position are added together. As for the addition in the least significant digital position, there are no addend and augend in the lower adjacent digital position. In this case, c = 0 is generated as the carry classification to the higher adjacent digital position, through utilization of the classification logic in which the addend and the augend are both 0s, shown in Table 1. Further, the transfer digit to the least significant digital position from the lower adjacent digital position is set to 0 by the application of the logic of transfer digit and interim sum digit in which the addend and the augend are both 0s, as shown in Table 2. The logic of carry classification and the logic of transfer digit and interim sum digit based on the carry classification are such as shown in Tables 1 and 2, respectively. In the columns divided into two in Table 2, the upper columns show the case where the -1 transfer never occurs from the lower adjacent digital position and the lower columns show the case where the +1 transfer never occurs from the lower adjacent digital position. Fig. 3 illustrates a specific operative example of the circuit arrangement of an adder of one digit of a radix-2 Signed-Digit adder, shown in Fig. 2, which performs an addition in accordance with the above-described rules of addition. More specifically, Fig. 3 shows an example of the adder in which each digit formed by any one of three values -1, 0 and +1 of the radix-2 Signed-Digit redundancy representation is represented by a binary code, as depicted below in Table 3, and the rules of addition shown in Tables 1 and 2 are employed. For the radix-2 Signed-Digit redundancy representation and the adder utilizing this, see the afore-mentioned literature "The Transactions of the IECE of Japan, Vol.E 69, No. 4, April 1986. And for Signed-Digit adder, also see US Patent No.3,462,589. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram illustrating a basic arrangement of a counter embodying the present invention, which comprises a radix-2 Signed-Digit adder, an initial value register, an interim value register, and an initial value and interim value selector; Fig. 1B is a block diagram illustrating the arrangement of an embodiment of the present invention which includes an initial value generator in the basic arrangement shown in Fig. 1A; Fig. 2 is a block diagram of the radix-2 Signed-Digit adder, showing the i-th digital position and the (i - 1)th digital position and their connection; Fig. 3 is a schematic diagram illustrating an example of the circuit arrangement of the radix-2 Signed-Digit adder formed in accordance with the rules of addition shown in Tables 1 and 2; and Fig. 4 is a schematic diagram showing a conventional binary counter formed by a synchronous counter using flip-flops. Fig. 1A illustrates in block form a basic arrangement of a counter embodying the present invention and Fig. 1B an arrangement including an initial value generator. In Fig. 1A each digit unit 5 of the counter is formed by a radix-2 Signed-Digit adder 1, an initial value register 2 for presetting an initial value, an interim value register 3 for holding an interim value during the counting operation and an initial value and interim value selector 4 for switching between the initial value and the interim value. Reference numeral 10 indicates a count input, 11 a count output, 12 an addend input, 13 an Augend input, 14 an interim value input, 15 a transfer digit, and 16 a carry classification. Prior to the counting operation an initial value is preset. The initial value is precalculated from a count value so that an overflow can be detected at a specified digital position when the count has advanced by a desired value. After this initialization the count is started to accumulate a constant (= +1) and is completed upon detection of an overflow of the sum V (value) bit in a preknown digital position in Fig. 3. Now, let it be assumed that the initial value is a 0 and an operation of adding thereto a +1 is repeated. When an numerical value is represented by an ordinary 2's complement, the accumulated value varies as shown in Table 4, and an overflow to the higher adjacent digital position, which results from the addition of +1 will occur at the point when the accumulated value has reached to a power of 2 (2 k = 1, 2, 4, ...). In the radix-2 Signed-Digit redundancy representation an overflow occurs in each digital position in response to a specific value, not the power of 2 as in the case of the ordinary 2's complement, and the value that will results in an overflow can be precalculated by forming an iteration equation based on the rule of addition using the radix-2 Signed-Digit redundancy representation. That is, in the case where a circuit based on the rules of addition shown in Tables 1 and 2 is formed on the assumption of repeating an operation of adding an initial value 0 (0s at all of n digital positions in the radix-2 Signed-Digit redundancy representation of n-digit length) with 1 (+1 at the least significant digital position alone and 0s at all the other (n - 1) digital positions in the radix-2 Signed-Digit redundancy representation of n-digit length), the accumulated value will undergo such changes as shown in Table 5. In Table 5, noting the value (= ϑ k ) at which an overflow occurs in a k-th digital position (the value at the digital position k-th from the least significant digital position changes from 0 to +1), the iteration equation is as follows: ϑ k = 2 k-2 + ϑ k-2 + 1 where k ≧ 3. Table 5 shows, by way of example, the case where k is 7. Solving this iteration equation, ϑ 2j+1 = (2 2j+1 + 3j + 1)/3 (k = 2j + 1) ϑ 2j+2 = (2 2j+2 + 3j + 5)/3 (k = 2j + 2) where j is a 0 or positive integer. There exists more than one representation for numerical values, except 0, by the radix-2 Signed-Digit redundancy representation of n-digit length, and for powers of 2 larger than 4 (2 k = 4, 8, 16, ... ) as well, many representation can be considered possible, as shown later in Table 6. It will be appreciated that the results (i.e. 2 k + 1 = 5, 9, 17, ... ) of addition with +1 (+1 at the least significant digital position alone and 0s at all the other (n - 1) digital positions in the radix-2 Signed-Digit redundancy representation of n-digit length), through application of the rules of addition shown in Tables 1 and 2, assume the same radix-2 Signed-Digit redundancy representation when any of these represented values is used as the augend also, as shown later in Table 7. That is, no matter what radix-2 Signed-Digit redundancy representation may be used for a value p ( 2 q-1 ≦ p ≦ 2 q - 1 ) which is preset as the initial value for the counter, the accumulated value obtained by repeatedly adding +1 (+1 only at the least significant digital position and 0s at all the other (n - 1) digital positions in the radix-2 Signed-Digit redundancy representation of n-digit length) through application of the rules of addition shown in Tables 1 and 2 should be represented in the same form as the accumulated value obtained at a point 2 q + 1 in Table 5, that is, the accumulated value obtained by repeatedly adding +1 (+1 only at the least significant digital position and 0s at all the other (n - 1) digital positions in the radix-2 Signed-Digit redundancy representation of n-digit length) to the initial value 0 (0s at all n-digits in the radix-2 Signed -Digit redundancy representation of n-digit length). Accordingly, it will be seen that in the case of further repeating the addition of +1, the accumulated value will undergo exactly the same changes as shown in Table 5. This indicates that the same iteration equation as mentioned previously will hold true for the value (ϑ k ) at which yields an overflow occurs at the k-th digital position (that is, the value at the digital position k-th from the least significant digital position changes from 0 to +1) after the accumulated value has become greater than 2 q + 1. For the reasons mentioned above, in order to implement a count value A (ϑ k-1 ≦ A ≦ ϑ k ), a value obtained by subtracting the count value from the value (= ϑ k ) at which an overflow occurs at the k-th digital position is preset as the initial value. In this instance, each digit of the preset value represented by an ordinary 2's complement is replaced with a digit represented by the radix-2 Signed-Digit redundancy code (namely, the value 0 or 1 of each digit represented by the 2's complement is replaced with 0 or +1, respectively, in the radix-2 Signed redundancy representation). In the above, dots indicate that the value of the digit is equal to those of the higher adjacent and lower adjacent digits. In the above, dots indicates that the value of the digit is equal to those of the higher adjacent and lower adjacent digits. For example, when the desired count value is 41, since ϑ₆ = 25 and ϑ₇ = 46, 5 [ordinary 7-digit 2's complement code (0000101)] is selected as the initial value. Totally seven values those represent a value 5 as a whole are preset in the initial value register 2 in Fig. 1, in the ascending order of +1, 0, +1, 0, 0, 0 and 0, and an overflow which occurs at the 7th digital position is detected. Next, a description will be given of the operation of respective parts of the circuit shown in Fig. 1B. Prior to the counting operation, the values k and ϑ k and the preset value are calculated from the desired count value A by the above-described method. Based on the values thus obtained, the counter shown in Fig. 1 is formed by digit units of (k + 1) digits so that n equals k. An interim value register 3 is synchronized with counting pulses from a count input 10 and is supplied with a new interim value which is the result of addition obtained by a radix-2 Signed-Digit adder 1, from an interim value input 14, and updates this interim value. An addend input 12 of the radix-2 Signed-Digit adder 1 for each digit is fixedly supplied with "+1" at the least significant digital position and "0s" at the other digital positions (corresponding to a value 1 as a whole). Accordingly, by adding the value 1 in the radix-2 Signed-Digit redundancy representation to the value of an augend input 13, which is also the output of an initial value and interim value selector 4, which is called an increment operation is realized, thereby performing a count-up operation of the counter. Further, the most significant digital position of an interim value register 4 is used as a count output 11 and a control signal for the initial value and interim value selector 4. When the most significant digital position is "+1", the initial value and interim value selector 4 selects the output value of the initial value register 2, and, at the same time, generates a count end pulse to the count output 11. When the most significant digital position is "0", the initial value and interim value selector 4 selects the output value of the interim value register 3 and sends it to the addend input 12 of the radix-2 Signed-Digit adder 1 without generating count end pulse to the count output 11. Prior to the counting operation (time t ≦ 0) the preset value (ϑ k - A) calculated from the desired count value A by the afore-said method is generated by an initial value generator 17 and the stored into the initial value register 2. Moreover, "+1" in the radix-2 Signed-Digit redundancy representation is stored into the interim value register 2, for each digit, prior to the counting operation. Upon application of the count pulse arrived at the count input, the counter starts counting (time t ≧ 0). At the start of the counting operation (t = 0), the initial value and interim value selector 4 selects the output value of the initial value register 2, which is sent to the augend input 13 of the radix-2 Signed-Digit adder 1. To the addend input 12 are sent "+1" at the least significant digital position and "0s" at the other digital positions, and the result of addition is provided to an interim value input 14 of the interim value register 3. After arrival of one pulse (t = 1) the interim value register 3 updates its value to a new interim value (i.e. the preset initial value plus one). At this time, since a "0" is stored into the most significant digital position, the initial value and interim value selector 4 selects the output value of the interim value register 3 and provides it to the augend input 13 of the radix-2 Signed Digit adder 1. Thereafter ( 2 ≦ t ≦ A ), the interim value register 3 will update its contents from a value provided at the time of the arrival of the immediately preceding pulse (i.e. a value provided at the time t = j - 1 ) to a new interim value which is the result of addition obtained by the radix-2 Signed-Digit adder 1. Upon each updating a "0" is stored into the most significant digital position. At the time of A-th arrival of the count input pulse (i.e. at the time t = A ), since ϑ k has been stored into the interim value register 3, "+1" is held at the most significant digital position in place of "0". Consequently, the count end pulse is sent to the count output 11 for the first time after starting the counting operation. As described above, the initial value to be preset can easily be precalculated by subtracting the count value from the value at which an overflow occurs. In the case of employing the counter of the present invention, it is necessary only to provide counters of a required number of digits in accordance with the count value, preset the initial value which is determined by the count value, and detect an overflow at a specified digital position. Unlike conventional counters, the counter of the present invention does not include a circuit of a large fan-in even if the count value is large. Also in the case where the counter is formed by a CMOS, which has generally a small fan-in limit but is widely used in a large scale integrated circuit because of its small power dissipation logic circuit, the counter can operate at high speed with a certain delay time of operation, regardless of an increase in the desired count value. For a radix-2 Signed-Digit adder, it is possible to calculate a value at which an overflow occurs at each digital position and to precalculate the initial value corresponding to the count value, through use of an iteration equation based on the rules of addition by using a Signed-Digit arithmetic technique. Accordingly, a Signed-Digit counter of high-speed operation can be realized by the radix-2 Signed-Digit adder, the initial value register and the interim value register and the initial value and interim value selector. As mentioned above, since the counter of the present invention does not include a circuit of a large fan-in limit even if the desired count value increases, the counter, even if formed by the CMOS logic circuit or the like, can operate at high speed, with a certain delay time of operation, regardless of an increase in the desired count value. As described above, according to the present invention, a counter which is capable of performing a high-speed operation with a certain delay time of operation, regardless of an increase in the count value, can be provided through utilization of the radix-2 Signed-Digit redundancy representation.

Claims: A counter comprising: an initial value generator operable to calculate an initial value to be preset; a presetting circuit for presetting the initial value; a radix-2 Signed-Digit adder circuit operable to count up from the preset initial value, each up-count involving the addition of +1 at the least significant digital position, the adder circuit being formed by a plurality of digits of radix-2 Signed-Digit adders, each including an adder, a transfer digit generator and an interim sum generator; and a circuit for detecting an overflow at a specified digital position, wherein the initial value generator obtains a value ϑ k at which overflow would occur at the specified digital position, being the kth digital position, if the counter were counted up from zero, in accordance with the following equations: ϑ 2j+1 = (2 2j+1 + 3j + 1)/3 where k=2j+1 ϑ 2j+2 = (2 2j+2 + 3j + 5)/3 where k=2j+2 j being 0 or a positive integer, and further supplies to the preset circuit as initial value the result of subtraction of A from ϑ k in that radix-2 Signed-Digit representation that does not contain any "-1" valued bits, where ϑ k-1 <= A <= ϑ k and where A is the desired count value at which overflow at the selected kth digital position is to occur. A counter as claimed in claim 1, wherein, at each digital position, the radix-2 Signed-Digit adder concerned comprises first means whereby a transfer digit and an interim sum digit, which are both interim values, are generated on the basis of a carry classification from the lower adjacent digital position, and second means whereby the transfer digit from the lower adjacent digital position and the interim sum digit generated in the adder are added together to generate a sum. A counter as claimed in claim 2, wherein, in each digital position, the carry classification (c, c ) is generated from input values of addend and augend to that digital position, in accordance with the classification logic of the following table:- A counter as claimed in claim 2 or 3, wherein, at each digital position, the interim sum digit and transfer digit of the radix-2 Signed-Digit adder concerned are generated from input values of addend and augend at that digital position and the carry classification from the lower adjacent digital position, in accordance with the transfer digit and interim sum digit logic of the following table:- Addend Augend Carry classification from lower adjacent digital position Transfer digit Interim sum digit +1 -1  +1 0 +1 0 c +1 -1 0 +1 c 0 +1 0 0  0 0 -1 +1 +1 -1 0 -1 c 0 -1 -1 0 c -1 +1 -1 -1  -1 0 c: +1 transfer from the lower adjacent digital position never occurs c : -1 transfer from the lower adjacent digital position never occurs : carry classification from the lower adjacent digital position may be either c or c

Inventors: NAKANISHI TADASHI, YAMAUCHI HIRONORI, NAKANISHI, TADASHI, YAMAUCHI, HIRONORI
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1988
Main classification: H03K23
IPC codes: G06F7, H03K23