A semiconductor device having metal wiring layers and method of manufacturing such a device

Abstract: A semiconductor device including a semiconductor substrate (1); a metal wiring layer (31) formed on the semiconductor substrate; a first insulation layer (411) formed on the metal wiring layer (31), the first insulation layer (411) being formed by a tensile stress insulation layer having a contracting characteristic relative to the substrate; and a second insulation layer (412) formed on the first insulation layer (411), the second insulation layer (412) being formed by a compressive stress insulation layer having an expanding characteristic relative to the substrate. The tensile stress insulation layer (411) is produced by thermal chemical vapor deposition or plasma assisted chemical vapor deposition which is performed in a discharge frequency range higher than 2 megahertz; and the compressive stress insulation layer (412) is produced by plasma assisted chemical vapor deposition which is performed in a discharge frequency range lower than 2 megahertz.

Description: The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, it relates to a semiconductor device having metal wiring layers and insulation layers formed on the metal wiring layers, and to a method of manufacturing the same. Generally, in producing a semiconductor device of the above type, the insulation layers formed on the metal wiring layers (e.g. aluminium wiring layers) are produced by chemical vapour deposition using an insulation material such as phosphor silicated glass (PSG). In this method, however, during the formation of the above insulation layers, problems have arisen such as disconnection of the metal wiring layers due to stress migration due to the effect of stress generated in the insulation layers, and cracks in the insulation layers. Semiconductor devices having lower side metal wiring layers with wiring lines of small width for signal interconnections and upper side metal wiring layers with wiring lines of larger width for power supply connections are known from IEEE Journal of Solid-State Circuits, vol. SC-21, no.1, 1986, New York, US, pages 150-156. From JP-A-62 057 255 it is known to compensate stresses in semiconductor devices by combining a tensile stress insulation layer with a compressive stress insulation layer. The present invention addresses the above-mentioned problems, and the present invention is concerned with not only the disconnection of the metal wiring layers due to stress migration but also the generation of cracks in the insulation layers. According to a first aspect of the present invention, there is provided a semiconductor device as defined in claim 1. According to a second aspect of the present invention, there is provided a method of manufacturing such a semiconductor device, as defined in claim 4. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a drawing explaining the characteristics of a tensile stress insulation layer; Fig. 2 is a drawing explaining the characteristics of a compressive stress insulation layer; Fig. 3 is a drawing showing a tensile stress insulation layer formed on a metal wiring layer as a first insulation layer; Fig. 4 is a drawing showing a compressive stress insulation layer formed on the first insulation layer as a second insulation layer; Figs. 5(a) to 5(e) are drawings showing a manufacturing process which is not in accordance with the present invention but useful for understanding the background thereof; Fig. 6 is a diagram showing how the stress generated in an insulation layer produced by plasma CVD varies with the discharge frequency used in a plasma CVD system; Fig. 7 is a diagram showing experimental data regarding the generation of cracks in insulation layers in various cases; and Figs. 8(a) to 8(h') are drawings showing a process for manufacturing a semiconductor device according to an embodiment of the present invention. A tensile stress insulation layer has a contracting characteristic relative to the substrate. Thus, when a tensile stress insulation layer T is formed on a semiconductor substrate $ as shown in Fig. 1, the tensile stress insulation layer T causes the substrate S to bend in a direction such that the insulation layer T contracts relative to the substrate S (i.e. a direction such that the insulation layer T compresses the metal wiring layer M formed on the substrate S). On the other hand, a compressive stress insulation layer has an expanding characteristic relative to the substrate. Thus, when a compressive stress insulation layer C is formed on a semiconductor substrate S as shown in Fig. 2, the compressive stress insulation layer C causes the substrate S to bend in a direction such that the insulation layer C expands relative to the substrate S (i.e. a direction such that the metal wiring layer M formed on the substrate S is expanded together with the insulation layer C when the metal wiring layer is heated by a current flowing therethrough). In embodiments of the present invention, by forming tensile stress insulation layers on respective lower side metal wiring layers having a small wiring width (e.g. on the first and the second metal wiring layers), a disconnection of the metal wiring layers having a small wiring width due to stress migration is prevented. Also, by forming compressive stress insulation layers on respective upper side metal wiring layers having a large wiring width (e.g. on the third and the fourth metal wiring layers), generation of cracks in the insulation layers due to the expansion of the metal wiring layers having a large wiring width is prevented. In this connection, with regard to the metal wiring layers having a large wiring width, a disconnection thereof due to stress migration need not be considered. As described in detail below, the tensile stress insulation layer may be produced by thermal chemical vapour deposition (thermal CVD) or plasma-assisted chemical vapour deposition (plasma CVD) performed in a discharge frequency range higher than 2 MHz. On the other hand, the compressive stress insulation layer may be produced by plasma-assisted chemical vapour deposition (plasma CVD) performed in the discharge frequency range lower than 2 MHz. Also, when the above tensile stress insulation layer or compressive stress insulation layer is formed by a particular plasma-assisted chemical vapour deposition such that the above plasma is produced by electron cyclotron resonance (ECR plasma CVD), the surface of the corresponding insulation layer can be made flat, and thus ensure a high reliability of the metal wiring layers formed on the flattened surfaces of the insulation layers. In this connection, U.S. Patent No. 4,446,194 discloses a method of forming a dielectric layer having a compressive stress (corresponding to compressive stress insulation layer) on the metal layer and forming a dielectric layer substantially free of compressive stress (corresponding to the tensile stress insulation layer) on the compressive stress insulation layer, to prevent a formation of voids in the metal layers. But, as shown in the experimental data described in detail below, a semiconductor device embodying the present invention may effectively prevent both a disconnection of the metal layers due to stress migration and a generation of cracks in the insulation layers, compared with the device disclosed in the above U.S. patent. Namely, in embodiments of the present invention, the above-mentioned particular advantages can be obtained, which cannot be expected from the above U.S. patent. Figs. 5(a) to 5(e) show a process for manufacturing a semiconductor device which is useful for understanding the background of the present invention. First, as shown in Fig. 5(a), a first metal wiring layer (e.g. aluminium wiring layer) 31 is formed on a semiconductor substrate 1 (e.g. a silicon substrate) via a silicon insulation film 2 (e.g. a silicon dioxide (SiO 2 ) film). Next, as shown in Fig. 5(b), a tensile stress insulation layer 411 is formed as a first insulation layer on the first metal wiring layer 31. The tensile stress insulation layer 411 functions to compress the metal wiring layer 31, due to the contracting characteristic thereof relative to the substrate, and thus prevents stress migration which will cause a disconnection of the metal wiring layer 31. Then, as shown in Fig. 5(c), a compressive stress insulation layer 412 is formed as a second insulation layer on the tensile stress insulation layer 411. In this connection, the compressive stress insulation layer 412 expands together with the metal wiring layer 31 when the metal wiring layer is heated by a current flowing therethrough, due to the expanding characteristic thereof relative to the substrate. Thereby, stress applied by the metal wiring layer to the insulation layer at that time is reduced and, as a result, generation of cracks in the insulation layer is prevented. In this connection, the tensile stress insulation layer 411 can be formed by thermal chemical vapour deposition (thermal CVD) or plasma-assisted chemical vapour deposition (plasma CVD). When the thermal CVD method is used, an insulation material such as phosphor silicated glass (PSG) or silicon dioxide (SiO 2 ) is deposited on the metal wiring layer under the condition of a reduced atmospheric pressure or standard atmospheric pressure, and a processing temperature range higher than 200°C, preferably from 300 to 450°C. When the plasma CVD method is used, an insulation material (reaction gas) such as the above PSG, SiO 2 , SiON, Si 3 N 4 or BPSG (boron-phosphor silicated glass), is deposited on the metal wiring layer by supplying high-frequency power having a discharge frequency higher than 2 MHz (e.g. 13.56 MHz) between flat electrodes arranged, for example, in parallel, one of which electrodes is connected to the substrate, under a processing temperature range of from 200 to 450°C. The plasma CVD method is used for forming the compressive stress insulation layer 412, and the insulation material (the reaction gas) such as the above PSG, SiO 2 , SiON, Si 3 N 4 or BPSG is deposited on the first insulation layer by supplying high-frequency power having a discharge frequency lower than 2 MHz (e.g. 200 KHz) between the above electrodes, under a processing temperature range of from 200 to 450°C. Note, the above plasma CVD is of a type other than a plasma CVD wherein the plasma is produced by electron cyclotron resonance (ECR plasma CVD) as described below. Fig. 6 is a diagram showing how the value of the stress generated in the insulation layer produced by the plasma CVD is changed in accordance with a change in the discharge frequency of the high-frequency power supplied from a high-frequency generator connected between the above electrodes used in the plasma CVD system. In Fig. 6, the abscissa corresponds to the discharge frequency, and the ordinate corresponds to the amount of stress (using 10 n dyn/cm 2 [1 dyn ≙ 10 -5 N], where n = 8 for PSG, and n = 9 for Si 3 N 4 , as a unit) generated in the insulation layer produced by the plasma CVD. This plasma CVD was performed by using the insulation material (reaction gas) of the above PSG and Si 3 N 4 . The value of the tensile stress generated in the insulation layer is represented as a positive value, and the value of the compressive stress generated in the insulation layer is represented as a negative value. The value of the stress becomes zero at the point where the discharge frequency is 2 MHz, and the value of above tensile stress increases in accordance with the increase of the discharge frequency in the frequency range higher than 2 MHz. On the other hand, the value of the above compressive stress increases in accordance with a decrease of the discharge frequency in the frequency range lower than 2 MHz. Namely, a tensile stress insulation layer is formed when the plasma CVD is performed at a discharge frequency higher than 2 MHz, and a compressive stress insulation layer is formed at a discharge frequency lower than 2 MHz. These conditions remain unchanged even when the above ECR plasma CVD is adopted, instead of another type of plasma CVD, for forming the insulation layer. Then, as shown in Fig. 5(d), a second metal wiring layer 32 is formed on the second insulation layer 412. When the above-mentioned steps are repeated, a tensile stress insulation layer 421 and a compressive stress insulation layer 422 are successively formed on the second metal wiring layer 32, and a third metal wiring layer 33 is formed on the above insulation layer 422 corresponding to the second insulation layer. Then, in the above process, the compressive stress insulation layer 432 is formed as a cover on the third metal wiring layer 33, as shown in Fig. 5(e) and, subsequently, an anneal processing for the semiconductor device is carried out for about half-an-hour under a temperature of, for example 450°C. Figs. 8(a) to 8(h') show a process for manufacturing a semiconductor device according to an embodiment of the present invention. In this embodiment, a plurality of metal wiring layers are provided, a tensile stress insulation layer is formed on each of lower side metal wiring layers having a small wiring width, and a compressive stress insulation layer is formed on each of upper side metal wiring layers having a large wiring width. The tensile stress insulation interlayers 41 and 42 are formed on the first and second metal wiring layers 31 and 32 having small wiring widths ℓ 1 , ℓ 2 respectively, to prevent disconnection of the metal wiring layers having the small wiring widths due to stress migration. In this connection, the tensile stress insulation layers may be formed by the same means used to form the tensile stress insulation layers in the process shown in Fig. 5. Also, the compressive stress insulation layers (interlayers and a cover) 43, 44 and 45 are formed on the third, fourth and fifth metal wiring layers 33, 34 and 35 having large wiring widths ℓ 3 , ℓ 4 and ℓ 5 , respectively. In this connection, it is not necessary to consider disconnection of the metal wiring layers having the large wiring widths ℓ 3 to ℓ 5 , due to stress migration. Accordingly, as mentioned above, the compressive stress insulation layers are formed on the metal wiring layers having the large wiring widths, to prevent the generation of cracks in the insulation layers, due to expansion of the metal wiring layers having the large wiring widths. The compressive stress insulation layers also may be formed by the same means used to form the compressive stress insulation layers in the above-described process of Fig. 5. In the above semiconductor device having a plurality of metal wiring layers, one or more metal wiring layers having small wiring widths (e.g. signal lines) are formed with a high wiring density as the lower side metal wiring layers (in the above case, as the first and second metal wiring layers), and the remaining metal wiring layers having large wiring widths (e.g. power supply lines) are formed with a low wiring density as the upper side metal wiring layers (in the above case, as the third to fifth metal wiring layers). In Figs. 8(a) to 8(h'), the steps shown in Figs. 8(a) and 8(b) correspond to those of Figs. 5(a) and 5(b), respectively. Next, as shown in Fig. 8(c), the second metal wiring layer 32 having the wiring width ℓ 2 is formed on the tensile stress insulation interlayer 41, and as shown in Fig. 8(d), the tensile stress insulation interlayer 42 is again formed on the metal wiring layer 32. Next, as shown in Fig. 8(e), the third metal wiring layer 33 having the wiring width ℓ 3 , which is larger than the above ℓ 1 and ℓ 2 , is formed on the insulation interlayer 42, and as shown in Fig. 8(f), the compressive stress insulation interlayer 43 is then formed on the metal wiring layer 33. Next, as shown in Fig. 8(g), the fourth metal wiring layer 34 having the wiring width ℓ 4 , which is also larger then ℓ 1 and ℓ 2 , is formed on the insulation interlayer 43. The above steps are repeated a predetermined number of times and, finally, as shown in Fig. 8(h), the compressive stress insulation layer 45 is formed as the cover on the fifth metal wiring layer 35 having, for example, the wiring width ℓ 5 which is also larger than ℓ 1 and ℓ 2 . Fig. 8(h') shows another example of the construction of a semiconductor device according to the present invention. This semiconductor device comprises four metal wiring layers including two lower side metal wiring layers (i.e. the first and second metal wiring layers 31 and 32 having small wiring widths ℓ 1 ' and ℓ 2 ', respectively) and two upper side metal wiring layers (i.e. the third and fourth metal wiring layers 33 and 34 having large wiring widths ℓ 3 ' and ℓ 4 ', respectively). The tensile stress insulation interlayers 41 and 42 are formed on the above lower side metal wiring layers 31 and 32, respectively, and the compressive stress insulation layers (an interlayer and a cover) 43 and 44 are formed on the above upper side metal wiring layers 33 and 34, respectively. The tensile stress insulation layers and the compressive stress insulation layers may be formed by the same means used to form the tensile stress insulation layers and the compressive stress insulation layers in the process of Fig. 5. Fig. 7 shows experimental data regarding the generation of cracks in the insulation layers in various cases. In Fig. 7, test data I corresponds to a case wherein insulation interlayers formed on the first, second and third metal wiring layers are all formed by tensile stress insulation layers T, and only the cover formed on the fourth metal wiring layer is formed by a compressive stress insulation layer C. Also, test data III corresponds to a case wherein insulation interlayers formed on the first and second metal wiring layers are formed only by tensile stress insulation layers T, and the insulation interlayer formed on the third metal wiring layer comprises a compressive stress insulation layer C as a first insulation layer 3-1 of the corresponding insulation interlayer and a tensile stress insulation layer T formed on the first insulation layer 3-1 as a second insulation layer 3-2 of the corresponding insulation interlayer, as shown in U.S. Patent 4,446,194, and the cover formed on the fourth metal wiring layer is formed by the compressive stress insulation layer C. These test data I and III show that, according to the above constructions, it is impossible to prevent the generation of cracks in the insulation layers, as shown by the marks "X". On the other hand, test data II shows an example of the present invention. That is, it shows a case wherein the insulation interlayers formed on the first and second metal wiring layers (i.e. the metal wiring layers having small wiring widths) are formed by the tensile stress insulation layers T, and the insulation interlayer formed on the third metal wiring layer and the cover formed on the fourth metal wiring layer (i.e. the insulation interlayer and the cover formed on the metal wiring layers having large wiring widths) are formed by the compressive stress insulation layers C. These test data II show that, according to the present invention, the generation of cracks in the insulation layers can be effectively prevented, as shown by the marks "o".

Claims: A semiconductor device comprising:- a semiconductor substrate (1); a plurality of metal wiring layers (31, 32, 33, 34) formed over said semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having wiring lines of a first width and one or more upper side metal wiring layers (33, 34) formed above said lower side metal wiring layers and having wiring lines of a second width larger than said first width; a respective first insulation layer (41, 42) formed on each of the lower side metal wiring layers (31, 32), each first insulation layer being formed by a tensile stress insulation layer having a contracting characteristic relative to said substrate; and a respective second insulation layer (43, 44) formed on each of the upper side metal wiring layers (33, 34), each second insulation layer being formed by a compressive stress insulation layer having an expanding characteristic relative to said substrate. A semiconductor device according to claim 1, wherein said wiring lines of said lower side metal wiring layers (31, 32) are signal lines and said wiring lines of said upper side metal wiring layers (33, 34) are power supply lines. A semiconductor device according to claim 1 or 2, wherein there are four said metal wiring layers (31, 32, 33, 34), of which first and second metal wiring layers (31, 32) are the lower side metal wiring layers, and third and fourth metal wiring layers (33, 34) are the upper side metal wiring layers. A method of manufacturing a semiconductor device, comprising steps of:- forming a plurality of metal wiring layers (31, 32, 33, 34) over a semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having wiring lines of a first width and one or more upper side metal wiring layers (33, 34) above said lower side metal wiring layers and having wiring lines of a second width larger than said first width; forming a respective first insulation layer (41, 42) on each of the lower side metal wiring layers (31, 32) by thermal chemical vapor deposition or plasma assisted chemical vapor deposition which is performed at a discharge frequency higher than 2 MHz so that each respective first insulation layer is a tensile stress insulation layer having a contracting characteristic relative to the substrate; and forming respective second insulation layers (43, 44) on each of the upper side metal wiring layers (33, 34) by plasma-assisted chemical vapor deposition which is performed at a discharge frequency lower than 2 MHz so that each respective second insulation layer is a compressive stress insulation layer having an expanding characteristic relative to the substrate. A method of manufacturing a semiconductor device according to claim 4, wherein there are four said metal wiring layers (31, 32, 33, 34), of which first and second metal wiring layers (31, 32) are the lower side metal wiring layers, and third and fourth metal wiring layers (33, 34) are the upper side metal wiring layers.

Inventors: ITOH JUNICHI, KURITA KAZUYUKI, ITOH, JUNICHI, KURITA, KAZUYUKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H01L23
IPC codes: H01L23, H01L21