MULTIPHASE MULTIPLIER

Abstract: A multiphase multiplier circuit employs analog switches, each of which is duty controlled for multiplying input vol­ tage signal with a multiplier determined depending on the duty cycle of ON/OFF period. The multiphase multiplier circuit further includes means for multiplying a reference voltage signal by a desired factor for deriving the difference between the product and the factor for controlling duty cycles of the analog switches on the basis of the difference.

Description: The present invention relates to a multiphase multiplier circuit for multiplying a plurality of analog voltage signals with a common multiplier value. Conventionally, LOG amplifiers, multiplier IC circuits, are known as analog multiplier circuits. Such conventional multiplier circuits amplify analog voltage signals representative of values to be multiplied at mu-factors corresponding to multipliers. These multiplier circuits generally comprise operational amplifiers and resistors to provide desired electrical characteristics, such as accuracy in arthimetic operation and response characteristics. On the other hand, such conventional multiplier circuits have complicated circuit constructions which cause them to be relatively high in cost. Therefore, in the case of an apparatus using a plurality of multiplier circuits, it becomes necessary to provide the necessary number of multiplier circuits leading to a substantial cost in constructing the circuit. Such a problem may be encountered even in a multiphase multiplier circuit which amplifies a plurality of analog voltage signals with a common mu-factor, since a corresponding number of multiplier circuits are required. US 3,588,713 discloses a multiplier circuit for multiplying two input signals. The first input, E₁ is integrated and the output of the integrator is fed into a comparator which activates a switch. When the switch is closed, E₁ is added to a reference signal and the summation signal is applied to the integrator causing its output to be driven in the reverse direction producing an oscillating loop which provides a sawtooth waveform at the integrator output which has a duty cycle proportional to E₁ . This is fed to the comparator which produces a pulse which activates a switch to gate the second input signal, E₂. The resulting output is a pulse of amplitude proportional to E₂ and duty cycle proportional to E₁. This is then filtered to provide an average signal proportional to the product of the two inputs E₁ and E₂. Therefore, it is an object of the present invention to provide a multiphase multiplier circuit which has simplified construction. Another object of the invention is to provide a multiphase multiplier circuit of a simplified construction which can maintain in accuracy, performance and response characteristics equivalent to the level of the conventional circuit. In order to accomplish aforementioned and other objects and advantages, a multiphase multiplier circuit, according to the invention, employs analog switches, for multiplying an input voltage signal with a multiplier signal by controlling the duty cycle of the switches. The multiphase multiplier circuit further includes a reference multiplier, including a switch, for multiplying a reference voltage signal by a multiplier signal and obtaining a product, summing the product with the multiplier signal to obtain an error signal, pulse width modulating the error signal, and feeding the pulse width modulated error signal back into the reference multiplier for the purpose of turning the switch on or off. According to one aspect of the invention, a multiplier circuit as defined in claim 1 comprises; a plurality of multipliers, each responsive to a corresponding one of a plurality of input signals including a reference signal, and each responsive to a duty cycle control signal for providing a plurality of corresponding multiplied output signals including a multiplied reference signal whereby each multiplier includes an analog switch connected to an input signal source, said analog switch being switched ON and OFF according to said duty cycle control signal for multiplying said input signal received from said input signal source by a factor corresponding to said duty cycle control signal; characterized by a duty cycle adjusting means, responsive to said multiplied reference signal, for comparing the magnitude of said multiplied reference signal to the magnitude of a multiplier signal for providing said duty cycle control signal in proportion to the difference therebetween. Each of the multipliers may include an operational amplifier connected to the analog switch for receiving the input signal through the analog switch, a feedback resistor and a filtering amplifier. In the preferred construction, each of the multipliers further includes an input resistor having a resistance cooperative with the feedback resistor for determining the mu-factor for adjusting the multiplier. The duty cycle adjusting means may include means for deriving the difference between the received output of the reference multiplier and a multiplier factor indicative signal to produce a difference indicative signal and a pulse generating means for generating a duty cycle control signal having a pulse width corresponding to the signal value of the difference indicative signal. Preferably, the pulse generating means comprises a frequency signal source for generating a signal having a constant frequency and constant amplitude and a comparator which compares the frequency signal with the difference indicative signal for producing the pulse signal defining the duty cycle. According to another aspect of the invention, a method is disclosed according to claim 7. The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiment but are for explanation and understanding only. In the drawings: Fig. 1 is a circuit diagram of the preferred embodiment of a multiphase multiplier circuit according to the present invention; and Figs. 2(a) through 2(d) are charts showing waveforms of signals at different components of the preferred embodiment of the multiphase multiplier circuit of Fig. 1. Referring now to the drawings, Fig. 1 shows the preferred embodiment of a multiphase multiplier circuit according to the invention, which has n-phase multipliers 1₁ to 1 n . The multipliers 1₁ to 1 n have input terminals IN₁ to IN n which are respectively connected to field -effect transistors (FETs) T₁ to T n via input resistors R₁₁ to R 1n . The FETs T₁ to T n serve as analog switches whose ON/OFF periods are controlled. The FETs T₁ to T n provide the input signals to operational amplifiers A₁ to A n , outputs of which are connected to output terminals OUT₁ to OUT n . The outputs of the operational amplifiers A₁ to A n are also connected to inputs thereof via feedback resistors R₂₁ to R 2n and via filtering capacitors C₁₁ to C 1n . As seen from Fig. 1, the filtering capacitors C₁₁ to C 1n are in parallel with their respective feedback resistors R₂₁ to R 2n . The multiphase multiplier circuit also includes a reference multiplier 2. Similar to the multipliers 1₁ to 1 n , the reference multiplier 2 has an input terminal IN s which is connected to an operational amplifier A s via a series circuit comprising an input resistor R₃ and an FET T s . The operational amplifier A s of the reference multiplier 2 has parallel feedback circuits, respectively including feedback resistor R₄ and filtering capacitor C₂. The output of the operational amplifier As is connected to an output terminal OUT s which in turn is connected to a control amplifier 4 which will be discussed herebelow, to feed the output of the operational amplifier A s as a feedback input for the control amplifier 4. The control amplifier 4 includes a variable resistor VR connected to the output terminal OUT s . The variable resistor VR is, in turn, connected to an operational amplifier A c . The operational amplifier A c is also connected to an absolute value circuit 3 which receives a multiplier signal input K representative of the factor by which the input voltages IN₁ to IN n will be multiplied. The absolute value circuit 3 outputs a positive polarity signal V in to the input of the operational amplifier A c via an input resistor R₅. The operational amplifier A c has a primary delay capacitor C₃ and a positive polarity cut diode D. The operational amplifier A c is connected to the inverting input terminal of a comparator 6. The comparator 6 has a non-inverting terminal connected to a triangular wave generator circuit 5 which generates a negative polarity triangular wave V osc having constant frequency and constant amplitude. The comparator 6 compares the output of the control amplifier V₄ with the output of the triangular wave generator circuit 5 to produce a pulse signal Pc having a pulse width corresponding to the level of the output v₄ of the control amplifier 4 thus, the pulse signal Pc is a pulse width modulated Vc signal. The pulse signal Pc is applied to the source of respective FET T s and T₁ to T n for turning them ON for a period corresponding to the pulse width of the pulse signal Pc. The operational amplifier A c of the control amplifier 4 operates to determine the level of the output V₄ so that at a given balance between the output V in of the absolute value circuit 3 and feedback input OUT s of the reference multiplier can be established. With the circuit construction set forth above, the input voltages at the input terminals IN₁ to IN n of the multipliers 1₁ to 1 n serve as signals representing values to be multiplied. On the other hand, the input K of the absolute value circuit 3 serves as a common multiplier. The absolute value circuit 3 outputs the absolute value signal V in corresponding to the input K. The operational amplifier A c receives the output OUT s of the reference multiplier 2 generated in response to reference input IN s and the absolute value signal V in of the absolute value circuit 3. The operational amplifier A c then compares the inputs and outputs a negative polarity signal V₄ representative of the difference between the output OUT S of the reference multiplier 2 and the absolute signal V in of the absolute value circuit 3. The negative polarity signal V₄ is fed to the comparator 6. The comparator 6 compares the negative polarity signal value with the triangular wave signal of the negative polarity input from the triangular signal generator circuit 5 to formulate a pulse signal Pc having a pulse width corresponding to the level of the negative polarity signal v₄. By this pulse signal Pc, the duty cycle of the ON/OFF period of the FETs T s and T₁ to T n is controlled. Figs. 2(a) to 2(d) show waveforms of the signals in the preferred embodiment of the multiphase multiplier circuit of Fig. 1. As seen from Fig. 2(a), the reference input IN s for the reference multiplier 2 is held at constant voltage. On the other hand, the input V in of the control amplifier 4 increases according to increasing of absolute value of the input K multiplier. The output OUT s of the reference multiplier 2 is initially held at zero. Therefore, the difference between output OUTs of the reference multiplier 2 and the output V in of the absolute value circuit 3 increases. Therefore, the level of the negative polarity signal V₄ of the operational amplifier A c is lowered from initial zero level. Since the ON/OFF period of the duty cycle of the FET T s is determined by the pulse width of the pulse signal Pc of the comparator 6 which increases according to lowering of the level of the negative polarity signal, the output OUT s increases (Fig. 2b). When the input K reaches the desired value and is held constant, the output OUT s of the reference multiplier 2 represents the product obtained by multiplying the reference input IN s by multiplier K. At this time, gain G of the system can be illustrated by: G = V in /IN s = (1/IN s ) x K The forgoing equation can be modified when the resistance R VR of the variable resistor VR is varied, as follows: When the multiplier gain, e.g. R₂₁/R₁₁, is same as the gain (R₄/R₃) in the reference multiplier 2, the relationship between inputs 1₁ to 1 n and outputs OUT₁ to OUT n becomes the same as that in the reference multiplier 2. For example, the output OUT₁ of the multiplier 1₁ can be illustrated by: OUT₁ = IN₁ x {(1/IN₁) x (R VR /R₅)} x K As can be appreciated from the above, the FETS T₁ to T n and T s are duty cycle controlled by means of the ON/OFF period generated by the pulse signal Pc which performs chopping for obtaining multiplied outputs, from the inputs IN₁ to IN n and IN s . The duty cycle of these FETs T₁ to T n and T s is adjusted based on the difference between the output OUT s of the reference multiplier 2, as applied to the multiplier in feedback manner and K. By this, the inputs IN₁ to IN n can be accurately amplified by a mu-factor corresponding to the input K multiplier. Therefore, the shown embodiment of the multiphase multiplier circuit can operate accurately. In addition, since multipliers 1₁ to 1 n and 2 perform the multiplying operation by chopper operation of the analog switches constituted by FETs T₁ to T n and T s , leak current and offset level in each circuit can be kept low so that accurate multiplying operation becomes possible for substantially low level inputs. Furthermore, since the FETs T₁ to T n and T s of the analog switches are capable of high frequency switching operation, improved response characteristics in multiplying operation can be provided. Furthermore, the multiplying gain in the preferred embodiment of the multiphase multiplier can be adjusted simply by adjusting the resistance of the variable resistor. If necessary, by adjusting the gain each multiplier which can be done by adjusting resistances of the input resistor and feedback resistor, multiplier can be adjusted independently of the other multipliers. With the construction and operation set forth above, the present invention fulfills all of the objects and advantages sought therefor. While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways. For example, though the shown embodiment of the multiphase multiplier circuit employs the feedback circuit constituted by the control amplifier 4, the triangular wave generator circuit 5 and the comparator 6, for controlling the duty cycle for chopper operation, any circuit constructions of feedback circuit which can accurately adjust duty cycle can be employed. Furthermore, the circuit construction of the multiplier can be modified in any way as long as the capability of chopper operation is maintained.

Claims: A multiplier circuit, comprising; a plurality of multipliers (1,-1n), each responsive to a corresponding one of a plurality of input signals (1N₁-1N n , 1N s ) including a reference signal (IN s ), and each responsive to a duty cycle control signal (P c ) for providing a plurality of corresponding multiplied output signals (OUT₁-OUT n ,OUT s ), including a multiplied reference signal (OUT s ) whereby each multiplier includes an analog switch (T₁-T n ,T s ) connected to an input signal source, said analog switch being switched ON and OFF according to said duty cycle control signal (P c ) for multiplying said input signal received from said input signal source by a factor (K) corresponding to said duty cycle control signal; characterized by a duty cycle adjusting means (4,6), responsive to said multiplied reference signal (OUT s ), for comparing the magnitude of said multiplied reference signal to the magnitude of a multiplier signal (V in ) for providing said duty cycle control signal (P c ) in proportion to the difference therebetween. The multiplier circuit of claim 1, wherein each of said multipliers (1₁-1 n ) includes an integrator (C₁₁R₂₁-C 1n R 2n ), responsive to one of said switched input signals, for providing a corresponding one of said multiplied output signals. The multiplier circuit of claim 1 or 2, wherein said duty cycle adjusting means includes: a summing means (4), responsive to the magnitudes of said multiplied reference signal and said multiplier signal, for providing a difference signal proportional to the difference therebetween; and pulse generating means (5,6) responsive to said difference signal for providing said duty cycle control signal (P c ). The multiplier circuit of any preceding claim wherein said duty cycle adjusting means includes a summing means (4), responsive to the magnitudes of said multiplied reference signal and said multiplier signal, for providing a difference signal proportional to the difference therebetween; and pulse generating means (5,6), responsive to said difference signal, for providing said duty cycle control signal (P c ) having a pulse width which is a function of the magnitude of said difference signal, wherein said pulse generating means includes a sawtooth signal source (5), for providing a sawtooth signal of constant amplitude and constant frequency; and a comparator (6), for comparing said sawtooth signal with the magnitude of said duty cycle control signal in response thereto. The multiplier circuit of any preceding claim wherein each multiplier (1₁-1 n ) includes an operational amplifier (A₁-A n ) connected to said analog switch (T₁-T n ) for receiving said input signal therethrough, a feedback resistor (R₂₁-R 2n ) and a filtering capacitor (C₁₁-C 1n ). The multiplier circuit of any preceding claim where each multiplier further includes an input resistor (R₁₁-R 1n ) having a resistance cooperative with said feedback resistor ((R₂₁-R 2n ) for determining the mu-factor for adjusting the multiplier. A method of multiplying electrical signals, comprising: providing a plurality of voltage signals (1N₁-1N n ,IN s ) to a plurality of corresponding switches (T₁-T n ,T s ); switching each of said voltage signals ON or OFF in response to a duty cycle control signal (P c ), thereby providing a plurality of corresponding switched voltage signals; integrating said switched voltage signals, thereby providing corresponding multiplied voltage signals(OUT₁-OUT n ,OUT s ); summing the magnitude of one of said multiplied voltage signals (OUT S ) with the magnitude of a multiplier signal (V in ), thereby providing a difference signal (V₄); multiplying said difference signal with a sawtooth signal (V osc ) , thereby providing said duty cycle control signal (P c ).

Inventors: KITO YASUTAMI, OSHIMA KENJI, KITO, YASUTAMI, OSHIMA, KENJI
Applicants: OTIS ELEVATOR CO, OTIS ELEVATOR COMPANY
Application year: 1988
Main classification: G06G7
IPC codes: H03K7, G06G7, H03F3