DRIVING APPARATUS FOR BRUSH-LESS MOTOR

Abstract: A phase difference between a counter-­ electromotive voltage induced in a driving coil and a voltage which is applied to the driving coil is detected by comparison of a terminal voltage of the driving coil (U₀) and a reference voltage (N B ), a frequency of a voltage-control oscillator which controls switching of the voltage applied to the driving coil is varied by an output signal made by the comparison, and the phase difference is controlled to be zero thereby.

Description: The present invention relates to a driving apparatus for a brushless motor according to the precharacterizing portion of the main claim. Generally, a conventional brushless motor has a position sensor for sensing a position of a rotor. The position sensor utilizes a light sensing device or a magnetic sensing device. And plural switching devices for switching driving currents of plural driving coils of the brushless motor are controlled on the basis of an output signal of the position sensor. In order to reduce a cost of the brushless motor and to miniaturize it in size, it is desirable to realize a brushless motor which does not require such a position sensor. A driving apparatus for the brushless motor in the prior art is shown, for example, in the Japanese published unexamined patent application Sho 52-80415. Fig. 14 is a circuitry of the driving apparatus in the prior art. Referring to Fig. 14, each one terminal of driving coils 1, 2 and 3 of the brushless motor is together coupled. The other terminal of the driving coil 1 is coupled to the junction between the anode of a diode 4 and the cathode of a diode 5, and is also coupled to the junction between the respective collectors of the transistors 10 and 13. The other terminal of the driving coil 2 is coupled to the junction between the anode of a diode 6 and the cathode of a diode 7, and is also coupled to the respective collectors of transistors 11 and 14. The other terminal of the driving coil 3 is coupled to the junction between the anode of a diode 8 and the cathode of a diode 9, and is also coupled to the junction of the respective collectors of transistors 12 and 15. The respective cathodes of the diodes 4, 6 and 8 and the respective emitters of the transistors 10, 11 and 12 are coupled to a positive power source line Vcc. The respective anodes of the diodes 5, 7 and 9 and the respective emitters of the transistors 13, 14 and 15 are grounded. Furthermore, the respective terminals of the driving coils 1, 2 and 3 are connected to respective input terminals of a filter circuit 16. Respective output terminals of the filter circuit 16 are connected to respective input terminals of a switching circuit 17. Output of the switching circuit 17 are applied to the respective bases of the transistors 10, 11, 12, 13, 14 and 15. Operation of the driving apparatus for the brushless motor in this prior art is elucidated hereafter. FIG.15(a)--FIG.15(1) are waveform charts showing operation of the driving apparatus. Waveforms as shown in FIG.15(a), 15(b) and 15(c) are of voltages U₀, V₀ and W₀ of the driving coils 1, 2 and 3, respectively. The voltages U₀, V₀ and W₀ are inputted to the filter circuit 16. Harmonic components of the voltages U₀, V₀ and W₀ are eliminated by the filter circuit 16, and hence, the respective phases of the voltages U₀, V₀ and W₀ becomes retard by 90°. The filtered and phase-shifted waveforms of the voltages U₀, V₀ and W₀ are shown by waveforms of output signals F₁, F₂ and F₃ of the filter circuit 16. The filter circuit 16 is a linear filter, and comprises RC passive filter or a linear Miller integrating circuit, for example. A cut-off frequency of the filter circuit 16 is selected by be far lower than a frequency of the voltages U₀, V₀ and W₀. The output signals F₁, F₂ and F₃ of the filter circuit 16 are inputted to the switching circuit 17. The switching circuit 17 comprises a logic circuit and generates control signals U H , U L , V H , V L , W H and W L by logical operation of the output signals F₁, F₂ and F₃. The control signals U H , U L , V H , V L , W H and W L are applied to the bases of the transistors 10, 11, 12, 13, 14 and 15. The transistors 10, 12, 13, 14 and 15 are switched by the control signals U H , V H , W H , U L , V L and W L , respectively, so that the torque of the rotor of the brushless motor is produced in a selected direction. In the brushless motor of the prior art, a filter circuit having a low cut-off frequency which is far lower than the frequency of the voltages U₀, V₀, W₀ is required for each driving coil of the brushless motor. The filter circuit having the low cut-off frequency comprises capacitors having large capacitance, and many large capacitors must be mounted in the driving apparatus. Furthermore, in the driving coil having a large inductance, a phase of the current flowing the driving coil is retard from a phase of the output of the transistors. Consequently, counter action of the rotor arises, and thereby a magnetic field of permanent magnets of the rotor is eliminated by the magnetic field produced by the driving coil itself. In the above-mentioned case, when the voltages U₀, V₀ and W₀ of phases relation as shown in FIG.15(a), 15(b) and 15(c), respectively are supplied to the driving coils 1, 2 and 3, respectively, it is known that the efficiency of the brushless motor is lowered. A method for compensating lag of the current due to the counter action of the rotor by advancement of the phases of the signals F₁, F₂ and F₃ as shown in FIG.15(d), FIG.15(e) and FIG.15(f), respectively in order to improve the efficiency, is disclosed in the Japanese published unexamined patent application Sho 52-80415. In the driving apparatus of the patent application Sho 52-80415, further capacitors and other electronic components are required. Furthermore, spike-shaped noises induced at turns ON are superimposed on the voltages U₀, V₀ and W₀, and further, the voltages U₀, V₀ and W₀ are varied by variation of the current induced by variation of the power supply voltage and variation of a load. Therefore, it is difficult to obtain the complete signals F₁, F₂ and F₃ by the filter circuit 16. In order to improve the above-mentioned difficulties, the Japanese patent Sho 59-36519 discloses that three-phase voltages generated in stator windings of the brushless motor are converted to signals of triangular waveform having phase difference of about 90° from that of the three-phase voltages, respectively. The three signals of the triangular waveform are applied to the respective terminals of the resistors which are connected in Y-shape. Then, the above-mentioned signals of the triangular waveform are compared with a voltage of the junction of the Y-shaped connection, and three pulse signals are output. Semiconductor switching devices of three-phase bridge-connection are controlled by the three-pulse signals, and a rotor of a permanent magnet is rotated. However, the method for producing the switching signals from the voltages of the driving coils by means of the filter circuit has fundamentally following problems: a spike-shaped noise is induced immediately after turns of state of the semiconductor switching device, and is superimposed on a fundamental signal of the counter-electromotive voltage generated in the driving coils. The level of the spike-shaped noise signal is always varied by variation of a power source voltage or load of the brushless motor. As a result, the switch timing of the current to be supplied to the driving coils deviates from a normal timing. In order to maintain a precise switch timing, various methods have been developed. One of the methods is to maintain a constant phase difference between the counter-electromotive voltage and the current switching signal by adjustment of the filter circuit. However, maintenance of the constant phase difference is very difficult in the actual operation. Furthermore, many capacitors are required to make the circuit in addition to the capacitors of the filter circuit, and there is difficulties in size-reduction by mounting the capacitors in an integrated circuit due to increase of the external components and number of the connection, consequently the driving apparatus is expensive. A current switching method using a digital circuit such as a microcomputer is disclosed in the Japanese published unexamined patent application Sho 61-293191. In this prior art, a time period from a time of current switching to a time wherein the terminal voltage of a driving coil meets to the voltage of the junction of the three driving coils is measured on the basis of a clock signal, and the subsequent current switching is operated at a time which is four times of the time period. A microcomputer is used to measure the above-mentioned time, and thereby the driving apparatus is expensive. Furthermore, a current switching method using a phase locked loop circuit (PLL) is described in the Japanese patent Sho 61-3193. The circuit block diagram of this prior art is shown in FIG.16. Counter-electromotive voltages A, B and C as shown in FIG.17(a), FIG.17(b) and FIG.17(c), respectively, are inputted to comparators 24, 25 and 26, respectively. Outputs D, E and F of the comparators 11, 12 and 13 as shown in FIG.17(d), FIG.17(e) and FIG.17(f), respectively, are applied to a logic circuit composed of AND gates 27, 28 and 29 and an OR gate 23. An output signal G of the OR gate 23 is shown in FIG.17(g). An output of a voltage control oscillator 20 is de-multiplied by a frequency de-multiplier 21, and the output of the frequency de-multiplier 21 is compared with the pulse signal G in a phase detector 18. The output of the phase detector 18 is fed back to the voltage control oscillator 20, and the output of the frequency de-multiplier 21 is synchronized with the output signal G. The output signal of the frequency de-multiplier 21 is demultiplied and by frequency de-multipliers 22A and 22B is applied to the semiconductor switching devices 10--15. In the above-mentioned method, since the voltage which is supplied to the driving coil and spike-shaped noise signal which is generated by turns ON or OFF of the switching device are superimposed on the counter-electromotive voltage generated in the driving coil in actual operation. Therefore, it is very difficult to obtain only the output signal G by reform and logical process of the counter-electromotive voltage. In the actual operation, the pulse signal G as shown in Fig. 17(g) can not be obtained by the circuitry as shown in Fig. 16 by influence of the spike-shaped noise signal. Therefore, the output of the frequency de-multiplier 21 can not be compared with the pulse signal G, and synchronization between both the signals I as shown in Fig. 17(i) and G is difficult. An object of the present invention is to provide an improved driving apparatus for a brushless motor for realizing precise current switching which is free from a spike-shaped noise superimposed on the current flowing in driving coils, variation of the power supply voltage, a load variation and reaction of a rotor. The driving apparatus for a brushless motor in accordance with the precharacterizing portion of claim 1 comprises, for solving the above object, the characterizing features of claim 1. In the driving apparatus in accordance with the invention, the phase difference between a supply voltage and a counter-electromotive voltage is compensated without use of a positive sensor of a motor. Preferred embodiments of the invention are stated in the dependent claims. Embodiments of the invention and examples of the state of art are disclosed below with reference to the drawings in which: Fig. 1 is a circuitry of a first embodiment of a driving apparatus for a brushless motor in accordance with the present invention; Fig. 2(a), Fig. 2(b) and Fig. 2(c) are waveform charts showing operation of the first embodiment; Fig. 3 is a circuitry of a phase difference detector; Fig. 4(a), Fig. 4(b), Fig. 4(c), Fig. 4(d), Fig. 4(e), Fig. 4(f), Fig. 4(g), Fig. 4(h) and Fig. 4(i) are waveform charts showing operation of the phase difference detector; FIG.5(a), FIG.5(b), FIG.5(c), FIG.5(d), FIG.5(e), FIG.5(f), FIG.5(g), FIG.5(h), FIG.5(i), FIG.5(j), FIG.5(k), FIG.5(l) and FIG.5(m) are waveform charts showing detailed operation of the first embodiment; FIG.6 is a circuitry of a second embodiment of the driving apparatus for the brushless motor in accordance with the present invention; FIG.7 is a circuitry of a lowest frequency limiting circuit; FIG.8 is a circuitry of a third embodiment of the driving apparatus of the brushless motor in accordance with the present invention; FIG.9(a), FIG.9(b), FIG.9(c) and FIG.9(d) are waveform charts showing operation of the third embodiment of the driving apparatus for the brushless motor; FIG.10(a) and FIG.10(b) are a detailed circuitry of the third embodiment as shown in FIG.8; FIG.11 is a circuitry of a fourth embodiment of the driving apparatus for the brushless motor in accordance with the present invention; FIG.12(a) and FIG.12(b) are a detailed circuitry of the fourth embodiment of the driving apparatus for the brushless motor; FIG.13(a), FIG.13(b), FIG.13(c), FIG.13(d) and FIG.13(e) are waveform charts showing operation of the fourth embodiment as shown in FIG.11 and FIG.12; FIG.14 is the circuitry of the driving apparatus of the brushless motor in the prior art; FIG.15(a), FIG.15(b), FIG.15(c), FIG.15(d), FIG.15(e), FIG.15(f), FIG.15(g), FIG.15(h), FIG.15(i), FIG.15(j), FIG.15(k) and FIG.15(l) are waveform charts showing operation of the driving apparatus of the brushless motor in the prior art; FIG.16 is the block diagram of the driving apparatus of the brushless motor in other prior art; FIG.17(a), FIG.17(b), FIG.17(c), FIG.17(d), FIG.17(e), FIG.17(f), FIG.17(g), FIG.17(h), FIG.17(i), FIG.17(j), FIG.17(k), FIG.17(l), FIG.17(m), FIG.17(n) and FIG.17(o) are the waveform charts showing operation of the driving apparatus of the brushless motor as shown in FIG.16. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.1 is a circuitry of a first embodiment of a driving apparatus for a brushless motor in accordance with the present invention. Referring to FIG.1, elements similar to the elements of FIG.14 are identified by like numerals. Each one terminal of driving coils 1, 2 and 3 is together coupled at a junction N. The other terminal of the driving coil 1 is coupled to the junction between the anode of a diode 4 and the cathode of a diode 5, and is also coupled to the junction between the respective collectors of the transistors 10 and 13. The other terminal of the driving coil 2 is coupled to the junction between the anode of a diode 6 and the cathode of a diode 7, and is also coupled to the respective collectors of transistors 11 and 14. The other terminal of the driving coil 3 is coupled to the junction between the anode of a diode 8 and the cathode of a diode 9, and is also coupled to the junction of the respective collectors of transistors 12 and 15. The respective cathodes of the diodes 4, 6 and 8 and the respective emitters of the transistors 10, 11 and 12 are coupled to a positive power source line Vcc. The respective anodes of the diodes 5, 7 and 8 and the respective emitters of the transistors 13, 14 and 15 are grounded. The respective terminals of the driving coils 1, 2 and 3 are connected to input terminals 127A, 127B and 127C of the comparator 127 through buffer circuits 121, 122 and 123, respectively. Resistors 124, 124 and 126 are connected across the input terminals 127A, 127B and 127C and an input terminal 127D of the comparator 127, respectively. The output of the comparator 127 is connected to an invert input of an operational amplifier 31 of an amplifier 30 through a resistor 32. A reference voltage which is decided by resistors 36 and 37 is applied to a noninvert terminal of the operational amplifier 31. A feedback capacitor 34 and a resistor 33 which are coupled in series and a feedback capacitor 35 are connected across the invert input and an output terminal of the operational amplifier 31. The output of the amplifier 30 is inputted to a voltage control oscillator 40. A frequency of the voltage control oscillator 40 is controlled by a voltage applied by the amplifier 30. The output of the voltage control oscillator 40 is inputted to a frequency de-multiplier 41. An output D₁ of the frequency de-multiplier 41 is inputted to a logic circuit 42 of a switching signal generation circuit 44. The other output D₂ of the frequency de-multiplier 41 is inputted to a phase difference pulse generator 128. Six outputs U₁, U₂, V₁, V₂, W₁, W₂ of the logic circuit 42 are inputted to a power amplifier 43, and are also inputted to the phase difference pulse generator 128. An output of the phase difference pulse generator 128 is applied to the comparator 127. A phase difference detector 120 is composed of the phase difference pulse generator 128 and the comparator 127. Outputs U H , U L , V H , V L , W H , W L of the power amplifier 43 are applied to the respective bases of the transistors 10--15. Operation of the first embodiment is elucidated hereafter. Waveforms of voltages across both the terminals of one of three driving coils 1, 2 and 3 in operation are shown in FIG.2(a), FIG.2(b) and FIG.2(c). Referring to FIG.2(a), FIG.2(b) and FIG.2(c), a sinusoidal counter-electromotive voltage as shown by both dotted lines and solid lines is superimposed by a square wave supply voltage from the switching circuit 45, and a composite waveform is shown by a solid line. Spike-shaped signal A are generated by inductance of the driving coil at turn-OFF of the transistors of the switching circuit 45. The most suitable state of the phase difference between the sinusoidal counter-electromotive voltage and the supply voltage is shown in FIG.2(a). On the other hand, in the composite waveform as shown in FIG.2(b), the phase of the supply voltage is retard from the phase of the sinusoidal counter-electromotive voltage by  degrees. On the contrary, the phase of the supply voltage advances to the sinusoidal counter-electromotive voltage by  degrees in the waveform as shown in FIG.2(c). Referring to FIG.1, since the switching circuit 45 is driven on the basis of the output signal of the voltage control oscillator 40, each phase of the voltages which are applied to the driving coil 1, 2 and 3 maintains a predetermined phase difference with the output signal of the voltage control oscillator 40. Therefore, phase difference between the counter-electromotive voltage and the voltage which is supplied to the driving coil 1, 2 or 3 is variable by control of the frequency and phase of the voltage control oscillator 40. In the first embodiment, the phase difference , as shown in FIG.2(b) or FIG.2(c) is detected by the phase difference detector 120 as a phase difference signal PD. The phase difference signal PD of the phase difference detector 120 is amplified by the amplifier 30, and is applied to the voltage control oscillator 40. The oscillating frequency of the voltage control oscillator 40 is varied by variation of an output EAO of the amplifier 30 so that the phase difference  is converged on zero. Namely a phase control loop is formed by the phase difference detector 120 and the voltage control oscillator 40. As a result, as shown in FIG.2(a), the most suitable state of the phase relation between the counter-electromotive voltage and the voltage which is applied to the driving coil 1, 2 or 3 are maintained, and stable revolution is realized, furthermore efficiency of the brushless motor is improved. An actual circuit of the phase difference detector 120 is shown in FIG.3. Referring to FIG.3, terminal voltages U₀, V₀ and W₀ of the respective driving coils 1, 2 and 3 are inputted to respective buffer circuits 121, 122 and 123. The output terminals of the respective buffer circuit 121, 122 and 123 are joined together through the respective resistors 224, 225 and 226, and the junction NB is coupled to the invert input terminals of comparators 100, 129 and 140, and is also coupled to respective noninvert input terminals of the comparators 110, 130 and 150. Furthermore, the output U B of the buffer circuit 121 is applied to the noninvert input of the comparator 100 and the invert input of the comparator 110. The output V B of the buffer circuit 122 is applied to the noninvert input of the comparator 129, and is applied to the invert input of the comparator 130. The output W B of the buffer circuit 123 is applied to the noninvert input of the comparator 140 and the invert input of the comparator 150. The respective outputs of the comparators 100, 110, 129, 130, 140 and 150 are output as open collector of the respective transistors 101, 111, 119, 131, 141 and 151. The respective collectors of the transistors 101, 111, 119, 131, 141 and 151 are joined together, and therefrom the output PD of the phase difference detector 120 is output. The base of the transistor 161 is coupled to the base and the collector of the transistor 162, and is also coupled to the collectors of the transistor 164 and the transistor 169 which serves as a constant current source. A regulated power source voltage Vreg is applied to the emitter of the transistor 161 through a resistor 163. The regulated power source voltage Vreg is also applied to the emitters of the transistors 161 and 164. The base of the transistor 164 is coupled to the emitter thereof through a resistor 166, and is coupled to the collector of the transistor 167 through a resistor 165. The emitter of the transistor 167 is grounded. An output S₀ of the phase difference pulse generator 128 is applied to the base of the transistor 167 through a resistor 168. Other outputs S₁, S₂, S₃, S₄, S₅ and S₆ of the phase difference pulse generator 128 are applied to the respective bases of the emitter-grounded transistors 170, 172, 174, 176, 178 and 180 through the resistors 171, 173, 175, 177, 179 and 181, respectively. The collectors of the transistors 170, 172, 174, 176, 178 and 180 are coupled to the bases of the transistors 101, 111, 119, 131, 141 and 151, respectively. The outputs U₁, U₂, V₁, V₂, W₁ and W₂ of the logic circuit 42 are inputted to the respective inputs of the phase difference pulse generator 128. The output D₂ of the frequency de-multiplier 41 is also inputted to the phase difference pulse generator 128. Operation of the above-mentioned phase difference detector 120 is elucidated hereafter. FIG.4(a)--FIG.4(i) are waveform charts showing operation of the phase difference pulse generator 128 for detecting phase difference between the counter-electromotive voltage and supply voltages with respect to the driving coil 1. The outputs U H , U L of the power amplifier 43 which are substantially identical with the outputs U₁, U₂ of the logic circuit 42 are in synchronism with the outputs D₁ and D₂ of the frequency de-multiplier 41 de-multiplied the frequency of output of the voltage control oscillator 40. The voltage which is applied to the driving coil 1 is controlled on the basis of the outputs U₁, U₂. When both the outputs U₁, U₂ are not issued, both bases of the transistors 10 and 13 remain low level and the driving voltage to the driving coil 1 are not supplied. The time period between a fall edge of the output U₁ and a rise edge of the output U₂ as shown in FIG.4(c) and FIG.4(d) is designated as "a current suspensive period I". In the current suspensive period I, the waveform of the terminal voltage U o of the driving coil 1 is identical with the waveform of the counter-electromotive voltage U e as shown in FIG.4(a). The current suspensive period I is shown by an interval in which both the output U₁ and U₂ are in low level as shown in FIG.4(c) and FIG.4(d), and is equal to one cycle of the output D₁ as shown in FIG.4(e), and is equal to four cycles of the output D₂ as shown in FIG.4(f). In the levels of the voltage N₀ of the junction N of the driving coils 1, 2 and 3 and terminal voltage U₀ of the driving coil 1, when the phase difference between the terminal voltage U₀ and the counter-electromotive voltage U e is zero, the voltage N₀ becomes equal to the terminal voltage U₀ at a intermediate time T₁ of the current suspensive period I. The intermediate time T₁ is equal to a time of two cycles of the output D₂ after a fall edge of the output U₁ as shown in FIG.4(c). On the other hand, when phase of the terminal voltage U₀ lags from that of the counter-electromotive voltage U e by a phase difference , the waveform of the voltage N₀ agrees with that of the terminal voltage U₀ at the part between the fall edge of the output U₁ and the intermediate time T₁ as shown in FIG.4(a) and FIG.4(b). On the contrary, when phase of the voltage U₀ advances to that of the counter-electromotive voltage U e by a phase difference , the waveform of the voltage N₀ agrees with the waveform of the voltage U₀ between the intermediate time T₁ and the rise edge of the output U₂. Therefore, phase relation between the voltages U₀ and U e is detected by comparison of the voltages U₀ and N₀ in the current suspensive period I. In order to detect the phase difference , as shown in FIG.4(g) and FIG.4(h), outputs S₂ and S₀ of phase difference detecting pulse signals, which has a pulse width substantially equal to a time of one cycle of the output D₂ and is positioned at the center of the current suspensive period I, are generated; and the voltage N₀ is compared with the output U₀ during the phase difference detecting pulse signals S₂ and S₀ are generated. Consequently, a phase difference signal PD having a duty ratio corresponding to the phase difference  is issued from the phase difference detector 120. Referring to FIG.4(i), the voltage U₀ is later than the voltage U e by the phase difference . The above-mentioned operation is accomplished during the current suspensive period I between the fall edge of the output U₂ and the rise edge of the output U₁. And in a similar manner, the operation is accomplished with respect to voltages V₀ and W₀ of the respective driving coils 2 and 3. The phase difference signal PD of the phase difference detector 120 is a composite signal of the plural comparators. The buffer circuits 121, 122 and 123 serve as inverting amplifiers having a gain of 1/2, and voltages of the outputs U B , V B and W B of the respective buffer circuit 121, 122 and 123 are made to be in the range of input voltages of the respective comparators 100, 110, 129, 130, 140 and 150. Output voltages of the respective circuits in operation of the phase difference detector 120 as shown in FIG.3 are shown in FIG.5(a)--FIG.5(m). Referring to FIG.5(l), the phase difference signal PD of the phase difference detector 120 is formed on the basis of the respective terminal voltages U₀, V₀ and W₀, and the output EAO for controlling the voltage control oscillator 40 is generated by the amplifier 30. The frequency of the voltage control oscillator 40 is varied by the output EAO. As a result, the output of the frequency de-multiplier 41 is phase-sifted, and thereby the phase difference  is made to be zero. Variation of the output EAO is shown in FIG.5(m). Referring to FIG.5(m), in initial stage, the output EAO is of comparatively low level as shown in a left portion of the waveform, and the revolution velocity of the brushless motor is low. The phase of the terminal voltage U₀ lags from that of the counter-electromotive voltage U e as shown in FIG.5(l). Then, the revolution velocity gradually rises by boost of the output EAO, and the phase of terminal voltage U₀ leads that of the counter-electromotive voltage V e as shown in central portion of FIG.5(l). Finally, the output EAO becomes a constant value, and the phase difference converges on zero in the right portion of the FIG.5(l) and FIG.5(m). As mentioned above, according to the embodiment, the driving coils 1, 2 and 3 of the brushless motor are driven on the basis of the output of the voltage control oscillator 40. Then, the phase difference between the voltages applied to the driving coils 1, 2 and 3 and the counter-electromotive voltages of the driving coils 1, 2 and 3 are detected by the phase difference detector 120, and the frequency of the voltage control oscillator 40 is controlled so that the phase difference is converged on zero by the amplified signal of the phase difference detector. Therefore, the brushless motor is free from influence of the rotor reaction, and efficiency of the brushless motor is improved. In the embodiment, the driving apparatus has no filter circuit, accordingly, the present invention dispenses with use of capacitors having large capacitance. Moreover, the phase difference signal PD is generated in the current suspensive period I by comparing voltages applied to the driving coils with a neutral voltage N B . Which is a composite voltage of the driving coils 1, 2 and 3. Since the phase difference signal PD is generated out of a period of presence of the spike-shaped signal A, influence by the spike-shaped signal A is avoidable. Moreover, detection of the phase difference is accomplished during the current suspensive period I, and therefore the switch timing of the driving apparatus is not influenced by the voltage drop due to the impedance of the driving coils and a variation of the current flowing the driving coils. Furthermore, a pulse width of the phase difference signal PD corresponds to "an electric angle" or "a mechanical angles" of the brushless motor. Therefore, the phase difference depends on a duty ratio of the output wherein the counter-electromotive voltage is compared with the neutral voltage N B in the current suspensive period I, and sensitivity for detecting the phase difference is not influenced by the revolution speed of the brushless motor. As a result, stable operation of the phase control loop is continuously maintained. FIG.6 is a circuit of a second embodiment of the driving apparatus for the brushless motor in accordance with the present invention. In the second embodiment, a lowest frequency limiting circuit 50 is added to the circuitry as shown in FIG.1. A circuitry of the lowest frequency limiting circuit 50 is shown in FIG.7. Referring to FIG.7, a reference voltage source 51 is applied to an invert input of a comparator 52 of the lowest frequency limiting circuit 50. The output voltage EAO of the amplifier 30 is applied to a noninvert terminal of the comparator 52. The output of the comparator 52 is inputted to the invert input of the operational amplifier 31 of the amplifier 30. The voltage of the reference voltage source 51 is to set a lowest frequency of the voltage control oscillator 40. The comparator 52 compares the output voltage EAO of the amplifier 30 with the reference voltage V₅₁ of the reference voltage source 51. The comparator 52 applies an output to the invert input of the operational amplifier 31 when the output voltage EAO is lower than the reference voltage V₅₁ of the reference voltage source 51, and further drop of the output voltage EAO is prevented. As a result, the frequency of the voltage control oscillator 40 is held above the lowest frequency corresponding to the voltage V₅₁ of the reference voltage source 51. Operation of the driving apparatus having the lowest frequency limiting circuit 50 is elucidated hereafter. Referring to FIG.6, since the lowest frequency limiting circuit 50 maintains the frequency of the voltage control oscillator 40 to a value which is higher than a predetermined lowest frequency, switching operation of the current switching circuit 44 is always maintained. Therefore, revolution of the brushless motor is maintained. Moreover, when the power source of the driving apparatus is supplied, or even if the revolution of the rotor is stopped, a torque of the rotor is generated. After start of revolution of the rotor, the counter-electromotive voltage is generated in the driving coils, and the phase control loop of the first embodiment is formed and the stable revolution of the brushless motor is maintained. In the circuit as shown in FIG.7, though the output EAO of the amplifier 30 is compared with the reference voltage V₅₁ of the reference voltage source 51, substantially the same function is effectuated by comparison of the reference voltage V₅₁ with a signal corresponding to the frequency, directly or indirectly. FIG.8 is a circuitry of a third embodiment of the driving apparatus for the brushless motor in accordance with the present invention. In the third embodiment, oscillation frequency initializing means 70, which is composed of the lowest frequency limiting circuit 50 and a oscillation frequency lowering circuit 60, is added to the circuitry of the first embodiment as shown in FIG.1. The oscillation frequency lowering circuit 60 controls the output of the phase difference detector 120 on the basis of operation of the lowest frequency limiting circuit 50. In starting of the brushless motor, when the power source voltage Vcc is supplied to the driving apparatus, the output EAO of the amplifier 30 is irregular due to influence of electric charges which are charged in the capacitors 34 and 35, and the phase difference signal PD of the phase difference detector 120 is generally unstable. Consequently, an oscillation frequency f of the voltage control oscillator 40 is also unstable. For example, if the voltage control oscillator 40 oscillates a very high frequency, the driving coils 1, 2 and 3 are switched on the basis of the high frequency. Thus, the magnetic field of the driving coils 1, 2 and 3 revolve in high velocity. On the other hand, since the rotor has a predetermined inertia, revolution of the rotor can not follow the revolving magnetic field by the driving coils 1, 2 and 3, since the revolution number of the magnetic field becomes higher than that of the rotor which has a considerable inertia. As a result, a starting torque is not produced, and the brushless motor can not be started. The oscillation frequency initializing means 70 serves to resolve the above-mentioned problem. An example of a detailed circuit of the driving apparatus comprising the oscillation frequency initializing means 70 is shown in FIG.10(a) and FIG.10(b). Referring to FIG.10(a), the oscillation frequency initializing means 70 is composed of the lowest frequency limiting circuit 50 and the oscillation frequency lowering circuit 60. The lowest frequency limiting circuit 50 is identical with the circuit as shown in FIG.7. The transistor 55 of the lowest frequency limiting circuit 50 turns ON when the voltage of output EAO of the amplifier 30 coincides with the voltage of the reference voltage source 51, and the frequency f of the voltage control oscillator 40 coincides with a lowest frequency f low corresponding to the voltage of the reference voltage source 51. However, the transistor 55 remains OFF when the frequency f is above the lowest frequency f low . Immediately after supply of the power source, the frequency f is generally higher than the lowest frequency f low , therefore the transistor 55 turns OFF. Then, the collector voltage level R₁ of the transistor 55 turns to high level. In the above-mentioned state, a transistor 62 remains OFF, and both transistors 63 and 64 remain OFF. Consequently, a transistor 66 remains ON because of the base current supplied through the resistor 65, and thereby the transistor 67 remains ON, and the output S remains at a high level. Thus, an electric power is not supplied to the comparators 100, 110, 129, 130, 140 and 150, and the respective transistors 101, 111, 119, 131, 141 and 151 turn OFF. As a result, a current does not flow into the output terminal 120A of the phase difference detector 120. On the other hand, outflow of the current from the output terminal 120A of the phase difference detector 120 is controlled by the transistor 161 under the low level of the output S₀ of the phase difference pulse generator 128. The output S₀ is generated by logical operation of the output of the voltage control oscillator 40 and becomes to a low level or to the high level in synchronism with the frequency f of the voltage control oscillator 40. Consequently, the phase difference signal PD turns to high level at every becoming to low levels of the output signal S₀, and thereby the output EAO of the amplifier 30 is lowered. Thus, the frequency f of the voltage control oscillator 40 is also lowered responding to the output EAO, and when the frequency f reaches the lowest frequency f low , the transistor 55 turns ON. In this time, the output R₁ of the oscillation frequency lowering circuit 60 turns to low level. Then, the transistor 62 turns ON, and the transistors 63 and 64 also turns ON. If the transistor 55 turns OFF after turns ON of the transistor 63, the transistor 62 remains ON by turn ON of the transistor 63. Namely, after the frequency f reaches the lowest frequency f low , the transistors 62, 63 and 64 remain ON, and the transistors 66 and 67 remain OFF. Consequently, the electric power is supplied to the comparator 100, 110, 129, 130, 140 and 150, and the respective transistor 101, 111, 119, 131, 141 and 151 become operable, and the phase difference detector 120 allows inflow of the current. Transistors 62 and 63 form a memory circuit 61 for memorizing the above-mentioned operation hysteresis of the lowest frequency limiting circuit 50. In the above-mentioned circuit, when the power source voltage Vcc is applied to the driving apparatus as shown in FIG.9(a), the output S of the oscillation frequency lowering circuit 60 remains high level as shown in FIG.9(d), and thereby the phase difference signal PD does not turns to low level, and increase of the output EAO is prevented. Therefore, when the phase difference signal PD turns high level, the output EAO lowers, and frequency f of the voltage control oscillator 40 is lowered as shown in FIG.9(b). When the frequency f of the voltage control oscillator 40 is lowered to the lowest frequency f low of the lowest frequency limiting circuit 50, the output R₁ of the lowest frequency limiting circuit 50 turns to low level as shown in FIG.9(c). The output R₁ is inputted to the oscillation frequency lowering circuit 60. Consequently the output S of the oscillation frequency lowering circuit 60 turns to low level as shown in FIG.9(d). The current inflow function of the phase difference detector 120 is activated by the low level output S, and the frequency f of the voltage control oscillator 40 rises from the lowest frequency f low . Accordingly, the revolution velocity of the revolving magnetic field of the driving coils gradually increases from a predetermined low revolution velocity which can be followed by the rotor, and the brushless motor is started. According to the above-mentioned third embodiment, since the oscillating frequency of the voltage control oscillator 40 is initialized to a predetermined frequency, when the power source is supplied to the driving apparatus, the brushless motor can be started without failure. In the example as shown in FIG.8, current inflow function of the phase difference detector 120 is stopped by turning to high level of the output S of the oscillation frequency lowering circuit 60, and the oscillation frequency of the voltage control oscillator 40 is lowered. The same effect is realized by turning to high level input of the inverse input terminal of the operational amplifier 31. FIG.11 is a circuitry of a fourth embodiment of the driving apparatus for the brushless motor in accordance with the present invention. In the fourth embodiment, an abnormal state detecting circuit 80 is added to the circuitry of the third embodiment as shown in FIG.8. When the rotating rotor is stopped by braking, for example, the counter-electromotive voltages of the driving coils 1, 2 and 3 disappear. In this time, if the frequency f of the voltage control oscillator 40 is higher than a predetermined value, the rotor can not follow a revolving magnetic field produced by the driving coils 1.2 and 3. As a result, a starting torque is not produced on the rotor, thus the brushless motor cannot restart revolution, even if the braking force is released. In the above-mentioned case, the abnormal state detecting circuit 80 detects a state of high frequency of the voltage control oscillator 40, and controls the oscillation frequency initializing means 70. Consequently, the Frequency of the voltage control oscillator 40 is initialized to a predetermined low frequency, and the brushless motor restarts. FIG.12(a) and FIG.12(b) are a detailed circuit of the driving apparatus comprising the abnormal state detecting circuit 80. Referring to FIG.12(a), the abnormal state detecting circuit 80 comprises a comparator wherein a reference voltage source 81 is coupled to the invert input terminal, and the invert input of the operational amplifier 31 of the amplifier 30 is coupled to the noninvert input thereof. The output R₂ of the abnormal state detecting circuit 80 is inputted to the oscillation frequency lowering circuit 60. The remaining circuits as shown in FIG.12(a) and FIG.12(b) are identical with that of FIG.10(a) and FIG.10(b). When the rotor is stopped, since the output EAO of the amplifier 30 rises or falls on the basis of the phase difference signal PD of the phase difference detector 120, and the frequency f of the voltage control oscillator 40 is varied. When the frequency f of the voltage control oscillator 40 is lowered, a revolution velocity of the revolving magnetic field decreases. When the revolution velocity reaches a value wherein the rotor can follow, the starting torque is produced and the brushless motor restarts revolution. On the other hand, in case that the frequency f of the voltage control oscillator 40 rises, the revolution velocity of the revolving magnetic field increases. Thus the rotor can not follow the revolving magnetic field, and the starting torque is not produced. In this state, the frequency f of the voltage control oscillator 40 rises to a saturation value of the output EAO. In the abnormal state detecting circuit 80, the above-mentioned abnormal state is detected by detecting saturation of the output EAO. Referring to FIG.12(a) and FIG.12(b), a reference voltage of the reference voltage source 81 which is slightly lower than a noninvert input voltage of the operational amplifier 31 is applied to the invert input of the comparator of the abnormal state detecting circuit 80. The invert input voltage of the operational amplifier 31 is compared with the reference voltage of the reference voltage source 81. When the output EAO saturates, the invert input voltage of the operational amplifier 31 becomes lower than the reference voltage of the reference voltage source 81, and a transistor 85 of the abnormal state detecting circuit 80 turns ON (Output R₂ is in low level). Then the transistors 63 and 64 turn OFF, and the transistors 66 and 67 turn ON. Therefore, the output S of the oscillation frequency lowering circuit 60 turns to high level, and the output EAO falls. Thus the frequency f is lowered and is initialized. As a result, the brushless motor is enabled to be started. FIG.13(a)--FIG.13(d) are waveform charts showing operation of the driving apparatus as shown in FIG.12(a) and FIG.12(b). Referring to FIG.13(a), the rotor is stopped at time t₀, and revolution velocity n becomes zero. Then, the output EAO rises to a maximum value as shown in FIG.13(b), and the output R₂ turns to low level as shown in FIG.13(d). Consequently, the output S turns to high level as shown in FIG.13(e). The output EAO is lowered and finally reach the lowest frequency of the lowest frequency limiting circuit 50 at time t₂. Thus the frequency of the voltage control oscillator 40 is initialized. In the abnormal state detecting circuit 80 as shown in FIG.12(a) and FIG.12(b), abnormal state is detected by saturation of the output EAO of the amplifier 30, wherein the abnormal state can be detected by rise of the output EAO to a predetermined upper limit of the output EAO. In the above-mentioned embodiments, though the disclosure is elucidated with respect to the three-phase full-wave driving method, the present invention is applicable to a two-phase full-wave driving method, two-phase half-wave driving method or three-phase half-wave driving method.

Claims: A driving apparatus for a brushless motor comprising: switching means (10-15) for switching a driving voltage (Vcc) to the driving coils (1, 2, 3) of said brushless motor; a switching signal generation circuit (44) for controlling said switching means (10-15); a phase difference detector (120) for detecting and outputting a signal (PD) proportional to the phase difference (PD) between the counter-electromotive voltages (Uo, Vo, Wo) induced in said driving coils (1, 2, 3) and switching signals (U n , V n , W n , U₁, V₁, W₁) generated by said switching signal generation circuit (40); an amplifier (30) for amplifying said detected phase difference signal (PD); a voltage-controlled oscillator (40) for generating a signal (f) controlled in phase by said detected phase difference signal (PD) and for supplying said phase controlled signal (f) to said switching signal generating circuit (44); characterized in that said phase difference detector (120) further comprises a phase difference pulse generator (128) for generating for each coil of the motor, during a current suspensive period (I) in which said driving voltage (Vcc) is not applied to the respective driving coil (1, 2, 3), pulse signals (S₁, S₂, S₃, S₄, S₅, S₆) on the basis of said phase controlled signal (f); comparing means (100, 110, 129, 130, 140, 150) for comparing, in synchronism with the respective pulse signal (S₁-S₆) of said phase difference pulse signal generator (128), said counter-electromotive voltage (Uo, Vo, Wo) induced in the respective driving coil with a reference voltage (NB) which is a composite signal of the driving coils voltages. Driving apparatus for a brushless motor according to claim 1, wherein said phase difference detector (120) further comprises buffer circuits (121-123) connected to respective terminals of said driving coils (1-3). Driving apparatus for a brushless motor according to claim 2 or 3, wherein said comparing means (100, 110, 129, 130, 140, 150) comprises plural comparators wherein output terminals thereof are coupled together, and operation of the respective comparators is controlled by outputs of said phase difference pulse generator (128). Driving apparatus for a brushless motor according to one of claims 1 to 3, characterized by a lowest frequency limiting circuit (50) for limiting lowest frequency of said voltage control generator (40). Driving apparatus for a brushless motor according to claim 4, wherein said lowest frequency limiting circuit (50) compises a lowest frequency setting means (51) and a comparator (52) for detecting a difference between a voltage applying to said voltage control oscillator and a voltage of said lowest frequency setting means, and said amplifier (30) is controlled by the output of said comparator and thereby the lowest oscillating frequency of said voltage control oscillator (40) is limited. Driving apparatus for a brushless motor according to one of the claims 1 to 5, characterized by an oscillation frequency intializing means (70) for initializing a frequency of said voltage control oscillator into a predetermined value. Driving apparatus for a brushless motor according to claim 6, wherein said oscillation frequency initializing means (70) comprises the lowest frequency limiting circuit (50) and an oscillation frequency lowering circuit (60) for lowering an oscillation frequency of said voltage control oscillator (40), and a lowest frequency of said voltage control oscillator (40) which is lowered by said oscillation frequency lowering circuit (60) is limited within a predetermined value. Driving apparatus for a brushless motor according to claim 7, wherein said oscillation frequency lowering circuit (60) comprises a memory circuit (61) for memorizing operation of said lowest frequency limiting circuit (60), and said phase difference detector (120) is controlled by said memory circuit (61). Driving apparatus for a brushless motor according to one of the claims 6 to 8, characterized by an abnormal state detecting circuit (80) for detecting abnormal state of frequency of said voltage control oscillator (40) and for activating said oscillation frequency initializing means (70). Driving apparatus for a brushless motor according to claim 9, wherein said abnormal state detecting circuit (80) comprises a comparator wherein an invert input voltage (PD) of an operational amplifier (31) of said amplifier (30) is compared with a reference voltage (81) applied to the invert input of said comparator.

Inventors: KIMURA, YOSHITSUGU, NAKANO, HIROMITSU, YASOHARA, MASAHIRO
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: H02P6
IPC codes: H02P6