Semiconductor memory device with improved column selection scheme

Abstract: A drive timing signal generator for generating a drive timing signal used for driving transfer gate transistors in a memory device, is disclosed. The generator includes a boost circuit for operative generating a boosted voltage above the power voltage and an additional boost circuit for further boosting the boosted voltage generated by the boost circuit after the generation of the boosted voltage in a write mode.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a semiconductor memory device, and more particular to a timing signal generator for column selection in a dynamic type semiconductor memory device. A dynamic memory device is structured such that a plurality of memory cells are arranged in a matrix form of rows with word lines and columns with a plurality pairs of digit lines and a plurality of sense amplifiers are provided for the plurality pairs of digit lines. The plurality pairs of digit lines are coupled to a pair of data bus lines through a plurality pairs of column selection transfer gates, respectively. Each pair of transfer gates are controlled by a column decode signal generated by a column decoder. The column decoder is generally composed of a NOR gates receiving column address signals, a source-follower transistor and a coupling transistor coupled between an output of the NOR gate and a gate of the source follower transistor. The drain of source-follower transistor is supplied with a drive timing signal and the decode signal for controlling the transfer gates is derived from the source of the source-follower transistor. The drive timing signal is generated in response to an externally applied chip enable signal ( CE ) and takes a boosted level higher than a power voltage V cc . Therefore, the column selection transfer gates are rendered conductive in the non-saturated, triode region so that signal transfer between the data bus lines and the bit lines is effectively performed. However, the above drive timing signal is generated by a known boot-strap circuit and the drive timing signal is capacitively boosted above V cc . Thus, the drive timing signal has a large internal impedance and its boosted level above V cc gradually falls. Furthermore, it is common that a wiring for carrying the drive timing signal has a plurality of crossing points with other signal wirings such as the data bus lines. Accordingly, it is difficult to effectively achieve the Read-Modify-Write cycle, in which a read operation is performed on a selected address and immediately thereafter a write operation is made on the same selected address. In this cycle, the drive timing signal is produced during a relatively long period and hence its boosted level inevitably falls below V cc in the write operation due to leakage of the boosted charge and coupling of the drive timing signal wiring with other wirings. As a result, in the write operation, the level of the drive timing signal is no more of the boosted level above V cc but lower than V cc and therefore the column selection transfer gates are made conductive in the saturated region and their effective conductances are small. Thus, it is difficult to write new data to the selected address through the transfer gates conductive in the saturated region, resulting failure in changing data stored in the selected address through the transfer gates. SUMMARY OF THE INVENTION: It is one object of the present invention to provide a semiconductor memory device which can read one data from a selected address and thereafter write the other data to the same selected address stably. It is another object to provide a semiconductor memory device provided with an improved timing signal generator which can produce a drive timing signal having the boosted level above V cc over the whole Read-Modify-Write cycle. These objects are achieved by a semiconductor memory as defined in the claim. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic block diagram of a semiconductor memory device according to a prior art; Fig. 2 is a schematic circuit diagram of a drive timing signal generator according to a first embodiment of the invention; Fig. 3 is a timing chart showing operation of the circuit of Fig. 2; Fig. 4 is a schematic circuit diagram of a drive timing signal generator according to a second embodiment of the present invention; Fig. 5 is a timing chart of operation of the circuit of Fig. 4; Fig. 6 is a schematic circuit diagram of a drive timing signal generator according to a third embodiment of the invention; Fig. 7 is a timing chart showing operation of the circuit of Fig. 6; Fig, 8 is a schematic circuit diagram of a drive timing signal generator according to a fourth embodiment of the present invention; and Fig. 9 is a timing chart showing operation of the circuit of Fig. 8. DETAILED DESCRIPTION OF THE INVENTION: Referring to Fig.1, a general structure of a semiconductor memory device is explained. A memory cell array 1 includes a plurality of word lines WL arranged in rows, a plurality of digit lines DL arranged in columns and a plurality of memory cells MC. A row decoder 2 receive row address signals and operatively selects one of the word lines WL. The digit lines are classified into a plurality of groups each including consecutive four digit lines. Each group of digit lines DL are coupled to four data bus lines I/O 1 - I/O 4 through four column selection transfer gates such as shown QC1 - QC4. The transfer gates QC1 - QC4 .... are controlled by column decoder units YD1 - YDn. The column decoder unit YD1 is composed of a NOR gate 4-1 receiving column address signals, a coupling transistor Q₁ and a source-follower transistor Q₃. The source-follower transistor Q₃ receives at its drain a drive timing signal YSE which is generated by a drive timing signal generator 5. The drive timing signal YSE is also applied to the source-follower transistors Q₃ of other decoder units via a wiring 7 extending in the column direction across the data bus lines I/O 1 - I/O 4. There are stray capacitances C S between the wiring 7 and the respective data bus lines. The drive timing signal generator 5 is a boot-strap circuit and the signal YSE is capacitively boosted above V cc . A bus selection circuit 3 selectively establishes a signal path between a common bus line CB and one of data bus lines. The common bus line CB is connected to a read/ write circuit 6 which is controlled between a read mode and a write mode in response to a read-write control signal WE . A timing control circuit 4 receives a chip enable signal CE and generates control signals XSE,  and DSE in a predetermined order for enabling the row decoder 2, the generator 5 and the selection circuit 3, respectively. As is well known in the art, the boosted level of the signal YSE gradually falls according to time elapse and therefore it is difficult to maintain the level of the signal YSE above V cc for a long period. Furthermore, the level of YSE is affected by the levels of the data bus lines I/O 1 - I/O 4 via stray capacitors C s . Therefore, after read out signals from the four digit lines DL are transferred to the data bus lines I/O 1 - I/O 4 and change in level at the data bus lines further lowers the level of YSE. Thus, the conductance of the selected transfer gates (QCI - QC4) is lowered. Under the above condition of the transfer gates, when a write operation is initiated, different write data signals are applied to the data bus lines I/O 1 - I/O 4 via the read/write circuit 6. However, the conductance of the transfer gates is small and it is difficult to write new data to the digit lines DL via the transfer gates at a high speed. Referring to Fig. 2, a drive timing signal generator 5 according to the first embodiment is explained. In Fig. 2, the portions or elements corresponding to those in Fig. 1 are denoted by similar or same references. In Fig. 2, a pair of digit lines DL and DL are provided for each column and the data bus lines I/O1, I/O1 - I/O4, I/O4 and transfer gates QC1, QC′1 - QC4, QC′4 are provided in balanced manner to accord with the pairs of digit lines. A flip-flop type sense amplifier SA is provided to each pair of digit lines. The drive timing signal generator 5 is basically composed of a boot-strap circuit 11, a first capacitive pull-up circuit 12 and a second capacitive pull-up circuit 13. The boot-strap circuit 11 is composed of N-channel field effect transistors (N-MOSTs) Q11 to Q22 and a boot capacitor C₁₁ and generates an output signal of V cc through N-MOST Q21 in response to a precharge signal ø p , and timing signals ₁ and ₂ which are generated in response to the chip enable signal CE . The first capacitive pull-up circuit 12 is composed of N-MOSTs Q₂₃ to Q₂₆ and pull-up capacitors C₁₂ and C₁₃, and further raises the V cc level output of the boot-strap circuit 11 above V cc thereby to generate the boosted level of YSE, in response to a timing signal ₃ generated in accordance with CE . The second boost circuit 13 is composed of N-MOSTs Q₃₀ to Q₃₃ and boost capacitors C₁₄ and C₁₅. The circuit 13 receives the precharge signal  P and a write timing signal  W which is generated in a write operation. The circuit 13 further boosts the level of YSE in the write operation in response to the rise of  W . Referring to Fig. 3, operations of the circuit of Fig. 2 is explained. The chip enable signal CE is changed to the low ("0") level at a time point t₁₀ to enable the memory for access. Then the precharge signal  P is fallen to the low level (ground level) at t₁₁. Then, the timing signal ₁ is raised to the high level at t₁₂ to enable the circuit 11. The N-MOSTs Q₂₀ and Q₂₂ are turned off and the potential at N₁₄ is raised above V cc . Thus, the signals YSE and YjA are raised to V cc . The timing signal ₂ is then raised at a time point t₁₃ to V cc level to make N-MOST Q₁₈ conductive so that the level at node 14 is lowered and N-MOSTs Q₁₉ to Q₂₂ are made non-conductive. As a result, the V cc level of YSE is maintained under high impedance, floating state. At a time point t₁₄, the timing signal ₃ is raised to V cc level so that nodes N₁₆ and N₁₅ are raised above V cc through capacitors C₁₂ and C₁₃. As a result, the level of YSE is raised to V cc + VT (VT being a threshold voltage of N-MOSTs) or more, and the signal YjA is also raised to V cc + VT or more. Accordingly, transfer gate MOSTs QC₁, QC′₁ - QC₄, QC′₄ are rendered conductive in the non-saturated, triode region thereby to provide large conductances between the four pairs of digit lines DL, DL and four pairs of bus lines I/O 1, I/O 1 - I/O 4, I/O 4 so that read signals on the above digit lines are transferred to the data bus lines for outputting read information. Then, at a time point t₁₅, the read/write control signal WE is changed to the low level and a write operation is initiated with respect to the same address on which the previous read operation has achieved. At a time point t₁₆, new data (low) signal is applied to the data bus line I/O 1 which has been at the high level. This change in potential at I/O 1 is transmitted to the signal YSE through the stray capacitors C S to lower the level of YSE. In this instance, in the case where the sum of four stray capacitors C S is about one-third of the total capacitance of YSE and YjA, the levels of YSE and YjA are fallen from (V cc + VT) to (V cc - VT) or less and the current flowing ability i.e. conductance of the transfer gate N-MOSTs QC1, QC′1 - QC4, QC′4 is remarkably reduced to the extent that inverting a state of the sense amplifier by the level of I/O 1 is difficult. Assuming that the current flowing ability of the transfer gate N-MOSTs QC1, QC′1 - QC4, QC′4 is one-tenth of that of N-MOSTs forming a flip-flop of the sense amplifier SA, the levels of the digit lines DL and DL become 9/10 V cc and 1/10 V cc , respectively. The timing signal  W is activated to the high level at t17 so that the circuit 13 boosts the level of YSE above (V cc + VT) by the capacitive boost due to the capacitor C₁₄ and C₁₅. As a result, the column decode signal YjA is again boosted to the level of (V cc + VT) or more so that the transfer gate N-MOSTs QC1, QC′1 - QC4, QC′4 are conducting in the non-saturated, triode region. Thus, the data bus lines I/O 1, I/O 1 - I/O 4, I/O 4 are connected to the four pairs of digit lines DL, DL via the large conductance of N-MOSTs QC1, QC′1 - QC4, QC′4 and the states of the sense amplifiers SA are easily inverted according to the new write data through the digit lines DL and DL which are set to D and V cc levels, respectively. At t₁₉, CE is reset to the high level and the signals ₁ - ₃ and  W are all changed to the low level at t₂₀. At t₂₁, the precharge signal  p is raised and the digit lines DL, DL are precharged to terminate the operation. Referring to Fig. 4, a drive timing signal generator according to a second embodiment of the invention is featured by a CMOS buffer circuit 11′ in place of the boot-strap circuit 11 in Fig. 2. The CMOS buffer circuit 11′ is composed of P-channel MOSTs (P-MOSTs) Q41, Q43 and N-MOSTs Q₄₂, Q₄₄ to Q₄₆. In the circuit 11′, in place of the timing signal ₂ of Fig. 2, its opposite signal ₂ is employed to make the output of the circuit 11′ at the high level, high impedance state when ₂ is made low in level. Operation of the circuit of Fig. 4 is illustrated in Fig. 5. Only difference with respect to the embodiment of Fig. 2 resides in the above-mentioned timing signal ₂ . Referring to Fig. 6, a drive timing signal generator according to a third embodiment of the invention is featured by a write timing boot-strap circuit 14 and a coupling control circuit composed of N-MOSTs Q₆₃ - Q₆₅. Also in place of  W , three sequentially generated write timing signals  W1 -  W3 are employed. The circuit 14 is composed of N-MOSTs Q₅₁ to Q₆₂ and a capacitor C₅₁ and has the similar circuit structure to the circuit 11. The circuit 14 produces the output of V cc level at a node N56 in response to the high level of  W1 and renders the high level output at the high impedance, floating state. The high level of the output at the node N56 is transmitted to the outputs of the circuits 11, 12 and 13′ via N-MOSFET Q₆₃ made conductive in response to  W1 via Q₆₄. Then, when  W3 goes to high in level, N-MOST Q₆₅ becomes conductive to make N-MOST Q₆₃ non-conductive so that the node N56 is isolated from the outputs (YSE) of the circuits 11, 12 and 13′. While in response to the rise  W3 , the circuit 13′ capacitively boosts the level of YSE above (V cc + VT). Operation of the circuit of Fig. 6 is illustrated in Fig. 7. As is apparent from Fig. 7, after WE goes to the low level at t₁₅, the timing signals  W1 ,  W2 and  W3 are sequentially produced at t₁₆, t₁₇ and t₁₈ respectively to boost YSE. Fig. 8 shows a drive timing signal generator according to a fourth embodiment of the invention. This embodiment is obtained by adding a write timing CMOS buffer 14′ and the coupling control circuit composed of N-MOSTs Q₆₃ - Q₆₅ to the embodiment of Fig. 4. The CMOS buffer 14′ generates the V cc level at the node N56′ in response to the high level of  W1 and renders the high level at the node N56′ at the high impedance, floating state in response to the low level of  W 2 which is opposite to  W2 . Operation of the circuit of Fig. 8 is similarly understood from Fig. 9. As has been explained above, the present invention advantageously produces boosted level of drive timing signal for a long period, particularly for a write period subsequent to a read period.

Claims: A semiconductor memory device comprising a plurality of word lines (WL), a plurality of digit lines (DL, DL), a plurality of memory cells (MC) coupled to said word lines (WL) and said digit lines (DL, DL), at least one data bus line (I/0 1 ...I/0 4), a plurality of transfer gate field effect transistors (QC1, QC1'...QC4, QC4') coupled between said digit lines (DL, DL ) and said at least one data bus line, a row decoder (2) coupled to said word lines for selecting one of said word lines, and a column decoder (YD1) coupled to gates of said transfer gate field effect transistors for making a part of said transfer gate field effect transistors conductive, said column decoder including a logic gate (4-1) receiving adress information, a source-follower transistor (Q3), means for connecting the source of said source follower transistor (Q3) to a gate or gates of the part of said transfer gate field effect transistors, a first boost circuit (12) for operatively generating a first boosted voltage above a power voltage (Vcc) at its output end, a second boost circuit (13) for operatively generating a second boosted voltage above said power voltage (Vcc) after the generation of said first boosted voltage in a write mode, means for applying said first boosted voltage to the drain of said source-follower transistor (Q3) and means for applying said second boosted voltage to the drain of said source-follower transistor (Q3).

Inventors: NAKAIZUMI KAZUO, NAKAIZUMI, KAZUO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G11C7
IPC codes: G11C7