Semiconductor device with semimetal

Abstract: Disclosed is a semiconductor device with semimetal having a high switching speed and high current gain in the microwave region. To reduce the energy difference between the conduction band edge of a base layer and the valance band edge of an emitter layer or a collector layer, and to reduce the base resistance, a semimetal base transistor is provided.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device with a semimetal having superior characteristics such as a high switching speed, high current gain in the microwave region, and so forth. 2. Description of the Related Art In general, electrons having a high energy higher than the Fermi energy by 2 to 3 kT (k: Boltsman constant, T: lattice temperature) are referred to as hot electrons. Several semiconductor devices are known in which the hot electrons are used for the transportation between one terminal and the other terminal in a three-terminal transistor similar to the bipolar transistor. In such semiconductor devices, only the metal base transistor (MBT), (see, for example, S. M. Sze and H. K. Gummel "Appraisal of Semiconductior-Metal-Semiconductor Transistors," Solid State Electronics, vol. 9, p. 751 (1966)) having a superior microwave characteristics with a high current gain is known. In the MBT, however, since the Schottky barrier between the semiconductor emitter or collector and the metal base is too high, the reflection factor of the carriers at the interface between the semiconductor layer and the metal layer is large, and therefore, the injection efficiency from the emitter to the base is low. Further, in the metal base layer, the injected carriers are scattered by the electrons so that a considerable amount of energy of the carriers is lost in the base layer, resulting in a large base current and small current amplification factor. As a semiconductor device in which the above-mentioned first drawback of the MBT is eliminated, a hot-electron transistor (HET) is known (Heiblum "Tunneling Hot Electron Transfer Amplifiers (THETA); A Proposal for Novel Amplifiers Operating in the Subpicosecond Range", International Electron Device Meeting, p. 629 (1980)). In the HET, a high density n-type semiconductor is used as base material so that the potential barrier between the emitter or the collector and the base is smaller than that in the MBT. The HET, however, has a drawback of a larger base resistance than the MET, which causes a lowering of the maximum oscillating frequency. To lower the maximum oscillating frequency in the HET, the base length can be elongated. The long base length, however, also lowers the maximum oscillating frequency, and therefore, it is not preferable in the HET to elongate the base length to lower the base resistance. Apart from the above-mentioned MBT or HET, Japanese Unexamined Patent Publication No. 62-45064, published on February 27 1987, discloses a four-terminal semiconductor device of heterojunctions. In this device, a semimetal is realized only when a bias voltage is applied to the device. Further, a semiconductor-semimetal transistor in InAs-GaSb superlattices is mentioned in a paper of Appl. Phys. lett. 35 (12), 15 December, 1979 0003 - 6951/79/240939, pp 939 - 942. In this paper, it is disclosed that a semimetal state is realized in a GaSb - InAs superlattice when the InAs layer thickness is between 100 Å and 200 Å. Appl. Phys. Lett. Vol. 51, No. 13, 28th Sept. 1987, pgs. 984 986 disclose the room temperature operation of hot-electron transistors having the features of the upper clause of claim 1. SUMMARY OF THE INVENTION In view of the above-mentioned prior art, an object of the present invention is to provide a semiconductor device with a semimetal base having a smaller base length and lower base resistance, so that the frequency characteristic in the high frequency range is improved. This object has been achieved by the features of claims 1,4 and 10. The first and second semiconductor layers have substantially the same conduction bands and have substantially the same valence bands when a bias voltage is not applied thereto. At the interfaces between the first and third semiconductor layers and between the second and third semiconductor layers, the energy level of the conduction band edge of the third semiconductor layer being lower than the energy level of the valence band edge of the first or second semiconductor layer. The third semiconductor layer has a thickness sufficiently thin that, at least at the interfaces between the first and third semiconductor layers and between the second and third semiconductor layers, a semimetal layer is formed. In the above-described semiconductor device according to the present invention, a three-terminal device having a semimetal layer is obtained in which a high switching speed, low reflection factor in quantum mechanics, and small base resistance are realized. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a main-portion cut side view of a conventional MBT and a corresponding energy-band diagram of the MBT ; Fig. 2 is an energy-band diagram of the state when a voltage is applied to the MBT shown in Fig. 1; Fig. 3 is an energy-band diagram of the state when a voltage is applied to a conventional HET; Fig. 4 is an energy-band diagram of a conventional InAs - GaSb superlattice in a semiconductor state; Fig. 5 is an energy-band diagram of the conventional InAs - GaSb superlattice in a semimetal state; Fig. 6 is an experimental graph illustrating the relationship between carrier concentrations and layer thickness to demonstrate the semiconductor-semimetal transition; Fig. 7 is an energy-band diagram for explaining the operating principle of a semiconductor device; Figs. 8 to 12 are main-portion cut side views of the semiconductor device in the main manufacturing processes, for explaining the manufacture of an embodiment of the present invention; Fig. 13 is a main-portion cut side view of a semiconductor device for explaining another embodiment of the present invention; Fig. 14 is an energy-band diagram of the embodiment shown in Fig. 13; Fig. 15 is a main-portion cut side view of a semiconductor device for explaining still another embodiment of the present invention; Fig. 16 is an energy-band diagram of the embodiment shown in Fig. 15; Fig. 17 is a diagram for explaining the energies of minibands in the embodiment shown in Fig. 15; and Fig. 18 is a diagram for explaining that the embodiment shown in Fig. 15 has a negative resistance. DESCRIPTION OF THE PREFERRED EMBODIMENTS For a better understanding of the present invention, the prior arts and the problems therein will be first described with reference to Figs. 1 to 6. Figure 1 is a main-portion cut side view of a conventional MBT and a corresponding energy-band diagram of the MBT (S. M. Sze and H. K. Gummel "Appraisal of Semiconductor-Metal-Semiconductor Transistors, " Solid State Electronics, vol. 9, p. 751 (1966)). In the figure, 11 represents an emitter layer (E) consisting of Si, 12 represents a base layer (B) consisting of Au, and 13 represents a collector layer (C) consisting of Ge, respectively. The horizontal axis in the band diagram represents the distance, and the vertical axis represents the energy. E C represents the bottom of the conduction band, E V the top of the valence band,  B the Schottky barrier height, and L B the length (here, 90 [Å]) of the base layer 12. The above-mentioned MBT has, as found by experiment, a common base current gain α 0 of only about 0.3, which is very low. The reasons for this are as follows. Figure 2 shows an energy-band diagram when a base-emitter voltage V BE is applied between the base and the emitter and a base-collector voltage V BC is applied between the base and the collector, in which the same symbols as used in Fig. 1 represent the same parts or have the same meaning. In the figure, E CE represents the bottom of the conduction band in the emitter layer, E CB the bottom of the conduction band in the base layer, E CC the bottom of the conduction band in the collector layer, eV BE the Fermi-level difference between the emitter layer and the base layer produced by the base-emitter voltage V BE , eV BC the Fermi-level difference between the base layer and the collector layer produced by the base-collector voltage V BC , Δε EB the energy difference, at the interface between the emitter layer and the base layer, between the bottom E CE of the conduction band in the emitter layer and the bottom E CB of the conduction band in the base layer, Δε BC the energy difference at the interface between the base layer and the collector layer, between the bottom E CB of the conduction band in the base layer and the bottom E CC of the conduction band in the collector layer, PS BE a power supply for generating the voltage V BE applied between the base and the emitter, PS BC a power supply for generating the voltage V BC applied between the base and the collector, and e - an electron, respectively. The current gain α 0 is i c /i e , i.e., the ratio of the electron e - injected from the emitter layer 11 to the electrons reaching the collector layer 13. When all of the electrons e - reach the collector layer 13, α 0 = 1. In the MBT, the current gain α 0 is very small. There are two major reasons for the small current gain α 0 in the MBT. First, when the electrons e - are injected from the emitter layer 11 to the base layer 12, the energy of the electrons e - is greatly increased, as illustrated in the figure by Δε. This is due to the very large energy difference Δε EB between the bottom E CE of the conduction band in the emitter region 11 and the bottom E CB of the conduction band in the base region 12, at the interface therebetween. Namely, such a sharp and large potential difference causes the electrons e - to be reflected quantum-mechanically so that the amount of the electrons e - which cannot reach the collector layer 13 is increased. In a similar way, such a reflection also occurs due to Δε BC when the electrons are injected from the base region 12 to the collector region 13. That is, at the interface between the semiconductor emitter and the metal base, and between the metal base and the semiconductor collector, the reflection factor τ is large and the transportation factor t is small, due to the large energy difference, as is well known in the field of quantum mechanics. From the above, it will be understood that, to increase the current gain α 0 , the base material having a relatively small Δε EB and small Δε BC must be chosen. Another reason is that, because the density of electrons in the metal layer is large, many electrons e - running through the base layer 2 are scattered by the electrons (- 10 22 [cm -3 ]) in the metal. Therefore, a considerable number of electrons, cannot reach the collector layer 13. From the above, it will be understood that the density of electrons in the base layer 12 must be relatively small. Figure 3 shows an energy-band diagram when a base-emitter voltage V BE and the base-collector voltage V BC are applied to an HET. Note, the same symbols as used in Figs. 2 and 3 represent the same parts or have the same meaning; 12a in Fig. 3 is a high density n-type semiconductor base layer. In the figure, R B is a base resistance, and Δε 1EB and Δε 1BC represent the potential differences affected when the electrons are injected from the emitter to the base and from the base to the collector, respectively. In the HET, to operate at a high frequency, the base resistance R B is preferably as small as possible. This is understood from the following expression of the maximum oscillating frequency f max in a bipolar transistor: f max = 1 2 ( fτ 2πγ B C C ) 1/2 where, f T = 1 2πτ ec τ ec = τ E + τ C + τ C , τ B : base resistance C C : collector capacitance f T : cut-off frequency: τ ec : emitter-collector delay time τ E : emitter depletion layer charging time τ B : base charging time τ C : collector depletion layer charging time, and τ C' : collector charging time. To lower the base resistance R B , the base length L B of the base layer 12a can be made as long as possible, to increase the cross sectional area of the base layer. But if the base length L B is increased, the cut-off frequency is lowered, and thus the maximum oscillation frequency f max is lowered. Therefore, to lower the base resistance R B and to make the base length L B thin are contradictory requirements. Further, to maintain the property of the HET, the doping of the n-type impurity into the semiconductor base layer 12a has a limit of, for example, about 10 18 to 10 19 (cm -3 ), and therefore, the base region R B cannot be made lower than a certain value. Japanese Unexamined Patent Publication No. 62-45064, discloses a four terminal semiconductor element. This semiconductor element comprises heterojunctions of at least a first semiconductor layer (InAs layer) and a second semiconductor layer (GaSb) having a valence band edge Ev higher than the conduction band edge Ec of the first semiconductor layer. A first voltage is applied in the vertical direction of the heterojunctions, while a second voltage is applied in the parallel direction of the heterojunctions, so that the first and the second semiconductor layers become a semimetal layer. Figures 4 and 5 are band diagrams of InAs - GaSb superlattices in a semiconductor state and semimetal state respectively, of the above-mentioned prior art. In this prior art, however, to enable a switching operation, the thickness of the InAs layer and the GaSb layer must be as thick as 300 Å to 500 Å, and therefore, the semimetal state is not realized unless the second voltage is not applied in the parallel direction of the heterojunctions. Second, the above-mentioned semiconductor element has four terminals, two of which are used for the bias voltage applied in the vertical direction of the heterojunctions and the other two of which are used for the signal voltage applied in the horizontal direction of the heterojunctions. Therefore, this element is not a transistor but a switching element. Third, in the semimetal state of the above prior art element, a current always flows through the subband (miniband) E 1 for electrons and through the energy level HH 1 of holes. Therefore, in the semimetal state, the switching operation will not occur. Figure 6 is an experimental graph illustrating the relationship between carrier concentrations and layer thickness, to demonstrate the semiconductor-semimetal transition region disclosed in App. Phys. Lett. 35 (12), 15 December 1979, pp 939 to 942. As shown in the graph, when the thickness of the InAs layer is between 100 Å and 200 Å, the carrier concentration is greatly increased so that a semiconductor-semimetal transition occurs. In view of the above-described prior arts with reference to Figs. I to 6, the present invention will provide a three-terminal semiconductor device with a semimetal base having a small energy difference Δε EB between the bottoms of the conduction bands of the emitter and the base, having a smaller energy difference Δε BC between the bottoms of the conduction bands of the base and the collector than the MBT, and having a smaller base resistance R B than the HET. In the present invention, the basic concept is that the base layer is constructed by a semimetallic material or a heterojunction is produced by using a specific semiconductor material in the base layer to realize a semimetal base transistor (SMBT), by utilizing the semimetallic characteristics at the boundary surface. As is well known, in a semimetal, both the electrons and holes are present without the provision of an energy band gap. That is, when the top of the conduction band in a semiconductor layer is lower than the bottom of the valence band of the adjacent semiconductor layer, a semimetal state is realized. As the semimetal material for constructing the above-mentioned base region, Hg 1-x Cd x Te, for example, can be recommended. In this case, by selecting the value x to be x = 0.14 and the temperature to be 77 [K], for example, a suitable condition for the semiconductor device of the present invention can be realized. Also, when the semimetal characteristic is utilized in the aforementioned heteroboundary surface, it is sufficient to select the conditions explained as follows. Figure 7 represents an energy band diagram of a semiconductor device when bias voltages V BE and V BC are applied to the semiconductor device, the semiconductor device is an SMBT utilizing the semimetallic characteristic near the boundary of the heterojunction generated by utilizing a specific semiconductor material in the base region, in which the same symbols as the symbols used in Fig. 1 to 3 represent the same parts or have the same meaning; for simplicity, the band diagram in Fig. 7 shows a state at the absolute temperature of zero degrees. In Fig. 7, 2 is a collector layer, 4 a base layer, 6 an emitter layer, 7 a collector electrode in ohmic contact with the collector layer 2, 8 an emitter electrode in ohmic contact with the emitter layer 6, and 9 a base electrode in ohmic contact with at least the base layer 4, e the electrons, h holes, Δε 2EB an energy difference between the bottoms of the conduction bands of the emitter and the base layers, and Δε 2BC an energy difference between the bottoms of the conduction bands of the base and the collector layers, respectively. E FC , E FB and E FE represent Fermi levels of the collector, base and emitter layers, respectively. As can be seen in the figure, when the heterojunctions are assembled, and when the relationship among the energy band gap E g , the electron affinity χ, and the work function  are: χ 2 + E g2 < χ 1 where, E g2 : the energy band gap of the semiconductor used in the emitter (or the collector) region 6 (or 2); χ 1 : the electron affinity of the semiconductor used in the base region 4; χ 2 : the electron affinity of the semiconductor used in the emitter (or the collector) region 6 (or 2); then, a semimetallic characteristic is realized at at least the boundary surfaces of the heterojuntions, whereby the energy difference Δε 2EB between the conduction band edges of the emitter and the base and the energy difference Δε 2BC between the conduction band edges of the base and the collector can be made smaller than the Δε EB and the Δε BC in the MBT, and the base resistance R B can be made smaller than in the conventional case utilizing semiconductor as a base layer. In other words, when the energy level E CB of the conduction band edge of the base layer 4 is lower than the energy level E VE of the valence band edge of the collector or emitter layer 2 or 6, a semimetal layer is formed at least at the boundary region between the base and the collector or between the base and the emitter, as illustrated in the figure by dash lines. The reduced resistance R B is obtained not only by the semimetal base but also by the electrons e in the conduction band and the holes h in the valence band. To obtain a large reduction of the base resistance, preferably the base electrode 9 is in contact with the full side surface of the base layer 4 and a part of the emitter layer 6 and the collector layer 2 at the vicinity of the interfaces, to conduct the electrons and holes. The semiconductor device shown in Fig. 7 is a three-terminal element structure, i.e., the collector electrode 7, the emitter electrode 8, and the base electrode 9. The base layer 4 and the vicinity of the interfaces form a semimetal base region. In operation of the transistor shown in Fig. 7, when V BE is applied between the base and the emitter, the barrier between the emitter and the base is lowered so that the electrons, which are carriers in the emitter region, having an energy higher then E CE , are injected into the base region. The electrons injected into the base region are transferred as hot electrons to the collector region. By employing the above-mentioned structure, a semiconductor device having a high switching speed, a smaller energy difference Δε than an MBT, and a smaller base resistance R B than an HBT can be realized. The small energy difference Δε results in a small reflection factor in quantum mechanics at the boundary surface of the heterojunctions. The collector layer 2, the base layer 4, and the emitter layer 6 are, preferably, GaSb, InAs, and GaSb, respectively. Figure 8 is a main-portion cut side view illustrating an embodiment of the semiconductor device described with reference to Fig. 7, in which the semimetallic characteristic at the heterojunction generated by a specific material is utilized. In Fig. 8, 1 represents a semiinsulating GaAs substrate, 2 an n + -type GaSb collector layer, 3 an n-type GaSb collector barrier layer, 4 an n + -type InAs base layer, 5 an n-type GaSb emitter barrier layer, 6 an n + -type GaSb emitter layer, 7 a collector electrode, 8 an emitter electrode, and 9 a base electrode, respectively. The main data relating to each portion in the embodiment shown in Fig. 8 are expressed as an example in the following. (a) For the collector layer 2: Thickness: 5000 [Å], where (and hereinafter) 1 Å is 1 x 10 -8 cm; n-type impurity: Te Density of the impurity: 2 x 10 18 [cm -3 ] (b) For the collector barrier layer 3: Thickness: 500 [Å] n-type impurity: Te or nondoped Density of the impurity: 6 x 10 16 [cm -3 ] (c) For the base layer 4: Thickness: 150 [Å] The thickness of the base layer 4 may be between 100 Å and 200 Å n-type impurity: Si Density of the impurity: 1 x 10 19 [cm -3 ] (d) For the emitter barrier layer 5: Thickness: 150 [Å] n-type impurity: Te or nondoped Density of the impurity: 6 x 10 16 [cm -3 ] (e) For the emitter layer 6: Thickness: 5000 [Å] n-type impurity: Te Density of the impurity: 2 x 10 18 [cm -3 ] (f) For the collector electrode 7: Material: Au·Te Thickness: 1000 [Å] (g) For the emitter electrode 8 Material: Au·Te Thickness: 1000 [Å] (h) For the base electrode 9 Material: Au Thickness: 1000 [Å] In the SMBT, the boundary surface, i.e., the interface between the collector barrier layer 3 and the base layer 4 and the boundary surface or the interface between the base layer 4 and the emitter barrier layer 5, constitute heterojunctions and represent semimetallic characteristics. Therefore, the Δε 2EB and the Δε 2BC are small and the base resistance R B is low. Note that the base electrode 9 is in ohmic contact with the side surface of the base layer 4 and with at least a part of the side surfaces of the emitter barrier layer 5 and the collector barrier layer 3, at a part of the vicinity of the interface between the emitter barrier layer 5 and the base layer 4 and between the collector barrier layer 3 and the base layer 4. Figures 9 to 12 are main-portion cut side views for explaining the main process of manufacturing the embodiment shown in Fig. 8. The following explanation is given with reference to Figs. 8 to 12. Referring to Fig. 9. (1) For example, by applying molecular beam epitaxy (MBE), layers from the collector layer 2 to the emitter layer 6 are continuously grown on the substrate 1. The various data for each semiconductor layer in this case are as described before. Referring to Fig. 10. (2) By applying a resist process in a usual photo-lithography technique, a photo resist film 14 is formed to cover the portion except for the portion for forming the collector region. Then, by using the film 14 as a mask and by applying a wet etching method, etching is carried out from the surface of the emitter layer 6 to the collector layer 2, to selectively expose a part of the collector layer 2. Note that, as the etchant, Br 2 CH 3 OH may be employed. (3) By applying a vacuum evaporation method under the conditions in which the photo-resist film 14 is kept as it is, an Au.Te film is formed, and by a lift-off method for removing the photo resist film 14, the collector electrode 7 is formed. Note that the figure shows the state in which the lift-off method has not been carried out. Referring to Fig. 11. (4) By applying a resist process in a usual photo-lithography technique, a photo resist film is formed to cover the portion except for the portion for forming the emitter region. Then, by applying a vacuum evaporation method, an Au·Te film is formed, and by a lift-off method for removing the photo-resist film, the emitter electrode 8 is formed. (5) By applying a laser annealing method, the collector electrode 7 and the emitter electrode 8 are alloyed. Referring to Figs. 12 and 8. (6) By applying a resist process in a usual photo-lithography technique, a photo resist film 15 is formed to cover the portion except for the portion for forming the base region. Then, by applying a vacuum evaporation method, an Au film is formed, and by a lift-off method for removing the photo-resist film 15, the base electrode 9 is formed. Note that the base electrode 9 made of Au can be brought into ohmic contact with the n + -type InAs base layer 4 without carrying out the annealing for alloying. Also, since Schottky barrier contacts are provided for the n-type GaSb collector barrier layer 3 or the n-type GaSb emitter barrier layer 5, leakage to the collector layer 2 or to the emitter layer 6 is automatically prevented. Note that the base electrode 9 made of Au is in ohmic contact with the holes generated at the junction surface of GaSb side. Figure 13 is a main-portion cut side view illustrating another embodiment of the present invention, in which the same symbols as used in Figs. 8 to 12 represent the same parts or have the same meaning. The difference between the present embodiment and the embodiment described with reference to Figs. 8 to 12 is that, in place of the n + -type InAs base layer 4, a superlattice consisting of n + -type InAs films 4A and n-type GaSb films 4B is employed. In this case, it is obvious that the semimetallic state is realized at each boundary surface of the InAs films 4A and the GaSb films 4B. The main data in the above-described superlattice are as an example as follows. (1) For the InAs film 4A Thickness: 150 [Å], the thickness may be between 100 Å and 200 Å n-type impurity: Si Concentration of impurity: 1 x 10 19 [cm -3 ] Number of films: 4 (2) For the GaSb film 4B Thickness: 100 [Å], the thickness may be between 100 Å and 200 Å n-type impurity: Te Concentration of impurity: 6 x 10 16 [cm -3 ] Number of films: 3 Figure 14 illustrates an energy-band diagram when bias voltages V BE and V BC are applied to the embodiment shown in Fig. 13, wherein the same symbols as used in Fig. 13 or in Fig. 7 represent the same parts or have the same meaning. As can be seen from Fig. 14, holes occupy mainly the area between the valence band edge of each GaSb layer and the Fermi level E FB of the base region, and electrons mainly occupy the area between the Fermi level E FB and the conductor band edge of each InAs layer, resulting in a reduced base resistance. Electrons injected from the emitter layer 6 are passed as hot carriers through the base layer consisting of the barriers of GaSb-InAs at the emitter side and at the collector side and the InAs-GaSb alternating layers, to the collector layer 2. Figure 15 is a main-portion cut side view illustrating still another embodiment of the present invention, wherein the same symbols as used in Figs. 8 to 14 represent the same parts or have the same meaning. In the figure, 20 represents an InP substrate, 21 an n + -type InGaAs collector layer, 22 an i-type Al x In 1-x As barrier layer, 23 an In x Ga 1-x As graded layer, 24A is an InAs film, 24B is a GaSb film, 25 is an In x Ga 1-x As graded layer, 26 an i-type AlInAs barrier layer, 27 an n + InGaAs layer, 28 a collector electrode, 29 an emitter electrode, and 30 a base electrode, respectively. The main data for each part in the present embodiment are exemplified as follows. (a) For the collector layer 21 Thickness: 5000 [Å] n-type impurity: Si Density of impurity: 1 x 10 19 [cm -3 ] (b) For the barrier layer 22 Thickness: 200 [Å] (c) For the graded layer 23 Value x: 0.47 → 1.0 (substrate - surface side) (d) For the InAs film 24A Thickness: 180 [Å], the thickness may be between 100 Å and 200 Å n-type impurity: Si Density of impurity: 1 x 10 19 [cm -3 ] Number of layers: 4 (e) For the GaSb film 24B Thickness: 180 [Å], the thickness may be between 100 Å and 200 Å Number of layers: 5 (f) For the graded layer 25 Thickness: 300 [Å] Value of x: 1.0 → 0.47 (GaSb side - AlInAs side) (g) For the barrier layer 26 Thickness: 200 [Å] (h) For the emitter layer 27 Thickness: 5000 [Å] n-type impurity: Si Density of impurity: 1 x 10 19 [cm -3 ] (i) For the collector electrode 28 Material: Ni·Au Thickness: 1000 [Å] (j) For the base electrode 30 Material: Au Thickness: 1000 [Å] In this embodiment also, it is obvious that a semimetallic state is realized at each heteroboundary surface as in the embodiment described with reference to Figs. 13 and 14. In addition, a tunnel barrier structure from the emitter layer 27 to the collector layer 21 is realized, as seen in Figure 16. Figure 16 illustrates an energy-band diagram of the embodiment shown in Fig. 15, wherein the same symbol as used in Figs. 8 to 15 represent the same parts or have the same meaning. Note that the solid lines in the regions 22 and 26 show the potentials thereof when bias voltages are not applied. In the figure, E 1 , E 2 and E 3 represent the electron-resonance levels, and H 1 , H 2 and H 3 represent the hole-resonance levels, respectively. The energy levels E 1 , E 2 , E 3 , H 1 , H 2 , H 3 are referred to as minibands. When the bias voltages V BE and V BC are not applied, the barrier layers 22 and 26 function as barriers for carriers. When the bias voltages are applied, the potentials at the barrier layers 22 and 26 are inclined so that carriers can pass therethrough by tunnelling. The carriers injected into the base layer having the InAs/GaSb/.../GaSb/InAs superlattice structure are passed through the minibands. Figure 17 shows a diagram for explaining miniband energies calculated by G. A. Sai-Halasz, L. Esaki and W. A. Harrison "Phys. Rev. B18 p. 2812, 1978" and so forth, wherein the same symbols as used in Fig. 16 represent the same parts or have the same meaning. In the figure, the horizontal axis represents the period of the superlattice and the vertical axis represents the energy. It is apparent that the energies in the minibands are a function of the period d of the superlattice. In the present embodiment shown in Figs. 15 and 16, a collector current flows when the injection energy of the electrons coincides with a miniband which is generated in accordance with the periodic structure of the superlattice. Therefore, a negative resistance is obtained due to the base-emitter voltage V BE . Figure 18 is a diagram illustrating the negative resistance of the embodiment described with reference to Figs. 15 to 17, wherein the horizontal axis represents the base-emitter voltage V BE and the vertical axis represents the collector current I C . The same symbols as used in Figs. 16 and 17 represent the same parts or have the same meaning. In the figure, the peak for the mini-electron band E 1 does not appear. This is because the mini electron band E 1 under a state in which the voltage is 0 is lower than the Fermi level of the emitter side. Note that, when the base emitter voltage V BE is negative, peaks will appear. In the semiconductor device according to the present invention, a three-terminal structure having a base region of semimetal is provided. By adopting the afore-mentioned structure, a semiconductor device having a high switching speed and a smaller Δε EB and Δε BC than the MBT and a smaller base resistance R B than the HET, can be realized.

Claims: A semiconductor device comprising: a first semiconductor layer (2) forming a collector layer, a second semiconductor layer (6) forming an emitter layer, a third semiconductor layer (4) forming a base layer sandwiched between said first and second semiconductor layers, a first electrode (7) in ohmic contact with said first semiconductor layer, a second electrode (8) in ohmic contact with said second semiconductor layer, a third electrode (9) in ohmic contact with at least said third semiconductor layer, a first barrier (5) layer provided between said third semiconductor layer (4) and said second semiconductor layer (6), for preventing an injection of carriers from said second semiconductor layer (6) to said third semiconductor layer (4) when a bias voltage is not applied between said third semiconductor layer (4) and said second semiconductor layer (6), and a second barrier layer (3) provided between said third semiconductor layer (4) and said first semiconductor layer (2), for preventing an injection of carriers from said first semiconductor layer (2) to said third semiconductor layer (4) when a bias voltage is not applied between said third semiconductor layer (4) and said first semiconductor layer (2), wherein at the interfaces between said first and third semiconductor layers (2 and 4, resp.) and between said second and third semiconductor layers (6 and 4, resp.), the energy level (E BC ) of the conduction band edge of said third semiconductor layer (4) is lower than the energy level of the valence band edge (E VE ,E VC ) of said first or second semiconductor layer (2 and 6, resp.), and wherein said third semiconductor layer (4) has a thickness sufficiently thin that at least at the interfaces between said first and third semiconductor layers (2 and 4, resp.) and between said second and third semiconductor layers (6 and 4, resp.), a semimetal layer is formed, and the third electrode (9) is in ohmic contact with the semimetal layers. A semiconductor device according to claim 1, wherein the interfaces between said first (2) and third (4) semiconductor layers and between said second (6) and third (4) semiconductor layers are heterojunctions. A semiconductor device according to claim 1, wherein said first (2) and second (6) semiconductor layers are GaSb layers, and said third semiconductor layer (4) is an InAs layer, the thickness of said InAs layer being from 100 Å (1 x 10 -6 cm) to 200 Å (2 x 10 -6 cm) A semiconductor device comprising: a base layer having at least three layers, forming a superlattice structure, including a first semiconductor material/second semiconductor material/first semiconductor material structure, outer layers in said structure being the first semiconductor material layers, the second semiconductor material layer in said structure having a thickness sufficiently thin that, at least at the interfaces between said first and second semiconductor material layers, a semimetal is formed, and the energy level of the conduction band edge of each said second semiconductor material layer is lower than the energy level of the valence band edge of each said first semiconductor material layer, an emitter layer (6) provided on one side of said structure, a collector layer (2) provided on the other side of said structure, a base electrode (9) provided to be in ohmic contact with at least the second semiconductor material layer in said structure, an emitter electrode (8) provided on and in ohmic contact with said emitter layer (6), a collector electrode (7) provided on and in ohmic contact with said collector layer (2), a first barrier (5) layer provided between said base layer and said emitter layer (6), for preventing an injection of carriers from said emitter layer (6) to said base layer when a bias voltage is not applied between said base layer and said emitter layer (6), and a second barrier layer (3) provided between said base layer and said collector layer (2), for preventing an injection of carriers from said collector layer (2) to said base layer when a bias voltage is not applied between said base layer and said collector layer (2). A semiconductor device according to claim 4 wherein said first semiconductor material is GaSb, said second is InAs, said base layer has at least three layers (2, 3, 4, 5) inculding a GaSb/InAs/GaSb structure, outer layers in said GaSb/InAs/GaSb structure are GaSb layers, the InAs layer (4) in said GaSb/InAs/GaSb structure has a thickness of between 100 Å (1 x 10 -6 cm) to 200 Å (2 x 10 -6 cm) so that said GaSb/InAs/GaSb structure has a characteristic of a semimetal, whereby, by applying a voltage between said emitter electrode (8) and said base electrode (9), carriers injected from said emitter layer (6) are passed through said base layer as hot carriers to said collector layer (2). A semiconductor device according to any of claims 4 to 5, wherein said base electrode (9) is in ohmic contact with the semimetal layer in said first/second/first structure. A semiconductor device according to any of claims 4 to 6, wherein said emitter layer (6) and said collector layer (2) are first layers. A semiconductor device according to any of claims 4 to 7, wherein the conductivity type of said first/second/first structure are n-n-n. A semiconductor device according to any of claims 4 to 7, whrein the conductivity type of said first/second/first structure is p-p-p. A semiconductor device comprising: a base layer having at least three layers, forming a superlattice structure, including a second semiconductor material/first semiconductor material/second semiconductor material structure, outer layers in said structure being second semiconductor material layers, the first semiconductor material layer in said structure having a thickness sufficiently thin that, at least at the interfaces between said first and second semiconductor material layers, a semimetal is formed , and the energy level of the conduction band edge of each said first semiconductor material layer is lower than the energy level of the valence band edge of each said second semiconductor material layer, an emitter layer (6) provided on one side of said structure, a collector layer (2) provided on the other side of said structure, a first barrier layer (5) provided between said base layer and said emitter layer (6), for preventing an injection of carriers from said emitter layer (6) to said base layer when a bias voltage is not applied between said base layer and said emitter layer (6), a second barrier layer provided between said base layer and said collector layer (2), for preventing an injection of carriers from said collector layer (2) to said base layer when a bias voltage is not applied between said base layer and said collector layer (2), a base electrode (9) provided to be in ohmic contact with at least the second semiconductor material layer in said structure, an emitter electrode (8) provided on and in ohmic contact with said emitter layer (6), and a collector electrode (7) provided on and in ohmic contact with said collector layer (2). A semiconductor device according to claim 10, wherein said first semiconductor material is GaSb, said second is InAs, said base layer has at least three layers including a InAs/GaSb/InAs structure, outer layers in said InAs/GaSb/InAs structure are InAs layers, each InAs layer in said InAs/GaSb/InAs structure has a thickness of between 100 Å (1 x 10 -6 cm) to 200 Å (2 x 10 -6 cm) so that said InAs/GaSb/InAs structure has a characteristic of a semimetal. A semiconductor device according to claim 4, 10 or 11, wherein, when a voltage is applied between said emitter electrodes (8) and said base electrode (9) carriers are injected from said emitter layer (6) through said first barrier layer (5) by tunneling to said base layer and are passed through minibands in the base layer. A semiconductor device according to claim 11 or 12, wherein said first and second barrier layers (5 and 3, resp.) are AlInAs layers.

Inventors: AWANO YUJI, AWANO, YUJI, AWANO, YUJI HIGHCITY OMOTESANDO 312
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H01L29
IPC codes: H01L29