Shared memory controller arrangement

Abstract: A shared memory controller arrangement is disclosed wherein a number of local memories are primarily dedicated to the shared use of a number of local processors to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected hereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Description: Field of the Invention This invention relates to data processing systems and more particularly to logic for allowing a plurality of processors to share a plurality of memories primarily used by the processors. Background of the Invention In the prior art, memory access arrangements are taught but they all have shortcomings. In one arrangement, a single memory is dedicated to and accessed by a single processor. While this speeds read/write access time by the processor to its dedicated memory, the efficiency of use of the memory is low. For systems having more than one processor, other memories must also be provided, and each processor is limited to accessing only it's own memory. This requires much memory and is expensive. Another approach is to have one common memory connected to a bus and the memory is accessed by two or more processors. While less memory needs to be provided, and efficiency of use of the common memory increases, very often more than one processor wants to access the common memory at the same time. This causes one or more of the processors to wait which decreases their efficiency of use. To overcome this problem cache memories are provided for each processor, as is known in the art, but this increases both circuit complexity and cost. A multi-processor configuration using a shared store module for inter-process communication is described in an article "Intercommunication in Multimodule Systems", by R.L. Grimsdale, in the Proceedings of the IMACS (AICA)-GI Symposium "Parallel Computers - Parallel Mathematics", Munich, March 14-16, 1977; North-Holland, Amsterdam 1977, pp. 283-286, in particular, Fig. 4. Data within said shared store module normally remains for its lifetime in the system and is successively accessed by processes executed by several processors of the system. Thus, facilities must be provided for the processors to gain access to the shared store module. Each processor is equipped with a Store Access Controller (SAC) which provides access by the processor to one or more shared memory buses. The memory bus is under the control of the Store Management Unit (SMU) which also regulates the access to shared data structures. The SAC provides access to the common memory buses and performs store mapping and protection functions and provides a virtual machine for each of the processes which run on the associated processor. Each shared store module has associated therewith its own single shared memory bus. The SACs provide access for its respective processor to all of the shared memory buses. Thus, a separate bus is required for each shared store module. The processors gain access to a shared memory module by being coupled via the respective SAC to the one selected single memory bus. A processor can gain access to any one of the shared store modules by being selectively coupled via its respective SAC to any one of the plurality of the separate memory buses. This multi-processor system configuration with such plurality of separate memory buses for each store module is quite expensive and complex in its hardware implementation so that there is still a need in the art for an improved and less expensive multiple processor, multiple shared memory arrangement wherein each of the processors can access any one of the memories without preventing another processor from accessing another of the memories at the same time. It is therefore the object of this invention to provide an improved shared memory controller arrangement which is less expensive in its hardware implementation. SUMMARY OF THE INVENTION The above object is achieved in a shared memory controller arrangement in a data processing system according to the characteristic features of claim 1. Further advantageous embodiments may be taken from the subclaims. The present invention provides a multiple shared memory arrangement wherein multiple processors can individually and concurrently access any one of the memories. This operation maximizes processor and memory use and efficiency and each processor has access to all of the shared memories even if not to all of them at the same time. Each of the shared memories has a memory controller associated with it and there is a switch arrangement between the processors and the memory controllers. The switch arrangement permits concurrent access between any one of the processors and any one of the memory controllers. The one limitation is that two processors cannot access the same memory at the same time. A processor that is connected to a particular memory controller is then connected via the switching arrangement to a memory associated with the particular controller. Read and write operations from and to the memory associated with each controller are accomplished in a manner known in the art. Each memory controller may be alternatively connected via the associated adapter circuit to the system bus on which they may read or write the other storage circuits in a manner well known in the art. Any one of the multiple processors connected to any one of the memory controllers may request and be alternately connected via an associated adapter circuit to the system bus on which they may read or write the other storage circuits in a manner well known in the art. System processors may access any one of the multiple processors via the adapter circuits. In addition, any one of the system processors connected to the system bus may request and be alternatively connected via any one of the adapter circuits to a memory controller and its associated memory. Description of the Drawing The invention will be better understood upon reading the following detailed description in conjunction with the drawing in which: Figure 1 is a block diagram of a portion of a computer system showing how the present invention connects thereto; and Figure 2 is a detailed block diagram schematic of a memory controller and memory; Figure 3 is a representation of a tie breaker circuit deciding access to a memory controller from competing circuits; Figure 4 is a block diagram of a control signal generator used to control operations in a memory controller; and Figure 5 is a table showing the correlation between input signals and output signals that can be used to program a programmable arithmetic logic circuit in the control signal generator. Detailed Descriptions In Figure 1 is shown a block diagram of a portion of a computer system in which the shared memory controller arrangement is utilized. Standard computer system elements are processor 10, processor 11, system bus 12, system memory 13, disk input/output device 14 and system processor 15. In the prior art processors 10 and 11 would normally be connected to system bus 12 along with system processor 15 and they would cooperate in a multiprocessing arrangement to process application programs, with processor 15 being a master processor, in a well known manner. In accordance with the teaching of the present invention the two memories 17 and 19 are dedicated to the joint use of application-program processors 10 and 11 to increase their operating efficiency, and to increase the efficiency of use of memories 17 and 19. Memories 17 and 19 are respectively associated with memory controller 16 and memory controller 18 which control access to the memories. Processors 10 and 11 are not connected directly to system bus 12, but rather are connected to a local bus 9. Memories 17 and 19 are also not connected to the system bus 12. Also connected to local bus 9 are the memory controllers 16 and 18. Memory controllers 16 and 18 primarily permit shared access to their respective associated memories 17 and 19 by either processor 10 or processor 11. In this manner the chances of either processors 10 or 11 having to wait to gain access to a memory are statistically decreased compared to one memory serving both processors. Memories 17 and 19 may also be accessed from system bus 12 via adapters 20 and 21 respectively to load application programs and data to be processed into these memories for subsequent use by processors 10 and 11. Similarly, memories 17 and 19 may be read out to circuits connected to system bus 12. In addition, processors 10 and 11 each have access via memory controllers 16 and 18 and adapter circuits 20 and 21 respectively connected thereto to system bus 12 to gain access to other storage circuits connected thereto such as system memory 13 and disk I/O 14. The circuit details of an exemplary memory controller 16 and a memory 17 are shown in Figure 2 which is described further in this specification. There are four basic types (A, B, C and D) of memory read and write transactions that can be performed by the invention working in the system configuration shown in block diagram form in Figure 1. In transaction type A processor 10 may read or write to memory 17 associated with memory controller 16, processor 11 may read or write to memory 19 associated with memory controller 18, processor 10 may read or write to memory 19 associated with memory controller 18, and processor 11 may read or write to memory 17 associated with memory controller 16. Access between processors 10 and 11 and memory controllers 16 and 18 for these type A transactions is via local bus 9 and switches that are part of memory controllers 16 and 18 and shown in Figure 2. These type A transactions never access other storage circuits connected to system bus 12. There are also type B transactions wherein some circuits connected to system bus 12, such as system processor 15, may request and gain access to memories 17 and 19 to write programs or data therein for use by processors 10 and 11, or to read processed data from these memories. A type B transaction request to access memory 17 associated with memory controller 16 is always made via (recognized by) adapter 20, and a request to access memory 19 associated with memory controller 18 is always made via (recognized by) adapter 21. With type C transactions, processors 10 and 11 can read or write system memory 13 or other circuits connected to system bus 12. To implement this type of transaction processor 10 must access only memory controller 16, and processor 11 must access only memory controller 18. When memory controller 16 is seized by processor 10, controller 16 determines if a memory or non-memory address received from processor 10 is to memory 17 and further determines if memory 17 is to be accessed. Upon determining that memory 17 is not to be accessed, memory controller 16 forwards the read or write request via adapter 20 to system bus 12. After memory controller 16 passes a read request to adapter 20 to be placed on system bus 12, memory controller 16 is not free to service other read or write requests until the read operation to, for example, system memory 13 is completed. Write operations to, for example, system memory 13 are considered completed as soon as the request, address and data are passed to adapter 20, and memory controller 16 can then process other read or write requests from either processor 10 or 11. When the type C transaction request is a read operation, the program or data will be returned, and can only be returned over the same path that the request is made on. In addition, when adapter 20 receives the returned program or data it must make an access request to memory controller 16. That request is granted an appropriate connection is established through memory controller 16 and adapter 20 returns the data or program to processor 10. Thereafter, processor 10 is again free to request memory read or write operations from controllers 16 or 18. Similarly, processor 11 can access system memory 13 or other system circuits via its associated memory controller 18 and adapter 21. The D type transaction is a lock cycle transaction wherein, for example, processor 10 can perform a read lock of either memory 17 or memory 19, but the read operation is not done directly through memory controller 16. The lock operation, when called for, assures that the addressed memory from one processor will not acknowledge a bus cycle initiated by another processor until the first processor operation is completed. Assuming processor 10 wants to do a read lock on memory 17, the address and read request sent to memory controller 16 is not used to read memory 17, but instead is passed to adapter 20. Adapter 20 places the read request and address on system bus 12 and then recognizes that the address is to memory 17. Adapter 20 answers the request it just placed on bus 12 and receives the read request and address. Then adapter 20 makes a request for connection to memory controller 16 and memory 17. When that request is granted, reading of memory 17 takes place. The information read out of memory 17 is returned to adapter 20 rather than to processor 10. Adapter 20 takes the information read out of memory 17 and destination and places it on system bus 12. Adapter 20 then recognizes that the information it just placed on bus 12 is for processor 10 and re-captures the information. Adapter 20 again makes a request for use of controller 16. When this request is granted, adapter 20 returns the information via memory controller 16 and local bus 9 to processor 10. Similarly, if processor 10 requests a read lock operation to memory 19, the read request and address are passed via memory controller 16 and adapter 20 to system bus 12 as described in the last paragraph. However, adapter 21 recognizes that the read request is for memory 19 and takes the request and address from system bus 12. Adapter 21 makes a request to memory controller 18 to read memory 19, and when the request is granted memory 19 is read. Like the read lock operation described in the last paragraph, the information read out of memory 19 is returned through memory controller 18 and adapter 21 to system bus 12. Adapter 20 recognizes that the information on system bus 12 is for processor 10 and stores the information. Adapter 20 then makes a request for use of memory controller 16. When this request is granted, adapter returns the information via controller 16 and local bus 9 to processor 10. While the type D read lock operation described in the last two paragraphs is initiated by processor 10 to either memory 17 or memory 19, processor 11 can also request read lock operation to memories 17 and 19 and the operation is the same as that described in the last two paragraphs. Furthermore, since the lock request is placed on system bus 12, a lock request of system memory 13 is performed in a manner transparent to processor 10. In Figure 2 is shown detailed block diagram schematic of a memory controller 16 and an associated memory 17. Since controller 16 with memory 17 is the same as memory controller 18 with memory 19, only the schematic of memory controller 16 and memory 17 are shown in Figure 2 and are described hereinafter. Around the edges of the portion of Figure 2 identified as memory controller 16 are shown three input/output connections to processor 10, to processor 11, and to adapter 20 which are shown in Figure 1. Each of these three connections can carry information in both directions as previously described with reference to Figure 1. In addition, the connections between controller 16 and associated memory 17 are shown. The three connections identified in the beginning of this paragraph are all connected to a switching network implemented with buffer amplifiers 26 through 33. The data paths within memory controller 16 are mostly thirty-two bit paths as indicated by the slash mark and the number thirty-two adjacent thereto. Accordingly amplifiers 26 through 33 each respectively represent thirty-two amplifiers. Each of the two-hundred fifty-six individual amplifers represented by amplifers 26 through 33 are a 74S241 Tri-State Octal Amplifier operated as a buffer driver in a manner well known in the art. They are available from Texas Instruments and other sources. The other circuits within memory controller 16 are word selector 37 which has two sixteen bit inputs and a thirty-two bit output. Word selector 37 is made up of eight Quad 2:1 Multiplexer chips designated 74A5157 which are also available from Texas Instruments and other sources. Each of these chips is a four pole double throw switch. Word selector 37 is used to reverse or transpose the two groups of sixteen input bits at the output. That is, the sixteen bits at the input from path 39 may be either the lower order sixteen bits or the higher order sixteen bits of the thirty-two bit output from translator 37. Similarly, the sixteen bits at the input of translator 37 from path 40 will be the remaining sixteen of the thirty-two bits output from translator 37. More detail of how this is accomplished is described further in this specification. Circuitry analogous to buffer amplifers 26 through 33 provide paths for thirty-two address bits to/from processor 10, processor 11 or adapter 20. At the output of memory controller 16 to memory 17 are two 2:1 multiplexers 35 and 36. Multiplexers 35 and 36 are each made up of a number of 74AS257 multiplexers having tri-state outputs. That is, the output may be high, low or open. Each of multiplexers 35 and 36 have thirty-two input bits and sixteen output bits. These 2:1 multiplexers 35 and 36 are used to selectively choose which of the higher order sixteen bits or lower order sixteen bits are to be applied to the even memory 51 and odd memory 52 in memory 17. In an alternative embodiment of the invention memory 17 may be a single memory instead of two smaller memories. In the following paragraphs are described the routing of data words within memory controller 16. The described operations are the type A-D transactions mentioned previously. After the routing of the data is described, the generation of the CS control signals used to operate the buffer amplifier switches within memory controller 16 is described with reference to Figures 3, 4 and 5. When processor 10 requests and gains access to memory controller 16 for a read operation from memory 17, an address is sent that is first checked. If the address is not in the address range of memory 17, or is used in a lock operation, read access is not granted. Otherwise, read access is granted. In response thereto a thirty-two bit word is read out of memory 17 and input to memory controller 16 as sixteen bits on path 39 to one input of word selector 37 and sixteen bits on path 40 to the other input of word selector 37. In response to a control signal CS input to word selector 37 the two sets of sixteen input bits are selectively connected to the higher order or lower order sixteen-bits of the thirty-two bit output from word selector 37. The output from word selector 37 is connected to a thirty-two bit MUXD bus 38 to which also are connected the inputs of buffer amplifier switches 27, 31 and 32. For the read operation from memory 17 a control signal CS2 is generated which operates the thirty-two individual amplifiers making up buffer amplifier 27. This connects the thirty-two bit word read from memory 17 to input/output path 53 to be returned to processor 10. Alternatively, if processor 10 is writing to memory 17, a thirty-two bit word is presented on input/output path 53. A control signal CS1 is generated which operates the thirty-two individual amplifiers making up buffer amplifier 26. Thus, the thirty-bit word on input/output path 53 is connected to MDTI bus 34. Multiplexers 35 and 36 have their inputs connected to MDTI bus 34 and control signals are applied to them to select which of the higher order and lower order sixteen-bits of the thirty-two bit word on bus 34 will pass through 2:1 multiplexers 35 and 36 and be stored in even memory 51 and odd memory 52 of memory 17. In an operation where processor 11 requests and gains access to memory controller 16 to read from memory 17, the thirty-two bit word read out of memory 17 appears as sixteen-bits on path 39 and sixteen-bits on path 40. As described above these two sets of sixteen bits are selectively transposed by word selector 37 and are present on MUXD bus 38. A control signal CS4 is generated which operates each of the thirty-two amplifiers making up buffer amplifier 32 to connect the thirty-two bit word read out of memory 17 to input/output 54 path and on to processor 11. If instead processor 11 is writing to memory 17, after the processor requests and gains access to memory controller 16, a control signal CS3 is generated which operates each of the individual amplifiers comprising buffer amplifier 33 and connects the thirty-two bit word to be written into memory 17 to MDTI bus 34. As previously described other control signals operate 2:1 multiplexers 35 and 36 to selectively apply the higher order and lower order sixteen-bits of the word to be stored to even memory 57 and odd memory 52 of memory 17. In a type B transaction a circuit connected to system bus 12, such as system processor 15 or system memory 13, requests access to memory 17 to either read data from this memory, or to store other data or programs in this memory for use by processor 10 in future processing. When system processor 15 wants to write into memory 17, it first gains access to adapter 16 or 18 and transmits to it information to be written and an address in memory 17. Adapter 20 in turn requests access to memory controller 16 to write into memory 17. When this request is granted, a control signal CS7 if generated which operates the thirty-two amplifiers making up buffer amplifier 30. A thirty-two bit word from adapter 20 present an input/output path 55 is thereby connected to MDTI bus 34. As previously described 2:1 multiplexers 35 and 36 are operated to selectively place the higher order and lower order sixteen bits of the thirty-two bit word from adapter 20 into even memory 51 and odd memory 52. To read memory 17 to adapter 20 and thence to a circuit connected to system bus 12, memory 17 is addressed and read out via paths 39 and 40, and work selector 37 to MUXD bus 38. Control signal CS8 is generated that enables the thirty-two amplifiers making up amplifier 31 to connect the thirty-two bit word read out to input/output 55 path and via adapter 20 to system bus 12. In an operation where processor 10 requests and gains access to memory controller 16 to be connected via adapter 20 and system bus 12 to other storage circuits, such as system memory 13, different control signals are generated. When this type C transaction is a write operation, control signal CS5 operates buffer amplifiers 28, and the data word present at input/output 53 is passed through to input/output path 55 and to adapter 20. As previously described adapter 20 will gain access to system bus 12 and will store the data word from processor 10 in the requested storage circuit. In a type C transaction where processor 10 is reading from a storage circuit, such as system memory 13 connected to system bus 12, processor 10 first requests and then gains access to memory controller 16. The connection to adapter 20 is the same as described in the last paragraph and the read request and address are passed to adapter 20. The connection between processor 10 and memory controller 16 is then broken. As previously described, controller 16 can now handle read/write requests from processor 11, but processor 10 cannot request any other read or write operations with controller 16, or controller 18 until the present read operation from a system storage circuit on system bus 12 is completed. When the read operation requested by processor 10 has been accomplished by adapter 20, this adapter makes a request for access to memory controller 16 and indicates that it needs a connection to processor 10. When the access request by adapter 20 is granted, a control signal CS6 operates buffer amplifiers 29. This passes a data word on input/output path 55 from adapter 20 directly to input/output path 53 and thence to processor 10. Type C transactions involving processor 11 are not handled by controller 16; instead, processor 11 uses controller 18 to access adapter 21. The details of such type C transactions involving processor 11 are indentical (except for the designations) to those outlined in the previous two paragraphs. Thirty-two bit word memory 17 is made up of two sixteen-bit memories 51 and 52 in the preferred embodiment of the invention. However, a single thirty-two bit word memory may also be used with minor changes in the error circuit which is well known in the art. Memory 51 is the even memory and memory 52 is the odd memory as described previously. Data or program instructions to be stored in even memory 51 are switched through memory controller 16 to even data bus 41, and then over path 43 to the input of even memory 51. Memory 51 also has an address applied thereto and a read/write indication that are not shown but which are well known in the art. The operation of memory 51 in response to such signals is also well known in the art. When memory 51 is being read rather than written, there is no data on path 43. Information read out of even memory 51 is twenty-two bits wide, sixteen bits of which are the information of interest, and six bits of which are an error correction code. The sixteen information bits read out of even memory 51 are connected to the inputs of buffer amplifier 45. Amplifier 45 is made up of sixteen individual amplifiers, and are implemented with Fairchild 74F373 Tri-State Octal Registers operating as buffer amplifiers. Buffer amplifier 45 is controlled by control signal CS9, which is generated and applied to amplifier 45 only when even memory 51 is read out. The six error correction bits read out of even memory 51 during a memory read operation are input to error circuit 47. The sixteen information bits read out of even memory 51 are switched through buffer amplifier 45 to even data bus 41 and are input via path 56 to error circuit 47. This makeup of sixteen information bits and six error correction bits is a standard 16/6 Hamming code that is well known in the art. Error circuit 47 is an AMD2960 error correction and detection chip available from American Micro-Devices, and is operated in a standard manner. Error circuit 47 processes the sixteen bit data word present at its input to check for and correct errors in the sixteen bits, if at all possible. The checked and/or corrected sixteen bit information word is output from error circuit 47 back onto path 56 to even data bus 41. This information word then flows from bus 41 onto path 39 back into memory controller 16 to word selector 37 as previously described. While the memory circuit operation described in the previous paragraphs is for even memory 51, the same described operation applies to odd memory 52. Accordingly, the operation is not again repeated with reference to odd memory 52. In Figure 3 is shown a simple block diagram of a tie breaker circuit 58. There are two tie breaker circuits, one associated with each of memory controllers 16 and 18. Tie breaker circuit 58 shown in Figure 3 is associated with processor 10. That is, in Figure 3 the lowest priority request is from processor 10, but in the second tie breaker circuit (not shown) the lowest priority request is from processor 11. In addition, the A and B suffixes on the A and B request and grant signals are reversed. That is, for example, an Adapter A request becomes an Adapter B request. Tie breaker circuit 58 is well known in the art and is taught in U.S. patent 4,493,036, having the same assignee as the present invention. The material in this earlier patent is not repeated herein to avoid detracting from the present invention, and because it does not form part of the invention. The description of the tie breaker circuit 58 shown in Figure 3 is made with this circuit being assigned to grant requests for access to memory controller 16. There are four request inputs to tie breaker 58. They are a P10 request from processor 10, a P11 request from processor 11, an Adapter A request from adapter 20, and a Refresh request. Even though circuit 58 is associated with processor 10, processor 10 is assigned the lowest priority access to memory controller 16. The highest priority is assigned to the Refresh request. Memory 17 is an NMOS memory, well known in the art, and in operation charge slowly leaks off and must be replaced or refreshed or the contents of memory 17 are lost. Since it cannot be permitted to lose the contents of memory 17, its contents are periodically refreshed. A memory refresh circuit is not shown or described since they are well known in the art, but a refresh request from same receives the highest priority to access memory controller 16 and refresh memory 17. Adapter 20 is assigned the second highest priority to access memory controller 16. This higher priority is assigned because on a relative basis adapter 20 is seldom requesting access to memory controller 16, but when it does it needs priority access to place programs or data in memory 17 for use primarily by processor 10, or to read the results of previous processing from memory 17. Similarly, processor 11 seldom requests access to memory controller 16 when compared to access by processor 10 so it has been given a higher priority than processor 10. In operation of tie breaker 58, when memory controller 16 is idle the first of the four requests to appear at the inputs of circuit 58 is immediately granted. However, if two requests from a first and a second circuit appear simultaneously, the request from the circuit having the higher priority is first granted access to memory controller 16. When the first circuit to which the access has been granted is finished with a read or write operation the request from the second circuit is granted. If while the first circuit has access to memory controller 16 a third circuit requests access to controller 16, tie breaker circuit 58 will then select between the second and third circuits requesting access and the one of these two circuits having the higher priority will be granted access to memory controller 16 following the first circuit. There is also an End of Cycle input to tie breaker circuit 58 which has a signal from a system clock or timing circuit, not shown but well known in the art, which indicates the end of the current memory controller cycle. This timing signal restarts circuit 58 to make another decision and grant access to memory controller 16 if any requests are awaiting service. Whichever access requesting circuit is granted access to memory controller 16 by tie breaker circuit 58, it has its associated Request Granted output lead go high. For example, if processor 10 requests connection to memory controller 16 and the request is granted, the Processor 10 Granted output from tie breaker circuit 58 goes high. The request granted outputs from tie breaker circuit 58 are input to a control signal generator circuit shown in Figure 4. Although not specifically shown in Figure 3, the request granted outputs from tie breaker circuit 58 are also connected back to their respective access requesting circuits so that the requesting circuits receive an indication when their request is granted and they are connected to memory controller 16. In Figure 4 is shown the control signal generator circuit which responds to the access granted signals output from tie breaker circuit 58 to generate CS control signals that operated the switching buffer amplifiers shown in Figure 2 and described previously in this specification. There is a control signal generator circuit associated with each memory controller, and the circuit shown in Figure 4 is associated with memory controller 16. The control signal generator comprises an equality detector 60 and a programmable array logic (PAL) circuit 59. In addition to the inputs from tie breaker circuit 58, there is also a R/W operation input on which is a signal indicating if a read or a write operation is to performed on memory 17 or another storage device connected to system bus 12 in Figure 1. There is also a Non-Memory Operation input that indicates if the requested read or write operation involves memory 17 or one of the other system storage devices. Finally, there is a valid address input from equality detector 60 that indicates if the memory address forwarded to memory controller 16 can be used to address memory 17. Path selection in memory controller 16 is by means of CS enable signals generated by circuit 59. More specifically, equality detector 60 is a 74F521 equality detector comparator available from Fairchild Semiconductor. The PAL is available from numerous sources and is programmed to provide outputs for specified input signal combinations in a manner well known in the art. The input and output signal relations are shown in Figure 5 and permit programming of PAL 59 to implement the control signal generator. One input to detector 60 is the memory address from processor 10. The other input to detector 60 indicates the range of addresses that can be addressed in memory 17 and can be supplied by settings on DIP switches as is well known in the computer art. Detector 60 compares an address from processor 10 with the range of addresses of memory 17. If the address from processor 10 is within range, there is an appropriate output from detector 60 indicating same. However, an output from detector 60 indicating that the address is in range or valid doesn't alone mean a read or write operation will be performed with memory 17. The address may also be valid for a storage device such as Disk I/O 14 connected to system bus 12 in Figure 1. Accordingly, the control signal generator also needs another input indicating if the requested read or write operation is to involve memory 17. The other input is the Non Memory Operation input which has an indication thereon only if the read or write operation involves memory 17. The lack of an indication on the non Memory Operation input or the lack of an Address OK signal from detector 60 indicates that the requested operation is to another storage device connected to system bus 12. When processor 11 requests and receives access to memory controller 16, the address it forwards is not checked because processor 11 can never establish a connection through memory controller 16 and adapter 20 to perform a read or write operation involving a storage device connected to system bus 12. In Figure 5 is shown a logic table showing the state of inputs to the control signal generator (PAL) 59 to get the indicated CS control signals that are used to operate the switching buffer amplifiers shown in Figure 2. This information enables one skilled in the art to program PAL 59. While what has been described hereinabove is the preferred embodiment of the invention, it should be understood that memory 17 may be a single memory rather than the even or odd memories disclosed. In addition, the number of processors, memory controllers and memories may be increased.

Claims: Shared memory controller arrangement in a data processing system having a system processor (15) and a system memory (13) coupled to a system bus (12), said system bus providing access to said system memory by said system processor and by other units coupled to said system bus; a plurality of further processors (10, 11), and a further memory (17, 19) associated with each further processor; apparatus for providing access to all of said memories by all of said processors, characterized by : a memory controller (16, 18) associated with and controlling access to each of said further memories; each of said controllers selectively coupling all of said further processors for access to its associated further memory; each of said controllers being coupled to the system bus by an adapter (20, 21) thereby providing access to the system memory for any one of said further processors; each of said controllers providing access to the one further memory associated therewith for any one of said processors to read data from or write data into said one further memory. The shared memory arrangement in accordance with claim 1 wherein each of said memory controllers comprises: a plurality of first switching means, one of said first switching means being associated with each of said plurality of further processors, and ones of said first switching means being operable to selectively connect its associated processor to the one of said plurality of further memories associated with said memory controller to pass information read out of said associated memory to a connected processor; and a plurality of second switching means, one of said second switching means being associated with each of said plurality of further processors, and ones of said second switching means being operable to selectively connect its associated processor to the one of said plurality of further memories associated with said memory controller to pass said information to be written to said associated memory. The shared memory arrangement in accordance with claim 2 wherein each of said memory controllers further comprises: third switching means that is selectively operable to connect said system processor to the one of said plurality of further memories associated with said memory controller to read information out of said associated memory. The shared memory arrangement in accordance with claim 3 wherein each of said memory controllers further comprises: fourth switching means that is selectively operable to connect said system processor to the one of said plurality of further memories associated with said memory controller to write information into said associated memory. The shared memory arrangement in accordance with claim 4 wherein each of said memory controllers further comprises: fifth switch mean that is selectively operable to connect ones of said plurality of further processors to said system bus to forward information to circuits connected thereto. The shared memory arrangement in accordance with claim 5 wherein each of said memory controllers further comprises: sixth switch means that is selectively operable to connect one of said plurality of further processors that is connected to said memory controllers directly to said system bus to receive information therefrom. The shared memory arrangement in accordance with claim 6 wherein each of said memory controllers further comprises: priority means monitoring requests by ones of said plurality of further processors to be connected to said memory controller to select on a priority basis only one of a number of said plurality of further processors at a time that are concurrently request access to said memory controller for connection to either said associated one of said plurality of further memories or to said system bus. The shared memory arrangement in accordance with claim 7 wherein each of said memory controllers further comprises: means for generating control signals for operating all said switch means. The shared memory arrangement in accordance with claim 8 wherein said control signal generating means comprises: detector means comparing a range of addresses indicating locations in the one of said plurality of said further memories that is associated with said memory controller that can be addressed with addresses received from ones of said further processors that are connected to said memory controller to determine if the received addresses are in said range of addresses, and when said received addresses are not in range said memory controller knows that said associated memory is not be read or written into and only said fifth or said sixth switches means will be operated. The shared memory arrangement in accordance with claim 9 wherein said control signal generating means further comprises: logic means responsive to signals from said detector means and from said priority means to generate said control signals for operating all said switch means. The shared memory controller arrangement of claim 1, further characterized by a local bus (9) connecting all of said further processors to all of said controllers.

Inventors: IZBICKI KENNETH J, LEMAY RICHARD A, WALLACE DAVID A, WOODS WILLIAM E, IZBICKI, KENNETH J., LEMAY, RICHARD A., WALLACE, DAVID A., WOODS, WILLIAM E.
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS INC.
Application year: 1988
Main classification: G06F13
IPC codes: G06F13, G06F15