DEPOSITION OF AMORPHOUS SILICON FOR THE FORMATION OF INTERLEVEL DIELECTRICS IN SEMICONDUCTOR MEMORY DEVICES

Abstract: A new and improved method using the deposition of amorphous silicon for the formation of semiconductor memory device interlevel dielectrics. After the deposition of a first polysilicon layer (18), an amorphous silicon layer (20) is deposited thereon. The polysilicon layer (18) and amorphous silicon layer (20) are etched to form a floating gate (22). The amorphous silicon layer (20) allows for the growth of thermal oxide layers (28) to take place at lower temperatures thereby decreasing the temperature at which the oxide layers are grown while still repressing the asperity formation. This allows for high quality oxide insulation layers.

Description: Background of the Invention This invention generally pertains to the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices. Generally, in semiconductor memory devices such as EEPROMs and EPROMs, it is desirable to insulate polysilicon layers in these multiple polysilicon layer memory structures. To do this, thermal oxide layers are generally grown between polysilicon layers. Commonly, the thermal oxide layers are grown at extremely high temperatures (1100-1150 degrees centigrade) or the oxidation occurs in an oxygen starved environment. This is done so that the asperity formation is greatly reduced. However, high temperature and oxygen starved (diffusion limited oxidation) degrade the tunnel oxide and interlevel oxide respectively. This in turn compromises the endurance and data retention respectively. Therefore, a method which reduces the interlevel oxidation temperature thereby reducing the degradation of the tunnel oxide without compromise to the interlevel oxide is highly desirable. In the memory device described in Patent Abstracts of Japan, vol.10, No. 32 (E-379)(2089) and JP-A-60 189971, an interlevel gate oxide having improved insulating characteristics is obtained by growing the interlevel oxide on a floating gate consisting of amorphous silicon. The layer of amorphous silicon is doped by ion implantation through a deposited insulating layer, prior to the growth of the interlevel gate oxide. Summary of the Invention In accordance with the present invention there is provided a method of making a semiconductor memory device comprising the steps of: providing a silicon wafer; isolating an area on said silicon wafer and defining a well thereon; growing a first oxide layer on said well; depositing a first polysilicon layer on said silicon wafer including said well and said first oxide layer; doping said first polysilicon layer; depositing an amorphous silicon layer on said doped first polysilicon layer; defining and etching said first oxide layer, said doped first polysilicon layer and said amorphous silicon layer to form a floating gate in said well; implanting a source and a drain; growing a second oxide layer on said well including said floating gate; depositing a second polysilicon layer on said second oxide layer; doping said second polysilicon layer; and defining and etching said doped second polysilicon layer. The present invention pertains to the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices. After the growth of a first oxide layer and the deposition and doping of a first polysilicon layer, a layer of amorphous silicon is deposited. This amorphous silicon serves many functions. It allows for the growth of interlevel oxide to occur at lower temperatures. In turn, the tunnel oxide layer is not severely degraded in quality. This enables the tunnel oxide to be a high quality insulator. The quality of the tunnel oxide is the major factor in endurance characteristics. Therefore, improvements in the tunnel oxide will result in improved endurance. Additionally, the amorphous silicon is smooth and is not susceptible to asperity formation which degrades the insulator properties of the interlevel oxide. Asperities in turn cause a thinner oxide layer at the points where the polysilicon is irregular. In the present invention, this geometrically enhanced field is repressed. It is an object of the present invention to provide a new and improved method using the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices which allows for superior insulation quality in the oxide layers. It is a further object of the present invention to provide a new and improved method using the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices which allows the thermal oxide layers to be grown at relatively low temperature. It is a further object of the present invention to provide a new and improved method using the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices which represses asperity formation. It is further object of the present invention to provide a new and improved method using the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices having electrically programmable memories with dual gates. These and other objects and advantages of this invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings. Brief Description of the Drawings Referring to the drawings, wherein like characters indicate like parts throughout the figures: FIG. 1 is an enlarged cross-sectional view of an isolated well disposed in a silicon wafer; and FIGS. 2-8 are highly enlarged cross-sectional views of a semiconductor memory device during various stages of processing in accordance with the present invention. Description of the Preferred Embodiments Referring specifically to FIG. 1, an enlarged cross-sectional view of a section of a silicon wafer, 10, is shown. Silicon wafer 10 is shown having a well, 12, which is disposed on silicon wafer 10. Well 12 of silicon wafer 10 is isolated from other areas of silicon wafer 10 by field isolation oxide 14. It should be understood that the following processing steps all occur in well 12 of silicon wafer 10. Referring specifically to FIGS. 2-8, highly enlarged cross-sectional views are shown of a semiconductor memory device during various stages of processing. Once well 12 (See FIG. 1) is isolated in silicon wafer 10, a first oxide layer 16, is grown on silicon wafer 10. In this embodiment, first oxide layer 16 is 10 nanometers thick. However, it should be understood that first oxide layer 16 may be anywhere from 5 to 15 nanometers thick. Following the growth of first oxide layer 16, a first polysilicon layer, 18, is deposited. Following this deposition, first polysilicon layer 18 is doped. In this embodiment, a phosphorous dopant is used, however it should be understood that many other dopants which are well known in the art may also be employed. Following the doping of first polysilicon layer 18, an amorphous silicon layer, 20, is deposited. In a semiconductor memory device such as an EEPROM or an EPROM, it is important that the oxide layers be of extremely high quality. If they are not, the result will be extremely poor data retention characteristics. Amorphous silicon layer 20 serves to seal first polysilicon layer 18. Additionally, amorphous silicon layer 20 is smooth relative to first polysilicon layer 18. The smoothness of amorphous silicon layer 20 allows for the oxide layers to be grown at a much lower temperature. While these oxide layers are being grown, amorphous silicon layer 20 seals the dopant into first polysilicon layer 18 so that it cannot escape and cause autodoping problems. Amorphous silicon layer 20 also suppresses asperity formation at the reduced temperature. Asperity formation causes protrusions into the oxide layers which cause a non-uniform current flow throughout the oxide layers. This degradation of the oxide layers causes poor data retention characteristics. Amorphous silicon layer 20 represses the asperity formation thereby allowing for improved data retention in the semiconductor device while improving the endurance at the same time. Once amorphous silicon layer 20 is deposited, amorphous silicon layer 20, first polysilicon layer 18 and first oxide layer 16 are etched to form a floating gate, 22. The etching of floating gate 22 is performed by using methods which are well known in the art. Following the formation of floating gate 22, a source, 24, and a drain, 26, are implanted. In this embodiment, a self-aligned implant is employed which uses floating gate 22 as a mask. Using this technique, no separate mask is needed. However, it should be understood that other methods well known in the art may be used to implant source 24 and drain 26. Following the implantation of source 24 and drain 26, a second oxide layer, 28, is grown. Second oxide layer 28 serves as an interlevel dielectric. In this embodiment, second oxide layer 28 has a thickness of 40 nanometers. However, second oxide layer 28 may have a thickness anywhere in the range of 30 to 50 nanometers. Again, due to amorphous silicon layer 20, the growth of second oxide layer 28 may occur at a relatively low temperature. In this embodiment, second oxide layer 28 is grown at a temperature in the range of 1000 to 1050 degrees centigrade. It should be understood, however, that second oxide layer 28 may be grown anywhere in the range of 950 to 1100 degrees centigrade. Following the growth of second oxide layer 28, a second polysilicon layer, 30, is deposited. Again, second polysilicon layer 30 is doped, in this case using a phosphorous dopant although other dopants which are well known in the art may be used. Following the doping of second polysilicon layer 30, second polysilicon layer 30 is defined and etched in predetermined manner using methods well known in the art. The resultant device is semiconductor memory device 32. Thus it is apparent that there has been provided, in accordance with the invention, an improved method using the deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices which meets the objects and advantages set forth above. While specific embodiments of this invention have been shown and described, further modifications and improvements will occur to those skilled in the art.

Claims: A method of making a semiconductor memory device comprising the steps of: providing a silicon wafer (10); isolating an area on said silicon wafer and defining a well (12) thereon; growing a first oxide layer (16) on said well (12); depositing a first polysilicon layer (18) on said silicon wafer (10) including said well (12) and said first oxide layer (16); doping said first polysilicon layer (18); depositing an amorphous silicon layer (20) on said doped first polysilicon layer (18); defining and etching said first oxide layer (16), said doped first polysilicon layer (18) and said amorphous silicon layer (20) to form a floating gate (22) in said well (12); implanting a source (24) and a drain (26); growing a second oxide layer (28) on said well (12) including said floating gate (22); depositing a second polysilicon layer on said second oxide layer (28); doping said second polysilicon layer (30); and defining and etching said doped second polysilicon layer (30). The method of claim 1 wherein the implanting step includes using a self-aligned implant. The method of claim 1 wherein the first oxide layer (16) has a thickness in the range of 5 to 15 nanometers. The method of claim 1 wherein the first oxide layer (16) has a thickness of 10 nanometers. The method of claim 1 wherein the second oxide layer (28) has a thickness in the range of 30 to 50 nanometers. The method of claim 1 wherein the second oxide layer (28) has a thickness of 40 nanometers. A semiconductor memory device comprising: a semiconductor substrate (10); a source (24) and a drain (26) disposed in said semiconductor substrate (10); a first oxide layer (16) on said semiconductor substrate (10); a first silicon layer (18) forming a floating gate (22), said floating gate (22) being positioned on said first oxide layer (26); a second oxide layer (28) on said first oxide layer (16) and said floating gate (22); and a second polysilicon layer (30) on said second oxide layer (28); the invention being characterized in that the silicon layer comprises a polysilicon layer and an overlying amorphous silicon layer disposed thereon. The device of claim 7 wherein the first oxide layer (16) has a thickness in the range of 5 to 15 nanometers. The device of claim 7 wherein the first oxide layer (16) has a thickness of 10 nanometers. The device of claim 7 wherein the second oxide layer (28) has a thickness in the range of 30 to 50 nanometers. The device of claim 7 wherein the second oxide layer (28) has a thickness of 40 nanometers.

Inventors: GRISWOLD, MARK DOUGLAS
Applicants: MOTOROLA, INC.
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L29