A signal distinction circuit

Abstract: A signal distinction circuit comprises a clock signal generating circuit for generating a clock signal whose frequency is longer than that of a pulse signal corresponding to a discrimination signal applied to a counter as an actuating signal; and an arithmetic circuit for operating the pulse signal and the clock signal, and generating an output signal according to the presence or non-presence of the discrimination signal so as to forcibly drive a detecting circuit to which an output signal of the counter is applied, whereby the detecting circuit can be forcibly driven irrespective of the condition of the counter when the discrimination signal is not applied thereto.

Description: The present invention relates to a signal distinction circuit for detecting a discrimination signal having a predetermined frequency, and more particularly, to a signal distinction circuit suitable for detecting a discrimination signal having a low frequency included in an FMX stereophonic broadcasting. The present invention also relates to a signal distinction circuit for detecting a signal by a counter is not malfunctioned when the signal is instantaneously cut off. Recently, an FMX stereophonic broadcasting is proposed to improve the S/N of an FM stereophonic broadcasting and enlarge a service area. According to the FMX stereophonic broadcasting, a compressed stereophonic difference signal is transmitted simultaneously with the signal of the FM stereophonic broadcasting. The amplitude of the compressed stereophonic difference signal is modulated by a subcarrier of 38 KHz in an orthogonal relationship therewith. A discrimination signal of 10 Hz is included in the signal of the FMX stereophonic broadcasting so that the FMX stereophonic broadcasting is distinguished from the FM stereophonic broadcasting. Therefore, in order to receive the FMX stereophonic broadcasting, it is necessary for a receiver to detect the discrimination signal and switch the receiving mode thereof to the FMX stereophonic receiving mode. The FMX stereophonic broadcasting is described in detail on pages from 11 through 15 of the September, 1986 edition of the magazine "JAS JOURNAL". The discrimination signal of 10 Hz can be detected by a signal distinction circuit as shown in Fig. 5. Referring to Fig. 5, a stereophonic pilot signal of 19 KHz applied to a first input terminal 1 is divided into approximately 74 Hz by a first dividing circuit 2 and then, applied to a counter 3 as a clock signal. A discrimination signal of 10 Hz applied to a second input terminal 4 is supplied to a pulse generating circuit 6 through a bandpass filter 5. Therefore, a pulse signal having the same frequency as that of the discrimination signal applied to the input terminal 4 is produced from the pulse generating circuit 6. The pulse signal thus produced is divided by a second dividing circuit 7 and then, supplied to the counter 3 as an actuating signal. As a result, the counter 3 counts the clock signal while the pulse signal maintains an "H" level. A detecting circuit 8 detects whether or not the value counted by the counter 3 equals to a predetermined value. The signal discrimination circuit shown in Fig. 5 is provided with a level detecting circuit 9 to detect the level of a signal outputted from the output terminal of the bandpass filter 5. The level detecting circuit 9 produces an "L" level signal when the level of the signal supplied thereto is above a predetermined value and produces an "H" level signal when the level of the signal is below the predetermined value. Therefore, when the level of the signal falls for some reason, the level outputted from the level detecting circuit 9 becomes the "H" level, which causes the detecting circuit 8 to be reset. However, the method of distinguishing the presence of the discrimination signal by the counter has a disadvantage that when the discrimination signal is not applied to the distinction circuit, the counter stops counting the clock signal. As a result, the signal distinction circuit maintains the condition in which the discrimination signal has been applied. For example, when a signal is not received by a receiver caused by a sudden retuning or when a receiver mounted on a vehicle is not capable of receiving a signal because of the fact that it is traveling in a tunnel, the receivers maintain the condition in which they have received discrimination signals despite that discrimination signals are not applied thereto, which causes, for example, an indicator to light erroneously. Further, when a discrimination signal of 10Hz included in the signal of an FMX stereophonic broadcasting is distinguished by the distinction circuit shown in Fig. 5, a bandpass filter 5 having a center frequency of 10 Hz is used. It is to be noted that the normal lower cut-off frequency of a program signal of the FMX stereophonic broadcasting is 50 Hz and the normal level of the program signal is greater than that of the discrimination signal. Therefore, a portion of the program signal is applied to the pulse generating circuit 6 through the bandpass filter 5. The pulse generating circuit 6 produces a pulse by detecting a zero crossing. Therefore, when a program signal having a low frequency and a large amplitude leaks from the bandpass filter 5, a narrow width-pulse is generated at the output terminal of the pulse generating circuit 6, which may cause the counter 3 to malfunction in response to the narrow width-pulse. In addition, in receiving a radio broadcasting having a discrimination signal, the discrimination signal is distorted and its level falls by a multipath interference or an external noise. It is desirable that the condition of a receiver does not change even though the level of the discrimination signal falls so that a listener enjoys listening to the radio. However, in the receiver provided with the signal distinction circuit shown in Fig. 5, the level of the level detecting circuit 9 outputs an "H" level signal caused by the instantaneous fall of the level of the discrimination signal instantaneously, which causes the detecting circuit 8 to be reset. As a result, the state of the receiver changes. For example, when a receiver is receiving the FMX stereophonic broadcasting, the receiver is switched to receive the FM stereophonic broadcasting by an instantaneous fall of a discrimination signal of 10 Hz and a noise level fluctuates, so that a listener feels uncomfortable. Furthermore, when a multipath interference occurs when the receiver is receiving the FMX stereophonic broadcasting, a received signal and a discrimination signal are distorted. As a result, the value counted by the counter 3 constituting the signal distinction circuit is out of a predetermined range of the detecting circuit 8. As a result, an "L" level signal is outputted from the detecting circuit 8 and the receiving mode is switched to the FM receiving mode. When the signal received by the receiver is subjected to a frequent interference such as by the multipath interference, the level of the signal outputted from the detecting circuit 8 are frequently switched, which causes the indicator to flash and the receiver to an inappropriate state that the FMX stereophonic broadcasting is received in the FM mode. The present invention has been made with a view to substantially solving the above-described disadvantages. It is an object of the present invention to provide a signal distinction circuit in which signal detection is retained even if one period/pulse is missing. This object is achieved by a signal distinction circuit as defined in claim 1 and claim 2, respectively. According to the signal distinction circuit having the construction defined in claim 1, the detecting circuit can be forcibly driven irrespective of the condition of the counter when the discrimination signal is not applied thereto because the pulse signal corresponding to the discrimination signal and the clock signal having a frequency longer than that of the pulse signal are operated and a signal to forcibly drive the detecting circuit is generated. According to the construction defined in claim 2, the reset signal generating circuit is controlled by the signal outputted from the pulse generating circuit for generating a pulse corresponding to a discrimination signal and the signal outputted from the level detecting circuit for detecting the level of the discrimination signal. Therefore, after a discrimination signal whose level is higher than a predetermined level is detected, a reset signal is not generated and a reset signal can be generated when a plurality of discrimination signals whose levels are lower than the predetermined level are continuously detected, the reset signal can be produced. Accordingly, the reset signal is generated when the level of the discrimination signal instantaneously falls. Thus, the detecting circuit to which the output signal of the reset signal generating circuit is applied does not respond to the instantaneous cut-off of the discrimination signal. These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a first embodiment of the present invention; Fig. 2 (a) through (f) is a characteristic view to explain the first embodiment; Fig. 3 is a circuit diagram showing a second embodiment of the present invention; Fig. 4 (a) through (h) is a characteristic view to explain the second embodiment; and Fig. 5 is a circuit diagram showing a conventional signal distinction circuit. Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings. Fig. 1 is a circuit diagram of a first embodiment of the present invention. The signal distinction circuit comprises first through fourth T-FFs 109, 110, 111, 112 in a cascade connection constituting a divider circuit, a first AND gate 113 which takes the logic of the output signal of the fourth T-FF 112 and the output signal of a pulse generating circuit 106, a second AND gate 114 which takes the logic sum of the first through fourth T-FFs 109 through 112, a first D-FF which receives the output of the first AND gate 113 as the input as a clock signal and the output of the second AND gate 114 as a reset signal, and a second D-FF which receives the Q output of the first D-FF 115 as D input and the output of the fourth T-FF 112 as a clock signal. The circuits other the above described circuits constituting this circuit in Fig. 1 is the same as those shown in Fig. 5. Therefore, the descriptions thereof are omitted herein. A stereophonic pilot signal of 19 KHz applied to a first input terminal 101 is divided by a divider circuit 102 and thereafter, applied to a counter 103 as a clock signal, and also applied to the first T-FF 109, and further divided by the first through fourth T-FFs 109 through 112. As a result, a clock signal of approximately 4.6 Hz less than half the frequency of a discrimination signal is generated at the output terminal of the fourth T-FF 112. The clock signal of 4.6 Hz and a pulse signal corresponding to the discrimination signal of 10 Hz supplied from the pulse generating circuit 106 are applied to the first AND gate 113. The waveform of the signal outputted from the pulse generating circuit 106 is as shown by (a) in Fig. 2 and the waveform of the signal outputted from the fourth T-FF 112 is as shown by (b) in Fig. 2. Accordingly, the waveform of the signal outputted from the first AND gate 113 is as shown by (c) in Fig. 2. A reset signal as shown by (d) in Fig. 2 is outputted from the second AND gate 114 whose input terminal is connected to the output terminals of the first through fourth T-FFs 109 through 112. The reset signal is applied to the reset terminal of the first D-FF 115. As a result, a signal is generated as the Q output of the first D-FF 115. The level of this signal becomes "L" as shown by (e) in Fig. 2 in response to the reset signal and an becomes "H" when the output signal (shown by (c) in Fig. 2) of the first AND gate 113 falls. The Q output of the first D-FF 115 is connected to the D input of the second D-FF 116 and the clock signal outputted from the fourth T-FF 112 is applied to the clock input of the second D-FF 116. A signal as shown by (f) in Fig. 2 is generated at the Q output of the second D-FF 116. The level of this signal is "H" while the signal is intermittently outputted from the first AND gate 113. The level of the output signal of the second D-FF 116 becomes "L" when a signal is not outputted from the first AND gate 113, i.e., a discrimination signal is not inputted to a second input terminal 104. Accordingly, whether or not a discrimination signal is applied to the signal distinction circuit can be detected by the level of the output signal of the second D-FF 116. The detecting circuit 108 is forced to be driven by the signal outputted from the second D-FF 116. Therefore, irrespective of the state ("H" or "L") of the output signal of the counter 103, an "L" level signal is outputted from the detecting circuit 108 and the "L" level signal is applied to the respective portions of the receiver. Thus, the switching of the receiver is effected. According to the first embodiment, since the discrimination signal is detected by the counter, a malfunction that the signal of a noise is distinguished as a discrimination signal can be prevented. Further, when the discrimination signal is not applied to the signal distinction circuit, a malfunction caused by the clocking of the counter can be prevented since the detecting circuit is forcibly switched by the output signal of the arithmetic circuit. Since a signal distinction circuit according to the present invention is capable of accurately distinguishing the presence of a discrimination signal, it can be preferably utilized as a receiver for an FMX stereophonic broadcasting. Fig. 3 is a circuit diagram showing a second embodiment of the present invention. The signal distinction circuit comprises a flip-flop circuit 310 set by the output signal of a level detecting circuit 309 which detects the level of a discrimination signal and reset by the inversion signal outputted from a pulse generating circuit 306 and a shift register 311 which comprises first D-FF through fourth D-FFs 312 through 315 in a cascade connection relationship and receives the signal outputted from the pulse generating circuit 306 as the clock signal and receives the output signal of flip-flop circuit 310 as a reset signal. The first through third D-FFs 312 through 314 receive the inverted signal outputted from the pulse generating circuit 306 as clock signals and the second through fourth D-FFs 313 through 315 receive the non-inversion output signal of the pulse generating circuit 306 as clock signals. Since the output signal of the flip-flop circuit 310 is applied to the first D-FF through the fourth D-FFs 312 through 315, respectively; the D-FFs 312 through 315 are simultaneously reset. The flip-flop circuit 310 and the shift register 311 comprising the first D-FF through fourth D-FFs 312 through 315 operate as reset signal generating circuits for generating the signal to reset the detecting circuit 308. Next, the operation of the signal distinction circuit of this embodiment is described hereinbelow with reference to the characteristic view shown in Fig. 4. Assuming that a discrimination signal as shown by (a) in Fig. 4 is outputted from the bandpass filter 305, a signal as shown by (b) in Fig. 4 is generated at the output terminal of the pulse generating circuit 306 which generates a pulse by detecting a zero crossing. A signal as shown by (c) in Fig. 4 is generated at the output terminal of the level generating circuit 309 which generates an "H" level signal when a signal whose frequency is higher than its threshold level (X) is inputted thereto and generates an "L" level signal when a signal whose frequency is lower than the predetermined threshold level (X) is inputted thereto. Since the output signal of the level detecting circuit 309 is applied to the flip-flop circuit 310 as a set signal, the level of the Q output of the flip-flop circuit 310 becomes "H" in response to the rise of the signal outputted from the level detecting circuit 309. The inverted output signal (shown by (d) in Fig. 4) of the pulse generating circuit 306 is applied to the flip-flop circuit 310 as a reset signal. Consequently, the level of the Q output of the flip-flop circuit 310 becomes "L" in response to the rise of the inverted output signal. Accordingly, the waveform of the signal outputted from the Q output of the flip-flop circuit 310 is as shown by (e) in Fig. 4. The inverted output of the pulse generating circuit 306 is applied to the first D-FF 312. Caused by this, the waveform of the output signal of the first D-FF 312 is as shown by (f) in Fig. 4. The inverted output of the pulse generating circuit 306 is also applied the second through fourth D-FFs 313 through 315, the waveforms of output signals of the second D-FF 313 through fourth D-FFs 313 through 315 are as shown by (f), (g), and (h) in Fig. 4. The signal (shown by (h) in Fig. 4) outputted from the fourth D-FF 315 is applied to the detecting circuit 308 as a reset signal. As apparent from the comparison of the signal (shown by (a) in Fig. 4) outputted from the bandpass filter 305 with the signal (shown by (h) in Fig. 4) output ted from the fourth D-FF 315, when a discrimination signal having a normal level is obtained, the level of the signal outputted from the fourth D-FF 315 becomes "L", so that the detecting circuit 308 is not reset. If the discrimination signal lacks one cycle, the level of the signal outputted from the fourth D-FF 315 is kept "L". If the discrimination signal lacks two cycles or more, the level of the signal outputted from the fourth D-FF 315 becomes "H". Accordingly, the reset signal generating circuit comprising the flip-flop circuit 310 and the shift register 311 does not respond to the instantaneous lack of the discrimination signal. Since the detecting circuit 308 is not reset when the level of the signal outputted from the bandpass filter 305 is higher than the predetermined value in the signal distinction circuit of this embodiment, the value counted by the counter 303 is detected by the detecting circuit 308. That is, if the detecting circuit 308 detects that a value counted by the counter 308 is in the predetermined range, it outputs an "H" level signal and if it detects that a value counted by the counter 308 is out of the predetermined range, it outputs an "L" level signal. If an instantaneous lack occurs in the signal outputted from the bandpass filter 305, a reset signal is not produced from the fourth D-FF 315. Accordingly, the detecting circuit 308 is not reset, i.e., it maintains the present state until a new data is supplied from the counter 303. If a signal is not outputted from the bandpass filter 305 for a certain period of time, a reset signal is outputted from the fourth D-FF 315. As a result, the detecting circuit 308 is reset, that is, the level of the signal outputted from the detecting circuit 308 is rendered to be "L". A receiver comprising the signal distinction circuit shown in Fig. 3 is capable of detecting a discrimination signal of 10 Hz when it receives a signal of the FMX stereophonic broadcasting. If the signal distinction circuit instantaneously lacks a discrimination signal of 10 Hz, the level of the distinction output thereof is not changed, i.e., it maintains the state in which the receiver has been turned on to receive the FMX stereophonic broadcasting, with the result that a noise level does not change suddenly. As apparent from the foregoing description, the signal distinction circuit of the second embodiment is capable of accurately distinguishing a discrimination signal from the signal of a noise or the like. Further, the present invention provides a signal distinction circuit which is not affected by the instantaneous lack of the discrimination signal. Thus, the signal distinction circuit can be preferably provided with a receiver so as to detect the discrimination signal of the FMX stereophonic broadcasting.

Claims: A signal distinction circuit having a pulse generating circuit (106) for generating a pulse corresponding to a discrimination signal, a counter (103) for counting clock signals in response to a pulse outputted from said pulse generating circuit, and a detecting circuit (108) for detecting the presence of said discrimination signal according to a value counted by said counter (103) comprising: a clock signal generating circuit (109-112) for generating a clock signal whose frequency is lower than that of a pulse outputted from said pulse generating circuit; and an arithmetic circuit (113-116) for generating an output signal in response to the signals from said pulse generating circuit (106) and said clock signal generating circuit (109-112), characterized by said arithmetic circuit having means (116) for detecting whether or not said output signal from said pulse generating circuit (106) exists during the presence of the output signal from said clock signal generating circuit, and means for producing a command signal for driving said detecting circuit when said output signal from said pulse generating signal is detected as non-existing. A signal distinction circuit having a pulse generating circuit (306) for generating a pulse corresponding to a discrimination signal, a counter (303) for counting clock signals in response to a signal outputted from said pulse generating circuit (306), and a detecting circuit (308) for detecting the presence of said discrimination signal according to a value counted by said counter and a level detecting circuit (309) for detecting the level of said discrimination signal; characterized by a reset signal generating circuit comprising a flip-flop circuit (310) set by a signal outputted from said level detecting circuit (309) and reset by a signal outputted from said pulse generating circuit (306) and a shift register (312-315) to which a signal outputted from said pulse generating circuit (306) is applied as a clock signal and a signal outputted from said flip-flop circuit (310) is applied as a reset signal; said detecting circuit being reset by a signal outputted from said reset signal generating circuit.

Inventors: ISHIKAWA TSUTOMU, TANNO MASAYA, ISHIKAWA, TSUTOMU, TANNO, MASAYA
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1988
Main classification: H04B1
IPC codes: H04B1, G01R19