Circuit for cancelling whole or part of a waveform using non-recursive and recursive filters

Abstract: The whole or part of a waveform is cancelled by a circuit comprising a nonrecursive filter (10) and a re­ cursive filter (11,12). The nonrecursive filter (10) has a plurality of first multipliers (17-0 to 17-(N-1)) having first tap weights for modifying symbols successively shift­ ed along a shift register (13-O to 13-N). The recursive filter (11,12) is connected in a series circuit to the shift register and has a second tap weight for recursively modifying the output of the shift register. The recursive­ ly modified symbol is modified by a second multiplier (16-O to 16-(N-1)) having a third tap weight and combined in an adder (18) with the symbols modified by the first tap weights to produce a replica of an undesired waveform. The replica is destructively combined in a subtractor (19) with an in­ coming symbol having an undesired waveform. The output of substractor (19) is utilized to derive the tap weights to adaptively control the inputs to the adder.

Description: The present invention relates generally to waveform correction, and more specifically to a circuit for cancelling whole or part of a waveform using a digital filtering technique. The invention is particularly useful for cancelling echo returning from a hybrid interface between a four-wire and a two-wire section of a digital transmission system or cancelling intersymbol interference that occurs between successive digital waveforms. Conventional echo cancellers and decision feedback equalizers for digital transmission employ a nonrecursive filter (or alternatively called, transversal or finite impulse response filter) having a plurality of tap weights which are adaptively controlled in accordance with the waveform of an incoming symbol so that it produces a replica of the undesired waveform to be destructively combined with the incoming symbol. Because of the finite numbers of the tap weights, the nonrecursive filter is not capable of completely cancelling a long tail portion of the undesired waveform which occurs as a result of the low-frequency cutoff characteristic of a line transformer. It is not practical to provide as many tap weights as necessary to cancel the tail of a waveform. Further echo cancellers are known from IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, 1st-4th December 1986, Houston, TX, 'Communications Broadening Technology Horizons', Conference Record, vol. 1 of 3, pages 44-48, IEEE, New York, US; C. MOGAVERO et al.: "Mixed recursive echo canceller (MREC)" and ICASSP'83 - IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, Proceedings, 14th-16th April 1983, Boston, Massachusetts vol. 1 of 3, pages 49-52, IEEE, New York, US; S.G. SMITH et al.: "A new structure for adaptive echo cancellation". It is therefore an object of the present invention to cancel an undesired waveform having a long tail portion in an economical manner. This object is solved with the features of the claims. A circuit as described is provided with a recursive (infinite impulse response) filter in a series circuit with the shift register of a nonrecursive filter by which an incoming symbol is successively delayed by a unit time interval. The nonrecursive filter has a plurality of first multipliers having first tap weights for respectively modifying a series of successive symbols, the modified symbols being summed in an adder. The recursive filter has a second tap weight for recursively modifying an output of the shift register. The output of the recursive filter is further modified by a third tap weight of a second multiplier and applied to the adder to produce a replica of an undesired waveform. The replica is destructively combined with an incoming symbol by a subtractor. The output of subtractor is utilized to derive the first and third tap weights to adaptively control the inputs to the adder. In a preferred embodiment, the first tap weights are derived from a plurality of first modifiers for modifying the successive symbols in the nonrecursive filter with the output of the subtractor. The second tap weight is derived from a second recursive filter by recursively modifying the output of the second multiplier with the second tap weight and further modifying the output of the second recursive filter with the output of the subtractor. In an alternative embodiment, the second tap weight assumes a value equal to an attenuation coefficient of a transmission medium, and the third tap weight assumes a value equal to one of the first tap weights. In a further alternative embodiment, the second tap weight is derived as a function of the ratio between two of the first tap weights and deter of the first tap weights including said one of the first tap weights. The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of an echo canceller according to a first embodiment of the invention, and Fig. 1a shows details of each of the integrators of Fig. 1; Fig. 2 is a block diagram of an echo canceller according to a second embodiment of the invention; Fig. 3 is a block diagram of an echo canceller according to a third embodiment of the invention; Fig. 4 is a block diagram of a decision threshold equalizer according to a fourth embodiment of the invention; Fig. 5 is a block diagram of a decision threshold equalizer according to a fifth embodiment of the invention; Fig. 6 is a block diagram of a decision threshold equalizer according to a sixth embodiment of the invention; Fig. 7 is a typical waveform of an impulse response; Fig. 8 is a graph showing the results of a simultation test conducted on an echo canceller of the invention in comparison with an echo canceller having no recursive filter; and Fig. 9 is a graph showing the results of a simultation test conducted on a decision threshold equalizer of the invention in comparison with a decision threshold equalizer having no recursive filter. Referring now to Figs. 1 through 6, digital filters according to embodiments of the present invention are illustrated. The digital filter of Fig. 1 is an echo canceller for cancelling echoes generated by the transhybrid coupling at the interface between a four-wire section and a two-wire section of a digital transmission system. The digital filter generally comprises a nonrecursive, or finite impulse response (FIR) filter 10, and first and second recursive, or infinite impulse response (IIR) filters 11 and 12. Nonrecursive filter 10 includes a series of unit-time delay elements 13-0 through 13-N typically implemented by a conventional shift register. The shift register is clocked so that each unit delay time corresponds to the interval T between successive symbols. The input of the shift register, or delay element 13-0, is connected to receive a digital bit stream "a n " applied to a "go-path" terminal 14 which is connected to a hybrid 15 for transmission over a two-wire section of the transmission system. The input terminals of delay elements 13-0 through 13-N are connected respectively to adaptive multipliers 16-0 through 16-(N-1) on the one hand and to multipliers 17-0 through 17-(N-1) on the other hand. The outputs of adaptive multipliers 16 are summed in an adder 18 whose output is fed as an echo replica "r n " to a subtractor 19 to cancel echo contained in a "return-path" signal "y n " from hybrid 15. Subtractor 19 produces an output "e n " which is supplied to a decision circuit 20 and to all multipliers 17-0 through 17-(N-1). These multipliers supply multiplication outputs e n ·a n , e n ·a n-1 , ..... e n ·a n-N+1 to integrators 21-0, 21-1, ..... 21-(N-1), respectively. Integrators 21-0 through 21-(N-1) supply tap weights C₀, C₁, ..... C N-1 to the control terminals of adaptive multipliers 16-0 through 16-(N-1), respectively. Recursive filter 11 comprises an adder 22, a unit-time (=T) delay element 23, and an adaptive multiplier 24. Adder 22 provides summation of the output of nonrecursive filter 10 from delay element 13-N and the output of multiplier 24 to produce an output "u n " which is applied through delay element 23 to multiplier 24 having a variable weighting factor "J". The output of adder 22 is also applied to an adaptive multiplier 25 whose output "w n " is summed with the outputs of multipliers 16 by adder 18. The tap weight "K" of multiplier 25 is derived from multiplication of signals "u n " and "e n " by a multiplier 26 and integration of the output of multiplier 26 by an integrator 27. Second recursive filter 12 comprises an adder 28 which provides summation of the signal "w n " and an output of a variable multiplier 30 and feeds the multiplier 30 through a unit-time delay element 29 to produce an output "p n " which is multiplied by the factor "J" to be fed back to adder 28. The tap weight "J" for multipliers 24 and 30 is derived from multiplication of signals "e n " and "p n-1 " by a multiplier 31 and integration of the output of multiplier 31 by an integrator 32. Echo replica "r n " is given by: where, u n is represented by a recurrence formula given by a n-N + J·u n-1 . This recurrence formula represents a recursive filter having a characteristic 1/(1 - J·z⁻¹) . Since e n = y n - r n , the relation holds, where ε represents an average of squared residual echo and E represents an expectation. The tap weights C i (i = 0, 1, 2 .... N-1), J and K are determined by minimizing the average of squared residual echo by the following partial differential equations: Since ∂K·u n /∂J is given by: and since w n = K·u n and ∂w n+1 /∂J = p n , the following relation holds: p n = w n + J·p n-1 Therefore, As shown in Fig. 1a, each of the integrators described above preferably comprises a multiplier 40, an adder 41 having a first input connected to the output of multiplier 40, and a unit-time delay element 42 connected in a feedback path between the output of adder 41 and a second input of adder 41. In the case of integrators 21-0 through 21-(N-1), multiplier 40 corrects the output signal e n ·a n-i from the associated multiplier 17 with a coefficient α C . Adder 41 sums the output of multiplier 40 with a unit-time delayed output C i (ν) from delay element 42 to produce an output C i (ν+1) , where i ranges from 0 to N-1. Therefore, the tap weights C₀ through C N-1 for multipliers 16-0 through 16-(N-1) are given by: C i (ν+1) = C i (ν) + α C ·e n ·a n-i (5) Likewise, the tap weights J and K are given by: K (ν+1) = K (ν) + α K ·e n ·u n (6) J (ν+1) = J (ν) + α J ·e n ·p n-1 (7) The operating characteristic of the echo canceller of Fig. 1 was verified by performing a simulation technique on an echo shown at Fig. 7 having a negative exponential decay response at a low cut-off frequency which corresponds to 1/200 of the data transmission speed. In this simulation test, the nonrecursive filter 10 was provided with 32 taps (N = 32) to cancel the major part of the echo replica. At time t = NT, the amplitude of the echo was -0.0118. To cancel the tail of an echo, the tap weights K and J of the recursive filter 11 were -0.0118 and 0.96907 (=e 2π/200 ), respectively. With initial values for C i (0) , K (0) and J (0) being set equal to 0, 0 and 1, respectively, the tail of the echo was successfully cancelled as indicated in Fig. 8, which favorably compares with the prior art having no recursive filter. Since the portion of echo prior to the instant t=NT is canceled by the nonrecursive filter 10 and the tail of echo following that instant decays as a function β -t/T , (where β is a coefficient determined by the inductance of the hybrid 15, the characteristic impedance and distance of the two-wire transmission medium), the embodiment of Fig. 1 can be simplified by setting the tap weights K and J of the recursive filter 11 equal to C N-1 and β, respectively. The simplified embodiment is shown in Fig. 2 in which the second recursive filter 12 is dispensed with and a recursive filter 111 is provided having adder 122, multiplier 124, delay unit 123 and an adaptive multiplier 125. Multiplier 124 multiplies the output of adder 122 with coefficient β, the output of multiplier 124 being passed through delay unit 123 to the second input of adder 122 to be summed with the output of the delay element 13-N of nonrecursive filter 110. Adaptive multiplier 125 modifies the output of delay unit 123 with tap weight K=C N-1 . A further alternative embodiment is shown in Fig. 3 in which the recursive filter 211 includes adder 222 connected to the output of delay element 13-N of nonrecursive filter 210, adaptive multipliers 224 and 225 and delay unit 223. The tap weight J of multiplier 224 is adaptively controlled by a tap control circuit 200 and the tap weight of multiplier 225 is set equal to C N-1 as in the previous embodiment. Since tap weights C i (i=0, 1, .... N-2) and C N-1 correspond respectively to echo impulse responses at instants t=iT and t=NT (Fig. 7), respectively, the ratio C i /C N-1 is given by: Therefore, Equation (8) is realized by line-segment approximation using a relation Y = X 1/(N-i) , where X = C i /C N-1 . In Fig. 3, tap weight C i is taken from the output of integrator 21-2 of nonrecursive filter 210. The tap weight values C₂ and C N-1 are supplied to a divider 50 to derive a ratio X, which is applied to a read only memory 51. This memory stores a plurality of sets of constants A(X) and B(X) in locations addressable as a function of ratio X. The constant A(X) is applied to a multiplier 52 to multiply the ratio X and the output of the multiplier is summed in an adder 53 with B(X) from the memory 51 to yield the Y-value by an equation Y = A(X)·X + B(X) . The output of adder 53 is applied to the tap control input of adaptive multiplier 224. The digital filter of the present invention can also be used as a decision feedback equalizer as shown in Fig. 4 to cancel intersymbol interference. In this embodiment, the decision feedback equalizer comprises a nonrecursive filter 310, a first recursive filter 311 and a second recursive filter 312. An input bit stream is applied through an input terminal 301 to a subtractor 302 where it is combined with a cancelling signal to produce an output signal "z n ", which is fed to a decision circuit 303. The output of decision circuit 303 serves as an input bit stream "d n " to the shift register formed by a series of unit-time delay elements 60-0 through 60-N. Adaptive multipliers 61-1 through 61-(N-1) are respectively coupled to the inputs of delay elements 60-1 through 60-N, the outputs of multipliers 61-1 through 61-(N-1) being summed in an adder 63. A signal representative of a decision error "e′ n " is derived from signals "z n " and "d n " by a subtractor 304 and fed to multipliers 62-1 through 62-(N-1) to multiply the inputs of delay elements 60-1 through 60-N with decision error "e′ n ". The outputs of multipliers 62-1 through 62-(N-1) are respectively supplied to integrators 64-1 through 64-(N-1) identical to those shown in Fig. 1a to generate tap weights C′₁ through C′ N-1 for adaptive multipliers 61-1 through 61-(N-1). Recursive filter 311 comprises an adder 322 having a first input coupled to the output of delay element 60-N. A unit-time delay element 323 and an adaptive multiplier 324 are connected in a loop from the output of adder 322 to a second input of adder 322. The output of adder 322 is further applied to an adaptive multiplier 325 where it is multiplied with a tap weight K′ which is derived from a multiplier 326 by multiplying an output signal "u′ n " from adder 322 by the signal "e′ n " from subtractor 304 and an integrator 327 which integrates the output of multiplier 326. Multiplier 325 produces an output "w′ n " which is applied to the adder 63. Adder 63 generates an output signal "r′ n " which is applied to the subtractor 302 as a cancelling signal, or replica of intersymbol interference. Second recursive filter 312 comprises a unit-time delay element 320 connected to the output of multiplier 325. The output of delay element 320 is summed by an adder 328 with the output of a feedback loop formed by a delay element 329 and an adaptive multiplier 330 to generate an output "p′ n " which appears at the output of adder 328. Multiplier 330 has the same tap weight J′ as that of multiplier 324. In order to control the tap weights of multipliers 324 and 330, the output "e′ n " of subtractor 304 and the output "p′ n " of adder 328 are multiplied by a multiplier 331 and integrated by an integrator 332 and fed to the tap weight control inputs of multipliers 324 and 330. The replica of an intersymbol interference "r′ n " is given by: where, u′ n is represented by a recurrence formula d n-N + J′·u′ n-1 . Since z n = y′ n - r′ n and e′ n = z n - d n = y′ n - r′ n - d n , the relation ε Δ E[e n ²] holds as in the previous embodiment. The tap weights C′ i (i = 0, 1, 2 .... N-1), J′ and K′ are determined by minimizing the average of squared residual echo by the following partial differential equations: Since ∂K′·u′ n /∂J′ is given by: and w n = K·u n and since and the following relation holds: p′ n = w′ n-1 + J′·p′ n-1 Therefore, Since the input signal y′ n is expressed by: where, a′ n is a transmitted bit stream and g n represents the impulse response of the transmission medium. Assuming that g₀ = 1 and g N+m = g N ρ m (where m = 0, 1, .... infinity, and ρ represents the negative exponential attenuation coefficient (0 < ρ < 1) attributed to the first order low-frequency cutoff), tap weights C′₀ through C′ N-1 , and K′ and J′ are represented by: C′ i (ν+1) = C′ i (ν) + α C ′·e′ n ·a′ n-i (13) K′ (ν+1) = K′ (ν) + α K ′·e′ n ·u′ n (14) J′ (ν+1) = J′ (ν) + α J ′·e′ n ·p′ n (15) where, α C ′, α K ′ and α J ′ are corrective coefficients. Each of the integrators shown in Fig. 4 can therefore be implemented in a manner similar to that shown in Fig. 1a. The operating characteristic of the decision feedback equalizer of Fig. 4 was verified by performing a simulation technique on an intersymbol interference having a negative exponential decay response ( ρ = e -2π/200 ) at a low cut-off frequency which corresponds to 1/200 of the data transmission speed. In this simulation test, the nonrecursive filter 310 was provided with 16 taps (N = 16) to cancel a greater part of the intersymbol interference. At time t = NT , the impulse response g N was 0.005. To cancel the tail of the symbol, the tap weights K′ and J′ of the recursive filter 311 were 0.005 and 0.96907 (=ρ), respectively. The tail of the intersymbol interference was successfully cancelled as indicated in Fig. 9, which favorably compares with the prior art decision feedback equalizer having no recursive filter. Since the portion of an intersymbol interference prior to the instant t=NT is cancelled by the nonrecursive filter 310 and the tail of the interference following that instant decays as a function β -t/T , the embodiment of Fig. 4 can be simplified by setting the tap weights K′ and J′ of the recursive filter 311 equal to C′ N-1 and β, respectively. The simplified embodiment is shown in Fig. 5 in which the second recursive filter 312 is dispensed with and a recursive filter 411 is provided having adder 422, multiplier 424, delay unit 423 and an adaptive multiplier 425. Multiplier 424 multiplies the output of adder 422 with coefficient β, the output of multiplier 424 being passed through delay unit 423 to the second input of adder 422 to be summed with the output of the delay element 60-N of nonrecursive filter 410. Adaptive multiplier 425 modifies the output of delay unit 423 with tap weight K′=C′ N-1 . A further alternative embodiment is shown in Fig. 6 in which recursive filter 511 includes adder 522 connected to the output of delay element 60-N of nonrecursive filter 510, adaptive multipliers 524 and 525 and delay unit 523. The tap weight J′ of multiplier 524 is adaptively controlled by a tap control circuit 500 and the tap weight of multiplier 525 is set equal to C′ N-1 as in Fig. 5. Since tap weights C′ i (i=0, 1, .... N-2) and C′ N-1 correspond respectively to the amplitudes of a symbol at instants t=iT and t=NT, respectively, the ratio C′ i /C′ N-1 is given by: Therefore, In a manner similar to that described with reference to Fig. 3, Equation (16) is realized by line-segment approximation using a relation Y′ = X′ 1/(N-i) , where X′ = C′ i /C′ N-1 . In Fig. 6, tap weight C′ i is taken from the output of integrator 64-3 of nonrecursive filter 510. The tap weight values C′₃ and C′ N-1 are supplied to a divider 550 to derive the ratio X′, which applied to a read only memory 551. This memory stores a plurality of sets of constants A′(X′) and B′(X′) in locations addressable as a function of the input ratio X′. The constant A′(X′) is applied to a multiplier 552 to multiply the ratio X′ to obtain A′(X′)·X′ which is summed in an adder 553 with constant B′(X′) from the memory 551 to yield the Y′-value by an equation Y′ = A′(X′)·X′ + B′(X′) . The output of adder 553 is applied to the tap control input of adaptive multiplier 524. The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims: A circuit for cancelling whole or part of a received waveform, comprising: a nonrecursive filter (10; 110; 210; 310; 410; 510) including a plurality of first delay elements for converting a symbol into a series of symbols spaced apart a unit time interval, a plurality of first multipliers associated respectively with said delay elements for modifying said spaced apart symbols with first tap weights (C i ; C′ i ) and an adder for summing outputs of said first multipliers; a recursive filter (11; 111; 211; 311; 411; 511) for recursively modifying an output of said delay elements with a second tap weight (J; J′); a second multiplier (25; 125; 225; 325; 425; 525) for modifying an output of said recursive filter with a third tap weight and applying the modified output of the recursive filter to an input of said adder to cause the adder to produce a replica of whole or part of said waveform; a subtractor (19; 302; 304) for combining said replica with a received symbol having said waveform; and tap weight deriving means for deriving said first and third tap weights (C i , K; C′ i , K′) from an output of said subtractor. A circuit as claimed in claim 1, wherein said tap weight deriving means comprises a plurality of first modifying means (17, 21; 62, 64) for modifying said spaced apart symbols of said series with the output of said subtractor to derive said first tap weights (C i ; C′ i ). A circuit as claimed in claim 2, wherein each of said first modifying means comprises: a third multiplier (17; 62) for multiplying a respective one of said spaced apart symbols with the output of said subtractor; a second adder (41) having a first input connected to an output of said third multiplier; and a second delay element (42) connected between an output of said second adder and a second input of said second adder to derive a respective one of said first tap weights. A circuit as claimed in any of claims 1 to 3, wherein said tap weight deriving means comprises: a second recursive filter (12; 312) for recursively modifying an output of said second multiplier (25; 325) with said second tap weight (J; J′); and second modifying means (31, 32; 331; 332) for modifying an output of said second recursive filter with the output of said subtractor (19; 302, 304) to derive said second tap weight (J; J′). A circuit as claimed in claim 4, wherein said second modifying means (31, 32; 331, 332) comprises: a third multiplier (31; 331) for multiplying the output of said second recursive filter with the output of said subtractor; a second adder (41) having a first input connected to an output of said third multiplier; and a second delay element (42) connected between an output of said second adder and a second input of said second adder to derive said second tap weight (J; J′). A circuit as claimed in claim 4 or 5, wherein said tap weight deriving means comprises third modifying means (26, 27; 326, 327) for modifying the output of said recursive filter with the output of said subtractor to derive said third tap weight (K; K′). A circuit as claimed in claim 6, wherein said third modifying means (26, 27; 326, 327) comprises: a third multiplier (26; 326) for multiplying the output of said recursive filter (11; 311) with the output of said subtractor; a second adder (41) having a first input connected to an output of said third multiplier (26; 326); and a second delay element (42) connected between an output of said second adder and a second input of said second adder to derive said third tap weight (K; K′). A circuit as claimed in any of claims 1 to 7, wherein second tap weight (J; J′) is equal to an attenuation coefficient of a transmission medium. A circuit as claimed in any of claims 1 to 8, wherein said third tap weight (K; K′) is equal to one (C N-1 ; C′ N-1 ) of said first tap weights. A circuit as claimed in any of claims 1 to 8, wherein said third tap weight (K; K′) is equal to one (C N-1 ; C′ N-1 ) of said first tap weights, and said tap weight deriving means comprises: means (50; 550) for determining a ratio between two of said first tap weights, said two of the first tap weights including said one of the first tap weights; and means (51-53; 551-553) for deriving said second tap weight (J; J′) as a function of said ratio. A circuit as claimed in claim 10, wherein said means for deriving said second tap weight (J; J') comprises: means (51; 551) for generating a pair of first and second constants as a function of said ratio; means (52; 552) for multiplying said first constant by said ratio; and means (53; 553) for adding said multiplied constant to said second constant and applying the sum to said recursive filter as said second tap weight. An echo canceller comprising a circuit for cancelling whole or part of a received wave form according to any one of claims 1 to 11. A decision feedback equilizer comprising a decision circuit (303) and a circuit for cancelling whole or part of the received wave form according to any one of claims 1 to 11.

Inventors: ARAI MASANOBU, KOIKE SHIN ICHI, OGATA TAKENORI C O NEC MIYAGI, YAMAGUCHI MASARU, ARAI, MASANOBU, KOIKE, SHIN'ICHI, OGATA, TAKENORI C/O NEC MIYAGI LTD., YAMAGUCHI, MASARU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H03H17
IPC codes: H03H17, H04B3