Data reproducing apparatus

Abstract: Data reproducing apparatus (10) demodulates digital data recorded on a magnetic recording medium (3) using a clock regeneration circuit (11) having a phase locked loop circuit arrangement (12 to 14, 16). A lock frequency of the clock regeneration circuit (11) is switch-­ controlled by a control circuit (15). Even if modulation systems having different recording densities are used, the bit error rate during demodulation can be decreased.

Description: This invention relates to data reproducing apparatus and, more particularly, to data reproducing apparatus for receiving digital data recorded on a magnetic recording medium such as magnetic tape. In a video tape recorder (VTR), for example, of an 8-mm video format, an audio signal is pulse code modulation (PCM)-encoded and compressed along the time axis. The signal is then modulated by biphase-mark modulation and recorded on an audio track which is formed adjacent and parallel to a video track. Such a VTR is disclosed in US Patent No. US-A-4 551 771 assigned to the present applicants. Figure 5 of the accompanying drawings shows a known 8-mm VTR track pattern. Parallel magnetic tracks (TRA, TRB) are sequentially formed on a magnetic tape T. Each track is divided into a video track area TRVD and a compressed PCM audio track area TRAD. A previously-proposed data reproducing apparatus 1 for reproducing audio data recorded on an audio track by a biphase-mark modulation system has an arrangement as shown in Figure 3 of the accompanying drawings. A regenerated clock signal CK1 of a repetitive frequency included in a reproduced signal SPB, picked up from a magnetic tape 3 by a rotary reproducing head 2, is extracted. The reproduced signal SPB (DTPB1) is demodulated, based on the regenerated clock signal CK1. For example, the reproduced signal SPB obtained at a timing at which the rotary reproducing head 2 travels along the video track of the magnetic tape 3, through a switching circuit (not shown) for alternately using two rotary heads, is supplied to a video signal processing circuit (not shown) and an automatic track following (ATF) circuit (not shown) through the switching circuit (not shown). The reproduced signal SPB obtained at a timing at which the reproducing head 2 scans the audio track of the magnetic tape 3 is supplied to an equaliser 5 through a reproducing amplifier 4. The equalised reproduced signal is supplied to the inverting input terminal of a comparator 6 having an operational amplifier arrangement. The non-inverting input terminal of the comparator 6 is earthed or grounded via a power supply VREF for generating a predetermined reference voltage. The comparator 6 compares the reproduced signal SPB with the reference voltage. A reproduced digital signal DTPB is supplied as the comparison result to an input terminal D of a synchronisation circuit 7 having a D flip-flop arrangement, and is also supplied to a clock regeneration circuit 8 having a phase locked loop (PLL) circuit arrangement. The clock regeneration circuit 8 compares phases of a reference signal of a predetermined frequency obtained by an internal voltage controlled oscillator (VCO) and a clock component of a predetermined frequency included in the input reproduced digital signal DTPB. Thus, the regenerated clock signal CK1 can be obtained which is correctly phase-locked with the clock component. The regenerated clock signal CK1 is supplied to a clock input terminal C of the synchronisation circuit 7, and is also supplied to a PCM demodulation processor or a PCM decoder (not shown). The synchronisation circuit 7 synchronises the reproduced digital signal DTPB with the regenerated clock signal CK1, and sends it to the following demodulation processor (not shown). The demodulation processor demodulates the input reproduced digital signal DTPB1 based on the regenerated clock signal CK1. In recent years, it has been proposed that a new modulation system such as that employed in a rotary-head type digital audio tape recorder (R-DAT) may be used as a recording system of an audio signal in the 8-mm VTR instead of the previous type of biphase-mark modulation system (referred to as the first type of modulation hereinafter) described in US-A-4 551 771. In this new system, an audio signal is PCM-encoded at a considerably higher bit rate than in the first modulation system, is modulated by the so-called 8-10 modulation system (referred to as the second type of modulation hereinafter) and is recorded on the audio track. A similar modulation system to this second type of modulation system is described in US Patents No. US-A-4 617 552 and No. US-A-4 577 180 in more detail. The 8-10 modulation system is a system of converting 8-bit data into 10-bit data and recording the 10-bit data. Thus, continuous generation of "1"s and "0"s of the data can be prevented. Therefore, the reproduced data does not include a DC component, and clock regeneration upon reproduction can be facilitated. However, in practice, the first and second types of modulation have different frequency bands of recording signals, and have a large difference in sampling clock frequency. That is, the first type of modulation has a sampling clock frequency of 11.6 MHz, while the second type of modulation has a sampling clock frequency of 14.8 MHz. For this reason, these systems have different Nyquist conditions of electromagnetic conversion, and different noise spectrum distributions. Figure 4A of the accompanying drawings shows an eye pattern EPN of the reproduced signal SPB of the first type of modulation in the data reproducing apparatus 1 shown in Figure 3. The clock regeneration circuit 8 obtains the regenerated clock signal CK1 (indicated by a solid line in Figure 4B of the accompanying drawings) which rises at a timing at which the crest value of the eye pattern EPN is maximum. When a regenerated clock signal CK2 is to be obtained from the reproduced signal SPB of the second type of modulation using this clock regeneration circuit 8, a phase shift of time τ occurs, as indicated by a broken line in Figure 4B. As a result, the bit error ratio of demodulated data demodulated by the demodulation processor is increased. US Patent No. US-A-4 534 044 discloses a disc read data recovery system in which a phase locked loop phase compares a signal generated by its oscillator and associated dividers with the incoming data stream to provide differing signals depending on whether the incoming data is leading or lagging the clock signal. For different types of incoming signal, different frequency dividers in the phase locked loop may be selected, and the output clock signal is also subject to differing frequency division. According to the present invention, there is provided data reproducing apparatus for receiving digital data recorded on a magnetic recording medium by one of first and second types of modulation having different recording densities, obtaining a regenerated clock signal based on a clock component included in the received data by a clock regeneration circuit having a phase locked loop circuit arrangement, and demodulating the received data based on the regenerated clock signal to reproduce digital data, wherein said clock regeneration circuit comprises: a voltage controlled oscillator; a low-pass filter circuit for switching a time constant in correspondence with the first or second type of modulation and for providing a control voltage for controlling said voltage controlled oscillator based on a phase comparison result of the received data and an output reference signal from said voltage controlled oscillator; and control means for generating a control signal to control switching of said low-pass filter circuit and for controlling switching of the frequency of the signal supplied to said low pass filter circuit from said voltage controlled oscillator for phase comparison; characterised in that: a resonance circuit is associated with said voltage controlled oscillator for switching the frequency of said reference signal output by said voltage controlled oscillator in dependence upon said control signal; and said control means includes processing means controlled by a stored table associating address data, including said type of modulation, with a control signal in order to control switching of said resonance circuit and said low-pass filter circuit. The frequency of the reference signal of the voltage controlled oscillator (VCO) and the resonance or tank circuit and the time constant of the low-pass filter (LPF) of the clock regeneration circuit are switch-controlled in correspondence with the type of modulation on the magnetic recording medium. For this reason, the clock regeneration circuit has a lock frequency corresponding to the first or second type of modulation. Thus, the regenerated clock signal can be obtained using the clock regeneration circuit. In this manner, when modulation systems having different recording densities are used, demodulation processing can be performed using the corresponding regenerated clock signal. Thus, the bit error ratio during demodulation can be decreased. Accordingly, a preferred embodiment of the present invention provides a data reproducing apparatus which can obtain a regenerated clock signal in correspondence with modulation systems of different recording densities. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a block diagram showing an embodiment of the present invention; Figure 2 is a table showing the relationship between first, second and third discrimination results in a control circuit and selected switch terminals in the circuit of Figure 1; Figure 3 is a block diagram showing a previously-proposed data reproducing apparatus; Figures 4A and 4B are signal waveform charts showing an eye pattern and phases of regenerated clock signals; and Figure 5 is a view showing a track pattern on a tape. The same reference numerals in Figure 1 denote similar parts to those in Figure 3. Referring to Figure 1, a data reproducing apparatus 10 according to an embodiment of the present invention includes a clock regeneration circuit 11 switch-controlling a lock frequency of a PLL circuit based on a control signal CNT from a control circuit 15. More specifically, the clock regeneration circuit 11 comprises a PLL circuit. A phase comparator 12 compares phases of an input reproduced digital signal DTPB and an oscillation output SVCO from a voltage controlled oscillator (VCO) 13. A comparison output SCP is supplied as the comparison result to an input terminal a of a first switching circuit 14 having an analog switch arrangement. The first switching circuit 14 selects one of eight output terminals b1 to b8 for connection to the one input terminal a based on the control signal CNT supplied from the control circuit 15 which may be, for example, a microcomputer arrangement. The output terminals b1 to b8 are connected to the VCO 13 through respective first to eighth low-pass filter (LPF) circuits 16A to 16H having different bandpass characteristics. The VCO 13 is connected to one input terminal c for switchable connection to one of eight output terminals d1 to d8 of a second switching circuit 17 having an analog switch arrangement based on the control signal CNT input from the control circuit 15, in order to set an oscillation frequency of the oscillation output SVCO serving as the reference signal. The switching circuit 17 selectively connects first to eighth tank circuits 18A to 18H having different resonance frequencies. The second switching circuit 17 is switch-controlled based on the control signal CNT input from the control circuit 15, so that the VCO 13 generates the oscillation output SVCO of the predetermined frequency. The first switching circuit 14 is switch-controlled to be interlocked with the second switching circuit 17, so that one of the LPFs 16A to 16H corresponding to the oscillation output SVCO is used. Thus, the lock frequency corresponding to the input reproduced digital signal DTPB is controlled by the control signal CNT from the control circuit 15. Based on, for example, a bit error rate signal SBE, the control circuit 15 discriminates if digital data recorded on the magnetic tape 3 is data of the first type of modulation (as the biphase-mark modulation system) or data of the second type of modulation (as the 8-10 modulation system), and obtains a first discrimination result. In this embodiment, in addition to the first discrimination result, the control circuit 15 discriminates the type of the magnetic tape 3 in use based on a tape type signal SMEP obtained from a mark formed on an 8-mm video tape cassette. More specifically, the control circuit 15 discriminates if the magnetic tape 3 in use is a coated type magnetic tape (to be referred to as an MP tape hereinafter) or a vapour deposition type magnetic tape (to be referred to as an ME tape hereinafter) having different phase characteristics from the MP tape, thus obtaining a second discrimination result. Based on, for example, an ATF error signal SATF obtained from an ATF circuit (not shown), the control circuit 15 further discriminates if data is recorded in a standard recording/reproducing mode (to be referred to as an SP mode hereinafter) or in a long-time or long-play recording/reproducing mode (to be referred to as an LP mode hereinafter), thus obtaining a third discrimination result. The control circuit 15 combines the first, second and third discrimination results as shown in the table of Figure 2, and sends, to the first and second switching circuits 14 and 17, the control signal CNT for selecting one of the first to eighth output terminals b1 to b8 of the first switching circuit 14 and one of the first to eighth output terminals d1 to d8 of the second switching circuit 17. Note that the control circuit 15 can easily select the signal CNT for switching the switching circuits 14 and 17 based on the first to third discrimination result input signals SRE, SATF and SMEP if a microprocessor is used and stores the table representing the chart shown in Figure 2. In this manner, the clock regeneration circuit 11 can obtain the regenerated clock signal CK10 having an optimal phase in accordance with the first or second type of modulation, the type of magnetic tape, and the recording/reproducing mode. According to the above arrangement, when a different type of modulation, a different type of magnetic tape, and a different recording/reproducing mode are used, the lock frequency of the clock regeneration circuit can be switch-controlled correspondingly. Thus, data can be demodulated using the regenerated clock signal which constantly has the correct phase. For this reason, a data reproducing apparatus capable of greatly decreasing the bit error ratio can be easily realised. In the above embodiment, the biphase-mark modulation system or the 8-10 modulation system is used for modulation. However, the present invention is not limited to this, but is applicable to any case in which a magnetic tape on which digital data recorded using a plurality of modulation methods of different recording densities is reproduced. In the above embodiment, the types of magnetic tape and recording/reproducing mode are discriminated in addition to the modulation system, and the lock frequency of the clock regeneration circuit is selected correspondingly, thereby obtaining a regenerated clock signal. However, the present invention is not limited to this. For example, the type of reproducing operation mode of the magnetic tape such as a slow reproducing mode, a double-speed reproducing mode and the like can be added. In addition, the type of recording/reproducing mode or reproducing operation mode of the magnetic tape can be discriminated, and the lock frequency of the clock regeneration circuit can be selected, so that the same effect as in the above embodiment can be obtained. In the above embodiment, the case has been described wherein the present invention is applied to an audio signal system of an 8-mm VTR. However, the present invention is not limited to this. For example, the present invention can be suitably applied to a data reproducing apparatus such as an R-DAT apparatus for reproducing digital data. According to the above description, when a regenerated clock signal included in a picked-up output is obtained using a clock regeneration circuit having a phase locked loop circuit arrangement, the frequency of a reference signal of the phase locked loop and the time constant of a low-pass filter circuit are switched in accordance with the first or second type of modulation. As a result, the PLL lock frequency corresponding to the first or second type of modulation can be obtained, and a regenerated clock signal which has the correct phase can be obtained. Therefore, a data reproducing apparatus can be provided which greatly reduces the bit error ratio even if modulation systems having different recording densities are used.

Claims: Data reproducing apparatus for receiving digital data recorded on a magnetic recording medium (3) by one of first and second types of modulation having different recording densities, obtaining a regenerated clock signal (CK10) based on a clock component included in the received data by a clock regeneration circuit (11) having a phase locked loop circuit arrangement, and demodulating the received data based on the regenerated clock signal (CK10) to reproduce digital data, wherein said clock regeneration circuit (11) comprises: a voltage controlled oscillator (13); a low-pass filter circuit (16A to 16H) for switching a time constant in correspondence with the first or second type of modulation and for providing a control voltage (SV) for controlling said voltage controlled oscillator (13) based on a phase comparison result of the received data and an output reference signal (SVCO) from said voltage controlled oscillator (13); and control means (15) for generating a control signal (CNT) to control switching of said low-pass filter circuit (16A to 16H) and for controlling switching of the frequency of the signal supplied to said low pass filter circuit (16A to 16H) from said voltage controlled oscillator (13) for phase comparison; characterised in that: a resonance circuit (17, 18A to 18H) is associated with said voltage controlled oscillator (13) for switching the frequency of said reference signal (SVCO) output by said voltage controlled oscillator (13) in dependence upon said control signal (CNT); and said control means (15) includes processing means controlled by a stored table (Figure 2) associating address data, including said type of modulation, with a control signal in order to control switching of said resonance circuit (17, 18A to 18H) and said low-pass filter circuit (16A to 16H). Apparatus according to claim 1, wherein when a magnetic tape (3) is used as said magnetic recording medium, said address data includes data representative of the type of the magnetic tape (3). Apparatus according to claim 1, wherein when a magnetic tape (3) is used as said magnetic recording medium, said address data includes data representative of the type of recording/reproducing mode of said magnetic tape (3). Apparatus according to claim 3, wherein the recording/reproducing mode has a mode wherein a plurality of transportation speeds of said magnetic tape (3) are used during a recording operation, and a reproducing operation is performed using a plurality of speeds corresponding to the recording transportation speeds. Apparatus according to claim 1, wherein when a magnetic tape (3) is used as said magnetic recording medium, said address data includes data representative of the type of reproducing operation mode of said magnetic tape (3). Apparatus according to claim 5, wherein the reproducing operation mode is performed at reproducing speeds different from the recording transportation speeds of said magnetic tape (3). Apparatus according to any one of the preceding claims, wherein said control means (15) is responsive to a signal (SBE) indicative of bit error rate in the reproduced digital data in order to discriminate between the first and second types of modulation. Apparatus according to any one of the preceding claims, wherein the digital data is audio data compressed along a time axis, and which is recorded on an audio PCM data area (TRAD) divided from a video signal area (TRVD) to be part of each track (TRA,TRB) successively formed on a tape (3).

Inventors: KANOTA KEIJI C O PATENTS DIVIS, MURABAYASHI NOBORU C O PATENTS, KANOTA, KEIJI C/O PATENTS DIVISION, MURABAYASHI, NOBORU C/O PATENTS DIVISION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: G11B20
IPC codes: G11B5, G11B20, H03L7, H04N5