Solenoid valve control circuit

Abstract: A solenoid valve control circuit [10] for operatively connecting a battery [1] to a solenoid [2] to energize the solenoid to actuate a valve has a coulomb controlling circuit [5] for supplying a controllable electric charge quantity to the solenoid [2].

Description: The present invention relates to a circuit for controlling the operation of a latching solenoid valve, and more particularly to a solenoid valve control circuit which employs a battery as a power supply. Some washroom faucets have an automatic water supply control unit for automatically supplying water by actuating a faucet solenoid valve when the approach of a user to the faucet is detected, and for automatically stopping the water supply by actuating the solenoid valve again when the leaving of the user from the faucet is detected. Generally, such solenoid valve comprises a plunger serving as a valve body and a latching solenoid for driving the plunger when it is energized. As shown in FIG. 4A of the accompanying drawings, it it empirically known that the solenoid valve has a certain characteristic between a power supply voltage Vcc applied to the solenoid and the quantity of electricity Q (i.e., all the electric current flowing through the solenoid, hereinafter referred to as an "electric quantity") through the solenoid. When the power supply voltage Vcc is low, the electric quantity Qn which is required by the solenoid to drive the plunger is larger than the electric quantity Qn that is required by the solenoid to drive the plunger when the voltage Vcc is sufficiently high. Stated otherwise, the electric quantity Qn which is required and sufficient to drive the plunger has to be passed through the solenoid for a relatively long time when the power supply voltage Vcc is lower and for a relatively short time when the power supply voltage Vcc is higher. Where a battery is employed as the power supply for the solenoid valve and the solenoid is to be energized for a constant period of time, a problem arises either when the voltage Vcc of the battery is higher because the battery is new or when the voltage Vcc of the battery is lower because the battery is old or deteriorated. More specifically, if the time for which the solenoid is to be energized is selected to be relatively short in view of new battery conditions, then the solenoid will not be sufficiently energized when the battery voltage Vcc becomes lower and the plunger will not be driven to a desired stroke. Conversely, if the time of energization of the solenoid is selected to be relatively long in view of old or deteriorated battery conditions, then the solenoid will be excessively energized when the battery voltage Vcc becomes higher, resulting in excessive electric power consumption and a shorter battery service life. JP-A-62120006 discloses a circuit for driving a magnet to actuate printing elements of a daisy wheel so that printing pressure is kept constant for a set time, in which the current supplied to the magnet is controlled by the width of a load driving pulse dependent on power source voltage. This circuit does not, however, relate to battery powered latching solenoids for opening and closing valves. The present invention has been made in view of the aforesaid problems with conventional latching solenoid valve control circuits. It is an object of the present invention to provide a latching solenoid valve control circuit which can energize such a solenoid under optimum conditions irrespective of the voltage of a battery applied to the solenoid, so that the electric power from the batter will efficiently be consumed and the service life of the battery will be increased. To accomplish the above object, there is provided in accordance with the present invention a solenoid valve control circuit for operatively connecting a battery to a solenoid to energize the solenoid to actuate a valve, the control circuit including coulomb controlling means for controllably supplying an electric quantity to the solenoid as detailed in claim 1. The above and further objects, details and advantages of the present invention will become apparent from the following detailed description of preferred embodiments thereof, given by way of example only, when read in conjunction with the accompanying drawings. FIG. 1 is a block diagram of a solenoid valve control circuit according to a first embodiment of the present invention; FIG. 2 is a circuit diagram, partly shown in block form, illustrating the solenoid valve control circuit in greater detail; FIG. 3 is a timing chart of output signals or operating conditions of circuit elements in the circuit shown in FIG. 2; FIG. 4A is a graph showing the relationship between a power supply voltage and an electric quantity required by a solenoid; FIG. 4B is a graph showing the relationship between a voltage produced by dividing the power supply voltage,and a sawtooth voltage; FIG. 5 is a block diagram of a solenoid valve control circuit according to a first modification; FIG. 6 is a block diagram showing some of the blocks of FIG. 5 in detail; FIG. 7 is a block diagram illustrating a decision circuit in the solenoid valve control circuit shown in each of FIGS. 1 and 6; FIG. 8 is a timing chart of output conditions of circuit elements in the circuit shown in FIG. 7 ; FIG. 9 is a block diagram of a portion of a solenoid valve control circuit according to a second modification; FIG. 10 is a timing chart of output conditions of circuit elements in the circuit shown in FIG. 9 ; FIG. 11 is a block diagram of a portion of a solenoid valve control circuit according to a third modification; and FIG. 12 is a block diagram of a portion of a solenoid valve control circuit according to a fourth modification. FIG. 1 shows a solenoid valve control circuit 10 according to a first embodiment of the present invention. The control circuit 10 in its entirety constitutes part of an automatic faucet unit (not shown). The control circuit 10 comprises a valve operation decision circuit 3 for determining valve operation, a voltage monitoring circuit 4 for monitoring a power supply voltage, a coulomb controlling circuit 5 for controlling the electric quantity to be supplied to a latching solenoid 2 of a solenoid valve (not shown), and a drive circuit 6 for driving the solenoid 2. The control circuit 10 controllably drives the latching solenoid 2 with electric power supplied from a battery 1 which is employed as the power supply for the control circuit 10. The solenoid 2 may have either a single winding (in which case the opening or closing of the solenoid valve is determined by the direction in which an electric current flows through the solenoid 2) or double windings (i.e., a winding for opening the solenoid valve and a winding for closing the solenoid valve). The power supply voltage Vcc is applied to the decision circuit 3 at all times. The decision circuit 3 is associated with an infrared-radiation light-emitting diode 3a which is intermittently energized to emit infrared radiation by the battery 1, and a phototransistor 3b which detects reflected light to detect whether a user moves toward or away from the automatic faucet device. Dependent on a detected signal from the phototransistor 3b, the decision circuit 3 applies valve opening/closing signals S1, S2 each of which can selectively take ON and OFF states (i.e., "high" and "low") to the drive circuit 6. The automatic faucet unit with the control circuit 10 may be incorporated in various devices. Where the automatic faucet unit is assembled in a washroom faucet, both the signals S1, S2 are OFF when no user is present at the faucet. When an approaching user is detected, only the signal S1 is turned ON and the signal S2 remains OFF. As described later on, the signal S1 is turned OFF after the solenoid 2 has been energized with a suitable electric quantity. Thereafter, when the leaving of the user is detected, only the signal S2 is turned ON and the signal S1 remains OFF. After the solenoid 2 has been energized with a suitable electric quantity, the signal S2 is turned off. Therefore, the signal S1 is a solenoid valve opening signal, and the signal S2 is a solenoid valve closing signal. The light-emitting diode 3a and the phototransistor 3b are located at a suitable position near the faucet. The power supply voltage monitoring circuit 4 monitors the voltage Vcc of the battery 1 and applies a signal dependent on the magnitude of the voltage Vcc to the coulomb controlling circuit 5. When either one of the signals S1, S2 is turned ON, the solenoid valve drive circuit 6 supplies the solenoid 2 with an electric current I of a prescribed polarity to drive a plunger (not shown) serving as a valve body in a given direction. As shown in FIG. 4A, the electric quantity Qn = Qo which is required to open the valve is greater than the electric quantity Qn = Qc which is required to close the valve. In each of the opening and closing of the valve, the electric quantity required by the solenoid 2 to drive the plunger when the voltage Vcc of the battery 1 is low is greater than the electric quantity required by the solenoid 2 to drive the plunger when the battery voltage Vcc is sufficiently high. The horizontal axis of FIG. 4A represents the battery voltage Vcc, and the vertical axis the electric quantity Qn required by the solenoid 2 to drive the plunger. Reference characters Eα, Eβ, Q3 will be described later with reference to FIG. 4A, and reference characters E0 through E4 will be described later with reference to FIG. 10. Generally, the entire electric charge quantity Q (= total electric quantity) passing through the solenoid is expressed by: Q = ∫Idt where I is the electric current flowing through the solenoid and t is the time for which the solenoid is energized. The coulomb controlling circuit 5 applies a detected signal S3 of a "high" level to the decision circuit 3 when the electric quantity Q supplied to the solenoid 2 reaches a prescribed value (= Qn = Qo or Qc). The solenoid valve opening/closing signals S1, S2 are also supplied to the coulomb controlling circuit 5, which varies output conditions for the detected signal S3 based on the signals S1, S2. In response to the detected signal S3 from the coulomb controlling circuit 5, the decision circuit 3 turns OFF the one of the signals S1, S2 which is ON at the time, whereupon the drive circuit 6 de-energizes the solenoid 2. FIG. 2 shows the solenoid valve control circuit 10, particularly the voltage monitoring circuit 4 and the coulomb controlling circuit 5, in detail. The decision circuit 3 comprises a plurality of logic circuits, for example, and each time it detects the approach or leaving of a user, it turns on a power supply switch 7 to apply the power supply voltage Vcc to the voltage monitoring circuit 4 and the coulomb controlling circuit 5. The drive circuit 6 is in the form of a bridge circuit comprising four power transistors, for example. The solenoid 2 is connected between the two output terminals of the bridge circuit. One of the two input terminals of the bridge circuit is connected to the positive terminal of the battery 1, whereas the other input terminal of the bridge circuit is grounded through a resistor. The signals S1, S2 are supplied to a pair of coacting power transistors which form opposite sides of the bridge circuit. While the solenoid 2 is being energized, part of the current I flowing through the solenoid 2 is supplied to a current amplifying circuit 5a of the coulomb controlling circuit 5 (Actually, a voltage signal similar to the solenoid current I is supplied to the amplifying circuit 5a). The current supplied to the amplifying circuit 5a is supplied as a charging current i through resistors R1, R2 to a monitoring capacitor 5d. Feedback signals are applied from those terminals of the resistors R1, R2 which are closer to the capacitor 5d than to the amplifying circuit 5a through switches 5b, 5c. The switches 5b, 5c are mutally exclusively closed by an output signal from the voltage monitoring signal 4. While only the switch 5b is closed, the current gain of the amplifying circuit 5a is maintained at k1, and while only the switch 5c is closed, the current gain of the amplifying circuit 5a is maintained at k2. k represents a prescribed gain determined by the circuit arrangement, and the current gains k1, k2 are selected such that k1 = k/R1 and k2 = k/(R1 + R2), and hence k1 > k2. Therefore, as described later on, the average current gain of the amplifying circuit 5a is varied by the closing and opening of the switches 5b, 5c dependent on variations in the power supply voltage Vcc. The charging current i which flows while only the switch 5b is closed is indicated by: i = k1·I = (k/R1)·I = k·I/R1. The charging current i which flows while only the switch 5c is closed is indicated by: i = k2·I = (k/(R1 + R2))·I = k·I/(R1 + R2). When the power supply switch 7 is turned ON, a sawtooth oscillator 4a of the voltage monitoring circuit 4 starts operating to supply a sawtooth voltage Vsa as a reference voltage to a comparator 4b. The sawtooth oscillator 4a may be replaced with a triangle generator. When the power supply switch 7 is turned ON, the power supply voltage Vcc is divided by resistors R3, R4, and a divided voltage V1 is applied to the comparator 4b. The comparator 4b compares the applied voltage V1 with the reference voltage Vsa. While V1 > Vsa, the comparator 4b issues an output signal of a "high" level, and while V1 < Vsa, the comparator 4b issues an output signal of a "low" level. The output signal from the comparator 4b is applied directly to one of the switches 5b of the coulomb controlling circuit 5 and via an inverter 5e to the other switch 5c. The switches 5b, 5c are closed only when they are supplied with a high-level signal, and hence they are exclusively or alternatively closed. More specifically, while V1 > Vsa, the switch 5b is closed and the amplifying circuit 5a has the current gain kl, and while V1 < Vsa, the switch 5c is closed and the amplifying circuit 5a has the current gain k2 during which time the charging current i is lower. Denoted at F in FIG. 2 is an input line for closing the valve through a manual override. As long as the current I flows through the solenoid 2, the capacitor 5d is continuously charged and a voltage V3 at the input terminal of the capacitor 5d progressively rises. The voltage V3 is applied as an input voltage to a comparator 5f which is supplied with a reference voltage Vr. While V3 < Vr, the comparator 5f issues an output signal of a "low" level, and when V3 > Vr, the comparator 5f issues an output signal of a "high" level. The high-level signal from the comparator 5f is sent as the de-energizing signal S3 to the decision circuit 3. The reference voltage Vr is determined according to the electric quantity Qn required by the solenoid 2, and thus has different values when the valve is to be opened (i.e., when the signal S1 is turned ON) and when the valve is to be closed (i.e., when the signal S2 is turned ON). The reference voltage Vr is selected to be equal to the voltage V3 across the capacitor 5d when the required electric quantity Qn (= Qo, Qc) has flowed through the solenoid 2 in the case where the power supply voltage Vcc is sufficiently high. The reference voltage Vr is produced by dividing, with resistors R5, R6, R7 and switches 5h, 5i, an output voltage from a constant voltage circuit or reference voltage generator 5g to which the power supply voltage Vcc is applied through the power supply switch 7. The switches 5h, 5i are closed respectively by the signals S1, S2. As described above with reference to FIG. 4A, the electric quantity Qn (= Qo) required by the solenoid 2 to open the valve is greater than the electric quantity Qn (= Qc) required by the solenoid 2 to close the valve. Therefore, when opening the valve, the switch 5h is closed by the signal S1 to supply a relatively high divided voltage Vr as a reference voltage to the comparator 5f. When closing the valve, the switch 5i is closed by the signal S2 to supply a relatively low divided voltage Vr as a reference voltage to the comparator 5f. Regardless of whether the valve is opened or closed, the voltage V3 across the capacitor 5d becomes equal to the reference voltage Vr when the electric quantity Q passing through the solenoid 2 reaches the required electric quantity Qn. At this time, the comparator 5f sends the high-level de-energizing signal S3 to the decision circuit 3. At the same time as the decision circuit 3 receives the signal S3, it turns OFF the one of the signals S1, S2 which is ON at the time, opens the power supply switch 7, and applies an output signal S4 of a "high" level to a discharging switch 5j. The energization of the solenoid 2 is stopped, the circuits 4, 5 are de-energized, and the capacitor 5d is discharged, readying the control circuit 10 for a next cycle of operation. As enclosed by the broken lines in FIG. 2, the voltage monitoring circuit 4 is constructed from the circuit elements 4a, 4b and the resistors R3, R4, and the coulomb controlling circuit 5 is constructed from the circuit elements 5a through 5j and the resistors R1, R2, R5, R6, R7. FIG. 3 shows a timing chart of output signals or operating conditions of the circuit elements illustrated in FIG. 2. Those output signals shown in a lefthand area A in FIG. 3 are produced when the voltage Vcc of the battery 1 is sufficiently high, and those output signals shown in a righthand area B in FIG. 3 are generated when the battery voltage Vcc is lower. FIG. 3 only illustrates the output signals in the areas A, B for opening the valve. The output signals produced for closing the valve are similar and are not shown. The charts of FIG. 3 represent the following conditions: (a) The operating condition of the decision circuit 3, i.e., the manner in which the circuit 3 detects the approach of a user. (b) The length of a processing time required to open the valve. (c) The opening and closing condition of the power supply switch 7. (d) The ON/OFF condition of the valve opening signal S1, i.e., the driving condition of the drive circuit 6. The drive circuit 6 is energized about 1 msec. after the power supply switch 7 is closed as shown at (c), and de-energized substantially at the same time that the power supply switch 7 is opened. (e) The current I flowing through the solenoid 2. (f) The battery voltage Vcc. In the area B, since the internal resistance of the battery 1 is high, the voltage Vcc considerably drops when the solenoid 2 is energized. (g) The output voltage Vsa from the sawtooth generator 4a. The waveform and peak value of the voltage Vsa remain unchanged in the areas A, B. (h) The output condition of the comparator 4b, which indirectly represents the opening and closing condition of the switch 5b. (i) The opening and closing condition of the switch 5c, which is a reversal of the condition of (h). With respect to the above charts (f), (g), (h), and (i), while the divided voltage V1 is higher than the sawtooth voltage Vsa, only the switch 5b is closed, and while the divided voltage V1 is lower than the voltage Vsa, only the switch 5c is closed. (j) The voltage V3 for charging the capacitor 5d. (k) The output condition of the comparator 5f, i.e., the output condition of the de-energizing signal S3. (ℓ) The time required for the decision circuit 3 to end the energization of the solenoid 2, i.e., the time in which the signal S4 is rendered "high" in level to close the discharging switch 5j for a time long enough to discharge the capacitor 5d. In the area A, the switch 5b remains continuously closed since V1 > Vsa at all times. Therefore, while the solenoid 2 is being energized, the charging current i = k1·I flows into the capacitor 5d. In the area B, the switches 5b, 5c are exclusively closed based on the magnitude relationship between the sawtooth voltage Vsa and the divided voltage V1. As described above, the current gain of the amplifying circuit 5a is k1 when the switch 5b is closed and it is k2 when the switch 5c is closed. Therefore, the average gain k10 of the amplifying circuit 5a in the area B can be determined as follows: FIG. 4B is a graph showing, at an enlarged scale, the charts (f) and (g) in overlapping relationship in the area B of FIG. 3. The reference characters Vsa(max) and Vsa(min) represent maximum and minimum values of the sawtooth voltage Vsa, and τ0 indicates the cyclic period of the sawtooth voltage Vsa. If the period in which V1 < Vsa within one cycle of the voltage Vsa is τ (0 ≦ τ ≦ τ0), then the average gain k10 of the amplifying circuit 5a can be expressed by: k10 = (1 - (τ/τ0))·k1 + (τ/τ0)·k2 Since 0 ≦ τ ≦ τ0 and k1 > k2 as described above, k1 ≧ k10 ≧ 2. Particularly, when V1 ≧ Vsa(max), since τ = 0, k10 = k1. When V1 ≦ Vsa(min), since τ = τ0, k10 = k2 Within the range of Vsa(min) ≦ V1 ≦ Vsa(max), because the period τ is in inverse proportion to the divided voltage V1, the average gain k10 is proportional to the divided voltage V1. In the area B, therefore, the average gain k10 is proportional to the power supply voltage Vcc, and hence as the voltage Vcc is lowered, so is the average gain k10. When the power supply voltage Vcc is relatively high, i.e., in the range of Vcc > Eα, in FIG. 4A, the electric quantity Qo required by the solenoid 2 to open the valve is of a substantially constant value Q1. When the power supply voltage Vcc is relatively low, i.e., Vcc = Eβ, the electric quantity Qo required by the solenoid to open the valve is of a value Q3. When the power supply voltage Vcc is in the range of Eβ ≦ Vcc ≦ Eα, Q1 ≦ Qo ≦ Q3. The range Eβ ≦ Vcc ≦ Eα corresponds to the area B in FIG. 3. The control circuit 10 is arranged such that when the power supply voltage Vcc is Eα and Eβ, the divided voltage V1 is equal to the maximum value Vsa(max) and the minimum value Vsa(min), respectively, of the sawtooth voltage Vsa. The values of the resistors R1, R2, the value of the reference voltage Vr supplied to the comparator 5f, and the capacitance of the capacitor 5d are selected such that when Vcc = Eα, the electric quantity Q supplied to the solenoid 2 is Q = Q1 and when Vcc = Eβ, Q = Q3. Therefore, Q = Q1 when Vcc > Eα. Since the average gain k10 is proportional to the power supply voltage Vcc when Eβ ≦ Vcc ≦ Eα, as described above, the electric quantity Q supplied to the solenoid 2 is controlled so as to be substantially equal to Qo in FIG. 4A. The aforesaid description has been directed to the opening of the valve. For closing the valve, the electric quantity Q supplied to the solenoid 2 in the area B is controlled so as to be equal to Qc in FIG. 4A since only the reference voltage Vr supplied to the comparator 5f is lower. As is apparent from the above description, the electric quantity Q supplied to the solenoid 2 is controlled so as to be dependent on the power supply voltage Vcc by the solenoid valve drive circuit 10. More specifically, the electric quantity Q is controlled so as to be equal to Qo, Qc shown in FIG. 4A. Therefore, the solenoid 2 is energized in an optimum fashion regardless of whether the battery voltage Vcc is high or low. As a consequence, the electric power from the battery 1 is efficiently consumed, and the service life of the battery 1 is prolonged. FIGS. 5 and 6 show a solenoid valve control circuit 20 according to a first modification of the present invention. Those components in FIGS. 5 and 6 which are identical to those of the control circuit 10 of the first embodiment are denoted by identical reference numerals, and will not be described. The control circuit 20 has a coulomb controlling circuit 5 comprising an energizing time determining circuit 50, a counter 51, and a switch driving circuit 52. The energizing time determining circuit 50 receives an analog output V1′ from the voltage monitoring circuit 4 and determines a time t for which the solenoid 2 is to be energized, based on the analog output V1′ and the valve opening/closing signals S1, S2 from the decision circuit 3. The counter 51 counts the determined energizing time t. While the counter 51 is counting the energizing time t, the switch driving circuit 52 closes a switch 60 to energize the solenoid 2. The switch 60 comprises a directional element such as a bridge circuit or the like for energizing the solenoid 2. The analog output V1′ from the voltage monitoring circuit 4 is produced by dividing the power supply voltage Vcc at a prescribed ratio. As shown in FIG. 6, the energizing time determining circuit 50 comprises an A/D converter 50a for converting the analog output V1′ from the voltage monitoring circuit 4 into a digital signal V1″, and a memory 50b for determining an energizing time t in response to the digital signal V1″ and the valve opening/closing signals S1, S2. The memory 50b has two memory maps which can be selected by the signals S1, S2, respectively. Each of the memory maps stores data on required energizing times t based on the characteristics of the required electric quantity Qn and the time-base current characteristics of the solenoid 2. The digital signal V1″ is applied as an address signal to the memory 50b to read data on the required energizing time t from the memory map which has been selected by the signal S1 or S2. The electric quantity Q supplied to the solenoid valve 2 can be controlled so as to be of a magnitude dependent on the power supply voltage Vcc by the solenoid valve control circuit 20. Accordingly, the solenoid 2 is energized in an optimum fashion regardless of whether the battery voltage Vcc is high or low. As a consequence, the electric power from the battery 1 is efficiently consumed, and the service life of the battery 1 is prolonged. The circuit components 50, 51 of the control circuit 20 may be replaced with a PWM (Pulse Width Modulation) circuit responsive to the output from the power supply voltage monitoring circuit for producing pulses of a duration inversely proportional to the power supply voltage Vcc, and an output signal from the PWM circuit may be supplied to the switch driving circuit 52. In this case, the PWM circuit doubles as a timer circuit. Thus, a pulse generator with the pulse duration variable by the output from the power supply voltage monitoring circuit may be used as a timer. FIG. 7 shows one detailed circuit arrangement for the decision circuit 3, and FIG. 8 is a timing chart showing output conditions of circuit components in the circuit 3. The circuit 3 normally generates the valve opening/ closing signals S1, S2 based on signals S01, S02 which serve as origins of the signals S1, S2. The signals S01, S02 have waveforms as shown in the chart (d) in FIG. 3 . When the de-energizing signal S3 is generated, these signals S01, S02 are changed to a "low" level by a non-illustrated logic circuit. If no de-energizing signal S3 is produced due for example to a failure of the coulomb controlling circuit 5 even when the signal S1 or S2 is generated, then the circuit 3 temporarily stops the issuance of the signals S1, S2. Thereafter, the circuit 3 produces the signals S1, S2 again. If a de-energizing signal S3 is still not produced even by the regenerated signals S1, S2, the circuit 3 forcibly closes the valve and stops its controlling operation on the solenoid 2. More specifically, the origin signals S01, S02 go high in level when the approach/leaving of a user is detected. The origin signals S01, S02 are applied respectively to D input terminals of F/F (flip-flop) circuits 301, 302 which serve as latch circuits. The signals S01, S02 are also applied to an OR gate 303, the output signal of which is applied to a CLK input terminal of the F/Fs 301, 302. Therefore, when either one of the origin signals S01, S02 goes high, both the F/Fs 301, 302 are operated, and a high-level output signal is issued from the Q output terminal of one of the F/Fs to which the high-level signal has been applied. Specifically, when the signal S01 goes high, the high-level output signal is issued only from the Q terminal of the F/F 301. When the signal S02 goes high, the high-level output signal is issued only from the Q terminal of the F/F 302. The output condition of the Q terminals of the F/Fs 301, 302 is latched until the signals S01, S02 go high again after they have gone low. The F/Fs 301, 302 are thus triggered by positive-going edges of the signals applied to their CLK input terminals. The signals S01, S02 are also applied to an OR gate 304, the output of which is applied to a START terminal of a timer 305. Therefore, the output signal from the OR gate 304 goes high when at least one of the signals S01, S02 goes high, starting the timer 305. The output signal from the timer 305 is normally low in level. When the timer 305 reaches a time-out condition after it has counted the output signal from the OR gate 304 for a prescribed period of time, the timer 305 continuously issues a signal To of a high level. When a retry signal Re of a high level from a retry commander 306 is applied to a RESET terminal of the timer 305 under this condition, the output signal from the timer 305 goes low and starts counting the output signal from the OR gate 304. Times for which the timer 305 counts the input signal in response to signals applied to the START and RESET terminals thereof are equal to each other. These counting times are selected to be longer than the energizing time Tb shown in FIG. 3 at (j). The output signal from the timer 305 which is normally low is applied to input terminals of AND gates 307, 308 through an inverter 309 to enable the AND gates 307, 308. The other input terminals of the AND gates 307, 308 are supplied with the output signals from the F/Fs 301, 302. The de-energizing signal S3 is applied to the STOP terminals of the timer 305 and the retry commander 306 for stopping the operation of the timer 305 and the retry commander 306. Therefore, insofar as the de-energizing signal S3 is normally generated, the timer 305 does not produce a high-level output signal. Normally, the output signals from the AND gates 307, 308 are thus equal to the origin signals S01, S02, respectively. The high-level time-out signal To from the timer 305 is applied to the retry commander 306. Simultaneously in response to the time-out signal To, the retry commander 306 applies the high-level retry signal Re to the RESET terminal of the timer 305 and an input terminal of an AND gate 310. The output terminal of the AND gate 310 thus issues a failure signal Tr of a high level only when the timer 305 issues the time-out signal To after the retry signal Re has been issued. The retry command 306 may comprise a latch circuit. The output signal from the AND gate 310 is supplied through an inverter 313 to an input terminal of an AND gate 311 and directly to an input terminal of an OR gate 312. The other input terminals of the AND gate 311 and the OR gate 312 are supplied with the signals S01, S02 from the AND gates 307, 308, respectively. Since the output signal from the AND gate 310 is low in level under normal condition, the output signal from the AND gate 311 is equal to the signals S01, S02 under normal condition. The output signal from the AND gate 310 is sent to a trouble display circuit 314. When the failure signal Tr is issued from the AND gate 310, the trouble display circuit 314 indicates a failure condition through a pilot lamp or the like to show that the control circuit is suffering a failure somewhere therein. The output signal from the AND gate 310 is also applied to a START terminal of a timer 317. The timer 317 normally continues to issue a low-level output signal. When the high-level failure signal Tr is applied to the START terminal of the timer 317, the timer 317 counts a prescribed period of time, and then continuously issues an output inhibit signal In of a high level. The time interval which is counted by the timer 317 is selected to be longer than the time counted by the timer 305. The output signal from the timer 317 is applied via an inverter 318 to input terminals of AND gates 315, 316, the other input terminals of which are supplied with the output signals from the AND gate 311 and the OR gate 312. Normally, the output signal from the timer 317 is low in level, and the output signals from the AND gates 315, 316 are the same as the origin signals S01, S02, respectively, under normal condition. The output signals from the AND gates 315, 316 are supplied as the valve opening/closing signals S1, S2 to the coulomb controlling circuit 5 and the solenoid valve drive circuit 6, respectively. Operation of the control circuit 3 shown in FIG. 7 will hereinafter be described with reference to FIG. 8. The timing chart of FIG. 8 shows the output conditions of the circuit elements indicated by the corresponding reference characters, and illustrates a failure condition of the control circuit 3 due to trouble of the coulomb controlling circuit 5, for example. As described above, the origin signals S01, S02 are generated by the non-illustrated logic circuit. Indicated at 316, S2(Tr) is a valve closing override signal produced by the failure signal Tr, and indicates that the signal functions in the same manner as the signal S2. Denoted at St in FIG. 8 is a time at which the timers 305, 317 start counting time. When either the origin signal S01 or S02 goes high in level, the corresponding one of the valve opening/closing signals S1, S2 goes high, starting to energize the solenoid 2. At the same time, the START terminal of the timer 305 is supplied with a high-level signal through the OR gate 304 to start counting a prescribed period of time (> Tb). Normally, the de-energizing signal S3 is generated before the timer 305 reaches a time-out condition, the origin signals S01, S02 go low, and the timer 305 and the retry commander 306 stop their operation. These conditions are not illustrated in FIG. 8. In the event that no de-energizing signal S3 is produced upon elapse of the energizing time, e.g., Tb, for some reason, the timer 305 reaches a time-out condition. The timer 305 continuously issues a high-level time-out signal To. Therefore, one of the input terminals of each of the AND gates 307, 308 is supplied with a low-level signal from the inverter 309, with the result that the output signals from the AND gates 307, 308 go low again. The conditions of the origin signals S01, S02 are maintained by the Q output signals from the F/Fs 301, 302. The time-out signal To is sent to the retry commander 306 to enable the latter to issue a retry signal Re after it has closed the discharging switch 5j for a prescribed period of time with a delay circuit (not shown). The retry signal Re is applied to the RESET terminal of the timer 305, which then issues a low-level signal and restarts counting a prescribed period of time (Tb <). Since the output signal from the timer 305 goes low, the AND gates 307, 308 are enabled again to issue the condition of the origin signals S01, S02 which are held in the F/Fs 301, 302. While the retry signal Re is also applied to the AND gate 310, the output signal from the timer 305 remains low. The signals from the AND gates 307, 308 are finally issued as the valve opening/closing signals S1, S2 from the AND gates 315, 316, respectively. This condition is indicated by a second "high" state of the chart represented by (307, 308) S1, S2 in FIG. 8, i.e., a retry condition. After the signals S1, S2 have been issued again, the origin signals S01, S02 go low if the de-energizing signal S3 is produced before the time-out condition of the timer 305, and the operation of the timer 305 and the retry commander 306 is stopped. This condition is not illustrated in FIG. 8. If no de-energizing signal S3 is produced upon elapse of the energizing time, e.g., Tb, for some reason, then the timer 305 reaches a time-out condition. The timer 305 continues to issue a high-level time-out signal To again. Therefore, the output signals from the AND gates 307, 308 go low, thus inhibiting the transmission of the origin signals S01, S02 past the AND gates 307, 308. As a result, the output of the valve opening/closing signals S1, S2 is inhibited. Since the retry signal Re is maintained at the high level at this time, the high-level failure signal Tr is issued from the AND gate 310. The failure signal Tr is sent to the trouble display circuit 314, which then continuously indicates the failure condition. The failure signal Tr is also applied to the START terminal of the timer 317 to enable the latter to start counting a prescribed period of time. Since the output signal from the timer 317 is low until it reaches a time-out condition, a high-level signal is applied to one input terminal of the AND gate 316 to enable the latter. The failure signal Tr is also fed to the OR gate 312. Therefore, the output signal from the OR gate 312 goes high, and is issued as the valve closing signal S2 (Tr) caused by the failure signal Tr. The solenoid valve drive circuit 6 closes the valve in response to the signal S2 (Tr). When the timer 317 has completed the counting of the prescribed time, it issues a high-level output inhibit signal In to disable the AND gates 315, 316, so that the issuance of the valve closing signal S2 (Tr) is inhibited. The timer 317 subsequently continues to issue the output inhibit signal In to inhibit the issuance of the valve opening/closing signals S1, S2. Even after the forced closing of the valve with the override signal S2 (Tr) has been brought to an end, the failure signal Tr and the output inhibit signal In are maintained to inhibit the solenoid 2 from being energized and to indicate the failure. With the aforesaid arrangement of the decision circuit 3, any wasteful consumption of the electric energy stored in the battery, which would otherwise be caused by some failure of the control circuit, can be avoided. Even if no de-energizing signal S3 is obtained within a prescribed period of time, the valve opening/closing signals S1, S2 are automatically rendered low, thus effectively preventing a reverse latching phenomenon in which if the energizing time is long, the valve which has once been opened is closed again because of solenoid characteristics exhibited when closing the solenoid. Since the circuit 3 informs the operator of a failure condition, the operator can immediately find such a failure of the control circuit. In addition, the valve is forcibly closed when the circuit 3 determines that the control circuit suffers a failure. Accordingly, the control circuit is associated with an effective fail-safe system. The circuit 3 does not regard a single time-out condition of the timer 305 as a failure, but tries to energize the solenoid again through the retry commander 306 should such a time-out condition occur. This prevents the control circuit from being de-energized by a single extrinsic error which may be caused by noise or the like. A solenoid valve control circuit 400 according to a second modification will be described with reference to FIGS. 9 and 10. Circuit elements 401, 402, 403, 404 illustrated in FIG. 15 are added to the control circuit 10, described above for detecting a drop in the battery voltage Vcc. A voltage produced by dividing the output voltage from the reference voltage generator 5g at a prescribed ratio is applied as a reference voltage Th to a comparator 401, the reference voltage Th providingathreshold value. The battery voltage Vcc is divided into an input voltage Vcc' which is applied to the comparator 401. When the input voltage Vcc' is higher than the threshold voltage Th, the comparator 401 issues a high-level signal to one input terminal of an AND gate 403 through an inverter 402. The valve opening/closing signals S1, S2 are applied to an OR gate 404, the output signal of which is applied to the other input terminal of the AND gate 403. Thus, while either the signal S1 or S2 is high in level, the AND gate 403 is enabled to issue an output signal. That is, the AND gate 403 can issue an output signal only when the solenoid 2 is energized. If the voltage Vcc' drops lower than the threshold voltage Th while either the signal S1 or S2 is high and the solenoid 2 is being energized, the output signal from the comparator 401 goes low. The low-level signal from the comparator 401 is applied through an inverter 402 as a high-level signal to the AND gate 403. Consequently, the AND gate 403 issues a signal S5 of a high level which represents that the battery voltage Vcc drops lower than a prescribed voltage level. FIG. 10 shows the output condition of the voltage drop signal S5. The voltage drop signal S5 is delivered to a non-illustrated circuit so as to be processed thereby in a predetermined manner. For example, the signal S5 is sent to a latch circuit (not shown) which produces an output signal to enable a liquid crystal display, for example, to display the reduction in the battery voltage. The signal S5 may be employed to perform the same function as the failure signal Tr shown in FIGS. 7 and 8. A drop in the battery voltage Vcc when there is no load on the battery can be detected even by dispensing with the OR gate 404 and the AND gate 403. It is in practice preferable, however, to detect any drop in the voltage Vcc when the battery is loaded by energizing the solenoid 2 as illustrated. While only one threshold Th is employed in the above modification, two threshold values may be established, with the higher threshold value used for warning the operator about a voltage drop and the lower threshold value for de-energizing the entire control system. FIG. 11 illustrates a solenoid valve control circuit 500 according to a third modification of the present invention. Circuit components 501, 502, 503 shown in FIG. 11 are added to the control circuit 10 for determining that the battery is used up when the solenoid 2 is energized a number of times in excess of a predetermined number. The solenoid opening/closing signals S1, S2 are applied to an OR gate 501, the output signal of which is applied to a counter 502 to count the number of times which the solenoid 2 is energized. The count is then applied as a digital signal to a digital comparator 503. A reference count applied to the digital comparator 503 is set to a prescribed value (= an integer) through a jumper switch J. The reference count is selected to be a number of times the solenoid 2 is energized to use up the electric energy stored in the battery. The digital comparator 503 issues an output signal S6 of a high level when the count exceeds the reference count. The signal S6 is a signal which statistically or indirectly represents that the battery voltage Vcc drops below a prescribed value. The voltage drop signal S6 is sent to a certain circuit (not shown) so as to be processed thereby. The signal S6 is practically equivalent to the voltage drop signal S5 described above, and the manner of utilizing the signal S6 is also the same as the manner of utilizing the signal S5. A solenoid valve control circuit 600 in accordance with a fourth modification of the present invention is shown in FIG. 12. Circuit elements 401, 402, 403, 404 (or 501), 502, 503 shown in FIG. 12 are added to the control circuit 10. Those circuit elements in FIG. 12 which are identical to those of the control circuits 400 and 500 will not be described below. The control circuit 600 simultaneously performs the functions of the control circuits 400, 500. However, the signals S5, S6 are applied to an OR gate 601, which produces an output signal S7 of a high level when the signal S5 or S6 goes high. The signal S7 is applied to a certain circuit and processed thereby. The signal S7 is produced when the solenoid 2 has been energized a number of times in excess of a predetermined number or when the battery voltage Vcc drops below a prescribed value. By using the signal S7 as a battery consumption signal, the battery can reliably be replaced with a new one before the battery power is completely used up. The aforesaid modifications of the invention may be combined in various combinations.

Claims: A solenoid control circuit (10;20) for operatively connecting a battery (1) to a solenoid (2) to energize the solenoid (2), said control circuit including: coulomb controlling means (4,5) for supplying a controllable electric charge quantity (Q) to the solenoid (2), said electric charge quantity (Q) corresponding to the voltage (Vcc) of the battery (1); characterised in that: said solenoid is a latching solenoid (2) having a plunger for opening and closing a valve, and in that said electric charge quantity (Q) is controlled to the value required (Qn, Qo, Qc) to energize said latching solenoid 15 (2) to move the solenoid plunger for opening and closing the valve. A solenoid valve control circuit (10) according to claim 1, further comprising: a decision circuit (3) for producing an energizing signal (S1, S2) indicating that said battery (1) is to be connected to said solenoid (2) under a prescribed condition; and a solenoid valve drive circuit (6) responsive to said energizing signal (S1, S2) for operatively connecting said battery (1) to said solenoid (2) to energize said solenoid (2), and wherein said coulomb controlling means (4, 5) comprises: a power supply voltage monitoring circuit (4) for monitoring the voltage (Vcc) of said battery (1) and producing a signal (f; g) corresponding to the battery voltage (Vcc); and a coulomb controlling circuit (5) for monitoring the electric quantity (Q) supplied from said battery (1) to said solenoid (2) and for producing a de-energizing signal (S3) based on the signal (f; g) from said power supply voltage monitoring circuit (4) when the electric quantity (Q) supplied to said solenoid (2) is equal to said required electric quantity (Qn) corresponding to said battery voltage (Vcc). A solenoid valve control circuit (10) according to claim 2, wherein said coulomb controlling circuit (5) comprises: an amplifying circuit (5a, 5b, 5c, R1, R2) connected to said solenoid (2) for amplifying an electric current (I) to be supplied to the solenoid (2); a capacitor (5d) chargeable to a prescribed charge level (C.V3) in response to the amplified current (k1.I, k2.I) from said amplifying circuit (5a, 5b, 5c, R1, R2) ; and a comparator (5f) for comparing a voltage (V3) across said capacitor (5d) with a reference voltage (Vr) and producing said de-energizing signal (S3) when the voltage (V3) across said capacitor (5d) is equal to said reference voltage (Vr); and said amplifying circuit (5a) being responsive to said signal (f; g) corresponding to the battery voltage from said power supply voltage monitoring circuit (4) for amplifying said electric current to be supplied to said solenoid (2) at a gain (k10) proportional to said battery voltage (Vcc). A solenoid valve control circuit (10) according to claim 2 or 3, wherein said amplifying circuit (5a, 5b, 5c, R1, R2) amplifies said electric current (I) at a constant gain (k1) when said battery voltage (Vcc) is relatively high, said reference voltage (Vr) of said comparator (5f) being set to be equal to the voltage (V3) across said capacitor (5d) when said required electric quantity (Qn = Q1, Q2) is supplied to said solenoid (2) in case said battery voltage (Vcc) is relatively high. A solenoid valve control circuit (10) according to claim 2, 3 or 4, wherein said de-energizing signal (S3) from said coulomb controlling circuit (5) is supplied to said decision circuit (3), said decision circuit (3) being responsive to said de-energizing signal (S3) for stopping the generation of said energizing signal (S1, S2). A solenoid valve control circuit (20) according to claim 1, further comprising: a decision circuit (3) for producing an energizing signal (S1, S2) indicating that said battery (1) is to be connected to said solenoid (2) under a prescribed condition, and wherein said coulomb controlling means (4, 5, 60) comprises: a power supply voltage monitoring circuit (4) for monitoring the voltage (Vcc) of said battery (1) and producing a signal (V1') corresponding to the battery voltage (Vcc); an energizing time decision circuit (50) for determining an energizing time (t) in which said solenoid (2) is to be energized, in response to said energizing signal (S1, S2) from said decision circuit (3) and said signal (V1') corresponding to said battery voltage from said power supply voltage monitoring circuit (4); and a drive circuit (51, 52, 60) for connecting said battery (1) to said solenoid (2) to energize said solenoid (2) for said determined energizing time (t). A solenoid valve control circuit 7 according to any preceding claim wherein said decision circuit (3) comprises a timer circuit (305) for producing a time-out signal (To) to stop the generation of said energizing signal (S1, S2) when said de-energizing signal (S3) is not produced upon elapse of a predetermined period of time (> Tb) after said energizing signal (S1, S2) has been produced. A solenoid valve control circuit 7 according to claim 7, wherein said decision circuit (3) further comprises a retry commander (306) for producing a retry signal (Re) to generate said energizing signal (S1, S2) once more when said time-out signal (To) is produced by said timer circuit (305). A solenoid valve control circuit 7 according to claim 8, wherein said decision circuit (3) further comprises a failure determining circuit (310 - 318) for producing a failure signal (Tr) to stop controlling said solenoid (2) when said de-energizing signal (S3) is not produced upon elapse of a predetermined period of time (> Tb) after said energizing signal (S1, S2) has been produced again based on said retry signal (Re). A solenoid valve control circuit 7 according to claim 9, wherein said failure determining circuit (310 - 318) comprises a valve closing override circuit (312, 316 - 318) for forcibly closing said valve, and a trouble display circuit (314) for indicating a failure condition. A solenoid valve control circuit 7 according to any of claims 2 to 7, wherein said decision circuit (3) further comprises a failure determining circuit (304 - 318) for producing a failure signal (Tr) to stop controlling said solenoid (2) when said de-energizing signal (53) is not produced upon elapse of a predetermined period of time after said energizing signal (S1, S2) has been produced. A solenoid valve control circuit (400) according to any preceding claim, further comprising: a voltage drop detecting circuit (401, 402, 403, 404) for detecting a drop in the voltage (Vcc) of said battery (1) below a predetermined value (Th) and for producing a voltage drop signal (S5) indicative of the detected voltage drop. A solenoid valve control circuit (500) according to any preceding claim, further comprising a counting circuit (501, 502, 503) for detecting that the number of times said solenoid (2) is energized by said battery (1) exceeds a predetermined number and for producing a voltage drop signal (S5) indicative of the detected number of times.

Inventors: DOUKE TAKAHIRO, EKI TOSHIO, IKEDA TOSHIO, YOSHIDA TAKAO, DOUKE, TAKAHIRO, EKI, TOSHIO, IKEDA, TOSHIO, YOSHIDA, TAKAO
Applicants: TOTO LTD, TOTO LTD.
Application year: 1988
Main classification: H01F7
IPC codes: H01F7