High-security integrated-circuit card

Abstract: An IC card having one-chip microcomputer (2), a memory (3) and an address bus (4) and a data bus (5) for coupling the microcomputer (2) and memory (3), all built in a card-shaped body. A plurality of terminals (12) for coupling microcomputer (2) to a terminal device are provided on the surface of the card. Microcomputer (2) includes a CPU 6, a timer (7), and an internal interrupt signal bus 8, through which the CPU 6 and timer (7) are coupled together. Timer (7) is always functioning during the operation of CPU 6 and includes a counter-­ register (13) for incrementing a count value and a timer control status register (14). The register (14) has an overflow flag (16) and interrupt enable flag (17). The overflow flag (16) is set by counter-register (13) when an overflow occurs in this register (13), and it is reset at a given timing by CPU 6. The interrupt enable flag (17) indicates the enable/disable of an internal interrupt for CPU 6, and is set or reset at a given timing by CPU 6. Overflow flag (16) and interrupt enable flag (17), which are coupled to an interrupt signal generator (18), are both set, an internal interrupt signal is sent to CPU 6 to generate an inter­ nal interrupt. Upon occurrence of the internal inter­ rupt CPU 6 starts returning a processing result of a processing command to the external device.

Description: The present invention relates to an integrated-circuit (IC) card which has an electronic circuit including a microcomputer, memory, etc. within a card type or package type body. An IC card is designed such that it receives data from an external terminal device through its terminals provided on the surface, processes the data, stores it in a memory if needed, and returns the processing result to the terminal device. An example of data processing executed in the IC card is a personal identification number (PIN) verification, which is done prior to the actual use of an IC card in order to confirm whether or not a user is a rightful holder of the card. Generally, a four-digit personal identification number is given in advance to each IC card and a user enters the number to a terminal device. The PIN is sent to the IC card for comparison with the correct card-holder's PIN stored in advance in the card, and the verification result is sent to the terminal device from the card. Here, the verification result only indicates that the entered PIN is either correct or not. In general, when an incorrect digit is found during a digit by digit verification, the verification is stopped and no further verification is executed, and a signal representing the negative result is returned to the terminal device. In other words, the processing time from the point at which a processing command is received by the IC card to the point at which its processing result is returned to the terminal device (i.e., processing time of the IC card) differs depending on the processing result. The processing time also naturally differs for different processing commands. According to a conventional IC card, as shown in Fig. 1, the processing time takes different values t a and t b for different types of processing commands (CMD A and CMD B). Even for the same command (CMD B), the processing time may take different values, t b and t b ', depending on the processing result (RES b or RES b'). This is because, immediately upon completion of data processing, the processing result is returned to the terminal device. Accordingly, it is possible to find out the processing result or the processing commands by measuring the processing time. Even with the use of a method for encrypting communication data between the IC card and terminal device, this encrypted data may be decrypted, resulting in unauthorized use of the IC card. Further, between the time of sending a processing command to an IC card and the time of receiving a processing result from the card, the terminal device of the conventional IC card system can do nothing but wait for the processing result from the card and cannot do other processing. This significantly impairs the system's operational efficiency. Furthermore from document EP-A 0 243 873, which falls within the terms of Article 54(3) EPC, an IC card identification system is known, in which a first identification number entered by a card holder into a terminal is compared to the second identification number previously stored in the IC card. The comparison result is transmitted from the IC card to the terminal after the elapse of a processing time period, which is constant and independent of the result indicating coincidence or incoincidence of the first and second identification numbers, but which can differ from the processing times for other processing commands and, therefore, identifyable and decryptable in the card data stream. Accordingly, it is an object of this invention to provide a high-security IC card which can surely prevent its unauthorized use. It is another object of this invention to provide an IC card which can improve the operational efficiency of a system utilizing the IC card. These objects are achieved by an integrated-circuit card comprising a microcomputer for executing a number of different processing commands received from an external device and returning a processing result to said external device in response to receiving any processing command, said integrated-circuit card comprising: timer means for measuring elapsed time after reception of any processing command from said external device, and generating an output signal when the measured time reaches a predetermined value; and return means for returning said processing result to said external device in response to said output signal, whereby, for any processing command received from said external device, said processing result is returned to said external device in response to the elapsed time measured by said timer means having reached a predetermined value irrespective of the actual processing time required to obtain said processing result. This invention can be more fully understood from the following detailed description when taken into conjunction with the accompanying drawings in which: Fig. 1 is a time chart illustrating processing times for a conventional IC card; Fig. 2 is a perspective view illustrating the outline of an IC card according to one embodiment of this invention; Fig. 3 is a block diagram of the IC card according to this embodiment; Fig. 4 is a block diagram illustrating the internal structure of a timer; Fig. 5 is a flowchart illustrating the operation of a central processing unit (CPU); Fig. 6 is a flowchart of an interrupt routine; and Fig. 7 is a time chart illustrating processing times for the IC card according to this embodiment. Fig. 2 is a perspective view of the outline of an IC card. An IC card 1 has a one-chip microcomputer 2 and a memory (E²PROM or EPROM) 3 built in its card-shaped body. The microcomputer 2 has a plurality of terminals 12 through which it exchanges the necessary data with a terminal device (not shown) as an external device, executes data processing and writes data in memory 3. The terminal device is further coupled to a host computer. Fig. 3 is a block diagram illustrating the circuit arrangement of IC card 1. The microcomputer 2 and memory 3 are coupled together through an address bus 4 and a data bus 5. Within the microcomputer 2, a CPU 6 is coupled to a timer 7 through the data bus 5 and an internal interrupt signal bus 8. Internal memories ROM 9a and RAM 9b of the microcomputer 2 are coupled through the address bus 4 and the data bus 5 to an interface 10 for communication with the terminal device. Fig. 4 is a block diagram of the timer 7 in the microcomputer 2. A counter-register 13 is coupled through the data bus 5 to the CPU 6, and it is always functioning so as to increment its count value by one for every given period while the CPU 6 is functioning. The counter-register 13 is coupled through an overflow signal bus 15 to a timer control status register 14, which is also coupled to the CPU 6 through the data bus 5. Timer control status register 14 stores in total eight flags, one for each bit. Here, only an overflow flag 16 and an interrupt enable flag 17 are illustrated, and the other flags are omitted as they are not associated with the operation of this embodiment. The overflow flag 16 is set by a signal supplied from the counter-register 13 through the overflow signal bus 15 when an overflow occurs in the counter-register 13, and is reset by a signal supplied from the CPU 6 through the data bus 5 at a given timing. The interrupt enable flag 17 indicates the enable/disable of an internal interrupt of the CPU 6, and it is set or reset by a signal supplied from the CPU 6 through the data bus 5 at a given timing. Data of the overflow flag 16 and the interrupt enable flag 17 are both input to an interrupt signal generator 18, which sends an internal interrupt signal to the CPU 6 through the internal interrupt signal bus 8 to cause an internal interrupt when both flags are set. Referring now to Figs. 5 and 6, the operation of the IC card 1 will be described. Fig. 5 is a flowchart for the operation of the CPU 6. When the IC card 1 is loaded in a card insertion slot of the terminal device and its terminals 12 are coupled to the corresponding terminals of the terminal device, the CPU 6 is given power from the terminal device and starts functioning. In step S1, the CPU 6 receives a reset signal from the terminal device to be initialized and executes the preprocessing for data communication or initialization of the transmission speed, transmission format, guard time, block size or the like. In step S4, the CPU 6 detects whether or not it has received a processing command from the terminal device and waits until it receives the command. Upon receiving a complete processing command, the CPU 6 sets a predetermined initial value in the counter-register 13 through the data bus 5 in step S5. This initial value is determined in such a way that the time for the counter-register 13 to up-count until an overflow occurs is longer than the longest processing time each processing command can have. That is, an initial value is set which generates no internal interrupts before the execution of a processing command requiring the longest processing time is completed. In step S6, the overflow flag 16 is reset, and in step S7, the interrupt enable flag 17 is set. In this manner, the generation of an internal interrupt becomes ready through steps S5 to S7. Then, the processing command received in step S4 is executed in step S8. After the execution of the processing command is completed, the CPU 6 detects in step S9 whether or not an internal interrupt execute flag is set, and waits until the flag is set. The interrupt execute flag indicates whether or not an internal interrupt has been generated and an interrupt routine has been executed, and this flag is set in the RAM 9b of the microcomputer 2, not in the timer control status register 14. Since, as described above, the initial value for the counter-register 13 is determined such that an internal interrupt occurs after the execution of the processing command requiring the longest processing time is completed, this processing is always completed before occurrence of an internal interrupt. Accordingly, the processing should end and an overflow should occur in the counter-register 13 before the setting of the interrupt execute flag is detected in step S9. When an overflow occurs in the counter-register 13, the overflow flag 16 in the timer control status register 14 is set by a signal from the counter-register 13 through the overflow signal bus 15. Since the interrupt enable flag 17 has already been set in step S7, the interrupt signal generator 18 generates an internal interrupt signal to the CPU 6 through the internal interrupt signal bus 8. Upon reception of this signal, the CPU 6 executes an interrupt routine as shown in Fig. 6. In this interrupt routine, the interrupt enable flag 17 is reset in step S11 in order to inhibit the occurrence of a further interrupt until the CPU 6 receives the next processing command from the terminal device. In step S12, the processing result is returned to the terminal device. In step S13, the interrupt execute flag in the RAM 9b is set to indicate that the interrupt routine has been executed. Then, the program flow returns to the original routine (step S9 in Fig. 5). When the CPU 6 detects in step S9 the interrupt execute flag being set, it resets the interrupt execute flag in step S10 to be ready for the next processing command and returns to step S4 to wait for a new processing command. By repeating the same operation for the next processing command starting with step S4, it is possible to always make constant the processing time between the point at which the IC card 1 receives a complete processing command from the terminal device and the point at which the IC card 1 begins returning the processing result to the terminal device, irrespective of the processing result and processing command. Fig. 7 is a time chart illustrating the processing times for the IC card 1 of this embodiment. It should be noted that the processing time t c is constant irrespective of the processing command (CMD A or CMD B) or irrespective of the processing result (RPS b or RPS b') for the same processing command (CMD B). As described above, with the use of the IC card 1 of this embodiment for communication of encrypted communication data with an terminal device, even if the involved processing time is measured by monitoring a serial I/O line, it is impossible to find out a processing command and processing result since the processing time is constant irrespective of the processing command and processing result. This makes it impossible to find out a PIN through try and error, which could be done with the prior art. Since the processing time for the IC card 1 is made constant, a terminal device can execute other processing or send a processing command to another IC card during this constant time between the transmission of a processing command to the IC card 1 and reception of the processing result therefrom. This can improve the operational efficiency of a system using this IC card 1 and can reduce the processing load of the terminal device as a consequence. This invention is in no way limited to the above particular embodiment, but can be modified in various manners. For instance, although the processing time is made constant, it need not be constant for every processing command. Different constant processing times may be set for individual processing commands. Although, according to the above embodiment, an interrupt is given to the CPU upon elapse of a given time after the IC card 1 receives a processing command and the processing result is returned to the terminal device after a given, constant time with the help of the timer built in the microcomputer, this may be done using software. For example, the PIN verification can be executed as follows. It is assumed that the PIN has four digits and a time required for verifying each digit of the PIN is a given period. If it is found that one of the first, second, and third digits is incorrect, the verification result is returned to the terminal device after the time delay routine corresponding to the incorrect digit is executed. In other words, when the first digit is found to be incorrect, the NOP (no-operation) instructions are executed given times or a count-up operation is executed to a given count for producing a time period in which three digits are verified, then the verification result is returned.

Claims: An integrated-circuit card comprising a microcomputer (2) for executing a number of different processing commands received from an external device and returning a processing result to said external device in response to receiving any processing command, said integrated-circuit card comprising: timer means (7) for measuring elapsed time after reception of any processing command from said external device, and generating an output signal when the measured time reaches a predetermined value; and return means (6) for returning said processing result to said external device in response to said output signal, whereby, for any processing command received from said external device, said processing result is returned to said external device in response to the elapsed time measured by said timer means (7) having reached a predetermined value irrespective of the actual processing time required to obtain said processing result. The integrated-circuit card according to claim 1, being characterized in that said predetermined value is a constant value irrespective of the processing command received from said external device. The integrated-circuit card according to claim 1, being characterized in that said predetermined value depends on the processing command received from said external device. The integrated-circuit card according to claim 1, being characterized in that said timer means (7) comprises: a counter-register (13) which includes means for increasing its count value when said microcomputer (2) operates, the counter-register (13) being arranged to overflow when its count value reaches a constant value, an initial value of said counter-register (13) being set by said microcomputer (2) when said microcomputer (2) receives a processing command, a register (14) for storing an overflow flag (16) which is set by said counter-register (13) when said counter-register (13) overflows and which is reset by said microcomputer (2) when said microcomputer (2) receives a processing command, and an interrupt enable flag (17) which is set by said microcomputer (2) when said microcomputer (2) receives a processing command, and means (18) for generating an interrupt signal for said microcomputer (2) when both said overflow flag (16) and said interrupt enable flag (17) have been set, thereby initiating return of the processing result to said external device. The integrated-circuit card according to claim 4, being characterized in that said microcomputer (2) includes means (6) for presetting a constant value in said counter-register (13), irrespective of the processing command received from said external device. The integrated-circuit card according to claim 4, being characterized in that said microcomputer (2) includes means (6) for presetting a value in said counterregister (13) varying in dependance on the processing command received from said external device.

Inventors: MATSUMURA HIDEKAZU, TAKAHASHI MASASHI, YORIMOTO YOSHIKAZU, MATSUMURA, HIDEKAZU, TAKAHASHI, MASASHI, YORIMOTO, YOSHIKAZU
Applicants: TOPPAN PRINTING CO LTD, TOPPAN PRINTING CO. LTD.
Application year: 1988
Main classification: G07F7
IPC codes: G06K19, G07F7, B42D15