INSULATED GATE TRANSISTOR OPERABLE AT A LOW DRAIN-SOURCE VOLTAGE

Abstract: A transistor having a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed in the semiconductor substrate, a source region of the first conductivity type, a gate electrode formed on the base region between the source region and the semiconductor substrate via a gate insulator film, an additional region of the second conductivity type formed in the semiconductor substrate but separated from the base region, a resistive layer formed in electrically contact with an area of the semiconductor substrate which is separated from the base region and the additional region, a source electrode connected with the source region and a drain electrode connected with the additional region and the resistive layer.

Description: Background of the Invention (Field of the Invention) This invention relates to an insulated gate transistor (IGT) having a PN-junction region in a drain region of a MOS field effect transistor using a semiconductor substrate as the drain region and, more particularly, to an improvement for being operable at a low drain-source voltage (V DS ). (Description of the Related Art) As a high-power device, there has been widely used a vertical MOS field effect transistor in which a source region of one conductivity type is formed in a base region of the other conductivity type which is formed in a semiconductor substrate of the one conductivity type as a drain region. A gate electrode is formed on the base region located between the source and drain regions via a gate insulator film. This kind of vertical MOS field effect transistor flows a drain current across the thickness of the semiconductor substrate to allow a large power consumption. This vertical MOS field effect transistor, however, has a drawback of a large ON-resistance due to the current flow across the thickness of the substrate. This drawback causes a large power loss. For improving this large ON-resistance, an IGT has been proposed by M. F. Chang et al in IEDM83, pages 83 to 86. The IGT has a high impurity region of the other conductivity type in the drain region in contact with the drain electrode to interpose the other conductivity type region between the drain region and the drain electrode. According to this IGT,a carrier injection of other conductivity type carriers is generated from the high impurity region to the drain region as a reaction of the drain current flowing into the high impurity region. By the carrier injection, the conductivity modulation is generated to make the ON-resistance very small. The carriers of the carrier injection are, however, majority carriers of the high impurity region. Therefore, the PN-junction between the drain region and the high impurity region is necessary to be forward biased. This required forward bias restricts the lower limit of the drain-source voltage to more than 0.5 or 0.6 volts. In a region of the drain-source voltage lower than this value, there flows little drain current to lose a transistor action. Thus, the proposed IGT has a drawback that it does not operate in a low drain-source voltage. The proposed IGT has another drawback of a deteriorated operational speed. When the IGT turns off, a discharging path of the charges in the drain region does not exist due to the existance of the high impurity region. Therefore, the IGT does not turn off until the charges in the drain region disappear by recombination in the drain region. As an IGT operable at a low drain-source voltage with a high speed, a lateral IGT has been proposed by M.R. Simpson in IEDM85, pages 740 to 743. In the lateral IGT, the high impurity region is formed in the same surface of the drain region as the base and source regions. The drain electrode is connected with the high impurity region and a portion of the drain region located on opposite side of the high impurity region to the source and drain regions. Drain current flows laterally along the surface of the drain region. In a high drain-source voltage region, the PN-junction between the high impurity region and the drain region is forward biased to allow the carrier injection, while the resistance component of the drain region under the high impurity region restricts the drain current following directly to the drain electrode, resulting in the IGT operation. On the other hand, in a low drain-source voltage region, since the IGT operation does not function due to insufficient forward bias of the PN-junction between the high impurity region and the drain region, the drain current bypasses the high impurity region to flow directly to the drain electrode, resulting in a MOS field effect transistor action. Thus, the lateral IGT can operate in a low drain-source voltage region. Furthermore, if the lateral IGT turns off, the discharging path of the carriers in the drain region is kept by a route through the direct connection of the drain region and the drain electrode. Therefore, the lateral IGT can operate at a high speed. This lateral IGT, however, has a large ON-resistance based on a drain current flowing along the surface of the drain region. By the same reason, it requires a large area on a semiconductor chip to lower a current capacity. Another improvement of the IGT has been proposed by T. Goto et al in a Japanese Laid-open Patent No. 60-170263 published on September 3, 1985. This improved IGT has the high impurity region of a lattice shape or a comb shape in a bottom region of the drain region. This improvement has an improved high speed operation, a low ON-resistance and a large current capacity. It is, however, difficult to obtain a sufficient resistance component in the drain region positioned adjacent to the high impurity region. Due to this insufficient resistance component, the MOS field effect transistor action is kept up to a large drain-source voltage. The low ON-resistance cannot be obtained until the drain-source voltage becomes fairly high voltage. A transistor according to the preamble of claim 1 is disclosed in EP-A-0 228 107. In this transistor the third region and the resistive layer are provided on the same surface of the base and source regions. Therefore, this device presents a large ON-resistance and a small current capacity. It is therefore an object of the invention to provide an IGT operable at a low drain-source voltage and at a high speed. It is another object of the invention to provide an IGT having a large current capacity and showing a low ON-resistance even at a low drain-source voltage. These objects are achieved by a transistor as defined in claim 1; the dependent claims are related to further developments of the invention. The present invention provides a transistor having a semiconductor substrate of one conductivity type and having an upper surface portion and a bottom surface portion, a base region of the other conductivity type formed in the upper surface portion of the semiconductor substrate, a source region of the one conductivity type formed in the base region, a source electrode connected to the source region, a gate insulator film covering a portion of the base region, a gate electrode formed on the gate insulator film, an additional region of the other conductivity type formed in the semiconductor substrate apart from the base region, a resistance region formed in electrical contact with the bottom surface portion, and a drain electrode formed in contact with the additional region and the resistance region. The resistance region is formed by resistive material deposited on the bottom surface portion. According to the present invention, the additional region is formed in the semiconductor substrate apart from the base region and the drain electrode is connected to the bottom surface portion through the resistance region and the additional region. Therefore, although the transistor operates as an IGT when the drain-source voltage is large, it operates as a vertical MOS field effect transistor when the drain-source voltage is small. Furthermore, since the charges in the semiconductor substrate which operates as a drain region can be discharged to the drain electrode through the bottom surface portion and the resistance region, the transistor according to the present invention can operate at a high speed. The drain current flows vertically across the thickness of the semiconductor substrate. Therefore, the transistor has a small ON-resistance and may have a large current capacity. Although the resistive component of the bottom surface portion at the remaining part is not enough for making the transistor operate at the IGT with a small drain-source voltage, this drawback is improved by using the resistance region. Thus, the transistor of the present invention operates to show a small ON-resistance for a small drain-source voltage. Brief Description of the Drawing The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawing, wherein: FIG. 1 is a sectional view showing a preferred embodiment of the present invention. Description of the Preferred Embodiments Referring to Fig. 1, the preferred embodiment uses an N-type Si substrate 12 having an impurity concentration of 2.5 x 10¹⁴ cm⁻³ and a thickness of 100 µm. A plurality of stripes of P-type base regions 21 having an impurity concentration of 9 x 10¹⁶ cm⁻³ and having a depth of 6 µm are formed in an upper surface portion of the substrate 12. In each stripe of base region 21, two stripes of N+-type source regions 30 are formed separated from each other. Each stripe of the source region 30 has an impurity concentration of 2.5 x 10¹⁸ cm⁻³ and a depth of 3 µm. A gate insulator film 8 of SiO₂ having a thickness of 100 nm (1,000 Å) are thermally grown on the whole upper surface of the substrate 12 and then etched away from the base regions 21 interposed between the two stripes of source regions 30 which are formed in the same base region 21 and from parts of the source regions 30 adjacent to the exposed region of the base region 21. On the remaining gate insulator film 8, gate electrodes 9 are formed with polycrystalline silicon to have a thickness of 500 nm (5,000 Å). The gate electrodes 9 are covered with SiO₂ film having a stripe of aperture. The exposed base and source regions are covered with a comb-shape source electrode 7-2 of aluminum and connected to a source terminal 1. The exposed portions of the gate electrodes 9 are also covered with a comb-shape gate wiring 7-3 of aluminum and connected to a gate terminal 2. The bottom surface portion of the substrate 12 has a plurality of stripes of N+-type regions 6 having an impurity concentration of 4 x 10¹⁷ cm⁻³ and a depth of 2 µm and a plurality of stripes of P⁺-type regions 5 having an impurity concentration of 3.5 x 10¹⁸ cm⁻³ and a depth of 3 µm. The stripes of the N⁺-type regions 6 and the stripes of the P⁺-type regions 5 are alternately formed. On the N⁺-type regions 6 are resistance regions 4 of Ni-Cr layer having a thickness of 500 nm (5,000 Å). This resistance regions 4 may be formed with epitaxially grown impurity-doped Si. The resistance across the thickness of the resistance regions is selected to have a resistance in a range from 1/10 to 10 times of ON-resistance of the obtained transistor at a MOS field effect transistor operation. The typical value of the resistance of the resistance region is from 10 to 50 ohms. A drain electrode 7-1 of aluminum is formed to cover all the P⁺-type regions 5 and the resistance regions 4. The drain electrode 7-1 is connected to a drain terminal 3. According to the transistor of the preferred embodiment, if the drain-source voltage V DS is small, the PN-junctions between the N-type substrate 12 and the P⁺-type regions 5 are not biased forward to produce no current 11 flowing through the PN-junction but to make current 10 flow through the N⁺-type region 6 and the resistance regions 4. Thus, the transistor operates as a MOS field effect transistor in an operational condition of a small drain-source voltage V DS . As the drain-source voltage V DS increases, the drain current becomes large to raise voltage drop across the N⁺-type region 6 and the resistance region 4. When the voltage drop becomes larger than a forward-biasing voltage of PN-junction, that is, larger than 0.6 volts, electrons in the substrate 12 are allowed to flow into the P⁺-type regions 5 and to inject holes in the P⁺-type regions 5 into the substrate 12. This hole-injection produces a conductivity-modulation in the substrate 12 to operate the transistor as the IGT. By the IGT-operation, ON-resistance of the current flow 11 becomes very small. Majority of current flows through the P⁺-type regions 5 with small ON-resistance. Thus, the transistor operates in a wide range of drain-source voltage with a small ON-resistance. Regarding the ON-resistance, that at the MOS field effect transistor operation is small compared to the lateral IGT in the prior art. Furthermore, the preferred embodiment uses additional resistance regions 4, a sufficient resistance can be applied in parallel with the P⁺-type region 5 in vertical direction. The applied resistance is easily controlled. Therefore, in spite of the vertical action, the IGT operation can be maintained to a sufficiently low drain-source voltage.

Claims: A transistor comprising: A semiconductor substrate used as a first region (12) of a first conductivity type semiconductor having an upper surface portion and a bottom surface portion; a second region (21) of a second conductivity type semiconductor formed in said upper surface portion; a third region (30) of said first conductivity type semiconductor formed in said second region; a gate insulator film (8) formed on a portion of said second region positioned between said third and first regions; a gate electrode (9) formed on said gate insulator film; a source electrode (7-2) connected with said second region and said third region; a fourth region (5) of said second conductivity type semiconductor formed in a first limited area of said first region apart from said second region; a resistive layer (4) formed in electrical contact with a second limited area of said first region positioned apart from said second region and said first limited area; and a drain electrode (7-1) contacting said fourth region and said resistive layer, said resistive layer presenting a predetermined value of resistance between said second limited area and said drain electrode, characterized in that said first limited area is in the bottom surface portion of said first region and said second limited area is formed in the remaining area of said bottom surface portion of said first region. The transistor as claimed in claim 1 , wherein said resistive layer is a resistive material formed on said second limited area. The transistor as claimed in claim 1, further comprising a fifth region (6) of said first conductivity type formed in said second limited area, said fifth region having an impurity concentration higher than said first region. The transistor as claimed in claim 3, wherein said second, third, fourth and fifth regions are respectively formed in a large number in said first region.

Inventors: OGAWA, KENJI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1988
Main classification: H01L29
IPC codes: H01L29