High-frequency bipolar transistor and its fabrication method

Abstract: A bipolar transistor with improved high-frequency performance is in­ vented. The improvement is attained by eliminating a parasitic base-­ collector capacitance. The invented transistor is constructed upon a semi-insulating substrate, and wherein a region which underlies an ex­ trinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector contact region and the collector region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the sub­ strate. As a result, the transistor has substantially no parasitic base-­ collector capacitance. Also, a novel method, utilizing a self-align tech­ nique which uses a "first mask" for defining a collector contact region and a collector region, a "second mask" for defining an extrinsic base region, and a "third mask" determined by self-alignment using the first and the second mask for defining an emitter region, is disclosed to fabricate the bipolar transistor mentioned above.

Description: BACKGROUND OF THE INVENTION 1.Field of the Invention This invention relates to a transistor and more particularly to a high-frequency bipolar transistor, and to a method of fabricating the transistor. 2.Description of the Prior Art A trend of semiconductor device technology is toward high speed and high frequency, as well as high integration. As is well-known, the high-frequency limitation of a bipolar transistor is usually described by the maximum oscillation frequency f max , which is expressed as follows: f max = [4π(R b C bc t ec ) 1/2 ] -1 (1), where R b is the base resistance, C bc is the base-collector junction capacitance and t ec is the emitter-to-collector delay time. Since t ec also contains the term proportional to C bc , f max is especially sensitive to C bc . Accordingly, the reduction of C bc is essential to improve the high-frequency performance of a bipolar transistor. In the case of an emitter-top transistor whose emitter is located on top of the transistor, C bc is expressed by the sum of an intrinsic capacitance C bci and a parasitic capacitance C bcp , as follows: C bc = C bci + C bcp (2). The portion of a base region which underlies an emitter region is called an intrinsic base region, the rest of the base region, which is extended from the intrinsic base region, is called an extrinsic base region. Therefore, the intrinsic base region is an active region, and the extrinsic base region is an inactive region. C bci is the junction capacitance formed between the intrinsic base region and the collector region. C bcp is the junction capacitance formed between the extrinsic base region and the collector region. Reduction of C bci is, however, quite difficult because C bci is almost automatically determined by the requirement to realize a fundamental transistor action. Accordingly, the possible choice is limited to reduce C bcp . Recently, AlGaAs/GaAs heterojunction bipolar transistors (HBT's) have been attracting much interest because of its outstanding possibilities for high-frequency devices. In such HBT's, the bandgap of a material of the emitter region is wider than that of a material of the base region, so that the emitter-base junction forms a heterojunction. The principal advantage of the HBT's over Si homojunction bipolar transistors is that sufficiently high base-doping is possible without sacrificing the emitter injection efficiency, because the minority carrier injection from the base region to the emitter region is suppressed by the wider emitter bandgap of the heterojunction. Accordingly, both the base width and R b can simultaneously be reduced. As is well-known, the reduction of the base width is especially effective to decrease the base transit time, which is generally the most important component of t ec . As a consequence, f max can be increased according to the formula (1). The other advantage is that the electron mobility of GaAs is faster than that of Si. One of the conventional methods to reduce C bcp in HBT's is, as shown in FIG. 1, to introduce a semi-insulative region 20 between an extrinsic base region 21 and a collector contact region 11. (Ref. P. M. Asbeck, D. L. Miller, R. J. Anderson and F. H. Eisen, IEEE Electron Device Letters, vol. EDL-5, p. 310, 1984.) Here the semi-insulative region means that its resistivity is sufficiently high compared with those of n-type or p-type transistor regions. In the prior art cited above, a collector contact region 11 is made of n⁺-GaAs, a collector region 12 made of n-GaAs, a base region 13 made of p⁺-GaAs, an emitter region 14 made of n-AlGaAs and an emitter contact region 15 made of n⁺-GaAs are fabricated in this order on a semi-insulating (s. i.) substrate 10. Be⁺ is implanted in the extrinsic base region 21 to reduce R b . A collector electrode 17, double base-electrodes 18 and an emitter electrode 19 are formed upon the collector contact region 11, the extrinsic base region 21 and the emitter contact region 15, respectively. The conduction property of the portion 20 sandwiched between the extrinsic base region 21 and the collector contact region 11 is changed from n-type to semi-insulative by O⁺ implantation. Accordingly, C bcp is reduced as the base-collector junction is thus changed from p⁺-n to p⁺-i-n⁺. In the above structure, however, the reduction of C bcp is limited to a certain extent, because the overlap between the extrinsic base region 21 and the collector contact region 11, which makes the p⁺-i-n⁺ junction, still remains. Another conventional method for reducing Cbcp in HBT is to introduce a semi-insulative region in the portion outside of the collector contact region under the extrinsic base region as shown in JP-A-61-182257. In this structure, however, Cbcp is not minimum, because a lead portion exists between the actual intrinsic base region in the base region and the extrinsic base region. That is, the area of the emitter region differs from that of the collector region. An object of this invention is to improve the high-frequency performance of a emitter-top (collector-top) bipolar transistor by eliminating the parasitic capacitance C bcp (C bep ) of a bipolar transistor. According to the present invention there is provided a bipolar transistor comprising: a semi-insulating substrate; a contact region formed on said substrate; a first semiconductor region formed on said contact region; a semi-insulative region formed on said substrate so as to extend from both said contact region and said first semiconductor region; a base region having an intrinsic base region formed on said first semiconductor region and an extrinsic base region formed on said semi-insulative region so as to extend from said intrinsic base region; and a second semiconductor region formed on said intrinsic base region, characterized in that said extrinsic base region is in a non-overlapping relationship with said first semiconductor region and said contact region when viewed in a direction perpendicular to said substrate, and that said transistor further comprises: a base electrode formed on said extrinsic base region and divided into two portions arranged at two sides of said second semiconductor region; and an electrode formed on said contact region and divided into two portions arranged at two other sides of said second semiconductor region. As a result, the transistor has substantially no parasitic capacitance C bcp (C bep ). Another object of this invention is to provide a novel method which fabricates the bipolar transistor mentioned above. According to this invention there is provided a method of fabricating a bipolar transistor, comprising the steps of: forming a multilayer structure by sequentially stacking on a semi-insulating substrate a contact layer, a first semiconductor layer, a base layer and a second semiconductor layer in this order; forming a first mask; changing said contact layer and said first semiconductor layer to be a first semi-insulative region by a deep ion-implantation at portions except for portions below said first mask so that the portions of said contact layer and said first semiconductor layer below said first mask become a contact region and a first semiconductor region, respectively; and forming a base region and a second semiconductor region, characterized in that the step of forming a base region and a second semiconductor region comprises the steps of: forming a second mask on a part of said multilayer structure to partly overlap a part of said first mask; removing said first mask except for the part overlapped with said second mask; changing said base layer to be a second semi-insulative region by a shallow ion-implantation at a portion except for a portion below said second mask so that the portion of said base layer below said second mask becomes a base region having an extrinsic base region formed on said first semi-insulative region; removing said second mask so that the part of said first mask which has been overlapped with said second mask remains as a third mask; etching off said emitter layer at a portion except for a portion below said third mask so that the portion of said second semiconductor layer below said third mask remains as a second semiconductor region; and removing said third mask. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a cross-sectional view of a conventional GaAs bipolar transistor. Fig. 2 is schematic views of an emitter-top GaAs bipolar transistor improved with this invention; (a) is a top view of the transistor seen in the direction perpendicular to a substrate; (b) is a cross-sectional view of the same transistor cut at A-A'; (c) is a cross-sectional view of the same transistor cut at B-B'. Fig. 3 shows schematic self-aligned processing steps of this invention, where the viewpoints (a-), (b-) and (c-) correspond to those of (a), (b) and (c) of Fig. 2, respectively. Figs. 4, 5 and 6 show the top views of three variations of the GaAs bipolar transistors improved with this invention. Fig. 7 is a cross-sectional view of a collector-top GaAs bipolar transistor improved with this invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The transistor improved with the present invention is shown Fig. 2, taking up an emitter-top HBT with double base-electrodes and double collector-electrodes as an embodiment. The transistor is constructed upon a semi-insulating substrate 10. A collector contact region 11, a collector region 12, an intrinsic base region 13, an emitter region 14 and an emitter contact region 15 are formed on the substrate 10 in this order. An extrinsic base region 21 is formed on a first semi-insulative region (1st. O⁺) 31. A second semi-insulative region (2nd. O⁺) 32 is formed around the extrinsic base region 21. Double collector-electrodes 17, double base-electrodes 18 and an emitter electrode 19 are formed on the collector contact region 11, the extrinsic base region 21 and the emitter contact region 15, respectively. Here, to reduce both the collector resistance R c and the base resistance R b , both the collector electrodes 17 and the base electrodes 18 are divided into two portions arranged at both sides of the emitter region 14. A fabrication method of the transistor is described along FIG.3. The method, utilizing self-align technique, is especially suitable for realizing the proposed transistor. The process steps are as follows. First of all, a multilayer structure is constructed by means of, for example, molecular-beam epitaxy. This multilayer structure comprises an n⁺-GaAs (e.g., 5x10¹⁸ cm⁻³ doped, 0.5 µm thick) collector contact layer, an n-GaAs (e.g., 5x10¹⁶ cm⁻³ doped, 0.4 µm thick) collector layer, a p⁺-GaAs (e.g., 2x10¹⁹ cm⁻³ doped, 0.1 µm thick) base layer, an n-AlGaAs (e.g., 1x10¹⁸ cm⁻³ doped, 0.2 µm thick) emitter layer and an n⁺-GaAs (e.g., 5x10¹⁸ cm⁻³ doped, 0.1 µm thick) emitter contact layer, which are stacked on a semi-insulating GaAs substrate 10 in this order. This initial structure is not shown in FIG.3. Then, in order to define a collector contact region 11 and a collector region 12, the portions 31 of the collector contact layer and the collector layer are changed semi-insulative by deep-implanting O⁺ (e.g., 1x10¹⁵ cm⁻² dosed at an energy of 500 keV) from the surface of the multi-layer structure, using SiO₂ 1 (e.g., 2 µm thick) as a mask (see FIG.3 (a-1), (b-1) and (c-1)). For convenience, the portion 31 is called "first O⁺-implanted region", and the mask made of SiO₂ 1 is called "first mask". Accordingly, the initial collector contact layer and collector layer are divided into the collector contact region 11, the collector region 12 and the first O⁺-implanted region 31. The transistor region with the highest resistivity, that is the collector region 12, shows resistivity of about 0.03 Ω·cm, whereas the semi-insulative region 31 prepared according to the above condition shows the resistivity of about 10⁵ Ω·cm, which is in fact sufficiently higher than the former. After that, to reduce an extrinsic base resistance, the region 21 upon the first O⁺-implanted region 31 is ion-implanted with Be⁺ (e.g., 1x10¹⁴ cm⁻² dosed at an energy of 100 keV), again using the first mask 1, as shown in FIG.3 (a-1), (b-1) and (c-1). The region 21 becomes p-type by this Be⁺ implantation. Part of the region 21 is to become an extrinsic base region 21 in the next step. Here, it's worthwhile to point out that a portion under the region 21 has been made completely semi-insulative down to the substrate 10 (see FIG.3 (a-2), (b-2) and (c-2)). As a next step, the extrinsic base region 21 in which Be⁺ has been implanted is defined as follows. The second mask 2 made of Al (e.g., 1 µ m thick) is formed on top of the multi layer structure, which crosses over the first mask 1 as shown in FIG.3 (a-2). Then the part of the first mask 1 which is not covered with the second mask 2 is removed by dry etching (e.g., reactive ion etching of CHF₃). After that, the portion 32 which is not covered with the second mask 2 is changed semi-insulative by shallow-implanting O⁺ (e.g., 1x10¹⁵ cm⁻² dosed at an energy of 200 keV). For convenience, the portion 32 is called "second O⁺-implanted region". As a next step, an emitter region 14 and an emitter contact region 15 are defined with self-alignment technique as follows. Removing the second mask 2 by wet etching (e.g. , HCl), SiO₂ 3 is exposed as shown in FIG.3 (a-3). The SiO₂ 3 is the part of the first mask 1 which have been covered with the second mask 2. Then the initial emitter layer and emitter contact layer are removed by wet etching (e.g., H₂SO₄:H₂O₂:H₂O = 1:1:12) using the SiO₂ 3 as a mask (see FIG.3 (a-3), (b-3) and (c-3)). For convenience, the SiO₂ 3 is called "third mask". As is described above, the shape of the third mask is determined by the first and second mask, that is, determined by self-alignment. This self-alignment ensures the extrinsic base region 21 not to overlap the collector contact region 11 and the collector region 12 at all. As a result, the parasitic capacitance C bcp can be substantially eliminated. After removing the third mask 3 by wet etching (e.g., HF), the sample is annealed (e.g., 800 °C for 10 seconds) to recrystallize all of the implanted regions 21, 31 and 32. Then, the collector, emitter and base electrodes are formed in this order. Via holes 40 reaching the collector contact region 11 are first formed by wet etching using photoresist 4 as a mask, as shown in FIG.3 (a-4), (b-4) and (c-4). Then evaporating AuGe/Ni/Au and using lift-off technique by resist 4, the double collector-electrodes 17 are formed upon the collector contact region 11. The emitter electrode 19 is next formed upon the emitter contact region 15 by evaporating the same metal and using lift-off technique. After alloying the electrodes 17 and 19 with heat treatment, the double base-electrodes 18 are last formed upon the extrinsic base region 21 by evaporating AuZn/Au and using lift-off technique (see FIG.3 (a-5), (b-5) and (c-5)). In case that the transistor described above is applied to integration circuits, each of the electrodes 17, 18 and 19 is led to an outer area by multi-level metallization technique. The HBT improved with this invention is easily fabricated with the self-aligned process as described above. The structure and the process have the following advantages: (1) the invented transistor has substantially no base-collector parasitic capacitance C bcp ; (2) the above fabrication method utilizes simple but useful self-alignment technique, owing to which the extrinsic base region 21 does not substantially overlap the collector contact region 11; (3) excessive device isolation process for integration circuits needs not be formed because each transistor area is defined by the first mask and the second mask in this process; (4) the layout scheme of the base and the collector electrodes can be set up freely. FIGs.4, 5 and 6 show top views of other layout schemes of those electrodes. The HBT shown in FIG.4 has a single collector-electrode. This transistor has an advantage that each of the electrodes can be directly led to an outer area without multi-level metallization technique. The HBT shown in FIG.5 has a single collector-electrode 17 and a single base-electrode 18. In this transistor, the base electrode 18 which surrounds the emitter contact region 15 is very effective to reduce R b . The HBT shown in FIG.6 has an single collector-electrode 17 and an single base-electrode 18, which both surround the emitter contact region 15. The scheme of this transistor enables to reduce the R c and R b even if adopting a single electrode configuration. In the previously-mentioned process, the Be⁺-implanting step is not necessary if the conditions of the first deep O⁺-implanting are decided such that this implantation does not affect the extrinsic base region. Also, the implanting ions other than O⁺ and Be⁺ may be used. For example, B⁺, H⁺, N⁺ or Cr⁺ may be used to form the semi-insulative region in place of O⁺, and Mg⁺, Zn⁺ or C⁺ may be used to form a p-type region in place of Be⁺. The conditions of ion implanting and annealing depend on the kind of the implanting ions and on the thickness and doping of the multilayer structures. The HBT may be fabricated by other method than that described above. For example, the extrinsic base region may be delineated by wet etching, in stead of the second O⁺-implanting. The previously-mentioned structure and process can be applied to a homojunction bipolar transistor without any alteration, and also to a collector-top transistor whose collector is located on top of the transistor. In the collector-top transistor, the reduction of the parasitic base-emitter capacitance C bep becomes important, just like the reduction of the parasitic base-collector capacitance C bcp was important in the emitter-top transistor. FIG.7 shows another embodiment of the present invention applied to a collector-top transistor. An emitter contact region 15, an emitter region 14, a base region 13, a collector region 12 and a collector contact region 11 are formed on a semi-insulating substrate 10 in this order, and a first O⁺-implanted region 31, a second O⁺-implanted region 32 and a Be⁺-implanted region 21 are also formed by the self-aligned process described above. That is, in the description of the process made in connection with FIG.2 and FIG.3, the terms "emitter" and "collector" may be changed to "collector" and "emitter", respectively, to form the transistor shown in FIG.7. Obviously, C bep is essentially eliminated with the concept of the present invention.

Claims: A bipolar transistor comprising: a semi-insulating substrate (10); a contact region (11,15) formed on said substrate; a first semiconductor region (12,14) formed on said contact region; a semi-insulative region (31) formed on said substrate so as to extend from both said contact region and said first semiconductor region; a base region (13, 21) having an intrinsic base region (13) formed on said first semiconductor region and an extrinsic base region (21) formed on said semi-insulative region so as to extend from said intrinsic base region; and a second semiconductor region (14,12) formed on said intrinsic base region, characterized in that said extrinsic base region (21) is in a non-overlapping relationship with said first semiconductor region (12,14) and said contact region (11,15) when viewed in a direction perpendicular to said substrate (10), and that said transistor further comprises: a base electrode (18) formed on said extrinsic base region and divided into two portions arranged at two sides of said second semiconductor region (14,12); and an electrode (17) formed on said contact region (11,15) and divided into two portions arranged at two other sides of said second semiconductor region (14,12). The bipolar transistor according to claim 1, wherein said contact region, said first semiconductor region and said second semiconductor region are a collector contact region (11), a collector region (12) and an emitter region (14), respectively. The bipolar transistor according to claim 2, wherein said collector region (12) is made of GaAs, and said semi-insulative region (31) is made by oxygen-ion implantation into a GaAs layer. The bipolar transistor according to claim 1, wherein said contact region, said first semiconductor region and said second semiconductor region are an emitter contact region (15), an emitter region (14) and a collector region (12), respectively. The bipolar transistor according to claim 4 wherein said emitter region (14) is made of AlGaAs, and said semi-insulative region (31) is made by oxygen-ion implantation into an AlGaAs layer. The bipolar transistor according to any of claims 1 to 5, wherein said emitter region (14) is made of a material having a bandgap wider than that of a material of said base region (13,21). A method of fabricating a bipolar transistor, comprising the steps of: forming a multilayer structure by sequentially stacking on a semi-insulating substrate (10) a contact layer (11), a first semiconductor layer (12), a base layer (13) and a second semiconductor layer (14) in this order; forming a first mask; changing said contact layer and said first semiconductor layer to be a first semi-insulative region (31) by a deep ion-implantation at portions except for portions below said first mask so that the portions of said contact layer and said first semiconductor layer below said first mask become a contact region and a first semiconductor region, respectively; and forming a base region and a second semiconductor region, characterized in that the step of forming a base region and a second semiconductor region comprises the steps of: forming a second mask (2) on a part of said multilayer structure to partly overlap a part of said first mask; removing said first mask except for the part overlapped with said second mask; changing said base layer to be a second semi-insulative region (32) by a shallow ion-implantation at a portion except for a portion below said second mask so that the portion of said base layer below said second mask becomes a base region having an extrinsic base region (21) formed on said first semi-insulative region; removing said second mask so that the part of said first mask which has been overlapped with said second mask remains as a third mask (3); etching off said emitter layer at a portion except for a portion below said third mask so that the portion of said second semiconductor layer below said third mask remains as a second semiconductor region; and removing said third mask. A method of fabricating a bipolar transistor according to claim 7, wherein said contact layer, said first semiconductor layer and said second semiconductor layer are a collector contact layer (11), a collector layer (12) and an emitter layer (14), respectively. The method of fabricating a bipolar transistor according to claim 7, wherein said contact layer, said first semiconductor layer and said second semiconductor layer are an emitter contact layer (15), and emitter layer (14) and a collector layer (12), respectively. The method of fabricating a bipolar transistor according to any of claims 7, 8 or 9, wherein said emitter layer (14) is made of a material having a bandgap wider than that of a material of said base layer (13).

Inventors: INADA MASANORI, OTA YORITO, YANAGIHARA MANABU, INADA, MASANORI, OTA, YORITO, YANAGIHARA, MANABU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: H01L29
IPC codes: H01L29, H01L21