CMOS INTEGRATED CIRCUIT FAN-IN LOGIC TREE LAYOUT ARRANGEMENT

Abstract: A logic circuit, such as used in a crossbar digital switch, containing a multistage fan-in logic tree is arranged in a compact folded layout having a width equal to a single stage of the tree, in order to minimize wiring delays and signal skew.

Description: Background of the Invention This invention relates to integrated circuits and more particularly to digital logic circuit layouts for implementing fan-in logic trees, such as can be used in a crossbar (crosspoint) switch in a telecommunication system for voice, video or data transmission. In prior art, interconnecting wiring delays in such logic trees, caused by differences in relatively long lengths of the interconnecting wiring, produce undesirable signal skews (signal-delay differences) in the outputs of the logic trees. Therefore, it would be desirable to have an integrated circuit layout arrangement for such trees which reduces this skew. Summary of the Invention Signal skew due to interconnection wiring delays in an integrated circuit fan-in logic tree is reduced, in accordance with the invention, by using a compact folded layout for the logic tree. More specifically, the inventive layout for such a logic tree -- composed of a plurality N of logic devices, each of such devices having a first and a second input terminal and an output terminal is characterized in that the plurality comprises seven of such devices sequentially arranged in a column (FIG. 4, 603) containing the seven devices in sequence; the first and second input terminals of the 1st, 3rd, 5th, and 7th devices are separately connected to receive signals emanating from sources that are external to all of the N devices; the output terminals of the 1st and the 3rd device are separately connected to the first and second input terminals, respectively, of the 2nd device; the output terminals of the 5th and 7th devices are separately connected to the first and second input terminals, respectively, of the 6th device; and the output terminals of the 2nd and 6th devices are connected to the first and second input terminals, respectively, of the 4th device, and the first and second input terminals of the 1st, 3rd, 4th, 5th, and 7th devices, as well as the output terminals of the 2nd and 6th devices, are all located essentially on a first side of the column; and the first and second input terminals of the 2nd and 6th devices, as well as the output terminals of the 1st, 3rd, 4th, 5th, and 7th devices, are all located essentially on a second side of the column opposite the first side thereof In particular, when each such logic device is a NOR gate connected in cascade with an inverter, such a fan-in logic tree is a multiplexer fan-in logic tree, which is useful in a crossbar switching arrangement. Brief Description of the Drawing This invention together with its features, advantages, and characteristics may be better understood from the following detailed description when read in conjunction with the drawings in which FIG. 1 is a schematic logic circuit diagram including an eight-information-signal-input multiplexer fan-in logic tree, useful for illustrating background of the invention; FIG. 2 is a schematic logic circuit diagram including a compact folded layout of an eight-information-signal-input multiplexer fan-in logic tree in accordance with a specific embodiment of the invention; FIG. 3 is a schematic logic circuit diagram of an integrated circuit digital crossbar switching arrangement, using fan-in logic tree layouts in accordance with the invention; and FIG. 4 is a block diagram of a compact folded layout of a sixty-four-information-signal input fan-in logic tree in accordance with another specific embodiment of the invention. Detailed Description As shown in FIG. 1, a fan-in multiplexer logic tree 300 includes a first multiplexer stage having a total of eight NAND gates 100, 101, 102,... 107 in pairs which fans-in to a second multiplexer stage comprising a total of four NAND gates 110, 111, 112, 113, each cascaded in series with an INVERTER gate 200, 201, 202, 203, respectively. In turn, these four INVERTER gates in pairs fan-in to a third multiplexer stage comprising a total of two NAND gates 120 and 121, each cascaded in series with an INVERTER gate 210 and 211, respectively. Further, these latter two INVERTER gates in pairs fan-in to a fourth multiplexer stage comprising multiplexer 130 cascaded in series with INVERTER gates 220 and 230 to node N1. Moreover, the node N1 is connected to a pair of parallel paths to first path containing cascaded INVERTER gates 241, 242, 243, 244, terminating in a first output pad 400, and the second path containing cascaded INVERTER gates 251, 252, 253 terminating in a second output pad 400' which thus supplies the complementary information signal to that developed at the first output pad 400, there being one more inverter in first such path than in the second. To minimize device skew when CMOS technology is being used for implementing the logic gates, as discussed in a paper autored by M. Shoji, published in the IEEE Journal of Solid State Physics , vol. SC-21, page 875 (October 1986), entitled "Elimination of Process-Dependent Clock Skew in CMOS VLSI", each of the NAND gates is symmetrized and each of the INVERTER gates likewise is symmetrized, except that the INVERTER gates in the first and second paths from node N1 to the output pads 400 and 400', respectively, generally are not symmetrized, since none of these INVERTER gates is immediately preceded by a NAND gate that would require compensation by symmetrization. Such symmetrization is achieved, as explained in that paper, by adding a pair of serial-connected NFETs (n-channel field effect transistors) in the NMOS portion of the conventional CMOS NAND gate, to equalize the number of NFETs in the two strings of transistors of such gate. On the other hand, the transistors in the INVERTER gates in the first and second paths are selected to have channel widths such that, in response to an upward -going signal edge at the node N1, the sum of the resulting pull- up delays in the first and second paths are made to be equal, and at the same time the sum of the resulting pull- down delays in these paths are also made to be equal--i.e., the sum of the resulting pull- up delays of INVERTER gates 242 plus 244 is equal to the resulting pull- up delay of the INVERTER gate 252, and moreover at the same time in response to this upward -going signal edge at the node N1 the sum of the resulting pull- down delays of the INVERTER gates 241 plus 243 is equal to the sum of the resulting pull- down delays of the INVERTER gates 251 plus 253. Similarly, in response to a downward -going signal edge at the node N1, the sum of the resulting pull- up delays of the INVERTER gates 241 plus 243 is made equal to the sum of the resulting pull- up delays of INVERTER gates 251 plus 253, and the sum of the pull- down delays of INVERTER gates 242 plus 244 is made equal to the sum of the resulting pull-down delay of the INVERTER gate 252. In this connection, it should be remembered that in any CMOS gate, the NMOS portion pulls- down the output of the gate in response to an upward -going input, whereas the PMOS portion pulls up the output of the gate in response to a downward -going input. It is important, if CMOS technology is being used for the logic gates, that the NAND gates 110, 111, 112, 113 (in the second stage of the logic tree) be symmetrized, and that the INVERTER gates 200, 201, 202, and 203 (in such second stage) also be symmetrized. Likewise it is important that the NAND gates 120, 121 and the INVERTER gates 210 and 211 in the third stage be symmetrized, and that the NAND gate 130 and the INVERTER gate 220 in the fourth stage be symmetrized. In this way, skews will not accumulate over a multiplicity of stages. It is further desirable, though not crucial, that the NAND gates 100, 101, 102, ... 107 (in the first stage) be symmetrized. As further shown in FIG. 1, a total of eight input pulsed information signals A0, A1, A2, ... A7 are controlled by a total of eight control signals C0, C1, C2, ... C7, respectively. At any instant of time at most one of these control signals is at the logic high level and hence at most one of the NAND gates 100, 101, 102, ... 107, respectively, is enabled, i.e., enables the corresponding one of the information signals to propagate through that one of NAND gates. For example, if control signal C2 is high and the remaining control signals are low, then A2 and only A2 propagates (as A2 )to the next stage of multiplexer, i.e., propagates to the NAND gate 111 in the second stage of the tree. Since all other control signals, including C3 in particular, are thus then low, the output of the NAND gate 103 will be high and hence will enable the NAND gate 111 to pass along the signal A2 to the INVERTER gate 201, and then to pass along the resulting signal A2 to the NAND gate 120 in the third stage, and so forth through the remaining fourth stage (or still further stages, if any). Thus the input information signal A2, and no other, can propagate all the way to the output pads 400 and 400' as output information signals A2 and A2 , respectively, if and when C2 is high. Similarly, any one of the other input information signals can propagate to and arrive as an output information signal and its complement at the output pads 400 and 400', respectively, if and when that other signal's corresponding control signal is high. As shown in FIG. 2, the previously described fan-in multiplexer logic tree 300 is folded into a compact folded layout scheme in the XY plane (major surface of semiconductor chip). The layout consists essentially of first and second interconnected columns 301 and 302, respectively, in order to minimize signal skews caused by interconnection wiring delays and at the same time economize on semiconductor chip area. The first column 301 contains the first stage and only the first stage of the multiplexer logic tree, consisting essentially of the NAND gates 100, 101, 102, ... 107; whereas the second column 302 contains all the remaining stages of the logic tree. It should be noted that in case the first stage is designed to receive more than just 8(= 2³) information signal inputs A0, A1,...A7 (plus a separate control signal input C0, C1, C2...C8 for each such information signal input) but instead is designed to receive say 2 n inputs (n = integer), then the first column will contain 2 n NAND gates, and the second column will contain 2 n -1 NAND gates each of which has its output terminal connected to the input terminal of a corresponding INVERTER gate--i.e., similarly to the way the second column 302 is constructed as shown in FIG. 2--plus a final INVERTER gate similar to the INVERTER gate 230 in the second column 302. In other words, each stage (except the first) consists essentially of half as many NAND gates as the stage immediately preceding it plus an INVERTER gate in cascade with each such NAND gate, and there are a total of (n + 1) stages. Note that in the layout of the logic tree 300 the first and second columns 301 and 302, respectively, both run along parallel to the Y direction: i.e., both of these columns may be viewed as running either in the +Y or the -Y direction. Note that at any location in the Y direction the first column 301 has a width (in the X direction) of only one logic gate, i.e., is one NAND gate wide; whereas the second column is at two logic gates wide, i.e., a NAND gate connected in cascade with a INVERTER gate. Advantageously, all the NAND gates 100, 101,... 107 in column 301 are mutually identical, and in column 302 all the NAND plus INVERTER gate cascades are mutually identical. In this way the electrical path length, including both wiring and gate delays, from each input A0, A1, ... A7 to the node N1 is the same for all. Thus, when switching the logic high level from one of the control signals C0, C1, C2, ... C7, to another, the corresponding information signals arrive at node N1 in a correlated manner. For example, if initially C2 = 1, C6 = 0 and immediately thereafter C2 = 0, C6 = 1, then at the node N1 the trailing edge of the arriving information pulses corresponding to the information signal A2 will immediately be followed by the leading edge of the arriving information pulses corresponding to the information stream A6 without undesirable overlap or delay therebetween. FIG. 3 shows an 8 input x 8 output crossbar switching arrangement 500 comprising eight input signal pads I0, I1, I2, ... I7, for receiving eight input information signals; eight input buffers IB0, IB1, IB2, ... IB7 for developing proper signal levels for the eight input information signals A0, A1,... A7; eight multiplexer logic trees 300, 310, 320,...370, each constructed in accordance with the compact folded layout 300 consisting of first and second columns 301 and 302 shown in FIG. 2 together with first and second signal paths (not shown in detail) for developing eight output information signals and their complements at output pads 400, 400', 401, 401',...407, 407'. In addition, there are 8 x 8 = 64 control signals. A first set of eight of them, designated by {C}0, is delivered to the first stage of logic tree 300, just as C0, C1,...C7, as previously described--i.e., {C}0 is the set formed by C0, C1,...C7. A second set of eight of them, designated by {C}1, are similarly delivered to the first stage of a second logic tree 310; and so forth, until finally an eighth set of eight control signals {C}7 are similarly delivered to the first stage of an eight logic tree 370. Note that each of the input information signals A0, A1,...A7 is connected as an input to the first stages of all the trees 300, 310,...370. It should be understood that the arrangement 500 can be expanded from an 8 input x 8 output to a 64 input x 17 output (or more) crossbar switching arrangement integrated in a single silicon ship simply by having a total of 64 input pads, a total of 64 input buffers, a total of 17 multiplexer logic trees, each of the trees having a first stage consisting essentially of a total of 64 (= 2⁶) NAND gates, and a total of six further stages each of which consists essentially of half as many NAND gates (plus an INVERTER gate in cascade with each such NAND gate) as the stage immediately preceding it. In this way, a 64 input x 17 output crossbar switch in CMOS technology has been fabricated in a single silicon chip with a minimum feature size of about 1.25 microns and has been successfully tested and operated at data rates as high as 280 megabits per second. A compact folded layout for such a 64 input crossbar switching arrangement is shown in FIG.4 wherein each box in column 601 represents a single NAND gate, and each box in columns 602 and 603 represents a NAND gate plus an INVERTER gate connected in cascade therewith, the structure of each such column for positive values of Y being a mirror image of the structure of such column for negative values of Y. It should be noted that the arrangement 500 enables any input signal to be delivered simultaneously (i.e., to be broadcast) to as many output pads as desired, depending upon the control signals. Note further, that at any instant of time at most one of the first set {C}0 of control signals should be high, plus (if desired) at most one of the second set {C}1, etc., lest more than one of the input signals be delivered to the same output pad at the same time and thereby cause undesired confusion. It should be understood that ultimately each of the input pads and each of the output pads in the arrangement 500 ultimately is connected to a subscriber (not shown) in a telecommunication system, either through further electronic means or through electro-optic and optical means, or both, as known in the art. Although the invention has been described in terms of specific embodiments, various modifications can be made without departing from the scope of the invention. For example, instead of symmetrized CMOS NAND gates, symmetrized CMOS NOR gates can be used, made from conventional CMOS NOR gates by adding PFETs in the PMOS portion.

Claims: A logic circuit layout for a fan-in logic tree (300) composed of a plurality N of logic devices, each of such devices having a first and a second input terminal and an output terminal, CHARACTERIZED IN THAT the plurality comprises 1st through 7th such devices (110, 120, 111, 130, 112, 121, 113) sequentially arranged in a column (302), whereby the column comprises in sequence the 1st through 7th devices, the first and second input terminals of the 1st, 3rd, 5th, and 7th devices (110-113) are separately connected to receive signals emanating from sources that are external to all of the N devices, the output terminals of the 1st and the 3rd devices (110, 111) are separately connected to the first and second input terminals, respectively, of the 2nd device, (120), the output terminals of the 5th and 7th devices (112, 113) are separately connected to the first and second input terminals, respectively, of the 6th device, (121), the output terminals of the 2nd and 6th devices (120, 121) are connected to the first and second input terminals, respectively, of the 4th device (130), the first and second input terminals of the 1st, 3rd, 4th, 5th, and 7th devices (110, 113), as well as the output terminals of the 2nd and 6th devices (120, 121), are all located essentially on a first side of the column, and the first and second input terminals of the 2nd, and 6th devices (120, 121), as well as the output terminals of the 1st, 3rd, 4th, 5th, and 7th devices, are all located essentially on a second side of the column opposite the first side thereof. The layout of claim 1 FURTHER CHARACTERIZED IN THAT all of 1st through 7th such logic devices are mutually substantially identical in structure. The layout of claim 2 in which each of the 1st through 7th devices consists essentially of a two-input NAND gate and a single-input inverter, the output terminal of the NAND gate being connected to the input terminal of the inverter. The layout of claim 1 FURTHER CHARACTERIZED IN THAT the plurality N further comprises 8th through 15th such devices sequentially arranged in the column, whereby the column comprises in sequence the 1st through 15th devices, the first and second input terminals of the 9th, 11th, 13th, and 15th devices are separately connected to receive signals emanating from sources external to all of the N devices, the output terminals and the first and second input terminals of the 9th through 15th devices are connected among one another in the same way as the output terminals and the first and second input terminals, respectively, of the 1st through 7th devices, respectively, are connected among one another, the output terminals of the 4th and 12th devices are separately connected to first and second input terminals, respectively, of the 8th device, the first and second input terminals of the 9th, 11th, 12th, 13th, and 15th devices, as well as the output terminals of the 8th, 10th and 14th devices, are all located essentially on the first side of the column, and the first and second input terminals of the 8th, 10th and 14th devices, as well as the output terminals of the 9th, 11th, 12th, 13th, and 15th devices are all located essentially on the second side of the column. The layout of claim 4 in which all the logic devices in the column are mutually substantially identical. The layout of claim 5 in which each of the 1st through 15th devices consists essentially of a two-input NAND gate and a single-input inverter, the output terminal of the NAND gate being connected to the input terminal of the inverter.

Inventors: BARBER, FRANK E.
Applicants: AMERICAN TELEPHONE AND TELEGRAPH COMPANY
Application year: 1988
Main classification: H04Q3
IPC codes: H03K19, H01L27, H01L21, H03K17