Apparatus and method for acceleration of effective subtraction procedures by the approximation of the absolute value of the exponent argument difference

Abstract: The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. In the performance of the effective subtraction operation, the determination of absolute value of the difference between the operand exponent arguments must be obtained in order to determine the correct procedure. In the present invention, a difference between a subset of the operand exponent arguments is calculated and the result of this calculation is used to anticipate the correct procedure. By careful selection of the anticipated correct procedure, when the selection is erroneous, the correct result is immediately available. The availability of the correct result is achieved by selecting the subset of operand exponent arguments so that, in the event that the result is erroneous, the correct difference is such that the associated operand fraction (i.e., to be shifted by the amount of the difference) is shifted completely out of the operand fraction field (stored in a register).

Description: 1. Field of the Invention This invention relates generally to data processing systems and, more particularly, to the detection logic unit 72 determine whether the output signals from selection logic unit 73 or the output signals from shift and selection logic unit 74 are applied to subtraction unit 75. The result of the operation of the subtraction unit 75, Y, is applied to selection logic unit 77 along with the operand fractions F A and F B . The operand exponent arguments E A and E B are applied to (11 bit) subtraction unit 76 where DELTA(E) is calculated. DELTA(E), the output signal from subtraction unit 76, is applied to detection logic unit 78. The detection logic unit 78, based on DELTA(E), selects the operand fractions, F A or F B or the output signal of the subtraction unit 75 as the final fraction result (Z). In the preferred embodiment, subtraction units 76 and 76′ are implemented in the same piece of apparatus the 6 lsb signals and the 7 lsb signals being available prior to the complete 11 bit difference being determined. Operation of the Preferred Embodiment When the effective subtraction operation is performed, the value of the difference between the exponent arguments is required to specify the operation involving the operand fractions. The present invention accelerates the effective subtraction operation by calculating a difference between an subset of signal positions of an operand exponent argument. Based on the operand exponent complexity is the result of having to align fractions prior to their addition or subtraction so that the exponents are identical, and then potentially having to normalize the result, i.e., shifting the fraction of the resulting quantity until a logic "1" is stored in the most significant bit position and adjusting the argument of the exponent accordingly. Referring now to Fig. 1, the addition and subtraction operations are defined in terms of effective addition and effective subtraction operations which more correctly identify related operation sequences. The addition and subtraction operations 101 are grouped into an effective addition operation 102 and an effective subtraction operation 103. The effective addition operation 102 includes the operations of adding operands that have the same sign and subtracting operands that have different signs. The effective subtraction operation 103 includes the addition of operands with differing signs and the subtraction of operands with the same sign. Referring next to Fig. 2, the steps in performing the effective subtract operation, according to the related art, is shown. In step 201, the difference between the exponents is determined. Based on the difference between exponents, the logic signals representing the smaller operands are shifted until the arguments of the exponents representing the two operands are the same, i.e., the operand fractions are aligned, in step 202. In step 203 the aligned quantities are then subtracted. If the resulting quantity is negative, then the 2's complement must be calculated, i.e., the subtrahend was larger than the minuend in step 204. In step 205 the most significant non-zero bit position (i.e., the leading logic "1" signal) is determined. Based on this bit position, the resulting quantity operand, is normalized, the leading logic "1" signal is shifted to the most significant bit position and the argument of the exponent is adjusted accordingly in step 206. In step 207, the rounding of the resulting operand fraction is performed. As will be clear to those familiar with the implementation of floating point operations, the seven steps of the effective subtraction operation of Fig. 2 can require a relatively long time for their execution. A need has therefore been felt for a procedure and associated apparatus for accelerating the effective subtraction operation. FEATURES OF THE INVENTION It is an object of the present invention to provide an improved data processing system. It is a feature of the present invention to provide improved apparatus for the execution of floating point operations. It is another feature of the present invention to provide a technique for acceleration of the effective subtraction operation in a floating point unit. It is yet another feature of the present invention to use a difference between a subset of signals of the operand exponent arguments to accelerate an effective subtraction operation.. It is still another feature of the present invention to begin an effective subtraction procedure based on the difference between a subset of operand exponent argument signals prior to the availability of the difference between the exponent arguments. SUMMARY OF THE INVENTION The invention is mainly directed to an apparatus for performing floating point subtraction operations in which operands with differing signs are added and operands with the same sign are subtracted, said subtraction means including first subtraction means for determining a first difference between operand exponent argument signals, wherein said subtraction means further includes: second subtraction means for determining a second difference between a subset of said operand exponent argument signals, said subset of said operand exponent argument signals being selected to exponentially correspond to a number greater than the number of bit positions representing an operand fraction, said second difference being used to identify the only combination of operand fractions for which an operation must be performed; third subtraction means including detection and selection logic unit for detecting and selecting, in response to said second difference, a combination of fraction operand signals from the two initial operand fraction signals, wherein one of said initial fraction operand signals is shifted by an amount corresponding to said second difference; said third subtraction means further including arithmetically combining means to arithmetically combine said selected combination of operand fraction signals to provide a possible final subtraction fraction result signals (Y); and selection means responsive to said first difference for selecting among one of said initial operand fraction signals and said first possible final fraction signal provided by said third subtraction means. The invention is also directed to a method for performing a floating point subtraction operation which includes the addition of operands with differing signs and the subtraction of operands with the same sign, said method comprising the steps of: determining a first difference between operand exponent argument signals; determining a second difference between a subset of said operand exponent argument signals, said subset of said operand exponent argument signals being selected to exponentially correspond to a number greater than the number of bit positions reprosenting an operand fraction, said second difference being used to identify the only combination of operand fractions for which an operation must be performed; detecting and selecting, in response to said second difference, a combination of fraction operand signals from the two initial operand fraction signals, wherein one of said initial fraction operand signals is shifted by an amount corresponding to said second difference, and further including arithmetically combining means (75) to arithmetically combine said selected combination of operand fraction signals to provide a possible final subtraction fraction result signals (Y); and, selecting, based on said first difference, a correct final fraction result from among one of said initial operand fractions and said possible fraction difference. The aforementioned and other features are accomplished, according to the present invention, by providing in a floating point execution that includes, in addition to the apparatus for determining the difference between operand exponential arguments, apparatus for determining the difference between a subset of the operand exponent arguments. The subset difference apparatus provides a result prior to a determination of the complete difference between the operand exponent arguments. The subset difference is used to begin subtraction of differences between operand fractions (or fractional portions thereof). The procedures are chosen so that when the complete operand argument difference is different from the subset operand argument difference, the correct result fraction is one of the operand fractions, a quantity that is available. These and other features of the present invention will be understood upon reading of the following descriptions along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates the relationship between the addition and subtraction operations and the effective addition and the effective subtraction operations. Figure 2 illustrates the steps for performing the effective subtraction operation according to the related art. Figure 3 illustrates the two procedures into which the effective subtract operations are divided in order to accelerate their execution. Figure 4 illustrates the steps in the effective subtraction operation when the absolute value of the difference of the exponent arguments is greater than one. Figure 5 illustrates the steps in the effective subtraction operation when the absolute value of the difference of the exponent arguments is less than or equal to one. Figure 6A and Figure 6B illustrate the effective subtraction flows initiated after determination of the difference between selected portions of the exponential arguments. Figure 7 is a block diagram of the apparatus implementing the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures Fig. 1 and Fig. 2 have been described with reference to the related art. Referring to Fig. 3, the effective subtraction operation can be accelerated by first considering the situation where the absolute value of the difference in the arguments of the exponents of the two operands, or the absolute value of DELTA(E), is = or<1 (i.e., is equal to less than 1) or is >1 (i.e., all other values), that is, ABS{DELTA(E)} = or <1 or ABS{DELTA(E)}>1. Referring next to Fig. 4, the situation where ABS{DELTA(E)}>1 is examined in more detail. Comparing Fig. 4 with Fig. 2, the determination of the difference in the arguments of the exponents is performed in each case, in step 201 and in step 401. However, because the larger operand is identified, the subtraction operation, performed in steps 203 and 403 can be performed to insure that a positive resultant quantity is obtained by the operation, obviating, in the process illustrated in Fig. 4, the necessity of a step equivalent to the step 204 for the negation of the resulting operand. Because of the amount of the difference between operands, the result that the normalization will require a shift of at most one bit position for the resulting operand. A one bit position shift does not require a separate step and the detection of the leading logic "1" signal in step 404A, the normalization in step 404B and the rounding operation in step 404C can be considered a single time consuming step 404 rather than three time consuming steps (i.e., step 205, 206 and 207) in Fig. 2. Referring next to Fig. 5, the technique for reducing the time to execute (i.e., by accelerating) the effective subtraction operation when ABS{DELTA(E)}≦1 is shown. In step 501, the difference between the exponent arguments is determined. Because of the small difference in the arguments, the alignment of the fractions in step 502 can be performed without requiring a separate step (or "on the fly") before performing the subtraction step 503. The negation step 504 can be required, but either the normalization step 506 or the rounding step 507 is required, but not both steps. The procedure reduces the seven major steps to five major steps by the floating point apparatus. Referring next to Fig. 6A, the results of determining the difference, TDELTA(E), between the (six) least significant position subset of the operand exponent argument, the operation involving the operand fractions initiated as a result TDELTA(E), the correct DELTA(E) and the final fraction result are shown. When, for example the TDELTA(E)=0, then the operation for determining FRACTION A -FRACTION B is begun. The result of calculating DELTA(E) can take only one of three values, i.e., 0, > or = 64, and < or equal -64. When DELTA(E)=0, then the correct final fraction is FRACTION A -FRACTION B . When DELTA(E) > or equal 64, then the correct final fraction = FRACTION A . When DELTA(E) < or equal -64, then the correct final fraction result is FRACTION B . FRACTION A and FRACTION B are available and no computation is necessary to provide these results. These operand fractions are correct because the operand fraction typically (but not necessarily) includes only 53 positions, so a shift by 64 or more positions reduces the associated operand fraction to 0. Similarly, when TDELTA(E)=1, the computation of the final fraction result FRACTION A -FRACTION B /2 is initiated. When this final fraction result is not correct, based on the calculation of DELTA(E), the correct final fraction result will be either FRACTION A or FRACTION B . When TDELTA(E)=-1, the computation of the final fraction FRACTION B -FRACTION A /2 is begun. If this fraction is incorrect, the correct final fraction result will he FRACTION A or FRACTION B as indicated in Fig. 6A. When TDELTA(E) takes on a value different from 0, 1 and -1, Fig. 6A lists the correct final fraction results under 'other' as a function of DELTA(E). In order to accelerate the computation of the final fraction result, several techniques can be employed, the technique of the preferred embodiment being shown in Fig. 6B. In this technique, a difference T7DELTA(E) is calculated, being the difference between the seven least significant bit signals of the operand exponent argument. When TDELTA(E)>1 and < or equal 62, and T7DELTA(E)>1 and < or equal 62, then the computation of the final fraction FRACTION A -{FRACTION B /2 T7DELTA(E) } is initiated. This quantity will be correct when DELTA(E)>1 and < or equal 62. Otherwise, FRACTION A is used when DELTA(E)>129 and FRACTION B is used when DELTA(E) < or equal -66. When TDELTA(E)>1 and < or equal 62 and T7DELTA(E) > or equal 66 and <127, then computation is begun on the final fraction result FRACTION B -{FRACTION A /2 -T7DELTA(E) }. This final fraction result will be correct when DELTA(E) > or equal -62 and <-1. Otherwise, the final fraction result will be FRACTION A when DELTA(E) > or equal 66 or FRACTION B when DELTA(E)<-129. Referring next to Fig. 7, the apparatus implementing the procedures of Fig. 6A and Fig. 6B is shown. The 7 least significant bits (lsbs) of operand exponent argument E A and the 7 least significant bits of operand exponent E B are applied to (7 bit) subtraction unit 76′. The 6 least significant bit difference, also referred to as TDELTA(E), is applied to detection and logic unit 72, while the 7 bit difference between E A and E B , also referred to as T7DELTA(E) is applied to shift and selection logic unit 74. The shift and selection logic unit 74 also has the operand fractions FRACTION A (F A ) and FRACTION B (F B ) and a control signal from detection logic unit 72 applied thereto. The detection logic unit 72, based on TDELTA(E), can make the decision between the 1, -1, 0 and other procedures of Fig. 6A. The shift and selection logic unit 74, based on T7DELTA(E), selects the procedures outlined in Fig. 6B. The output signals X A and X B from shift and logic unit 74 are the individual quantities in the final fraction column of Fig. 6B, i.e., the quantities determined when TDELTA(E)>1 and < or equal 62 and when T7DELTA(E)>1 and < or equal 62 or when T7DELTA(E) > or equal -62 and <-1. The output signals X A and X B from shift and selection logic unit 74 are applied to subtraction unit 75. Selection logic unit 73 receives the operand fraction signals F A and F B and control signals from detection logic unit 72. The selection logic unit 73 determines the components of the final fraction result calculation illustrated in the final fraction result column of Fig. 6A. The output signals of the selection logic unit 73, X A and X B , are applied to subtraction unit 75. The control signals from detection logic unit 72 determine whether the output signals from selection logic unit 73 or the output signals from shift and selection logic unit 74 are applied to subtraction unit 75. The result of the operation of the subtraction unit 75, Y, is applied to selection logic unit 77 along with the operand fractions F A and F B . The operand exponent arguments E A and E B are applied to (11 bit) subtraction unit 76 where DELTA(E) is calculated. DELTA(E), the output signal from subtraction unit 76, is applied to detection logic unit 78. The detection logic unit 78, based on DELTA(E), selects the operand fractions, F A or F B or the output signal of the subtraction unit 75 as the final fraction result (Z). In the preferred embodiment, subtraction units 76 and 76′ are implemented in the same piece of apparatus, the 6 lsb signals and the 7 lsb signals being available prior to the complete 11 bit difference being determined. Operation of the Preferred Embodiment When the effective subtraction operation is performed, the value of the difference between the exponent arguments is required to specify the operation involving the operand fractions. The present invention accelerates the effective subtraction operation by calculating a difference between an subset of signal positions of an operand exponent argument. Based on the operand exponent argument subset difference, a difference in the operand fractions (or fractional portion thereof) is determined during the time that the difference between the complete operand exponent arguments is being calculated. The subset is chosen so that when the complete difference is determined and the current procedure determined to be the incorrect procedure, the correct resulting fraction is available. This availability is accomplished by providing that, when the operand fractions are shifted by an amount represented by any operand argument position not in the subset, the shifted operand fraction has a value of zero. Therefore, the non-shifted operand fraction is all that remains and becomes the final resulting fraction. The difference in the operand argument subsets can identify the only combination of operand fractions for which an operation (subtraction) must be performed. This operation requiring a calculation is initiated prior to the determination of the difference between the complete operand arguments. Thus, when the difference between the complete operand arguments is available, the final fraction result, if a calculation is required, will be at least in progress, thereby accelerating the computation. The other possible final fraction results are operand fractions and are available based on the differences between the complete operand exponent arguments. The foregoing description is included to illustrate the operation of the preferred embodiment.

Claims: Apparatus for performing floating point subtraction operations in which operands with differing signs are added and operands with the same sign are subtracted, said subtraction means including first subtraction means (76) for determining a first difference between operand exponent argument signals, wherein said subtraction means further includes: second subtraction means (76′) for determining a second difference between a subset of said operand exponent argument signals, said subset of said operand exponent argument signals being selected to exponentially correspond to a number greater than the number of bit positions representing an operand fraction, said second difference being used to identify the only combination of operand fractions for which an operation must be performed; third subtraction means (76-75) including detection and selection logic unit (72-74) for detecting and selecting, in response to said second difference, a combination of fraction operand signals from the two initial operand fraction signals, wherein one of said initial fraction operand signals is shifted by an amount corresponding to said second difference; said third subtraction means (72-75) further including arithmetically combining means (75) to arithmetically combine said selected combination of operand fraction signals to provide a possible final subtraction fraction result signals (Y); and selection means (77, 78) responsive to said first difference for selecting among one of said initial operand fraction signals and said first possible final fraction signal provided by said third subtraction means. The apparatus for performing floating point subtraction operations of Claim 1 wherein said second subtraction means (76′) is a portion of said first subtraction means (76). The apparatus for performing floating point subtraction operations of Claim 1 wherein said first and said second subtraction means (76) and (76′) operate in parallel. The apparatus for performing floating point subtraction operation of Claim 1 wherein said second and said third subtraction means (76′) and (72, 73, 74, 75) determine said possible final fraction signals requiring calculation in parallel with operation of said first subtraction means (76). The apparatus for performing floating point subtraction operation of Claim 1 wherein said apparatus further includes addition means for performing floating point addition operations by adding operands that have the same sign and subtracting operands that have different signs. The apparatus for performing floating point addition and subtraction operations of claim 5 further comprising operation means responsive to operand fraction signs for selecting a one of an addition and a subtraction operation. A method for performing a floating point subtraction operation which includes the addition of operands with differing signs and the subtraction of operands with the same sign, said method comprising the steps of: determining a first difference between operand exponent argument signals; determining a second difference between a subset of said operand exponent argument signals, said subset of said operand exponent argument signals being selected to exponentially correspond to a number greater than the number of bit positions representing an operand fraction, said second difference being used to identify the only combination of operand fractions for which an operation must be performed; detecting and selecting, in response to said second difference, a combination of fraction operand signals from the two initial operand fraction signals, wherein one of said initial fraction operand signals is shifted by an amount corresponding to said second difference, and further including arithmetically combining means (75) to arithmetically combine said selected combination of operand fraction signals to provide a possible final subtraction fraction result signals (Y); and, selecting, based on said first difference, a correct final fraction result from among one of said initial operand fractions and said possible fraction difference. The method of performing a subtraction operation of Claim 7 further comprising the step of initiating calculation of said possible operand combination in parallel with said determining said first difference.

Inventors: GAVRIELOV NASHUM MOSHE, GRONOWSKI PAUL E, PENG VICTOR, GAVRIELOV, NASHUM MOSHE, GRONOWSKI, PAUL E., PENG, VICTOR
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1988
Main classification: G06F7
IPC codes: G06F7