Decoding unit for CMI-encoded signals

Abstract: Decoding unit for CMI-encoded input signals. A signal having 0/1 transitions is first derived from a signal. A 0/1 transition occurs in a CMI-signal as the result of encoding a binary zero or two consecutive binary ones. In the latter case the 0/1 transition is preceded two bits earlier by a 1/0 transition. By deriving a signal having 1/0 transitions, delaying this signal by two bit intervals and by comparing it to the first signal, the 0/1 transitions corresponding to a binary zero are then accurately detected. The resultant signal can easily be extended by one bit period, so that independent of any phase inversions of the read clock, the appropriate binary information is always generated.

Description: The invention relates to a decoding unit for CMI-encoded input signals having an input and an output, the input of the decoding unit being coupled via a time delay stage to a first input of a first gate circuit a second input of which is connected to the input of the decoding unit, the output of the gate circuit being coupled to the output of the decoding unit. In a digital multiplex transmission system of the type described in, for example, Netherlands Patent Application NL-A- 8203110, a digital signal is applied at the transmitter end to a CMI-encoding unit in which the digital signal is converted into the CMI-code format (coded mark inversion) recommanded for the bit rate. The CMI-code is a two-level code, in which a logic 0 bit is encoded such that each of the two levels is present during half a bit time interval, first one and then the other level. A logic 1 bit is encoded by one of the two levels during an entire bit interval, more specifically such that the level alternates for consecutive logic 1 bits. At the receiver of the CMI-interface the digital channel includes a CMI decoding unit in which, after equalisation and regeneration with the aid of the recovered system clock, the received CMI-encoded signal is converted into the normal binary code. The original composite digital signal with the nominal bit rate and the original system clock are then available at the output of the CMI-decoding unit. In current decoding units of the above-defined type, as, for example, disclosed in the European patent application EP-A-0,208,558, the time delay stage is constituted by a bistable element producing a delay of half a bit interval. The gate circuit is constituted by an exclusive-OR gate. The CMI-encoded input signal and the delayed version thereof are each applied to an input of the exclusive-NOR gate. The output signal of the exclusive-NOR gate contains the appropriate information as regards the binary data during the second half of each bit interval. In the first half of each bit interval the data then occurring is undefined and assumes at random one of the logic values 0 or 1. Often, from the point of view of bandwidth limitation, the exclusive NOR gate output signal is applied to the D-input of a D-flip-flop to whose clock input a read clock signal is applied. Since in the first half of each bit interval the data then occurring is undefined, it is necessary for the read clock signal to be word-synchronous with the 2-bit words in the CMI-encoded input signal. This has the disadvantage that an additional synchronizing circuit is required to realise this. An example of a decoder of this kind is disclosed in EP-A-0 115 327. The invention has for its object to provide a solution of the problem mentioned in the foregoing, and is characterised, in that the time delay stage comprises a series arrangement of first, second and third delay elements, each providing a delay of half a bit time interval, that the first input of the first gate circuit is connected to the output of a second gate circuit an input of which is connected to the output of the third delay element and another input of which is connected to the output of the second delay element, and that a third input of the first gate circuit is connected to the output of the first delay element to indicate a binary '0' on detecting the presence of a transition from said first level to said second level which is not preceded two halves of a bit time interval earlier by a transition from said second level to said first level. JP-A-61-105946 (abstracted in Patent Abstracts of Japan, vol. 10, no. 153, E-441) discloses a circuit for detecting the discontinuance of a CMI signal. The CMI signal is retimed by a first flip-flop and then passed to three flip-flops in series, acting as half-bit-period delay elements. The inputs and outputs of each delay element are applied to respective exclusive-or gates to detect transmissions in signal level and the outputs of the exclusive-or gates are applied to an or-gate, which thus provides a '0' output whenever the signal level is the same for four successive half-bit-periods, which cannot occur in a valid CMI signal. The invention and its advantages will now be described in greater detail with reference to the accompanying drawings. Fig. 1 shows an embodiment of the decoding unit according to the invention. Fig. 2 shows time-sequence diagrams to explain the operation of the decoding unit of Fig. 1. In the embodiment of Fig. 1, the input I of the decoding unit is connected to the input of a time delay stage III, which comprises the series arrangement of a first delay element 1, a second delay element 2 and a third delay element 3. The output C of the delay stage III is connected to an input of the second gate circuit 4 a further input of which is connected to the output B of the second delay element 2. The output D of the second gate circuit 4 is connected to the first input 14 of the first gate circuit 5. The input I of the decoding unit is connected to the inverting, second input 15 of the gate circuit 5. The third input 13 of the gate circuit 5 is connected to the output A of the first delay element 1. The delay elements 1, 2 and 3 are constituted by D-flip-flops, whose clock signal inputs are jointly connected to the clock signal input 11 of the decoding unit. The first gate circuit 5 and the second gate circuit 4 are formed by NOR-gates. The output E of the NOR-gate 5 is connected to the output H of the decoder unit via the series arrangement of a pulse stretcher II and a bistable element 9. The pulse stretcher II includes the series arrangement of a bistable element 6 and a NOR-gate 7. The signal input d of the bistable element 6 and an input of the NOR-gate 7 are connected to the output E of the NOR-gate 5. The output F of the bistable element 6 is connected to a further input of the NOR-gate 7. The bistable element 6 is preferably a D-type flip-flop. The output G of the NOR gate 7 is connected to the input d of the D-flip-flop 9, whose output 9 is connected to the output H of the decoding unit. The clock input of the flip-flop 9 is connected to the clock input 11 of the decoding unit via the series arrangement of an inverter 10 and a D-flip-flop 8 which is arranged as a divide-by-two divider. Fig. 2a illustrates how the conversion of a binary signal having logic 1-bits and logic 0-bits into a CMI-encoded signal is effected. The CMI-code is a 2-level code in which a logic 0 bit is encoded such that each of the two levels E₁ and E₂ is present during half a bit interval T, first E₁ and thereafter E₂. A logic 1 bit is encoded by one of the two levels E₁ or E₂ during an entire bit interval T, more specifically such that the level is alternated for consecutive logic 1-bits. In the further time sequence diagrams of Fig. 2 E₁ is chosen equal to 0. From a further, careful examination of Fig. 2a it will be apparent that a binary zero is encoded as a 0/1 (E₁/E₂) transition. A further 0/1 transition can only occur at the interface of two encoded ones. In that case the first one is encoded as a 0/0 signal which is then preceded by either an encoded zero (0/1) or an encoded one (1/1). If now a check is made to see whether a 1/0 transition, which precedes a 0/1 transition by a bit interval, is present, an encoded zero and a sequence of encoded ones can be differentiated. The CMI-encoded input signal is delayed by 3 bit intervals by means of the three flip-flops 1, 2 and 3 which are clocked by a read clock signal as shown in Fig. 2 b . The information delayed by one bit interval τ is available at the point A of the decoding unit, see Fig. 2 c . The information delayed by two bit intervals 2τ are available at the point B of the decoding unit, see Fig. 2 d . The signal delayed by 3 bit intervals 3τ is present at the point C of the decoder unit, see Fig. 2 e . The information in accordance with Fig. 2 d and the inverted information in accordance with Fig. 2 e , see broken line, are applied to the inputs of the NOR-gate 4. The output of this gate 4 is in the high state only when the input signals of this gate are equal to zero. This is the case at the instants indicates in Fig. 2 f . When the output D of the gate 4 is in the high state, this implies that two bits intervals 2τ earlier a 1/0 transition was present in the applied CMI-encoded input signal. This is illustrated in Fig. 2f for two 1/0 transitions. The information of Fig. 2 f is applied together with the information of Fig. 2 e and the inverted CMI-encoded input signal of Fig. 2 a , to the inputs of the NOR-gate 5. The output of this gate 5 is high only when all the input signals of this gate 5 are equal to zero. This is the case at the instants indicated in Fig. 2 g . When the output E of the gate 5 is in the high state this implies that a 0/1 transition has occurred which was not preceded two bit intervals 2τ earlier by a 1/0 transition. See, for example, the two last 0/1 transitions in the signal of Fig. 2 a in combination with the fact that the signal shown in Fig. 2 g is in the high state. The signal present at point E of the decoding unit, see Fig. 2 g is delayed by one bit interval with the aid of the flip-flop 6. The signal present at the point E and the delayed signal at the output of the flip-flop 6 are combined with the aid of the NOR-gate 7, see Fig. 2 i . The fully encoded binary signal is now present at the output G of this gate 7. The binary signal present in the point G of the decoding unit see Fig. 2 i , is once again entered into a flip-flop 9 at an appropriate clock signal, so that a fixed relationship is produced between the outgoing binary signal and the read clock signal. Since the read clock signal, see Figs. 2 j and 2 k is generated with the aid of a divide-by-two divider 8, which is clocked with the inverted read clock signal of Fig. 2 b , the active edge of the read clock signal is always contained within the stable period of the signal of Fig. 2 i . The signal transitions in the binary signal of Fig. 2 i have already occurred before the active edges occur, see the arrows in Figs. 2 j and 2 k . When a read clock signal as shown in Fig. 2 j is used, a binary output signal illustrated in Fig. 2 m is produced at the output H of the decoding unit. When a read clock signal as illustrated in Fig. 2 k is used, a binary output signal in accordance with Fig. 2 l is produced at the output H of the decoding unit. Instead of flip-flops, it is alternatively possible to use other types of delay elements such as electrically conducting conductors, cables or microstrips, depending on the frequency range in which the decoding unit is operative. The decoding unit is perfectly suitable for integration in a monolithic IC.

Claims: A decoding unit for CMI-encoded input signals in which a binary '0' is encoded by a first level of signal for half a bit time interval followed by a second level of signal for half a bit time interval and a binary '1' is encoded by said first or second level for one complete bit time interval, consecutive binary '1's being encoded alternately by said first and said second level, said unit having an input (I) and an output (E), the input of the decoding unit being coupled via a time delay stage (III) to a first input of a first gate circuit (5) a second input of which is connected to the input of the decoding unit, the output (E) of the gate circuit (5) being coupled to the output of the decoding unit (H) characterised in that the time delay stage (III) comprises a series arrangement of first, second and third delay elements, (1, 2, 3) each providing a delay of half a bit time interval, that the first input of the first gate circuit (5) is connected to the output of a second gate circuit (4) an input of which is connected to the output (C) of the third delay element (3) and another input of which is connected to the output (B) of the second delay element (2), and that a third input of the first gate circuit (5) is connected to the output (A) of the first delay element (1) to indicate a binary '0' on detecting the presence of a transition from said first level to said second level which is not preceded two halves of a bit time interval earlier by a transition from said second level to said first level. A decoding unit as claimed in claim 1, characterised in that the delay elements are constituted by bistable circuits and that the first and second gate circuits are constituted by NOR gates. A decoding unit as claimed in claim 1 or 2, characterised in that the output of the first gate circuit is coupled to the output of the decoder unit by a pulse stretcher. A decoding unit as claimed in claim 1, 2 or 3, characterised in that the output of the pulse stretcher is connected to the output of the decoding unit via a bistable element, that the clock input of the bistable element is connected to the clock signal input of the decoding unit via the series arrangement of an inverter and a divide-by-two divider. A decoding unit as claimed in claim 3 or 4, characterised in that the pulse stretcher includes the series arrangement of a bistable element and a NOR gate, the signal input of the bistable element and an input of the NOR gate being connected to the output of the first gate circuit and the output of the bistable element being connected to a further input of the NOR gate.

Inventors: AKKERMANS GERARDUS PETRUS MARI, AKKERMANS, GERARDUS PETRUS MARINUS
Applicants: AT & T NETWORK SYSTEMS INT, AT & T NETWORK SYSTEMS NL, AT&T NETWORK SYSTEMS INTERNATIONAL B.V., AT&T NETWORK SYSTEMS NEDERLAND B.V.
Application year: 1988
Main classification: H03M5
IPC codes: H03M5, H04L25