HIGH-SPEED DIGITAL ADDING SYSTEM

Abstract: A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connect­ ed to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipa­ tion at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are conti­ guous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.

Description: This invention relates to a digital computing system comprising: A first binary adder having a plurality of parallel stages equal in number to the bits of input signals, each stage having first, second, third and fourth inputs and first and second outputs, said first binary adder producing at its first output a binary signal representative of the sum of the binary signals applied to its inputs disregarding the carry, and said first binary adder producing at its second output a binary signal representative of the carry of the binary signals applied to its inputs; a second binary adder having a plurality of parallel stages equal in number to the bits of said input signals, each stage having first, second and third inputs and first and second outputs, said second binary adder producing at its first output a binary signal representative of the sum of the binary signals applied to its inputs disregarding the carry, and said second binary adder producing at its second output a binary signal representative of the carry of the binary signals applied to its inputs; connection means for connecting said first output of said first binary adder to said first input of said second binary adder; connection means for connecting said second output of said first binary adder to said third input of the second binary adder of the next higher order stage, and connection means for connecting said third input of said second binary adder to the second output of the first binary adder of the preceding stage, the output of each stage providing a multi-bit, two-component sum signal consisting of a binary sum value and a binary carry value, wherein said binary sum value of said multi-bit, two-component sum signal is provided by said first output of said second binary adder. A digital computing system of this kind is disclosed in DE-A-35 24 797. The adding system in this prior art document is wired as an accumulator; it deals primarily with the measures necessary to ensure that the carry bit in the highest-order adder is correct, without a need for an additional adder stage. This invention pertains thus to the field of digital computing and, more particularly, to a large scale digital computing system capable of performing high-speed addition without unduly increasing power consumption. Addition is a fundamental operation in the arithmetic unit of a digital computing system because it is employed to perform, not only the addition function, but also the multiplication function and the accumulation function. In a conventional adder, the processing time is directly related to the number of bits in the numbers being processed because of the necessity for carries to propagate from stage to stage before the arithmetic result is generated. A number of schemes have been developed over the years, such as the so-called look ahead adder, to generate arithmetic results without the delays occasioned by carry propagation. These schemes require a great deal of extra electronic circuitry and, therefore, dissipate more power than a conventional adder. The present invention provides, in a digital computing system of the kind described above, the following characteristics: Connection means for connecting a first source of a first multi-bit, two-component signal consisting of a binary sum value and a binary carry value to said first and second inputs of said first binary adder; connection means for connecting a second source of a second multi-bit, two-component signal consisting of a binary sum value and a binary carry value to said third and fourth inputs of said first binary adder; connection means for connecting said second output of said second binary adder to the binary carry value of the multi-bit, two-component sum signal of the next higher order stage, and connection means for connecting said binary carry value of said multi-bit, two-component sum signal to the second output of the second binary adder of the preceding stage. According to the invention, sum and carry computations are processed separately during the execution of a plurality of arithmetic operations in tandemly-connected arithmetic units so that carry propagation delay only occurs once, namely, at the end of the multi-operation computation. In the preferred embodiment, a digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. The sum of the first and second signals represents a first binary number to be added. The sum of the third and fourth signals represents a second binary number to be added. The sum of the fifth and sixth signals represents a third binary number to be added. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the second full adder of the next higher order stage, and the fourth source is connected to the augend input of the second full adder. A feature of the preferred embodiment is implementation of the full adders with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. Separate processing of sum and carrier computations and use of currently available low-level logic circuitry permits something on the order of one billion arithmetic operations per second to be carried out with an average power dissipation of only about one watt. The foregoing measures increase the number of wire interconnections fourfold. A doubling of the wire interconnections results from the separate processing of carry and sum signals, and a doubling of the wire interconnections results from the use of bipolar logic circuitry. To better organize and route this increased number of wire interconnections, a feature of the invention is the physical layout of the circuitry on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other. The features of a specific embodiment of the best mode contemplated of carrying out the invention are illustrated in the drawings, in which: FIG. 1 is a block diagram of one stage of a full adder that employs low-level, non-saturating, bipolar differential logic circuitry; FIG. 2 is a schematic circuit diagram of the circuitry of FIG. 1; FIG. 3 is a schematic block diagram of three stages of an adder incorporating principles of the invention; FIG. 4 is a schematic block diagram of a digital computing system incorporating a number of adders of the type disclosed in FIG. 3; FIG. 5 is a schematic block diagram illustrating on an integrated circuit chip the layout of stages within an adder and stages of adjacent adders. In FIG. 1, one stage of a full adder implemented with low-level, non-saturating, bipolar differential logic circuitry is shown. Such a full-adder stage is the basic building block from which the preferred embodiment of the invention is implemented. Single-ended input terminals X, Y, and C i are connected to registers 10, 12, and 14, which have complementary outputs. One bit of a binary addend signal to be added is applied to terminal X. The corresponding bit of a binary augend signal to be added is applied to terminal Y. The next lower order bit of a binary carry signal is applied to terminal C i . The complementary outputs of registers 10, 12, and 14 are connected to a sum circuit 16 and a carry circuit 18. Sum circuit 16 and carry circuit 18 perform the well-known logical functions required to generate a binary sum value and a binary carry value from the signals applied to terminals X, Y, and C i . These logical functions are described, for example, on page 161 of Digital Computer Fundamentals , Second Edition, by Thomas C. Bartee, McGraw-Hill Book company, 1966. The complementary outputs from sum circuit 16 and carry circuit 18 are connected to registers 20 and 22, respectively, to transform them to single-ended form. Thus, register 20 has an output terminal S at which one bit of a binary sum signal appears, and register 22 has an output terminal C o at which one bit of a binary carry signal appears. FIG. 1 illustrates how the use of complementary signals doubles the number of wire interconnections vis-a-vis single-ended signals. In the preferred embodiment of the invention, data transmission from stage to stage of an adder and between successive adders is carried out by complementary signals within an integrated circuit chip. As taught in US-A-4 941 153 entitled High-Speed Digital Data Communication System, the complementary signals are transformed to single-ended signals only to make inter-chip connections or at the end of the computation. In FIG. 2, sum circuit 16 is implemented by a hierarchy of transistors 24 to 33. The emitters of transistors 24 and 25 are connected to the collector of a transistor 34. The emitter of transistor 34 is connected through a resistor 36 to a source of negative bias potential V EE . The base of transistor 34 is connected to a conventional bias voltage source that compensates for changes in the characteristics of the circuitry with changing temperature as described in the above-identified US-A-4 941 153. The disclosure of said application is incorporated fully herein by reference. Input terminal C i is connected to the base of transistor 24, and complementary input terminal C i is connected to the base of transistor 25. Input terminal Y is connected to the bases of transistors 26 and 27. Complementary input terminal Y is connected to the bases of transistors 28 and 29. The emitters of transistors 26 and 28 are connected to the collector of transistor 24. The emitters of transistors 27 and 29 are connected to the collector of transistor 25. Input terminal X is connected to the bases of transistors 30 and 31. Complementary input terminal X is connected to the bases of transistors 32 and 33. The emitters of transistors 30 and 32 are connected to the collectors of transistors 27 and 28. The emitters of transistors 31 and 33 are connected to the collectors of transistors 26 and 29. The collectors of transistors 30 and 33 are connected to the base of an output transistor 36. The collectors of transistors 31 and 32 are connected to the base of an output transistor 38. The collectors of transistors 36 and 38 and the base and collector of a transistor 40 are connected to ground. The emitter of transistor 40 is connected by a resistor 42 to the base of transistor 36. The emitter of transistor 40 is also connected by a resistor 44 to the base of transistor 38. The emitters of transistors 36 and 38 are connected to bias source V EE by resistors 46 and 48, respectively. Output terminal S is connected to the junction of the emitter of transistor 38 and resistor 48. Complementary output terminal S is connected to the junction of the emitter of transistor 36 and resistor 46. Carry circuit 18 is implemented by a hierarchy of transistors 48 to 55. The emitters of transistors 48 and 49 are connected to the collector of a transistor 56. The emitter of transistor 56 is connected through a resistor 58 to source V EE . The base of transistor 56 is connected to a conventional bias voltage source that compensates for changes in the characteristics of the circuitry with changing temperature as described in US-A-4 941 153. Input terminal C i is connected to the base of transistor 48, and complementary input terminal C i is connected to the base of transistor 49. Input terminal Y is connected to the bases of transistors 50 and 51. Complementary input terminal Y is connected to the bases of transistors 52 and 53. The emitters of transistors 50 and 52 are connected to the collector of transistor 48. The emitters of transistors 51 and 53 are connected to the collector of transistor 49. Input terminal X is connected to the base of transistor 54. Complementary input terminal X is connected to the base of transistor 55. The emitters of transistors 54 and 55 are connected to the collectors of transistors 51 and 52. The collectors of transistors 50 and 54 are connected to the base of an output transistor 56. The collectors of transistors 53 and 55 are connected to the base of an output transistor 58. The collectors of transistors 56 and 58 and the base and collector of a transistor 60 are connected to ground. The emitter of transistor 60 is connected by a resistor 62 to the base of transistor 58. The emitter of transistor 60 is connected by a resistor 64 to the base of transistor 56. The emitters of transistors 56 and 58 are connected to bias source V EE by resistors 66 and 68, respectively. Output terminal C o is connected to the junction of the emitter of transistor 58 and resistor 68. Complementary output terminal C i is connected to the junction of the emitter of transistor 56 and resister 66. Transistors 24 to 33 and 48 and 55 are preferably operated in a non-saturating linear mode with a low-level voltage swing of the order of 130-200 millivolts. Typically, these transistors could be FAST-Z FINELINE transistor type VN5H211, with the remaining transistors being type VN5H111. In FIG. 3 is shown three stages of an adder incorporating principles of the invention. These stages, separated by vertical broken lines 70 to 76, process three bits, designated i-1, i, and i+1, of a multi-bit binary addend signal a and a multi-bit binary augend signal b to be added (where i could be a positive or negative number designating the denominational order of the particular bit in question). Each stage comprises two full adders (CSA). Each full adder is preferably implemented as described in FIGS. 1 and 2. Addend signal a comprises two component binary signals, a sum signal and a carry signal. The sum of these component signals represents one of the binary numbers to be added. Augend signal b also comprises two component binary signals, a sum signal and a carry signal. The sum of these component signals represents the other binary number to be added. Although the binary signals are represented as single ended, in practice they are preferably bipolar in nature so as to utilize the logic circuitry described above. Each stage of the adder has first and second full adders, preferably of the type disclosed in FIG. 2, each CSA having complementary input terminals X, Y and C i , and output terminals C o and S. At each stage, one bit of the complementary sum component signal a is applied to complementary input terminals X, the corresponding bit of the complementary carry component signal a is applied to complementary input terminals Y, and the corresponding bit of the complementary sum component signal b is applied to complementary input terminals C i of the first CSA. The complementary signals at output terminals C o of one bit of the first CSA are applied to complementary input terminals C i of the second CSA of the stage for the next higher order bit. The complementary signals at output terminals S of the first CSA are applied to complementary input terminals X of the second CSA of the same stage. The corresponding bit of the complementary carry component signal b is applied to complementary input terminals Y of the second CSA. (Alternatively, the carry component signal b could be applied to input terminal C i of the first CSA and the sum component signal b could be applied to input terminal Y of the second CSA.) Each bit of the resultant signal R generated by the adder comprises a sum component and a carry component as represented in FIG. 3 by R i -1, R i , R i +1. For each stage, the complementary signals at output terminal S comprise the sum component of the resultant signal for the bit, e.g., the "i" bit, and the complementary signals generated at output terminal C o of the next lower order stage, e.g., the "i-1" bit, comprise the carry component of the resultant signal for that bit. In summary, the entire addition process is completed without propagation of carries with an execution time that is independent of the word length of the addend and augend signals. Specifically, the execution time is the sum of the delay times through the first CSA and the second CSA. The invention contemplates a digital computing system that employs a plurality of the adders described in connection with FIG. 3 connected in tandem to perform arithmetic operations such as addition, multiplication, and accumulation. FIG. 4 illustrates a typical digital computing system utilizing the adders of FIG. 3. A multi-bit binary addend signal a and a multi-bit binary augend signal b are applied to an arithmetic unit, i.e., an adder 80 constructed as shown in FIG. 3. Similarly, a multi-bit binary addend signal d and a multi-bit binary augend signal e are applied to another arithmetic unit, i.e., an adder 82 constructed as shown in FIG. 3. Typically, since binary signals a , b , d , and e are input signals to the computing system, they would not have a carry component, although they could. Assuming that they do not have a carry component, one input of the first CSA and one input of the second CSA of each stage, e.g., input terminal Y in FIG. 3, would not be used, or a binary carry component signal representing the number zero would be applied to these input terminals. Adder 80 generates a multi-bit binary component sum signal r₁ and a multi-bit binary component carry signal c₁. The sum of signals r₁ and c₁ represents the sum of the numbers represented by signals a and b . Similarly, adder 82 generates a multi-bit binary component sum signals r₂ and a multi-bit binary component carry signal c₂. Signals r₁, c₁, r₂, and c₂ are applied to another arithmetic unit, i.e., a multiplier 84. Multiplier 84 can be constructed from a number of adders of the type shown in FIG. 3 as building blocks using conventional techniques for digital multiplication such as, for example, the so-called Booth algorithm. Generally, multiplier 84 would have a number of adders of the type shown in FIG. 3 equal to the bits in the numbers being multiplied. Signal r₁ serves as a sum component multiplicand signal, signal c₁ serves as a carrier component multiplicand signal, signal r₂ serves as a sum component multiplier signal, and signal c₂ serves as a carrier component multiplier signal. Multiplier 84 generates a multi-bit binary component product signal r₃ and a multi-bit binary component carry signal c₃. Each adder used in multiplier 84 separately adds a binary sum component signal and a binary carry component signal to another binary signal (with or without components) to produce a separate binary component sum signal and a binary component carry signal. As a result, the time required to complete the multiplication process is dramatically reduced vis-a-vis a conventional multiplier because the carry bits do not propagate from stage to stage. The more bits in the binary signals being processed, the greater the reduction in processing time vis-a-vis a conventional arithmetic unit because the processing time is independent of the number of bits in the binary signals being processed. Binary signal r₃ is applied to an adder 85 as a component addend signal, binary signal c₃ is applied to adder 85 as a component addend signal, and a binary augend signal f is applied to adder 85 to be additively combined with the component addend signals. Depending upon the source of signal f , i.e., whether or not it was the subject of previous processing in the computing system, it could also comprise two component signals. In either case, adder 85, configured as shown in FIG. 3, generates a multi-bit binary component sum signal r₄ and a multi-bit binary component carry signal c₄. The sum of the numbers represented by signals r₄ and c₄ represents the sum of the numbers represented by signals r₃, c₃, and f. Binary signals r₄ and c₄ are applied to an accumulator 86. Accumulator 86, which comprises the adder shown in FIG. 3, an output register for storing sum and carry components of such an adder, and feedback connections to the inputs of the adder, performs the conventional accumulating function of repeatedly adding the sum stored in the output register to the input signal applied to the accumulator. Signal r₄ serves as one component of the signal to be accumulated, and signal c₄ serves as the other component of the signal to be accumulated. Accumulator 86 generates a multi-bit binary component signal r₅, which is the accumulation of the component sum signals generated by the adder, and a multi-bit binary component signal c₅, which is the accumulation of the component carry signals generated by the adder. As a result, the time required to complete the accumulation process is dramatically reduced vis-a-vis a conventional accumulator because the carry bits do not propagate from stage to stage. The more bits in the binary signals being processed, the greater the reduction in processing time vis-a-vis a conventional arithmetic unit because the processing time is independent of the number of bits in the binary signals being processed. Signal r₅ and c₅ are applied to a conventional adder 88, which forms a single, multi-bit binary sum signal R f . In summary, although the illustrated computing system employs numerous adders in performing the arithmetic operations of addition, multiplication and accumulation, only one adder, namely, adder 88, incurs the delay occasioned by propagation of carries through its stages. Thus, the processing time is dramatically reduced. The use of complementary signals and sum and carry components increases the wire interconnections fourfold relative to a conventional carry-propagating adder implemented with single-ended logic circuitry. In order to minimize the complexity of the wire interconnections between stages, the stages of each adder are laid out on an integrated circuit chip in physically contiguous relationship to each other in bit order, and the same order stages of tandemly connected adders are laid out on the integrated circuit chip in physically aligned relationship with each other. This is illustrated in FIG. 5 where an adder 90 is connected in tandem with an adjacent adder 92. Adder 90 has individual adder stages for processing a "0" bit, a "1" bit, a "2" bit, . . . and an "n" bit. Adder 92 has individual adder stages for processing a "0" bit, a "1" bit, a "2" bit, . . . and an "n" bit. Each adder stage is preferably constructed as shown in FIGS. 2 and 3. Other circuit components of an arithmetic unit, such as registers, multiplier related logic circuitry, and accumulator feedback connections, have been omitted for simplicity. These would also be individualized on the integrated circuit chip for each stage and, thus, be laid out in physically contiguous relationship to each other in bit order and in physically aligned relationship with the other circuit components of the same bit. In other words, the circuit components are laid out on the chip in a grid of rows and columns- the rows comprising the same order bits of different circuit components and the columns comprising different order bits of the same circuit components. As illustrated, the stages of adder 90 and the stages of adder 92, respectively, are physically contiguous to each other in bit order, e.g., the "0" bit stage is contiguous to the "1" bit stage, and the "1" bit stage is contiguous to the "2" bit stage, etc. Similarly, the same order stages of adjacent, tandemly-connected adders are physically aligned with each other, e.g., the "0" bit stage of adder 90 is physically aligned with the "0" bit stage of adder 92, and the "1" bit stage of adder 90 is physically aligned with the "1" bit stage of adder 92, etc. As used herein, the term "aligned" means either directly aligned or aligned with a constant offset. FIG. 5 also illustrates the number of signals processed by the stages of adders 90 and 92. Adder 90 operates upon a multi-bit binary addend signals a and a multi-bit binary augend signal b . Each bit of signal a and signal b comprises two bipolar, i.e., complementary, component (e.g., sum and carry) signals. Each bit of signal a and each bit of signal b are applied to the corresponding bit stage of adder 90, e.g., signals a₁ and b₁ are applied to the "1" bit stage of adder 90. Thus, as indicated at a₁ and as indicated at b₁, four augend signals are applied to the "1" bit stage of adder 90. In other words, a total of eight signals are applied to each stage of adder 90. Adder 90 generates a multi-bit binary signal x that represents the sum of the addend and augend signals. Each stage generates four bipolar, i.e., complementary, component (e.g. sum and carry) signals. The component sum signal from each stage is used with the component carry signal from the next lower bit stage to form the input to the same order stage of the adjacent tandemly-connected adder, e.g., the sum component from the "1" bit stage and the carry component from the "0" bit stage of adder 90 together form the four signals designated x₁, and the sum component from the "2" bit stage and the carry component from the "1" bit stage of adder 92 together form the four signals designated Y₂. A multi-bit binary addend signal d is processed with signal x in adder 92. As illustrated, each bit of signal d comprises two bipolar, i.e., complementary, component (e.g., sum and carry) signals. Each bit of signal d and each bit of signal x are applied to the corresponding bit stage of adder 92, e.g., signals d₂ and x₂ are applied to the "2" bit stage of adder 92.

Claims: Digital computing system comprising: (1.1) A first binary adder having a plurality of parallel stages (70,72,74,76) equal in number to the bits of input signals, each stage having first, second, third and fourth inputs (X,Y,C i ) and first and second outputs (S,C o ), said first binary adder producing at its first output (S) a binary signal representative of the sum of the binary signals applied to its inputs (X,Y,C i ) disregarding the carry, and said first binary adder producing at its second output (C o ) a binary signal representative of the carry of the binary signals applied to its inputs (X,Y,C i ); (1.2) a second binary adder having a plurality of parallel stages (70,72,74,76) equal in number to the bits of said input signals, each stage having first, second and third inputs (X,Y,C i ) and first and second outputs (S,C o ), said second binary adder producing at its first output (S) a binary signal representative of the sum of the binary signals applied to its inputs (X,Y,C i ) disregarding the carry, and said second binary adder producing at its second output (C o ) a binary signal representative of the carry of the binary signals applied to its inputs (X,Y,C i ); (1.3) connection means for connecting said first output (S) of said first binary adder to said first input (X) of said second binary adder; (1.4) connection means for connecting said second output (C o ) of said first binary adder to said third input (C i ) of the second binary adder of the next higher order stage, and (1.5) connection means for connecting said third input (C i ) of said second binary adder to the second output (C o ) of the first binary adder of the preceding stage, (1.6) the output of each stage (70,72,74,76) providing a multi-bit, two-component sum signal (R i-1 ,R i ,R i+1 ) consisting of a binary sum value and a binary carry value, wherein said binary sum value of said multi-bit, two-component sum signal (R i-1 ,R i ,R i+1 ) is provided by said first output (S) of said second binary adder; characterized by (1.7) connection means for connecting a first source of a first multi-bit, two-component signal (a i-1 ,a i ,a i+1 ) consisting of a binary sum value and a binary carry value to said first and second inputs (X,Y) of said first binary adder; (1.8) connection means for connecting a second source of a second multi-bit, two-component signal (b i-1 ,b i , b i+1 ) consisting of a binary sum value and a binary carry value to said third and fourth inputs (C i ) of said first binary adder; (1.9) connection means for connecting said second output (C o ) of said second binary adder to the binary carry value of the multi-bit, two-component sum signal (R i-1 ,R i , R i+1 ) of the next higher order stage, and (1.10) connection means for connecting said binary carry value of said multi-bit, two-component sum signal (R i-1 ,R i , R i+1 ) to the second output (C o ) of the second binary adder of the preceding stage. Digital computing system according to claim 1, characterized by connection means for connecting said fourth input of said first binary adder to said second input (Y) of said second binary adder. Digital computing system according to claim 2, characterized in that said binary sum value of said first multi-bit, two-component signal (a i-1 ,a i ,a i+1 ) is fed to said first input (X) of said first binary adder, and said binary carry value of said first multi-bit, two-component signal (a i-1 ,a i ,a i+1 ) is fed to said second input (Y) of said first binary adder. Digital computing system according to claim 2 or 3, characterized in that said binary sum value of said second multi-bit, two-component signal (b i-1 ,b i , b i+1 ) is fed to said third input (C i ) of said first binary adder, and said binary carry value of said second multi-bit, two-component signal (b i-1 ,b i , b i+1 ) is fed to said fourth input of said first binary adder. Digital computing system according to any of claims 2 through 4, characterized in that, in each stage, said first binary adder and/or said second binary adder comprises an addend input, an augend input, a carry input, a sum output, and a carry output. Digital computing system according to any of the preceding claims, characterized by (6.1) a third adder having a plurality of parallel stages equal in number to the bits of said input signals, each stage having first and second inputs and an output, said third adder producing at its outputs a resultant multi-bit binary signal which represents the sum of the numbers represented by binary signals applied to its inputs, and (6.2) means for connecting said output of a stage to the respective inputs of the corresponding order stages of said third adder, wherein (6.3) the second output of each stage is connected to an input of the next higher order stage of the third adder. Digital computing system according to any of the preceding claims, characterized in that said input and/or output signals are complementary signals. Digital computing system according to any of the preceding claims, characterized in that said first and second binary adders are full adders (CSA). Digital computing system according to any of the preceding claims, characterized in that the stages of said first and/or second binary adder are physically contiguous to each other in bit order. Digital computing system according to claim 9, characterized in that the stages of said second adder are physically aligned with the stages of said first adder in bit order.

Inventors: BALLER, HOWARD, H., CONILOGUE, RANDALL, L., KELLEY, EDWIN, A.
Applicants: HUGHES AIRCRAFT COMPANY
Application year: 1988
Main classification: G06F7
IPC codes: G06F7