Pulse conditioning circuit

Abstract: A pulse conditioning circuit is shown which conditions a read back signal from a data storage device by performing amplitude equalization (pulse slimming) and phase equalization. The circuit includes a simplified single stage equalizer that effects both amplitude and phase equalization and does so using components that can be selected or adjusted independently of one another. Further, the principal embodiment shows a single ended circuit that provides the function with a minimum number of components to conserve space on the circuit card as well as reducing cost.

Description: This invention relates to pulse conditioning circuits for conditioning signals representing digital data and more particularly to processing read-back signals representing data recorded on a storage media which are read using a transducer means. BACKGROUND OF THE INVENTION Signal processing of read-back signals has in the past involved the use of equalizer devices in order to correct distortion of the signal. The use of a pulse conditioning circuit, which includes an equalizer, on the input signal from magnetic data storage devices affords a significant reduction in the soft error rate that can provide significant increase in storage capacity at a given tolerated error rate. This can result in an error rate improvement of 100 times or two orders of magnitude. This improvement, in conjunction with transducer head and media development, make possible the major portion of recent storage density improvements. A feedforward equalizer consists of a passive network and a differential amplifier. The input signal to the passive network is "fed forward" and summed or differenced with a portion of the network output signal. The resulting signal is the equalized output. An early equalizer of this type is described in "An Improved Pulse Slimming Method For Magnetic Recording" by R. C. Schneider, IEEE Transactions on Magnetics, September 1975, pp. 1240-1241. The development of equalizer devices has included two stage devices in which each stage functioned to equalize both amplitude and phase. This intermixing of the functions results in adjustment complexity. Equalizers have been improved by a circuit that uses two feed forward stages, but permits independent control of amplitude and phase (IBM Technical Disclosure Bulletin, October 1977, pp. 1705-1706, 'Time Domain Adjustable Equalizer by F Castor and H J Gardner). It has been shown that amplitude equalization can be accomplished using a single feedforward stage, if the passive network is a reflective delay line. This device has been called a cosine equaliser in the article 'Improvement of Recording Density be Means of Cosine Equalizer' by T Kameyama, S Takanami and R Arai, IEEE Transactions on Magnetics, November 1976, pp. 746-748. Another solution is a four stage structure with two stages used for amplitude equalization and two stages for phase equalization, as shown in US Patent Application Serial No. 815,110 (US-A-4 875 112) filed December 31, 1985. Thus all known feedforward equalizers which correct both amplitude and phase use a minimum of two stages while single stage equalizers have had the capability of equalizing for amplitude only. DISCLOSURE OF THE INVENTION According to the invention there is provided a pulse conditioning circuit for conditioning pulse signals representing digital data including a single stage feedforward equalizer for equalizing the pulse signals, characterised in that the feedforward equalizer comprises an RLC circuit connected to the input of a differential amplifier, the RLC circuit comprising: a resistor divider circuit, connected to the first input of the differential amplifier, which operates with the differential amplifier to provide amplitude equalization; and a capacitance/inductance circuit, connected to the second input of the differential amplifier, which operates with the differential amplifier to provide phase equalization. The invention thus avoids the necessity for a minimum of two feedforward stages to equalize both phase and amplitude. Preferably, said first means and said second means are arranged to operate independently of each other such that altering component values of the resistor divider circuit affects only amplitude equalization and altering component values of the capacitance/inductance circuit affects only phase equalization. Preferably, the amplitude equalization is a function of the ratio of resistance values in the divider circuit and the phase equalization is a function of the values of the capacitance and inductance in the capacitance/inductance circuit. It is further preferred that said resistor divider circuit includes first and second resistors which are series connected and the values of said inductance and said capacitance are selected such that the characteristic impedance, the square root of the result of the inductance divided by the capacitance, is equal to half the sum of the resistances of said first and second resistors. Preferably, in order to carry out noise suppression, the pulse conditioning circuit further includes low pass filter means (eg, Butterworth filter) connected to the output of said differential amplifier. A further advantage of the present invention is evident in a preferred embodiment wherein the phase distortion introduced by the low pass filter is corrected by choosing the value of inductance (L) and capacitance (C) such that Although the application of the preferred circuit of the present invention is to a magnetic recording read-back system, application to other forms of storage system, such as optical, and to telecommunications can be envisaged. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a simplified schematic of a pulse conditioning circuit according to the present invention; Fig. 2 is a more detailed circuit diagram illustrating the equalizer and filter circuitry of Fig. 1; Fig. 3 illustrates an alternative double ended pulse conditioning circuit according to the present invention; and Figs. 4 through 7 depict the frequency response. DETAILED DESCRIPTION Fig. 1 is a schematic showing of a pulse conditioning circuit according to this invention consisting of a single stage RLC feedforward equalizer followed by a five pole, Butterworth low pass filter for noise suppression. The equalizer receives a data signal which is read by a transducer from a storage media and is current driven from the AGC circuitry and transmits the equalized signal to the detector (DET) circuitry. The amount of pulse slimming (amplitude equalization) is controlled by resistors R1 and R2. The phase equalization is controlled by capacitor C1 and inductance L1. For initial selection of L and C, the phase distortion introduced by the low pass filter can be corrected by choosing the values of L1 and C1 such that: equals substantially 0.6 to 0.8 times the filter cutoff frequency. In the absence of further compensation, the characteristic impedance: should equal approximately half of the total resistance R1 + R2, where (R1 + R2) is chosen as the DL load resistance for Is. With reference to Fig. 1, the transfer function, H(s), of the equalizer is given in Equation 1, where A is the amplifier gain, s = jw , R = R1 + R2 and w = 2f x Pi is the angular frequency. The phase of the H(jw) is shown in Equation 2 and the gain of H(jw) is shown in Equation 3. Amplitude equalization is controlled by adjusting only the ratio of R2 and R1 and keeping R constant. The phase remains constant as long as L1, C1 and R are kept constant as shown in Equation 2. Phase equalization is controlled by adjusting only L1 and C1 and keeping the ratio of L1 to C1 constant. This minimises the change in the amplitude equalization, which merely shifts up or down in frequency as seen in Equation 3. The fine tuning of L1, C1, R1 and R2 is required to achieve optimum performance for a given recording system. In order to take advantage of the independent controls offered by the equalizer, the following sequence of events should be followed. First, select the initial value of R. R is selected to accommodate the DC biasing of the circuit and to insure the values of L1 and C1 are reasonable. Next, select L1 and C1 such that the square root of the ratio L1 to C1 is approximately equal to R divided by two as explained earlier. Continue to adjust L1 and C1 in order to fine tune the phase to compensate for any phase non-linearity of the low pass filter or read-back signal, head or disk. Fig. 4 shows how the phase changes when both L1 and C1 are adjusted from nominal (case 1) to + 10% (case 2) and - 10% (case 3) while keeping the ratio of L1 to C1, R1 and R2 constant. Fig. 5 shows how the gain changes when both L1 and C1 are adjusted from nominal (case 1) to + 10% (case 2) and - 10% (case 3) while keeping the ratio of L1 to C1, R1 and R2 constant. Note that while adjusting the phase with L1 and C1, the amount of amplitude equalization remains constant although it is shifted in frequency. Once L1 and C1 have been selected for the proper phase equalization, the ratio of R2 to R1 should be fine tuned to obtain the desired amplitude equalization. Fig. 6 shows how the gain changes when the ratio of R2 to R1 is adjusted from nominal (case 1) to + 10% (case 4) and - 10% (case 5) while keeping L1, C1 and R constant. Fig. 7 shows how the phase changes when the ratio of R2 and R1 is adjusted from nominal (case 1) to + 10% (case 4) and - 10% (case 5) while keeping L1, C1 and R constant. Note that while adjusting the gain with R2 and R1, the phase equalization remains constant. This is a pulse conditioning circuit including a single ended equalizer that performs the required functions while affording a simplified circuit. The circuit does not duplicate the circuits of even the single stage as would be required for a double ended device using both inputs from the automatic gain control (+AGC and -AGC). The differential amplifier 10 transmits the output pulse to a modified low pass (MLP) filter which is illustrated as a five pole Butterworth (BW) filter. BW filter 12 includes capacitors C6, C7 and C8 connected as shunts to ground and inductor elements L2 and L3 connected in series with the output of differential amplifier 10. The filter elements within BW filter 12 perform successive integrations of the pulse received from differential amplifier 10 producing a filtered pulse at the filter output which is supplied to the detection circuitry, +DET and -DET. In the environment of a magnetic disk storage device, a signal from the transducer coil is received by the arm electronics circuitry and transmitted through the automatic gain control (AGC) circuit to the detection circuits (DET). Fig. 2 is a device level showing of the pulse conditioning circuit of Fig. 1. The +AGC input signal is applied to the input of the single ended equalizer that includes amplitude equalizing resistors R1 and R2 and the phase equalizing components, inductance L1, capacitance C1. The circuit and method using a single stage as shown affords the lowest cost implementation and fewest circuit components. The simplicity of design is coupled with flexibility and convenience, since phase and amplitude can be independently adjusted with non-interfering controls. When chosen in sequence, the values of amplitude adjusting resistors R1 and R2 and the values of phase adjusting components, inductor L1 and capacitor C1 can be selected and adjusted independently of one another. Fig. 3 shows a double ended pulse conditioning circuit which includes a similar single equalizer stage for each output of the AGC. This effectively duplicates the components in each branch of the equalizer circuit. The +AGC signal has amplitude adjustment, pulse slimming by selection of the resistance values of R1 and R2 and phase adjustment by selection of the values of inductor L1 and capacitor C1. The equalization stage output is fed to the differential amplifier including transistors T1, T2, T3 and T4 with the output from the differential amplifier received by the Butterworth filter 12 which includes capacitors C6, C7, C8 and inductors L1, L2. The -AGC signal is conditioned by an identical circuit wherein the amplitude equalization or pulse slimming is provided by resistors R11 and R12 and phase equalization is afforded by the selection of inductor 11 and capacitor 11. The differential amplifier includes transistors T11, T12, T13 and T14 and the filter 13 includes capacitors C16, C17, C18 and inductors L12, L13. In a disk drive environment, the form factor or overall dimensions of the unit are usually set by a standard that has either been established or arrived at on a de facto basis. Within the dimensions space is at a premium as capacities are increased. The pulse conditioning circuit provides a low cost means of enhancing storage capacity at a constant soft error rate, but the inductor and capacitor components of this circuit function are not adaptable to inclusion in a large scale integration chip. These components use space or real estate on a printed circuit board where such space is in great demand and usually heroic efforts are undertaken to include all circuit components for the device on a single board. This makes the pulse conditioning circuit with independently adjustable amplitude and phase corrections an attractive means of providing a beneficial function with a minimum number of components that must be individually mounted on the scarce surface of the planar board. This also dictates the use of the single sided equalizer structure of Figs. 1 and 2 which provides the benefits of the circuit while using half the number of individually mounted components.

Claims: A pulse conditioning circuit for conditioning pulse signals representing digital data including a single stage feedforward equalizer for equalizing the pulse signals, characterised in that the feedforward equalizer comprises an RLC circuit (R1,R2,L1,C1) connected to the input of a differential amplifier (10), the RLC circuit comprising: a resistor divider circuit (R1,R2), connected to the first input of the differential amplifier, which operates with the differential amplifier to provide amplitude equalization; and a capacitance/inductance circuit (L1,C1), connected to the second input of the differential amplifier, which operates with the differential amplifier to provide phase equalization. A pulse conditioning circuit as claimed in claim 1 wherein the resistor divider circuit and the capacitance/inductance circuit are arranged to operate independently of each other such that altering component values of the resistor divider circuit affects only amplitude equalization and altering component values of the capacitance/inductance circuit. A pulse conditioning circuit as claimed in claim 1 or claim 2 further including low pass filter means (12) connected to the output of the differential amplifier. A pulse conditioning circuit as claimed in claim 3 wherein the low pass filter means comprises a Butterworth filter (12). A pulse conditioning circuit as claimed in any preceding claim wherein the amplitude equalization is a function of the ratio of resistance values on the resistor divider circuit, and the phase equalization is a function of the values of capacitance and inductance in the capacitance/inductance circuit. A pulse conditioning circuit as claimed in claim 5 wherein said resistor divider circuit includes first and second resistors which are series connected and the values of said inductance and said capacitance are selected such that the characteristic impedance (the square root of the result of the inductance divided by the capacitance) is equal to half the sum of the resistances of said first and second resistors. A pulse conditioning circuit as claimed in claim 5 or claim 6 wherein the phase distortion introduced by the low pass filter (12) is corrected by choosing the value of inductance (L) and capacitance (C) such that

Inventors: KUKSON DEAN RICHARD, MELAS CONSTANTIN MICHAEL, POSS JOEY MARTIN, KUKSON, DEAN RICHARD, MELAS, CONSTANTIN MICHAEL, POSS, JOEY MARTIN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: G11B20
IPC codes: G11B5, H03H7, G11B20, H04B3