IMPEDANCE SYNTHESIS MULTIPLE LOOP USING FILTERING MEANS

Abstract: To supervise a telephone subscriber line (v'2, v'1) and provide it with adjustable AC and DC termination impedances from the exchange (v1, v2), these are supplied by an impedance synthesis multiple loop split into separate DC and AC loop parts by filters at the output of a sense amplifier in the common loop part and fed (e) through a Herter bridge. The amplifier AC output has however to be limited to avoid saturation by a larger DC signal. It now includes a Miller effect integrator output stage (A2) with a low pass frequency response supplying the DC loop and also feeding back an input stage (A1) so that the latter exhibits a high pass frequency response with a DC free output to drive the AC loop and the consequent ability to supply a larger AC output.

Description: IMPEDANCE SYNTHESIS MULTIPLE LOOP USING FILTERING MEANS The invention relates to an impedance synthesis multiple loop using filtering means in association with a ' common loop and with separate DC and AC loop parts * A circuit of this type is known for instance from the European patent application published under No 0201635 * It can be used in telecommunication line circuits in order to synthesize suitable signal (AC) impedances presented to various telecommunication lines from an exchange? as well as resistances (DC) to feed the equipment connected to such exchanges via the telecommunication lines? i ♦e. * provide adequate AC and DC ter inating impedances under various line conditions♦ In this known circuit? particular use of a Herter bridge? providing immunity against longitudinal currents? is made in association with a common sense amplifier which is designed to react to a variety of signals having widely differing characteristics such as speech signals!- DC signals and relatively high voltage AC ringing currents. This sense amplifier is included in the common loop part and its output feeds separate filter- circuits included in both the DC and AC loop parts * In particular? the separate AC loop includes a DC blocking serial capacitance which has a relatively large value for s suitable high pass cut off characteristic eliminating DC but passing the lowest frequency voice si als * Also? in order to cater for the variety of signals that may appear at the input of the sense amplifier? the latter must be carefully designed to avoid saturation by the higher amplitude input signals * Input biassing resistances are used at each of the two inputs terminals of an operational amplifier constituting the sense amplifier * These input biassing resistances are connected to two auxiliary potentials distinct from either ground (0 Volt) or battery potential (-48 Volts)? e * g * -33 and -40 * 5 Volts respectively * As explained in the European application referred to? the first auxiliary potential enables to avoid saturation of the sense amplifier when relatively high voltage ringing signals are applied to the telephone line through the Herter bridge * The second auxiliary potential is used as a special common reference potential for the signals appearing in various parts of the telecommunication line circuit * Since the internal impedances of such auxiliary biassing sources? and particularly the second can never be ideally small? the design must also take care that it will not lead to an unacceptable level of parasitic cross coupled signals * A general object of the invention is to improve the structure of such an impedance synthesis multiρ " le loop by avoiding previous constraints and more particularly reduce the value of the above filter capacitance? /enable a higher AC output from the sense amplifier and avoid a special common reference potential * In accordance with a first characteristic of the invention? the filtering means include a transducer fed from the common loop part and with an input stage cascaded with an output stage? an overall negative feedback loop extending from the output of the output stage to the input of the input stage and one of said stages providing to the AC loop part an output signal excluding low frequency components such as DC* the latter appearing only at the output of the other stage feeding the DC loop part * In this manner? the sense amplifier is now realised as a frequency dependent two-stage amplifier with overall feedback and with the outputs of these two stages supplying directly the low pass? e * g * DC? and high pass <AC) signals respectively♦ In accordance with a further characteristic of the invention? the input stage provides the output signal excluding low frequency components such as DC * This is particularly advantageous for the telecommunication line circuit applications envisaged since in the previously identified European patent application? the amount of gain of the sense amplifier was limited in order to avoid saturation? the AC signal having a relatively small amplitude superposed on a much larger DC amplitude occupying a substantial part of the available voltage range at the output of the sense amplifier * With the new design however? most of that voltage range can be occupied by the output AC signal excursions devoid of any DC component? the latter being only permitted to appear at the output of the output stage? this being eventually true also for low frequency ringing signals * Thus? with only AC signals r maining at the output of the input stage it is now possible to define the gain of that part of the sense amplifier as a function of the maximum AC signal and independently of the DC component * The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of a preferred embodiment taken in co junction with the accompanying drawing epresenting that part of s Subscriber Line Interface Circuit <SLIC) including a Herter bridge feeding a two-stage sense amplifier in accordance with the invention having separate outputs for the AC and DC synthesis loops * The Herter bridge is the classical one discussed in the above identified European patent application and is generally embedded in the same manner in the SLIC * Thus? it is essentially a hexapole network with six impedances in a closed ring and three distinct ports? the two terminals of each port being separated by two parallel sets of three impedances in series * The first port coresponding to the indicated signal voltages vl and v2 is connected to the remaining part LC of the telephone line circuit? the second port corresponding to the indicated signal voltages V r 2 and V goes towards the distant telephone subset or other apparatus (not shown) while the third port has its two terminals identified by the common mode voltage signal e appearing at both the inverting and non-inverting input terminals of operational amplifier Al constituting the input- stage of the sense amplifier and to which this third port is connected * Part LC containing the rest of the multiple loop also gives access to the telephone exchange on a four wire basis as opposed to the bidirectional telephone line on the other side * To simplify some of the subsequent relations* the six impedances constituting the hexapole or Herter bridge have been labelled using en admittance notation so that one has a potential difference v r 2 - vl across feed admittance YO and likewise? v2 - v'l across feed admittance Y'O for the other subscriber wire * In the classical manner for a Herter bridge affording immunity against longitυdial currents and other advantages explained in detail in the above identified European patent application? these feed admittances are relatively high (low resistances)? contrary to the remaining four admittances which have relatively low values? i * e * high resistance potentiometers constituted by admittances Yl and Y'l in series between the terminals having potentials vl and v'l? and correspondingly for Y2 in series with Y'2 between v2 end v'2? the potentiometer- tapping points constituting the inputs of the first stage Al of the sense amplifier * As shown? the inverting input of that stage is biassed to a potential VI through conductance Gl while the non-inverting input is biassed to V2 through G2 * The amplifier input stage Al develops an output signal va at its output which is coupled to the inverting input of Al through admittance Y3 as well as to LC in order to complete part of the multiple loop back to the Herter bridger (vl? v2) * So far? the circuit has the general configuration already disclosed in the above identified European application but in contradistinction thereto? the input stage Al is not a separate sense amplifier to be followed by two separately branched filters at its output in order- to isolate the AC and DC signals * Instead? Al feeds a second amplifier stage A2 and particularly its inverting input since it is also an operational amplifier? and this through the series admittance Ya * This second stage A2 has its non-inverting input suitably biassed? e * g * to ground as indicated? and its output at which a signal vb is developed is connected to its inverting input through admittance Yb * As illustrated? Yb is a capacitance? contrary to the other two-terminal elements such as Ya which are all illustrated as r sistances * In addition to the feedback connection between the output of A2 and its inverting input? 3 further negative feedback connection goes towards the non-inverting input of Al through admittance Y4 * In this manner? it has been found possible to develop a high pass output va from which the DC component has been eliminated and this is used in the AC loop part through the remaining part LC of the circuit * On the other- hand a th out ut o A2? th vb r sponse i a lo a function giving a DC signal which feeds the DC loop part also through LC. While A2 is essentially 3 Miller effect integrato and the negative feedback connection over- the two stages Al and A2 enables Al to exhibit a high pass response without e DC component? the following analysis identifies various interacting design parameters * One may write three current node equations corresponding to the inverting and non-inverting inputs of Al and " o the inverting input of A2 in that order? i * e * <vl-e)Yi+(v' l-e)Y'l+(Vl-e>Gl+(va-e)Y3 = 0 (1) <v2-e)Y2+(v'2-e)Y , 2+(V2-e)G2+(vb-e)Y4 = 0 (2) (va>Ya+(vb)Yb = 0 (3) The above takes into account the usual conditions at the two input terminals of operational amplifiers? i * e * negligible input currents and same common mode voltage * Since there 3re three unknown voltages? i * e * va? vb and e? these C3n be explicitly produced from the above and by simpler expressions if one bears in mind the constraint already highlighted in the above identified European application and namely th3t the output voltage of the first stage Al? and accordingly that of the output stage A2 in view of the simple relation (3)? should solely be proportions! to the sum of the voltages across feed admittances Y0 and Y'O * In other words? one should have va = m(v2-v r l+v l 2-vl) (4) in which is some dimensiαnless parameter-«• In order to achieve such 3 form for vs as the above? by replacing into CD? (2) and (3>? it can be shown that such a result for va? i * e * directly proportional to the current flowing into the subscriber line through the first wire and returning through the second? without any other component for va depending on the bias voltsges VI snd V2? can be secured provided (5) (6) (7) G1 * Y2 * V1 = G2 * Y1 * V2 (8) This last out of the four 3bove relations will 3lso be satisfied irrespective of the values of the admittances involved in the particular case of both VI and V2 being 0 * Using these four constraints on the parameters? the voltage transfer function for vs given by m is defined by m(n+l)Y3 = Yl (9) in which the further di ensionless parameter n is given by n * Y2 * Y3.Yb = Yl * Y4 * Ya (10) Thus? m being now identified in function of the sdmittsnce parsmeters? the response vs is fully determined whereby this is 3lso true for vb in view of the simple relation (3) between the two * On the other hand? using the constraints (5) to (8) as well es the parameters m and n defined by ( ? ) and (10)? the common mode voltsge e at the two inputs of stage Al is identified by e(2Yl+Gl+Y3)=m(n * vl+n * v' l+v2+v ' 2)+V1 * Gl (11) The voltage transfer function for the output voltage vs is given by m spρe3ring in (4) end defined by (9) 3nd (10) from which it is seen that can be expressed ss s function of the r3tio between Ys and Yb * In view of this ratio also linking the output voltages vs and vb in the manner defined by (3)? if Ye and/or Yb are/is the only frequency dependent admittance( ) in the above expressions? then it is possible to obtain frequency complementary characte istics for the output voltages va and vb * For the circuit shown where Ya is purely resistive and Yb is purely cspacitive? a high pass frequency cha acteristic is obtained for va snd a low psss one for vb * By inverting the nature of these two elements? i * e * s capacitance for Ya and a resistance for Yb? the frequency responses would be exchanged so that the low psss one would appear at the output of the input stage Al and the high pass characteristic at the output of the output stage A2 * However? the circuit shown has the advantage that the output amplifier stage A2 is an integrator whereas otherwise it would become a differentiator? the latter being known to be more sensitive tα high frequency noise in view of the series input capscitsnce * Foremost? obtaining the high pass frequency characteristic at the output of the first stage Al is advantageous when a DC component can have 3 substantial amplitude much larger than the AC signal amplitude super-posed thereon * Indeed? in such e case one must then restrict the gain of Al in order to prevent saturation? due to most of the svailable output voltage rsnge being occupied by the output DC signal * This problem is eliminated by removing the DC signal from the output of the first stage Al 3nd providing this DC signs! 3t the output of the second stage A2 instead * In a Herter bridge used in a telephone line circuit to couple sn outside balanced subscriber line to the rest of the telephone exchange? it is often required to have symmetry for the corresponding elements associated with the two wires of the line so that one will have not only the relations (5) and .6 ) but all four admittances Yl? Y'l? Y2 and Y l 2 will be equal to one another just ss this will be the case for the series feed admittances YO and Y'O also part of the Herter bridge * For instance? while these last two might correspond to 50 Ohm resistances? the remaining four impedances constituting the two cross /-connected potentiometers chsrscteristic for the Herter bridge might each have a value of 60 kOhm * With such an additional relation as Yl = Y2? the respective gains obtained at the outputs of Al and A2 will still be determined by the ratio between Yl and Y3 appearing in (9) and between Y3 and Y4 present in (10)? this apart from the frequency response determined by such an admittance as Yb appearing also in the latter * Assuming for instance that unity gain is desired for Al at high frequency whereas only s gain of 1/2 (in absolute value) is desired at the output of A2 for DC? this can be obtained by choosing the same value for Y3 as for Yl? e * g * resistances of 60 kOh ? whereas Y3 will only have half the value of Y4? e * g * a 30 kϋhm resistance for the latter * In such a case one can write 1 Yb pCR m - — =,- =_ (12) i+n 2Ya+Yb 2+pCR in which the first expression for m defining va in view of (4) is directly obtained in function of n in view of (9) whereas (10) enables n to be expressed in function of the ratio between Ya and Yb giving the final expression in terms of R? the pure resistance corresponding to Ya? and C? the pure capacitance corresponding to Yb? p representing hie i a i ary sn υ1sr qu ncy * O th other ha d? calling ' the voltsge transfer function for vb corresponding to m for va given by (4)? this is resdily obtained from (3)? i * e * -Ya -Ya -1 (13) Yb ' 2Ya+Yb 2+pCR In the above? the second expression for m' is again obtained from (10) and the final one by sgsin introducing P? C and R? this showing that the DC gain at the output of A2 is only half the unitary gain at high frequency at the output of Al * If one had desired to obtain strictly complementary characteristics in terms of frequency for m and m' ? i * e * m~ ' equ3l to unity? then this would have been achieved by making both Y3 snd Y4 equal to Yl * Finally? once the values of such admittances as Yl? Y2? Y3? and Y4 have been determined? those of Gl and G2 as well as the biassing voltages VI and V2 can be found from (7) and (8) * For instance? with Y1=Y2 as considered above? in case Y4=2Y3? a suitable solution will be G1=Y4 and G2=Y3 in the particular case where both VI and V2 sre equal to 0? i * e * ground reference potential * In case of both unity gain both at high frequency at the output of Al and f'orour DC at the output of A2? this time with Y3=Y4? it is clear from (7) end (8) that this will be satisfied by G1=G2 and VI-V2 * As in the above mentioned European application? suitable values for the bisssing sources at the inverting and non-inverting inputs of Al will lead to s non objectionable common mode voltage at the input of Al ss defined by e obtained from (ID * While the principles of the invention have been described above in connection with specific apparatus? it- is to be clearly understood thst this description is made only by way of example and not ss s limitstion on the scope of the invention *

Claims: CLAIMS 1 * Impedance synthesis multiple loop using filtering means in association with a common loop and with separate DC end AC loop parts? characterised in that said filtering means include a transducer fed from the common loop pert and with an input stage (Al) cascaded with an output stage (A2)? an overall negative feedback loop (Y4) extending from the output of the output stage towards the input of the input stage and one of ssid stages providing to the AC loop part an output signsl excluding low frequency components such as DC the latter appearing only at the output of the othe stage feeding the DC loop part * 2 * Impedance synthesis multiple loop as claimed in claim 1? characte ized in that said input stage provides _• the output signal excluding low frequency components such as DC. 3 * Impedance synthesis multiple loop as claimed in claim 1? characte ised in that said input stage includes a first operational amplifier- (Al) with a first admittance (Y3) between its output and its inverting input? said output being coupled through a second admittance (Ys) to the invertig input of a second operational amplifier CA2) with a third admittance (Yb) between its output and its inverting input? and e fourth sdmittsnce (Y4) coupling the output of the second operational amplifier to the non-inverting input of the first operetiorisl amplifier to provide ssid negative feedback loop * 4. Impedance synthesis multiple loop as claimed in claim 3? characterized in that ssid first snd fourth 3dmittsnces are resistive * 5. Impedance synthesis multiple loop as clsimed in claims 2 snd 4? chsrscterized in that said second admittance is resistive and S3id third admittance is frequency dependent? e * g * a capacitence * 6 * Impedance synthesis multiple loop as claimed in clsim 1? chsracterized in that it is part of a telecommunication line circuit including s Herter bridge with s first pair of terminals (v'2? v'l) coupled to a bidirectionel two wire line? 3 second psir of terminals (vl? v2> coupled to said separate DC snd AC loop psrtε snd a third psir of terminals (e) coupled to ssid input stage * 7 * Impedance synthesis multiple loop as clsimed in claims 3 and 6? charscterized in that the sdmittsnces Yl and Y'l of the Herter bridge connected to the inverting input of the first operstionsl smplifier have a common value snd that the edmittanceε Y2 and Y'2 of the Herter bridge connected to the non-inverting input of the first operstionsl amplifier have s common velue whereby the 'voltage across said third pair of terminals solely depends on the sum of the voltages between the first terminals (v'2-vl) of said first and second pairs of /.terminals snd between the second terminals (v2-v'l) of ssid first snd second pairs of terminals and is directly proportional thereto♦ 8. Impedance synthesis multiple loop as claimed i claim 7? chsrscterized in that a source of voltsge VI and admittance Gl biasses the inverting input of the first operational amplifier? that a source of voltage V2 and admittance G2 biasses the non-inverting input of the first operational amplifier end that their values sre related to those of the admittances Yl and Y2 and to those of said first (Y3) snd fourth (Y4) admittances by the relations YKG2+Y4) = Y2(G1+Y3) G1 * Y2 * V1 = G2.Y1.V2 * 9 * Impedance synthesis multiple loop as claimed in clai 1? characterized in that low frequency ringing signals mey appear at the output of ssid other stage *

Inventors: GUEBELS PIERRE-PAUL FRANCOIS M, GUEBELS, PIERRE-PAUL, FRANCOIS, MAURICE, MARIE
Applicants: ALCATEL NV, BELL TELEPHONE MFG, ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENN
Application year: 1988
Main classification: H04M19
IPC codes: H04M3, H04M19