Isolation of a charge coupled device

Abstract: An intergrated circuit formed in a semiconduc­ tor die which has at least two distinct functional regions is treated by mounting the die by way of its front face on a support member, and subsequent­ ly removing die material by way of its back face so as to physically separate the functional regions of the die from each other. The optically opaque dielectric material (66) is optional.

Description: Background of the Invention This invention relates to a method of treating a charge coupled device. A charge-coupled device (CCD) may be made by processing a silicon wafer of p conductivity using conventional MOS technology to form a plurality of buried channels of n conductivity beneath the front surface of the wafer (the surface through which the wafer is processed). Each channel is made up of a linear array of like elementary zones. A clocking electrode structure overlies the front surface of the wafer, and by application of selected potentials to the clocking electrode structure, charge present in a given elementary zone of a channel may be advanced through the linear array of elementary zones, in the manner of a shift register, and extracted from the channel. Charge may be generated in the channels photoelectrically. Thus, if electromagnetic radiation enters the wafer it may cause generation of conduction electrons and these conduction electrons may become confined in one of the elementary channel zones. A known type of CCD has three distinct functional components formed in different regions of a single silicon die. The buried channels are formed in a channel region. In operation, the channel region is clocked between voltages of approximately 7-15 volts relative to the substrate, which is typically held at 0 volts. Charge that is propagated to the output ends of the buried channels is applied to an output amplifier which is formed in an amplifier region of the CCD. The output amplifier normally includes at least one field effect transistor. In the known type of CCD the substrate bias in the amplifer region is the same as that in the channel region. The field effect transistor of the output amplifier is generally operated with a large potential difference between the source and substrate and between the drain and substrate. This is required because the gate of the output transistor is connected to an output diode which is required to operate at a voltage of the order of 15 V. The large drain to substrate voltage causes the transistor to operate in an undesirable fashion. First, the large reverse bias on the drain causes light emission to occur from the junction. This light may propagate through the die of the known type of CCD and result in generation of conduction electrons in the buried channels, thus adding noise to the signals received by the output amplifer from the buried channels. Second, the large drain to substrate bias forces the transistor, which is normally of the buried channel type, to operate in the surface channel mode. That is, the conduction channel, which normally would reside away from the silicon/silicon dioxide interface, is forced to the surface. This contributes additional noise to the output signal. It is known to use a level shifting amplifier to couple useful original information from a first circuit node at a first potential to a second circuit node at a second potential. However, it would not be practicable to use a level shifting amplifier to couple the output diode of a CCD to the gate of the output field effect transistor, because it would be the first amplifier in a chain of amplifiers and would inevitably introduce substantial noise into the output signal provided by the amplifier chain. The clock electrodes of the CCD are connected to clock drivers, which may be formed in a clock driver region of the wafer. The clock drivers are used to change the potentials of the clock electrodes at a high frequency, and therefore rapidly changing electric fields are generated by the clock drivers. In the known type of CCD, these fields are coupled through the die to the channel region, and influence the quantity of charge confined in the buried channels. A CCD may be used to generate a two-dimensionally sampled electrical signal representative of the distribution of light intensity over the channel region of the CCD. In such an imaging CCD, it is desirable that the thickness of the die be not much greater than the depth of the interface between the channels and the substrate. This may be achieved by securing the wafer at its front surface to a reinforcing member, and thinning the wafer from its back surface. A prior art method of treating an integrated circuit formed in a semiconductor block is described in US-A-3,665,263 (K. Akiyama), in particular figures 2-4 and column 3, line 1 to line 4, line 46. A method of filling isolation trenches commonly known in the art is shown in IBM Technical Disclosure Bulletin, Volume 27, No. 4A, September 1984, pages 1836 - 1837. A charge coupled device and a method of forming it, having a support member on the front surface of a thinned semiconductor die is known from EP-A-0 203 591. Summary of the Invention The invention consists of a method of treating a charge coupled device as defined in claim 1 and a charge coupled device as defined in claim 5. Advantageous embodiments are disclosed in the dependent claims. Brief Description of the Drawings For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings in which: FIG. 1 is a diagrammatic view of the front surface of an imaging CCD, FIGS. 2A and 2B are partial sectional views of one part of the CCD at two stages in the fabrication thereof, and FIGS. 3A and 3B are partial sectional views of another part of the CCD at the two fabrication stages shown in FIGS. 2A and 2B respectively. Detailed Description The CCD illustrated in FIG. 1 comprises a mono-crystalline die 2 of p conductivity having three distinct functional regions, namely, a channel region 10, a clock driver region 20, and an output amplifier region 30. In the channel region 10, multiple parallel buried channels 12 of n conductivity are formed in the die. Each channel 12 ends in a floating diffusion 13 of n+ conductivity, which is also shown in FIG. 2A. A layer 14 (FIG. 2A) of thermally-grown silicon dioxide covers the buried channels 12. Three arrays of polysilicon clock electrodes 15, 16 and 17 (FIG. 1) extend over the silicon dioxide layer 14, perpendicular to the buried channels 12, and a further layer 18 (FIG. 2A) of silicon dioxide, formed by a reflow operation, covers the clock electrode arrays. Ohmic contact is made to the die 2 inside the channel region 10 by a metal electrode 19 (FIG. 3A). A metal interconnect strip 40 connects the electrode 19 to a bonding pad 42 which, as shown in FIG. 1, lies outside the channel region 10. The clock driver region 20 contains, integrated in the die, a circuit having input terminals which are connected by metal interconnect strips 44 (FIG. 1) to bonding pads 46, which lie outside the clock driver region 20, for connection to a power supply. The circuit also has output terminals connected to the clock electrode arrays 15, 16, and 17 respectively by metal interconnect strips 48. The output amplifier region 30 contains field effect transistors 31 of which the polysilicon gates 32, shown also in FIG. 2A, are connected by metal interconnect strips 49 to the floating diffusions 13 of the channels respectively. Each field effect transistor 31 has a source electrode 33, and pairs of adjacent FETs share a common drain electrode 34. A source diffusion 35, which lies out of the plane of FIG. 2A, is shown in dashed lines in FIG. 2A. The source and drain electrodes 33 and 34 are connected by metal interconnect strips 50 to respective metal bonding pads 52 outside the amplifier region 30. Ohmic contact is made to the die 2 inside the amplifier region 30 by a metal electrode (not shown) which is connected by a metal interconnect strip 55 to a bonding pad 56 which lies outside the region 30. The interconnect strips 40, 44, 48, 49, 50 and the bonding pads 42, 46, 53 are deposited on top of the silicon dioxide layer 18. A layer 60 (FIGS. 2 and 3) of high silica borosilicate glass is formed on top of the front surface of the die, and the die is thinned from its back surface to a thickness of about 10-20 µm. The borosilicate glass, which bonds firmly to the metal interconnect strips and bonding pads as well as to the silicon dioxide layer 18, reinforces as a support member the thinned substrate. The use of borosilicate glass as a reinforcing material for thinned CCDs is described in EP-A-0 203 591. Using conventional photoprocessing techniques, the die is selectively etched from the back surface to the level of the silicon dioxide layer 14, to divide the die into three distinct portions, corresponding to the channel region 10, the clock driver region 20 and the output amplifier region 30 respectively. The etchant does not attack silicon dioxide, and therefore the layer 14 remains intact. Preferably, a crystalline etch is performed, in which the etchant attacks the crystal planes parallel to the front surface of the die more strongly than it does other crystal planes. For example, if, as is conventional in fabrication of integrated circuits, the front surface is parallel to the 100 crystal plane, ethylene diamine pyrocatechol may be used as the etchant. A second etching operation is then carried out, using an etchant that attacks silicon dioxide but does not attack silicon or the metal employed for the interconnect strips and the bonding pads. In this second etching operation, the silicon dioxide of the layers 14 and 18 is removed where it covers the bonding pads 42. In this manner, the bonding pads are exposed. However, the oxide that covers the interconnect strips connecting the various regions of the die is masked so that the interconnect strips are not exposed. The etchant employed in the second etching operation attacks the material of the layer 60, but by controlling the time of the second etching operation removal of excessive material can be avoided. By thus dividing the die into discrete portions, corresponding respectively to the functional regions of the die, it becomes possible to employ different substrate bias voltages for the output amplifier region and for the channel region respectively. Similarly, the rapidly changing fields in the clock driver region are not coupled through the die to the channel region. Light generated by operation of the transistors in the output amplifier region and the clock driver region is not propagated so readily to the channel region, due to reflection and scattering at the walls of the trenches formed by etching. In any event, an optically opaque dielectric material 66 (FIG. 2B), such as a synthetic polymer material, is placed in the trenches to ensure that no light would be propagated to the channel region from the output amplifier region or the clock driver region. It will be appreciated that the present invention is not restricted to the particular embodiment that has been described and illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims. The invention is not limited to use with any particular material for the support member. It is necessary only that the coefficient of thermal expansion of the material of the support member match closely that of the wafer. Accordingly, in the case of a silicon wafer it is generally desirable that the material of the support member have a high silicon content.

Claims: A method of treating a charge coupled device formed in a semiconductor die (2) having a front face and a back face, the die having at least two distinct functional regions (10, 20, 30) including a channel region and an output amplifier region, that are electrically connected by interconnect portions (40, 48, 49) extending over the front face of the die, comprising the steps of: mounting the die by way of its front face on a continuous support member (60) of material having a coefficient of thermal expansion closely matching that of the die ; thinning the die from its back face; and removing material of the die by way of the back face so as to separate the functional regions of the die from each other, while the functional regions are supported relative to each other by the support member; wherein one functional region of the die is the channel region which is a photosensitive region and another functional region is the output amplifier region and contains a light emitting semiconductor junction, the step of removing material of the die (2) results in formation of a trenches between said functional regions, and the method further comprises placing optically opaque dielectric material (66) in the trenches. A method according to claim 1, wherein the step of removing material of the die (2) comprises selectively etching the die by way of its back face. A method according to claim 1 or 2, wherein the die (2) has a layer of dielectric material (14, 18) adhered to its front face and the interconnect portions (40, 48, 49) extend over the layer of dielectric material and the continuous support member (60) is adhered to the layer of dielectric material and the interconnect portions, and the step of removing material of the die comprises etching the material of the die with an etchant that does not attack the dielectric material. A method according to claim 3, comprising forming metal bonding portions (42, 46, 53) on the layer of dielectric material (14, 18) before mounting the die (2) on the support member (60), said bonding portions lying at least partially outside said functional regions (10, 20, 30), and the method also comprises removing dielectric material (14, 18) so as to expose the bonding portions. A charge coupled device which comprises: a semiconductor die (2) having front and back faces, the die having at least two distinct functional regions (10, 20, 30), including a channel region and an output amplifier region that are electrically connected by interconnect portions (40, 48, 49) that extend over the front face of the die, and a continuous support member (60) made of material having a coefficient of thermal expansion closely matching that of the die and attached to the front face of the die wherein one functional region of the die is the channel region which is photosensitive and another functional region is the output amplifier region and contains a light emitting semiconductor junction, and trenches are provided between said functional regions, said trenches being filled with an optically opaque dielectric material. An integrated circuit according to claim 5, comprising metal bonding portions (42, 46, 53), each of which is connected to at least one of the functional regions and extends at least partially outside said functional regions.

Inventors: BLOUKE MORELY M, CORRIE BRIAN L, HEIDTMANN DENIS L, BLOUKE, MORELY M., CORRIE, BRIAN L., HEIDTMANN, DENIS L.
Applicants: SCIENT IMAGING TECHNOLOGIES IN, SCIENTIFIC IMAGING TECHNOLOGIES, INC.
Application year: 1988
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L23, H01L27