Semiconductor integrated circuit having a built-in power voltage generator

Abstract: A semiconductor integrated circuit having a voltage generator circuit for generating an internal power voltage lower than an externally supplied power voltage, a control circuit for generating at least one control signal and a functional circuit operating with the internal power voltage and controlled by the control signal is disclosed and featured in that the control circuit includes a first circuit operating with the externally supplied power voltage and generating a first signal with a predetermined timing relationship with respect to an input control signal thereto and a second circuit operating with the internal voltage and generating a second signal in response to the first signal, as the control signal for the functional circuit.

Description: The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a voltage generator generating an internal power voltage lower than an externally applied power voltage. The integration scale of semiconductor integrated circuits has been increased by reducing the size of circuit elements such as transistors formed therein. As a result of such reduction in size of circuit elements, large scale integrated circuits have been realized. For example, for reducing the size of MOS field effect transistors, the channel length of MOS transistors has been particularly reduced. Specifically, in the recently announced proto-type 4M-bit DRAMs, MOS transistors having channel length of 1 micron or less were employed. However, if MOS transistors having such short channel length as 1 micron or less are driven by high power voltage such as the conventional power voltage of 5 volts, the characteristics of the short-channel MOS transistors are likely to be degraded due to hot carriers, resulting in a lowered withstanding voltage. For avoiding the above degradation, it is desirable to drive the short-channel MOS transistors with a lower power voltage than the conventional power voltage (5 volts). From a view point of interface with system outside DRAMs and simplification of power voltage source, however, it is still advantageous to employ the conventional power voltage. Under the above circumstance, it has been proposed (eg. in US-A-4.585.955) to provide in a semiconductor chip a voltage generator generating an internal power voltage lower than 5 volts used in the conventional power system for driving the reduced-size circuit elements. By the proposed, while the unification of the power voltage with peripheral system is kept, the problem due to the short-channel MOS transistors was solved. However, current driving ability is also reduced by driving the short-channel MOS transistors with the lower internal power voltage. A clock generator or a delay circuit for producing clocks which is combined in the same chip cannot supply clocks having sufficient current. As a result, switching characteristics, particularly, switching time of the short-channel MOS transistors used for signal processing become unstable. This unstability of the switching characteristics causes another serious problem in a timing signal generator circuit or a delay signal generator circuit which is composed of the reduced-size MOS transistors driven by the internal voltage. Namely, it is an essential matter in the timing signal generator that current values of currents flowing through a transistor for feeding the power voltage and through a transistor for feeding the ground voltage in a unit of inverters forming the timing signal generator and a ratio of the current values flowing through the above transistors are important parameters to determine a delay of response time of the unit of inverter. However, the reduced-size transistors driven by the internal power voltage cannot produce an accurate amount of current as designed and it is difficult to establish a predetermined ratio between the currents flowing through each of the two transistors forming the inverter. In other words, fluctuations in current values and ratio of currents flowing through a plurality of transistors are large in those transistors driven by the internal power voltage. Thus, timing signals generated from the timing signal generator driven by the internal power voltage fail to have an accurate time relationship therebetween. Therefore, it is difficult to regulate operations of a functional circuit accurately by the timing signals generated by the above timing signal generator. It is an object of the present invention to provide a semiconductor integrated circuit having a functional circuit operating reliably with an internal power voltage generated therein. It is another object of the present ivention to provide a semiconductor integrated circuit having a large integrated scale and having a clock generator or delayed signal generator improved for a reliable operation of the semiconductor integrated circuit. A semiconductor integrated circuit according to the present invention as defined in claim 1 comprises a first means for receiving an externally supplied power voltage; a voltage generator circuit coupled to said first means for generating an internal power voltage lower than said externally supplied power voltage; a functional circuit coupled to said voltage generator circuit, said functional circuit operating with said internal power voltage to perform a predetermined function, and characterised by a second means for receiving a control signal; a first circuit coupled to said first means and said second means, said first circuit operating with said externally supplied power voltage to generate a first signal after a predetermined time from an activation of said control signal; a second circuit coupled to said voltage generator circuit and said first circuit, said second circuit operating with said internal power voltage to generate a second signal in response to said first signal, said second signal having an amplitude approximately of said internal power voltage; the functional circuit being coupled also to the second circuit, and being controlled by the second signal. The first circuit operates with the externally supplied power voltage and the first signal has an amplitude approximately of the externally supplied power voltage. Since the first generating circuit operates with the externally supplied power voltage (the conventional power voltage), the current driving ability of the MOS transistors contained in that circuits becomes large to make the switching characteristics thereof stable. Thus, the control signal generating circuit generates the first signal with an accurate timing relationship with respect to the input signal. The amplitude converter circuit operates with the internal power voltage and simply converts the first signal having the amplitude of the externally supplied power voltage into the second signal having the amplitude approximately of the internal power voltage, in response to the first control signal. Thus, according to the present invention, a control signal such as a timing signal and a delay signal having the amplitude of the internal power voltage can be generated with an accurate timing relationship by the combination of the control signal generating circuit and the amplitude converter circuit. The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description and drawings which are by way of example only. In the accompanying drawings: Fig. 1 is a schematic block diagram showing an integrated circuit in the prior art; Fig. 2 is a schematic block diagram showing an integrated circuit according to one embodiment of the present invention; Fig. 3 is a schematic block diagram showing one example of a power voltage generator; Fig. 4 is one example of a functional circuit in Fig. 2; and Fig. 5 is another example of the functional circuit in Fig. 2. A semiconductor integrated circuit in the prior art will be explained with reference to Fig. 1. A voltage generator circuit 1, a control signal generator 2 and a functional circuit 3 are formed on a semiconductor chip to form an integrated circuit. The voltage generator circuit 1 receives an externally supplied voltage Vcc of 5 volts as well as a ground voltage to generate an internal power voltage V A (e.g. 3 volts) lower than the externally supplied voltage Vcc. The control signal generator 2 receives the internal power voltage V A as its power source and generates timing control signals ₁ and ₂ in response to an input control signal  c which is externally supplied. The control signal generator 2 includes a plurality of P-channel MOS transistors TP1 to TP5 and N-channel MOS transistors TN1 to TN5 which form 5 stages of CMOS inverters connected in cascade. The timing control signal ₁ is generated from the second stage of inverter (TP2, TN2) and the timing control signal ₂ is generated from the fourth stage of inverter (TP4, TN4). Therefore, when the input control signal  c is activated, the timing control signal ₁ is generated after a first delay time and the timing control signal ₂ is then generated after a second longer delay time from the activation of the input control signal  c . An output (₃) of the fifth stage of inverter (TP5, TN5) may be applied to the functional circuit or other circuits, if necessary. The functional circuit 3 operates with the internal power voltage V A under control by the timing control signal ₁ and ₂ to perform a predetermined operation on an input signal supplied at an input terminal IN. A result of the operation is outputted to an output terminal OUT. The functional circuit 3 inlcudes a large number of small-size transistors and the transistors contained in the control signal generator 2 are also small in size. This is the reason why the internal power voltage V A is applied to the control signal generator 2 and the functional circuit 3. However, in the integrated circuit of Fig. 1, the transistors (TP1 - TP5, TN1 - TN5) forming the control signal generator 2 are small in their sizes or dimensions, and particularly channel length thereof is very short (e.g. 1 micron or less) and those transistors are driven by the internal power voltage V A . Therefore, effective current driving ability of those transistors is limited and small, and those transistors are likely to have insufficient current driving ability. Thus, desirable switching characteristics of those transistors cannot be obtained as intended. This causes unstability of time relationship among the input control signal and the timing control signals ₁ and ₂, and it is difficult to generate the timing control signals ₁ and ₂ with predetermined delay times with respect to the input control signal  C . As a result, the timing control signals ₁ and ₂ are not adequately generated so that the functional circuit makes malfunctions. With reference to Fig. 2, an integrated circuit according to one embodiment of the present invention will be explained. In Fig. 2, elements or portions corresponding to those in Fig. 1 are denoted by the same or similar references. The present embodiment is obtained by employing a control signal generator circuit 2′ operating with the externally supplied power voltage Vcc and an amplitude converter circuit 4, in place of the control signal generator circuit 2 of Fig. 1. The control signal generator 2' includes a plurality of P-channel transistors TP1 to TP5 and a plurality of N-channel MOS transistors TN1 to TN5 which have a larger size of channel length than those used in the other amplitude converter circuit 4 and functional circuit 3. The transistors TP1-TP5,TN1-TN5 form CMOS inverters operating with the externally supplied power voltage Vcc (5 volts), and timing signals ₁₁ and ₁₂ are generated from the second and fourth stages of inverters, respectively. The timing signals ₁₁ and ₁₂ have an amplitude of the power voltage Vcc and a swing between the ground voltage and the power voltage Vcc. The input control signal  c also has the amplitude of Vcc to effectively drive the first stage of inverter. Those transistors contained in the control signal generator circuit 2' are required only to withstand the externally supplied power voltage Vcc. Since the transistors (TP1 - TP5, TN1 - TN 5) forming the circuit 2' are driven by the externally supplied power voltage Vcc, those transistors are fully driven to have large current driving ability. Thus, those transistors in the circuit 2' provide desirable switching characteristics and the timing signals ₁₁ and ₁₂ are generated with desirable timing relationship with respect to the input signal  c . However, the functional circuit 3 operates with the internal power voltage V A generated by the voltage generator circuit 1. Therefore, it is not desirable to apply the timing signals ₁₁ and ₁₂ directly to the functional circuit for controlling it. The amplitude converter circuit 4 is provided in this point of view. Namely, the amplitude converter circuit 4 inlcudes a first inverter composed of a P-channel MOS transistor TP6 and an N-channel MOS transistor TN6 and a second inverter composed of a P-channel MOS transistor TP7 and an N-channel MOS transistor TN7. The first and second inverters operate with the internal power voltage V A and generate timing control signals ₁′ and ₂′ for controlling the functional circuit 3, in response to the timing signals ₁₁ and ₁₂, respectively. The timing control signals ₁′ and ₂′ have the amplitude of the internal power voltage V A and swing betwen V A and the ground voltage so that they control the functional circuit 3 effectively. In this embodiment, the timing control signals ₁′ and ₂′ are the so-called low-active signals, and they assume a low, ground level in response to the activation (high level) of the input control signal  c . However, it is a simple design choice to generate the so-called high-active signals that assume the high level in response to  c , in place of ₁′ and ₂′. According to the present embodiment, the timing signals ₁₁ and ₁₂ are generated with accurate, desirable timing relationship by the circuit 2′ operating with the externally supplied power voltage Vcc and then the timing signals ₁₁ and ₁₂ are converted into the timing control signals ₁′ and ₂′ having the amplidue of the internal power voltage V A . Therefore, the integrated circuit having the functional circuit which can operate stably under control of timing control signals can be obtained according to the present invention. An example of the voltage generator circuit 1 is shown in Fig. 3. As shown in Fig. 3, the voltage generator circuit 1 comprises a bias voltage generating circuit 11 for generating a bias voltage V B (0 ≦ V B ≦ Vcc), an operational amplifier 12 having a non-inverting input (+) receiving the bias voltage V B and an inverting input (-), and an N-channel MOS transistor Q1 having a gate connected to an output of the amplifier 12 and a source connected to the inverting input of the amplifier 12. From the source of the transistor Q1, an output voltage "V B - V TH " (V TH being a threshold voltage of Q1) is generated as the internal power voltage V A . Example of the functional circuit 3 will be shown in Figs. 4 and 5. The example of Fig. 4 includes a plurality of stages of logic circuits such as inverters and two inverters IV1 and IV2 are representatively illustrated. The inverter IV1 receives an input signal  IN which may be the input signal IN or a signal derived therefrom to produce an output signal ₀₁ in response to the active (low) level of ₁′. The inverter IV2 receives a signal derived from the signal ₀₁ and produces a signal ₀₂ in response to the active (low) level of the timing control signal ₂′. The transistors TP10 - TP13, TN10, TN11 contained in the functional circuit 3 are smaller than those of the circuit 2′. The example of the functional circuit 3 shown in Fig. 5 is a memory circuit. The memory circuit mainly comprises a memory cell array 23 having word lines WL arranged in rows, digit lines DL arranged in columns, memory cells MC each consisting of a transfer MOS transistor QM and a storage capacitor CM, a row decoder 21 for selecting one of the word lines WL in accordance with row address signals AR, a sense amp block 22 having a plurality of sense amplifiers SA, and column selection circuit 24 for selecting one of digit lines for accessing thereto in accordance with column address signals AC. In this memory circuit, the timing control signal ₁′ is used to enable the row decoder while the timing control signal ₂′ is used to enable the sense amplifiers SA after the selection of the word line, in a known way. A timing control signal ₃' used to enable the column selection circuit 24 is such a signal that is generated after the generation of the timing control signal ₂'. Thus, sequential operations in the memory circuit can be performed by the timing control signals such as ₁' and ₂' accurately. The present invention has been explained above by way of the embodiment, however, the present invention should not be limited to the above embodiment. For example, bipolar transistors may be employed as transistors and a variety of circuits may be utilized as the functional circuit.

Claims: A semiconductor integrated circuit comprising: a first means for receiving an externally supplied power voltage (Vcc); a voltage generator circuit (1) coupled to said first means for generating an internal power voltage (V A ) lower than said externally supplied power voltage; a functional circuit (3) coupled to said voltage generator circuit (1), said functional circuit operating with said internal power voltage to perform a predetermined function, and characterised by a second means for receiving a control signal ( c ); a first circuit (2') coupled to said first means and said second means, said first circuit operating with said externally supplied power voltage to generate a first signal (₁₁,₁₂) after a predetermined time from an activation of said control signal; a second circuit (4) coupled to said voltage generator circuit (1) and said first circuit (2'), said second circuit operating with said internal power voltage to generate a second signal (₁',₂') in response to said first signal, said second signal having an amplitude approximately of said internal power voltage (V A ); the functional circuit (3) being coupled also to the second circuit (4), and being controlled by the second signal (₁',₂'). The integrated circuit according to Claim 1, in which said functional circuit (3) includes a memory circuit (21-24). The integrated circuit according to Claim 1, in which said functional circuit (3) includes a plurality of field effect transistors (TP₁₀₋₁₃,TN₁₀,TN₁₁) and said first circuit includes a plurality of field effect transistors (TN₁-TN₅,TP₁-TP₅). The integrated circuit according to any preceding claim, in which said voltage generator circuit includes a field effect transistor (Q₁) having a drain receiving said externally supplied power voltage, a bias voltage generator (11) generating a bias voltage (V B ), and an operational amplifier (12) having a non-inverting input receiving said bias voltage and an inverting input connected to a source of said field effect transistor, wherein said internal power voltage is generated from the source of said field effect transistor. The integrated circuit according to any preceding claim, in which said first circuit includes a plurality of first inverter circuits (TP₁,TN₁, etc) connected in cascade, said first signal being generated from an output of a predetermined one of said first inverter circuits. The integrated circuit according to Claim 5, in which said second circuit includes a second inverter (TP₆,TN₆;TP₇,TN₇) operating with said internal power voltage and being responsive to said first signal to generate said second signal. The integrated circuit as claimed in any preceding claim, wherein the first circuit (2') is a clock generator driven by said externally supplied power voltage to generate as said first signal a clock signal having an amplitude of approximately the externally supplied power voltage; the second circuit (4) being a clock converter driven by said internal power voltage to convert said clock signal to said second signal. The integrated circuit as claimed in Claim 7, wherein said clock generator is formed of MOS transistors (TP₁,TN₁, etc) having a dimension larger than a corresponding dimension of MOS transistors used in said clock converter (TP₆,TN₆, etc) and said functional circuit (3). The integrated circuit as claimed in Claim 8, wherein said dimension is a channel length of the MOS transistors. The integrated circuit as claimed in Claim 9, wherein said clock generator (2') generates said clock signal by delaying an externally applied clock signal ( c ) constituting said control signal.

Inventors: HOSHI KATSUJI, HOSHI, KATSUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G06F1
IPC codes: G11C11, H03K19, G06F1, H03K5