MULTIPLIER AND WATT-HOUR METER

Abstract: A multiplier comprises pulse width modulators (35, 37) for modulating input signals into pulse signals whose pulse widths are corresponding to the levels of the input signals and which are synchronous to each other; an oscillator (39) for outputting a pulse signal at a frequency higher than any of those of the pulse signals from the pulse width modulators; a logical gate portion which receives the pulse signals from the pulse width modulators as well as the pulse signal from the oscillator to execute predetermined logical operation on the pulse signals; and a subtracter (69) which calculates, according to the pulse widths of the pulse signals from the pulse width modulators (35, 37), the number of pulses outputted within a predetermined interval forom the oscillator (39) to provide a signal proportional to the product of levels of the input signals.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a watt-hour meter for measuring electric power with the use of a multiplier which provides a digital output signal proportional to the product of input signal levels, and particularly to a multiplier which is suitable for integration. Description of the Prior Art Fig. 1 is a view showing a conventional multiplier which is applicable for a watt-hour meter for measuring electric power and provides a digital output signal proportional to the digital of input signal levels. The multiplier shown in the figure is so constituted to provide a frequency proportional to the product of voltage values of two input signals. In Fig. 1, an input signal is given to an input terminal 1. A voltage of the input signal is modulated by a pulse width modulator 3 to provide a pulse signal. The pulse signal is given to a switch 5 as well as being inverted in an inverter circuit 7 and given to a switch 9. Namely, the switch 5 is opened and closed under the control of an input of the pulse width modulator 3, and the switch 9 is opened and closed under the control of an inverted output of the pulse width modulator 3. An input signal to an input terminal 11 passes through the switch 5 and is smoothed in a smoothing circuit 16 which comprises a resistor 13 and a capacitor 15. The same input signal to the input terminal 11 is inverted and amplified in an inverter amplifier 23 which comprises an operational amplifier 17 and resistors 19 and 21. The inverted and amplified signal passes through the switch 9 and is smoothed in the smoothing circuit 16. Namely, the input signal from the input terminal 11 and its inverted and amplified signal are selectively smoothed according to the pulse signal and its inverted signal which have been obtained by pulse-width-modulating and inverting the input signal to the input terminal 1. Thus, the input signals to the input terminals 1 and 11 are multiplied in time-shearing manner. A multiplied and smoothed result from the smoothing circuit 16 is an analog signal which is converted in a voltage-to-frequency (V-F) converter circuit 25 into a frequency. Based on this frequency, a digital signal proportional to the product of voltage values of the input signals is obtainable. In the application of this multiplier for a wall-hour meter, a digital signal proportional to the product of input voltage values is counted by a counter to display the counted result as electric energy. Since the conventional multiplier applicable for a watt-hour meter analogously processes and multiplies input signals, it requires many parts such as capacitors and resistors to be assembled so that its size is unavoidably large to hinder its integration into an IC, particularly a custom IC. To correctly measure electric energy, the capacitors of the multiplier shall be accurate. The use of the switches 5 and 9 complicates the multiplier. If the switches 5 and 9 are semiconductor switches, their internal resistors may be affected by heat to cause measurement errors. Watt-hour meters presently marketed are well digitized by using microcomputers, etc. Therefore, it is desirable to digitize the multipliers. GB-A-2,094,989 describes a power flow direction detector circuit and a pulse width modulation circuit for converting a voltage signal proportional to the load voltage. In accordance with the output of the power flow direction circuit, the polarity of the output signal of the pulse width modulation circuits is either inverted or not inverted. A multiplication circuit under the control of the output of the inversion circuit produces an output representing the product of (a) the voltage signal proportional to the load voltage and (b) a voltage signal proportional to the load current. The output of multiplication circuit indicates the power consumed according to the direction of power flow. FR-A-2,188,170 describes a circuit arrangement for measuring electrical energy by forming the product from voltage and current, comprising two modulators for forming respective pulse trains wherein the ratio of difference to sum of mark duration and space duration is proportional to the voltage and the current respectively, a coincidence circuit form determining coincidence between pulses of the two trains, a reference pulse generator, a pulse counter which counts the reference pulses produced by the reference pulse generator, in dependence on the output signal of the coincidence circuit, and a rectangular pulse generator for periodically reversing the polarity of the input signal of one of the two modulators and at the same time reversing the direction of counting of the pulse counter. An object of the present invention is to provide a multiplier which is compact and suitable for integration into an IC. Another object of the present invention is to provide a multiplier applicable for a watt-hour meter and able to execute digital multiplication on pulse signals converted from input signals. In order to accomplish the objects mentioned in the above, the present invention provides a multiplier for providing a product of a first and a second input signals, comprising: a first pulse width modulator, coupled to the first input signal, for generating a first pulse train with a pulse width equal to the sum of its half period and a time proportional to the first input, a second pulse width modulator, coupled to the second input signal, for generating a second pulse train asynchronous with the first pulse train, with a pulse width equal to the sum of a half period of the second pulse and a time proportional to the second input, an oscillating means for supplying a third pulse train with a frequency higher than the individual frequencies of the first and the second pulse trains, and a logic circuit, coupled to the first and the second pulse width modulators characterized in that the logic circuit is also connected to the oscillating means for generating pulses the same as the output pulses from the oscillating means when either an output of the first or of the second pulse width modulator is high, a frequency divider, coupled to the oscillating means, for generating a pulse train having half the frequency of the third pulse train, a first pulse counter, coupled to the logic circuit, for counting the number of the pulses from the logic circuit, a second pulse counter, coupled to the frequency divider, for counting the number of the pulses from the frequency divider, and a subtracting means, coupled to the first and the second pulse counters for providing the result of substracting the first pulse counter from the second pulse counter. According to the multiplier with the above arrangement, input signals to be multiplied are converted into pulse signals whose pulse widths are corresponding to levels of the input signals. The logical operation is carried out on the pulse signals as well as on a predetermined pulse signal to digitally process the input signals and obtain a signal proportional to the product of levels of the input signals. The multiplier of the present invention is the most suitable to apply for a digitized watt-hour meter. These and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the constitution of a multiplier applicable for a watt-hour meter, according to a prior art; Fig. 2 is a view showing the constitution of a watt-hour meter using a multiplier according to the present invention; Figs. 3a to 3i are waveform diagrams showing the operation of the multiplier of Fig. 2; Fig. 4 is a view showing the constitution of a wattmeter using the multiplier of the present invention shown in Fig. 2; and Fig. 5 is a view showing the constitution of a watt-hour meter using a multiplier according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 shows a multiplier 30 according to the present invention and a watt-hour meter 32 of single phase two wire type using the multiplier 30. The watt-hour meter 32 comprises a voltage input circuit 61 for converting an external high voltage into a circuit low voltage and supplying it to the multiplier 30; a current input circuit 63 for converting an external high current into a circuit low voltage and supplying it to the multiplier 30; the multiplier 30 for pulse-width-modulating the two input signals from the voltage input circuit 61 and current input circuit 63 and multiplying them to obtain a digital signal proportional to the product of the input signals; and an indicator 71 for indicating the digital signal from the multiplier 30. The voltage and current inputted into the voltage input circuit 61 and current input circuit 63, respectively, are multiplied in the multiplier 30 and transferred as the digital signal representing electric energy to the indicator 71 on which the electric energy is indicated. The details of the multiplier 30 of the present invention will be described. As shown in Fig. 2, the multiplier 30 comprises pulse width modulators 35 and 37 which receive input signals from the voltage input circuit 61 and current input circuit 63 via input terminals 31 and 33, respectively; an oscillator 39; a frequency divider 41; inverter gates 43 and 45; AND gates 47 and 49; an OR gate 51; counters 65 and 67; and a subtracter 69. The pulse width modulators 35 and 37 receive the input signals from the input terminals 31 and 33, respectively, to pulse-width-modulate the input signals. The pulse width modulator 35 gives an output pulse signal "a" to the inverter gate 43 and AND gate 47, while the pulse width modulator 37 gives an output pulse signal "b" to the inverter gate 45 and AND gate 49. As shown in Fig. 3a, the pulse width modulator 35 modulates an input signal into a pulse signal whose one period is 2ta and those pulse width Ta changes according to an input voltage Va. The pulse width Ta is expressed as follows: Ta = ta + τa Here, the value τ a is proportional to the input voltage Va. On the other hand, as shown in Fig. 3b, the pulse width modulator 37 modulates an input signal into a pulse signal whose one period is 2tb and whose pulse width Tb changes according to an input voltage Vb. The pulse width Tb is expressed as follows: Tb = tb + τb Here, the value τ b is proportional to the input voltage Vb. The period 2ta of the output pulse signal "a" from the pulse width modulator 35 and the period 2tb of the output pulse signal "b" from the pulse width modulator 37 have random phases such that the phases do not synchronize with each other for a predetermined interval. As shown in Fig 3c, the oscillator 39 outputs a pulse train signal "e" with regular pulses at a frequency which is sufficiently higher than any one of the frequencies of the output pulse signals from the pulse width modulators 35 and 37. The pulse train signal "e" is given to the AND gates 47 and 49 and frequency divider 41. The frequency divider 41 receives the pulse train signal "c" from the oscillator 39 and divides the frequency of the signal "c" by two to provide a pulse train signal "i" to an output terminal 53. The inverter gate 43 receives the output pulse signal "a" from the pulse width modulator 35 and inverts the same to provide an inverted output signal "c" shown in Fig. 3c to the AND gate 49. The inverter gate 45 receives the output pulse signal "b" from the pulse width modulator 37 and inverts the same to provide an inverted output signal "d" shown in Fig. 3d to the AND gate 47. The AND gate 47 receives the output pulse signal "a" from the pulse width modulator 35, the inverted output signal "d" from the inverter gate 45 and the pulse train signal "e" from the oscillator 39, and finds a logical product of them to provide a logical product output "f" to the OR gate 51. The AND gate 49 receives the output pulse signal "b" from the pulse width modulator 37, the inverted output signal "c" from the inverter gate 43 and the pulse train signal "e" from the oscillator 39, and finds a logical product of them to provide a logical product output "g" to the OR gate 51. The OR gate 51 receives the logical product output "f" from the AND gate 47 and the logical product output "g" from the AND gate 49, and finds a logical sum of them to provide a logical sum output "h" to the output terminal 55. The counters 65 and 67 count the number of pulses of the logical sum output "h" from the output terminal 55 and the number of pulses of the pulse train signal "i" from the output terminal 53, respectively. The subtracter 69 subtracts a value of the counter 65 from a value of the counter 67 to provide a digital signal (electric energy) proportional to the product of the respective input signals. Operation of the multiplier 30 with the above-mentioned arrangement will be explained with reference to Fig. 3. The input signals given to the input terminals 31 and 33 are modulated into the pulse signals "a" and "b" shown in Figs. 3a and 3b according to their input voltages Va and Vb, respectively. As shown in Fig 3e, the pulse train signal "e" has, for instance, "F" pulses within a predetermined time period which is sufficiently longer than one period of each of the output pulse signals "a" and "b". Then, the AND gate 47 provides the logical product output "f" shown in Fig. 3f. The number PA of output pulses of the logical product output "f" will be expressed as follows: The AND gate 49 provides the logical product output "g" shown in Fig. 3g. The number PB of output pulses of the logical product output "g" will be expressed as follows: The logical product outputs f and g are given to the OR gate 51 in which the logical sum of them is obtained. The logical product outputs f and g are not overlaying each other, and the logical sum output "h" of the OR gate 51 shown in Fig. 3h is given to the output terminal 55. The number PT of output pulses of the logical sum output is expressed as follows: On the other hand, the number Pi of pulses of the pulse train signal "i" given from the frequency divider 41 to the output terminal 53 is F/2. The number of pulses of the pulse signals outputted to the output terminals 53 and 55 are counted by the counters 65 and 67, respectively. The subtracter 69 subtracts the number of pulses of the logical sum output "h" from the number of pulses of the pulse train signal "i" to obtain the following number of pulses: The values τa and τb are proportional to the input voltages Va and Vb so that, by subtracting the number of pulses of the pulse signal given to the output terminal 55 from the number of pulses of the pulse signal given to the output terminal 53, a digital signal proportional to the product (Va x Vb) of the input voltages, i.e., a digital signal proportional to electric energy can be obtained. The input voltages Va and Vb may be positive or negative so that quadrant multiplications (positive x positive, positive x negative, negative x positive, and negative x negative) may be possible. Since analog input signals are pulse-modulated according to their levels and digitally processed and multiplied, the multiplier of the present invention can be integrated in an IC, particularly a custom IC. Even if the multiplier is not integrated in the IC, it can be easily assembled because only a small number of external parts such as capacitors and resistors are needed. As shown in Fig. 4, a timing circuit 73 may be connected to the counters 65 and 67 to form a wattmeter. The timing circuit 73 provides timing signals for latching and clearing, at regular intervals, values counted by the counters 65 and 67. Fig. 5 shows another embodiment of the present invention. In the figure, outputs of pulse width modulators 35 and 37 are directly inputted into a microcomputer 75. The oscillator 39 of the first embodiment for outputting a pulse train signal is not used, but software of the microcomputer 75 realizes the functions of the gates 43, 45, 47, 49 and 51, oscillator 39, frequency divider 41, counters 65 and 67, and subtracter 69 of the first embodiment. Although the multiplier 30 shown in Fig. 2 are using logical gates such as inverter gates, AND gates and OR gates, it is possible to use other kinds of gate circuits if they realize the similar logical operations. Further, it is possible to use three or more inputs instead of two which is the case used in the embodiments. In summary, according to a multiplier of the present invention, input signals are converted into pulse signals having pulse widths corresponding to the levels of the input signals. Logical operation is carried out on the pulse signals as well as on a predetermined pulse signal to obtain a signal proportional to the product of levels of the input signals. Since the multiplier can digitally process the pulse signals converted from the input signals, the multiplier can suitably be integrated in an IC. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure.

Claims: A multiplier for providing a product of a first and a second input signals, comprising: a first pulse width modulator (35), coupled to the first input signal (61), for generating a first pulse train with a pulse width (Ta) equal to the sum of its half period (ta) and a time (τa) proportional to the first input signal, a second pulse width modulator (37), coupled to the second input signal (63), for generating a second pulse train asynchronous with the first pulse train, with a pulse width (Tb) equal to the sum of a half period (tb) of the second pulse train and a time (τb) proportional to the second input signal, an oscillating means (39) for supplying a third pulse train with a frequency higher than the individual frequencies of the first and the second pulse trains, and a logic circuit (43, 45, 47, 49, 51), coupled to the first and the second pulse width modulators (35, 37) characterized by the logic circuit (43, 45, 47, 49, 51) being also connected to the oscillating means (39) for generating pulses the same as the output pulses from the oscillating means (39) when either an output of the first or of the second pulse width modulator (35, 37) is high, a frequency divider (41), coupled to the oscillating means, for generating a pulse train having half the frequency of the third pulse train, a first pulse counter (65), coupled to the logic circuit, for counting the number of the pulses from the logic circuit, a second pulse counter (67), coupled to the frequency divider, for counting the number of the pulses from the frequency divider, and a subtracting means (69), coupled to the first and the second pulse counters (65, 67) for providing the result of substracting the output signal of the first pulse counter (65) from that of the second pulse counter (67). A multiplier as claimed in claim 1, characterized in that the multiplier further comprises a timing circuit (73) for repeated clearing the first and the second pulse counters (65, 67) at a certain interval and a latch circuit for storing the resulting count of these pulse counters. A multiplier as claimed in claim 2, characterized in that the first and the second input signals are a voltage signal between two lines and a current flow signal in one of these lines, and the multiplier is used for measuring kilowatthours in electric power lines.

Inventors: MARUYAMA, RYOJI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: G01R21
IPC codes: G06F7, G01R21, G06G7