A planar type heterostructure avalanche photodiode

Abstract: A planar type heterostructure avalanche photodiode comprises first and second semiconductor layers (3, 14) having first and second forbidden energy gaps. The second forbidden energy gap is larger than the first forbidden energy gap. In the second semiconductor layer, the second forbidden energy gap is increased as a distance is increased from a hetero-interface between the first and second semiconductor layers, and a pn junction is provided. A cross sectional shape of the outer periphery of the pn junction is defined by a curvature dependent on the increase of the second forbidden energy gap.

Description: The invention relates to a planar type heterostructure avalanche photodiode, and more particularly to a planar type heterostructure avalanche photodiode which is provided with a guard-ring in a multiplication layer. These days, the development of an avalanche photodiode which is fabricated from In 0.53 Ga 0.47 As compound semiconductor has been promoted. Such an avalanche photodiode can be applied to an optical fiber transmission system in which 1 to 1.6 µm wavelength region is dominantly used to transmit an optical information through an optical fiber with a low transmission loss. Since the InGaAs semiconductor is lattice-matched to a wide energy gap InP semiconductor, heterostructure comprising with the InGaAs and InP can be obtained. In the heterostructure, the InGaAs semiconductor is for a light absorption layer, and the InP layer is for an avalanche multiplication layer into which either electrons or holes generated in the light absorption layer inject to produce the avalanche multiplication. Using such separated absorption and multiplication structure, a photo detector can be realized with an excellent receiving sensitivity. The concept as described above has been described on pages 251 to 253 of "Appl. Phys. Lett. Vol. 35, 1979" by K. Nishida et al. An avalanche photodiode fabricated in accordance with the concept will be explained in detail later. According to the avalanche photodiode, however, there is a disadvantage that it is difficult to provide a guard-ring effect by which an edge breakdown is prevented from being occurred at an outer peripheral edge of a p + -conduction region selectively formed in a multiplication layer, although the reason thereof will be also explained later. From EP-A-0 205 899, a planar heterojunction avalanche photodiode is known. It comprises a first semiconductor layer of a first conductivity type for generating carriers by absorbing light and a second semiconductor layer of the first conductivity type for avalanche-multiplying the carrier injected from said first semiconductor layer, wherein the impurity concentration decreases with the distance from said first semiconductor layer and whose bandgap is greater than that of said first semiconductor layer. In this photodiode, avalanche-multiplication takes place over InP layers having no variation of the bandgap energy. Accordingly, it is an object of the invention to provide a planar type heterostructure avalanche photodiode in which a guard-ring effect can be obtained without inviting the aforementioned edge breakdown. A method according to the present invention is defined in claim 1. A device according to the present invention is defined in claim 4. Dependent claims 2 and 3 define further embodiments. The invention will be explained in more detail in conjunction with appended drawings wherein, Fig. 1 is a conventional planar type heterostructure avalanche photodiode, Fig. 2 is a planar type heterostructure avalanche photodiode in a first embodiment according to the invention, and Fig. 3 is a planar type heterostructure avalanche photodiode in a second embodiment according to the invention. Before describing a planar type heterostructure avalanche photodiode according to the invention, a conventional avalanche photodiode which is fabricated in accordance with the aforementioned concept will be explained. Fig. 1 shows a cross-sectional view of the conventional avalanche photodiode which comprises a buffer layer 2 of n-InP, a light absorption layer 3 of n - -In 0.53 Ga 0.47 As and an n-InP layer 4 successively grown on a substrate 1 of n + -InP, a p + -conduction region 5 formed into the n-InP layer 4 to a predetermined depth to provide a multiplication layer, a guard-ring 8 formed into the n-InP layer 4 to encircle the outer peripheral edge of the p + -conduction region 5, a surface protection film 6 having a function of anti-reflection provided on the n-InP layer 4, a p-electrode 7 in contact with the p + - conduction region 5 through an aperture of the surface protection film 6, and an n-electrode 9 formed on the back surface of the substrate 1 wherein a forbidden energy gap of the n-InP layer 4 is wider than that of the light absorption layer 3. In the avalanche photodiode, a reverse bias voltage is applied across the p and n-electrodes 7 and 9 to extend a depletion layer into the light absorption layer 3 with the narrow forbidden energy gap so that light is absorbed therein thereby transferring only hole carriers generated therein to the pn junction in the n-InP layer 4 with the large forbidden energy gap to give rise to the avalanche multiplication. In other words, a photo-detector with low dark current performance can be obtained, because the dark current due to the tunneling process in the narrow energy gap InGaAs layer is suppressed and a voltage breakdown is occurred in the n-InP layer 4 with the wide forbidden energy gap. However, there is the aforementioned disadvantage for the following reason. That is to say, the purpose of providing the guard-ring 8 which encircle the outer peripheral edge of the p + -conduction region 5 is to prevents a local voltage breakdown which is liable to occur at the outer peripheral edge so that an uniform avalanche multiplication is obtained in a flat portion 5A of the p + n junction. On the contrary, it is difficult to obtain such a guard ring effect because an edge breakdown is occurred at the outer peripheral edge 8A of the guard-ring 8 when the avalanche gain is approximately less than ten. As shown in Fig. 1, the junction position of the guard-ring 8 is nearer the light absorption layer 3 than that of the p + -conduction region 5, and thus the strength of electric field is greater at the hetero-interface under the guard-ring 8 than at the hetero-interface under the p + -conduction region 5. Therefore, a voltage breakdown in the light absorption layer 3 with the narrow forbidden energy gap deteriorates the guard-ring effect. In more detail, the influence of the breakdown is strongest on the outer peripheral edge 8A of the guard-ring 8 so that a breakdown is occurred at the outer peripheral edge 8A earlier than at the flat portion 5A of the p + -conduction region 5. This is the aforementioned disadvantage. Next, a planar type heterostructure avalanche photodiode in a first embodiment according to the invention will be explained in conjunction with Fig. 2. The planar type heterostructure avalanche photodiode comprises a buffer layer 2 of n-InAlAs having a thickness of approximately 1 µm, a light absorption layer 3 of n - -In 0.53 Ga 0.47 As having a thickness of approximately 3 µm and a carrier density of 3 to 5 x 10 15 cm -3 , and a graded forbidden energy gap layer 14 of In 0.53 (Ga 1-x Al x ) 0.47 As having a thickness of 2.5 to 3.0 µm and a carrier density of 1 to 2 x 10 16 cm -3 in which a forbidden energy gap is graded from 1.0eV to 1.4eV successively grown on a substrate 1 of n + -InP doped with Sulfur. The buffer layer 2 eliminates the dislocation and defect propagation from the substrate to epitaxial layers, and the graded forbidden energy gap layer 14 is for an avalanche multiplication layer and a window layer for light having a wavelength of 1.0 to 1.6 µm. In the graded forbidden energy gap layer 14, a p + -conduction region 5 having a plane round or oval shape as viewed from above and a guard-ring 8 encircling the outer peripheral edge of the p + -conduction region 5 are selectively provided. Further, a ring shaped p-electrode 7 is provided to be in contact with the p + -conduction region 5 through an aperture of a surface protection film 6 on the graded forbidden energy gap layer 14, and an n-electrode 9 is formed over the back surface of the substrate 1. The above epitaxial layers 2 to 4 are grown at a temperature of 700°C by metalorganic vapor phase epitaxy. The elements of In, Ga and Al are obtained from organicmetals of tri-methyl-indium (TMI), tri-ethyl-gallium (TEG) and tri-methyl aluminum (TMA) respectively. The materials of As and P are made from source gases of arsine (AsH 3 ) and phosphine (PH 3 ) respectively. A mask of a resist film is formed on the wafer surface of the epitaxial layer by the normal light exposure technique, and then Be-ions are implanted into the graded forbidden energy gap layer 14 through the mask under the conditions of 3 to 5 x 10 13 cm -2 dose and an acceleration energy of 100 to 150 kV. After the ion-implantation, the mask is removed from the wafer surface which is then annealed at a temperature of 700°C for 10 to 20 minutes to provide the guard-ring 8 of p-conduction region. At this process, the greater a forbidden energy gap of a semiconductor layer is, the more extensive Be is diffused thereinto so that the guard-ring 8 is of a cross section having a curvature-relieved shape. After the formation of the guard-ring 8, a film of SiO 2 is deposited on the wafer surface by chemical vapor deposition process to provide the p + -conduction region 5. Then, the SiO 2 film is patterned by the normal light exposure process. After that, Zn for the p + -conduction region 5 is diffused to the prescribed depth through the patterned SiO 2 film into the graded forbidden energy gap layer 14. The surface protection film 6 is of silicon nitride (SiNx) which is deposited on the graded forbidden energy gap layer 14 by plasma enhanced chemical vapor deposition. The p-electrode 7 is of a multi-layered film of Ti/Pt/Au which are formed by electron bombardment evaporation. Finally the n-electrode 9 of a AuGe film is formed by resistive heating evaporation to finish the avalanche photodiode as shown in Fig. 2. Here, a planar type heterostructure avalanche photodiode according to the invention will be again explained, especially, in its principle. As shown in Fig. 2, the curvature at the peripheral edge of the guard-ring 8 is relieved to some extent. As a result, a breakdown voltage of the guard-ring 8 is heightened by itself. A forbidden energy gap of the layer 14 is increased in its value with a predetermined inclination as the distance is increased from the light absorption layer 3. This results in a cross sectional shape of a relieved curvature in the guard-ring 8 as shown in Fig. 2, as compared to the conventional avalanche photodiode as shown in Fig. 1. As explained before, in a case where p-type impurities are diffused or ion-implanted into an n-conduction region, the greater a forbidden energy gap of the n-conduction region is, the more it is difficult that semiconductor composition atoms are replaced by p-type impurities, in general, for the reason why a bond energy is high among the semiconductor composition atoms. The p-conduction region is formed by a mechanism in which the p-type impurities diffuse among the semiconductor composition atoms and a mechanism in which the semiconductor composition atoms are replaced by the p-type impurities wherein the two mechanisms are repeated alternately. The greater a forbidden energy gap of a semiconductor is, the lower a rate in which impurities are stabilized by substituting for semiconductor composition atoms is, so that the mechanism for the diffusion of the p-type impurities among the semiconductor composition atoms is more dominant than the mechanism for the substitution of the semiconductor composition atoms. That is to say, the greater a forbidden energy gap of a semiconductor is, the more extensive the p-type impurities diffuse into the semiconductor. This phenomenon is applied to the planar type heterostructure avalanche photodiode as shown in Fig. 2. In a case where the p-type impurities diffuses vertically into the layer 14 from the upper surface thereof, a diffusing velocity becomes low gradually as a distance becomes large from the upper surface thereof because the forbidden energy gap becomes low. On the other hand, in a case where the p-type impurities diffuses into the layer 14 in a parallel direction to the upper surface thereof, the diffusing velocity does not become low. Therefore, the diffusing distance of the p-type impurities is longer in the parallel direction than in the vertical direction. As a result, the guard-ring 8 of the p-conduction region having a cross section of a relieved curvature in which the diffusion of the p-type impurities is more expanded transversely is obtained as shown in Fig. 2. Next, a planar type heterostructure avalanche photodiode in a second embodiment according to the invention is shown in Fig. 3 wherein like parts are indicated by like reference numerals in Fig. 2. The difference is that the planar type heterostructure avalanche photodiode in the second embodiment comprises first to third forbidden energy gap layers 14A, 14B and 14C in place of the graded forbidden energy gap layer 14 in Fig. 2. The first forbidden energy gap layer 14A is of In 0.53 Ga 0.4 Al 0.07 As having a forbidden energy gap of 1eV, the second forbidden energy gap layer 14B is of In 0.53 Ga 0.23 Al 0.24 As having a forbidden energy gap of 1.2eV, and the third forbidden energy gap layer 14c is of In 0.53 Al 0.47 As having a forbidden energy gap of 1.4eV. All of the three layers 14A, 14B and 14C are the same thickness of 0.7 to 1.0 µm and the same carrier density of 1 to 2 x 10 16 cm -3 . As a result, a cross sectional shape of a guard-ring 8 becomes a shape of three different curvature lines which are connected to each other continuously at points crossing two dotted lines for indicating boundary surfaces of the three layers 14A, 14B and 14C, as understood from the aforementioned principle. As apparent from the first and second embodiments, the so-called guard-ring effect is remarkably improved as compared to the conventional avalanche photodiode. That is to say, a curvature of the guard-rings is higher in Fig. 1 than in Figs. 2 and 3. Consequently, an breakdown voltage difference is equal to or less than only approximately 5V between the portions 5A and 8A in Fig. 1, and the maximum avalanche gain is limited only approximately less than ten for the conventional avalanche photodiode. However, it is expected in the invention that the breakdown voltage difference is increased up to 20 to 30V, and the maximum avalanche gain is more than forty.

Claims: A process of producing a planar type heterostructure avalanche photodiode comprising the steps of: forming a first semiconductor layer (3) for a light absorption layer having a first forbidden energy gap, forming a second semiconductor layer (14) representing an avalanche multiplication layer and being arranged on a surface of said first semiconductor layer (3) and having a second forbidden energy gap larger than said first forbidden energy gap, said second forbidden energy gap increasing as the distance increases from the hetero-interface between said first and second semiconductor layers (3,14), selectively forming a pn type junction including a pn junction and a p + n junction in said second semiconductor layer (14) by ion-implanting p-type impurities into said second semiconductor layer in a ring configuration and annealing to produce a p-guard ring (8), thereby letting the p-type impurities diffuse more expandingly as said second forbidden energy gap is increased to obtain a relieved curvature of the cross sectional shape of said p-guard ring, diffusing p-type impurities into said second semiconductor layer (14) to produce a p + -conduction region (5) encircled by said p-guard ring (8), and forming first and second electrodes (7,9) for applying a predetermined voltage across said first and second semiconductor layers (3,14). A process of producing a planar type heterostructure avalanche photodiode according to claim 1, wherein the increase of said second forbidden energy gap is linear. A process of producing a planar type heterostructure avalanche photodiode according to claim 1, wherein said semiconductor layer (14) includes a plurality of semiconductor layers (14A, 14B, 14C) having different forbidden energy gaps whereby the increase of said forbidden energy gap is in a stepwise manner. A planar type heterostructure avalanche photodiode comprising a first semiconductor layer (3) for a light absorption layer having a first forbidden energy gap, a second semiconductor layer (14) for an avalanche multiplication layer being arranged on a surface of said first semiconductor layer (3) and having a second forbidden energy gap larger than first forbidden energy gap, and first and second electrodes (7,9) for applying a predetermined voltage across said first and second semiconductor layers (3,14) said second forbidden energy gap increasing as the distance increases from the heterostructure-interface between said first and second semiconductor layers (3, 14), said second semiconductor layer (14) comprising a pn type junction including a pn junction and a p + n junction with a p + -conduction region (5) encircled by a p-guard ring (8) with a relieved curvature wherein the p-guard ring (8) extends vertically from the upper surface less than transversally caused by said increasing of the second forbidden band gap said photodiode being producible with a process according to any of claims 1 to 3.

Inventors: TORIKAI TOSHITAKA, TORIKAI, TOSHITAKA, TORIKAI, TOSHITAKA C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H01L31
IPC codes: H01L31