Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors

Abstract: A semiconductor process for fabricating bipolar devices of one type and extendible to include bipolar devices of a second type in the same epi-layer. The process protects selected surfaces of the epi-layer against deleterious processes associated with the formation of future emitter/contact regions for the devices. Subsequently, such emitter/contact regions are formed beneath such protected surfaces and contribute to enhanced device performance. The process also provides improved planarization of an insulating layer on the epi-layer by chemical-mechanical polishing. The planarization in conjunction with a mask formed in the insulating layer facilitates the formation of self-aligned emitter/base regions to appropriate thicknesses for high performance devices.

Description: Background of the Invention 1. Technical Field This invention relates to semiconductor devices and more particularly, to improvements in the process for fabricating high performance semiconductor devices. 2. Background Art In the prior art, high performance semiconductor devices, as shown for example in US-A-4,431,460 entitled "Method of Producing Shallow, Narrow-Based Bipolar Transistor Structures Via Dual Implantations of Selected Polycrystalline Layers"; Serial Number 355,633, filed March 8, 1982 and assigned to the assignee of the present invention, are processed in a sequence of steps whereby the extrinsic base is formed before a poly emitter structure. This sequence has a significant disadvantage insofar as the surface physics of the device are concerned. In particular, the emitter surface is exposed to a variety of potentially contaminating or damaging process steps. Among the most damaging, is a reactive ion etching (RIE) step during which the future emitter surface is exposed to ion bombardment and deposition of films of hydrocarbons and heavy metals. These conditions require the insertion of elaborate cleaning steps such as oxidation in oxygen plasma, cleaning in hot oxidizing acids, surface conditioning by wet etching, growth of sacrificial oxide films, and oxide removal in dilute solutions of hydrofluoric acid. In addition, the need to overetch during the RIE step and subsequent sacrificial oxide growth recess the emitter surface below that of the surrounding base junction which makes control of the impurity concentration at the emitter-based junction more difficult. The process steps needed to restore a clean and undamaged surface add complexity and process time to fabricating sequences which are already long and expensive. Moreover, the restored surfaces have been found not to produce contact resistances as low as are obtained on surfaces that have never been exposed to RIE conditions. It is also known to fabricate a high performance polysilicon base and emitter structure by depositing or forming a surface protective layer of polysilicon or other material for an emitter before forming an extrinsic base whereby such layer serves to protect the subsequently formed emitter region. See, for example, a publication entitled "Self-Aligning Polysilicon Base and Emitter Transistor", by S.F. Chu, B. Hwang and W. Hwang, published in the IBM Technical Disclosure Bulletin , dated January 19, 1985, at pages 4899 through 4902. The Chu et al. process, however, does expose the surface of the crystal contiguous to the emitter area to RIE damaging. Also, the process of interconnecting the extrinsic and intrinsic base of the transistor is complicated, tolerance limited and prone to faulty or lack of interconnection between these two areas of the base region. Further, the degree of planarity required for high performance devices is not achieved in the Chu et al. process which has a photoresist or polyimide covering etched by processes which are not readily controllable. Objects of the Invention An object of the invention is a process for fabricating a high performance bipolar device that has improved performance through an enhanced emitter or contact surface which has not been subject to deleterious process steps. Another object is a process for fabricating a bipolar device to protect a surface against deleterious processes and subsequently form a selected active region under such surface after other active regions of the device have been formed. Another object is a planarization and self-aligned masking sequence for fabricating emitter/base regions to controllable thicknesses appropriate for high performance bipolar devices. Still another object is an integrated process for fabricating the NPN and PNP devices in which selected surfaces of the devices are protected against deleterious processes while forming active regions of the device. Summary of the Invention These and other objects, features and advantages of the invention are achieved by a process in which a polysilicon layer which subsequently becomes an emitter structure, either N or P-type, is deposited before an extrinsic base is formed, whereby the sensitive monocrystal emitter surface is never exposed to RIE. The process for forming an NPN transistor includes the step of depositing successive layers of undoped polysilicon and silicon nitride to appropriate thicknesses. A photoresist masking step patterns the layers to define future emitter regions. The patterned layers of silicon nitride and polysilicon protect the future emitter regions against subsequent process steps for forming an extrinsic base regions and an intrinsic base. An etching process, typically, RIE, exposes the surface of the crystal outside the protected emitter regions. A thermal oxide is grown on the exposed crystal surface through which a first boron implant is made in the crystal to serve as a link up or interconnection between a future extrinsic and intrinsic base regions. A chemical vapor-deposited layer of silicon oxide is deposited, patterned and etched to form sidewalls about the juxtaposed nitride and polysilicon layers protecting the future emitter regions. A second layer of polysilicon, either intrinsic or in situ-doped, is formed across the surface of the crystal and planarized by a chemical-mechanical polishing process using the nitride areas as polishing stops. The silicon dioxide sidewalls are exposed and serve as self-aligned masks for the subsequent formation of extrinsic/base regions. The planarized polysilicon is oxidized and, if intrinsic, an implant is made into the polysilicon which diffuses into the underlying epi-layers to form an extrinsic base region after a drive-in heat cycle. If the planarized polysilicon is doped only, a drive-in cycle is required to form the extrinsic base region. The nitride layer is etched out and a third boron implant is made into the first polysilicon layer. A drive-in cycle is performed to establish an intrinsic base region. The intrinsic base is connected to the extrinsic base through the link-up or interconnection diffusions made in the first boron implant. An arsenic or phosphorous implant is made in the first polysilicon and a drive-in cycle is employed to out-diffuse the dopant partially into the intrinsic base region as an emitter. The process is completed by forming openings in the oxide to contact the base and collector regions. A layer of metallization is deposited or otherwise formed to complete the contacts to the device. The wiring pattern is formed by either subtractive etching or by a "lift-off" process. A compatible vertical PNP (VPNP) may be formed by starting with the same P-type substrate and N epi followed by an implant of boron to produce a P-layer as the collector for the VPNP transistor. Alternatively, a heavily or moderately doped P-type epi-layer may be grown over an N epi, whereby the P-type epi-layer serves as the collector for the vertical PNP. A lightly doped N region (the intrinsic base for VPNP) is formed above the P collector region by ion implanting phosphorus or arsenic into the top P collector region. The process for forming the NPN device is initiated in which the N-type diffusion serves as the contact to the N-type base region of the VPNP and similarly, the emitter region of the VPNP is formed at the time the extrinsic base region is formed for the NPN device. In Summary, the process of the present invention facilitates the fabrication of NPN and vertical PNP devices by protecting areas or regions in the crystal for subsequently formed emitters and/or base contacts. Brief Description of the Drawings Figs. 1A through 1G show a sequence of process steps for forming a bipolar NPN transistor. Figs. 2A and 2B show a series of process steps, compatible with the process steps of Figs. 1A through 1G, to integrate a vertical PNP device with the NPN transistor. Fig. 3 shows a cross-section of the NPN and vertical PNP devices fabricated by the processes shown in Figs. 1A through 1G and Figs. 2A through 2B. Description of the Best Mode for Carrying Out the Invention In Fig. 1A, an N-type epi-layer 10 is shown. The layer 10 may be formed on a P-type substrate having an N+ region (as will be discussed in connection with Fig. 2A) to serve as a subcollector for subsequently formed devices. The process of the invention is initiated by depositing successive layers of undoped polysilicon 12 and silicon nitride 14. The layers 12 and 14 are formed to thicknesses of the order of 180 nm and 160 nm, respectively, although different thicknesses will also work with appropriate modifications in the process. The polysilicon may be deposited at a temperature in the range of 600-700 degrees centigrade at a rate of the order of 10 nm per minute. The nitride may be deposited at a temperature in the range of 600-850 °C at a rate of 2 nm per minute. A photoresist masking step is employed to form patterned photoresist regions 16 which define the area under which emitter regions will be subsequently formed in a bipolar device. The layers 12 and 14 not covered by the patterned resist 16, are removed by a conventional reactive ion etching process. The etch is timed to stop at the surface of the crystal 10. In the event of non-uniform etch rates, removal of a residual polysilicon layer, up to a thickness of 20 nm, is acceptable for purposes of the process. After stripping the resist region 16, the surface of the crystal 10 is thermally oxidized to grow a layer of dioxide 18, as shown in Fig. 1B, to a thickness of 50nm. The edge of polysilicon layer 12 is also converted to silicon dioxide during the oxidation process to form an enclosure 20, surrounding the layer 12. The oxidation takes place at a temperature in the range of 800-1000 degrees centigrade and forms at the rate of 1.6 nm per minute. A first boron implantation is performed through the layer 18. The implant energy and dose is adjusted to yield after all annealing processes, a boron concentration of the order of 10¹⁸ atoms/cm³ where the emitter and extrinsic base intersect. This interconnection or link-up doping region 22 extends beneath the oxide to serve as a connection between future extrinsic and intrinsic base regions. A sidewall 24 is formed about the juxtaposed layers 12 and 14, as shown in Fig. 1C, by chemically vapor depositing silicon dioxide to a thickness of the order of 200 nm to 300 nm. The chemical vapor process may take place at a temperature in the range of 700-900 degrees centigrade at deposition rates of 1,2 to 15 nm per minute. The silicon dioxide sidewall 24, is formed around the defined polysilicon Si₃N₄ region by reactive-ion-etching. The plasma conditions are so chosen as to attack the silicon dioxide at a significantly faster rate than the silicon in the crystal 10. This dielectric sidewall 24, provides selfaligned, precise, narrow spacing between future extrinsic base and emitter-intrinsic base regions. The etching process, however, results in the surface of the crystal adjacent to the sidewall 24 being at a lower level than the surface of the interface between layers the 12 and the crystal 10. This step like feature facilitates both the formation of thin emitter base regions and the extrinsic-intrinsic base interconnection, as will become more apparent hereinafter. In Fig. 1D, a second polysilicon layer 26 is vapor deposited to a thickness of approximately 300 to 400 nm. The layer 26 may be either intrinsic or in situ-boron doped to solid solubility. The layer 26 is planarized by chemical-mechanical polishing and the nitride regions 14 serve as polishing stops. A typical polishing process is described in US-A-4,671,851 issued June 9, 1987. In Fig. 1E the layer 26 is thermally oxidized to form a layer 28 to a thickness of 100 to 150 nm. If the layer 26 was intrinsic, then a second boron implant of about 10¹⁵ atoms/cm² is required. Depending on the desired depth and lateral diffusion for an extrinsic base 29, including the link-up or interconnecting layer, a separate drive-in diffusion may be required. If omitted, the extrinsic base 29 receives the same drive-in as the intrinsic base later in the process, but it will diffuse deeper because of the higher boron concentration at the silicon interface. In Fig. 1F, the silicon nitride region 14 is etched away by a hot, phosphoric/nitric acid process to expose the polysilicon layer 12 under which an intrinsic base region will be formed. A third boron implant is performed at a dosage of about 2x10¹⁴ atoms/cm². This is a low-energy implant such that the entire boron stays in the polysilicon layer 12. A diffusion is performed at a temperature around 900 degrees centigrade to diffuse the boron into the single crystal 10 as an intrinsic base 30 which connects to the extrinsic base 29 through the interconnect 22. An arsenic dosage of 2x10¹⁶ cm⁻³ is implanted again in the layer 12 to change the conductivity type from P-type to N+. The energy level for the dosage is selected to be low enough to avoid implanting the arsenic into the underlying crystal 10. A drive-in cycle is performed for about twenty minutes at 880 °C in nitrogen to diffuse the arsenic into the crystal to form an emitter region 32, as shown in Fig. 1G. The implantation of the emitter and base regions through the self-aligned mask formed by the sidewall 24 facilitates the doping of these regions to controllable thicknesses in appropriate ranges for high performance bipolar devices. The device fabricated by the described process has an intrinsic base 30 at a higher vertical level than the extrinsic base 29. The interconnecting or link-up region 22 facilitates the interconnection between the extrinsic and intrinsic base regions. The region 22 makes unnecessary the removal of sidewall 24 to implant a link-up or interconnection path, as has been done in the prior art. Such additional processing step exposes the crystal to deleterious etching processes and because of the lack of precise control, offers the possibility of etching beneath the surface of the crystal to lessen or open the required interconnection between the base regions. In Fig. 1G, the process may be completed by another photoresist masking step to open base, collector and to form Schottky barrier diode contacts, if so desired. Subsequently, a thin platinum film 34 is either evaporated or sputtered to form platinum silicide over the bare silicon in the device contact regions. The unreached platinum over the silicon dioxide is etched off in aqua regia. A first level aluminum wiring pattern 36 is formed, either by subtractive etching or by a lift-off process, to complete connections to the device. To form a vertical PNP device in the same crystal with the NPN device described in Figs. 1A through 1G, the following preliminary steps are required before formation of the NPN device. In Fig. 2A, the N- epi-layer 10 is grown on a P-substrate 50 with an N+ layer 52. Trench isolation regions 54, are established to isolate the NPN and vertical PNP devices. The formation of such regions is well known in the prior art. Alternatively, other isolation may be employed in the crystal. A photoresist layer 54 is formed across the surface of layer 10 and patterned to define openings 56. A boron ion implant is made in the opening 56 to serve as a P+ collector region 58 for the vertical PNP device. The photoresist layer 54 is removed and a second layer of photoresist 60, as shown in Fig. 2B, is deposited on the surface of the layer 10 and patterned to form openings 62. A phosphorous or arsenic implant is made through the openings 62 to create a lightly doped N intrinsic base region 64 above the P+ collector region 58. A typical dosage of phosphorous ions is about 4x10¹³ cm⁻² at 130 Kev. In order to avoid inversion near the surface, a second phosphorous dosage of 4x10¹³ cm⁻² at a lower energy in the range of 60-80 Kev may be required. Following the preliminary process steps, the process steps described in Figs. 1A-1G are performed to form both the NPN and PNP devices in the same crystal 10. In Fig. 1A, the resist 16 is patterned for the NPN 10 device to define a region for a future extrinsic base 29 (see Fig. 1E) and a region for a future emitter 32 intrinsic base 30 (see Fig. IF). Simultaneously, the resist 16 is patterned for the PNP device to define a future base contact 66 and emitter 68 (see Fig. 3). The extrinsic base 29 for the NPN device and the emitter 68 for the PNP device are simultaneously formed by the processes described in conjunction with Fig. 1E. The emitter 32 for the NPN device and base contact 66 for the PNP device are simultaneously formed by the processes described in conjunction with Fig. IF. In connection with the base contact, the low dose boron implant for the intrinsic base of the NPN will be completely compensated by the background phosphorous or arsenic ion implant for the base of the vertical PNP. Thus, the subsequent arsenic implant for the NPN emitter can be used as the base contact for the vertical PNP transistor. Fig. 3 shows a cross section of the NPN and vertical PNP devices made by the compatible process of the present invention. A base contact 70 and a reach through 72 are shown as the contact structures for the base region 29 and collector 10 and subcollector region 52, respectively, of the NPN device. An emitter contact 74 and collector contact 76 are shown for the PNP device. The contacts 70, 72, 74 and 76 may be made by standard metallization processes. The present invention provides an improved process for fabricating high performance, the NPN bipolar devices using only two masking steps for the entire emitter/base and an additional 2 masking steps prior to forming the other active areas of the device for an entirely integrated PNP and NPN devices. This sequence protects the surface of the crystal during deleterious etching steps which are prone to introduce contaminants and/or crystal damage. In particular, the absence of ion etching in the emitter regions has been found to reduce emitter contact resistance and emitter base leakage due to silicon surface modifications by shallow implanted impurity ions. The chemical-mechanical polishing process with the nitride regions serving as etch stops and the oxide sidewalls provide a self-alignment mechanism for forming emitter and base regions at narrow controllable spacings for high performance devices.

Claims: A process for forming a bipolar device having a selfaligned emitter region which includes a surface not subjected to deleterious processes during the formation of other active regions in the device comprising the steps of, forming an epi-layer (10) of a first conductivity type (N) suitable as a collector region on a substrate to define a structure, sequentially forming a first semiconductor layer (12) and an overlying first insulating layer (14), on the epi-layer, patterning these layers (12, 14) at the location of the future emitter region of the said device, forming and controlling a first region (22) of a second conductivity type (P) in the epi-layer having a portion adjacent to the future emitter region; thermally oxidizing the structure to have the side walls of said first semiconductor layer (12) and the exposed surface of the epi-layer (10) coated by a first thermal oxide layer (20); forming a second insulating layer (24) onto the structure; etching said thermal oxide layer (20) and said second insulating layer (24) leaving a dual insulating sidewall (20, 24) ; depositing a second semiconductor layer (26) and planarizing the structure until the first insulating layer (14) at the location of the future emitter region is exposed; thermally oxidizing the exposed top of the remaining portions of said second semiconductor layer (26) to convert it in a thermal oxide layer (28); blanket implanting dopants of the second conductivity type to form an extrinsic base region (29) below said remaining portion of said second semiconductor layer (26); removing the exposed first insulating layer (14) to expose the first semiconductor layer (12) overlying the future emitter region; implanting impurities of the second conductivity type into the exposed first semiconductor layer (12), and heating the substrate to drive the said impurities into the epi-layer to serve as an intrinsic base region (30) which is connected to the extrinsic base region (29) through a linking region (22) disposed beneath said dual insulating sidewall; implanting dopants of the first conductivity type into the first semiconductor layer and heating the structure to drive-in the said dopants to form an emitter region (32) disposed within the intrinsic base region (30); and, forming metal contact connections to the emitter, base and collector regions to terminate the device construction. The process of Claim 1 wherein a chemical-mechanical process planarizes the second insulating material while the first insulating layer serves as a polishing stop. The process of Claim 2 wherein prior to forming the contact connections a schottky barrier diode contact (34) is formed with the first semiconductor layer (12).. The process of Claim 3 wherein the steps of forming a sidewall including defining the sidewall to overly the linking region.

Inventors: GLANG REINHARD, KU SAN MEI, GLANG, REINHARD, KU, SAN MEI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H01L29
IPC codes: H01L29, H01L27, H01L21