Oversampling a/d converter with two capacitor arrays

Abstract: The oversampling A/D converter samples an input analog signal at a higher frequency than the frequency band thereof and converts it into a digital signal. It is comprised of a first and second sample and hold means for alternately sampling and holding said input analog signal and generating first and second sample signals. First and second D/A converting means (12, 13) convert first and second digital local signals into corresponding first and second analog local signals, respectively. The respective differences between said first and second sample signals on the one hand and said first and second analog local signals on the other are determined by first and second subtracting means which generate first and second difference signals. Said first and second difference signals are alternately selected by selecting means (7) and delivered to integrating means (8). An integrated signal is supplied to quantizing means (9) which generate a quantized signal. Control logic circuit means (10) generate a digital signal based on said quantized signal. Distributing means (11) distribute said digital signal alternately to said D/A converters (12, 13) as said first and second digital local signals. The present converter makes it possible to achieve about twice as fast operation as the conventional oversampling A/D converters by providing and alternately operating two each of sample and hold circuits, subtracters and D/A converters.

Description: This invention relates to an oversampling analog-to-digital (A/D or A-to-D) converter for sampling an input analog signal at an oversampling frequency into an output digital signal. An oversampling A/D converter is ordinarily manufactured by using a very large scale integration technology and is promising in digital communication. By an oversampling A/D converter, an input analog signal of an input signal frequency bandwidth is sampled into an output digital signal at an oversampling frequency which is much higher than the input signal frequency bandwidth, for example, higher than one hundred times the input signal frequency bandwidth. An example of the oversampling A/D converter is discussed in a paper contributed jointly by Akira Yukawa, Rikio Maruta, and Kenji Nakayama to Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing held in March 1985, pp. 1400 to 1403, under the title of "An Oversampling A-to-D Converter Structure for VLSI Digital CODEC's". However, the oversampling A/D converter according to Yukawa et al, because of the large integrating capacitor, the time constant attributable to the output resistance of its operational amplifier and this integrating capacitor is correspondingly great, with the result that a long static time of the integrating capacitor is required every time the polarity of the input analog signal is inverted and high speed operation is thereby prevented. This problem is solved with a balanced A/D converter in which two electric charge redistributing D/A converters are connected in parallel, described in EP-A2-0169535. Specifically, the static time of the integrating capacitor is shortened by inverting the connections between the D/A converters and input terminals when the polarity of the input analog signal changes. An oversampling A/D converter according to the EP application, however, uses a balanced operational amplifier as integrator, so that the circuit dimensions are increased and a greater consumption of power is therefore inevitable. Nor is the increase of speed any more than corresponding to the reduction of the static time. IEEE Transactions on Nuclear Science, vol.NS-30, no.1, February 1983, pages 283-288, New York, US; R.C.EDEN: "GaAs analog-to-digital converter and memory IC′s for ultra-high-speed transient recording" discloses an A/D converter with a plurality of flash converters in parallel in order to achieve faster operation. An object of this invention, therefore, is to provide an oversampling A/D converter capable of high speed operation with a minimum quantity of circuitry. This object is solved with the features of the claims. The present invention makes it possible to achieve about twice as fast operation as the conventional oversampling A/D converters by providing and alternately operating two each of sample and hold circuits, subtracters and D/A converters. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description when taken with accompanying drawings in which: FIG. 1 is a block diagram for explaining the principle of the invention; FIGS. 2A to 2G are timing charts for explaining the principle of FIG. 1; FIG. 3 is a circuit diagram illustrating a preferred embodiment of the invention; and FIG. 4 is a circuit diagram illustrating in detail a control logic circuit and a switching circuit illustrated in FIG. 3. Referring to FIG. 1, an input analog signal entered into an input terminal 1 are alternately sampled and held by first and second sample and hold circuits (S&H circuits) 3 and 4. The sampled signals are entered into one each of the input terminals of first and second adders 5 and 6 whose other input terminals are supplied with local signals from first and second D/A converters 12 and 13. As described later, since the polarity of the sampled signal is different from that of the local signal, the adders 5 and 6 produce difference signals between the sampled signals and local signals. The difference signals from these first and second adders 5 and 6 are selectively switched by a switch 7, operating in synchronism with the first and second S&H circuits 3 and 4, and entered into an integrator 8. The integrator 8 integrates the sampled signal supplied through the switch 7, and feeds the integrated signal to a quantizer 9. The quantizer 9 quantizes the integrated signal, and supplies the quantized signal to a control logic circuit 10. The control logic circuit 10, responding to the quantized signal, supplies a control signal for first and second D/A converters 12 and 13 to a switching circuit 11. The switching circuit 11 supplied this control signal alternately to the first and second D/A converters 12 and 13 in synchronism with the operation of the switch 7. The first and second D/A converters 12 and 13 generate the analog local signals on the basis of the control signal, and supply them to the other each of the input terminals of the first and second adders 5 and 6, respectively. The output of the A/D converter is taken out of an output terminal 2. Next will be explained the operation of the oversampling A/D converter illustrated in FIG. 1 with reference to timing charts shown as FIGS. 2A to 2G. As illustrated in FIGS. 2A and 2B, the S&H circuits 3 and 4 repeat sampling-holding and reseting in regular periods t s . These two operations are so controlled by an oversampling clock sequence (FIG. 2G) that always one of the S&H circuits 3 and 4 be in the sample-hold and the other in the reset mode. The control can be readily achieved by so predetermining that, for instance, the sample-hold mode prevail when the oversampling clock sequence is at its high level and the reset mode does when it is at the low level, and giving a reversed oversampling clock sequence to the other S&H circuit. The differences between sampled signals, which are the outputs of the S&H circuits 3 and 4, on the one hand and local signals. (FIGS. 2C and 2D) from the D/A converters 12 and 13 on the other hand are determined by the adders 5 and 6, respectively. The switch 7 supplies the output signals from the adders 5 and 6 alternately to the integrator 8 as a difference signal in accordance with the oversampling clock sequence. The integrator 8 integrates the difference signal inputted through the switch 7 (FIG. 2E). A resultant integrated signal 102 is quantized by the quantizer 9 to produce a quantized signal (FIG. 2F) in periods of T s . A quantized output 103, besides being supplied from the output terminal 2, is entered into the control logic circuit 10. The control logic circuit 10, based on the quantized output 103, generates a control signal for the D/A converters. The control signal is alternately supplied to the two D/A converters 12 and 13 by the switching circuit 11 in synchronism with the oversampling clock sequence. It should be noted that since the period T s (the output period of the quantizer 9) of the A/D converter is set to be half of the period t s (the interval between one sampling and the next) of each individual S&H circuit, the present device achieves twice as fast operation as a conventional oversampling A/D converter. FIG. 3 is a circuit diagram of a preferred embodiment of the present invention, a modified version of the circuit of FIG. 1 suitable for integrated circuit implementation. In FIG. 3, the first and second S&H circuits 3 and 4 and the first and second adders 5 and 6 as shown in Fig. 1 are integrated and represented by capacitors 15a to 15d and a switch 14. The equivalent of the integrator 8 in FIG. 1 comprises an operational amplifier 8a and an integrating capacitor 8b, and those of the first and second D/A converters 12 and 13 consist of a capacitor array described in EP-A-0169535 referred to above. Explanation of the operations of the integrator 8, first and second D/A converters 12 and 13, and quantizer 9 is dispensed with here as they are described in said EP application. The control logic circuit 10 and switching circuit 11 will be briefly described below, though a detailed explanation will further be made afterwards with reference to FIG. 4. The logic circuit 10 generates, based on the quantized signal, a control signal 10a for turning over switches Sa and Sb and a local signal 10b in a digital form for the D/A converters. The switching circuit 11, in response to the oversampling clock sequence supplied from outside as illustrated in FIG. 2G, feeds the control signal 10a and the local signal 10b alternately to the D/A converters 12 and 13. The signal 10b controls the switching operations of the switches (except for switches Sa and Sb) in the D/A converters 12 and 13. Switches 14, 7, 16 and 17 achieve switching between the solid line state and the broken line state according to the oversampling clock sequence. The switches Sa and Sb, which select a reference voltage (+Vr or -Vr) given to the first and second D/A converters 12 and 13, are switched by the control signal 10a from the switching circuit 11. The reference voltage is +Vr when the polarity of the input analog signal is positive, or -Vr when it is negative. As the oversampling A/D converter structured in this manner performs the same operation as the basic block illustrated in FIG. 1, description of its operation is dispensed with here. Referring now to FIG. 4, the control logic circuit 10 and the switching circuit 11 will be described a little more in detail. It will be presumed that the number of capacitors used in the D/A converters 12 and 13 is equal to five. A delay circuit 31 gives a delay of one oversampling period T s to the quantized signal which is supplied from the quantizer 9. The delay circuit 31 thereby produces a delayed digital signal, which is inverted by an inverter 32 into an inverted digital signal. When the input analog signal is higher than the local signal from the D/A converter, the integrated voltage of the integrator 8 becomes negative according to the following equation. Vo = Qm/Ci = ( Vr · L · C 31C + C′ - Vi) C′ Ci where Vo is the integrated voltage of the integrator 8; Qm, moved electric charges into the integrator 8; Vr, the reference voltage of the D/A converters 12 and 13; L, the local value (decimal number); Vi, the input analog signal voltage; Ci, capacitance of an integrating capacitor 8b; and C, minimum capacitance of capacitor in the capacitor array of the D/A converters. In this event, the inverted signal has a positive level. When the analog signal is lowered than the local signal, the inverted signal has a negative level. In the manner known in the art, a polarity counter 33 is supplied with the inverted signal to produce a count signal A and a polarity signal B. An up-down counter 34 counts up and down the count signal A. Inasmuch as the number of capacitors is equal to five, the up-down counter 34 has first through fifth stages 2⁰ to 2⁴ to supply a digital adder 35 with first through fifth binary signals collectively representative of the' up-down count. When the up-down count reaches 00000 and should be further counted down, the up-down counter 34 delivers a switching signal C (designated by the reference letter for the reference capacitance merely for convenience) to the polarity counter 33. It will be assumed that the converter input terminal 1 (FIGS. 1 and 3) is supplied with the input analog signal which is positive and increasing. Meanwhile, the polarity signal B has the binary zero value. When the inverted signal has the positive level, the count signal A has the binary one value to count up the up-down count in the up-down counter 34. When the inverted signal has the negative level, the count signal A has the binary zero value to count down the up-down count. It will then be assumed that the input analog signal is negative and has an increasing amplitude. In this event, the polarity signal B has the binary one value. When the inverted signal has the positive level, the count signal A has the binary zero value to count down the up down count. When the inverted signal has the negative level, the count signal A has the binary one value to count up the up-down count. As a result, the first through fifth binary signals are produced by the up-down counter 34 so that the up-down count follows a change in the input analog signal. Adding as a summand the binary one or zero value of the count signal A supplied from the polarity counter, the digital adder 35 produces first through fifth digital signals D1 to D5, which represent the local signal. A clock input terminal 18 is supplied with the clock sequence. It should be noted that the oversampling clock sequence is delivered through connections (not depicted merely for simplicity of illustration) to the input switch 14 (FIG. 3) and to other switches, which will be described. In the illustrated example, the switching circuit 11 has a pair of gate circuits 37 and 38. Each gate circuit consists of first through sixth AND gates supplied with the first through fifth digital signals D1 to D5, and the polarity signal B from the polarity counter 33, respectively. The oversampling clock sequence is fed to the AND gates of the gate circuit 37, and the oversampling clock sequence inverted by an inverter 19, to the AND gates of the gate circuit 38. As a result, the digital signals D1 to D5 of the up-down counter 34 are alternately supplied to the two D/A converters 12 and 13 according to the oversampling clock sequence. The switches 14, 7, 16 and 17 are similarly turned over according to the oversampling clock sequence. As hitherto described, according to the present invention, the periods of time allowed for the operations of the D/A converters, adders and integrator are approximately doubled, compared with a conventional circuit for the same purpose, making it possible to realize a high speed oversampling A/D converter, whose sampling speed is about twice as high as a conventional such converter.

Claims: An oversampling A/D converter for sampling an input analog signal at a higher frequency than the frequency band thereof and converting it into an output digital signal, comprising: first and second sample and hold means (3 and 4, respectively) for alternately sampling and holding said input analog signal in a predetermined first period (t s ) and generating first and second sampled signals; first and second D/A converting means (12 and 13, respectively) for converting first and second digital local signals into corresponding first and second analog local signals, respectively; first and second subtracting means (5 and 6, respectively) for determining the respective differences between said first and second sampled signals on the one hand and said first and second analog local signals on the other hand, and generating first and second difference signals; selecting means (7) for alternately selecting said first and second difference signals in a second period (T s ) equal to half of said predetermined first period; integrating means (8) for integrating the output signal of the selecting means (7) and generating an integrated signal; quantizing means (9) for quantizing said integrated signal and generating a quantized signal as said output digital signal; control logic circuit means (10) for generating a digital control signal based on said quantized signal; and distributing means (11) for distributing said digital signal alternately to said D/A converting means (12,13) in said second period as said first and second digital local signals. An oversampling A/D converter, as claimed in Claim 1, wherein said D/A converting means (12,13) comprise electric charge redistributing D/A converters. An oversampling A/D converter as claimed in Claim 1 or 2 wherein said integrating means (8) comprises an operational amplifier (8a) and an integrating capacitor (8b). An oversamplig A/D converter as claimed in Claim 1,2 or 3, wherein said control logic circuit means (10) comprises: delay means (31) for delaying an input signal by said second prescribed period and supplying a delayed signal; inverter means (32) for inverting said delayed signal and supplying inverted signal; means (33) for supplying a control signal based on said inverted signal; and up-down counter means (34), counting up or down according to said control signal, for supplying said digital control signal to said distributing means (11). An oversampling A/D converter as claimed in any one of claims 1 to 4, comprising: in said first and second sample and hold means, a switching circuit (14) having first and second switches, both connected to an input terminal (1), so operating alternately that one be open when the other is closed in said predetermined first period; first and second hold means being connected to said first and second switches, for holding said input analog signal and supplying said first and second sampled signals; and in said selecting means (7) connected to said first and second substracting means, third and fourth switches performing the same operations in synchronism with said first and second switches, for alternately supplying said first and second difference signals in said predetermined first period.

Inventors: KURAISHI YOSHIAKI, KURAISHI, YOSHIAKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H03M1
IPC codes: H03M1, H03M3