METHOD AND SYSTEM FOR EXCHANGING DATA BETWEEN A MASTER PROCESSOR AND A MULTIPLICITY OF SLAVE PROCESSORS

Abstract: A system comprising a communication link (13, 18, 19) between a master processor (5) and a multiplicity of slave processors (29) uses the communication cycle to transmit equidistant timing signals to the slave processors, whereby said timing signals are at least partially differing. For this purpose, the master processor operates in time slices of 2 ms. Com­ munication with the slave processors is performed in fixed format. The master proces­ sor manages the communications in certain time slices according to a matrix wherein each column represents a certain time slice. The columns in this matrix are organized such that the communications with those slave processors preceding the communica­ tion with a specific slave processor are the same as in all other columns containing a communication with said specific slave processor. In particular, the slave processors requiring short-intervallic timing signals are entered on top of the columns, whereas slave processors with longer-intervallic timing signals are entered below these. This system and the method of communication are particularly useful in a con­ figurable medical monitoring system where the slave processors need equidistant timing signals for analog-to-digital conversion.

Description: This invention relates to a method and a system for exchanging data between a master processor and a multiplicity of slave processors, in particular for a configurable medical monitoring system, wherein the master processor is connected with the slave processors via at least a data channel, communication as performed on a bidirectional basis between the master processor and each of the slave processors in fixed time slices, each slave processor is to be supplied with equidistant timing signals, e.g. for data acquisition, the required timing signals of the slave processors at least partially differing. Modern medical monitors are of the configurable type, i.e. they comprise a host system and parameter modules. The host system usually consists of an electronic box containing the host processor, the operating system, a power supply and so on; a display; a keyboard and a plug-in cabinet or rack for the insertion of parameter modules. Further components like a printer or a plotter may be added. The parameter modules contain the front end electronics required to measure a specific medical parameter such as ECG, respiration, blood pressure, temperature, blood gases and so on. If we, for example, regard the ECG (electrocardiogram), the associated parameter module contains the electronics required for lead selection, a preamplifier and, if data transmission to the host system is performed in digital format, an analog-to-digital conversion circuit. Each of the parameter modules contains the front end electronics for at least one medical parameter of interest; still it is also possible to combine frequently used parameters (such as ECG and respiration) in a single parameter module. The parameter modules comprise a connector jack for the insertion of an electrode connector, e.g. of a connector which is connected with the ECG electrodes via a cable. The parameter modules are provided for insertion into a cabinet or a rack of the host system. This provides full flexibility in choosing only those parameters for monitoring which are required for a specific patient. In other words, the system can be "adapted" to specific clinical requirements, e.g. in the operating room, the recovery room, the intensive care unit or for a special kind of disease. For the purpose of galvanic isolation, the parameter modules are usually connected with the host system via optical couplers. The parameter modules further need clock or timing signals for the purpose of data acquisition. In order to obtain meaningful results, data acquisition has to be performed in equidistant intervals. Therefore, each parameter has to be supplied with equidistant timing signals which are used as start signal for the conversion cycle of an analog-to-digital conversion. Unfortunately, the intervals between said timing signals are not identical for all parameters. For example, the ECG has to be sampled any 2 ms (milliseconds) in order to obtain a smooth and meaningful ECG wave. On the other hand, temperature must be sampled any 32 ms only. A solution to fulfill these requirements is, of course, to provide each parameter module with an internal timer which generates the timing signals necessary for the data acquisition of said module. Still this solution has the disadvantage that a lot of timers are required which increases the cost and the volume of the system. Further, communication between the parameter modules and the host system is rather difficult in this case as this communication can only be performed on an asynchronous basis. Even such an asynchronous communication may generate several problems. For example, if every parameter which has converted a sample into digital format is programmed to send an inquiry to the host system in order to transmit its data, it may occur that certain inquiries overlap in time. On the other hand, if we assume that data transmission from the parameter modules to the host system is only performed after an inquiry from the host system, the number of samples which a certain parameter has converted into digital format since the last inquiry is not necessarily constant. Therefore, the length of the communication between the host system and a certain parameter module may vary which further increases the difficulties in a "handshake"-based system. Last not least, in such a system the parameter module needs own memory space for buffering of converted samples. European patent application EP-A-210 365 describes a system of communication between several input/output modules which require two different kinds of timing signals, i.e. sound input/output modules which require high frequency sampling and other data modules - such as a temperature sensor - which require low frequency sampling. According to this document, addressing is set up in a way so that the modules requiring high frequency sampling are addressed more often than the modules requiring low frequency sampling. Still this method may only be applied if the number, kind and address of all modules are known in advance, if they incorporate only two different sampling frequencies and if the communication times are equal for all modules. Such is not possible in configurable systems such as a modern medical monitoring system. The difficulties arising from asynchronous communication can be overcome by using a synchronous data transmission format, i.e. communication in fixed time slices and with a predefined number of bytes to be transmitted. Still we then have the problems that internal timers can no longer be used. On the contrary, timing must be performed by a central clock or timing signal provided by the host system. For the transmission of this timing signal, additional wiring and at least one additional optical coupler for every parameter module has to be provided. Due to the hight costs of optical couplers and additional wiring, this solution is not feasible. Further, if we want to avoid that separate clock signals must be transmitted to the parameter modules which require timing signals of differing intervals, the master clock transmitted from the host system must be divided by the parameter modules to generate the appropriate timing signals. A solution to overcome this disadvantage is to use the end of a synchronous communication as a timing signal, i.e. a "start of conversion" signal. On the other hand, this is only possible if not more than one parameter is addressed during a certain time slice of the synchronous transmission. If more than one parameter module is addressed in each time slice and the kind of addressed parameters is not identical - which is necessarily the case in a multiparameter system with different conversion cycles, - the timing signals are not equidistant due to the varying length of the transmission times of the various parameters. It is a major object of the present invention to provide a method and a system for data transmission between a host processor and a multiplicity of slave processors in which the communication is organized most efficiently and which provides transmission of non-uniform timing signals without requiring additional hardware such as optical couplers etc.. According to the invention, this problem is solved in that any communication between the master processor and a slave processor is performed in an identical format, the master processor is able to address more than one slave processor during a certain time slice, the master processor controls a list of items associated with time slices, any item in this list defining a set of communications with certain slave processors, whereby the master processor performs communications with the slave processors according to this list, during one time slice performing the communication with the slave processors contained in one of the items, during the next time slice performing the communication with slave processors contained in the next item, and so on in a rotating order, the sets of communications in the items of said list are arranged such that the communications with those slave processors preceding the communication with a specific slave processor are the same as in all other items containing a communication with said specific slave processor. The method and the system according to the invention therefore use a synchronous data transmission format with fixed time slices. Further, the format of the communication between the master processor and each slave processor is fixed, i.e. the same number of digits are exchanged upon any communication. Such a communication may not only be used to transmit the samples (data), but also for exchange of control and status information (filter control, keys, multiplexer etc.). The master processor further communicates with more than one slave processor during a certain time slice. To manage these communications, the master processor controls a list of items associated with time slices. Any item in this list defines a set of communications with certain slave processors. For example, item No. 1 may contain communications with the ECG module, a blood pressure module and a temperature module. During the associated time slice, the master processor communicates with these slave processors in the same order as they are contained in the item. The next time slice is processed in similar manner in that the master processor communicates with the slave processors contained in the next item, and so on. When all of the items are processed, the master processor starts again with item No. 1. This is called "rotating order". The items are arranged such that the types of slave processors entered into an item before a specific slave processor are always the same in all items containing this specific slave processor. For example, if an item contains the following set of communications with slave processors (in descending order): ECG, blood pressure, pleth, then all other items also containing pleth must have the same order of communications ECG, blood pressure, pleth, regardless of any following communication (which indeed may be different). That is, an item containing ECG, blood pressure, pleth, temperature is not in conflict with another item containing EGG, blood pressure, pleth and CO (cardiac output). Further, an item containing ECG, blood pressure and SaO₂ (oxygen saturation) is also allowed, but no item containing ECG, blood pressure, SaO₂ and pleth. In the latter case, the parameters (slave processors) preceding pleth are not identical to the first example; therefore, this item is not allowed. In the discussed examples, the several slave processors are - for the purpose of explanation - associated with medical parameters. It is understood that this must not necessarily be the case as the present invention is also suited for other systems with comparable requirements. The method and the system according to the invention provide a combination of several advantages. In particular, the feature of a very compact and time-saving data transmission format is combined with the feature that necessary timing signals may be transmitted using the normal communication between the master processsor and the slave processors. Therefore, the timing signals need not be transmitted via additional lines and optical couplers. Further, there is the possibility of transmitting timing signals with different intervals to slave processors which require different timings. Still these timing signals are equidistant which is ensured by the structure of the items which are used for the communication during certain time slices by the master processor. Preferably, the slave processors use the end of the communication with the master processor as timing signal, e.g. for the start of an analog-to-digital conversion. Transmission of a timing signal with an interval longer than the duration of time slice may be easily performed by entering the communication with the associated slave processor only in selected, but not in all items. For example, if we use time slices with a duration of 2 ms (milliseconds) and want to transmit a timing signal of 4 ms to a specific slave processor, a communication with this slave processor has to be entered into every second item. The communication with a specific slave processor may be performed in several ways. For example, it may be addressed directly by addressing means. It is also possible to connect all slave processors with a common bus and to send an addressing byte to a certain slave processor to initiate communication with it. During the communication, data bytes may be exchanged as well as control information or status information. Advantageously, the list of items is organized in matrix-like structure, the columns each containing a set of communications with slave processors, whereby the master processor performs the communications with the slave processors in a time slice in the same order as contained in the associated column. This is, the items form the columns of the matrix, each column containing a set of communications, whereas the single communications form the rows of this matrix. Such a matrix increases the simplicity of the list and is easy to use by the master processor. A specific problem arises if the single slave processors are individually addressable, but the type of slave processor under a certain address is originally unknown. This may be e.g. the case in a medical monitoring system as described above with several slots in a cabinet or rack wherein the system has originally no information on the position of the parameters which were inserted into the various slots. In such a system, the parameters must first be identified. This may advantageously be performed, for example, in that the master processor transmits an identifying inquiry to all slots, the slave processors responding with an identifying code when their slot was addressed. The master processor then has to generate a list of the above mentioned kind. According to an important preferred embodiment of the invention, this is done in that slave processors requiring short-intervallic timing signals are entered on top of the columns of the list, whereas slave processors requiring longer-intervallic timing signals are entered below these, and so on. By applying this simple rule, it can be ensured that a list is generated which meets the requirement of generating equidistant timing signals. The present invention relates to the method for generating such a list as well as to a system programmed to perform this method. Hardware connection between the master processor and the slave processors may be realized in several ways. Basically, a single line connecting the processors is sufficient. If, on the other hand, one-way optical couplers are used - e.g. in a medical monitoring system -, it is advantageous to use 2 lines, a transmit line and a receive line. The transmit line may be used to transmit address bytes, too; but it is also possible to use specific addressing means like address decoders and the like. The invention also relates to a monitor, particularly a medical monitor, for a system as described above. This monitor contains a master processor programmed to perform the communication with the slave processors according to a list of items as described above, whereby the master processor performs the communication with the slave processors contained in one of the items during one time slice, then performs the communications with the slave processors contained in the next item during the next time slice, and so on. Preferably, the master processor in said monitor transmit an identifying inquiry to the slave processors upon power-on of the monitor. This feature is particularly helpful if the position of the slave processors in the system is originally unknown. The clock for the time slices may be either generated internally by the master processor, or the master processor may receive an external clock signal. The invention also relates to a module for a system, in particular a medical monitoring system, which contains a slave processor for communication with the master processor in the monitor. This slave processor is programmed to respond to an inquiry of the master processor with a communication and utilizes the end of the communication as a timing signal for tasks which requires synchronizing in time. The most important task of this type is data acquisition, for example as a "start of conversion" signal for analog-to-digital conversion. Such a module is suited to operate with and support a system as described above; in particular, it evaluates the timing signals as transmitted through the communication by the master processor in the monitor. Further, such a module may advantageously respond with an identifying code to an identifying inquiry generated by the master processor. Other features and advantages of the invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of non-limiting example, the principles of the invention. In the drawings, Fig. 1 depicts an overall diagram of a configurable medical monitoring system, Fig. 2 is a block diagram of the interconnection of a single parameter module, Figs. 3a and 3b depict timing diagrams of various communications between the master processor in the central monitor and the slave processors in the parameter modules, Fig. 4 is the internal timing diagram of a single parameter module, Fig. 5 is the timing diagram of the master processor, Fig. 6 depicts a matrix defining the communications of the master processor and Fig. 7 is another version of this matrix for the explanation of timing considerations. The overall diagram of Fig. 1 depicts a configurable medical monitoring system. A monitor 1 contains a host processor 2. This host processor coordinates the communication with all other parts of the system and executes the operating system. It is connected via an internal data bus 3 with a display processor 4 and a master processor 5. Display processor 4 controls a display unit 6 which is used to display waveforms and trends of the monitored patient as well as for data entry. Data entry may be performed via a keyboard (not shown) or by other means such as a touch screen. Monitor 1 further comprises an internal rack or cabinet with a multiplicity of slots 7a to 7h (for graphical purposes, only slots 7a and 7h are labelled in Fig. 1). These slots are provided for insertion of parameter modules, six of which being shown in Fig. 1 (8a to 8f, wherein only the first and the last module are labelled). Any parameter module contains the front end and electronics to measure a certain parameter of medical interest. Parameters of this type are, for example: ECG (electrocardiogram), invasive blood pressure, temperature, pleth, non-invasive blood pressure, blood gases like pO₂ or pCO₂, cardiac output, further blood parameters such as SaO₂ (oxygen saturation) or the pH-value of the blood, the concentration of inspired or expired gases (O₂, CO₂). All parameter modules comprise front end connectors for the insertion of the connector of an electrode cable. For example, parameter module 8a could be an ECG module, and cable 9a could lead to a multiplicity of ECG electrodes. The details of the electrodes or transducers, their cables and the connection of these cables to the parameter modules are not shown in Fig. 1. When inserted into one of the slots, the parameter module is connected with internal data bus 10 and thus under control of master processor 5. This master processor controls the communication with all parameter modules. The front end electronics contained in the parameter modules comprises preamplification, preprocessing (e.g. filtering) and analog-to-digital conversion of the received signals. Further, it comprises galvanic isolation between the host system and the electrodes, e.g. by optical couplers. This ensures that the parameter module is not connected with the ground potential of the host system, i.e. is "floating". Slots 7a and 7h are identical, even in their connectors to the parameter modules, so that a parameter module may be inserted in any free slot. The medical monitoring system further comprises two racks 11 and 12. These racks are separated from the monitor and may e.g. be placed near the patient's bed. These racks are connected - via a bus 13 - with master processor 5 and are also controlled by this processor. They comprise slots 14a to 14h and 15a to 15h for the insertion of parameter modules, these slots being identical to slots 7a to 7h. Therefore, the parameter modules may be inserted either in slots 7a to 7h of the monitor as well as in one of the slots of the racks, depending on the application. For example, if the patient has to be monitored in various rooms such as the operating room and the recovery room, it can be desirable to leave the electrodes and transducers in place during transportation. In this case, a rack such as one of racks 11 or 12 may be attached to the patient's bed, this rack being connected to a monitor in the operating room. When the patient is to be wheeled in the recovery room, the rack is removed from the monitor there; after transportation into the recovery room, the rack is again connected to a second local monitor in this recovery room. The whole system is therefore adaptable to various needs. Of course, it is also possible to operate the monitor without additional racks or to cascade more than the two racks shown in Fig. 1. It makes therefore no difference whether a parameter module is inserted into one of the "internal" slots 7a to 7h or into one of the slots 14a to 14h or 15a to 15h of racks 11 and 12. In the example shown in Fig. 1, parameter modules 16a to 16c, 17a and 17b have been inserted into the slots of the racks. Fig. 2 depicts a cable 18 for the connection of monitor 1 with a rack. Further racks may be connected via cable 19. The circuit shown in Fig. 2 depicts the details of the addressing and communication means provided for data exchange between master processor 5 and a parameter module. The hardware elements shown there are integrated in a rack. It is understood that this scheme does not only apply to external racks, but also to the internal slots 7a to 7h (although no cables are required for connection there). Two address lines 20 and 21 are provided for addressing a specific rack. Therefore, a maximum of four racks may be addressed. The signals on address lines 20 and 21 are fed to an AND-gate 22 which generates a logical "1" at its output (23) if the rack shown in Fig. 2 is addressed. Output 23 is fed to the "enable" input of a decoder 24. This decoder further receives the signals on three address lines 25, 26 and 27 which are used to address a single slot - i.e. a single parameter module - within the rack. Decoder 24 generates a "select" signal at output 28 whenever the rack shown in Fig. 2 and a parameter module 29 in this rack are addressed. The other outputs of decoder 24 are used to address other slots/parameter modules (not shown) in the rack. The "select" signal at output 28 of decoder 24 enables the communication between the master processor and parameter module 29. For this communication, a transmit line 30 and a receive line 31 are provided. These signals are buffered (buffers 32 and 33). Communication may be performed any time parameter module 29 is addressed. Fig. 2 depicts only the principles of addressing and communication. That is, not all hardware elements are contained and described here. For a more detailed description of these circuits, references made to European patent (European application No. 88 107 187.2). Communication between the master processor and the parameter modules (which contain the slave processors) is performed in fixed time slices. For this purpose, the master processor receives an internal clock signal in intervals of 2 ms which cause an interrupt. Within such a time slice, the master processor communicates with several parameter modules. An example of such a communication is depicted in Fig. 3a. Immediately after the interrupt occurred, the master processor (upper diagram) addresses a certain slave processor in a parameter module (not shown in Fig. 3a). It then puts a control word (ref. No. 34) on transmit line 30 (Fig. 2). The slave processor responds (ref. No. 35) with a data word on receive line 31 (Fig. 2). This data word is the digital representation of a sample of a medical parameter. Immediately after appliance of data word 35 on receive line 31, the slave processor starts its next analog-to-digital conversion cycle and puts the digitized sample in a buffer for read-out during the next communication. Meanwhile, the master processor address the next parameter module as indicated by broken line 36. The slave processor therefore uses the end of a communication as timing signal for analog-to-digital conversion. If the event "end of communication" occurs in equidistant timing intervals, sampling is also performed in equidistant intervals. Therefore, no separate transmission of a timing signal is necessary. The problem of triggering a multiplicity of slave processors with equidistant timing signals within one time slice will be discussed below. Fig. 3b depicts a further example of a communication between the master processor and the slave processor. Immediately after the interrupt (t = 0), the master processor puts the control word on transmit line 30 (ref. No. 37). At the same time, a parameter module is addressed. In the case shown in Fig. 3b, the slave processor in the parameter module responds with the transmission of three data words 38, 39 and 40 on receive line 31. This is an example for a transmission of more than one word. For example, data word 38 may represent a digitized sample, whereas data word 39 contains coded status information of the parameter, and data word 40 contains further status information. As communication is performed on a bidirectional basis via two separate transmission lines (30 and 31), the master processor may transmit additional control information during receipt of data words 38 to 40. In the shown example, two additional control words transmitted by the master processor are indicated by dashed lines 41 and 42. Addressing of the next parameter module is indicated by dashed line 43 in Fig. 3b. The overall timing diagram of a parameter module is depicted in Fig. 4. At t = t₀, the parameter is addressed, and the master processor puts the control word on transmit line 30 (ref. No. 44). As a response thereto, the parameter module puts a data block 45 on the receive line, this data block consisting of one or a few data words containing digitized samples and control information. These words are read out from a buffer, the contents of this buffer having been prepared for transmission prior to the addressing of the parameter module. As already mentioned, the parameter module uses the end of a communication as a timing signal (t = t₁). Upon this event, analog-to-digital conversion is started. In the shown example, the parameter modules comprises four data acquisition channels. Block 46 represents the A/D-conversion of channel 1, block 47 the A/D-conversion of channel 2, block 48 the A/D-conversion of channel 3, and block 49 the A/D-conversion of channel 4. When the A/D-conversion is finished, the slave processor in the parameter module prepares the transmission buffer for the next communication (ref. No. 50), i.e. the digitized samples and status information is written into the transmission buffer. The slave processor then performs other tasks (ref. No. 51), e.g. interpretation of the control information received from the master processor, error handling and so on. In contrast to A/D-conversions 46 to 49, these tasks need different time intervals depending on the control information to be processed. This is indicated by dashed line 52. When these tasks are performed (t = t₂), the slave processor waits for the next communication (t₂<t<t₃). At t = t₃, the master processor puts the next control word (ref. No. 53) on transmit line 30, and the next cycle starts. Therefore, 54 indicates the next communication and 55 and A/D-conversion of channel 1 starting at t = t₄. A time slice is defined by the interval between t = t₀ and t = t₃. This time slice corresponds to the interrupt cycle of the master processor. In the shown example, this is an interval of 2 ms. As the time interval between t = t₀ and t = t₁, i.e. the time interval for transmitting the control word and performing the communication, is always the same (which implies that t₁ = t₀ = t₄ - t₃), the A/D conversions are also started in equidistant time intervals of 2 ms. Fig. 5 depicts the timing diagram of the master processor. In this diagram, the time slices are defined by the interrupts at t = t₀, t = t₁ and t = t₂. During the first time slice (t₀<t<t₁), communication with three parameter modules is performed. ref. No. 56 indicates the transmission of the control word to a first parameter module, and ref. No. 57 the communication with this module. In similar manner, ref. Nos 58 to 61 indicate the transmission of control words (58, 60) and the communication (59, 61) with two further parameter modules. During the next time slice (t₁<t<t₂), control word transmission (62, 64) and communication (63, 65) is performed with only two parameter modules. Further communications follow after t = t₂. The reason that the communication with the parameter modules may vary from time slice to time slice is simply that not all parameters need to perform an A/D-conversion every 2 ms. For example, the invasive blood pressure must be sampled any 4 ms and temperature any 32 ms, whereas the ECG has a sampling rate of 2 ms. Therefore, communication with the ECG module is performed in every time slice., whereas communication with the invasive blood pressure module is only performed in every second time slice and communication with the temperature module every 16 th time slice. For example, in the timing diagram shown in Fig. 5 ref. Nos. 56, 57, 62 and 63 may refer to a communication with the ECG module, ref. Nos. 58 and 59 to a communication with the invasive blood pressure module, ref. Nos. 60 and 61 to a communication with a temperature module and ref. Nos. 64 and 65 to a communication with a pleth module. As all parameter modules need equidistant time intervals between their various timing signals, it must be ensured that these timing signals are generated appropriately. This will be explained by means of Fig. 6. Fig. 6 depicts a matrix which is used by the master processor to manage the communication with the slave processors in certain time slices. This matrix comprises sixteen columns numbered from 0 to 15, each column representing the communications during a certain time slice. Any column contains several parameter modules which are subject to addressing and to communication during the associated time slice. Therefore, every time slice represents an interval of 2 ms. As indicated in the uppermost line, the whole matrix therefore represents 16 x 2 ms = 32 ms. Upon power-on of the monitor, the position of the various parameter modules is unknown, i.e. the master processor does not know where a specific parameter in the slots of the internal or external racks is positioned and which slots are empty. Therefore, the master processor starts an "identifying cycle" by sending an identifying inquiry to all addresses in the system. The parameter modules are programmed to respond with an identifying code. After receipt of this identifying code, the master processor may use this code to identify a specific parameter module by means of an internal reference table which contains all necessary information about this module, in particular about the intervals between timing signals required by this parameter. Alternatively, it is also possible to transfer the required information about a certain parameter to the master processor during the identifying cycle. This omits the need for a specific reference table in the master system. After receipt of all necessary information about the connected parameter modules, the master processor starts to generate the matrix as depicted in Fig. 6. The parameter with the shortest sampling time, i.e. with the shortest interval between two subsequent timing signals, is entered on top of the list. In the shown example, this is the ECG parameter with a sampling time of 2 ms. As any column in Fig. 6 depicts a time frame of 2 ms, the ECG is entered into every column. The next parameter to be entered into the matrix is the invasive blood pressure (label "PR") with a sampling time of 4 ms. It is entered in column 0 below the ECG. As only a 4 ms-timing is required, "PR" is not entered into column 1. "PR" is then further entered into every second column, i.e. columns 2, 4, 6, 8, 10, 12 and 14. There are three further parameters with a sampling rate of 8 ms. These are pleth ("PL"), oxygen saturation ("SaO₂") and non-invasive blood pressure ("BP"). These parameters have to be entered in every forth column starting with any desired column. In the shown example, "PL" starts in column 0, "SaO₂" in column 1 and "BP" in column 3. Still other arrangements are possible as long as it is ensured that the total time for communication within a certain column/time slice does not exceed two ms. The master processor can control this as the reference table or the identifying data transmitted during the identifying cycle contains information about the duration of a communication with a certain parameter. For example, a communicaton including a transmission of 4 bytes needs 125 µs. The master processor performs this control calculation ("calculation of data link usage") when generating the matrix. The next parameter to be entered is the "cardiac output" parameter ("CO") with a sampling time of 16 ms. This parameter is entered into every eighth column - in the example shown in Fig. 6, in column 0 and 8. The system further comprises five temperature modules T1 to T5. As these parameters need only a sampling time 32 ms, they are entered into the matrix only once, for example in column 0 to 4. For the generation of the matrix, only two points of view are important: 1. Parameters with a longer-intervallic timing signal (sampling time) must be entered below parameters which require shorter-intervallic timing signals, and 2. the communication time in one slice must not exceed 2 ms. Free times in the matrix may be used to perform further functions, e.g. analog output ("AO"). This communication is used to transmit data to a module or built-in circuit which generates analog signals. Further free times in the matrix may be used to address free slots. Thus, the system is able to detect a further parameter module which was inserted during system operation (if this happens, the matrix must eventually be re-generated). It is also possible to generate sampling times of less than 2 ms although the 2 ms-times slices cannot be shortened. In this case, the parameter module must contain an internal timer triggered by the 2 ms timing signal and internally generating intervals which are shorter in time, e.g. 500 µs. Data transmission is still performed in the 2 ms cycle; therefore, a device operating with a sample rate of 500 µs has to transmit 4 digitized samples during any communication. When the matrix is generated, normal operation is started. In this mode, the master processor performs communication during the first 2 ms-time slice according to column 0 of the matrix, i.e. it addresses the ECG module, the invasive blood pressure module, the pleth module, the cardiac output module and the "temperature 1" module in this order and communicates with them. At the end of this time slice, an analog output signal may be generated. For the purpose of correct communication, the matrix has at least one entry containing the address of the parameter modules and the number type of bytes to be transmitted and received. In the second time slice, the master processor performs the communication according to column 1 of the matrix, during the third time slice communication is performed according to column 2, and so on. After the 16 th time slice (column 15) the whole cycle is started again with column 0, i.e. the matrix is processed in rotating order. It will now be shown by means of Fig. 7 that the structure of the matrix ensures that all parameter modules receive appropriate timing signals. This will be shown by means of three parameters with different sampling times. The first is the ECG parameter requiring a sampling time of 2 ms. As an example of the internal timing of this parameter, the communication in column 12 of the matrix (ref. No. 66) will be regarded. The ECG parameter uses the end of the communication as a start signal for the analog-to-digital coversion. This is indicated by ref. No. 67. It is evident that the time interval until the next A/D conversion occurs (ref. No. 68) is exactly 2 ms (this time interval of 2 ms is indicated by hatched blocks 69a and 69b). In the next example, the invasive blood pressure module with a sampling time of 4 ms will be regarded. A/D-conversion (column 0) occurs when the communication with the ECG parameter (ref. No. 70) and the invasive blood parameter (ref. No. 71) is completed. Start of the A/D conversion is labeled as 72 in this case. In this example, hatched block 73 indicates the time interval until the next A/D conversion occurs (ref. No. 74). As the parameter preceding the invasive blood pressure in columns 0 and 2 (ECG) uses a fixed format for the communication, i.e. a communication requires always the same time, and as this also applies to the communication of the invasive blood pressure parameter itself, A/D conversion (sampling) is also performed in equidistant timing intervals of 4 ms so that the sampling theorem is fulfilled. It is evident that this can only be achieved because the parameters preceding the invasive blood pressure are the same in all columns, and because they use a fixed format for communication. If, for example, the parameter preceding the invasive blood pressure would be ECG in one column and SaO₂ in another one, equidistant timing intervals could not be guaranteed as SaO₂ needs more time for communication with the master processor than the ECG. It can also be readily seen that a matrix fulfilling these requirements can be obtained by entering the parameters with the shortest sampling times on top of the columns, whereas parameters with longer-intervallic timing signals (sampling times) are entered below these. When entering parameters with equal longer-intervallic timing signals into the columns of the matrix, they may be entered either in different columns or, alternatively, in the same columns one after the other; in the latter case, attention has to be given to the total communication times in a time slice, i.e. the master processor has to calculate the total length of communication within a time slice and to perform control that these comunications do not exceed the total time of 2 ms. When generating such a matrix, first the parameters with a sampling time of 2 ms (e.g. ECG) have to be entered, then the parameters with a sampling time of 4 ms (e.g. invasive blood pressure), then the parameters with a sampling time of 8 ms (e.g. SaO₂), then the parameters with a sampling time of 16 ms (e.g. CO) and, finally, the parameters with a sampling time of 32 ms (e.g. temperature). Depending on the sampling times, they are entered into every column (sampling time of 2 ms), in every second column (sampling time of 4 ms), every forth column (sampling time of 8 ms), every eighth column (sampling time of 16 ms) or only in one column in the whole matrix (sampling time of 32 ms). As a last example, the SaO₂ parameter with a sampling time of 8 ms will be regarded. A/D-conversion starts (in column 5) when communication with the ECG parameter (ref. No. 75) and the SaO₂ parameter (ref. No. 76) has been performed. Start of the A/D-conversion is indicated by ref. No. 77. Hatched block 78 indicates the time interval until the next A/D conversion occurs, see ref. No. 79. It can be readily seen that equidistant timing (of 8 ms) is also ensured in this case. It is understood that the matrix in Fig. 7 is the same as in Fig. 6; merely for the purpose of explanation, several parameters have not been entered with their labels in the matrix of Fig. 7.

Claims: Method for exchanging data between a master processor (5) and a multiplicity of slave processors, in particular for a configurable medical monitoring system, wherein the master processor (5) is connected with the slave processors via at least a data channel (10,13), communication is performed on a bidirectional basis between the master processor (5) and each of the slave processors in fixed time slices, each slave processor is to be supplied with equidistant timing signals, e.g. for data acquisition, the required timing signals of the slave processors at least partially differing, characterized in that any communication between the master processor (5) and a slave processor is performed in an identical format, the master processor (5) is able to address more than one slave processor during a certain time slice, the master processor (5) controls a list of items associated with time slices, any item in this list defining a set of communications with certain slave processors, whereby the master processor (5) performs communication with the slave processors according to this list, during one time slice performing the communication with the slave processors contained in one of the items, during the next time slice performing the communication with slave processors contained in the next item, and so on in rotating order, the sets of communications in the items of said list are arranged such that the communications with those slave processors preceding the communication with a specific slave processor are the same as in all other items containing a communication with said specific slave processor. Method according to claim 1, characterized in that said list is of matrix-like structure, the columns each containing a set of communications with various slave processors, whereby the master processor (5) performs the communications with the slave processors in a time slice in the same order as contained in the associated column. Method for exchanging data between a master processor (5) and a multiplicity of slave processors according to claim 1 or 2, characterized in that said list is generated in that the slave processors requiring short-intervallic timing signals are entered on top of the columns of said list, whereas slave processors requiring longer-intervallic timing signals are entered below these, and so on. System for exchanging data between a master processor (5) and a multiplicity of slave processors, in particular for a configurable medical monitoring system, wherein the master processor (5) is connected with the slave processors via at least a data channel (10,13), communication is performed on a bidirectional basis between the master processor (5) and each of the slave processors in fixed time slices, each slave processor is to be supplied with equidistant timing signals, e.g. for data acquisition, the required timing signals of the slave processors at least partially differing, characterized in that any communication between the master processor (5) and a slave processor is performed in an identical format, the master processor (5) is able to address more than one slave processor during a certain time slice, the master processor (5) controls a list of items associated with time slices, any item in this list defining a set of communications with certain slave processors, whereby the master processor (5) is programmed to perform communication with the slave processors according to this list, during one time slice performing the communication with the slave processors contained in one of the items, during the next time slice performing the communication with slave processors contained in the next item, and so on in rotating order, the sets of communications in the items of said list are arranged such that the communications with those slave processors preceding the communication with a specific slave processor are the same as in all other items containing a communication with said specific slave processor. System according to claim 4, characterized in that said list is of matrix-like structure, the columns each containing a set of communications with various slave processors, whereby the master processor (5) performs the communications with the slave processors in a time slice in the same order as contained in the associated column. System according to claim 5 where the single slave processors are individually adressable, but the type of slave processor under a certain address is originally unknown, characterized in that the master processor is programmed to generate said list such that the slave processors requiring short-intervallic timing signals are entered on top of the columns of said list, whereas slave processors requiring longer-intervallic timing signals are entered below these, and so on. System according to claim 6, characterized in that the slave processors are programmed to respond with an identifying code to an identifying inquiry generated by the master processor (5). System according to at least one of claims 4 or 7, characterized in that it comprises adressing means (22,24) for addressing of any single slave processor by the master processor (5). System according to at least one of claims 4 to 8, characterized in that the master processor (5) is connected with each of the slave processors via at least a transmit line (30) and a receive line (31). System according to at least one of claims 4 to 9 for medical monitoring, characterized in that said master processor (5) is a host processor located in a mainframe and said slave processors are front end processors contained in exchangeable front end modules (8a-8f;16a-16c;17a,17b) for measuring at least a medical parameter each. Monitor, in particular medical monitor, for a system according to at least one of claims 4-10, characterized in that it contains a master processor (5) programmed to perform the communication with the slave processors according to a list of items associated with time slices, any item in this list defining a set of communications with certain slave processors, whereby the master processor (5) performs the communication with the slave processors contained in one of the items during one time slice, then performs the communication with the slave processors contained in the next item during the next time slice, and so on. Monitor according to claim 11, characterized in that the master processor (5) is programmed to transmit an identifying inquiry to the slave processors upon power-on of the monitor. Monitor according to claim 11 or 12, characterized in that the master processor (5) receives or generates a clock signal for the generation of said time slices. Module for a system, in particular a medical monitoring system, according to at least one of claims 4-10, characterized in that it contains a slave processor for communication with a master processor (5), said slave processor being programmed to respond to an inquiry of the master processor with a communication and to utilize the end of the communication as a timing signal for tasks which require synchronizing in time, in particular for data acquisition, e.g. as "start of conversion" signal for analog-to-digital conversion of an analog value. Module according to claim 14, characterized in that said slave processor is programmed to respond with an identifying code to an identifying inquiry generated by the master processor (5).

Inventors: KAISER, WINFRIED
Applicants: HEWLETT-PACKARD GMBH
Application year: 1988
Main classification: H04Q9
IPC codes: G06F15, H04Q9, A61B5