Data transfer circuit

Abstract: A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits (11b, 11d) for latching data in response to first and second latch control signals, respectively, a first data transfer gate (11a) connected between the first circuit and the first latch circuit (11b) and responsive to a first gate control signal to selectively make connection or disconnection there­ between, a second transfer gate connected (11c) between the first and second data latch circuits (11b, 11d) and responsive to a second gate control signal to selec­ tively make connection or disconnection therebetween, and a third data transfer gate (11c) connected between the second data latch circuit (11d) and the second cir­ cuit and responsive to a third gate control signal to selectively make connection or disconnection there­ between.

Description: The present invention relates to a data transfer circuit for use in a semiconductor device. As shown Fig. 1, a data transfer section conventionally used in a dual-port memory is arranged between a random-accessed RAM section and, for example, a serial port section. The data transfer section is comprised of a data holding section 101 and two data transfer gate sections 102 and 103. In a read transfer cycle data bits read from the RAM section in bit parallel are first transferred to data holding section 101 via gate section 102. Data holding section 101 is accessed in bit serial so that the data bits are serially output to the serial port section via gate section 103. In a write transfer cycle serial data bits from the serial port section are written into data holding section 101 via gate section 103. Thereafter, data holding section 101 transfers the data bits in parallel to the RAM section via gate section 102. With the circuit arrangement of Fig. 1, however, when data bits on bit-line pairs 104a through 104b are transferred to data holding section 101 via data transfer gate section 102, if a row address strobe signal RAS goes from a "L" level to a "H" level, the data bits on the bit-line pairs will generally disappear. Thus, the timing for data transfer must be set before the signal RAS goes from "L" level to "H" level. For this reason the flexibility of determination of the data transfer timing becomes small, and the data transfer circuit is thus very hard to use. When the bit lines are made of a material of high resistivity, it takes long to transfer data on the bit lines to data holding section 101 in the read transfer cycle. During this period of time data cannot be transferred from data holding section 101 to the serial port section. It also takes long to transfer data held in data holding section 101 onto the bit lines in a write transfer cycle. Therefore, this kind of data transfer section cannot continuously transfer data from data transfer section to the serial port section and from the serial port section to data transfer section, via gate section 103. Prior art document EP-A-171 518 discloses a memory comprising an additional buffer for enabling specific data transfers, wherein this buffer includes a first transfer gate, a first latch, a second gate, a second latch and a third gate. In this memory , the second transfer gate shifts data one way from a previous position to the next position, and data latches are directly connected with each other without using a transfer gate, so that the first and second latches cannot be operated independently from each other. Further prior art document IBM TDB, Vol. 29, No. 5, October 1986, pages 1985 - 1990, discloses a synchronous- to asynchronous buffer which uses 2-ported functional display RAM chips. The RAM consists especially of a dynamic type memory chip with a primary I/O port, and a secondary port and a row buffer, which once loaded from a main array is completely independent and asynchronous from the primary port. Finally, prior art document EP-A-199 134 describes a memory system which includes latch circuits interposed between a row decoder and a row driver, between the row driver and a memory array, between the memory array and column sense amplifiers, and between the column sense amplifiers and a column multiplexer. The same number of latch circuits are interposed in serial fashion between an incoming row and column address bus and the column multiplexer. As a result of the use of these latch circuits in the memory system pipelining techniques are utilized for an improvement of the performance system. It is an object of the present invention to provide a data transfer circuit which enables transferring of data continuously without the limitation on the data transfer timing. To solve this object the present invention provides a data transfer circuit as specified in claim 1. To summarize up, a data transfer circuit is arranged between first and second circuits to control data transfers therebetween. The data transfer circuit comprises first and second data latch circuits for latching data in response to input first and second latch control signals, respectively, a first data transfer gate arranged between the first circuit and the first data latch circuit and responsive to an input first gate control signal to make connection or disconnection therebetween, a second transfer gate arranged between the first and second data latch circuits and responsive to an input second gate control signal to make connection or disconnection therebetween, and a third data transfer gate arranged between the second data latch circuit and the second circuit and responsive to an input third gate control signal to make connection or disconnection therebetween. According to the data transfer circuit of the present invention as described above, if data is transferred from the first circuit to the first data latch circuit during the data transfer from the second data latch circuit to the second circuit, the data from the first circuit can be transferred at any timing from the second data latch circuit to the second circuit even after the data in the first circuit disappears. More specifically, the data has been transferred from the first cirucuit to the first data latch circuit, and therefore, the data transfer timing when the second data transfer gate must be opened to transfer the data from the first data latch circuit to the second data latch circuit can be set as desired, after the data in the first circuit disappears. Previous data held in the second data latch circuit can be transferred to the second circuit until the data is transferred from the first data latch circuit to the second data latch circuit. Therefore, the timing for switching from the previous data to the data transferred from the first circuit can be set arbitrarily. Also, if the second data transfer gate is closed, the data transfer from the second data latch circuit to the second circuit can be performed continuously even while the data is transferred from the first circuit to the first data latch circuit. As a result, the data transfer timing from the first cirucuit to the second circuit can be set arbitrarily. In the write transfer cycle, data held by the second data latch circuit can be transferred from the first data latch circuit to the first circuit even while new data is written from the second circuit into the second data latch circuit, if the data held in the second data latch circuit has been transferred to the first data latch circuit. As mentioned above, this data transfer circuit can arbitrarily set the timing of the data transfer and can continuously input or output the data. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a prior-art data transfer section including a prior-art data transfer circuit; Fig. 2A is a diagram showing the configuration of a data transfer circuit according to a first embodiment of the present invention; Fig. 2B is a block diagram of the data holding circuit of the first embodiment; Fig. 3A is a block diagram of a first embodiment of a data transfer section in which the data transfer circuit of Fig. 2A is included and which is applied to a semiconductor memory having a RAM section and a serial port section; Fig. 3B is a block diagram of a control section used with the first embodiment of the data transfer section; Fig. 3C is a block diagram of the semiconductor memory to which the data transfer section is applied; Figs. 4A through 4P are timing charts showing operations of the first embodiment of the data transfer section during a read transfer cycle · serial read cycle to transfer data from the RAM section connected to bit line pair 211a and 211b to the serial port section connected to data line pair 2x and 2y; Figs. 5A through 5R are timing charts showing operations of the first embodiment of the data transfer section during a write transfer cycle to transfer data from the serial port section to the RAM section. Referring now to the accompanying drawings, a data transfer circuit of the present invention will be described below in detail. First, referring to Fig. 2A, the configuration of the first embodiment will be described. The data transfer circuit includes two data latch circuits 11b and 11d and three data transfer gates 11a, 11c, and 11e. Data transfer gate 11a is connected to, for example, a RAM section (not shown) which includes a memory cell array, via lines 411a and 411b and to data latch circuit 11b via lines 412a and 412b. Gate 11a controls data transfers between the RAM section and data latch circuit 11b in response to a control signal 4a. Data transfer gate 11c is connected to data latch circuit 11b via lines 413a and 413b and to data latch circuit 11d via lines 414a and 414b. Gate 11c controls data transfers between circuits 11b and 11c in response to gate control signal 4d. Data transfer gate 11e is connected to circuit 11d via lines 415a and 415b and to, for example, a serial port section (not shown) via lines 416a and 416b. Gate 11e controls data transfers between circuit 11d and the serial port section (not shown) in response to gate control signal 4g. Data transfer gates 11a, 11c and 11e are comprised of N-type MOS transistors Q1 and Q2, Q13 and Q14, and Q25 and Q26 and controls the data transfer in response to gate control signals 4a, 4d, and 4g. respectively. Each data transfer gate is rendered conductive when gate control signal supplied thereto is at a "H" level, and rendered nonconductive when the gate control signal is at a "L" level. Data latch circuits 11b and 11d are controlled in accordance with equalize signals 4b and 4e and sense signals 4c and 4f, respectively. When the equalize signal goes to a "H" level, the data latch circuit loses data held therein. When the equalize signal is at a "L" level, if the sense signal goes to a "H" level, then the data latch circuit senses and amplifies small data bit signal transferred thereto to latch them during a period of time when the sense signal is at a "H" level. Data holding circuit 11b is comprised of a sense circuit section including P-type MOS transistors Q6 and Q7, and N-type MOS transistors Q3 and Q4 and an equalize circuit section including an N-type MOS transistor Q5. In this case the common sources of transistors Q6 and Q7 are supplied with a signal on line 11b-1, the common sources of transistors Q3 and Q4 are supplied with a signal on line 11b-2, and the gate of transistor Q5 is supplied with an equalize signal 4b. Controller 12a includes a P-type MOS transistor Q8, N-type MOS transistor Q9 through Q12, and an inverter Q30. Transistors Q8 and Q9 are in the off state when sense signal 4C is at "L" level. At this time, when equalize signal 4b becomes high, transistor Q5 is turned on, voltages on lines 417a and 417b are equalized. Also transistor Q10 to Q12 are turned on so that voltages on lines 11b-1 and 11b-2 are equalized to voltage VBL as bit line equalize voltage. When equalize signal 4b is at "L" level, transistors Q10 through Q12 are turned off. At this time, when sense signal 4C becomes high, transistors Q8 and Q9 are turned on, but transistors Q10 through Q12 are remained in the off state. Therefore, line 11b-1 is connected to voltage Vcc via transistor Q8 and line 11b-2 connected to voltage Vss via transistor Q9. Thus, small data bit signals on lines 412a and 412b, 417a and 417b, or 413a and 413b are sensed and amplified. Data latch circuit 11d and controller 12b are similar to circuit 11b and controller 12a. In the data transfer circuit according to the first embodiment, controller 12a and 12b are omitted in Fig. 2B for reason of convenience of illustration. Referring to Fig. 3A, an arrangement of a first embodiment of a data transfer section for controlling data transfers between a RAM section and a serial port section will be described, in which the data transfer circuits according to the first embodiment are included. An example that the data transfer section according to the first embodiment is applied to a semiconductor memory is shown in Fig. 3C. Data transfer is performed between a RAM section, including a equalizer, a memory cell array, a sense amplifier, a data line gate, a data line and the like, and a RAM port section including a sense write circuit, an input buffer, an output buffer, and the like. This transfer is well known. Also, the data transfer is performed between the RAM section and a serial port section, including sense write circuit M18, input buffer M20, output buffer M22 and the like, via data transfer section M17 according to the present invention. Data bits output from sense write circuit M18 in serial are written into the RAM section via data transfer section M17 in parallel in accordance with a control signal from controller M14 of control section (CTRL SEC.). The control section includes controller M11, M13, and M14, generator M12, and serial decoder M15. Data bits readout from the RAM section in parallel are output to the serial port via data transfer section M17 in serial in accordance with a control signal from controller M14. Controller M14 generating the control signals in accordance with a control signal from controller M13 receiving an address Ain and a control signal from controller M12. In this data transfer section shown in Fig. 3A each data transfer circuit is connected to bit line pairs from the RAM section. In this figure, lines 211a and 211b, 221a and 221b, 231a and 231b, 241a and 241b, and 251a and 251b are bit line pairs of the RAM section and each of them corresponds to lines 411a and 411b in Fig. 2A. Gates 21a - 25a, 21c - 25c and 21e - 25e correspond to data transfer gates 11a, 11c, and 11e, respectively. Data latch circuit 21b - 25b and 21d - 25d correspond to data latch circuits 11b and 11d, respectively. Signals 2a, 2d, 2g, 2h, 2i, 2j and 2k denote the gate control signals, signals 2b and 2e denote the equalize signals, and signals 2c and 2f denote the sense signals. Lines 2x and 2y denote a pair of data lines connected to the serial port section and hence correspond to lines 416a and 416b in Fig. 2A. Fig. 3B shows an arrangement of a control section (CTRL SEC.) for generating control signals. The control section includes controller 20h′ for generating a control signal in accordance with address Ain input from the external of the semiconductor memory, control signal generator 20h for generating a control signal in accordance with row address strobe signal RAS , column address strobe signal CAS , write enable signal WE , data transfer control signal DT / OE , and signal SE from the external, and control signal generator 20h″ for generating a control signal in accordance with the control signals from controller 20h′ and generator 20h and signal SC from the external. Generators 20h and 20h″ correspond to generator M12 in Fig. 3C. Controller 20h′ corresponds to controller M13 in Fig. 3C. Generator 20g is included in serial decoder M15. Generators 20a through 20f and controller 12a and 12b shown in Fig. 2A is included controller M14. In the arrangement of Figs. 3A and 3B, the operation of the data transfer section will be described. First, the operations in a read transfer cycle · serial read transfer data on the bit line pairs connected to the RAM section to common data lines 2x and 2y will be described with reference to timing charts of Figs. 4A through 4P. The operations will be described here with respect to the data transfer circuit composed of gates 21a, 21c, 21e and latch circuits 21b, 21d with exception of the case where need arises. In the initial state of the read transfer cycle in which the row address strobe signal RAS is at "H" level so that no data is read out of the RAM section, gate control signal 2a is at "H" level, equalize signal 2b is at "H" level, and sense signal 2c is at "L" level. Circuit 21b and bit lines 211a and 211b connected thereto are equalized to the same voltage potential. At this time gate control signal 2d is at "L" level and thus circuits 21b and 21d are disconnected from each other by gate 21c and can thus operate independently. In this state, therefore, data bits held in circuits 21d through 25d can be read onto common data lines 2x and 2y in serial by switching gate control signals 2g, 2h, 2i, 2j and 2k from "L" to "H" level in sequence. When signal RAS goes from "H" level to "L" level, generators 20a and 20b make gate control signal 2a and equalize signal 2b low in response to a control signal from controller 20h, as shown in D and E of Fig. 4. Memory cells are specified among a memory cell array in the RAM section to read out data bits. The readout data bits are sensed and amplified. Hence, when a bit-line sense initiating signal (not shown) is activated in response to the signal RAS , "H"-level and "L"-level signals corresponding to one of the data bits appear on bit lines 211a and 211b after a delay time, as shown in B and C of Fig. 4. At this time, signal 2a is made high as shown in E of Fig. 4, so that the data bit signals on bit line 211a and 211b are transferred to circuit 21b. Generator 20c responds to signal 2a to cause signal 2c to go to "H" level after a predetermined delay time from the time when signal 2a goes to "H" level. In response to signal 2c, circuit 21b senses and amplifies the data bit signals on lines 501a and 501b. As a result, the data bit signals on lines 501a and 501b shift to the "H" and "L" levels, respectively, from the equalize level in circuit 21b as shown in J and K of Fig. 4. When the data sensing operation is initiated, generator 20a responds to signal 2c to cause gate control signal 2a to go to "L" level as shown in E of Fig. 4, so that circuit 21b is disconnected from bit line pair 211a and 211b. In this way latch circuit 21b latches data bit signals on the corresponding bit lines as shown in J and K of Fig. 4. Next, when a signal (not shown) for determining the initiation of data transfer from circuit 21b to circuit 21d is activated, generator 20f make sense signal 2f low as shown in I of Fig. 4, so that data latching operation of circuit 21d is stopped. In response to the transition of signal 2f, equalize signal 2e is made high for a predetermined time period as shown in G of Fig. 4. Circuit 21d is thus equalized, as well as the signals on wires 502a, 502b, as shown in L and M of Fig. 4. In response to the fall of signal 2e, generator 20d cause gate control signal 2d to go to "H" level as shown in H of Fig. 4, so that circuits 21b is electrically connected to circuit 21d. Consequently, data bit signals latched by circuit 21b are transferred to circuit 21d. Generator 20f responds to the rise of signal 2d to cause sense signal 2f to go to "H" level so that the data bit signals are sensed by circuit 21d. When the data bit signals are sensed, generator 20d responds to the rise of signal 2f to cause signal 2d to go to "L" level. This results in disconnection between circuits 21b and 21d. When the data transfer is completed, signal 2c is made low in response to signal 2d to stop the latching operation of circuit 21b. After signal 2c is made low, signal 2b is made high to equalize the signals in circuit 21b. Thereafter signal 2a is also made high. As a result, the signals on lines 501a and 501b are equalized and then lines 501a and 501b are connected to equalized bit line pair 211a and 211b to provide for the next data transfer. In this way, data bits latched by circuits 21b through 25b, namely data bit signals on bit line pairs 211a and 211b through 251a and 251b are transferred to circuits 21d through 25d. If gate control signal 2d is at "L" level, data bit latched by circuit 21d through 25d can be sequentially read out onto data lines 2x and 2y by making gate control signals 2g through 2k high in sequence, even while new data bits are being transferred from bit line pairs to circuit 21b through 25b. In Fig. 4N, the new data bits are read out onto data lines 2x and 2y from a timing of signal 2k. An operation of a write transfer cycle will be described with reference to Figs. 5A through 5R. In the write transfer cycle, data bits serially supplied onto data lines 2x and 2y are transferred onto bit line pairs in parallel. In this initial state, gate control signal 2a is at "H" level as shown in E of Fig. 5, sense signal 2c is at "L" level as shown in F of Fig. 5, and equalize signal 2b is at "H" level as shown in D of Fig. 5. Circuit 21b and bit line pair connected thereto are thus equalized to the same potential level. At this time gate control signal 2d is at "L" level as shown in H of Fig. 5, so that circuits 21d and 21b are disconnected from each other and thus can operate independently. When gate control signal 2d is at "L" level, signals 2g through 2k which are at "H" level is generated in accordance with signal SC with "H" level. Signals 2g through 2k are sequentially switched from a column specified in accordance with a predetermined start address each time signal SC is switched. When signal SC is at "H" level, data bit is fetched from a S I/O terminal and is written onto data lines 2x and 2y. At this time, one of gates 21e through 25e corresponding to one of signals 2g through 2k which is at "H" level is opened. Thus, data bit signals latched by one of circuit 21d through 25d which corresponds to the opened gate is forcedly inverted or writes data bit on lines 2x and 2y into the corresponding latch circuit. More specifically, one of data lines precharged to "H" level is fallen to "L" level. At this time, the voltage level of a node fallen to "L" level in the latch circuit is set to be lower than an inverted voltage of the latch circuit. Signal 2f is left high. Thus, data bits on data lines 2x and 2y are written into latch circuit 21d through 25d. Generators 20a and 20b cause gate control signal 2a and equalize signal 2b to go to "L" level in response to the transition of signal RAS to "L" level and signals WE , DT / OE and SE . Consequently circuit 21b and bit line pair 211a and 211b are disconnected. Gate control signal 2d is made high in response to the transition of signal 2b to "L" level, so that the data bit held in circuit 21d is transferred to circuit 21b. As a result, the data bit signals appear on lines 501a and 502b as shown in J and K of Fig. 5. When gate control signal 2d goes to "L" level after the lapse of a predetermined time from the transition of signal 2d to "H" level, disconnection is made between circuits 21d and 21b. Thereafter, in response to the transition of signal 2d to "L" level, sense signal 2c is then made high, so that the data bit signal is sensed and latched. Signal 2a is made high in response to the transition of signal 2c to "H" level, so that the data bit latched by circuit 21b is transferred onto bit line pair 211a and 211b. Thereafter, signal 2a is made low, so that circuit 21b is disconnected from bit line pair 211a and 211b. After signal 2d has been made low, new data bits on common data lines 2x and 2y can be written into circuits 21d through 25d in serial, switching signals 2g through 2k to "H" level in sequence. According to the data transfer circuit of the first embodiment, as described above, second data latch circuits, connected to a pair of data lines, are arranged separate from first data latch circuits connected to bit line pairs. Therefore, even if data bits disappear in the RAM section when the data bits from the bit line pairs are transferred from the second data latch circuits to the serial port section data bits to be transferred from the second data latch circuits to the serial port section can be switched to the data bits output from the RAM section at a desired timing. More specifically, the timing for transferring data bits held by first data latch circuits to the second data latch circuits can be set to a timing after data bits disappear in the RAM section, since the data bits from the RAM section have already been transferred to the first data latch circuits. Data bits previously transferred and held by the second data latch circuits can be transferred to the serial port section in serial, until the data bits held by the first data latch circuits are transferred to the second data latch circuits. Therefore the switching timing from the previous data bits to the data bits transferred from the RAM section can be set arbitrarily. Also, if the second data transfer gate is closed, the data transfer from the second data latch circuits to the serial port section can be performed continuously even while the data is transferred from the RAM section to the first data latch circuits. As a result, the data transfer timing from the RAM section to the serial port section can be set arbitrarily. In the write transfer cycle, data bits can be transferred from the first data latch circuits to the RAM section even while new data bits are written from the serial port section into the second data latch circuits, if the data bits held in the second data latch circuits have been transferred to the first data-latch circuits. As mentioned above, this data transfer circuit can arbitrarily set the timing of the data transfer and can continuously input or ouput the data.

Claims: A data transfer circuit comprising: first data latch means (11b) for receiving and holding data; second data latch means (11d) for receiving and holding data; and first data-transfergatemeans (11a) connected between a RAM and said first data latch means (11b), for controlling the transfer of data between the RAM and said first data latch means (11b), said first data-transfer gate means (11a) being designed to open upon lapse of a predetermined time after a sense signal supplied from the RAM has been activated while the data transfer circuit is in a first data-transfer condition, thereby to transfer data from the RAM to said first data latch means (11b), and to open after the RAM has been activated, but before a sense signal supplied from the RAM is activated, while the data transfer circuit is in a second data transfer condition, thereby to transfer data from said first data latch means (11b) to the RAM; characterized by second data-transfer gate means (11c) connected between said first data latch means (11b) and said second data latch means (11d), for controlling the transfer of data between said first data latch means (11b) and said second data latch means (11d), said second data-transfer gate means (11c) being designed to open when data is switched in said second data latch means (11d) while the data transfer circuit is in the first data-transfer condition, thereby to transfer data from said first data latch means (11b) to said second data latch means (11d), and to open when the RAM is activated while the data transfer circuit is in the second data-transfer condition, thereby to transfer data from said second data latch means (11b) to said first data latch means (11b); and third data-transfer gate means (11e) connected between said second data latch means (11d) and a serial port section, for controlling the transfer of data between said second data latch means (11d) and the serial port section, said third data-transfer gate means (11e) being designed to open while the serial port section is in a read mode, thereby to transfer data from said second data latch means (11d) to the serial port section, and to open while the serial port section is in a write mode, thereby to transfer data from the serial port section to said second data latch means (11d) ; wherein: said first data latch means (11b) holds data from the RAM in accordance with a control signal which is activated after the first data-transfer gate means (11b) has been opened while the data transfer circuit is in the first data-transfer condition, and hold the data from the second data latch means (11d) in accordance with a control signal which is activated after the second data-transfer gate means (11c) has been opened and then closed while the data transfer circuit is in the second data-transfer condition, said second latch means (11d) holds data from the first data latch means (11b) in accordance with a control signal which is activated after the second data-transfer gate means is opened while the data transfer circuit is in the first data-transfer condition, and holds data from the serial port section when the third data-transfer gate means (11e) is opened while the data transfer circuit is in the second direction, the data read from the RAM is transferred to the serial port section while the data transfer circuit remains in the first data-transfer condition, and the data input from the serial port section is written into the RAM while the data transfer circuit remains in the second data-transfer condition. A data transfer circuit according to claim 1, further comprising first control means (12a) for controlling said first data latch means (11b), and second control means (12b) for controlling said second data latch means (11d). A data transfer circuit according to claim 2, wherein said first data latch means (11b) includes first latch means (Q3, Q4, Q6, Q7) for latching the data transferred under the control of said first control means (12a), and first equalizing means (Q5) for equalizing the data latched in said first latch means (Q3, Q4, Q6, Q7) before data is transferred to said first latch means (Q3, Q4, Q6, Q7) under the control of said first control means (12a); and said second data latch means (11d) includes second latch means (Q15, Q16, Q18, Q19) for latching the data transferred under the control of said second control means (12b), and second equalizing means (Q17) for equalizing the data latched in said second latch means (Q15, Q16, Q18, Q19) before data is transferred to said second latch means (Q15, Q16, Q18, Q19) under the control of said second control means (12b). A data transfer circuit according to claim 3, wherein said first control means (12a) includes a first MOS transistor (Q8) of a first conductivity type having a current path coupled at one end to a power supply (Vcc) and a gate connected to receive a signal obtained by inverting a first sense signal (4c) supplied from the RAM, a second MOS transistor (Q10) of a second conductivity type having a current path coupled at one end to the other end of the current path of said first MOS transistor (Q8) and a gate connected to receive a first equalize signal (4b), a third MOS transistor (Q9) of the second conductivity type having a current path connected between the other end of the current path of said second MOS transistor (Q10) and a ground potential (Vss), and a gate connected to receive the first sense signal (4c), a fourth MOS transistor (Q12) of the second conductivity type having a current path connected at one end to a potential source (VBL) which is at the same potential as the bit lines of the RAM assume when equalized, and at the other end to a node of said first MOS transistor (Q8) and said second MOS transistor (Q10), and a gate connected to receive the first equalize signal (4b), and a fifth MOS transistor (Q11) of the second conductivity type having a current path connected at one end to said potential source (VBL) and at the other end to a node of said second MOS transistor (Q10) and said third MOS transistor (Q9), and a gate connected to receive the first equalize signal (4b); and said second control means (12b) includes a sixth MOS transistor (Q20) of the first conductivity type having a current path coupled at one end to the power supply (Vcc) and a gate connected to receive a signal obtained by inverting a second sense signal (4f) supplied from the RAM, a seventh MOS transistor (Q22) of the second conductivity type having a current path coupled at one end to the other end of the current path of said sixth MOS transistor (Q20) and a gate connected to receive a second equalize signal (4e), an eighth MOS transistor (Q21) of the second conductivity type having a current path connected between the other end of the current path of said seventh MOS transistor (Q22) and the ground potential (Vss), and a gate connected to receive the second sense signal (4f), a ninth MOS transistor (Q24) of the second conductivity type having a current path connected at one end to said potential source (VBL) and at the other end to a node of said sixth MOS transistor (Q20) and said seventh MOS transistor (Q22), and a gate connected to receive the second equalize signal (4e), and a tenth MOS transistor (Q23) of the second conductivity type having a current path connected at one end to said potential source (VBL) and at the other end to a node of said seventh MOS transistor (Q22) and said eighth MOS transistor (Q21), and a gate connected to receive the second equalize signal (4e). A data transfer circuit according to claim 4, wherein said first latch means includes an eleventh MOS transistor (Q6) of the first conductivity type having a current path connected at one end to a first data-transfer line (412a) and at the other end to a node of said first and second MOS transistors (Q8, Q10), and a gate connected to a second data-transfer line (412b), a twelfth MOS transistor (Q7) of the first conductivity type having a current path connected at one end to the second data-transfer line (412b) and at the other end to the node of said first and second MOS transistors (Q8, Q10), and a gate connected to the first data-transfer line (412a), a thirteenth MOS transistor (Q3) of the second conductivity type having a current path connected at one end to the first data-transfer line (412a) and at the other end to the node of said second and third MOS transistors (Q10, Q9), and a gate connected to the second data-transfer line (412b), and a fourteenth MOS transistor (Q4) of the second conductivity type having a current path connected at one end to the second data-transfer line (412b) and at the other end to a node of said second and third MOS transistors (Q10, Q9), and a gate coupled to the first data-transfer line (412a); said first equalizing means includes a fifteenth MOS transistor (Q5) having a current path connected between the first data-transfer line (412a) and the second data-transfer line (412b) and a gate connected to receive the first equalize signal (4b); said second latch means includes a sixteenth MOS transistor (Q18) of the first conductivity type having a current path connected at one end to a third data-transfer line (414a) and at the other end to the node of said sixth and seventh MOS transistors (Q20, Q22), and a gate connected to a fourth data-transfer line (414b), a seventeenth MOS transistor (Q19) of the third conductivity type having a current path connected at one end to the fourth data-transfer line (414b) and at the other end to a node of said sixth and seventh MOS transistors (Q20, Q22), and a gate connected to the third data-transfer line (414a), a eighteenth MOS transistor (Q15) of the second conductivity type having a current path connected at one end to the third data-transfer line (414a) and at the other end to the node of said seventh and eighth MOS transistors (Q22, Q21), and a gate connected to the fourth data-transfer line (414b), and a nineteenth MOS transistor (Q16) of the second conductivity type having a current path connected at one end to the fourth data-transfer line (414b) and at the other end to the node of said seventh and eight MOS transistors (Q22, Q21), and a gate connected to the third date-transfer line (414a); and said second equalizing means includes a twentieth MOS transistor (Q17) having a current path connected between the third data-transfer line (414a) and the fourth data-transfer line (414b) and a gate connected to receive the second equalize signal (4e). A data transfer circuit according to claim 1, wherein said first data-transfer gate means (11a) includes a first MOS transistor (Q1) which has a current path connected in series to a first data-transfer line (412a) and which is turned on in response to the sense signal supplied and a data-transfer signal, both supplied to the RAM, and a second MOS transistor (Q2) which has a current path connected in series to a second data-transfer line (412b) and which is turned on in response to the sense signal and the data-transfer signal, both supplied to the RAM. A data transfer circuit according to claim 1, wherein said second data-transfer gate means (11c) includes a first MOS transistor (Q13) which has a current path connected in series to a first data-transfer line and which is turned on in response to a data-switching signal supplied to said first data latch means (11b), and a second MOS (Q14) which has a current path connected in series to a second data-transfer line and which is turned on in response to a data-switching signal supplied to said second data-holding means (11d). A data transfer circuit according to claim 1, wherein said third data-transfer gate means (11e) includes a first MOS transistor (Q25) which has a current path connected in series to a first data-transfer line and which is turned on in response to a data-input/output timing signal supplied to said serial port section, and a second MOS transistor (Q26) which has a current path connected in series to a second data-transfer line and which is turned on in response to a data-input/output timing signal supplied to the serial port section.

Inventors: OHSHIMA SHIGEO, SAHARA HIROSHI, TODA HARUKI, WATANABE YUJI, OHSHIMA, SHIGEO, SAHARA, HIROSHI, TODA, HARUKI, WATANABE, YUJI, OHSHIMA, SHIGEO C/O PATENT DIVISION, SAHARA, HIROSHI C/O PATENT DIVISION, TODA, HARUKI C/O PATENT DIVISION, WATANABE, YUJI C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: G06F5
IPC codes: G11C11, G06F5, G11C7