Method of producing a dynamic random access memory device

Abstract: A dynamic random access memory device includes a storage capacitor (C) having a plurality of stacked conductive films (26a₁, 26a₂,..., 26a n ) which form a storage electrode (26a). A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap (24₁) is formed between an insulating film (15) which covers a gate electrode (WL1) for insulation and a lowermost film (26a₁) of the storage electrode. Connection between the adjacent films is established so that an uppermost film (36₂) elevationally extends so as to make contact with a drain region (13). Also, connection can be established so that an upper film (46₂) is mounted directly on an lower film (46₁). An end portion of the film is thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a method of producing a dynamic random access memory. Currently, samples of dynamic random access memory devices (hereafter simply referred to as DRAM device) of 16 Mbits are available. As the integration density is increased, a size of the cell on a plane must be reduced. Generally, a reduction in the size of the cell leads to a reduction in capacitance of the charge storage capacity. Additionally, as the capacitance is reduced, a soft error arising from the incidence of an α-ray is increased. For this reason, it is desired to decrease the size of the charge storage capacitor on the plane without reducing the capacitance thereof. For this requirement, stacked capacitor type DRAM devices have been proposed and realized. In a conventional stacked capacitor type DRAM device, one of a pair of electrodes of the storage capacitor is formed so as to have a three dimensional structure. The three dimensional structure of the electrode results in a 30 - 40 % increase in the capacitance of the storage capacitor, compared with a storage capacitor of two dimensional structure having the same size on the plane. However, an increase in the capacitance provided by the conventional three-dimensional electrode is not enough to fabricate a highly integrated DRAM device having a integration density of 16 Mbits or more. It is also known that in order to increase the capacitance of the capacitor, a dielectric film included in the storage capacitor is made of a material of a high dielectric constant such as tantalum oxide (Ta 2 O 5 ). However, the use of Ta 2 O 5 causes an increased leak current passing through the insulating film, compared to a dielectric film made of silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). Trench type DRAM devices have also been proposed and realized in which a number of trenches are formed on a surface of a semiconductor substrate, and storage capacitors are formed into the trenches. For a 16Mbit-class DRAM device, it is difficult to separate neighboring storage capacitors from each other by a distance of less than approximately 0.5 [µm]. Such an arrangement of the neighboring storage capacitors may cause an interference which occurs. In the interference, a charge stored in one of the neighboring storage capacitors is transferred to the other capacitor when a voltage is applied to the other capacitor, and therefore information is destroyed. Yet another conventional DRAM device has been proposed in the Japanese Laid-Open Patent Publication JP-A-60 9154 (18.1.95). The publication discloses a storage capacitor having a multilayer structure, the elevational cross section of which has a comb shape. However, the prior art disclosed in the above publication has the following disadvantages. Firstly, the transfer transistor and the charge storage capacitor are arranged side by side on the substrate. Therefore, a high integration density cannot be obtained. Secondly, a considerably increased capacitance of the storage capacitor of the publication cannot be obtained, because the storage capacitor has the comb-shaped cross section, that is, the storage electrode does not have the projections formed on all the side surfaces thereof. From Patent Abstracts of Japan, vol. 5, no. 121 (E-68) [793] 5.8.81 & JP-A-56 58254, (Oke Denki Kogyo KK) 21.5.81, a method of producing a dynamic random access memory device is known, comprising the steps of forming a transfer transistor comprising a pair of impurity diffused regions which are located within an area defined by a field insulating film formed on a substrate and a gate electrode being located between the pair of impurity diffused regions, forming a first film so as to cover the transfer transistor for insulation, forming a second film on the first film, the second film being made of a material different from the first film, forming an opening in the first conductive film, forming a first conductive film on the second film, patterning the first conductive film in accordance with a desired size of a storage electrode, forming a dielectric film on an exposed surface of the patterned first conductive film, and forming a second conductive film so as to surround the patterned first conductive film around which the dielectric film formed. From Patent Abstracts of Japan, vol. 11, no. 351 (E-557) [2798] 17.11.87 & JP-A-62 128168, (Hitachi Ltd) 10.6.87, a cell of a dynamic random access memory device is known comprising a storage capacitor formed on a substrate, and a transfer transistor. The transfer transistor comprises a pair of impurity diffused regions which are formed in the substrate and are located within an area defined by a field insulating film formed on the substrate, and a gate electrode being located between the pair of impurity diffused regions and being covered by an insulating film. The storage capacitor comprises a storage electrode formed by a conductive material being connected to either one of the impurity diffused regions through an opening formed in the insulating film, and extending above the field insulating film and the gate electrode, a dielectric film being formed so as to surround an exposed surface of the storage electrode, and an opposed electrode made of a conductive material being formed so as to surround the storage electrode. Finally, document EP-A-0 317 199, which is a prior art document according to Art. 54(3) EPC, discloses a layer structure of a memory cell for a dynamic random access memory device as well as a method of producing the same. According to this document, the capacitor comprises a storage electrode being arranged below the opposed electrode, wherein both electrodes are separated from each other by a dielectric film. SUMMARY OF THE INVENTION Accordingly, a genral object of the present invention is to provide a method of producing a dynamic random access memory device in which the disadvantages of the conventional arts have been eliminated. A more specific object of the present invention is to provide a method of producing a dynamic random access memory device in which a further increased integration density can be obtained. Another object of the present invention is to provide a method of producing a dynamic random access memory device in which an extremely increased capacitance of a charge storage capacitor can be obtained without decreasing the integration density. Yet another object of the present invention is to provide a method of producing a dynamic random access memory device in which the dynamic random access memory device can be produced by a simplified process. According to the present invention, these objects are achieved by a method of producing a dynamic random access memory device according to claim 1. Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a circuit diagram of a DRAM cell; FIG.2 is a perspective view for explaining the principle of the present invention; FIG.3 is a graph showing a relationship between a depth of a groove formed in a storage electrode and a storage capacitance; Fig.4 is an elevational cross sectional view of a DRAM device; FIG.5A is an elevational cross sectional view of a DRAM useful for understanding the present invention; FIG.5B is an elevational cross sectional view of a variation of the DRAM of FIG.5A ; FIGS.6A through 6H are elevational cross sectional views showing steps of a process for producing the DRAM of FIG.5A; FIGS.7A through 7F are elevational cross sectional views showing steps of a process for producing the variation of FIG.5B; FIG.8 is a plan view of various embodiments of the present invention; FIG.9 is an elevational cross sectional view of a second example of a DRAM useful for understanding the present invention; FIGS.10A through FIG.10G are elevational cross sectional views showing steps of a process for producing the second example of FIG. 9; FIG.11 is an elevational cross sectional view of a third example of a DRAM useful for understanding the present invention; FIGS.12A through 12I are elevational cross sectional views showing steps of a process for producing the third example of FIG.11; FIG.13A is an elevational cross sectional view of a DRAM produced by a first method of the present invention; FIG.13B is an elevational cross sectional view of a DRAM produced by a variation of the first method of the present invention; FIGS.14A through 14I are elevational cross sectional views showing steps of the first method of the present invention for producing the DRAM of FIG.13A; FIG.15 is an elevational cross sectional view of a DRAM produced by a second method of the present invention; FIGS.16A through 16H are elevational views showing steps of the second method of the present invention for producing the DRAM shown in FIG.15; FIG.17 is an elevational cross sectional view of a DRAM produced by a third method of the present invention; FIGS.18A through 18J are elevational cross sectional views showing steps of the third method of the present invention for producing the DRAM of FIG.17; FIGS.19A and 19B are views for explaining specific advantages of a DRAM produced by methods of the present invention; FIG.20 is a plan view of a DRAM produced in accordance with the present invention; FIG.21 is an elevational cross sectional view of the DRAM of Fig.20; and FIGS.22A through 22G are elevational cross sectional views showing steps of a process for producing the DRAM shown in FIGS.20 and 21. DETAILED DESCRIPTION Referring to FIG.1, a DRAM cell includes a transfer transistor T and a charge (information) storage capacitor C. The transfer transistor T is used for transferring a charge (information). The transfer transistor T is constituted by an n + -type metal insulator semiconductor transistor FET (field effect transistor) or a metal oxide semiconductor transistor. The storage capacitor C is used for storing a charge which can be transferred by the transfer transistor T. A storage electrode 16 of the storage capacitor C is connected to a drain or source of the transfer transistor T. There is provided a dielectric film interposed between the storage electrode 16 and an opposed electrode 18. A bit line BL1 and a word line WL1 is connected to a source and a gate of the transfer transistor T, respectively. FIG.2 is a perspective view, which is used for explaining the principle of the present invention. The charge storage electrode 16, which is one of a pair of electrodes of one DRAM cell, includes two n + -type polysilicon (polycrystalline silicon) films 16a and an n + -type polysilicon film 16b which is interposed between the opposing the polysilicon films 16a. As illustrated, there is formed a groove 16b around the side surfaces of the storage electrode 16. Symbols L1 and L2 denote lengths of each of the storage electrodes 16a. A Symbol L3 denotes a thickness of each of the polysilicon films 16a, and a symbol L4 denotes a thickness of the polysilicon film 16b. A letter d denotes a depth of the groove 16c. It is now assumed in the illustrated structure that L1 = 1.2 [µm], L2 = 2.0 [µm] and (L3 x 2) + L4 = 0.5 [µm], and that the presence of the groove 16c is neglected (that is, the storage electrode has no groove). In this case, the storage electrode 16 is a three-dimensional body of 1.2 [µm] x 2.0 [µm] x 0.5 [µm]. Also, a surface area S of five surfaces which contribute to storing a charge is calculated as follows: S = 1.2 x 2 + (1.2 x 0.5 + 2 x 0.5) = 5.6 [µm 2 ] In the case where an insulating film (dielectric film) which has a thickness of 7,5 nm (75 [Å]) and a dielectric constant of 3.8, is used with respect to the above storage electrode having the above size, a capacitance of the storage capacitor is 25.1 [fF]. It is further assumed that the above storage electrode 16 is provided with one groove having a length L4 of 0.15 [µm] and a depth d to form the storage capacitor illustrated in FIG.2. FIG.3 is a graph showing a relationship between a storage capacitance and a depth of the groove 16b. The horizontal axis of the graph represents a depth of the groove 16b and the vertical axis represents a capacitance of the storage capacitor. As will be seen from FIG.3, when d = 0, that is, there is no groove, the storage capacitance has a value of 25.1 [fF]. When the groove 16b of having a depth of 0.3 [µm] is formed around all the side surfaces of the storage capacitor 16, the storage capacitance having a value of 37.5 [fF] is obtained. That is, the latter storage capacitor has an increase by 49.4 [%] in the storage capacitance, compared with the former storage capacitor. The storage capacitor shown in FIG.2 has only one groove 16c. However, it will be obviously seen that an increased number of grooves increases the capacitance of the storage capacitor. A description is given of a preferred method of producing a DRAM device, by referring to Fig.4. Referring now to FIG.4, a surface of a silicon (Si) substrate 11 is subjected to heat oxidation by a local oxidation technique. Thereby, a field oxidation film 12 having a thickness of approximately 500 nm (5,000 [Å]) is formed on the surface of the Si substrate 11. Next, a gate oxidation film (not shown) made of silicon dioxide (SiO 2 ) having a thickness of approximately 20 nm (200 [Å]) is formed by subjecting the Si substrate 11 to the thermal oxidation process. Then a polysilicon film having a thickness of approximately 300 nm (3,000 [Å]) is grown on the entire surface of the Si substrate 11 by chemical vapor deposition (hereafter simply referred to as CVD). In order to obtain low resistance of the deposited polysilicon film, phosphorus is diffused therein. Alternatively, an impurity-doped polysilicon film may be deposited by CVD or low-pressure CVD (LPCVD). Thereafter, the polysilicon film of low resistance is subjected to a patterning process, and thereby gate electrodes (word lines) WL1 and WL2 are formed as shown in FIG.4. The gate electrodes WL1 is a word line of the cell shown in FIG.1, and the gate electrode WL2 is a word line adjacent to the word line of the gate electrode WL1. Subsequently, a desired impurity ion such as an arsinic (As + ) ion is injected into the Si substrate 11 with an impurity concentration of approximately 1 x 10 15 [cm -2 ] and an energy of 70 [keV], for example. In this step, the word lines WL1 and WL2 are used as mask films. Thereby, n + -type impurity diffused regions 13 and 14 are formed. The n + -type impurity diffused regions 13 and 14 act as drain and source of the transfer transistor T shown in FIG.1, respectively. Thereafter, an insulating film 15 is formed on the entire surface of the Si substrate 11 by CVD or LPCVD. The insulating film 15 has a thickness of 100 nm (1,000 [Å]), for example, and is made of silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ) or the like. Thereafter, a resist film is formed on the insulating film 15 except for a surface portion at which an opening 13a is to be formed. Then, the Si substrate 11 is subjected to anisotropic etching such as reative ion etching (RIE) and thereby the opening 13a is formed in the insulating film 15 as illustrated in FIG.4. A description is given of a first example useful for understanding the present invention with reference to FIGS.5A,5B 6A through 6H and 7, in which the same elements as those in the previous figures are denoted by the same reference numerals. One of the essential features of the example shown in FIG.5A is that a gap is formed between the insulating film 15 and a storage electrode 26 so as to be formed around the storage electrode 26 which is surrounded by a dielectric film 27. The gap is filled with a polysilicon film which serves as an opposed electrode 28. The DRAM cell of FIG.5A can be produced as follows. First, a layer structure shown in FIG.6A is formed by a sequence of processes which are identical to those described previously with reference to FIG.4. In FIG.6A, a gate oxidation film 21 which is not shown in FIG.4 is indicated by a broken line. Next, as shown in FIG.6B, a film 22 having a thickness almost equal to 100 nm (1,000 [Å]) is formed on the entire surface of the Si substrate 11 by CVD or LPCVD. The deposition of the films 15 and 22 may be successively performed. It is to be noted that the film 22 is made of a material different from a material forming the insulating film 15. For example, in the case where the insulating film 15 is a Si 3 N 4 film, a SiO 2 film can be used as the film 22 formed thereon. Alternatively, in the case where the insulating film 15 is a SiO 2 film, a Si 3 N 4 film is used to form the film 22. In the following description, it is assumed that the films 15 and 22 are formed by Si 3 N 4 and SiO 2 films, respectively. Then, as shown in FIG.6C, an opening 23 is formed in the SiO 2 film 22 and the Si 3 N 4 film 15 is formed by anisotropic etching such as reactive ion etching (RIE). In this step, a resist film (not shown) is used as a mask. The opening serves as a contact hole at which the drain region 13 is electrically in contact with the storage electrode 26 which is formed by the later step. Thereafter, an impurity-doped conductive polysilicon film having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 22 having the opening 23 by CVD or LPCVD. Then the polysilicon film is subjected to the patterning process. Thereby, as shown in FIG.6D, the storage electrode 26 having an illustrated elevational cross section is formed. Subsequently, as shown in FIG.6E, the SiO 2 film 22 is completely removed by isotropic etching in which the Si substrate 11 of FIG.6D is put into a liquid containing hydrogen fluoride (HF). The Si 3 N 4 film 15 which covers the gate electrodes (word lines) WL1 and WL2 is not etched by the HF liquid. Thereby, it is to be noted that a gap 24 1 is formed between the insulating film 15 and the storage electrode 26 so as to be formed around the storage electrode 26. Then, the storage electrode 26 is subjected to the thermal oxidation process and thereby the dielectric film 27 made of a SiO 2 film is formed on the exposed surface of the storage electrode 26, as shown in FIG.6F. In this step, it is preferable to set an oxidation atmosphere at a low pressure equal to or lower than 1330 Pa (10 [torr]). Under this condition, the dielectric film 17 can be uniformly formed on a surface portion of the storage electrode 26 which faces the insulating film 15 through the gap 24 1 . In place of the formation of the SiO 2 film 27, it is possible to grow a Si 3 N 4 film around the storage electrode 26 by LPCVD. Following the process of FIG.6F, an impurity-doped polysilicon film having a thickness of approximately 150 nm (1,500 [Å]), is deposited on the entire surface of the substrate 11 of FIG.6F by CVD or LPCVD. In this process, it is preferable to grow the polysilicon film in low-pressure atmosphere lower than approximately 133 Pa (1 [torr]). Under this condition, the polysilicon film can be grown so as to completely fill the gap 24 1 . Then, the polysilicon film is subjected to the patterning process, whereby as shown in FIG.6G, the polysilicon film 28 is formed. The patterned polysilicon film 28 is the opposed electrode 28. Then, as shown in FIG.6H, the insulating film 19 made of phosphosilicate glass (PSG), for example, is deposited on the entire surface of the Si substrate 11 of FIG.6G, by CVD. Then, the contact window 14a for the source region 14 is formed by the photolithography technique. Finally, a bit line 20 made of aluminum (Al), for example, is formed on the insulating film 19 by vacuum evaporation and photolithography technology. FIG.5A is a variation of the example shown in FIG.5A. The variation has an essential feature such that a storage electrode 26a includes a plurality of polysilicon films 26a 1 , 26a 2 ,..., 26a n . A dielectric film 27a is formed so as to surround an exposed surface of the storage electrode 26a. An opposed electrode 28a is formed so as to surround the storage electrode 26a, on the surface of which the dielectric film 27a is formed. The storage capacitor of the variation has a capacitance greater than that of the second embodiment of FIG.5A. The DRAM cell of FIG.5B can be produced as follows. First, the structure shown in FIG.6C described before is formed by the processes indicated in FIGS.6A through 6C. Then, as shown in FIG.7A, an impurity-doped polysilicon film 26a 1 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on a SiO 2 film 22 1 by CVD or LPCVD. Thereafter, as shown in FIG.7B, a SiO 2 film 22 2 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the polysilicon film 26a 1 by CVD or LPCVD. Then, as shown in FIG.7C, an opening 23 1 is formed in the SiO 2 film 22 2 by reactive ion etching (RIE) in which etching gas containing CF 4 /H 2 is used. The polysilicon film 26a 1 is exposed through the opening 23 1 . Thereafter, as shown in FIG.7D, a polysilicon film 26a 2 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 22 1 having the opening 23 1 by CVD or LPCVD. Then, as shown in FIG.7E, an opening is formed in the polysilicon film 22 3 . The contact between the polysilicon films 26a 2 and 26a 3 may be not necessarily positioned above the drain region 13. For example, the contact may be positioned above gate electrode WL1. Thereafter, an impurity-doped polysilicon film 26a 3 is deposited on the entire surface of the SiO 2 film 22 3 . In this manner, n number of the polysilicon films (fins) can be formed. Although three polysilicon layers 26a 1 , 26a 2 and 26a 3 are formed as shown in FIG.7F, two layers 26a 1 and 26a 2 may be formed without depositing the polysilicon layer 26a 3 . Then, the SiO 2 films 22 2 and 22 3 and the polysilicon films 26a 1 , 26a 2 and 26a 3 are subjected to the patterning process such as reactive ion etching (RIE), in which a resist film (not shown) is used as a mask. Subsequently, remaining portions of the SiO 2 films are completely removed by isotropic etching in which a liquid containing HF is used. Thereby, the storage electrode 26a having a structure shown in FIG.7F is formed. As shown in FIG.7F, there is formed a gap 24 1 between the insulating film 15 and the lowermost film 26a 1 so as to surround the storage electrode 26a. There are also formed gaps 24 2 and 24 3 between the mutually adjacent polysilicon films so as to surround the storage electrode 26a. Then, the entire exposed surface of the storage electrode 26a is subjected to the thermal oxidation process, and thereby the dielectric film 27a is formed thereon. Subsequent processes are the same as those for the DRAM device shown in FIG.6A. The multilayer structure of FIG.5B can also be produced by another process, which will be described later with reference to FIGS.10A through 10G. FIG.8 is a plan view of essential parts of each of the DRAM devices shown in FIGS.5A and 5B. The cross sectional views of FIGS.5A and 5B correspond to views taken along a line VI-VI. In FIG.8, the same reference numerals as those in the previous figures denote the same elements as those shown in the previous figures. As shown in FIG.8, the storage electrode 26 extends above the word lines WL1 and WL2. The storage electrode 26 partially overlaps the width of the word line WL1 and almost overlaps the width of the word line WL2. Reference numerals 12a', 20', 23' and 26' correspond to reference numerals 12a, 20, 23, and 26. A description is given of a second example useful for understanding the present invention with reference FIG.9. A storage electrode 36 of a DRAM cell of FIG.9 has an essential feature such that an uppermost polysilicon film elevationally extends so as to make contact with the drain region 13. Polysilicon films other than the uppermost film are connected to an elevationally extending portion thereof. The DRAM device of FIG.9 can be formed in accordance with steps shown in FIGS.10A through 10G. First, a structure shown in FIG.10A is formed by the processes which are the same as those described before by referring to FIG.5A. Subsequently, as shown in FIG.10B, there are successively deposited a SiO 2 film 32 1 having a thickness of approximately 100 nm (1,000 [Å]), an impurity-doped polysilicon film 36 2 having a thickness of approximately 100 nm (1,000 [Å]), and a SiO 2 film 32 1 having a thickness of approximately 100 nm (1,000 [Å]). The deposition of the above films can be performed by CVD or LPCVD. In this manner, a plurality of polysilicon films (fins) may be formed. Then, as shown in FIG.10B, a resist film 24 is formed on the SiO 2 film 32 1 and is then subjected to the patterning process. Thereafter, the SiO 2 films 32 1 and 32 2 , the polysilicon film 36 1 and the insulating film 15 are selectively removed by anisotropic etching such as RIE in which the resist film 24 is used as a mask. In this etching process, etching gas containing CF 4 /H 2 is used for the SiO 2 films 32 1 and 32 2 and the Si 3 N 4 film 15, and CCl 4 /O 2 is used for the polysilicon film 36 1 . Thereby, an opening 23 2 is formed. Then, as shown in FIG.11C, an impurity-doped polysilicon film 36 2 having a thickness of 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 32 2 by CVD or LPCVD. Thereafter, by using a resist film (not shown) as a mask, the polysilicon film 36 2 , the SiO 2 film 32 2 and the polysilicon film 36 1 are subjected to the patterning process by anisotropic etching such as RIE, as shown in FIG.10D. Then, remaining portions of the SiO 2 film 32 1 and 32 2 are completely removed by isotropic etch in which a liquid containing hydrogen fluoride (HF) is used. Thereby the storage electrode 36 having the structure shown in FIG.10E is formed. The lower film 36 1 is connected to an elevationally extending portion 36' of the upper film 36 2 . There is formed a gap 34 1 between the lower film 36 1 and the insulating film 15 15 so as to surround the storage electrode 36. Also there is formed a gap 34 2 between the films 36 1 and 36 2 so as to surround the storage electrode 36. In the case where the insulating film 15 is a SiO 2 film, and films 36 1 and 36 2 are formed by Si 3 N 4 films, phosphorus acid (PH 3 PO 4 ) etching is used. Then, the entire surface of the storage electrode 36 is subjected to the thermal oxidation process, and thereby the dielectric film 37 is formed thereon, as shown in FIG.10F. Thereafter, as shown in FIG.10G, an impurity-doped polysilicon film 38 is deposited on the Si substrate 11 of FIG.10F and is then subjected to the patterning process. Thereby the opposed electrode 38 is formed. In the deposition of the polysilicon film 38, the gaps 34 1 and 34 2 can be completely filled by growing the film in a low-pressure atmosphere than 1330 Pa (10 [torr]). Thereafter, the insulating film 19 made of phosphosilicate glass, for example, is formed on the entire surface of the Si substrate 11, and the contact window 14a is formed by CVD and photolithography technology. Finally, the bit line 20 made of aluminum (Al), for example, is formed on the insulating film 19 by vacuum evaporation and photolithography technology. A description is given of a third example useful for understanding the present invention with reference to FIG.11. A storage electrode 46 of the embodiment of FIG.11 has an essential feature such that an upper polysilicon film out of adjacent films is mounted directly on a lower polysilicon film of the adjacent films above the drain region 13. This feature is distinct from the feature of the second example. The DRAM cell of FIG.11 can be produced in accordance with steps shown in FIGS.12A through 12I. First, a structure shown in FIG.12A is produced by processes which are the same as those described previously by referring to FIG.4. Successively, as shown in FIG.12B, a SiO 2 film 42 1 having a thickness of approximately 100 nm (1,000[Å]) is deposited on the entire surface of the insulating film 15 by CVD or LPCVD, as described previously with reference to FIG.6B. Then an opening 23 5 is formed by a process which is identical to the process described before with reference to FIG.6C. Thereafter, as shown in FIG.12D, an impurity-doped polysilicon film 46 1 is deposited on the entire surface of the insulating film 15 having the opening 23 5 by CVD or LPCVD. The polysilicon film 46 1 has a thickness of 100 nm (1,000 [Å]), for example. Subsequently, as shown in FIG.12D, a SiO 2 film 42 2 is deposited on the entire surface of the polysilicon film 46 1 by CVD or LPCVD. The SiO 2 film 42 2 has an almost a thickness identical to that of the polysilicon film 46 1 . Then, as shown in FIG.12E, an opening 23 6 is formed in the SiO 2 film 42 2 by reactive ion etching (RIE) in which CF 4 /H 2 gas is used. A bottom of the opening 23 6 is the surface of the polysilicon film 46 1 . Thereafter, as shown in FIG.12F, an impurity-doped polysilicon film 46 2 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 42 2 having the opening 23 6 by CVD or LPCVD. Then, as shown in FIG.12G, the SiO 2 film and 42 2 and the polysilicon films 46 1 and 46 2 are subjected to the patterning process using reactive ion etching (RIE), in which a resist film (not shown) is used as a mask. Subsequently, as shown in FIG.12H, a remaining portion of the SiO 2 films are completely removed by isotropic etching in which a liquid containing HF is used. Thereby, the storage electrode 46 having a structure shown in FIG.12H is formed. As illustrated, there is formed a gap 44 1 between the insulating film 15 and the lower polysilicon film 46 1 so as to surround the storage electrode 46. Also there is formed a gap 44 2 between the films 46 1 and 46 2 so as to surround the storage electrode 46. Then, the entire exposed surface of the storage electrode 46 is subjected to the thermal oxidation process, and thereby the dielectric film 47 is formed thereon, as shown in FIG.12I. Subsequent steps are the same as those for the DRAM cell shown in FIG.5A, and thereby an opposed electrode 48, the insulating film 19 and bit line 20 are formed. FIG.13A shows a DRAM produced by a first method according to the present invention which is a modification of the first embodiment shown in FIG.5A. One of the essential features of the present invention is that a storage electrode 126 is formed by a polysilicon film 226 and a polysilicon film 326 so that stepped portions are formed on the both sides of the elevational cross section of the storage electrode 126. The stepped portions contribute to a further increase in the capacitance of the storage capacitor, compared with the first example shown in FIG.5A. The DRAM cell of FIG.13A is produced by the following producing method. First, the layer structure shown in FIG.14 is formed by processes which are the same as those described previously with reference to FIG.5A. Next, a SiO 2 film 122 is formed on the entire surface of the Si 3 N 4 film 15 by a process identical to that described before with reference to FIG.6B. Thereafter, as shown in FIG.14C, an impurity-doped polysilicon film 226 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 122 by CVD or LPCVD. Subsequently, the polysilicon film 226 is selectively removed by RIE in which the resist film (not shown) is used as a mask. Thereby, an opening 123 1 which is wider than the n + -impurity diffused region of drain region 13 is formed in the polysilicon film 226. The polysilicon film 226 is used for forming stepped portions located on the both sides of the elevational cross section of the storage electrode 126. Although the polysilicon film 226 has a thickness of approximately 100 nm (1,000 [Å]) described above, it is possible to form the polysilicon film 226 having a thickness of approximately 200 nm (2,000 [Å]). In this case, a laser beam is projected on the polysilicon film 226 so as to form convex portions and recess portions thereon. Thereafter, as shown in FIG.14D, an opening 123 2 which penetrates the SiO 2 film 122 and the Si 3 N 4 film 15 is formed by anisotropic etching such as RIE in which the resist film (not shown) is used. The opening 123 2 serves as a contact hole at which an electric contact between the storage electrode 126 and the drain region 13. Subsequently, as shown in FIG.14E, an impurity-doped polysilicon film 326 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the substrate 11 shown in FIG.14D by CVD or LPCVD, and is then subjected to the patterning process. Then, the SiO 2 film 122 is completely removed by isotropic etching using a liquid containing HF, so that the storage electrode 126 having the elevational cross section shown in FIG.14F is formed. As illustrated, a gap 54 is formed between the insulating film 15 and the storage electrode 126 so as to surround the storage electrode 126. In the above etching step, the Si 3 N 4 film 15 is not etched by the liquid containing HF. Thereafter, an exposed surface of the storage electrode 126 is subjected to the thermal oxidation process, and thereby as shown in FIG.14G, a dielectric film 127 is formed so as to surround the the storage electrode 126. Next, an impurity-doped polysilicon film 128 is deposited on the entire surface of the substrate 11 of FIG.14G, and is then subjected to the patterning process. Thereby, the opposed electrode 128 is formed. Finally, as shown in FIG.14I, the insulating film 119 made of PSG for example, is formed on the entire surface of the Si substrate 11 by CVD or LPCVD, and then the bit line 120 made of Al is formed on the insulating film 119 by the vacuum evaporation and photolithography technology. FIG.13B is a variation of the DRAM of FIG.13A. One of the essential features of the variation is that a storage electrode 126a is formed so as to have a plurality of stacked polysilicon films. A lowermost polysilicon film has stepped portions on the both sides of the elevational cross section of the storage electrode 126a. The stepped portions can be formed by a polysilicon film 226a. The DRAM cell of FIG.13B is formed by the same process as that described before with reference to FIG.7A through 7F except that before the polysilicon film 26a 1 of FIG.7A is formed, the polysilicon film 226a is formed on the SiO 2 film 22 1 , and an opening is formed therein as in the step shown in FIG.14C. FIG.15 is a DRAM produced by a second method in accordance with the present invention. The DRAM of Fig.15 is a modification of the second example of FIG.9. At first, the layer structure of FIG.16A which is the same as that shown in FIG.14A is formed. Next, a SiO 2 film 132 having a thickness of approximately 100 nm (1,000 [Å]) is formed on the entire surface of the Si 3 N 4 15 by CVD or LPCVD. Then, as shown in FIG.16B, an impurity-doped polysilicon film 236 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 132 by CVD or LPCVD, and is then selectively removed by RIE, so that an opening 133 1 which is wider than the drain region 13 is formed. Thereafter, as shown in FIG.16C, an impurity-doped polysilicon film 336 1 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the substrate 11 by CVD or LPCVD. Subsequently, as shown in FIG.16C, a SiO 2 film 132 2 having a thickness of 100 nm (1,000 [Å]) is formed on the entire surface of the polysilicon film 336 1 by CVD or LPCVD. The step for forming the bilayer structure consisting of the polysilicon film 336 1 and the SiO 2 film 132 1 may be repetitively carried out if desired. Then, a resist film 124 is formed on the entire surface of the SiO 2 film 132 1 and is then subjected to the patterning process. Next, by using the resist film 124 as a mask, the SiO 2 film 132 2 , the polysilicon film 336 1 , the SiO 2 film 132 1 and the Si 3 N 4 film 15 are selectively etched by anisotropic etching such as RIE. In the etching process, etching gas containing CF 4 /H 2 is used for etching the SiO 2 films 132 1 and 132 2 and the Si 3 N 4 film 15, and etching gas containing CCl 4 /O 2 is used for etching the polysilicon film 336 1 . Thereby as shown in FIG.16D, an opening 132 2 which penetrates the above stacked films is formed. Subsequently, the as shown in FIG.16D, an impurity-doped polysilicon film 336 2 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 132 2 having the opening 133 2 . Thereafter, the polysilicon film 336 2 , the SiO 2 film 132 2 , and the polysilicon films 336 1 and 236 are subjected to the patterning process by anisotropic etching such as RIE in which a resist film (not shown) is used. Thereby, the layer structure of FIG.16E is obtained. Next, remaining portions of the SiO 2 films 132 1 and 132 2 are completely removed by isotropic etching in which a liquid containing HF is used, and thereby the storage electrode 136 having the layer structure shown in FIG.16F is formed. As illustrated, a gap 64 1 is formed between the Si 3 N 4 film 15 and the lower polysilicon film consisting of the films 236 and 336 1 so as to surround the storage electrode 136. A gap 64 2 is formed between the polysilicon films 64 1 and 64 2 so as to surround the storage electrode 136. In the above etching step, the Si 3 N 4 which insulates the gate electrodes WL1 and WL2 from the polysilicon film 336 1 is not etched. In the case where the insulating film 15 is a SiO 2 film and insulating films 132 1 and 132 2 are Si 3 N 4 films, phosphorus acid (PH 3 PO 4 ) etching is employed. Thereafter, the exposed surface of the storage electrode 136 is subjected to the thermal oxidation process, and thereby a dielectric film 137 is formed so as to surround the storage electrode 136. Then, an opposed electrode 138, the insulating film 119 and the bit line 120 are formed in this order by the processes described before. FIG.16H shows the DRAM cell obtained by the above method. The DRAM cell of FIG.16H has the storage capacitor having the capacitance larger than that of FIG.9. A description is given of a DRAM produced by a third method according to the present invention, by referring to FIG.17. The DRAM of Fig.17 corresponds to a modification of the third example of FIG.11. The DRAM of Fig.17 has also an essential feature in that a storage electrode 146 has stepped parts on both the sides of the elevational cross section thereof. Therefore, a storage capacitor of the DRAM of Fig.17 has a capacitance larger than that of the third example shown in FIG.11. The DRAM of Fig.17 is produced by the following production process. First, the structure shown in FIG.18A is formed by processes identical to those described before with reference to FIG.4. Next, as shown in FIG.18B, a SiO 2 film 142 1 is deposited on the entire surface of the Si 3 N 4 film 15 by CVD LPCVD. Subsequently, an impurity-doped polysilicon film 246 having a thickness of approximately 100 nm (1,000 [Å]) is formed on the entire surface of,the SiO 2 film 142 1 by CVD or LPCVD. Then, as shown in FIG.18B, the polysilicon film 246 is selectively removed by RIE in which a resist film (not shown) is used, and thereby an opening 1431 is formed. The opening formed in the polysilicon film 246 is wider than the drain region 13. Thereafter, the SiO 2 film 142 1 and the Si 3 N 4 film 15 are selectively removed by anisotropic etching such as RIE in which a resist film (not shown) is used, and thereby an opening 1432 is formed as shown in FIG.18C. In this etching step, etching gas containing CF 4 /H 2 is used. Then, as shown in FIG.18D, an impurity-doped polysilicon film 346 1 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the Si substrate shown in FIG.18D by CVD or LPCVD. Subsequently, as shown in FIG.18D, a SiO 2 film 142 2 is deposited on the entire surface of the polysilicon film 346 1 by CVD or LPCVD. Then, as shown in FIG.22E, an opening 1433 is formed in the SiO 2 film 142 2 by RIE in which etching gas containing CF 4 /H 2 is used. Thereby, the polysilicon film 346 1 is partially exposed through the opening 143 3 . Thereafter, as shown in FIG.18F, an impurity-doped polysilicon film 346 2 having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the SiO 2 film 142 2 having the opening 143 3 by CVD or LPCVD The deposition of the polysilicon film 346 1 and the SiO 2 film 142 2 , and the formation of the opening 143 3 may be repetitively performed, if desired. Thereafter, as shown in FIG.18G, the polysilicon film 346 2 , the SiO 2 film 142 2 and the polysilicon films 346 1 and 24 6 are subjected to the patterning process by RIE. Thereafter, remaining portions of the SiO 2 films 142 1 and 142 2 are completely removed by isotropic etching in which a liquid containing HF is used. Thereby, there is formed the storage electrode 146 having the elevational cross section of FIG.18H which has convex portions and recess portions. As illustrated, a gap 84 1 is formed between the insulating film 15 and the lower polysilicon films consisting of the films 246 and 3461 so as to surround the storage electrode 146. Also, a gap 842 is formed between the adjacent upper and lower films so as to surround the storage electrode 146. In the etching step, the gate electrodes WL1 and WL2 made of Si 3 N 4 are not etched. Then, the exposed surface of the storage electrode 146 is subjected to the thermal oxidation process, and thereby, as shown in FIG.22I, a dielectric film 147 is formed around the storage electrode 146. Thereafter, an impurity-doped polysilicon film 148 is deposited on the entire surface of the substrate shown in FIG.18I, and is then subjected to the patterning step. Finally, the insulating film 119 and the bit line 120 is formed. FIGS.19A and 19B are views for explaining an additional advantage obtained by the methods of the present invention. A symbol X1 denotes one film of the storage capacitor, and a symbol X2 denotes a central portion thereof. FIG.19A is with respect to the DRAM device of Fig.4, and FIG.19B is with respect to the DRAMs produced by the methods of the present invention. In the DRAM device of Fig.4, the grooves 16c are formed by etching the n + -type polysilicon films. Therefore, distances a , b , c and d between ends of the film and ends of the central portion are necessarily equal to each other. That is, a = b = c = d . On the other hand, the shape of the film of the storage electrode of the present invention may be changed, depending on the patterning process and a position of the opening for establishing the connections between the films of the storage electrode. Therefore, arbitrary distances a , b , c and d are obtainable. That is, a ≠ b ≠ c ≠ d . This advantage can also be provided by a method which is described below. Additionally, the value of X2 of FIG.19B may be made smaller than that of X2 for the case of FIG.19A. That is, a larger capacitance of the storage capacitor can be obtained. Moreover, the gap can be formed by completely removing the SiO 2 films and therefore the depths of the gaps can be controlled with a high accuracy. A description is given of a method in accordance with the present invention by referring to FIG.20, 21 and 22A through 22G. One of the essential features of this method is that storage capacitors of adjacent DRAM cells are formed to partially overlap with each other. The resulting structure has an advantageous effect of preventing the bit line from being disconnected between adjacent word lines. As described before, the polysilicon film of the storage capacitor extends above the word lines which are surrounded by the insulating film. Therefore, a stepped portion between the adjacent word lines would be formed in a layer structure containing an insulating film, and a bit line. The stepped portion becomes greater as the storage capacitor is formed by an increased number of polysilicon films. Such a stepped portion may cause the disconnection of the bit line. The present method can effectively prevent the occurrence of the undesirable stepped portion. FIG.20 is a plan view of an essential part of a DRAM produced by the present method, and FIG.21 is an elevational cross sectional view taken along a line XXVII-XXVII shown in FIG.20. As shown in these figures, a polysilicon film 356a extending above the word line WL2 of a storage electrode consisting of the polysilicon film 356a and another polysilicon film 366a, overlaps, through an opposed electrode 158, with a polysilicon film 366b extending above a word line WL3 of a storage electrode which is adjacent to the former storage capacitor and consists of the polysilicon film 366b and another polysilicon film 356b. With this structure, the occurrence of a stepped portion of a bit line 120 extending above the two cells can be prevented. The structure of FIGS.20 and 21 is produced by the following process described below with reference to FIGS.22A through 22G. Referring to FIG.22A, a surface of the Si substrate 11 is subjected to the thermal oxidation process by the local oxidation technique, and thereby the field oxidation film 21 having a thickness of approximately 500 nm (5,000 [Å]) is formed. Next, a gate oxidation film 21 having a thickness of approximately 20 nm (200 [Å]) is formed by subjecting the Si substrate 11 by the thermal oxidation process. Then a polysilicon film having a thickness of approximately 300 nm (3,000 [Å]) is grown on the entire surface of the Si substrate 11 by CVD or LPCVD. In order to obtain the polysilicon film of low resistance, a phosphorus ion is diffused into the polysilicon film. Thereafter, the polysilicon film of low resistance is subjected to the patterning process, and thereby gate electrodes (word lines) WL1 through WL4 are formed as shown in FIG.22A. Then, an As + ion is injected into the Si substrate 11 with an impurity concentration of approximately 1 x 10 15 [cm -2 ] and an energy of 70 [keV]. In this step, the word lines WL1 through WL4 are used as mask films. Thereby, drain regions 13a and 13b and source regions 14a and 14b are formed in the Si substrate 11. Next, as shown in FIG.22B, a Si 3 N 4 film 15 and a SiO 2 film 152 are successively grown in this order by CVD or LPCVD. The Si 3 N 4 film 15 may have a thickness of approximately 100 nm (1,000 [Å]), and the SiO 2 film 152 may have a thickness of approximately 100 nm (1,000 [Å]). Then, as shown in FIG.22B, contact holes 163a and 163b are formed by the conventional photolithography technique so that the drain regions 13a and 13b become exposed. Thereafter, a polysilicon film having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the Si substrate of FIG.22B by CVD or LPCVD. Then an As + ion is injected into the polysilicon film with an impurity concentration of 1 x 10 15 [cm -2 ] and an energy of 50 [keV] to obtain the polysilicon film of low resistance. Then the polysilicon film is subjected to the patterning process, and thereby a lower storage electrode film 356a and 356b are formed as shown in FIG.22C. Then, a SiO 2 film having a thickness of approximately 100 nm (1,000 [Å]) is deposited on the entire surface of the Si substrate 11 of FIG.22C by CVD or LPCVD. Although a material of the film is not limited to the SiO 2 film, it is necessary to use a material which can be selectively removed so that the polysilicon film can remain without being etched, because it is to be selectively removed at the later step. Then, the SiO 2 film is subjected to the patterning process so that there can be formed contact holes through which the lower storage electrode films 356a and 356b are exposed. Subsequently, a polysilicon film of a thickness of approximately 100 nm (1,000 [Å]) is deposed on the entire surface of FIG.22D by CVD or LPCVD. Then, an As + ion having is injected into the polysilicon film with an impurity concentration of 1 x 10 15 [cm -2 ] and an energy of 50 [keV] by CVD or LPCVD. Thereafter, the polysilicon film is subjected to the patterning process and thereby upper storage electrode films 366a and 366b are formed as shown in FIG.22E. Then, as shown in FIG.22F, the Si substrate 11 of FIG.22E is placed into an etching liquid capable of selectively etching a SiO 2 film, a HF liquid, for example, so that the SiO2 films 152 and 162 are completely removed by isotropic etching. At this step, the word lines WL1 through WL4 are not etched because they are covered with the Si 3 N 4 film 15. Thereafter, a dielectric film consisting of a SiO 2 film having a thickness of approximately 10 nm (100 [Å]) is formed on the surface of each of the polysilicon films 356a, 356b, 366a and 366b of the storage electrodes. The formation of the SiO 2 film is performed by the thermal oxidation process. In the thermal oxidation process, an uniform SiO 2 film can be formed even on opposing surfaces of the storage electrode films 356a and 366a; 356b and 366b around each of the storage electrodes, with an oxidation atmosphere kept at a low pressure equal to or lower than 1330 Pa (10 [torr]). In place of use of the SiO 2 film, it is possible to grow a Si 3 N 4 film serving as the dielectric film formed on the surface of the storage electrode by CVD or LPCVD. Next, in order to form an opposed electrode 158, a polysilicon film of a thickness of approximately 200 nm (2,000 [Å]) is grown on the entire surface of the Si substrate 11 shown in FIG.23F by CVD or LPCVD so as to enclose the entire of the storage electrodes films 356a, 356b, 366a and 366b. In the step, it is preferable to carry out the growth of the polysilicon film in a low-pressure atmosphere at a pressure equal to or lower than 1330 Pa (10 [torr]). Under this pressure condition, the polysilicon can be grown even on the surfaces of the storage electrode films opposite to each other through the gaps formed therebetween, so that the gaps can be completely filled with the polysilicon film. In order to obtain the opposed electrode 158 of low resistance, phosphorus is doped into the polysilicon film used for forming the opposed electrode 158 by gas diffusion in which POCl 3 is used as a gate. Then the polysilicon film of low resistance is subjected to the patterning process, and thereby the opposed electrode 158 having the elevational cross section shown in FIG.22G can be obtained. Thereafter the SiO 2 film 119 having a thickness of approximately 200 nm (2,000 [Å]) is grown on the entire surface of the Si substrate 11 of FIG.22G by CVD or LPCVD. Then contact holes through which the source regions 14a and 14b are exposed, and then a polysilicon film having a thickness of approximately 100 nm (1,000 [Å]) is grown on the SiO 2 film 119 having the contact holes. Subsequently, an As + ion is injected into the grown polysilicon film with an impurity concentration of 1 x 10 16 [cm -2 ] and an energy of 50 [keV]. Thereafter, a tungsten silicide (WSi) having a thickness of approximately 200 nm (2,000 [Å]) is grown on the polysilicon film 119 by CVD or LPCVD and is then subjected to the patterning process. Thereby, the bit line 120 is formed. Thereafter, a PSG film 121 of a thickness of approximately 0.5 [µm] is grown on the entire surface of the Si substrate 11, and then Al wiring lines 200a through 200d each having a thickness of approximately 1 [µm] are formed on the PSG film 121. The Al wiring lines 200a through 200d are connected to the corresponding wiring lines WL1 through WL4 at portions (not shown). These connections contribute to low resistances of the word lines. The present method can be applied to the first through third methods. With respect to the second and third methods, the elevationally adjacent polysilicon films of the storage electrode are formed by the same resist film. On the other hand, it is possible that the lower electrode out of the adjacent polysilicon film is first patterned, and then the film is deposited on the patterned polysilicon film, and thereafter the upper polysilicon film formed on the film is patterned. In this case, it is unnecessary to use the same resist film for the adjacent polysilicon films.

Claims: A method of producing a dynamic random access memory device, characterized by the steps of: forming a transfer transistor comprising a pair of first and second impurity diffused regions (13, 14) which are located within an area defined by a field insulating film (12) formed on a substrate (11) and a gate electrode (WL1) being located between said pair of impurity diffused regions (13, 14); forming a first insulating film (15) so as to cover said transfer transistor for insulation; forming a second insulating film (122) on said first insulating film (15), said second film being made of a material different from said first film; forming a first conductive film (226) on said second insulating film (122); forming a first opening (123 1 ) in said first conductive film (226) so that a region being wider than one of said impurity diffused regions (13, 14) of said second insulating film (122) is exposed; forming a second opening (123 2 ) in said first and second insulating films, said one of said first and second impurity diffused regions (13, 14) being exposed through said second opening; depositing a second conductive film (326) on said first conductive film (226), said second insulating film (122) and in said second opening (123 2 ); patterning said first and second conductive films (226, 326) in accordance with a desired size of a storage electrode, so that a storage electrode having a stepped part on an end thereof is formed by said patterned first and second conductive films; removing said second insulating film (122) by isotropic etching; forming a dielectric film (127) on an exposed surface of said patterned first and second conductive films (226, 326); and forming a third conductive film (128) so as to surround said patterned first and second conductive films (226; 326) around which said dielectric film (127) is formed. A method according to claim 1, characterized in that the step of forming said dielectric film (127) is carried out by a thermal oxidation process in which an oxidation atmosphere is set at a low pressure equal to or less than 1330 Pa. A method according to claim 1, characterized in that the step of forming said dielectric film (127) is carried out by depositing a silicon nitride film by low-pressure plasma vapor deposition with a pressure equal to or lower than 1330 Pa. A method according to claim 1, characterized in that the step of forming said third conductive film (128) is carried out by a chemical vapor deposition process in which an atmosphere is set at a low pressure equal to or less than 1330 Pa. A method according to anyone of claims 1-4, characterized in that said first insulating film (15) is a silicon nitride film and said second insulating film (122) is a silicon dioxide film; said first, second and third conductive films (226; 326; 128) are polysilicon films; and the step of removing said second insulating film (122) uses a liquid containing hydrogen fluoride (HF). A method according to anyone of claims 1-4, characterized in that said first insulating film (15) is a silicon dioxide film and said second insulating film (122) is a silicon nitride film; said first, second and third conductive films (226; 326; 128) are polysilicon films; and the step of removing said second insulating film (122) uses a liquid containing phosphoric acid (PH 3 PO 4 ).

Inventors: EMA TAIJI, TAGUCHI MASO, EMA, TAIJI, TAGUCHI, MASO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H01L27
IPC codes: H01L21, H01L27