SIGNAL PROCESSING CIRCUIT

Abstract: A signal processing circuit has a differential circuit (11) for differentiating an analog signal and a comparator circuit (12) for converting the signal output from the differential circuit into a digital signal. The signal processing circuit is characterized by further comprising a delay circuit for delaying the converted digital signal by a predetermined period of time. In the signal processing circuit of the present invention, the analog signal is first differentiated and digitized, and then finally, delayed by the digital delay circuit. With such an arrangement, analog filters can be dispensed with, thus enabling most of the signal processing circuit to be built into the IC circuit, and to be of more simple design.

Description: This invention relates to a signal processing circuit used in detecting peaks of pulse signals read out from a magnetic head of a hard disk device. Many methods exist for removing pseudo peaks --which arise from noise, for example -- from a read-out signal output via the magnetic head of a hard disk device. Typical pseudo peak removal methods are the time domain system, the level-slice system, the minute voltage system, also called the Δ (delta) V system, and the like. In the case of the ΔV system, for example, the true peak level of an original waveform is used as a reference level, with those peaks below the reference level being treated as pseudo peaks and therefore removed. Because this system is free from the problem of the amplitude limit of the original waveform, it has, accordingly, found widespread application, from MFM modulation to RLL modulation. When using the ΔV system, the peak position of the read-out signal from the magnetic head must be delayed a predetermined period of time; conventionally, the read-out signal is subjected to the delay processing in the analog signal mode. A prior signal processing circuit based on the ΔV system, is shown in Fig. 1, while signal waveforms at key points in this circuit are shown in Fig. 2. A read-out signal A from the magnetic head is delayed a predetermined period of time by analog delay circuit 61, which includes an LCR type filter. Signal A then becomes delayed signal B which, in turn, is differentiated by differentiator circuit 62. The resulting differentiated signal C is then supplied to comparator 63, where it is converted into a digital signal D. Finally, signal E corresponding to the write data is reproduced by use of digital signal D. Using an analog circuit for signal delay presents the following problems: In order to expand the frequency range in which the signal can be read out, it is necessary to provide a large number of filters in the signal processing circuit. When a large number of filters is provided in the signal processing circuit, it is necessary to provide a large number of external LCR elements on the wiring board, leading to the signal processing circuit of undesirably large size. As is clear from the above, in the signal processing circuit based on the ΔV system for pseudo peak removal, the entire circuitry cannot be fabricated into a circuit with a high packing density. This creates many problems, such as higher manufacturing costs, a large number of required external elements, a large chip area occupied by the signal processing circuit, and difficult in design work of the circuit. Prior art document Patent Abstracts of Japan, Vol. 7, No. 262, discloses a reading system of a magnetic recording device. In this reading system, an analog waveform read by a reproducing head is passed through an amplifier, differentiated at a section, and then inputted to a zero-cross detector. The output of the differentiating section is put in to level comparators, whose outputs are put in to an edge detector through a first flip-flop. The edge detector sends a signal to a second flip-flop when the tristate level variation discriminated by the positive and negative threshold values of the differentiated waveform occurs successively. The peak signal of the zero-cross detector is inputted to the second flip-flop through a delay circuit. The second flip-flop detects only read data corresponding to the position of a correct peak securely and erroneous read data due to a pseudo peak is removed securely. Thus, reading operation with accurate and stable wide-range recording density and a readout speed is carried out. Further, prior art document JP-A-61-168 106 discloses a signal processing circuit comprising differentiating means, comparing means, and delay means. The differentiating means differentiate complementary analog signals to generate differentiated complementary analog signals. The comparing means compare the differentiated complementary analog signals with each other to generate complementary pulse signals indicative of a comparison result of said differentiated complementary analog signals, the pulse signals being changed in synchronism with the event of equal magnitude of the differentiated complementary analog signals. The delay means delay the pulse signals by a predetermined period of time. It is an object of this invention to provide a signal processing circuit based on the ΔV system, which can be assembled into an integrated circuit with a high packing density, and which can provide an easy circuit design. To solve this object, the present invention provides a signal processing circuit as specified in claim 1. An analog signal input into the signal processing circuit is first differentiated, than digitized, and, finally, is delayed by the digital delay means. Since this arrangement dispenses with need for analog filters, most of the signal processing circuit can therefore be built into the IC circuit; thus, a signal processing circuit of simpler design can be realized. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a block diagram of a prior signal processing circuit; Fig. 2 shows signal charts of the Fig. 1 signal processing circuit; Fig. 3 shows a block diagram of a signal processing circuit according to one embodiment of this invention; Fig. 4 shows signal charts of the Fig. 3 circuit; Fig. 5 is a circuit diagram of a digital delay circuit incorporated in the signal processing circuit of Fig. 3; and Fig. 6 shows signal charts of the Fig. 5 circuit. A preferred embodiment of the invention will be described, with reference to the accompanying drawings. A signal processing circuit according to an embodiment of this invention is shown in Fig. 3, with signal waveforms at key points in this circuit being shown in Fig. 4. A read-out signal a from the magnetic head is differentiated by differentiator circuit 11. The resulting differentiated signal b is supplied to differential type comparator 12, where it is converted into a digital signal c . Finally, signal d corresponding to the write data is reproduced using this digital signal c . Fig. 5 shows a detailed circuit diagram of a delay circuit used in the signal processing circuit described above. The signals input into this delay circuit, i.e., the output signals from comparator 12, are complementary signals INA and INB. Signal INA is supplied to the base of NPN transistor Q1, and signal INB, to the base of NPN transistor Q2. Transistors Q1 and Q2 are interconnected at their emitters and form a differential amplifier 20 for amplifying signals INA and INB. Located between and connected to the collectors of transistors Q1 and Q2 is capacitor C0. Differential amplifier 20 charges and discharges capacitor C0 according to the levels of input signals INA and INB. Bias voltage source VB1, resistor R1, NPN transistors Q3 and Q4, and PNP transistors Q5 to Q10 make up constant current source 30. Circuit 30 supplies a constant current I0 to the emitters of transistors Q1 and Q2, and a constant current I0/2 to transistors Q8 and Q7, the collectors of which are connected to the respective terminals of capacitor C0. The values of currents I0 and I0/2 can be adjusted by varying the resistance value of resistor R1. Bias voltage source VB2, resistor R2, NPN transistors Q11, Q12, and Q13, PNP transistors Q14 to Q18, and constant current sources I1 and I2 make up clamp circuit 40. Clamp circuit 40 limits the voltage across capacitor C0 to the voltage drop ΔV across resistor R2, which is caused by constant current I2. Resistors R3 and R4, NPN transistors Q19 to Q22, and constant current sources I3 to I5 make up a differential type converter 50. Converter 50 amplifies the voltage across capacitor C0, waveshapes it, and produces complementary signals OUTA and OUTB. It should be noted that the circuit shown in Fig. 5, except for variable resistor R1 thereof, can entirely be formed in a form of an integrated circuit. The base of NPN transistor Q1 receives input signal INA, and the base of NPN transistor Q2 receives input signal INB. The collector of NPN transistor Q1 is connected to the collector of PNP transistor Q8, the emitter of which is connected to positive power supply Vcc. The collector of NPN transistor Q2 is connected to the collector of PNP transistor Q7, the emitter of which is connected to positive power supply Vcc. The emitter of NPN transistor Q1 is connected to the emitter of NPN transistor Q2. The node of the emitters of NPN transistors Q1 and Q2 is connected to the collector of NPN transistor Q3, the emitter of transistor Q3 being connected to the ground via variable resistor R1. The base of NPN transistor Q3 is connected to the base of NPN transistor Q4. The bases of NPN transistors Q3 and Q4 are connected to the positive polarity terminal of bias voltage supply VB1. The negative polarity terminal of bias voltage supply VB1 is connected to the ground. The emitter of NPN transistor Q4 is connected to the ground via variable resistor R1, and its collector is connected to the collector of PNP transistor Q5. The emitter of PNP transistor Q5 is connected to positive power supply Vcc. The base of PNP transistor Q6 is connected to the collector of NPN transistor Q4, its emitter is connected to the base of PNP transistor Q5, and its collector is connected to the ground. The collector of NPN transistor Q1 is also connected to the emitter of NPN transistor Q13, and the collector of NPN transistor Q2 is also connected to the emitter of NPN transistor Q12. The collectors of NPN transistors Q12 and Q13 are connected to positive power supply Vcc, the bases of transistors Q12 and Q13 being connected to the emitter of PNP transistor Q18. The collector of PNP transistor Q18 is connected to the ground. The emitter of PNP transistor Q18 is connected to the collector of PNP transistor Q9, the emitter of which is connected to positive power supply Vcc. The base of PNP transistor Q18 is connected to the ground via current source I2, as well as to the emitter of NPN transistor Q11, via resistor R2. The collector of NPN transistor Q11 is connected to positive power supply Vcc, and its base is connected to positive power supply Vcc via current source I1. The base of NPN transistor Q11 is also connected to the emitter of PNP transistor Q17. The collector of transistor Q17 is connected to the ground, and its base is connected to the collector of PNP transistor Q10, the emitter of which is connected to positive power supply Vcc. The collector of PNP transistor Q10 is also connected to the emitter of PNP transistor Q16, the collector of which is connected to the ground, and the base of which is connected to the positive terminal of bias voltage supply VB2 via the bases of PNP transistors Q14 and Q15. The negative terminal of bias voltage supply VB2 is connected to the ground. The collectors of PNP transistors Q14 and Q15 are connected to the ground. The emitter of PNP transistor Q14 is connected to the base of NPN transistor Q19, and the emitter of PNP transistor Q15 is connected to the base of NPN transistor Q20. The collectors of NPN transistors Q19 and Q20 are connected to positive power supply Vcc. The emitter of NPN transistor Q19 is connected to the ground via current source I3, and the emitter of NPN transistor Q20 is connected to the ground via current source I4. The emitters of NPN transistor Q19, Q20 is also connected to the bases of NPN transistors Q21 and Q22 respectively. The collector of NPN transistor Q21 is connected to positive power supply Vcc via resistor R3, and the collector of NPN transistor Q22 is connected to positive power supply Vcc via resistor R4. The emitters of NPN transistors Q21 and Q22 are connected to the ground via common current source I5. The collector of NPN transistor Q22 forms an output terminal for outputting signal OUTA, and the collector of NPN transistor Q21 forms an output terminal for out-putting signal OUTB. The bases of PNP transistors Q5, Q7, Q8, Q9, and Q10 are connected one another. Capacitor C0 is inserted between the collector of NPN transistor Q1 and the collector of NPN transistor Q2 and connected thereto. The operation of the Fig. 5 circuit will now be described, with reference to the signal charts of Fig. 6. When input signal INA is logical low, and input signal INB is logical high, transistor Q1 of differential amplifier 20 is turned off, while transistor Q2 is turned on. As a result, collector current I0 flows through transistor Q2. Capacitor C0 is charged by the constant current I0/2 flowing through transistor Q8. In turn, voltage VC1 at the terminal of capacitor C0, which is connected to the collector of transistor Q1 begins to rise. Voltage VC2 at the terminal of capacitor C0, which is connected to the collector of transistor Q2 begins to fall. Finally, terminal voltages VC1 and VC2 are clamped by clamp circuit 40 at the potentials of logical high and logical low, respectively, and are given by VC1 = VB2 + VBE15 (1) VC2 = VB2 + VBE16 + VBE17 - VBE11 + ΔV + VBE18 - VBE12 (2) where VBE11, VBE12, VBE15, VBE16, VBE17, and VBE18 are respectively the base-emitter voltages of transistors Q11, Q12, and Q15 to Q18, and ΔV is the voltage drop across resistor R2, caused by constant current I2. Assuming that pairs of transistors Q15 and Q16, Q17 and Q18, and Q11 and Q12 each have the same characteristics, and that constant current sources I1 and I2 also have the same characteristics, the voltage difference VC1 - VC2 across capacitor C0 when the clamp circuit operates is expressed as VC1 - VC2 = ΔV (3) The clamp voltage across capacitor C0 is determined by only the values of resistor R2 and constant current I2. When input signal INA is logical high, and input signal INB is logical low, transistor Q1 of differential amplifier 20 is turned on, while transistor Q2 is turned off. As result, collector current I0 flows through transistor Q1. Capacitor C0 is charged by the constant current I0/2 flowing through transistor Q7. In turn, voltage VC1 at the terminal of capacitor C0, which is connected to the collector of transistor Q1 begins to rise, and voltage VC2 at the terminal of capacitor C0, which is connected to the collector of transistor Q2 begins to fall. Finally, terminal voltages VC1 and VC2 are clamped by clamp circuit 40 at the potentials of logical high and logical low, as given by equations (1) and (2), respectively. Subsequently, every time input signals INA and INB change between the logical high level and the logical low level, the levels of terminal voltages VC1 and VC2 alternately fluctuate, each within the difference ΔV. Comparator 50 inverts the logical states of output signals OUTA and OUTB when the terminal voltages VC1 and VC2 of capacitor C0 coincide with each other. Since the voltage across capacitor is ΔV, charge quantity g of capacitor C0 when it is charged is given by q = C0·ΔV (4) Capacitor C0 is charged by the current I0/2 during period T which starts when terminal voltages VC1 and VC2 change and which ends when those voltages are equal. The charge quantity g of capacitor C0, when capacitor C0 is charged during period T, is given by From the equations (4) and (5), the equation T = (2C0/I0)ΔV (6) is obtained. The period T in the above equation (6) is the time delay of the output signal of the delay circuit to the input signals INA and INB, and is a function of I0 and ΔV. Since it is technically easy to make factors I0 and ΔV independent on temperature variation, the time delay T can be kept constant. To set the time delay T to a desired value, it is only needed to use external resistor R1 of an appropriate resistance and constant current I0 of an appropriate current. Generally, a pulse delay circuit cannot delay the input signal exceeding its 1/2 pulse width of the input signal. Therefore, when the delay exceeding the 1/2 pulse width of the input signal is required for a particular use, a plurality of the delay circuits shown in Fig. 5 must be connected in cascade fashion. Since the signal processing circuit of Fig. 3, uses a digital -- as opposed to an analog -- delay circuit to perform signal delay, no analog filters are then required, unlike the prior signal processing circuit. This makes it possible for the entire signal processing circuit, with the exception of variable resistor R1, to be fabricated in a one-chip manner. The effects of this embodiment are a significant, and desirable, decrease in the area of the wiring board taken up by the signal processing circuit, and a more simplified circuit design. As can be seen from the foregoing description, according to this invention, a signal processing circuit based on the ΔV system is provided, which can be built into the IC circuit and is simple in design.

Claims: A signal processing circuit, comprising: differentiating means (11), comparing means (12), and pulse shaping means (13), said differentiating means (11) differentiating complementary analog signals to generate differentiated complementary analog signals; said comparing means (12) comparing the differentiated complementary analog signals with each other to generate complementary pulse signals having a level indicative of the comparison result of said differentiated complementary analog signals, the pulse edges being in synchronism with every occurrence of equal magnitudes of said differentiated complementary analog signals, characterized in that said pulse shaping means (Q1, Q2, Q7, Q8, C0) convert the edges of said complementary pulse signals to complementary ramp shaped waveforms, and further comparing means (Q19, Q20, Q21, Q22) reshape said complementary ramp shaped waveforms to complementary pulse signals, thereby suppressing pulses shorter than a predetermined period of time. The signal processing circuit according to claim 1, characterized in that said pulse shaping means includes first and second transistors (Q1, Q2) having emitters which are connected together, and bases which receive said complementary pulse signals, a first constant current source (Q3) connected to said emitters of said first and second transistors (Q1, Q2), said first constant current source (Q3) feeding a first constant current (I0), a capacitor (C0) connected between the collectors of said first and second transistors (Q1, Q2), second and third constant current sources (Q7, Q8) connected to the collectors of said first and second transistors (Q1, Q2) and supplying constant currents having values which are 1/2 of the constant current of said first constant current source, clamp means (40) for clamping the potential difference across said capacitor (C0) to below a predetermined value, and a differential amplifier means (50) for amplifying a potential difference between the ends of said capacitor (c0). The signal processing circuit according to claim 1, characterized in that said clamp means (40) includes a resistor (R2) and a constant current source (I2) supplying a constant current to said resistor (R2).

Inventors: SHIRAMATSU, TOSHIO C/O PATENT DIVISION, TSUZUKI, MITSUO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: G11B20
IPC codes: G11B20, G11B5