Time base correctors for image signals

Abstract: A time base corrector converts an analog input PAL image signal including a certain time base error into digital form and then stores it in a memory (13) by using a write clock signal derived from the input PAL image signal including the time base error. The stored signal is read out from the memory (13) by a reference readout clock signal to eliminate the time base error, and a reference colour burst signal is added to it in an adder (22). The time base corrector extracts a colour subcarrier signal (C′) from the input PAL image signal by means of a low pass filter (2), samples the colour subcarrier signal by using a first clock signal (CK) in a manner such that U-axis data and V-axis data of the colour subcarrier signal are generated independently of each other, compares by means of an exclusive -OR gate (19) the polarity of the V-axis data of the colour burst of the sampled colour subcarrier signal with the polarity of the V-axis data of the reference colour burst signal, and selectively inverts in a V-axis inverting circuit (18) the polarity of the V-axis data of the colour burst of the sampled colour subcarrier signal on the basis of the comparison result.

Description: This invention relates to time base correctors for correcting time base errors of PAL colour image signals. A time base corrector (hereinafter sometimes referred to simply as a "TBC") as described in US Patent No. US-A-4258384 has been proposed for correcting the time base error of an image signal reproduced by a video tape recorder (VTR). The previously-proposed TBC adds a colour burst signal of a reference colour image signal to a colour image signal whose time base error has been corrected. The V-axis signal component of the colour subcarrier signal of the PAL image signal has its phase inverted at every line. Corresponding to this phase inversion, the phase of the colour burst signal alternates between +135° and -135° at every line. Therefore, when a colour burst signal of a reference colour image signal is added to a PAL colour image signal whose time base error has been corrected, it is necessary to invert the polarity of the V-axis signal component of the colour subcarrier signal in accordance with the phase alternation between +135° and -135° of the colour burst signal to be added to the colour burst signal of the reference colour image signal. For this purpose, the TBC for the PAL system may be provided with a circuit for inverting the polarity of the colour subcarrier signal in such a manner that it is coincident with the phase of the colour burst signal of the reference colour image signal. However, incorporating such a TBC in a VTR complicates the VTR circuitry. US Patent No. US-A-3 996 605 discloses an example of such a TBC which includes the features of the pre-characterising portion of claim 1. In accordance with the present invention there is provided a time base corrector for correcting time base errors in an analog input PAL image signal which includes a luminance signal and a colour subcarrier signal having a colour burst in odd-numbered and even-numbered lines and U-axis data and V-axis data, the time base corrector comprising: a first extractor for extracting said luminance signal from said analog input PAL image signal; a first analog-to-digital converter for converting said luminance signal to a first digital signal; a memory for storing said first digital signal; a clock generator for generating a first clock signal; a memory controller responsive to said first clock signal for generating a write clock signal controlling writing of said first digital signal into said memory and for generating a reference readout signal controlling readout of said first digital signal from said memory; an adder for adding a reference colour burst signal having at least V-axis data to said first digital signal read out from said memory; and a second extractor for extracting said colour subcarrier signal from said analog input PAL image signal; characterized by: a sampler for sampling said colour subcarrier signal by the use of said first clock signal in a manner such that said U-axis data and said V-axis data of said colour subcarrier signal are generated independently of each other; a comparator for comparing the polarity of said V-axis data of the colour subcarrier signal with the polarity of said V-axis data of said reference colour burst signal; a V-axis inverter, arranged to receive the sampled colour subcarrier signal and responsive to said comparator, for selectively inverting the polarity of said V-axis data of said colour subcarrier signal; wherein the write clock signal is operable to effect storing in said memory of the colour subcarrier signal of which said V-axis data has been selectively inverted by said inverter. A preferred embodiment of the present invention, to be described in greater detail hereinafter, provides a time base corrector which corrects the time base error of a PAL colour image signal while simplifying the circuitry for achieving coincidence between the polarity of V-axis data of the colour burst of the colour subcarrier and the polarity of the V-axis data of a reference colour burst. The preferred time base corrector facilitates extraction of V-axis data of the colour burst of the colour subcarrier, is of simple construction, and extracts the V-axis data from the colour burst as well as inverting the polarity thereof. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a circuit block diagram of a time base corrector according to a preferred embodiment of the present invention; Figure 2 is a circuit block diagram of a V-axis inverting circuit in the time base corrector of Figure 1; Figure 3 is a circuit block diagram of a sampling phase detecting circuit in the time base corrector of Figure 1; Figures 4A to 4D are charts showing waveforms of the colour burst of the PAL colour image signal in four successive lines; Figures 5A to 5C are diagrams showing the relationship between the phase of a sampling clock and the U- and V-axes of the PAL colour image signal; and Figures 6A, 6B, 6C to 6F, and 6C′ to 6F′ are timing charts used for explaining the operation of the sampling phase detecting circuit of Figure 3. Figure 1 shows an input terminal T₁ supplied with an analog PAL colour image signal reproduced by a rotary head of a video tape recorder (VTR) (not shown). A colour subcarrier signal is included in the reproduced colour image signal. The reproduced colour image signal is supplied to both a high pass filter (HPF) 1 and a low pass filter (LPF) 2 wherein it is respectively separated into an FM-modulated luminance signal and a low-band-converted colour subcarrier signal C′. The FM-modulated luminance signal is demodulated by an FM demodulating circuit 3, and the luminance signal (hereinafter sometimes referred to as the "Y signal") thus demodulated is supplied to a first analog-to-digital (A/D) converter 5, a clock generating circuit 4, and a burst flag forming circuit 29. The low-band-converted colour subcarrier signal C′ from the LPF 2 is supplied to a second A/D converter 6. The first and second A/D converters 5 and 6 are supplied with a first clock signal CK generated by the clock generating circuit 4. The clock signal CK has a frequency of 4fsc, which is four times greater than the frequency fsc of the colour subcarrier signal. The colour subcarrier signal is synchronised with a horizontal synchronising signal (including jitter or time base error) of the Y signal. The A/D converters 5 and 6 respectively convert the demodulated luminance signal Y and the low-band-converted colour subcarrier signal C′ to digital signals. The luminance signal digitally converted by the first A/D converter 5 is supplied to a first adder circuit 10 through a delay circuit 7. The first adder circuit 10 is also supplied with a digital colour subcarrier signal, the phase of the V-axis component of which is controlled as described below. The adder 10 adds this modified digital colour subcarrier signal to the digital luminance signal D-Y from the delay circuit 7. The output of the first adder circuit 10, which represents this addition, is stored in a time base corrector (TBC) memory circuit 13. Writing a digital image signal into and reading the signal out of the TBC memory circuit 13 is controlled by a memory controller 12. The memory controller 12 is supplied with the first clock signal CK having the frequency of 4fsc and with a synchronising signal and a burst signal from a synchronising signal generating circuit 16, which is supplied with an image signal (black burst) through an input terminal T₂. The digital image signal D-YC read out from the TBC memory circuit 13 is reconverted to an analog signal by a digital-to-analog (D/A) converter 17 and processed by an LPF 20 to derive the PAL colour image signal YC which is then supplied to a second adder circuit 22 wherein the synchronising signal and the burst signal from the synchronising signal generating circuit 16 are added to the PAL colour image signal YC. The PAL colour image signal YC thus processed is supplied by the second adder circuit 22 to an output terminal T₃. A digital frequency converting signal generating circuit 9 and a sampling phase detecting circuit 14 are both supplied with the first clock signal CK of 4fsc from the clock generating circuit 4. The phase of the digital frequency converting signal from the digital frequency converting signal generating circuit 9 is controlled by a control signal P c supplied thereto from the sampling phase detecting circuit 14. The sampling phase detecting circuit 14 is also supplied with a burst flag signal BF formed by the burst flag forming circuit 29. The low-band-converted digital colour subcarrier signal D-C′ produced by the second A/D converter 6 is supplied to a digital multiplying circuit 8 in which it is multiplied by the digital frequency converting signal produced by the digital frequency converting signal generating circuit 9. The output signal from the digital multiplying circuit 8 is supplied to a band pass filter (BPF) 11 whose central pass-band frequency is 4.43 MHz to produce thereby a high-band digital colour subcarrier signal D-C of 4.43 MHz. The digital colour subcarrier signal D-C from the BPF 11 is supplied to the sampling phase detecting circuit 14 and a V-axis inverting circuit 18. The sampling phase detecting circuit 14 detects whether the phase of a sampling point (angularly near the V-axis) of the colour subcarrier signal D-C digitised by the clock signal CK of 4fsc is coincident with the phase of the U-axis and V-axis or is leading or lagging with respect thereto by checking whether the addition of odd-numbered and even-numbered lines of the digital burst signal at the sampling point is zero, negative or positive. It is possible to determine whether a line is odd-numbered or even-numbered by detecting whether the sampling phase component of the digital burst signal near the V-axis is negative or positive. A second output of the sampling phase detecting circuit 14 is supplied to an input terminal of an exclusive-OR gate 19. The other input terminal of the exclusive-OR gate 19 is supplied, through an input terminal T₄ (see also Figure 2), with a discrimination reference signal REF O/E formed by the memory controller 12 for determining whether any given line is odd-numbered or even-numbered. The output of an exclusive OR gate is "1" if one input is "1" and the other is "0"; the output is "0" if both inputs are "0" or both inputs are "1". The exclusive-OR gate 19 thus functions as a comparator or discriminator for determining whether its two inputs are alike or different. The clock signal CK of the frequency 4fsc is supplied to a 1/2 frequency divider circuit 15, in which it is divided by two. The resulting clock signal having a frequency 2fsc is supplied to the V-axis inverting circuit 18. The V-axis inverting circuit 18 is also supplied with the output signal from the exclusive-OR gate 19 as a control signal. The digital colour subcarrier signal D-C is selectively inverted with respect to its V-axis by the V-axis inverting circuit 18, and the digital colour subcarrier signal formed of the signal components U, V, U, V ... or U, -V, U, -V ... is supplied to the first adder circuit 10. The V-axis inverting circuit 18 will be described in more detail with reference to Figure 2. In Figure 2, a terminal T₇ is supplied with the digital colour subcarrier signal D-C from the BPF 11 (Figure 1) whose carrier frequency is converted to 4.43 MHz. A terminal T₈ is supplied with the clock signal of the frequency 2fsc from the 1/2 frequency divider circuit 15, and a terminal T₉ is supplied with a signal indicative of a value "1". The exclusive-OR gate 19 and the first adder circuit 10 function as explained in connection with Figure 1. The first adder circuit 10 is supplied with the digital luminance signal D-Y from the delay circuit 7 through a terminal T₁₁ and supplies its output to the TBC memory circuit 13 (Figure 1) through a terminal T₁₂. The V-axis inverting circuit 18 includes first and second latch circuits 24 and 25 which are supplied with the digital colour subcarrier signal D-C from the terminal T₇. The first latch circuit 24 latches or extracts U-axis data by using an inverted clock signal of frequency 2fsc. This signal is obtained from an inverter circuit 23 that inverts the clock signal supplied by the 1/2 frequency divider circuit 15 (Figure 1). The first latch circuit 24 supplied its latch output U to a fixed contact b of a first switching circuit 21. The second latch circuit 25 latches or extracts V-axis data using the uninverted clock signal of 2fsc supplied by the 1/2 frequency divider circuit 15 (Figure 1). Its latch output V is inverted by an inverter circuit 26 and then incremented by "1" by a third adder circuit 27. The resulting inverted V-axis data is supplied to a fixed contact c of a second switching circuit 28. A fixed contact b of the second switching circuit 28 is directly supplied with the uninverted output V of the second latch circuit 25. The second switching circuit 28 alternatively outputs positive V-axis data and inverted V-axis data, namely V, -V, V, -V ..., by changing over its movable contact a in response to the output from the exclusive-OR gate 19. Since the output of the second switching circuit 28 is supplied to a fixed contact c of the first switching circuit 21, the first switching circuit 21 supplies as its output a digital colour subcarrier signal formed of the signal components U, V, U, V ... or U, -V, U, -V ... by changing over its movable contact a in response to the clock signal of 2fsc from the terminal T₈. The digital colour subcarrier signal thus formed is supplied to the first adder circuit 10. In the embodiment of the invention described above, the V-axis inversion is accomplished in a simple manner, thereby simplifying the circuitry of a VTR in which the time base corrector is incorporated. The sampling phase detecting circuit 14 of Figure 1 will now be described in detail with reference to Figures 3 to 6. Figure 3 is an overall block diagram of the sampling phase detecting circuit 14. The digital colour subcarrier signal D-C received from the BPF 11 (Figure 1) at a terminal T₁₃ of the sampling phase detecting circuit 14 is supplied to a pedestal level detecting circuit 30 and to a fourth adder circuit 31. The output of the pedestal level detecting circuit 30 is supplied to a negative input of the fourth adder circuit 31 for subtraction from the digital colour subcarrier signal D-C received from the BPF 11. The output of the fourth adder circuit 31 is supplied to a third latch circuit 32, an output X₁, X₃ or X₅ (discussed below) of which is supplied to a fifth adder circuit 33, an output terminal T₁₄, and a fourth latch circuit 34. The signal at the terminal T₁₄ is supplied to the exclusive-OR gate 19. An output X₂, X₄ or X₆ (discussed below) of the fourth latch circuit 34 is supplied to the fifth adder circuit 33 to be added to the output of the third latch circuit 32. The output of the fifth adder circuit 33 is supplied to a fifth latch circuit 35. The output of the fifth latch circuit 35 is supplied to a detecting circuit 36, the output of which is supplied to an up/down counter 37 as a control signal. The output of the up/down counter 37 is delivered as the phase control signal P c to an output terminal T₁₅ through an LPF 38. The phase control signal P c delivered to the output terminal T₁₅ is supplied to the digital frequency converting signal generating circuit 9 shown in Figure 1 for controlling the phase of the digital signal supplied as an output by the digital frequency converting signal generating circuit 9 in such a manner that, measured at the sampling point, the phase of the digital colour subcarrier signal at the output of the digital multiplying circuit 8 is coincident with the phase of the U-axis or V-axis. Figure 3 further shows an input terminal T₁₆ supplied with the first clock signal CK of frequency 4fsc from the clock generating circuit 4 shown in Figure 1. The clock signal CK is supplied to a pulse generating circuit 39 which is also supplied with the burst flag signal BF from the burst flag forming circuit 29 (Figure 1) through an input terminal T₁₇. The output BCK₁ of the pulse generating circuit 39 is supplied to the pedestal level detecting circuit 30. The output BCK₂ of the pulse generating circuit 39 is supplied to the third to fifth latch circuits 32, 34 and 35 and to the up/down counter 37 at its clock terminal CLK through an inverter circuit 40. An understanding of the PAL colour image signal will facilitate an understanding of the operation of the circuit described above. The PAL colour image signal may be represented by the following equation: E Y ′ + E B ′-E Y ′ 2.03 sin ω sc t ± E R ′-E Y ′ 1.14 cos ω sc t where ω sc represents the colour subcarrier angular frequency. The following substitutions may be made for simplicity: E u ′ = E B ′-E Y ′ 2.03 E v ′ = E R ′-E Y ′ 1.14 A colour subcarrier with a phase of 90° is subjected to balanced modulation by E u ′, and a colour subcarrier whose phase alternates between 0° and 180° at every line is subjected to balanced modulation by E v ′. The two modulated signal are added to each other to generate a colour subcarrier signal. The colour subcarrier frequency fsc is offset by 1/4 line from f H and represented by the following equation: fsc = (284 - 1/4) f H + f H /625 The addition of f H /625 (=25 Hz) in equation (4) is a correction for removing dot interference caused by the colour subcarrier in the reproduced image. The phase of the colour burst signal alternates between +135° and -135° with respect to the U-axis at every line. Figures 4A to 4D show waveforms of colour burst signals of the above-mentioned PAL colour subcarrier signal. Figure 4A shows a waveform of a colour burst signal BST o on a first line which is synthesised by colour subcarrier signals SUB -u1 and SUB +v1 whose phases are coincident with those of the -U-axis and +V-axis, respectively. Figure 4B shows a colour burst signal BST e on a second line (following the first line), synthesised by colour subcarrier signals SUB -u2 and SUB -v2 whose phases are coincident with the -U-axis and -V-axis which are shifted by 90° from the -U-axis and +V-axis on the first line. Figure 4C shows a colour burst signal BST o1 on a third line (following the second line), synthesised by colour subcarrier signals SUB -u3 and SUB +v3 whose phases are coincident with the -U-axis and +V-axis which are shifted by 180° from the -U-axis and +V-axis on the first line. Figure 4D shows a fourth colour burst signal BST e1 on a fourth line (following the third line), synthesised by colour subcarrier signals SUB -u4 and SUB -v4 whose phases are coincident with the -U-axis and -V-axis which are shifted by 270° from the -U-axis and +V-axis on the first line. SYNC₁ to SYNC₄ in Figures 4A to 4D designate horizontal synchronising signals. After the first to fourth colour burst signals BST o , BST e , BST o1 and BST e1 have circulated once, they appear repeatedly in the same sequence beginning with the fifth line. When the PAL colour image signal as described above is sampled at a frequency four times the frequency fsc of the colour subcarrier signal, that is, at a frequency of 4fsc, the level and phase of the burst signal corresponding to the degree of deviation in the sampling phase with respect to the U- and V-axes can be represented as shown in Figures 5A, 5B and 5C. In Figures 5A, 5B and 5C, reference letters a and b designate sampling axes (phases) having a phase difference of 90° with respect to each other. Figure 5A shows a case where the sampling axes a and b are respectively coincident with the U- and V-axes; Figure 5B shows a case where they lead by α° with respect to the U- and V-axes; and Figure 5C shows a case where they lag by β° with respect to the U-and V-axes. Reference letters BST o and BST e appear in Figures 5A to 5C designate vectors representing burst signals in odd-numbered and even-numbered lines, respectively having phases of +135° and -135° with respect to the U-axis. In Figure 5A, where the sampling axes a and b are respectively coincident with the U- and V-axes, the resolved vectors (vector components) of the vectors representing the burst signals BST o and BST e on the sampling axis a have the same magnitude and the same direction, while resolved vectors thereof on the sampling axis b have the same magnitude but directions opposite to each other. In the case where the sampling axes a and b lead by α° with respect to the U- and V-axes as shown in Figure 5B, with reference to the resolved vectors or components of the vectors representing the burst signals BST o and BST e on the sampling axis a , the former is smaller than the latter in magnitude and both are the same in direction, while with reference to the resolved vectors thereof on the sampling axis b the former is greater than the latter in magnitude and the directions thereof are opposite to each other. When the sampling axes a and b lag by β° with respect to the U- and V-axes, as shown in Figure 5C, with reference to the resolved vectors of the vectors representing the burst signals BST o and BST e on the sampling axis a , the former is greater than the latter in magnitude and both are in the same direction, whereas, with reference to the resolved vectors thereof on the sampling axis b , the former is smaller than the latter in magnitude, and they are in directions opposite to each other. It will be understood from Figures 5A to 5C that it can be detected whether the sampling phase is coincident with, leads, or lags with respect to the phase of the U- and V-axes by detecting the magnitude and the phase of the components of the burst signal BST (BST o and BST e ) on the sampling axis b which has a phase angularly close to that of the V-axis. It is also possible to detect whether or not the sampling phase is coincident with the phase of the U- and V-axes by detecting the magnitude and the phase of the components of the burst signal BST (BST o and BST e ) on the sampling axis a which has a phase close to that of the U-axis. However, lead and lag in phase cannot be detected in the latter case. Figures 6A and 6B show the operation of the sampling phase detecting circuit 14, which compares the magnitude of the high-band-converted colour burst signal applied by the digital multiplier circuit 8 during odd-numbered and even-numbered lines and detects the phase difference between the signal and the sampling clock CK formed be clock generating circuit 4. The input terminal T₁₃ (Figure 3) of the sampling phase detecting circuit 14 (Figures 1 and 3) is supplied with a high-band-converted digital colour subcarrier signal D-C filtered by the BPF 11 (Figure 1). Figures 6A and 6B show waveforms of PAL colour burst signals BST o and BST e in first and second lines supplied to the input terminal T₁₃. In practice, these signals have been converted to digital signals by the A/D converter 6 and converted to a high band by the digital multiplier 8; however, analog burst signals are illustrated in Figures 6A and 6B for ease of understanding. Figures 6C and 6C′ show the sampling clock signal (first clock signal) CK formed by the clock generating circuit 4 and having the frequency of 4fsc, which is supplied to the input terminal T₁₆ of Figure 3. The digital colour subcarrier signal D-C received at the terminal T₁₃ of the sampling phase detecting circuit 14 is supplied to the pedestal level detecting circuit 30 and to the fourth adder circuit 31. The clock signal CK of frequency 4fsc formed by the clock generating circuit 4 is supplied to the pulse generating circuit 39 by way of the input terminal T₁₆. The pulse generating circuit 39 generates a rectangular wave CK/4 (Figures 6D and 6D′) by frequency-dividing the clock signal CK by four. As shown in Figures 6D and 6D′, the signal CK/4 has a phase lag of 90° with respect to the horizontal synchronising signal at every line. Within a predetermined period in which the pulse generating circuit 39 (Figure 3) is supplied with the burst flag signal BF through the input terminal T₁₇, it twice generates the clock signal BCK₁ (Figures 6E and 6E′) having a frequency of 2fsc for extracting data components of a digital burst signal on the sampling axis b angularly near the V-axis, and supplying the extracted data components to the pedestal level detecting circuit 30. Further, the latch circuits 32, 34 and 35 are supplied with a clock signal BCK₂ (Figures 6F and 6F′) having a frequency of fsc generated from the rectangular signal CK/4. In response to the signal BCK₂, the latch circuits 32, 34 and 35 latch the digital burst signal. The signal BCK₂ is inverted in phase by the inverter circuit 40 and supplied to the up/down counter 37 at its clock terminal. The pedestal level detecting circuit 30 operates as follows. Since the sampling frequency of the clock signal CK (Figures 6C and 6C′) is 4fsc, data X and Y (shown in Figures 6A and 6B) obtained by sampling the burst signal at every other clock signal are vertically symmetrically positioned with respect to a pedestal level PL. Therefore, the pedestal level (a digital value) PL can be obtained by taking out the data X and Y at the rising edge of the clock signal BCK₁ and calculating the average value (X+Y)/2 in the pedestal level detecting circuit 30. The pedestal level thus obtained is latched for a predetermined time and then supplied to the fourth adder circuit 31. The fourth adder circuit 31 subtracts the pedestal level PL from the digital burst signal level D-C passed by the BPF 11. The output of the fourth adder circuit 31 is supplied to the third latch circuit 32 and latched thereby at the rising edge of the clock signal BCK₂ in order to detect digital level data including the positive or negative polarity of the sampling phase (the axis b in Figures 5A to 5C) of the digital burst signal angularly near the V-axis. Figure 6A shows a typical value X₁ of the burst signal in an odd-numbered line of the V-axis latched (extracted) by the clock signal BCK₂ (in practice, as indicated above, it takes a digital value). By the same process as that described above, the level data of the next digital burst signal is latched by the third latch circuit 32. In this case, the data of the digital burst signal in the preceding line has been latched by the fourth latch circuit 34 in response to the clock signal BCK₂. The level data of the digital burst signal in the next line, which in the PAL system is an even-numbered line with a phase difference of 90° with respect to the odd-numbered line, is shown at X₂ in Figure 6B (in practice, it takes a digital value). The data X₁ and X₂ taken from adjacent odd and even lines are added to each other in the fifth adder circuit 33 (Figure 3). If X₁ is equal in absolute value to X₂, the output of the fifth adder circuit 33 is zero, which means that the sampling axis b is coincident with the V-axis, as shown in Figure 5A. When the phase of the sampling clock signal CK shown in Figures 6C and 6C′ deviates by Δ in the direction of an arrow D₁ in Figures 6C and 6C′, the positions of the data X₁ and X₂ are moved to those of the data X₃ and X₄, respectively, and the added value in the fifth adder circuit 33 becomes positive, which means that the sampling axis b deviates by α° anticlockwise from the V-axis as shown in Figure 5B. When the phase of the sampling clock signal CK shown in Figures 6C and 6C′ deviates by - Δ in the direction of an arrow D₂ in Figures 6C and 6C′, the positions of the data X₁ and X₂ are moved to those of the data X₅ and X₆, respectively, and the added value in the fifth adder circuit 33 becomes negative, which means that the sampling axis b deviates by β° clockwise from the V-axis as shown in Figure 5C. The output of the fifth adder circuit 33 is latched in the fifth latch circuit 35 by the clock signal BCK₂. The detecting circuit 36 detects whether the aforementioned addition shows a positive value, a negative value or zero by the use of the output from the fifth latch circuit 35. If it is detected that the addition result is positive or negative, the detecting circuit 36 supplies to the up/down counter 37 a control signal for correcting the phase of the sampling clock signal CK in such a manner that the addition of the data X₁ and X₂ becomes zero; that is, the phase of the digital frequency converting signal is shifted by Δ in the negative direction if the addition shows a positive value, and by Δ in the position direction if the addition shows a negative value. The up-down counter 37 is controlled to be changeably set into one of non-counting, up-counting and down-counting modes on the basis of the control signal from the detecting circuit 36. The counted value is digitally supplied to the LPF 38 and then supplied to the digital frequency converting signal generating circuit 9 (Figure 1) as a feedback signal P c corresponding to a lead or a lag in phase of the sampling point to be used for the phase adjustment. The time base corrector as described above can detect a difference in phase between the sampling signal and the colour burst signal of the PAL colour image signal merely by comparing the magnitudes of the colour burst signals in odd-numbered and even-numbered lines, thereby to provide a simple and highly accurate phase detecting circuit.

Claims: A time base corrector for correcting time base errors in an analog input PAL image signal which includes a luminance signal and a colour subcarrier signal having a colour burst in odd-numbered and even-numbered lines and U-axis data and V-axis data, the time base corrector comprising: a first extractor (1,3) for extracting said luminance signal (Y) from said analog input PAL image signal; a first analog-to-digital converter (5) for converting said luminance signal (Y) to a first digital signal; a memory (13) for storing said first digital signal; a clock generator (4) for generating a first clock signal (CK); a memory controller (12) responsive to said first clock signal (CK) for generating a write clock signal controlling writing of said first digital signal into said memory (13) and for generating a reference readout signal controlling readout of said first digital signal from said memory (13); an adder (22) for adding a reference colour burst signal having at least V-axis data to said first digital signal read out from said memory (13); and a second extractor (2) for extracting said colour subcarrier signal (C′) from said analog input PAL image signal; characterized by: a sampler (6,8,9,11,14) for sampling said colour subcarrier signal (C′) by the use of said first clock signal (CK) in a manner such that said U-axis data and said V-axis data of said colour subcarrier signal are generated independently of each other; a comparator (19) for comparing the polarity of said V-axis data of the colour subcarrier signal with the polarity of said V-axis data of said reference colour burst signal; a V-axis inverter (18), arranged to receive the sampled colour subcarrier signal (D-C) and responsive to said comparator (19), for selectively inverting the polarity of said V-axis data of said colour subcarrier signal; wherein the write clock signal is operable to effect storing in said memory (13) of the colour subcarrier signal of which said V-axis data has been selectively inverted by said inverter (18). A time base corrector according to claim 1, wherein said sampler (6,8,9,11,14) comprises a second analog-to-digital converter (6) for converting said extracting colour subcarrier signal (C′) into a second digital signal (D-C′), a digital frequency converting signal generator (9) responsive to said first clock signal (CK) for generating a frequency converting signal, and a digital multiplier (8) for multiplying said second digital signal (D-C′) by said frequency converting signal. A time base corrector according to claim 1 or claim 2, wherein said sampler (6,8,9,11,14) comprises a phase detector (14) for detecting the phase difference between the first clock signal (CK) and the V-axis by comparing the magnitude of the colour burst in an odd-numbered line (BST o ) with the magnitude of the colour burst in an even-numbered line (BST e ). A time base corrector according to claim 3 as appendent to claim 2, wherein said phase detector (14) is operable to produce a control signal (P c ), said digital frequency converting signal generator (9) being controlled by said control signal (P c ). A time base corrector according to any one of the preceding claims, wherein said V-axis inverter (18) is responsive to a frequency divider (15) which frequency-divides said first clock signal (CK) by two to form a second clock signal (2fsc), and wherein said inverter (18) comprises a latch (25) for extracting said V-axis data (V) from said colour subcarrier signal on the basis of said second clock signal (2fsc), and a data inverter (26,27,28) for selectively inverting the polarity of the V-axis data of the colour subcarrier signal extracted by said latch (25).

Inventors: TATAMI MITSUSHIGE, TATAMI, MITSUSHIGE
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: H04N9
IPC codes: H04N9