Digital signal processor

Abstract: A digital signal processor of a simple circuit configu­ ration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal proces­ sor comprises instruction execution pipeline stages including a stage in which data is read from a data memory (205, 207, 208) and the data is applied to an arithmetic unit (206); an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories (207, 208) and a DMA transfer bus (210) for a write/accumulation stage, an address generating unit (203) capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit (209) for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory (205) for an instruction execution stage.

Description: The present invention relates to a digital signal processor capable of efficiently carrying out the arithmetic or interruption processing mainly of successive signals at a high speed through a small number of steps. Description of the Prior Art Fig. 1 is a block diagram showing the constitution of DSSP1 (Digital Speech Signal Processor 1), namely, an exemplary conventional digital signal processor, "A High-speed VLSI Signal Processor with Normalizing Floating-point Systems", the proceedings of the annual communication Symposium of the Institute of Electronics and Communication Engineers of Japan (IECEJ), 1986, Japan. Shown in Fig. 1 are program counter (PC) 1 internally provided with a stack for instruction address control, an instruction mask ROM 2 storing micro-instructions, an instruction register (IR0) 3 for receiving one microinstruction provided by the instruction mask ROM 2 or one external microinstruction every machine cycle, an instruction register (IR1) 4 for receiving only the bit field requiring decoding included in a microinstruction given to the instruction register (IR0) 3, an instruction decoder 5 for decoding the microinstruction given to the instruction register (IR1) 4, a program bus (P-Bus) 6 for distributing microinstructions to the functional units, a register (BI) 7 which receives immediate data (18-bit width) included in a microinstruction provided on the program bus (P-Bus) 6 and applies the same to a data bus (D-Bus) 8 (18-bit width) for internally transferring data obtained by operation, a register (AM) 9 which receives an address mode instruction of data memory through the program bus (P-Bus) 6, a register (AD) 10 (4w x 16-bit width) for holding address pointer information for generating an indirect address, a page register (PR) 11 (3-bit width) which specifies the page in an external data memory, an address computation unit (AAU) 12 (9-bit width) capable of simultaneously generating three addresses at the maximum, an address register (AR0) 13, an address register (AR1) 14, an address register (AR2) 15, an address selector (RAS) 16, a loop counter (LC) 17, a status register (SR) 18 for indicating the operating mode and status of the processor, a DMA control unit 19 for controlling the direct data transfer between serial I/O ports (SI0/1, SO0/1) 32 and an external data memory, an address register (AR) 20 for holding addresses of 12-bit width to be given to an external data memory, a dual port internal data memory (20-RAM) 21 of 512w x 18 bits capacity capable of simultaneous read and write of two data, a register (DP0) 22 for holding input data of operand, a register (DP1) 23 for holding input data of operator, a multiplier (FMPL) 24 for multiplying the floating point of 12E6 bit format, a register (P) 25 for holding the results of operation of the multiplier (FMPL) 24, a selector 26, a selector 27, a floating-point arithmetic logical operation unit 28 mainly for carrying out the floating-point operation of 12E6 bit format, accumulators (ACC0 to ACC 3) 29 of 4w x 18 bits for holding and accumulating the outputs of the floating-point arithmetic logical operation unit (FALU) 28, a data register (DR) 30 connected to the data bus (D-Bus) 8 to temporarily hold data to be read from and to be written in an external data memory, a read/write control circuit (R/W Cont) 31 for reading data from and writing data in an external data memory, serial I/O ports (SI0/1, SO0/1) 32 for full-duplex two-channel data transfer with external devices, an interrupt control circuit (Int Cont) 33, an external data memory bus control circuit (Bus Cont) 34, a clock control circuit (CLK Cont) 35 for controlling internal timing, and a selector 36. Fig. 2 is a time chart of assistance in explaining the microinstruction execution sequence of the digital signal processor DSSP1 shown in Fig. 1. Shown in Fig. 2 are cycle timing 40 consisting of four phases of clocks, fetch stage timing 41 showing stages of the address output of the program counter (PC) 1 and the microinstruction input of the instruction register (IR0) 3, decode stage timing 42 of decoding the input microinstruction of the instruction register (IR1) 4 by the instruction decoder 5, timing 43 of updating the address computation unit 12 in the decode stage, timing 44 of operation of the floating-point multiplier (FMPL) 24, timing 45 of operation of the floating-point arithmetic logical operation unit (FALU) 28, timing 46 of transferring data through the data bus (D-Bus) 8 between the registers, and timing 47 of reading data from and writing data in the external data memory through the data register (DR) 30. Referring to Fig. 3 showing the respective constructions of microinstructions of 32-bit width per word representing four groups of microinstructions of the digital signal processor DSSP1 of Fig. 1, indicated at 50 is a sequence instruction for controlling instruction processing steps, at 51 is a mode instruction for initializing and setting modes of the status register (SR) 17, the address computation unit (AAU) 12 and the DMA control unit 19, at 52 is an operation instruction mainly for controlling the operation of the floating-point arithmetic logical operation unit (FALU) 28 and parallel data transfer accompanying the operation of the floating-point arithmetic logical operation unit (FALU) 28, and at 53 is a load instruction for loading immediate data on an optional register or a data memory. The operation of the digital data processor (DSSP1) will be described hereinafter, in which the components will be denoted by the abbreviated designation shown in the foregoing description. First the general mode of operation will be described with reference to Fig. 1. In this digital signal processor DSSP1, the P-Bus 6 and the D-Bus 8 are provided individually. The application of the microinstruction to the IR0 3, the transfer of the microinstruction through the P-Bus 6, the decoding of the microinstruction by the instruction decoder 5, and execution of the instruction by the D-Bus 8, the FMPL 24 and the FALU 28 are carried out in parallel through a pipeline process. The D-Bus 8 and all the execution units including the 2P-RAM 21 are of register-base, namely, all the inputs and outputs are connected to the registers. In the timing of access to the registers, outputs are provided at the leading edge of the machine cycle and the outputs are set in the registers at the trailing edge of the machine cycle. The contents of data actually processed is not the contents of data set in the register by the same microinstruction, but the contents of data set in the register by the preceding microinstruction. Such a mode of operation is called as delayed operation. The interior of the arithmetic unit is partitioned into sections by the registers to enable the parallel operation of the sections. For example, the FMPL 24 continually executes the floating-point multiplication once every machine cycle. In applying data to the FMPL 20, the data is set in the DP0 22 and DP1 23 by the preceding microinstruction, and the contents of the P 25 is fetched by the succeeding or later microinstruction to obtain the results of multiplication. While the contents of the P 25 is being fetched, the data is held by the DP0 22, DP1 23 and the P 25. Accordingly, one multiplication operation formerly requiring three microinstructions for data input, multiplication and data output can be carried out by one microinstruction when the process is executed continuously. In this DSSP1, the FMPL 24 and the FALU 28 are connected by the P 25. The FALU is able to accumulate the contents of the P25 in the ACC0 29 to the ACC3 29 to execute one term of product-sum operation which is often used in filtering and the butterfly operation of fast Fourier transform (FFT) in one machine cycle similarly to one pair of a multiplier and accumulator shown in "Packing a signal processor onto a single digital board", Louis Schirm, Electronics, Dec. 20, 1979. For example, the product-sum is calculated by using an expression: where N is an integer not less than 1 (one), and a i and b i are input data. In this processor, three microinstructions for applying data to the DP0 22 and DP1 23, for executing multiplication by the FMPL 24 and for accumulating the results of multiplication set in the P 26 by the FALU 28 in the ACC0 to ACC3 to obtain one term of the product-sum. Naturally, when the operation is carried out continuously, one term of the product-sum can be obtained for one microinstruction. Thus, to obtain one term of the product-sum for one microinstruction, two input data corresponding to the input data a i and b i must be given respectively to the DP0 22 and the DP1 23 every one microinstruction. Accordingly, the 2P-RAM 21 is enabled to supply the two input data, and a bus is provided to transfer the data read from the 20-RAM 21 directly to the DP0 22 and DP1 23 without using the D-Bus 8 to avoid bus contention in the D-Bus 8. The AAU 12 has output means for selectively providing two address data among address data of 9-bit width provided through the AR0 12, AR1 14 and AR2 15 mainly to address the input data of the 2P-RAM 21. The AAU 12 is able to specify three addresses simultaneously at the maximum only in generating addresses for the two input data given thereto from the 2P-RAM 21, and an address for one output data given through the DR 30 and the AR 20 to the external data memory. Each addressing is so-called indirect addressing system using an address pointer internally set in the AAU 12. The AR0 13 is susceptible to increment, modulo, bit reverse, repeat, increment base address and updating of increment, while the AR1 14 and the AR2 15 are susceptible only to simple increment. The AAU 12 is able to perform address operation only in a 9-bit natural binary system. In specifying a 12-bit address in the external data memory, three bits for specifying a memory page are added to the nine bits to specify twelve bits. On the other hand, since the FMPL 24 and the FALU 28 execute operation in a normalized floating-point system of 12E6, all the data for the 2P-RAM 21, the DP0 22, the DP1 23, the ACC0 29 through ACC3 29, the DR 30, the D-Bus 8 and BI 7 are of 18-bit width, and hence the FALU 28 needs a special operation mode for calculating a special address initial value. Accordingly, the data representing the result of operation stored in the AR0 13, the AR1 14, the AR2 15, the AR 20 and the ACC0 29 through the ACC3 29 are not compatible with those data. The DMA control unit 19 controls, independently of the microinstruction, full-duplex 2-channel data transfer between the serial I/O ports SI0/1 32 and SO0/1 32, and the external data memories through the D-Bus 8 and the AR 20 and DR 30. Therefore it is possible that the microinstruction operation controlled by the instruction decoder 5 and the internal resource content with each other. To avoid the contention, the instruction decoder 5 is held inoperative for six machine cycles for every word to interrupt operation according to the microinstruction in transferring data by the DMA control unit 19. After all, the DSSP1 is capable of performing the following operations in parallel within one microinstruction in executing microinstructions. (1) The 9-bit address operation of three kinds at the maximum by the AAU 12. (2) The floating-point multiplication of 12E6 by the FMPL24. (3) The floating-point operation of 12E6 by the FALU 28. (4) Data transfer through the D-Bus 8 and the DR 30 between the external memories. (5) DMA data transfer through the full-duplex 2-channel serial I/O ports SI0/1 32 and SO0/1 32, D-Bus 8 and the DR 30 between the external memories. The microinstruction execution timing of the DSSP1 will be described with reference to Fig. 2. The machine cycle 40 of the DSSP1 is divided into four phases of timing P0 through P3. The nominal machine cycle time is as high as 50 nsec. Accordingly, it is practically difficult to accomplish three operations, namely, reading a microinstruction from the instruction mask ROM 2, decoding the microinstruction by the instruction decoder 5 and execution of the instruction by the internal resources such as the FMPL 24 and the FALU 28, within one machine cycle. Accordingly, the three operations are divided into stages for each machine cycle to form a three-stage pipeline to enable high-speed operation. The following operations are performed in the stages of the three-stage pipeline. (1) Fetch stage 41: A microinstruction address is provided by the PC 1, a microinstruction is read from the instruction mask ROM 2 and the microinstruction is set in the IR0 3. (2) Decode stage 42 and 43: The microinstruction is transferred from the IR0 3 to the IR1 4, the microinstruction is decoded by the instruction decoder 5, the program control mode is set, the microinstruction is transferred from the IR0 3 to the P-Bus 6, and address operation of the AAU 12 through the AM 9 and the AD 10. (3) Execution stage 44, 45, 46 and 47: Operation of data by the FMPL 24 and FALU 28, data transfer through the D-Bus 8, and access to the external data memories through the AR 20 and the DR 30. Thus, the DSSP1 needs three machine cycles to execute one microinstruction. This processor executes one microinstruction equivalently by the pipeline method. Accordingly, the actual execution of the microinstruction is delayed by two machine cycles from the read of the microinstruction from the instruction mask ROM 2. To avoid the timing contention between the internal resources, the internal buses are divided into the P-Bus 6 and the D-Bus 8, and the instruction mask ROM 2 and the 2P-RAM 21 are separated. However, since a branch instruction is executed actually in the decode stage [article (2)], the microinstruction being set in the IR0 3 is executed in the decode stage. That is, an instruction succeeding a branch instruction is executed unconditionally. To avoid such unconditional execution of instructions, the DSSP/1 changes the instruction succeeding the branch instruction automatically into a no-operation instruction (NOP) during the execution of the branch instruction. Such a function is aimed at simplifying microinstruction description, however, one machine cycle is wasted in the branching operation and two machine cycles are wasted in indirect branching operation using the D-Bus 8. Generally, no problem arises in about 80% of unconditional branching operations even if the succeeding instruction is executed when the sequence of instruction description is arranged properly and hence loss of machine cycles can be avoided. However, the DSSP1 is unable to avoid the loss of machine cycles. The microinstruction set of the DSSP1 will be described hereinafter with reference to Fig. 3. A microinstruction set includes only four instructions, namely, a sequence instruction, a mode instruction, an operation instruction and a load instruction. The sequence instruction controls the PC 1 for loop and subroutine call. The mode instruction initializes and sets the modes of the AAU 12, the selector 16, the LC 17, the SR 18 and the DMA control unit 19. The load instruction is used for loading immediate data of 18-bit width on the registers connected to the D-Bus 8 through the BI 7. The objective resources of the foregoing three microinstructions are fixed depending on instruction operation. On the other hand, as regards the operation instruction, all the internal resources capable of parallel operation must be specified directly. Accordingly, the bit length of the instructions is dependent on the bit length of the operation instruction. The DSSP1 uses horizontal microinstructions of 32-bit width. The FMPL 24 is free to run and no instruction is given thereto directly. The operation of the FALU 28 is specified directly by an instruction. For example, operations of the FALU 28 is controlled by the following instructions. (1) Absolute value instruction: |X| (2) Signum function instruction: Sign (Y)·X (3) Addition instruction: X + Y (4) Subtraction instruction: X - Y (5) Maximum value instruction: MAX (X, Y) (6) Minimum value instruction: MIN (X, Y) (7) Fixed-to-floating translation instruction: FLT (X) (8) Floating-to-fixed translation instruction: FIX (X) (9) Shift instruction: R1, L1 to L8 (10) Logic instruction: AND, OR, EOR, NOT (11) Mantissa addition instruction: X M + Y M (12) Characteristic subtraction instruction: X E - Y E However, it is a problem in the DSSP1 that the operation of the DSSP1 is based on floating-point operation, while the DSSP1 carries out logic and address operations on the basis of fixed-point operation. As mentioned above, the floating-point operation and the fixed-point operation are not compatible with each other. In addressing in the memory, for example, on the basis of the results of operation, the instruction (8) must be executed by the FALU 28. Furthermore, since floating-point data is not handled in general data input and output operation, the instruction (7) or the instruction (8) must be executed for every data input or output operation to translate the data. Another problem in the DSSP1 is that bits are always truncated in normalizing floating-point data entailing errors in operation, because the accuracy of operation of the signal processor is limited. However, when floating-point data is normalized only by truncating bits, the absolute value of the results of operation is always smaller than the true value and hence the distribution of the errors is not random. The errors can be regarded as negligibly small by increasing the operation word length. However, since the ordinary signal processor is required to operate at a high speed, increase in the operation word length is limited. Such a problem cannot be ignored particularly in image signal processing in which interframe processing is performed by an IIR digital filter (recursive digital filter), and the DSSP1 must round the results of operation by a logical operation instruction or the like. Furthermore, in a general signal processing algorithm, in most cases, the accuracy of operation is regulated specifically for every unit process, and hence the accuracy of operation does not necessarily coincide with the operation word length of the signal processor. In such a case, the format of the operation data is converted repeatedly by the FALU 28 for every unit process. It is a further problem in the DSSP1 that operation capable of high-speed processing is limited only to product-sum operation. Such a limitation to the mode of operation is not a problem for FFT and FIR filters. However, the recent signal processing algorithm requires for operation to determine the degree of approximation of vectors and , i.e., distance calculation, such as expressed by the following expressions to be carried out at a high processing speed. where a i and b i are the elements of vectors and N is the number of vectors. The DSSP1 is unable to support such an operation and hence such an operation must be decomposed into individual four arithmetic operations for processing. Therefore, three separate operations must be executed to calculate a single term. When each one term is calculated by using the foregoing expressions are nine instructions (9 = 3 x 3) must be provided for one term due to delay, which deteriorates process multitude excessively. Naturally, the process multitude can be increased by sorting in differential + square accumulation by saving interim results by the 2P-RAM 21. However, it is difficult to use the limited space of the data memory effectively and hence it is impossible to process a large quantity of data. Consider, for example, binary tree search as shown in Fig. 4. Suppose that an input vector is set in the 2P-RAM 21, and a reference vector of a tree construction is allocated to the nodes indicated by reference numerals in an external memory as shown in Fig. 5. An evaluation function expressing the degree of approximation between the input vector and the reference vector is absolute differential sum: B = (b₁, b₂, ..., b N )}. A reference vector which provides the least absolute differential sum is selected at each node of the binary tree and finally a reference vector which provides the highest degree of approximation is obtained. In this binary tree search, when the number of the present node is n, the degree of approximation between two reference vectors B at a node 2n+1 and 2n+2 is determined, and then the node number of a reference vector to be compared at the next stage is calculated on the basis of the degree of approximation. To carry out the foregoing binary tree search by the DSSP1, the following instruction steps are necessary. Input data conversion: N + 2 steps Evaluation value calculation for one vector: 9N + 2 steps Evaluation value rounding: About 3 steps Evaluation value comparison: 4 steps Calculation of reference vector address for the next node: About 9 steps Total: 18N + 14 steps 1 stage + N + 2 steps. This total number of steps is approximately nine times the number of steps when the ideal number of steps necessary for evaluation value calculation is 2N and the conversion of address and input data is unnecessary. In such a process, since the same process is not performed successively, it is necessary to be always conscious of the context of instructions. Consequently, process efficiency is deteriorated significantly, a very complex program is necessary and, obviously, a problem arises in the quantity of work necessary for developing softwares. The conventional digital signal processor thus constituted has the following problems. It is necessary to be always conscious of the context of instructions in producing a program, and the same instructions must be executed successively otherwise the process efficiency cannot be improved. Address and data format are not compatible with each other, and hence format needs to be converted for every data, for example, in table look-up. Designed particularly for obtaining product-sum, the arithmetic unit is unable to operate at a high efficiency and a complex program is necessary in operation other than that for obtaining product-sum. The control of the accuracy of data operation is difficult and automatic rounding is impossible. Simultaneous data read from and data read from the data memory for 2-input 1-output operation is impossible, and the efficiency is deteriorated excessively, for example, in vector data processing. Immediate specification of an indirect address mode in the instruction is impossible and hence the process needs to be interrupted for every address mode change. SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the conventional digital signal processor. Accordingly, it is a first object of the present invention to provide a digital signal processor having compatible addresses and data format and capable of performing processes having less repetition of the same operation without deteriorating the efficiency, capable of performing high processes as well as process for product-sum at a high processing speed, capable of efficiently controlling data operating accuracy by simple means, capable of applying vector data to and providing vector data from an arithmetic unit at a high speed, and capable of highly flexible addressing. To achieve the foregoing objects the present invention as claimed has the following constitution, functions and features. A digital signal processor according to the present invention as defined in claim 1 has a five-stage constitution including, in addition to an instruction execution pipeline stage, a stage for reading data from a data memory and applying the data to an arithmetic unit and a stage for writing data provided by the arithmetic unit in the data memory, or accumulating or rounding the data by an accumulator included in the arithmetic unit, a barrel shifter, a multiplier and an arithmetic and logic unit respectively for the execution stage of the five stages are arranged on the same lie in the arithmetic unit, a normalizing barrel shifter for write/accumulation state is connected to the barrel shifter, the multiplier and the arithmetic and logic unit to use the outputs of the normalizing barrel shifter as inputs of an adder for rounding or accumulation or as the outputs of the arithmetic unit, an internal memory comprises two 2-port memories, one of the ports, namely, the read port, of each 2-port memory is connected to the corresponding two internal buses of the arithmetic unit and the other read port, namely, the read/write port, of the same is connected to one of the output bus of the arithmetic unit or to a DMA transfer bus, an address generating unit which generates a 2-input 1-output data memory addresses two-dimensionally and in parallel for the arithmetic unit and a DMA control unit for two-dimensionally transferring data between the internal data memory and an external data memory by using the DMA bus are provided for the instruction execution stage, and the respective data formats of the address generating unit, the DMA control unit and the arithmetic units are compatible with each other. The digital signal processor according to the present invention specifies the operations of the arithmetic unit uniquely and operates on microinstruction codes constructed by combining function codes corresponding to the operations of the arithmetic unit and 2-source and 1-destination control codes corresponding to the normalizing barrel shifter, the two inputs and one output. Thus, the instruction execution pipeline stage of the present invention eliminates most part of a microinstruction description taking into consideration delayed operation and is able to operate efficiently even when the frequency of repetition of execution of the same instruction is not very large. The arithmetic unit of the digital signal processor according to another embodiment of the present invention performs the calculation of one term of product-sum, absolute differential sum and differential square sum, and rounding and shift of data in a time equivalent to one machine cycle. The internal data memory and the bus construction enables execution of 2-input and 1-output data transfer to the arithmetic unit in parallel to arithmetic operation, and the combination of the internal data memory, the bus construction and the address generator for two-dimensional address generation enables efficient operation of vector data. Since the data format of the address generator is compatible with that of the arithmetic unit, data conversion is unnecessary, for example, in table look-up and reference to a dictionary. The DMA control unit performs two-dimensional data reception from the external data memory in parallel with the internal operation to curtail processing time for data input and output effectively. The microinstruction set used by a further embodiment of the present invention specifies the combination of the operations of internal H/W resources uniquely to simplify the program description, and specifies the number of digits of data and source destination address generating formula for each microinstruction to enable the direct control of the digit adjustment for complex data operation and the method of scanning the data memories. Accordingly, the necessity of considering the context of the instruction is limited to the least extent, the program description is simplified, and the program can easily be described in a high level language such as C language. In accordance with a preferred embodiment of the present invention, each of the address generators of the address generating unit stores an initial address through the internal data bus in the address register, stores an index value through the internal data bus in the index register, adds the index modify value, a displacement specified by a microinstruction and the content of the address register, simultaneously updates the content of the address register by using the result of addition and treats the result of addition as a data memory address, and performs two-dimensional or other addressing by a combination of the microinstructions by sequentially assigning each address generator to the address generating mode of every microinstruction. According to a further preferred embodiment, the direct memory access control unit and the direct memory transfer address generating unit sequentially assign the rectangular portion of row k x column 1 (k and 1 are positive integers) of a two-dimensional data address space of m rows and n columns (m and n are positive integers) for addressing the external data memory interface unit, assign addresses to the plurality of 2-port memories in an ascending order from an optional start address and select one of the plurality of 2-port memories by the highest bit of the address or a plurality of bits of the address for two-dimensional data transfer between the 2-port memories and the external data memory, and a transfer direction and the number of data to be transferred are specified by a microinstruction in starting direct memory transfer and the direct memory access control unit informs the sequence control unit of the end of data transfer in ending direct memory transfer to concurrently implement transferring data in a rectangular block of row k x column 1 between the 2-port memory and the external data memory, and internal arithmetic process. The sequence control unit preferably implements conditional branch operation dealing with a plurality of branch operations on one microinstruction by previously storing a plurality of conditions in a special register, previously storing instruction memory addresses to which the program is branched when the branch conditions are met in registers corresponding to the branch conditions, testing the plurality of branch conditions in parallel on a microinstruction, branching the program to one of instruction memory addresses stored in the special registers corresponding to the branch conditions of the highest priority among those which are met, and branching the program to the instruction memory address stored in the special register corresponding to which all the branch conditions are not met. In a still further embodiment of the present invention, the sequence control unit has a loop counter and a repeat counter which are capable of receiving initial values from the internal data buses and providing the contents thereof, the content of the repeat counter is decremented by one for each execution of microinstruction and the same microinstruction is executed repeatedly until the content of the repeat counter is reduced to zero when repeat is assigned by the first microinstruction of repeat operation, the content of the loop counter is decremented by one when loop is assigned by a microinstruction, the program is branched to an instruction memory address specified by the microinstruction when the content of the loop counter is not zero after decrement, and the branch is not completed in order to finish the loop operation when the content of the loop counter is zero after decrement to repeat a single microinstruction or a plurality of microinstructions by a predetermined cycle. In accordance with a further aspect of the invention, the external data memory interface unit divides the external data memory into two parts by using an address previously specified by a microinstruction as a boundary, treats the external data memory as a high-speed memory which accomplishes read/write operation within one machine cycle in addressing one of the two parts of the external data memory, and treats the external data memory as a low-speed memory which stays on standby until an external read/write termination signal is detected in addressing the other part of the external data memory. Preferably, the instruction memory is partly or totally reloadable, microprograms corresponding functional processes are written in the reloadable instruction memory by an external device to enable the digital signal processing to implement complex or diversified processes, and microprograms are provided automatically by an external memory when the microprograms are not written in the instruction memory. The microinstruction can be preferably a microinstruction set consisting of a function code uniquely specifying an operation in each stage of the 5-stage pipeline according to the kind of operation, an input assignment code and an output assignment code individually assigning the address generating mode of the address generator of the address generating unit for every microinstruction at least corresponding to a 2-input 1-output or 1-input 1-output data memory, a resource specifying code specifying the objective data memory or the register of data input/output, the number of shift bits of the normalizing barrel shifter of the execution unit, a test condition code specifying the kind of operation, an immediate data, and a hold condition code. In accordance with a further embodiment of the invention, the external data memory address arbitrary assigns an address for communications between processors, the address is corresponding to an external first-in-first-out memory or an external 2-port memory for communications to connect the same processors or other processors to enable a plurality of processors to implement complex processes at a high processing speed. In a still further embodiment of the present invention, the most significant bit of a data of bits from the least significant bit to be truncated by shift in adjusting the number of bits by shifting toward the least significant bit by the normalizing barrel shifter is used as a carry bit or a borrow bit, the adder has an operating mode in which data round-off operation or data round-off accumulation is executed by performing addition with carry or borrow using the contents of the working registers or zero data, and the operating mode assigned by directly controlling the adder by mode setting or a microinstruction. In accordance with a still further preferred embodiment of the present invention, the arithmetic logic unit of the execution unit decides whether or not a test condition (for example, a condition that two input data are equal to each other) for testing the result of comparison, specified by a microinstruction is met in comparing the sizes of two input data or in testing a special bit in an input data, and sequentially stores the results of decision in one vertical direction of the special shift register for every comparing microinstruction bit by bit, reads the horizontal content of the shift register from the internal data bus, and uses the plurality of results of decision obtained by repeating the comparing microinstructions a plurality of times as a search history code in tree search or for combinational branch operation based on a plurality of conditions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the constitution of a DSSP1 as a first example of a conventional digital signal processor; Fig. 2 is a time chart of assistance in explaining the instruction execution timing of the DSSP1 of Fig. 1; Fig. 3 is an illustration of a microinstruction set to be executed by the DSSP1 of Fig. 1; Fig. 4 is a diagram of assistance in explaining binary tree search operation; Fig. 5 is a diagram showing an example of arrangement of reference vectors of Fig. 4 in a data memory; Fig. 6 is a block diagram of a digital signal processor, in a preferred embodiment, according to the present invention; Fig. 7 is a block diagram of an arithmetic unit incorporated into the digital signal processor of Fig. 6; Fig. 8 is a diagrammatic illustration showing the constitution of an internal data memory incorporated into the digital signal processor of Fig. 6; Fig. 9 is a diagrammatic illustration showing the constitution of an address generator incorporated into the digital signal processor of Fig. 6; Fig. 10 is a time chart of assistance in explaining the timing of operations of the digital signal processor of Fig. 6; and Fig. 11 is a diagram of an example of a microinstruction set to be executed by the digital signal processor of Fig. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described hereinafter with reference to the accompanying drawings. Referring to Fig. 6 showing a digital signal processor, in a first embodiment, according to an embodiment of the present invention, there are shown an external program bus 200 connecting the digital signal processor to an external extension microinstruction memory, an internal writable instruction memory (WCS) 201, a sequence control unit 202 which receives a microinstruction read through the external program bus 200 or from the WCS 201 and performs predetermined control operation in an instruction execution pipeline, an address generating unit 203 which generates 2-input 1-output addresses in parallel for data memories, three internal data buses 204 each having a width of twenty-four bits, for the parallel transfer of the 2-input 1-output data, an external bus 211 connected to an external extension data memory, an external data memory (I/F) 205 for selectively connecting one of the three internal data buses 204 to the external data bus 211, an arithmetic unit 206 which performs predetermined operations, connected to the three internal data buses 204, an internal data memory (M0) 207 having one read port and one read/write port and connected to the internal data buses 204, an internal data memory (M1) 208 similar to the M0 207, connected to the internal data buses 204, a DMA control unit 209 individually provided with an external data memory address generator and an internal data memory address generator, a DMA bus 210 for DMA transfer between the external data bus 211 and M0 207 and M1 208, a reset terminal 212 through which an external reset signal is applied to the sequence control unit 202, and an interrupt terminal 213 to which an external interrupt control signal is applied. Referring to Fig. 7 showing the constitution of the arithmetic unit 206 of Fig. 6, there are shown an X-bus 220 for transferring operand data among the three internal data buses 204, a Y-bus 221 for transferring operand data among the three internal data buses 204, a Z-bus 222 for transferring output data among the three internal data buses 204, a barrel shifter (B-SFT) 223 having a word length of twenty-four bits, for shifting or rotating input data by a predetermined number of bits in one machine cycle, an arithmetic and logic unit (ALU) 224 having a word length of twenty-four bits which performs a predetermined arithmetic and logical operation or absolute difference calculation in one machine cycle, a multiplier (MPY) 225 which performs multiplication of twenty-four bits and provides the result of forty-seven bits of multiplication in one machine cycle, a data pipeline register (DPR0) 226 which holds the output difference of the ALU 224 temporarily and applies the output difference to the square input port of the MPY 225 to calculate a square difference, a multiplexer 227 which selects either the 24-bit output of the B-SFT 223 or the 24-bit output of the ALU 224, and applies the selected output to a data pipeline register (DPR1) 229 for temporarily holding the output of the multiplexer 227, a data pipeline register (DPR2) 228 for temporarily holding the 47-bit output of the MPY 225, a normalizing barrel shifter (N-SFT) 230 which selectively receives either the 24-bit data provided by the DPR1 229 or the 47-bit data provided by the DPR2 228, operates the received data for predetermined digit adjustment in half the machine cycle to provide a 24-bit data, a 24-bit output 231 of the N-SFT 230, a working register (Wr) 235 of 24-bit x 8-word constitution, a 24-bit accumulation output 232 of the Wr 235, an adder (AU) 233 for accumulation and round-off, a 24-bit output 234 of the AU 233, a flag output 236 of the ALU 224, a flag check circuit 237 for the conditional test of the flag output 236, a conditional test shift register (tcsr) 238 of 24 x 1 bits for sequentially storing the 1-bit outputs of the flag check circuit 237, namely, the results of decisions of the flag check circuit 237, and a 1-bit carrier 239 which provides the highest bit shifted out when the N-SFT 230 provides a shift instruction for shifting in the LSB direction, namely, right shift. Fig. 8 illustrates the relation between the internal data memories and internal data buses of the digital signal processor of Fig. 6. Shown in Fig. 8 are a multiplexer 240 which applies a 24-bit data at the read port of the M0 207 selectively to the X-bus 220 or the Y-bus 221, a multiplexer 241 which applies a 24-bit data at the read port of the M1 108 selectively to the X-bus 220 or the Y-bus 221, a multiplexer 242 which selects either write data on the DMA bus 210 or write data on the Z-bus 222 and applies the selected data to the read/write port of the M0 207, a multiplexer 243 which selects either write data on the Z-bus 222 or write data on the DMA bus 210 and applies the selected data to the read/write port of the M1 208, a 2-2 addressing selector 244 which applies a write address D address 247 and an internal data memory address I address 248 provided by the DMA control unit 202 selectively to either the read/write port of the M0 207 or the read/write port of the M1 208, an S0 address 245, i.e., the read port address of the M0 207, an S1 address 246, i.e., the read port address of the M1 208, a write address 247 for the M0 207 or the M1 208, and an I address, i.e., an internal memory address, corresponding to data transferred through the DMA bus 210. Fig. 9 illustrates the constitution of the address generating unit 203 of Fig. 6. Shown in Fig. 9 are displacement data 250 indicated by an immediate value included in a microinstruction given to the sequence control unit 202, a 24-bit x 4-word address register (AR) 251, a 12-bit x 4-word index modify register (IXR) 252, a data I/O bus 253 connecting the AR 251 to the X-bus 220, a data I/O bus 254 connecting the IXR 252 to the X-bus 220, an address adder 255 of 24-bit word length, three individual address generators (AGUs) 256, a write address pipeline register (DAPR3) 257 for delaying a 24-bit write address by one machine cycle, and a write address pipeline register (DAPR4) 258 similar to the DAPR3 257. Fig. 10 is a diagram of assistance in explaining an instruction execution pipeline of 5-stage construction of the digital signal processor of Fig. 6. In Fig. 10, there are shown a four-phase machine cycle 260, a fetch stage 261, a decode stage 262, an address update timing 263 in the latter half of the decode stage, a read stage 264, an execution stage 265, a write/accumulation stage 267, and normalizing timing 266 in the former half of the write/accumulation stage 267. Fig. 11 shows part of a microinstruction set for the digital signal processor of Fig. 6. Shown in Fig. 11 are a load instruction 270, a branch instruction 271, a 1-source operation instruction 272, a 2-source operation instruction 273, a source specifying code 274, a destination specifying code 275, a source 0 specifying code 276, and a source 1 specifying code 277. The operation of the digital signal processor will be described hereinafter, in which the components are denoted by the abbreviations. First the general mode of operation of the digital signal processor will be described briefly with reference to Fig. 6. The digital signal processor of the present invention, likewise the conventional digital signal processor, is provided separately with the program bus 200 and the data bus 204, for the parallel execution, on microinstructions, of application of a microinstruction to the sequence control unit 202, data input and output of the arithmetic unit 206 through the data bus 204, parallel generation of 2-input 1-output data addresses by the address generating unit 203, and access of M0 207, M1 208 and the I/F 205 to the external data memory. The DMA control unit 209 implements data DMA transfer through the DMA bus 210 between the M0 207, M1 208 and the I/F 205 independently of the internal operation. Each execution unit, likewise that of the conventional digital signal processor, is of register base. In this digital signal processor, the instruction execution pipeline includes data input and output stages because most instructions do not require delayed operation. Accordingly, in implementing addition, for example, by the arithmetic unit 206, an addition instruction including input and output may be executed by a microinstruction of one step. Consequently, even in a program including various arithmetic operations in combination, one microinstruction can be executed in a time equivalent to one machine cycle. However, the result of execution of an instruction can be used after three instruction steps corresponding to the difference in the number of stages from the read stage of the next instruction. This digital signal processor executes most operations for providing results which need to be used immediately in combinational operations by one instruction to avoid loss. Accordingly, most programs do not suffer from loss. The arithmetic unit 206 and the address generating unit 203 are the same in data word length and format, and are perfectly compatible with each other. Therefore, in processes such as a table look-up process and a dictionary reference process, the result of operation can directly be converted into a data memory address. Functions of the arithmetic unit 206 will be described hereinafter with reference to Fig. 7. The B-SFT 123, the ALU 224 and the MPY 225 are able to operate in one machine cycle and operate in an execution stage among instruction execution pipeline stages. In the next stage, i.e., a write/accumulation stage, the N-SFT 230 is able to perform digit adjustment and applies the result 231 to the Z-bus 222 to write the result in the data memory, or the AU 233 is able to accumulate or round off the contents 232 of the Wr 235 to write the result 234 of accumulation or round-off in the Wr 235. The DPR1 229 and the DPR2 228 are registers to transfer the results to the next stage. Thus, the combinational operation are performed in the following manner. Product-sum: MPY 225 → DPR 228 → N-SFT 230 → AU 233 → Wr 235 Absolute difference sum: ALU 224 → MUX 227 → DPR1 229 → N-SFT 230 → AU 233 → Wr 235 Difference square sum: ALU 224 → DPR0 226 → MPY 225 → DPR2 228 → N-SFT 230 → AU 233 → Wr 235 The difference square sum is obtained by the delayed operation of the DPR0 226. However, this instruction is used continuously in most cases and hence problems attributable to the instruction is negligible. The digital signal processor performed rounding by the following procedure. Thus, the highest bit of data shifted out by the N-SFT 230 is a carry and the AU performs carry addition to round-off the data, and hence the destination of the result of round-off is limited to the Wr 235. Then, the flag check circuit 237 checks the flag 236 indicating the result of comparison operation of the ALU 224 with reference to a condition code specified by a microinstruction and provides a flag of one bit indicating that the condition is met or that the condition is not met. Flags provided by the flag check circuit 237 are set sequentially in the tcsr 238. For example, in determining the maximum value and the minimum value among two input data, the process of selection of either data can be stored. The lateral arrangement of the contents of the tcsr 238 from MSB to LSB corresponds to an index code in binary tree search. The constitution of the internal data memories will be described hereinafter with reference to Fig. 8. The M0 207 and the M1 208 are 24-bit x 512-word 2-port RAMs. In applying two input data in parallel to the arithmetic unit 206, the outputs at the respective read ports of the M0 207 and the M1 208 are provided on the X-bus 220 and the Y-bus 221 respectively through the selectors 240 and 241. At this time, an S0 address 245 and an S1 address 246 are given respectively to the M0 207 and the M1 208. Furthermore, when both the source and destination are data memories as in vector addition: + + , data is applied from the Z-bus 222 through the MUX 242 or the MUX 243 to the read/write port of the M0 207 or the M1 208. Therefore bus contention does not occur in the internal operation. The constitution of the address generating unit 203 will be described hereinafter with reference to Fig. 9. The address generating unit 203 comprises the three AGUs 256, namely, the S0 address generator (AGU0) 256, the S1 address generator (AGU1) 256 and the D address generator (AGU2) 256. Each AGU 256 has the 24-bit x 4-word AR 251 and the 12-bit x 4-word IXR 252. The address adder 255 adds three terms of the displacement 250, the AR251 and the IXR 252 for two-dimensional address generation. Although the AGU 256 operates in the decode stage, there is a stage difference corresponding to two stages between the decode stage and the write/accumulation stage. Therefore, the D address 247 is provided by the AGU2 after being delayed by two machine cycles by the DAPR3 257 and the DAPR4 258. The ARs 251 and the IXRs 252 are connected to the X-bus 220. The data format of the address generating unit 203 is compatible with that of the arithmetic unit 206. Accordingly, in table look-up, for example, data may be transferred directly from the Wr 235 through the X-bus 220 to the AR 251 and may be provided without changing as the S0 address 245 or the S1 address 246. The instruction execution pipeline of the digital signal processor will be described with reference to Fig. 10. The instruction execution pipeline comprises the following five stages for one instruction. (1) Fetch stage 261 Output of the program counter and reading a microinstruction of one word (48 bits) (2) Decode stage Decoding 262 the microinstruction and address update 263 (3) Read stage 264 Reading source data from data memories or registers through the X-bus 220 and the Y-bus 221 (4) Execution stage 265 Operation of the B-SFT 223, the ALU 224 and the MPY 225 (5) Read/accumulation stage Normalization 266 by the N-SFT 230, and round-off/accumulation by the AU 233 or writing data in the data memory In the write/accumulation stage (5), the output of the AU 233 is stored only in the Wr 235, and the Z-bus 222 and the AU 233 are in an exclusive relation in which the AU 233 is not used when the Z-bus is used, and hence the timing 267 of data write through the AU 233 is the same as that of data write through the Z-bus 222. Since the instructions are executed in the foregoing sequence, consideration of complex delay in producing a program is practically unnecessary, and hence an efficient microprogram can be produced by using a high language compiler. Fig. 11 shows examples of microinstruction sets used by the digital signal processor of the present invention. All the microinstruction sets are 1-word horizontal instruction sets of a word length of 48 bits. The instruction set is not used for the parallel specification of internal resources capable of simultaneous operation. The combination of the resource operations in each stage is specified by a function code according to the instruction. Thus, microinstruction description is simplified. The instruction sets are classified roughly into a load 270, a branch 271, a 1-source operation 272 and a 2-source operation 273. A source code 274 for controlling source destination, a destination code 275, a source 0 code 276 and a source 1 code 277 are set corresponding to the function code. When the data memories are the objective controlled elements, these codes are addressing codes for specifying the corresponding AGUs 256 of the address generating unit 203. The AGUs are identified by resource codes. The addressing mode can be changed over and the setting of normalization shift value can be changed for every operation instruction by using the instruction set, so that a complex signal processing algorithm can be programmed at the least loss. For example, in performing binary tree search as shown in Fig. 4, the operation of the digital signal processor for calculating approximation may be programmed as follows. rep N {subaa sc0, sc1, wr x } Repeat N times sc0: Input vector address control sc1: Reference vector address control Wr x : Working register specification This operation needs N+1 machine cycles. The approximation of a reference vector of a direction 0 and a reference vector of a direction 1 can be determined by repeating the program twice. A process for deciding a reference vector having high approximation and obtaining the node number of the next stage can be programmed as follows. Total Seven instructions Thus, 2N+9 machine cycles are necessary for one stage. Obviously, the number of machine cycles practically coinciding with the ideal number of machine cycles, the process is highly efficient and the program is simple. Although the foregoing example has been described on an assumption that the word length has a 24-bit address space of 16 MW (24 bits), the word length and the data format may be other than those described therein. Although this embodiment has been described with reference to binary search, the same effect can be expected with other signal processing algorithms. Obviously, the details of the foregoing embodiments are not related with and not limitative of the substance of the present invention as claimed As apparent from the foregoing description, the digital signal processor according to the present invention as defined in claim 1 highly adaptive, flexible and capable of operating at high processing speed.

Claims: A digital signal processor comprising: an instruction fetch unit for reading a microinstruction every machine cycle through a program bus (200) from an instruction memory (201) previously storing microinstructions specifying various internal operations; an execution unit (206) for processing two input data; a plurality of working registers (235) capable of storing the results of operation of the execution unit (206); a plurality of 2-port memories (207, 208) for individually storing the two data or for storing the two data block by block for the operation of said execution unit (206) and the results of said operation, each having a read port and a read/write port and capable of concurrently reading data from or writing data through both the ports; a direct memory transfer control unit (209); and an address generating unit including a plurality of address registers (251) and being capable of parallel generation of read and write addresses for said plurality of 2-port memories (207, 208); characterized by a sequence control unit (202) for controlling the execution of the microinstruction in every machine cycle by separating the steps of microinstruction execution procedure in a 5-stage pipeline including an instruction fetch stage, an instruction decode stage, a data read stage, execution stage and a write/accumulation stage, to execute one word of the microinstruction in one machine cycle; a plurality of internal data buses (204) for the parallel transfer of two input data to said execution unit (206) for binomial operation in the data read stage of the 5-stage pipeline; and for for transferring the output data of the execution unit (206) in the data write/accumulation stage of the 5-stage pipeline; said execution unit (206) processing said two input data transferred by the internal data buses through a single operation or combinational operations both in the execution stage and data write/accumulation stage of the 5-stage pipeline; said working registers (235) also being connected to said internal data bus in order to transfer data to said internal data buses (204); an output control unit for selecting one of the internal data buses or one of the working registers to which the output of the execution unit is to be provided a read control unit for selecting one or the plurality of read ports of the plurality of 2-port memories (207,208) to read the input data from the 2-port memories (207,208) and to provide the input data on the internal data buses; an external data memory interface unit (205) for selecting one or the plurality of internal data buses (204) to read data from an external data memory connected to said external data memory interface unit (205) and for writing data provided on one or the plurality of internal data buses in the external data memory; a direct memory access bus (210) separated from the internal data buses (211) for selectively connecting one or the plurality of the read/write ports of the plurality of 2-port memories (207,208) to the external data memory interface unit (205); said direct memory transfer control unit (209) transferring the block by block data through the direct memory transfer bus (210) between the external data memory interface (205) and the 2-port memories (207,208) independently of the internal operation of the sequence control (202); an external data memory arbitration unit which controls contention in connecting the internal data buses (204), and the direct memory transfer bus (210) to the external memory interface unit (205); said address generating unit (203) comprising a plurality of address generators (256) each having said plurality of address registers (251) and a plurality of index registers (252) connected to the data input buses (204) for data transfer therebetween, and capable of parallel generation of read and write addresses for the 2-port memory (207,208) or the external memory at least of the two input data and one output data of the execution unit (206) in the decode stage of the 5-stage pipeline; an address selecting unit for selecting the 2-port memory (207, 208) or the external memory interface unit (205) corresponding to the read and write addresses provided by the address generating unit (203) each synchronized with the read and write stages of the 5-stage pipeline; and a direct memory access address generating unit comprising a plurality of transfer address control registers for pre-setting data through the internal data buses (204) to control data transfer range, and for simultaneously generating the 2-port memory address for direct memory access and an address for the external memory interface unit (205). A digital signal processor according to claim 1, wherein said execution unit (206) and said address generating unit (203) have compatibility of data formats thereby using the data generated in said execution unit (206) as address data. A digital signal processor according to Claim 1, wherein said execution unit (206) comprises: a barrel shifter (223) capable of receiving data from said data input buses (204), and capable of shifting or rotating the input data by an arbitrary number of bits within one machine cycle, and capable of combinational operation of the shifted or rotated data and another input data through a logical operation; an arithmetic logic unit (224) capable of processing the input data at least through addition, subtraction and absolute differential operation within one machine cycle; a multiplier (225) capable of multiplying the two input data or squaring one input data within one machine cycle; a temporarily register (228,229) which selects and holds temporarily one of the output of the arithmetic logic unit (224), the multiplier (225) and the barrel shifter (223); a normalizing barrel shifter (230) which shifts the output data provided by the temporarily register (228, 229) by a predetermined number of bits in half the machine cycle at the longest for the adjustment of the data range; an adder (233) which accumulates the output (231) of the normalizing barrel shifter (230) and the content of selected one of the working registers (228,229) in half the machine cycle at the longest; and a data output unit which transfers the output of the normalizing barrel shifter (230) to the data output buses in half the machine cycle at the longest when the adder is not used; and the barrel shifter (223), the arithmetic logic unit (224) or the multiplier (225) is operated in the execution stage of the 5-stage pipeline for arithmetic logic operations or absolute differential operation, the difference obtained by the arithmetic logic unit (224) in the execution stage is held temporarily by a temporarily register (226), the difference is squared by the multiplier (225) to obtain the square of the difference in one machine cycle, the adder (233) is used for accumultion when accumulation is performed after the range-adjustment of the result of the execution stage has been performed by the normalizing barrel shifter (230) in the data write/ accumulation stage of the 5-stage pipeline or the square of the difference is provided directly on the data output buses when range adjustment is not performed by the normalizing barrel shifter (230) to accomplish various arithmetic and logic operations or combined operations including those for obtaining the product-sum, the sum of absolute differences, the square sum of the differences in a time equivalent to one machine cycle by pipeline technique. A digital signal processor according to Claim 1, wherein each of the address generators (256) of said address generating unit (203) stores an address through said internal data bus (204) in said address register (251), stores an index value through the internal data bus (204) in said index register (252), adds the index modify value, a displacement specified by a microinstruction and the content of the address register (251), simultaneously updates the content of said address register (251) by using the result of addition and treats the result of addition as a data memory address, and performs two-dimensional or other addressing by a combination of the microinstructions by sequentially assigning each address generator (256) to the address generating mode of every microinstruction. A digital signal processor according to Claim 1, wherein said direct memory access control unit (209) and said direct memory transfer address generating unit sequentially assign the rectangular portion of row k x column ℓ, k and ℓ are positive integers, of a two-dimensional data address space of m rows and n columns, m and n are positive integers, for addressing said external data memory interface unit (205), assign addresses to said plurality of 2-port memories (207,208) in an ascending order from an optional start address and select one of said plurality of 2-port memories (207,208) by the highest bit of the address or a plurality of bits of the address for two-dimensional data transfer between said 2-port memories (207,208) and the external data memory (205), and a transfer direction and the number of data to be transferred are specified by a microinstruction in starting direct memory transfer and said direct memory access control unit (209) informs said sequence control unit (202) of the end of data transfer in ending direct memory transfer to concurrently implement transferring data in a rectangular block of row k x column ℓ between the 2-port memory (207,208) and the external data memory (205), and internal arithmetic process. A digital signal processor according to Claim 1, wherein said sequence control unit (202) implements conditional branch operation dealing with a plurality of branch conditions on one microinstruction by previously storing a plurality of conditions in a special register, previously storing instruction memory addresses to which the program is branched when the branch conditions are met in registers corresponding to the branch conditions, testing the plurality of branch conditions in parallel on a microinstruction, branching the program to one of instruction memory addresses stored in the special registers corresponding to the branch conditions of the highest priority among those which are met, and branching the program to the instruction memory address stored in the special register corresponding to which all the branch conditions are not met. A digital signal processor according to Claim 1, wherein said sequence control unit (202) has a loop counter and a repeat counter which are capable of receiving initial values from said internal data buses and providing the contents thereof, the content of the repeat counter is decremented by one for each execution of microinstruction and the same microinstruction is executed repeatedly until the content of the repeat counter is reduced to zero when repeat is assigned by the first microinstruction of repeat operation, the content of the loop counter is decremented by one when loop is assigned by a microinstruction, the program is branched to an instruction memory address specified by the microinstruction when the content of the loop counter is not zero after decrement, and the branch is not completed in order to finish the loop operation when the content of the loop counter is zero after decrement to repeat a single microinstruction or a plurality of microinstructions by a predetermined cycle. A digital signal processor according to Claim 1, wherein said external data memory interface unit divides the external data memory (205) into two parts by using an address previously specified by a microinstruction as a boundary, treats the external data memory (205) as a high-speed memory which accomplishes read/write operation within one machine cycle in addressing one of the two parts of the external data memory, and treats the external data memory (205) as a low-speed memory which stays on standby until an external read/write termination signal is detected in addressing the other part of the external data memory. A digital signal processor according to Claim 1, wherein said instruction memory (201) is partly or totally reloadable, microprograms corresponding functional processes are written in the reloadable instruction memory by an external device to enable the digital signal processing to implement complex and diversified processes, and microprograms are provided automatically by an external memory when the microprograms are not written in the instruction memory (201). A digital signal processor according to Claim 1, wherein said microinstruction is a microinstruction set consisting of a function code uniquely specifying an operation in each stage of said 5-stage pipeline according to the kind of operation, an input assignment code and an output assignment code individually assigning the address generating mode of the address generator (256) of said address generating unit (203) for every microinstruction at least corresponding to a 2-input 1-output or 1-input 1-output data memory, a resource specifying code specifying the objective data memory or the register of data input/output, the number of shift bits of the normalizing barrel shifter (230) of said execution unit (206), a test condition code specifying the kind of operation, an immediate data, and a hold condition code. A digital signal processor according to Claim 1, wherein said external data memory address arbitrary assigns an address for communications between processors, the address is corresponding to an external first-in-first-out memory or an external 2-port memory for communications to connect the same processors or other processors to enable a plurality of processors to implement complex processes at a high processing speed. A digital signal processor according to Claim 1 or 3, wherein the most significant bit of a data of bits from the least significant bit to be truncated by shift in adjusting the number of bits by shifting toward the least significant bit by said normalizing barrel shifter is used as a carry bit or a borrow bit, said adder has an operating mode in which data round-off operation or data round-off accumulation is executed by performing addition with carry or borrow using the contents of said working registers or zero data, and the operating mode assigned by directly controlling said adder by mode setting or a microinstruction. A digital signal processor according to Claim 1 or 3, wherein the arithmetic logic unit (224) of said execution unit (206) decides whether or not a test condition (for example, a condition that two input data are equal to each other) for testing the result of comparison, specified by a microinstruction is met in comparing the sizes of two input data or in testing a special bit in an input data, and sequentially stores the results of decision in one vertical direction of the special shift register (238) for every comparing microinstruction bit by bit, reads the horizontal content of the shift register from the internal data bus, and uses the plurality of results of decision obtained by repeating the comparing microinstructions a plurality of times as a search history code in tree search or for combinational branch operation based on a plurality of conditions.

Inventors: KAMEYAMA MASATOSHI MITSUBISHI, KAMIZAWA KOH MITSUBISHI DENKI, KATOH YOSHIAKI MITSUBISHI DENK, KINJO NAOTO MITSUBISHI DENKI K, MURAKAMI TOKUMICHI MITSUBISHI, OHIRA HIDEO MITSUBISHI DENKI K, KAMEYAMA, MASATOSHI MITSUBISHI DENKI K.K., KAMIZAWA, KOH MITSUBISHI DENKI K.K., KATOH, YOSHIAKI MITSUBISHI DENKI K.K., KINJO, NAOTO MITSUBISHI DENKI K.K., MURAKAMI, TOKUMICHI MITSUBISHI DENKI K.K., OHIRA, HIDEO MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1988
Main classification: G06F7
IPC codes: G06F9, G06F15, G06F7, G06F13