ELECTRONIC DEVICES AND SIGNAL COMPARATOR USING SAME

Abstract: The subjects of the present invention are a bistate device (ST), a current source (BS), a bistable device (FF) and an input circuit (IC) which are all associated to constitute a signal comparator. The bistate device (ST) is a Schmitt trigger which includes current control devices (N17, P13; N18, P14) to provide a current for counterbalancing the deviation of the construction parameters of the transistors so that the operation characteristics of this device remain identical from one process to another. The current source (BS) uses a current mirror configuration and is controlled via a branch coupled between the voltage supply terminals (VDD; VSS), two (N2, N3) of the four (N1 to N4) series connected transistors forming part of this branch have a greater Width-by-Length W/L channel parameter so that identical current sources (BS) may be produced on a large scale because the current (I5; II) supplied by the latter is then independent of the threshold voltages of the constituent transistors. The bistable device (FF) is a fliflop circuit which has differential commoned input and output terminals (T1; T2) and is used to associate the input circuit (IC) having a differential analog output and the bistate device (ST) having a differential digital input. This bistate device has its input/output terminals shunted by a MOS transistor (N14) at every high clock signal (CLK) by which the common voltage on its terminals is then half way between the supply voltages so that, when the state changes, these voltages have only to vary by half instead of the full voltage difference. This allows a faster switching of the bistable device. The input circuit (IC) is an high frequency differential input (I1; I2)/double ended output (T1; T2) circuit.

Description: ELECTRONIC DEVICES AND SIGNAL COMPARATOR USING SAME . The subjects of the present invention are a bistate device, a current source, a bistable device and an input circuit which may for instance all be associated to constitute a signal comparator. The present invention thus relates to a bistate device including two parallel branches each comprising the series connection of a first and a second active devices, said first active device of a branch being controlled from the junction point of said first and said second active devices of the opposite branch. Such a bistate device is already known in the art, e.g. from the article "A 12-bit Sigma-Delta Analog-to-Digital Converter with a 15 MHz Clock Rate" by R. KOCH et al, published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 6, DECEMBER 1986, pages 1003 to 1009. Therein, the bistate device forms part of a comparator (III.C; Fig. 11) and includes PMOS transistors as first active devices and NMOS transistors as second active devices. The switching over of this bistate device occurs when the current flowing through the PMOS transistor of a branch is equal to the current flowing through the NMOS transistor forming part of the same branch. These currents are controlled by the gate-to-source voltages across the corresponding transistors but depend on the process or construction parameters of these transistors, i.e. for instance on the threshold voltage, on the mobility of the charge carriers and on characteristics of the oxide. Because of the latter parameters the matching of a PMOS transistor with an NMOS transistor cannot always be easily reproduced from one process to another. As a result, the operation characteristics of the bistate device may be modified and negatively affected. An object of the present invention is to provide a bistate device of the above known type but of which the operation characteristics are substantially independent of the process parameters. In other words, the object is to obtain a bistate device which can easily be reproduced on a large scale. According to the invention, this object is achieved due to the fact that said bistate device includes a distinct current control device between each of said junction points and the corresponding controlled first device. In this way, the current control device supplies to the first device a current which counterbalances the deviation of the above construction parameters. The operation characteristics of the bistate device may thus be - identical from one process to another even if the construction parameters are different. Another characteristic feature of the present invention is that said first and said second active devices are of opposite polarity types and in that the current generated by each of said current control devices is controlled from said corresponding junction point by a distinct third active device forming part of said current control device and having the polarity type of said second active devices. Since active devices, e.g. transistors, of a same polarity type can easily be matched when built on a same chip and since the current flowing through the first active device - having the opposite polarity type - is controlled by the third active device - having the polarity type of the second device - it is easy to reproduce such a bistate device with identical operational characteristics. The present invention also relates to a current source including a first branch constituted by the series connection of a first transistor of a first polarity type and a second control transistor of a second polarity type, the control electrode of said first transistor being connected to that of a third transistor of said first polarity type so as to control the current flowing therethrough . Here again, with such a current source using a current mirror configuration, if identical current sources have to be produced on a large scale, the matching of the constituent transistors of opposite polarity types creates process problems, one of the matching parameters being the threshold voltages of these transistors. Another object of the present invention is to provide a current source of the known type but wherein the controlled current flowing through the third transistor is independent of the threshold voltages of the constituent transistors thereof. Still according to the invention, this other object is achieved due to the fact that said current source further includes a second branch coupled in parallel with said first branch and constituted by the series connection of a fourth, fifth, sixth and seventh transistors all of said second polarity type and of which the control electrode of said fifth transistor is connected to that of said second transistor. Another characteristic feature of the current source according to the invention is that said fourth and seventh transistors are substantially identical, that said fifth and sixth transistors are substantially identical, and that the Width-by-Length W/L channel parameter of said fifth and sixth transistors is relatively much larger than that of said fourth and seventh transistors. It has been found that with the above condition, the current flowing through the third transistor is independent of the threshold voltages of the constituent transistors of the current source. Simulations have confirmed the expected results. The present invention still relates to a bistable device including two parallel branches each comprising the series connection of a fifth and a sixth active devices, said fifth active device of a branch being controlled from the junction point of said fifth and said sixth active devices of the opposite branch. Such a bistable device is already known, e.g. from the above mentioned article. Still another object of the present invention is to provide a bistable device of the known type but which may be used to associate a circuit having a differential analog output and another circuit having a differential digital input, with the intention of avoiding clock feed through from the digital circuit towards the analog circuit. Still according to the invention, this other object is achieved due to the fact that the junction point between said fifth and sixth active devices of a branch also controls said sixth active devices of the opposite branch. Yet another characteristic feature of the bistable device according to the present invention is that it has differential commoned input and output terminals respectively constituted by said junction points. In this way, a differential analog input signal applied to the differential input/output terminals is clamped on these same terminals as a differential digital output signal. Yet a further characteristic feature of the bistable device according to the present invention is that said interconnected differential input and output terminals are further shunted through a seventh active device. Then, by closing this seventh active device, the input/output terminals of the bistable device are almost short-circuited so that the common voltage thereon is half way between the two supply voltages. As a consequence, when the bistable device changes of state, the voltages at these input/output terminals has only to vary by half instead of the full voltage difference. This allows a faster switching of the bistable device as already described in the European patent application No 88201127.3. The present invention yet relates to an input circuit including a differential amplifier coupled to a first voltage supply terminal via a constant current source and having two legs each coupled to an input terminal and to a second supply voltage terminal via an input active device of a current mirror circuit through which flows a current function of the signal at said input terminal, this current being mirrored to a first output active device of said current mirror circuit, said first output device being connected in series with a second output active device between said first and second voltage supply terminals. Such an input circuit is already described, e.g. in the above mentioned European patent application. Yet another object of the present invention is to provide an input circuit of the known type but which has double ended output terminals, i.e. which can be used as a double ended amplifier. Yet according to the invention, this other object is achieved due to the fact that the input circuit further includes two parallel branches each including the series connection of an eighth and a ninth active devices connected between said first and second voltage supply terminals, said eighth active device being controlled by said second output active device of one of said current mirror circuits and said ninth active device being controlled by said first output active device of the other of said current mirror circuits, the differential output terminals of said input circuit being constituted by the junction points of said eighth and ninth active devices of each of said branches. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings in which : Fig. 1 shows a signal comparator including a bistate device ST, a current source BS, an input circuit IC and a bistate device FF all according to the invention; and Figs. 2 to 5 show various signal waveforms appearing at terminals of the signal comparator of Fig. 1. The signal comparator shown in Fig. 1 is a double ended circuit which is for instance used as a one bit analog to digital converter forming part of the last stage of a sigma-delta modulator and able to provide differential Pulse Density Modulated CPDM) output signals. It has differential input terminals II and 12 and differential output terminals 01 and 02 providing respectively like named complementary output signals. The comparator is connected to a power supply Cnot shown) which provides the supply voltages VSS of 0 Volts Cground) and VDD of 5 Volts, and to a clock signal generator CLK supplying a clock signal, e.g. of 15.36 MegaHertz, all these signals being applied to the comparator via respective like named terminals. The comparator comprises four stages all connected to the supply voltages VDD and VSS: - a current source or bias source BS including NMOS transistors Nl to N5 and PMOS transistors PI and P2, and having an output terminal Blj - an input circuit IC including NMOS transistors N6 to Nil and PMOS transistors P3 to P8, whose input terminals II and 12 are those of the comparator, which has the input current supply terminal BI connected to the bias source BS, and which has output terminals Tl and T2j - a bistable device or flipflop circuit FF including NMOS transistors N12, N13 and N1 and PMOS transistors P9 and P10 and to which the clock terminal CLK and the output terminals Tl and T2 of the input device IC are connected; and - a bistate device or Schmitt trigger ST including NMOS transistors N15 to N18 and PMOS transistors Pll to P1 , to which the output terminals Tl and T2 of the input circuit IC are also connected, its output terminals 01 and 02 being those of the comparator. It is to be noted that the PMOS transistors have generally their source electrode connected to the most positive voltage terminal, e.g. VDD, whilst the NMOS transistors have generally their source electrode connected to the less positive voltage terminal, e.g. VSS. Moreover, a transistor having its gate and drain electrodes interconnected is called hereinafter a diode connected transistor. The bias source BS includes two parallel branches between the voltage supply terminals VDD and VSS. A first branch includes the diode connected transistors Nl to N in series and the second branch includes the series connection of the diode connected transistor PI and the drain-to-source path of the transistor N5 of which the gate electrode is connected to that of the transistor N2 of the first branch in a current mirror configuration. The gate and the drain electrodes of the transistor PI are both connected the gate electrode of the transistor P2 feeding the input circuit IC. The transistor P2 has its drain electrode connected to the output terminal BI of the bias source BS and so further to the like named input current supply terminal of the input circuit IC for which this transistor P2 constitutes a constant current source. The input circuit IC includes six branches coupled between the voltage supply terminals VDD and VSS. The first two of these branches are each constituted by the series connection of the source-to-drain path of the transistor P3/ 4 and the diode connected transistor N6/N7. The source electrode of the transistor N6/N7 is connected to the voltage supply terminal VSS whilst the voltage supply terminal VDD is connected to both these two branches via the commonly used current source P2. The input terminals II and 12 are connected to the gate electrodes of the transistors P3 and P4 respectively. Two other branches are constituted by the series connection of the diode connected transistor P5/P6 and the drain-to-source path of the transistor N8/N9, and the two last branches are constituted by the series connection of source-to-drain path of the transistor P7/P8 and the drain-to-source path of the transistor N10/N11. The branches P5, N8 and P6, N9 are used in current mirror configuration with the branches P2, P3, N6 and P2, P4, N7 respectively. Both the pairs of transistors P5, N9 and P6, N8 control in a complementary way the pairs of transistors P8, Nil and P7, N10 respectively. The junction points between the drain electrodes of the transistors P7 and N10 and of the transistors P8 and Nil are used as respective input terminals Tl and T2 for the flipflop circuit FF as well as for the Schmitt trigger ST. The flipflop circuit FF includes between the voltage supply terminals VDD and VSS two parallel branches each comprising the series connection of the source-to-drain path of the transistor P9/P10 and the drain-to-source path of the transistor N12/N13. The terminal 11/12 is connected to the junction point of the drain electrodes of the transistors P9/P10 and N12/N13 as well as to the interconnected gate electrodes of the transistors P10/P9 and N13/N12 respectively. The terminal Tl is further coupled to the terminal T2 via the source-to-drain path of the transistor N1 of which the gate electrode is controlled by the clock signal CLK applied thereto via the like named clock terminal. The bistate device or Schmitt trigger ST includes between the voltage supply terminals VDD and VSS two parallel branches each comprising the series connection of the source-to-drain path of the transistor P11/P12 and the drain-to-source path of the transistor N15/N16. The terminal T1/T2 is connected to the gate electrode of the transistor N15/N16 whilst the junction point of the drain electrodes of the transistors P11/P12 and N15/N16 is connected to the output terminal 01/02. ST further includes between the voltage supply terminal VDD and the output terminal 02 the series connection of the diode connected transistor P13 and the drain-to-source path of the transistor N17, and between this voltage supply terminal VDD and the output terminal 01 the series connection of the diode connected transistor P14 and the drain-to-source path of the transistor N18. The gate electrodes of the transistors N17 and N18 are both connected to the voltage supply terminal VDD whilst the gate and drain electrodes of the transistors P13 and P14 are connected to the gate electrodes of the transistors Pll and P12 respectively in a current mirror configuration. The purpose of the bias source BS is to maintain a constant current II through the source-to-drain path of the transistor P2 which constitutes the current source of the input circuit IC as already mentioned. The latter IC is a double ended differential amplifier forming the analog input part of the comparator and which receives via its differential input terminals II and 12 the analog output signals from the preceding stage of the sigma-delta modulator Cnot shown). The input circuit IC provides at its differential output terminals Tl and T2 respective analog output signals which are applied to the flipflop circuit circuit FF. According to the relative amplitude of the signals VTl and VT2 at the respective terminals Tl and T2, the flipflop circuit FF is set in a state which clamps in a complementary way these signals VTl and VT2 either to the voltage VSS or to the voltage VDD thus providing to the differential input terminals Tl and T2 of the Schmitt trigger ST the logical levels 0 or 1 respectively. It is to be noted that for each positive value of the clock signal CLK CFig. 3), the terminals Tl and T2 are almost short-circuited via the transistor N1 . At that moment, unless it is to change following a reversal of the input conditions, the previous state of the flipflop circuit FF is latched owing to the hysteresis function of the Schmitt trigger ST. The operation of the comparator is explained more in detail hereinafter by making reference to an example illustrated by the waveform signals shown in the Figs. 2 to 5. First, the bias source BS is described. The purpose of this bias source BS is to provide a current II flowing through the source-to-drain path of the transistor P2 which is independent of the threshold voltages VTn and VTp of any NMOS and PMOS transistors respectively forming part of this bias source BS. Since the current II is a mirror copy of the current 15 flowing through the diode connected transistor PI and also through the drain-to-source path of the transistor N5 connected in series therewith, it is necessary to obtain that the current 15 is independent of VTn and VTp. The current 15 is equal to 15 = Cmn*Cox/2) * CW5/L5) 56 (Vgs5 - VTn)**2 CD wherein * is the multiplication sign for the adjoining terms ; ** precedes the exponent for the previous term; mn is the mobility of the charge carriers; Cox is the capacity of the oxide; VTn is the threshold voltage; W5 is the width of the channel of the transistor N5; L5 is the length of the channel of the transistor N5; and Vgs5 is the gate-to-source voltage of the transistor N5 which is equal to Vgs5 = VB - VSS C2) wherein VB is the bias voltage at the interconnected gate electrodes of the transistors N5 and N2. It is to be noted that the parameters mn , Cox and the threshold voltages VTn are almost identical for all the NMOS transistors built on a same chip. The above equation (1) may for instance be found in the book "INTRODUCTION TO VLSI SYSTEMS" by C. MEAD et al published by "ADDISON-WESLEY PUBLISHING COMPANY", chapter 1.1 "MOS Devices and Circuits", page 5. In this bias source BS, the transistor Nl is chosen identical to the transistor N<-» and the transistor N2 is chosen identical to the transistor N3. One may thus write Wl/Ll = W4/L4 (3) and W2/L2 = W3/L3 C4) wherein Wl, W2, W3 and W4 are the widths of the channels of the transistors Nl, N2, N3 and N respectively; and LI, L2, L3 and L4 are the lengths of the channels of the transistors Nl, N2, N3 and N4 respectively. Furthermore, the construction of these transistors is such that W2/L2 = N * CW1/L1) (5) and thus W3/L3 = N 56 CW /L4) C6) wherein N is a proportionality factor. On the one hand, the current II flowing through the diode connected transistor Nl is equal to II = (mn*Cox/2) * CW1/L1) * CVgsl - VTn)56562 C7) wherein Wl is the width of the channel of the transistor Nl; LI is the length of the channel of the transistor Nl; and Vgsl is the gate-to-source voltage of the transistor Nl which is equal to Vgsl = VDD - VB C8) Thus 11 = Cmπ*Coχ/2) * CW1/L1) * VDD-VB-VTn)*962 C9) On the other hand, the current 12 flowing through the diode connected transistor N2 is equal to 12 = Cmn*Cox/2) * (W2/L2) 5 CVgs2 - VTn)56962 (10) wherein W2 is the width of the channel of the transistor N2; L2 is the length of the channel of the transistor N2; and Vgs2 is the gate-to-source voltage of the transistor Nl which is equal to Vgs2 = VB - VAG Cll) wherein VAG is the voltage at the junction point between the source electrode of the transistor N2 and the drain and gate electrodes of the transistor N3. Thus 12 = Cmn56Coχ/2) 56 W2/L2) 56 CVB-VAG-VTn)56*2 (12) The equation (12) combined with the equation (5) may be written 12 = Cmn96Cox/2) *N56(W1/L1)56 CVB-VAG-VTn) 6562 (13) Because the four diode connected transistors Nl to N4 are in series a same current IS flows through the drain-to-source paths. Therefore, with II and 12 each equal to IS, the equations (9) and (13) then lead to (VDD-VB-VTn)56562 = N -* (VB-VAG-VTn )56562 (14) By choosing the proportionality coefficient N large, this is solved by the physically acceptable approximation VB = VAG + VTn (15) Which, used in equation (2), causes equation (1) to become 15 = (mn56Cox/2) 5 (W5/L5) 56 (VAG - VSS)**2 (16) This last form shows that the current 15 and thus also the current II which is a mirror copy thereof - with or without a proportionality coefficient - is independent of the threshold voltages VTn and VTp of the transistors of the bias source BS when the coefficient N is chosen sufficiently large. This means that the transistors N2 and N3 are much greater than the transistors Nl and N . Fig. 2 shows an example of differential input voltage waveforms VII and VI2 respectively applied to the input terminals II and 12 of the input circuit IC. Up to the instant t2, the voltage VII is more positive than the voltage VI2. At this instant t2, the amplitudes of these voltages VII and VI2 are modified so that the voltage VI2 then becomes more positive than the voltage VII. At the instant t4 on Fig. 2, the amplitudes of these voltages VII and VI2 again change but the amplitude of the voltage VI2 remains higher than that of the voltage VII. As long as the voltage VII is more positive than the voltage VI2, i.e. before t2, the transistor P4 is more conductive than the transistor P3. The current 14 flowing through the transistor P4 is then larger than the current 13 flowing through the transistor P3, although the sum of these currents 14 and 13 remains equal to the current II flowing through the transistor P2. These currents 14 and 13 are mirrored to the other branches of the input circuit IC via the diode connected transistors N7 and N6 respectively. As a result the transistors N9, Nil, P6 and P7 are more conductive than the transistors N8, N10, P5, and P8. As shown in Fig. 4, the voltage VTl at the terminal Tl is then more positive than the voltage VT2 at the terminal T2. As long as the clock signal CLK shown in Fig. 3 is high, the transistor N14 of the flipflop circuit FF is closed so that the terminals Tl and T2 are then almost short-circuited by this transistor N14. This appears in Fig. 4 where prior to the instant tl at which the clock signal CLK becomes low, the voltages VTl and VT2 are forced within a voltage range VL located near the average voltage VAG of 2.5 Volts. However, due to the voltage VTl being more positive than the voltage VT2, the transistors N13 and P9 of the flipflop circuit FF are more conductive than the transistors N12 and P10 thereof. This anticipates the next coming state of this flipflop circuit FF which will be effective when the clock signal CLK is low, i.e. between the instants tl and t2 in Fig. 3. From this instant tl, the transistor N14 becomes blocked so that the flipflop circuit FF may bring the terminals Tl and T2 to the respective voltages VDD (5 Volts) and VSS (0 Volts), i.e. to the logical levels 1 and 0 respectively. The variation of these voltages VTl and VT2 to these logical levels occurs slowly because until the instant t2 the relative amplitudes of the input voltages VII and VI2 are low with respect to that of the average voltage VAG and that the flipflop circuit FF has to overwin these input voltages VII and VI2 and lead them to the extreme values of VDD and VSS respectively. At t2, the clock signal CLK is again high as a consequence of which the amplitudes of the voltages VTl and VT2 are brought within the voltage range VL. Because after t2> the amplitude of the input voltage VII becomes lower than that of the voltage VI2, the flipflop circuit FF has to change its state. This occurs while the clock signal is high, i.e. between t2 and t3. When the clock signal CLK becomes low at the instant t3, the amplitude of the voltages VTl and VT2 are already inverted but both remain within the voltage range VL . From the instant t3, the amplitude of the voltages VTl and VT2 rapidly reach their respective final amplitudes or logical levels 0 and 1. This variation occurs faster than that previously described because the difference of the input voltages VI1-VI2 is now greater (Fig. 2), i.e. closer to the difference of the supply voltages VDD-VSS. At the instant t4, when the clock signal CLK becomes high, the amplitudes of the voltages VTl and VT2 are again brought within the voltage range VL but because the input voltage VI2 now remains more positive than the input voltage VII, the same is true for the respective voltages VT2 and VTl. When the clock signal CLK becomes low at the instant t5, the voltages VTl and VT2 return to their respective previous logical levels, i.e. to the logical level they had before t4. Since the relative amplitudes of the input voltages VII and VI2 with respect to that of the average voltage VAG are now relatively lower than these before t4 (fig. 2), the voltages VTl and VT2 vary a little slowe . The purpose of bringing the two voltages VTl and VT2 back to a neutral value, i.e. within the voltage range VL, at each high clock signal CLK is to reduce the transition time when the flipflop circuit FF changes state. Indeed, when for instance the input voltage VII was more positive than the input voltage VI2 and that this situation is changed, at the following occurence of a low clock signal CLK the voltages VTl and VT2 have then only to vary by 2.5 Volts (VDD-VAG or VAG-VSS) instead of 5 Volts (VDD-VSS). The voltage range VL is so chosen that it is within the hysteresis voltage range from VH- to VH+ (Fig. 4) of the Schmitt trigger ST. In this way, the Schmitt trigger ST remains in its previous state as long as the amplitude of the voltage VTl or VT2 which was the less positive does not exceed the upper value of the hysteresis voltage range VH+. Then, the output voltages V01 and V02 at the output terminals 01 and 02 switch from the logical levels 0 to 1 and vice versa. In the present example, such a variation only occurs at the instant t2 and the state of the Schmitt trigger ST shown in Fig. 5 only changes at the instant t6 - after t3 - when the amplitude of the voltage VT2 increases up to the upper hysteresis voltage VH+ and the amplitude of the voltage VTl becomes lower than the hysteresis voltage VH-. More in detail, when the amplitude of the voltage VTl is relatively larger than that of the voltage VT2 and it exceeds the hysteresis voltage VH+, the transistors N15 and P12 are more conductive than the transistors N16 and Pll. As a result, the voltage V01 at the terminal 01 is at the logical level 0, and the voltage V02 at the terminal 02 is at the logical level 1. In other words, the voltage V02 at the output terminal 02 is at the logical level 1 when the current 112 flowing through the source-to-drain path of the transistor P12 is greater than the current 116 flowing through the drain-to-source path of the transistor N16. The switching of the Schmitt trigger ST occurs when the current 112 is equal to the current 116. It is obvious that by symmetry the same reasoning may be made for the currents flowing through the transistors Pll and N15. The present Schmitt trigger ST is so built that this transition point, i.e. when the current 112 becomes equal to the current 116, is known with accuracy and is independent of the construction or process parameters of the constituent transistors. Indeed, by construction W12/L12 = A * (W14/L14) (17) W16/L16 = B 56 (W18/L18) (18) wherein A and B are proportionality coefficients both greater than 1; W12, W14, W16 and W18 are the widths of the channels of the transistors P12, P14, N16 and N8 respectively; and L12, L14, L16 and L18 are the lengths of the channels of the transistors P12, P14, N16 and N8 respectively. The current 112 is controlled by the transistor N18 of which the drain-to-source current 118 is mirrored to the transistor P12 via the diode connected transistor P14. The gate-to-source voltage Vgsl8 of the transistor N18 is equal to Vgslδ = VDD - V01 (19) and its drain-to-source current 118 is thus equal to 118 = (mn56Cox/2)56(W18/L18)56(VDD-V01-VTn)56*2 (20) Since the transistors N18 and P14 are in series, the drain-to-source current 114 of the transistor P14 is equal to the current 118, and because of the relation (17) one may write 112 = 114 56 A = 118 56 A (21) 112 = (mn56Cox/2)56(W18/L18)56 A 56(VDD-VOl-VTn )56962 (22) or, combined with the relation (18) to have 112 in function of W16 and L16 112 = (mn56Cox/2)56(W16/L16)56A/B96(VDD-V01-VTn)**2 (23) On the other hand, the gate-to-source voltage Vgsl6 of the transistor N16 is equal to Vgsl6 = VT2 - VSS (24) and its drain-to-source current 116 is equal to 116 = ( mn56Cox/2)* ( W16/L16 ) 56 ( VT2-VSS-VTn)56*2 (25 ) It is to be noted that the current 116 increases with the voltage VT2. From the equations (23) and (25), it appears that at the transition point of the Schmitt trigger ST these currents 112 and 116 are both independent of the parameters mp and of the threshold voltage VTp of any PMOS transistor, more especially of the transistor P12. Furthermore, by equating the currents 112 and 116, this transition point is also shown to be independent of the parameter mn of any NMOS transistor and of the parameter Cox. Finally, by a suitable choice of the proportionality coefficients A and B» the equations (23) and (25) may become, in a first approximation, almost independent of the threshold voltage VTn of any NMOS transistor. Indeed, these coefficients may be so chosen that any variation of the threshold voltage VTn affects almost in a same way the values of both the currents 112 and 116 so that such a variation is compensated. Because the operational characteristics of this Schmitt trigger ST are substantially independent of the process parameters of the constituent transistors thereof, identical circuits can be produced on a large scale. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: CLAIMS 1. Bistate device (ST) including two parallel branches (Pll, N15, P12, N16) each comprising the series connection of a first (Pll; P12) and a second (N15; N16) active devices, said first active device of a branch being controlled from the junction point (02; 01) of said first and said second active devices of the opposite branch, characterized in that it includes a distinct current control device (P13, N17; P14, N18) between each of said junction points (02; 01) and the corresponding controlled first device (Pll; P12). 2. Bistate device (ST) according to claim 1, characterized in that it has differential input terminals (Tl; T2) each connected to the control terminal of a respective one of said second active devices (N15; N16) and differential output terminals (01; 02) to which respective ones of said junction points (01; 02) are connected. 3. Bistate device (ST) according to claim 1, characterized in that said first (Pll; P12) and said second (N15, N16) active devices are of opposite polarity type and in that the current generated by each of said current control devices (P13, N17; P14, N18) is controlled from said corresponding junction point (02; 01) by a distinct third active device (N17, N18) forming part of said current control device and having the polarity type of said second active devices. 4. Bistate device (ST) according to claim 3, characterized in that said first active devices (Pll; P12) are PMOS transistors and that said second CN15, N16) and third (N17; N18) active devices are NMOS transistors, and in that said two parallel branches (Pll, N15; P12, N16) are connected between a first (VDD) and a second (VSS) voltage supply terminals. 5. Bistate device (ST) according to claim 4, characterized in that each of said current control devices (P13; N17; Pl4, N18) is constituted by the series connection of a fourth (P13; P14) and said third (N17; N18) active devices connected between said first voltage supply terminal CVDD) and the corresponding junction point (02; 01), and in that said fourth active devices are PMOS transistors. 6. Bistate device (ST) according to claim 5, characterized in that, in each of said current control devices CP13, N17; P14, N18), both the gate and drain electrodes of the fourth active device (P13; P14) are connected to the gate electrode of the first active device (Pll; P12) of one of said branches (Pll, N15; P12, N16) whilst the source electrode of the third active device (N17; N18) is connected to said junction point (01; 02) of the opposite branch, said first voltage supply terminal (VDD) being connected to the gate electrodes of both said third active devices. 7. Current source (BS) including a first branch (PI, N5) constituted by the series connection of a first transistor (PI) of a first polarity type and a second control transistor CN5) of a second polarity type, the control electrode of said first transistor being connected to that of a third transistor (P2) of said first polarity type so as to control the current flowing therethrough, characterized in that it further includes a second branch (Nl to N4) coupled in parallel with said first branch (PI, N5) and constituted by the series connection of a fourth (Nl), fifth (N2), sixth (N3) and seventh (N4) transistors all of said second polarity type and of which the control electrode of said fifth transistor is connected to that of said second transistor (N5). 8. Current source (BS) according to claim 7, characterized in that said fourth (Nl) and seventh (N4) transistors are substantially identical, that said fifth (N2) and sixth (N3) transistors are substantially identical, and that the Width-by-Length W/L channel parameter of said fifth and sixth transistors is relatively much larger than that of said fourth and seventh transistors . 9. Current source (BS) according to claim 8, characterized in that said first (PI) and third (P2) transistors are PMOS transistors, said first transistor having its gate and drain electrodes interconnected, and that said second (N5), fourth (Nl), fifth (N2), sixth (N3) and seventh (N4) transistors are NMOS transistors said fourth to seventh transistors having their respective gate and drain electrodes interconnected, and in that both said first (PI, N5) and second (Nl to N4) branches are coupled in parallel between a first (VDD) and a second (VSS) voltage supply terminals. 10. Bistable device (FF) including two parallel branches (P9, N12; P10, N13) each comprising the series connection of a fifth (P9; P10) and a sixth (N12; N13) active devices, said fifth active device of a branch being controlled from the junction point (T2; Tl) of said fifth and said sixth active devices of the opposite branch, characterized in that the junction point (Tl; T2) between said fifth (P9; P10) and sixth (N12; N13) active devices of a branch (P9, N12; P10, N13) also controls said sixth active devices of the opposite branch. 11. Bistable device (FF) according to claim 10, characterized in that it has differential commoned input CTl; T2) and output (Tl; T2) terminals respectively constituted by said junction points. 12. Bistable device (FF) according to claim 10, characterized in that said fifth active devices CP9; P10) are of a polarity types opposite to that of said sixth active devices (N12; N13), and in that said two parallel branches (P9, N12, P10, N13) are connected between a first (VDD) and a second (VSS) voltage supply terminals. 13. Bistable device CFF) according to claim 12, characterized in that said fifth active devices (P9; P10) are PMOS transistors and in that said sixth active devices CN12, N13) are NMOS transistors, all said transistors being controlled via their gate electrodes. 14. Bistable device (FF) according to claim 10, characterized in that said interconnected differential input CTl; T2) and output (Tl; T2) terminals are further shunted through a seventh active device CN14). 15. Bistable device CFF) according to the claims 13 and 14, characterized in that said seventh active device CN14) is an NMOS transistor controlled by a clock signal CCLK) applied to its gate electrode. 16. Input circuit CIO including a differential amplifier CP3; P4) coupled CBI) to a first voltage supply terminal (VDD) via a constant current (II) source (P2) and having two legs (P3, P4) each coupled to an input terminal (II, 12) and to a second supply voltage terminal CVSS) via an input active device CN6; N7) of a current mirror circuit CN6, N8, P5; N7, N9, P6) through which flows a current CI3; 14) function of the signal CVI1; VI2) at said input terminal (II; 12), this current being mirrored to a first output active device CN8; N9) of- said current mirror circuit, said first output device CN8; N9) being connected in series with a second output active device CP5; P6) between said first CVDD) and second CVSS) voltage supply terminals, characterized in that it further includes two parallel branches (P7, N10; P8, Nil) each including the series connection of an eighth (P7; P8) and a ninth (N10; Nil) active devices connected between said first (VDD) and second (VSS) voltage supply terminals, said eighth active device (P7; P8) being controlled by said second output active device (P5; P6) of one of said current mirror circuits (N6, N8, P5; N7, N9, P6) and said ninth active device (N10; Nil) being controlled by said first output active device (N9; N8) of the other of said current mirror circuits, the differential output terminals (Tl; T2) of said input circuit (IC) being constituted by the junction points of said eighth CP7; P8) and ninth (N10, Nil) active devices of each of said branches. 17. Input circuit (IC) according to the claim 16, characterized in that said input (N6; N7), first output (N8; N9) and ninth (N10; Nil) active devices are NMOS transistors, in that said second output (P5; P6) and eighth (P7; P8) active devices are -PMOS transistors, in that the control of said active devices occurs via their interconnected gate electrodes and in that the voltage at said first voltage supply terminal (VDD) is more positive than the one at said second voltage supply terminal (VSS). 18. Signal comparator (BS, IC, FF, ST) for the comparaison of two input signals (VII; VI2) characterized in that it includes a current source (BS), a input circuit (IC) a bistable device (FF) and a bistate device (ST), according to one of the claims 1 to 6, 7 to 9, 10 to 15 and 16 to 17, said signal comparator having said differential input terminals (II; 12) of said input circuit (IC) and said differential output terminals (01; 02) of said bistate device (ST) and being coupled between said first (VDD) and said second (VSS) voltage supply terminals, said third transistor (P2) of said current source (BS) constituting said constant current (II) source (P2) of said input circuit (IC) and said differential output terminals (Tl; T2) of said input circuit (IC) being respectively connected to said differential input and output terminals (Tl; T2) of said bistable device (FF) and to said said differential input terminals (Tl; T2) of said bistate device (ST).

Inventors: GUEBELS PIERRE-PAUL FRANCOIS M, SEVENHANS JOANNES MATHILDE JOS, GUEBELS, PIERRE-PAUL, FRANCOIS, MAURICE, MARIE, SEVENHANS, JOANNES, MATHILDE, JOSEPHUS
Applicants: ALCATEL NV, BELL TELEPHONE MFG, ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE VEN
Application year: 1988
Main classification: H03K3
IPC codes: G05F3, H03F3, H03K3