Method of manufacturing a semiconductor device with insulated-gate structure

Abstract: Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.

Description: The invention relates to a method for manufacturing a semiconductor device comprising the steps of: forming a structure in which a patterned electrically insulating cover layer overlies a similarly patterned conductively doped layer of non-monocrystalline silicon lying on a dielectric layer that lies along the upper surface of a major doped region of a semiconductor body after which, depositing a layer of silicon oxide on the upper surface of the structure, removing largely all of the silicon oxide layer except for small spacer portions adjoining the sidewalls of patterned cover layer and the doped layer and implanting a main semiconductor dopant into selected parts of the major region using the spacer portions and the patterned layers to substantially block the main dopant from being implanted into the part of the major region below the spacer portions and the patterned layers. An insulated-gate field-effect transistor (FET) made from a body of monocrystalline silicon according to state-of-the-art semiconductor processing techniques usually consists of a conductively doped polycrystalline silicon (polysilicon) gate electrode, a thin gate dielectric lying under the gate electrode, and a pair of source/drain (S/D) regions formed in the semiconductor body. The S/D regions are separated from each other by a channel region that lies below the gate dielectric. The S/D regions are typically created by ion implantation in which the gate electrode is used as a shield to prevent implantation into the channel. At the end of the implantation, the sides of the gate electrode are in substantial vertical alignment with the inside boundaries of the S/D regions. However, lateral diffusion of the implanted dopant during subsequent heating steps causes the gate electrode to partially overlap the S/D regions in the final FET. The overlap causes a loss in effective channel length and a loss in FET speed. One technique for controlling the vertical alignment is to form insulating spacers along the sidewalls of the gate electrode before performing the ion implantation to define the S/D regions. The sidewall spacers then act as a further implantation shield during the S/D implantation. This increases the initial lateral separation between the S/D regions, thereby substantially reducing undesirable overlap of the gate electrode to the S/D regions. In US-A- 4,420,872, sidewall spacers are created by thermally oxidizing side portions of a patterned polysilicon layer formed on the gate dielectric. The oxidation is done at 1050°C. A layer of silicon nitride lying on the polysilicon layer largely prevents the underlying polysilicon at the intended location for the gate electrode from being oxidized. Later in the fabrication process, contact openings are etched through silicon dioxide along the upper surfaces of the S/D regions. The spacers and nitride layer protect the gate electrode. Although the etch is actually performed using a photoresist mask, the S/D contact openings are self-aligned in that the boundaries of the openings nearest the gate electrode are determined by the spacers rather than the photoresist pattern. The self-alignment leads to a relatively compact FET. A disadvantage of the method described in US-A- 4,420,872 is that some of the polysilicon that forms the bottom surface of the gate electrode near its sidewalls is oxidized during spacer formation. This phenomenon is termed "Gate dielectric encroachment" because the thickness of the gate dielectric becomes significantly greater at the sides than in the middle. The encroachment reduces the effective area of the gate electrode. Also, the S/D regions must be driven laterally in further below the gate dielectric. This usually leads to a performance degradation because the S/D regions go deeper into the semiconductor body at the same time. Gate dielectric encroachment is substantially avoided when the sidewall spacers are formed by a combination of oxide deposition and anisotropic etching. Ogura et al, "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEEE IEDM Tech. Dig., 7 - 9 Dec. 1981, pp. 651 - 654, employ this process in fabricating a so-called lightly doped drain (LDD) FET. In material part, Ogura et al start by forming a structure in which a patterned cover layer of silicon dioxide lies on a similarly patterned doped polysilicon layer (destined to become the gate electrode). The The polysilicon layer lies on a dielectric layer located along the upper surface of a P-type region of a monocrystalline silicon body. Using the two patterned layers as an implantation shield, the LDD part of the FET is created by implanting an N-type dopant a at a low dosage into the P-type region. A layer of silicon dioxide is then deposited conformally on the upper surface of the structure. Using an anisotropic etchant, largely all of the conformal layer is removed except for small spacer portions that adjoin the sidewalls of the polysilicon layer. Due to the nature of the etching process, each of the sidewall spacers is thicker at the bottom than at the top. The main portions of the S/D regions are formed by implanting an N-type dopant into the P-type region using the spacer portions and the patterned layers as an implantation mask. An annealing heat treatment is then performed to repair lattice damage and activate the implanted species. Parts of the polysilicon layer and the P-type region are oxidized along their upper surface during the heat treatment. The remaining polysilicon forms the gate electrode. Because the same material - - i.e., silicon dioxide -- lies on both the gate electrode and the S/D regions in Ogura et al, it is extremely difficult to etch self-aligned contact openings down to the S/D regions without exposing the gate electrode at the same time. A critical photoresist mask must be utilized to define the S/D contact openings. This increases the FET die area. According to the invention the method described in the opening paragraph of page 1 is characterized in that the cover layer comprises a toplayer of a protective material that substantially prevents the non-monocrystalline silicon of the doped layer, except along its side walls, from being oxidized during a heat treatment and that, after the small spacer portions are formed but before implanting the main semiconductor dopant into selected parts of the major region, an oxidizing heat treatment is carried out whereby portions of the doped layer along its side walls are oxidized to increase the thickness of the spacer portions. Preferred embodiments are given in dependent claims 2-4. Thus gate sidewall spacer portions, having a relatively large thickness at the top of the gate electrode, can be created without a significant gate dielectric encroachment. In practice the structure formed will then further be covered with a phosphosilicate or boron-doped phosphosilicate glass layer. Because the gate is protected by said relatively thick spacer portions and the protective toplayer formed on the gate, contact windows for the source and drain zones now can be etched easily in that glass layer down to the semiconductor region, whereby the contact windows may overlap the gate. The invention further will be described by way of example referring to a drawing, in which: Fig. 1a to Fig 1j are cross-sectional structural views representing steps in a process for manufacturing a semiconductor device in accordance with the invention. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Referring to the drawings, Figs. 1a - 1j illustrate steps in the fabrication of an N-channel insulated-gate FET that utilizes sidewall spacers made in accordance with the invention. Conventional cleaning and photoresist masking techniques are employed in the fabrication process. References to cleaning steps, to the steps involved in making photoresist masks, and to other such steps that are well known in the semiconductor art are omitted from the following description to simplify the discussion. The starting point is a (100) monocrystalline silicon semiconductor body having a lightly doped major P-type region 10 as shown in Fig. 1a. A recessed electrically insulating layer 12 of silicon dioxide underlaid by a P-type channel-stop region 14 is formed according to conventional oxide-isolation techniques along the upper surface of P-region 10. Oxide layer 12 laterally separates a group of active semiconductor islands from one another along the upper surface of region 10. One such island 16 appears in Fig. 1a. A thin dielectric layer 18 (destined to become the FET gate dielectric) is formed along the upper surface of island 16 in P-region 10 to a thickness of 100 - 500 angstroms (10 angstroms = 1 nanometer). See Fig. 1b. Dielectric layer 18 preferably consists of thermally grown silicon dioxide. However, layer 18 may be formed with other dielectric materials such as silicon nitride or a combination of silicon dioxide and silicon nitride. A layer of polysilicon having a thickness of 0.25 - 0.35 micrometer is deposited according to conventional low-pressure chemical vapor deposition (LPCVD) techniques on dielectric layer 18 and is then doped either by diffusion or ion implantation to produce an electrically conductive polysilicon layer 20 (destined to become the FET gate electrode). See Fig.1b again. The dopant in layer 20 may be P-type (boron) or N-type (arsenic or phosphorus). Fig. 1b illustrates the N-type case. A thin electrically insulating layer 22 of silicon dioxide is thermally grown along, or deposited on, the upper surface of doped polysilicon layer 20. Oxide layer 22 has a thickness of 300 - 500 angstroms. A relatively thin layer 24 of silicon nitride is now deposited according to conventional LPCVD techniques on oxide layer 22. Nitride layer 24 has a thickness of 600 - 1,000 angstroms. This completes the structure illustrated in Fig.1b. A photoresist mask 26 is formed on nitride layer 24 at the general location for the gate electrode and gate dielectric. Using one or more conventional anisotropic dry etchants, the exposed portions of layers 24, 22, 20 and 18 are removed in sequence. Fig. 1c shows the resulting structure in which patterned layers 18A, 20A, 22A, and 24A are the respective remainders of layers 18 - 24. Oxide layer 18 could also be left intact. After removing mask 26, ions 28 of a suitable N-type dopant are implanted into P-region 10 at a low dosage and a low energy to produce lightly doped N-type S/D regions 30 for an LDD architecture. See Fig. 1d. The LDD dopant is preferably phosphorus implanted at a dose of 1x10 13 ions/cm 2 and an energy of 50 keV. Arsenic could also be used as the dopant. Layers 18A - 24A act as a shield that substantially blocks ions of the LDD dopant from being implanted into the part of region 10 underlying layers 20A - 24A. A further layer 32 of silicon dioxide is conformally deposited according to a conventional LPCVD technique on the upper surface of the structure as depicted in Fig. 1e. The deposition temperature is typically 420°C. Oxide layer 32 has a thickness approximately equal to the total thickness of layers 18A - 24A. For example the thickness of layer 32 is approximately 0.3 micrometer. An anisotropic etch is performed to remove largely all of oxide layer 32 except for small spacer portions 34 that adjoin the sidewalls of layers 18A - 24A. See Fig. 1f. The etch is typically done according to reactive ion etch (RIE) techniques using a combination of CHF 3 , CO 2 , and He as the etchant. Due to the nature of the etch and the original shape of oxide layer 32, the spacer thickness -- i .e., the lateral spacer dimension in the drawings -- gradually increases in going from top to bottom. The spacer thickness is typically 0.25 micrometer at the upper surface of island 16. Portions of the polysilicon that forms the sidewalls of doped layer 20A are thermally oxidized to increase the thickness of oxide spacers 34. This is done by performing a heat treatment on the structure in an oxidizing environment at a temperature no greater than 850°C. The oxidation temperature is at least 700°C. The heat treatment is preferably done for 2 hours in dry oxygen at 800°C. Nitride layer 24A functions as a thermal oxidation shield during the heat treatment to block the oxygen above layer 24A from reaching polysilicon layer 20A. Layer 24A thereby substantially protects the underlying polysilicon, except for the polysilicon along the sidewalls of layer 20A, from being oxidized. Fig. 1g shows the resulting structure in which the remainder 36 of layer 20A forms the gate electrode for the FET. The portion 38 of oxide layer 18A underlying gate electrode 36 is the gate dielectric for the FET. Due to both the relatively low oxidation temperature and the shielding effect provided by the lower parts of spacers 34, very little polysilicon along the bottom of electrude 36 is oxidized during the heat treatment. The thickness of gate dielectric 38 remains largely constant across its area, as indicated in Fig. 1g. That is there is little gate dielectric encroachment. The amount of additional spacer thickness achieved during the heat treatment is greater at the top of each spacer 34 than at the bottom due to the oxidation mechanism and the initial spacer shape. Compare Figs. 1f and 1g. The thickness of spacers 34 therefore becomes more uniform across their height. This is a highly beneficial result because the spacer thickness at the top corners of electrode 36 is now great enough to avoid electrical shorts that might otherwise occur between electrode 36 and the S/D metalization (described below) during subsequent processing. The minimum spacer thickness at the end of the heat treatment is typically 0.2 micrometer. A small thickness of the silicon nitride along the top of layer 24A is converted into a very thin layer 40 of silicon dioxide (typically 20 angstroms in thickness) during the heat treatment. The remainder of nitride layer 24A is labeled as layer 42 in Fig. 1g. The portion of oxide layer 22A above electrode 36 is labelled as layer 44. Also, a small thickness of the exposed silicon along the tops of N-regions 30 is converted into layers 46 of silicon dioxide. The thickness of oxide layers 46 is typically 400 angstroms. Ions 48 of a suitable N-type dopant are implanted into P-region 16 at a high dosage and a high energy to produce main S/D regions 50. See Fig. 1h. The main S/D dopant is preferably arsenic implanted at 6 x10 15 and 80 keV. Antimony could also be used. Spacers 34 and layers 36-44 act as a shield that substantially blocks ions of the main dopant from being implanted into the part of region 10 below elements 34 - 44. Oxide layers 46 (along with oxide layer 40 and a small thickness of spacers 34) could be removed before the main S/D implantation. The structure is now annealed to repair lattice damage and activate the implanted N-type dopants The anneal is preferably done for one hour at 920°C in nitrogen with 10% oxygen. The implanted N-type dopants diffuse outward. Each pair of N-type regions 30 and 50 becomes a composite N-type S/D region 52 having a heavily doped main portion and a lightly doped extension (demarcated by a dotted line) as indicated in Fig. 1i. Polysilicon electrode 36 slightly overlaps the N- extensions in the vertical direction but does not overlap the main N+ portions. This LDD configuration prevents undesired hot carrier generation. A layer 54 of an electrically insulating material such as phosphorsilicate glass, boron-doped phosphosilicate glass, or plasma silicon nitride is typically deposited on the upper surface of the structure at this point. To provice more protection for electrode 36, a thin layer of LPCVD silicon nitride could be formed on the top of the structure before depositing insulation layer 54. In either case, a photoresist mask 56 is formed on layer 54. Mask 56 has apertures generally above, but substantially larger than, oxide layers 46 that overlie the N+ portions of S/D regions 52. Self-aligned contact openings to the N+ portions of S/D regions 52 are created by etching the structure with a suitable oxide etchant to remove oxide layers 46. See Fig. 1i. Slight thicknesses of the other portions are also removed during this etch. Layer 40A is, for example, the remainder of oxide layer 40. The etch is typically performed with the above-mentioned RIE etchant. Spacers 34 and the exposed parts of nitride layer 42 (in combination with mask 56) function as an etch barrier to prevent any portion of electrode 36 from being exposed during the etch. Mask 56 is subsequently removed. Insulation layer 54 may not be needed in some applications. In such a case, self-aligned contact openings can be etched down to N+ regions 52 in the manner described above exept that a photoresist mask need not be used. The structure is provided with a metalization pattern 58 that contacts S/D regions 52 through the contact openings as depicted in Fig. 1j. Metalization 58 is typically created by depositing a layer of a suitable metal such as aluminium with 1 % silicon and 1 % copper and then removing the undesired metal. Prior to metal deposition, the upper surface of the exposed silicon may be supplied with a thin layer of a self-aligned metal silicide (such as titanium silicide) or a thin layer of selectively deposited tungsten. The FET occupies a small area because the metal contacts to regions 52 are self-aligned. While the invention has been described with reference to a particular embodiment, this description is solely for the purpose of illustration and is not to be construed as limiting. The scope of the invention is defined in the claims. For example, the above process could be employed to make a P-channel insulated-gate FET by reversing the conductivities for all of the regions except possibly the conductivity for the gate electrode. The P-channel FET would typically not have an LDD extension. Both types of FET's could be made in the same semiconductor device using the process of the invention. Rather than starting directly with polysilicon, the gate electrode could be formed by initially depositing another form of non-monocrystalline semiconductor material such as amorphous silicon. During the subsequent high-temperature steps, the amorphous silicon is converted into polysilicon. Thus, various modifications, changes, and applications may be made by those skilled in the art without departing from the scope of the invention as defined by appended claims.

Claims: A method for manufacturing a semiconductor device comprising the steps of: a) forming a structure (10;18A;20A;22A,24A) in which a patterned electrically insulating cover layer (22A,24A) overlies a similarly patterned conductively doped layer (20A) of non-monocrystalline silicon lying on a dielectric layer (18A) that lies along the upper surface of a major doped region (16) of a semiconductor body (10) after which, b) depositing a layer (32) of silicon oxide on the upper surface of the structure (10; 18A;20A;22A,24A), c) removing largely all of the silicon oxide layer (32) except for small spacer portions (34) adjoining the sidewalls of patterned cover layer (22A,24A) and the doped layer (20A) and d) implanting a main semiconductor dopant into selected parts of the major region (16) using the spacer portions (34) and the patterned layers (18A;20A;22A,24A) to substantially block the main dopant from being implanted into the part of the major region (16) below the spacer portions (34) and the patterned layers (18A;20A;22A,24A), characterized in that, e) the cover layer (22A,24A) comprises a toplayer (24A) of a protective material that substantially prevents the non-monocrystalline silicon of the doped layer (20A), except along its side walls, from being oxidized during a heat treatment and that, f) after the small spacer portions (34) are formed but before implanting the main semiconductor dopant into selected parts of the major region (16), an oxidizing heat treatment is carried out whereby portions of the doped layer (20A) along its side walls are oxidized to increase the thickness of the spacer portions (34). A method as claimed in claim 1 characterized in that the oxidizing heat treatment is performed at a temperature in the range of 700°C and 850°C. A method as claimed in claim 1 or 2 characterized in that the cover layer (22A,24A) is formed of a layer (22A) of silicon oxide provided with a top layer (24A) of silicon nitride. A method as claimed in claim 1, 2 or 3 characterized in that before the layer (32) of silicon oxide is deposited on the upper surface of the structure (10;18A;20A;22A,24A), a preliminary semiconductor dopant implantation into selected parts of the major region (16) through its upper surface is carried out, using the patterned layers (18A;20A;22A,24A) to substantially block the preliminary dopant from being implanted into the part of the major region (16) below the patterned layers (18A;20A;22A,24A).

Inventors: CHEN TEH-YI JAMES, CHEN, TEH-YI JAMES
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L29