VOLTAGE TRANSDUCER

Abstract: The transducer includes a differential input stage (DIS) having an output (03) controlling the gate of an output transistor (P3) whose main current path is connected between the poles of a DC supply source in series with three resistances (R1/3). The junction of the first (R1) and second (R2) resistances is connected to one input (I2) of the differential stage and the junction of the second (R2) and third (R3) resistances constitutes an output (02) of the transducer having another output constituted by the junction of the transistor (P3) and the first resistance (R1).

Description: Voltage transducer The present invention relates to a transducer including an amplifier having a first input as well as an output coupled to a second input via a negative feedback loop and such that the voltage at said second input is substantially equal to an input voltage applied to said first input. Such a transducer is well known in the art, e.g. from the article "A Bipolar Voltage-Controlled Tunable Filter" by K. Fukahori, Journal of Solid-state Circuits, Vol. SC-16, No 6, December 1981, pp 729-731 and more particularly from Fig.8 on page 773 thereof. This transducer is able to convert an input voltage, e.g. a reference DC voltage, into a reference DC current flowing from the output. An object of the present invention is to provide a transducer of the above type, but which provides two separate output voltages that are respectively smaller and larger than said input voltage by accurate predetermined voltages. Such output voltages may for instance be used as reference voltages in the feedback loop of a sigma-delta modulator of the type disclosed in the published European patent application No 0155061. According to the invention this object is achieved due to the fact that said output is coupled to a DC bias potential through three impedances in series, the junction between the first and the second being coupled to said second input and the junction between the second and the third constituting an additional output for said transducer. In this way the same current flows through all three impedances so that the voltages at the transducer outputs are equal to the input voltage plus and minus respective predetermined voltages which are each function of the ratio of two impedances. Because such a ratio can be realised in an accurate way - better than the impedances themselves - the predetermined voltages and therefore also the output voltages are accurate. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will * be best understood by referring to the following description of embodiments taken in conjunction with the accompanying drawings wherein : Fig. 1 is a schematic diagram of a first embodiment of a transducer according to the present invention; Fig. 2 shows a second embodiment of a transducer according to the present invention. The transducer shown in Fig. 1 is built up by means of PMOS transistors PI to P3, of which P2 is connected in diode configuration, NMOS transistors Nl and N2, constant current source CS, resistors Rl to R3 and capacitor C. The transducer comprises an amplifier constituted by the cascade connection of a differential input stage DIS and an output stage OS and has an external input II and two external outputs 01 and 02. The differential input stage DIS comprises two parallel branches connected in series with the constant current source CS between the poles of a DC supply source. These poles are at the bias potentials V and ground respectively. These branches comprise the series connected transistors PI, Nl and P2, N2 respectively. The gates of transistors Nl and N2 constitute the negative and positive inputs II and 12 of the differential stage DIS, whilst the junction point of transistors PI and Nl is the output 03 of this stage. The output stage OS comprises the series connection, between V and ground, of transistor P3 and the resistors Rl to R3 which constitute the drain impedance of this transistor. The gate of transistor P3 is controlled by the output 03 of the input stage DIS and the drain of this transistor P3 constitutes the transducer output 01. The latter is connected to the output 03 via capacitor C which is used for stability purposes as well as to the input 12 of the input stage stage DIS via the feedback resistance Rl. Hence 12 is the feedback input of DIS. The junction point of the resistors R2 and R3 is the transducer output 02. Instead of connecting the resistors Rl/3 of the output stage OS in the way shown in Fig. 1 they may also be connected as represented in Fig. 2. Therein they constitute the source resistance of transistor P3 whose gate is again controlled by the output 03 of the differential input stage DIS. However, II and 12 are now used as feedback input and as external input of the transducer respectively. In both cases the external input is at a high impedance level and the three resistances Rl/3 are decoupled therefrom. To be noted that in Fig. 1 the output 01 is connected to the positive input 12 via feedback resistor Rl because the voltages at 03 and 01 vary in opposite direction. On the contrary, in Fig. 2 the output 01 is connected to the negative input II via resistor Rl because these voltages vary in the same direction. Instead of using a PM0S transistor P3 in the output stage OS use may obviously also be made therein of an NM0S transistor. Also instead of M0S transistors bipolar transistors could be utilised. Returning to Fig. 1, when for instance a DC reference voltage VI is applied to the transducer input II and assuming that the gain of the input stage DIS is sufficiently high the input 12 will substantially also be at the same reference voltage VI. As a consequence a DC current I = V1/CR2+R3) CD flows to ground through the resistors R2 and R3. Because no current flows into the input 12 this DC current I necessarily flows through P3 and Rl in series so that the voltages V01 and V02 at the transducer outputs 01 and 02 are given by : V01 = VI + Rl.I C2) V02 = VI - R2.I C3) or, when taking the relation CD into account by V01 = VI + V1.R1/CR2+R3) C ) V02 = VI - V1.R2/CR2+R3) C5) In the transducer of Fig. 2 the output voltages V01 and V02 are given by the following relations : V01 = VI - CV-VDR1/CR2+R3) C6) V02 = VI + CV-VDR2/CR2+R3) C7) From the relations C ) to C7) it follows that the two voltages V01 and V02 are equal to a same reference voltage VI plus and minus a respective predetermined voltage which is dependent on the value of the ratio of two resistances and not on the values of these resistances themselves. This is advantageous when the transducer has to be integrated on a chip since it is easier to realise an accurate resistance ratio then an accurate resistance. Instead of resistances other impedances, e.g. Zener diodes, could be used. Further, instead of applying an input DC voltage, an AC voltage or an AC/DC voltage could be aplied. From the above it is also clear that the present transducer first converts the DC reference voltage VI into -a DC reference current I and then uses this current to generate predetermined voltage drops in the resistances Rl and R2, thus creating the output voltages V01 and V02. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: - - CLAIMS 1. Transducer including an amplifier CDIS, OS) having a first input CI1, Fig. 1, 12, Fig. 2) as well as an output COl) coupled to a second input CI2, Fig. 1, II, .-'ig. 2) via a negative feedback loop CRD and such that the voltage at said second input CI2, ID is substantially equal to an input voltage CVD applied to said first input CI1, 12), characterized in that said output COD is coupled to a DC bias potential through three impedances CRl, R2» R3) in series, the junction between the first CRD and the second CR2) being coupled to said second input CI2, ID and the junction between the second CR2) and the third CR3) constituting an additional output C02) for said transducer. 2. Transducer according to claim 1, characterized in that said output COD is further connected to a second DC bias potential, having a value distinct from the first, through the main current path of an output transistor CP3), all three said impedances CR1/3) allowing the flow of DC current. 3. Transducer according to claim 2, characterized in that said output transistor CP3) is controlled from the output C03) of a differential amplifier stage CDIS) having said first CI1, 12) and second CI2ϊ ID inputs. 4. Transducer according to claim 1, characterized in that said first input CI1, 12) is at a high impedance level, e.g. input of an operational amplifier, said three impedances CR1/3) being decoupled therefrom.

Inventors: HASPESLAGH DIDIER RENE, HASPESLAGH, DIDIER, RENE
Applicants: ALCATEL NV, BELL TELEPHONE MFG, ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENN
Application year: 1988
Main classification: G05F3
IPC codes: G05F1, G05F3