Protective relay

Abstract: A protective relay for detecting faults within a predetermined protected zone of a three phase alternating current electrical power distribution system generates a polarizing signal V POL which includes a signal V₁ related to a positive sequence component of a phase voltage of the three phase power distribution system. A signal I₁Z R , which is a signal related to a positive sequence component of a phase current of the three phase power distribution system multiplied by a replica impedance of the protected zone of the three phase power distribution system, is also generated. The coincidence of the V POL and I₁Z R signals are compared and an operate signal is generated as a result of positive coincidence. A first restraint signal is generated as a result of negative coincidence. A second restraint signal related to V₁ is also generated. A net operating signal is generated when the magnitude of the operate signal exceeds the sum of the magnitudes of the first restraint signal and the second restraint signal.

Description: The present invention relates to protective relay circuits for use in AC power distribution systems and more particularly to distance relays for transmission line protection. Distance relays are well known in the art of protective relaying. For example, reference may be had to "The Art and Science of Protective Relaying", Mason, published by John Wiley & Son, Inc. (1956), particularly to chapter 14. Prior art distance relays include those which employ a phase comparator method of measurement. Exemplary circuits for phase comparator distance relays are disclosed in U.S. Patent No. 4,034,269, issued to S.B. Wilkinson, the inventor of the present invention, on July 5, 1977; and U.S. Patent No. 4,420,788, issued to S.B. Wilkinson and G.E. Alexander on December 13, 1983. Positive sequence distance relays are utilized in protective systems for AC power transmission lines to detect three phase faults within a protected zone or portion of the transmission line. If such a fault is detected within the relay's zone or reach, the positive sequence distance relay will cause the operation of a three pole circuit breaker to trip all three phases of the transmission line. This is to be contrasted with a ground relay which detects faults between a phase and ground, again within a designated zone or reach; and, upon detection of such a fault, generates a signal which may operate a circuit breaker to trip the faulted phase only. As indicated above, each particular positive sequence distance relay should only detect faults within its protected zone or reach. The parameters of a distance relay are commonly selected to correspond to the parameters of the transmission line. For example, the parameters are selected to provide a forward reach that may correspond to the forward distance of the zone of the transmission line under protection of the particular relay. It is desired that the distance relay operate within its selected forward reach thereby confining the protection of a particular distance relay to a selected zone within a protected system. The desired operation of the distance relay may be hindered by the inability to distinguish between internal and external faults. Internal faults are those which occur within the protected zone or reach of the relay, whereas external faults are those that occur outside the zone or relay reach. For example, transients generated by capacitive voltage transformers or series capacitors in series compensated lines, often cause external faults to appear as internal faults to a distance relay. In the past, many distance relays have employed phase angle comparator circuits; an example of such a distance relay is disclosed in US-A-4,433,353. In some cases, these relays have employed amplitude comparators as well as phase angle comparators. In phase angle comparators, the characteristic is typically developed by measuring the angle between an operating signal, for example V OP = IZ-V , and a polarizing signal, V POL . This measurement may be accomplished by use of a coincidence logic circuit and a characteristic timer; see, for example, the above referenced U.S. Patent No. 4,034,269. For the simplest phase angle comparator, the operating time is a function of the phase angle between V OP and V POL and the fault incidence angle rather than the severity of the fault (i.e., the magnitude of the operating signal). Consequently, a fault just in front of the relay and a fault at a remote location (for example, 90% of the relay reach), would produce the same steady state timer input blocks of approximately one half cycle even though the operating signal for the close-in fault is much larger than that for the remote fault. In the case of a fault just beyond the reach of the relay, the operating and polarizing signals are 180% out of phase and therefore produce no input to the characteristic timer. In addition, the magnitude of the operating signal is very small; therefore any errors in the operating signal, such as those caused by capacitive coupled voltage transformer errors, may cause the operating signal to reverse thus producing an undesirable operation of the measuring unit. In order to prevent such an overreach condition in a zone 1 relay, the operate signal must be sufficiently filtered to remove erroneous signals or the reach must be reduced. Amplitude comparators have typically been used in negative sequence distance units and restrained overcurrent units. In this design, the minimum operating time is also determined by the setting of the characteristic timer as it is in the phase angle comparator design. However, even though this function operates on a comparison of signal magnitude, the speed of operation is not directly related to the fault severity. In this regard, the amplitude comparator circuit is similar to the phase angle comparator implementation. An aspect of the present invention seeks to provide a distance relay for detecting three phase faults in a protected zone of AC power transmission line which relay has an operating time which is based upon fault severity. Another aspect of the present invention seeks to provide a distance relay which operates more quickly for a close-in fault as compared to a remote end fault in a protected zone of an AC power transmission line. Yet another aspect of the present invention seeks to provide a distance relay with improved discrimination between internal and external faults thereby increasing the reliability of relay operation and the security of the protection system. A further aspect of the present invention seeks to provide a distance relay having improved discrimination between internal and external faults on series capacitive compensated AC power transmission lines. Still another aspect of the present invention seeks to provide a distance relay having improved discrimination between internal three phase faults and close-in internal single line to ground faults for improved phase selection in single pole tripping schemes. A still further aspect of the present invention comprises a positive sequence distance relay whose main purpose is to detect three phase faults within a predetermined protected zone of a three phase AC electrical power transmission line. The positive sequence distance relay includes an energy comparator comprising an integrator circuit and a level detector circuit. The output of the integrator circuit varies as a function of the magnitude of the difference between operate and restraint signals, which provides an operating time based on fault severity. The output of the integrator circuit is coupled to the input of the level detector circuit which generates an output signal when the input signal magnitude exceeds a predetermined trip level. A close-in fault, as compared to a remote end fault, produces a larger signal to drive the integrator circuit output more quickly to the trip level. The positive sequence distance relay of the present invention preferably utilizes an operate signal determined by the positive coincidence of a polarizing signal (V POL ) and the positive sequence component of the phase current (I₁) multiplied by the replica impedance of the protective zone of the transmission line (Z R ). The negative coincidence of V POL and I 1 Z R is utilized to determine one restraint and the positive sequence component of the voltage (V₁) is utilized as a second restraint. The invention, both as to its organization and operation, may be better understood by reference to the following illustrative description in conjunction with the accompanying drawings, in which:- Figure 1 is a one line, block diagram of a current and voltage processing portion of a preferred embodiment of the present invention. Figure 2 is a block diagram of a reach adjustment and polarizing portion of the preferred embodiment of the present invention. Figure 3 is a block diagram of positive sequence units in accordance with a preferred embodiment of the present invention. Figure 4 is a R-X diagram depicting a mho/lens characteristic of a positive sequence distance relay in accordance with the present invention. Referring to Figure 1, there is shown a three-phase alternating current electric power transmission line, generally designated 10, having an A phase (A), a B phase (B), a C phase (C) and ground (G). Each of the three phases have associated with it means 12 for sensing the current in that particular phase as well as means 20 for sensing voltage on that phase. As is well known to those skilled in the protective relaying and power transmission art, current sensing means 12 may be a current transformer and voltage sensing means 20 may be a step down potential transformer. As shown in Figure 1, a current sensing means is associated with each phase; means 12a being associated with phase A, 12b being associated with phase B and 12c being associated with phase C. Likewise, there is a separate voltage sensing means 20a associated with phase A, means 20b associated with phase B and means 20c associated with phase C. However, it is to be understood that although a specific type of current and voltage sensing scheme is depicted in Figure 1, other schemes known in the art may be substituted for that depicted; the purpose being to obtain signals which are related to each phase voltage and each phase current. The output from the current sensing means 12a is coupled to a first transactor 13a; the output from current sensing means 12b is coupled to a second transactor 13b; and the output from the current sensing means 12c is coupled to a third transactor 13c. As is known in the art, the secondary voltage output of a transactor is related to the input current by a complex proportionality constant or a vector operator known as the transfer impedance of the transactor. For the transactors 13a, 13b and 13c shown in Figure 1, the transfer impedance of each is selected to be equal to a fixed transfer ratio and a fixed angle, for example 85°. Consequently, the output of transactor 13a is a signal I AT which has, for example, a fixed 85° phase shift with respect to the input I A . The output signals I BT and I CT from the transactors 13b and 13c respectively, are similarly related to their respective inputs I B and I C . Further detailed descriptions of transactors may be had by reference to U.S. Patent No. 3,374,399, issued to Dewey. The outputs of the transactors 13a, 13b, and 13c are coupled to the inputs of a first positive sequence network 14 and a first three-input summing amplifier 16. The summing amplifier 16 has an output which is equal to the sum of the inputs multiplied by a predetermined gain which, the preferred embodiment, is minus one-third. Consequently, the output of the summing amplifier 16 is equal to MI₀ where I₀ is the zero sequence component of the phase current in the transmission line and M indicates, in the convention used in this detailed description, that the signal is inverted. The output of the first three-input summing amplifier 16 is coupled to the input of a phase shift network 18. The output of the phase shift network 18 is the input signal which has been shifted in phase by a predetermined amount which, in the preferred embodiment, is 25 degrees lagging. Consequently, the output of the phase shift network 18 is the signal MI₀F where F, in the convention used in this detailed description, indicates that the signal has been phase shifted. The output of the voltage sensing means 20a is coupled to the primary of a first transformer 21a; the output of the voltage sensing means 14b is coupled to the primary of a second transformer 21b; and the output of the voltage sensing means 20c is coupled to the primary of a third transformer 21c. The signals from the secondaries of transformers 21a, 21b and 21c are coupled to the inputs of the second positive sequence network 22. It is well understood by those skilled in the art of electrical power transmission relaying that phase currents in a three-phase alternating current circuit can be resolved into three sets of symmetrical, balance voltage and current vectors known as positive sequence, negative sequence and zero sequence components. It is also well known that certain circuits called "symmetrical component networks" can be connected to a three-phase electrical power system to provide an output signal that is proportional to the magnitude of the selected one of the three sequence components of voltage or current. The positive sequence networks 14 and 22 are such networks. The positive sequence current and voltage networks also include a lagging phase shift network as described above for phase shift network 18 with the preferred phase shift of 25°. The output of the first positive sequence network 14 is the positive sequence component I A1 of the current flowing in the A phase of the transmission line. The output of the second positive sequence network 22 is the positive sequence component V A1 of the voltage in the A phase of the transmission line. Sequence networks of this type are disclosed in U.S. Patent No. 4,342,062. Further detailed descriptions of symmetrical component networks can be had by reference to U.S. Patent No. 3,992,651 issued to Hodges; and 4,034,269 issued to Wilkinson, both of which patents, as well as U.S. Patent No. 4,342,062, are assigned to the assignee herein and the teachings of all are incorporated into this detailed description by reference as if fully set forth herein. The output signal I A1 is coupled to the input of a positive sequence angle adjust circuit 24. The output of the positive sequence angle adjust circuit 24 (I A1 S) is equal to the input signal (I A1 ) having a preselected angle which, in the preferred embodiment, is in the range of from approximately 70 to 85 degrees. Consequently, the S in the expression I A1 S indicates that, in the convention used herein, the positive sequence component of the phase A current has been adjusted to a predetermined angle. The angle adjust circuit 24 allows the relay replica impedance (Z R ) to be adjusted to the same impedance angle as the protected line. Referring now to Figure 2, there is shown the reach adjustment and polarizing portion of the positive sequence distance relay of the present invention. The positive sequence component of the phase A voltage (V A1 ), which has been obtained in accordance with the description set forth with reference to Figure 1, is coupled to a non-inverting input of a first two-input summing amplifier 30 and the input of a first absolute value circuit 32. In the preferred embodiment, the first two-input summing amplifier 30 is an operational amplifier whose output is equal to the vector sum of the inverting and non-inverting inputs. In the preferred embodiment, each of the absolute value networks 32, 44, 46, 68 and 86 comprises a full wave precision rectifier of the type shown and described on pages 206 and 207 of the publication entitled "IC Op-Amp Cookbook", Second Edition, W. G. Jung, Howard Sams & Co., Inc. which is incorporated in the detailed description by reference as if fully set forth herein. The output of the first absolute value network 32, which is substantially equal to the absolute value of the input signal, is coupled to the input of a first gain select circuit 34. The output of the first gain select circuit 34 has a magnitude which is selectable in accordance with a predetermined gain which is selectable by a "high" or "low" signal applied to a gain select input. In the preferred embodiment, the gain is either 1, selectable by application of a "high" signal to the gain select input, or, selectable by application of a "low" signal 0.4; consequently, the magnitude of the output is either equal to the magnitude of the input signal or is equal to 0.4 times the magnitude of the input signal depending upon the gain select control input. The I A1 S signal, which was generated in accordance with the description set forth with respect to Figure 1, is coupled to the input of a first positive sequence reach adjust circuit 36 and a second positive sequence reach adjust circuit 38. The first 36 and the second 38 positive sequence reach adjust circuits are operational amplifier circuits having an adjustable gain. The output of the first positive sequence reach adjust circuit 36, which has an adjustable gain selected to provide the replica impedance magnitude for the overreaching zone of protection (ZT), is coupled to the input of a first AC couple circuit 40. The output of the second positive sequence reach adjust circuit 38, which has an adjustable gain selected to provide the replica impedance for zone one protection (Z₁), is coupled to the input of a second AC couple circuit 42. In the preferred embodiment, the first 40 and second 42 AC couple circuits comprise non-inverting operational amplifier circuits which have a gain of one for 60HZ signals but have a gain of zero for any dc component in the input signal. The output of the first 40 and second 42 AC couple circuits, each of which is equal to the input but with any dc component removed, are coupled to the inputs of a second 44 and third 46 absolute value network respectively. The outputs of the second 44 and third 46 absolute value networks are respectively coupled to the inputs of a second 48 and third 50 gain select networks. In the preferred embodiment, the second 48 and third 50 gain select networks are of the same type as the first gain select network 34 having a selectable gain which is, in the preferred embodiment, the same as the first gain select network 34. The output of the second gain select network 48 is coupled to the input of a first electronic switch 52 and a second electronic switch 54. In the preferred embodiment, the electronic switches 52 and 54 are each controlled by a signal applied to a control input. Application of a control signal to the control input will operate the switch thereby connecting the signal applied to the input of the switch directly to the output. With respect to the first electronic switch 52, a "high" signal applied to the control input will connect the input of the switch to the output. With respect to the second electronic switch 54, a "low" input applied to the control input will cause the input of the electronic switch to be connected to the output. The output of the first electronic switch 52 is coupled to the input of the first inverter 56. The first inverter 56 is preferably an operational amplifier having an inverting input and an output which is substantially equal to the inverted input signal. Consequently, the output of the first inverter 56 is a signal MI₁ZT which is the inverse of the output I₁ZT of the second electronic switch 54. The output of the second AC couple circuit 42 is also connected to the input of a second inverter 58. The second inverter 58 is preferably an operational amplifier whose output is the inverse of the input. The output of the second inverter 58 is coupled to the input of a forward offset circuit 60 and one input of a two-input coincidence logic circuit 62. In the preferred embodiment, the forward offset circuit is an operational amplifier circuit with an adjustable gain selectable between 0 and 0.4. The output of the forward offset circuit 60, which is a selectable portion of the zone 1 reach magnitude (Z) multiplied by the phase shifted positive sequence current (I A1 S) is coupled to the input of a clip circuit 64. In the preferred embodiment, the clip circuit 64 comprises a zero suppression circuit which passes that portion of the input signal which is greater than a preset level, and a differential amplifier which subtracts the output of the zero suppression network from the input signal. Consequently, the output signal of the clip circuit 64 comprises only that portion of the input signal that is less than the preset level. In the preferred embodiment, the clip circuit 64 is of the type shown and described under the heading "BOUNDS" of a publication entitled "Nonlinear Circuits Handbook", edited by Daniel H. Sheingold, published 1974 by Analog Devices Inc., Norword, Mass, which publication is incorporated in this detailed description as if fully set forth herein. The output of the clip circuit 64 is coupled to an inverting input of the first two-input summing amplifier 30. The output of the first two-input summing amplifier 30, which as previously stated is the algebraic sum of the inverting and non-inverting inputs, is coupled to the input of a band pass filter 66. In the preferred embodiment, the band pass filter 66 has a center frequency equal to the nominal power system frequency typically 50 HZ or 60 HZ. and a Q of approximately 3.8. The output of the band pass filter 66 is coupled to the input of a fourth absolute value network 68 and the second input of the two-input coincidence logic circuit 62. In the preferred embodiment, the fourth absolute value circuit 68 is of the type previously described with respect to the first 32, second 44, and third 46 absolute value networks. The output of the fourth absolute value network 68, which is the absolute value of the input, is coupled to the input of a level detector 70. The output of the level detector 70, which is a signal generated when the input exceeds a predetermined level which is, in the preferred embodiment 0.35 per unit, is coupled to the gain control inputs of the first 34, second 48 and third 50 gain select networks. An output signal from the level detector 70 causes the first, second and third gain selector networks to apply the high gain to the input signals of the circuits. With no output from the level detector 70, the first, second and third gain select networks will apply the low gain to the input signals. The output of the third gain select network 50 is coupled to the inputs of a third electronic switch 72 and a fourth electronic switch 74. The third 72 and fourth 74 electronic switches are of the type described previously with respect to the first 52 and second 54 electronic switches. The third electronic switch 72 will cause the signal applied to its input to be connected to its output upon application of a high signal to the control input; whereas the fourth electronic switch 74 will connect the signal applied to its input to its output upon application of a low signal to the control input. The output of third electronic switch 72 is coupled to the input of a third inverter 76. The third inverter 76 is preferably an operational amplifier whose output is the inverse of the input. The output of the coincidence logic 62, which is a high signal during coincidence of the two inputs, is coupled to the control inputs of the first 52, second 54, third 72 and fourth 74 electronic switches. Consequently, the output of the third inverter 76 is a signal MI₁Z₁ which is the inverse of the output I₁Z₁ of the fourth electronic switch 74. The MI₀F signal, which was generated as described with respect to Figure 1, is coupled to the input of a zero sequence reach adjust network 78 and the input of a fixed reach network 80. In the preferred embodiment, the zero sequence reach adjust network 78 is the same design as the previously described positive sequence reach adjust networks 36 and 38. The output of the zero sequence reach adjust network 78, which has an adjustable gain selected to provide the replica impedance magnitude for the first zone of the protective zone, is coupled to a third AC couple network 82. In the preferred embodiment, the third AC couple network 82 is of the type described with respect to the first 40 and second 42 AC couple networks. The output of the zero sequence reach adjust network 78 is also coupled to one input of a second two-input summing amplifier 84. In the preferred embodiment, the second two-input summing amplifier 84 is preferably an operational amplifier whose output signal has a magnitude which is equal to the sum of the magnitude of the signals applied at the first and second inputs. The output of the second AC couple network 82 is coupled to the input of a fifth absolute value network 86. In the preferred embodiment, the fifth absolute value network 86 is of the type described with respect to the first, 32, second, 44, third, 46, and fourth, 68 absolute value networks. The output of the fifth absolute value network 86, which has a magnitude which is the absolute value of the magnitude of the input signal, is coupled to the input of a zero suppression network 88. In the preferred embodiment, the zero suppression network 88 comprises a circuit which removes that portion of the input signal that is less than a preset level. Consequently, the output signal of the zero suppression network 88 comprises only that portion of the input signal which is greater than the preset level. In the preferred embodiment, the zero suppression network 88 is of the type shown and described under the heading "DEAD ZONE" on pages 25-26 of the aforementioned "Nonlinear Circuits Handbook" previously incorporated into this detailed description by reference. The output of the zero suppression network 88 is coupled to the input of a fast rise, slow decay circuit 90. The fast rise, slow decay circuit 90 is preferably an operational amplifier circuit with a dual time constant: a short time constant on the application of an input signal and a long time constant on the removal of the input signal. The output I₀Z₁ of the fast rise, slow decay circuit 90 is a signal which decays with a long time constant following the removal of the input signal to the circuit 90. The output of the second two-input summing amplifier 84, which has a magnitude substantially equal to the sum of the outputs from the zero sequence reach adjust network 78 and the fixed reach network 80 as previously described, is coupled to the input of a fourth AC couple circuit 92. In the preferred embodiment, the fourth AC couple circuit 92 is of the type previously described with respect to the first, 40, second, 42, and third, 82 AC couple circuits. The output of the fourth AC couple circuit 92 is coupled to the input of a sixth absolute value network 94. The sixth absolute value network 94 is of the type previously described with respect to the first, 32, second, 44, third, 46, fourth, 68, and fifth, 86 absolute value networks. The output of the sixth absolute value network I₀ZT, is a signal having a magnitude which is the absolute value of the magnitude of the input signal as previously described. Referring now to Figure 3, there is shown a block diagram of a tripping positive sequence unit, generally designated 102; a blocking positive sequence unit, generally designated 104; and a first zone positive sequence unit, generally designated 106. The MI₁ZT signal, which was generated as described with respect to Figure 2, is coupled to a non-inverting input of a second three-input summing amplifier 108 of the positive sequence trip relay 102 and an inverting input of a third two-input summing amplifier 110 of the positive sequence blocking relay 104. The signal I₁ZT generated as described with respect to Figure 2 is coupled to an inverting input of the second three-input summing amplifier 108 and a non-inverting input of the third two-input summing amplifier 110. The I₀ZT signal, generated as previously described with respect to Figure 2, is coupled to an inverting input of the second three-input summing amplifier 108. The output of the second three-input summing amplifier 108, which is a signal having a magnitude equal to the algebraic sum of the inverting and non-inverting inputs, is coupled to a non-inverting input of a third three-input summing amplifier 112. The signal V₁, which is generated as described with respect to Figure 2, is coupled to an inverting input of the third three-input summing amplifier 112; an inverting input of a first six-input summing amplifier 114 of the positive sequence blocking relay 104; and an inverting input of a second six-input summing amplifier 116 of the positive sequence zone one relay 106. A bias signal is coupled to an inverting input of the third three-input summing amplifier 112 and an inverting input of the first six-input summing amplifier 114 through a fifth electronic switch 118. The fifth electronic switch 118 is of the type described with respect to the second electronic switch 54 and fourth electronic switch 74 in that a low signal applied to the control input will cause the signal at the input of the switch to be connected to its output. A restraint control signal (RTCON), which is generated to switch out restraint in the positive sequence units 102, 104 and 106, for reasons which will be subsequently described, is coupled to the control input of the fifth electronic switch 118 and the control input of a sixth electronic switch 120. The sixth electronic switch 120 is preferably of the type described with respect to the second electronic switch 54, the fourth electronic switch 74 and the fifth electronic switch 118 in that a low signal applied to the control input will cause the signal appearing at the input of the switch to be switched to its output. As shown in Figure 3, a bias signal is coupled to an inverting input of the second six-input summing amplifier 116 through the sixth electronic switch 120. The output of the third three-input summing amplifier 112, which, as previously described, is a signal having a magnitude which is equal to the algebraic sum of the magnitudes of the signals coupled to the inverting and non-inverting inputs, is coupled to a non-inverting input of a fourth two-input summing amplifier 122 and the input of a first filter 124. A bias signal, having an adjustable magnitude, is applied to an inverting input of the fourth two-input summing amplifier 122. The output of the fourth two-input summing amplifier 122, which is a signal having a magnitude equal to the algebraic sum of the inverting and non-inverting inputs, is coupled to the input of a first "integrator" circuit 126. In the preferred embodiment, the first "integrator" circuit 126 comprises an operational amplifier having a feedback circuit connected between its output and its input. The feedback circuit comprises a resistor and a capacitor connected in parallel. The input to the "integrator" circuit 126 is the input to the operational amplifier; and the output of the "integrator" circuit 126 is the output of the operational amplifier. The output of the first "integrator" circuit 126, is coupled to the input of a second level detector 128. In the preferred embodiment, the second level detector 128 is of the type described with respect to the first level detector 70 in which the output is a signal (PDT) which is generated when the input of the second level detector 128 exceeds a predetermined value. In the preferred embodiment, this predetermined level is equal to 60 mv to provide a threshold to overcome extraneous signals. The PDT signal is utilized in the system as a circuit breaker trip signal. In the preferred embodiment, the filter 124 is a simple R-C filter followed by an operational amplifier buffer. The output of filter 124, which is essentially equal to the input of the filter except that the magnitude of any high frequency components has been reduced, is applied to the input of a half-wave rectifier 130. The output of the half-wave rectifier, which is a signal comprising only the positive half-wave portions of the input signal, is coupled to an inverting input of the first six-input summing amplifier 144. The output of the third two-input summing amplifier 110, which as previously described is a signal having a magnitude which is the algebraic sum of the magnitude of the signals applied to the inverting and non-inverting inputs, is coupled to a reach adjustment network 132. In the preferred embodiment, the reach adjustment network 132 is an operational amplifier with adjustable gain, having a gain range of 0.5 to 2.25. The output of the reach adjust network 132 which has been adjusted in magnitude to provide the proper replica impedance reach for the blocking zone of protection, is coupled to a non-inverting input of the first six-input summing amplifier 114. The V A1 signal, generated as described with respect to Figure 1, is coupled to the input of a second band pass filter 134 and a non-inverting input of a fifth two-input summing amplifier 136. In the preferred embodiment, the second band pass filter 134 is a multiple feed back band pass filter with the center frequency selected equal to the rated frequency of the power system, which frequency is typically 50Hz or 60Hz, and connected to an inverting input of a fifth two-input summing amplifier 136. The second band pass filter 134 preferably has a Q approximately equal to two and a gain of one. With a Q of two, a change in the output signal from the band pass filter 134 lags a corresponding change in the input thereby providing short term memory of the pre-change signal. Although a higher Q would provide a longer time constant and a longer term memory, it would create greater phase variation upon occurrence of a change in frequency, which could cause generation of a signal from the fifth two-input summing amplifier 136 to which the output of the second band pass filter 134 is coupled. Such a signal could create erroneous operation of the relay since it could be generated as a result of an expected variation in frequency and not as a result of a fault. The output of the fifth two-input summing amplifier 136 is a signal ΔV₁ having a magnitude which is the algebraic sum of the inverting and non-inverting inputs of the amplifier 136. Due to the short term memory of the band pass filter 134, as previously described, immediately following occurrence of a fault, the output signal ΔV₁ from the amplifier 136 is initially equal to the postfault positive sequence component of the voltage minus the pre-fault positive sequence component of the voltage or the change in the positive sequence component of the voltage which is attributable to the fault. The signal ΔV₁ is coupled to the input of a seventh absolute value network 138 which is of the type previously described with respect to the first, 32, second, 44, third, 46, fourth, 68, fifth, 86, and sixth, 94 absolute value networks. The output of the seventh absolute value network 138 is a signal whose magnitude is the absolute value of the magnitude of the input signal and is coupled to a non-inverting input of the first six-input summing amplifier 114. The output of the first six-input summing amplifier 114 is coupled to the input of a second "integrator" circuit 140. The second "integrator" circuit 140 is of the type described with respect to the first "integrator" circuit 126. The output of the second "integrator" circuit 140 is coupled to a third level detector 142. In the preferred embodiment, the third level detector 142 is the same type as the previously described second level detector 128. The output of the third level detector 142 is a blocking signal (PDB) which is generated when the input of the third level detector 142 exceeds a predetermined level, which, in the preferred embodiment, is 60mv to provide a threshold to overcome extraneous signals. The PDB signal is used to block generation of a tripping signal as will be subsequently described. The output of the second level detector 142 is also coupled to the control input of a seventh electronic switch 144. The seventh electronic switch 144 is of the type described with respect to the first 52 and third 72 electronic switches in that a high signal applied to the control input causes the signal at the input of the switch to be connected to its output. A bias signal is coupled to a non-inverting input of the first six-input summing amplifier 114 through the sixth electronic switch 144. The MI₁Z₁ signal, which was generated as described with respect to Figure 2, is coupled to a non-inverting input of the second six-input summing amplifier 116. The I₁Z₁ signal, which is generated as described with respect to Figure 2, is coupled to an inverting input of the second six-input summing amplifier 116. The I₀Z₁ signal, which is generated as described with respect to Figure 2, is coupled to an inverting input of the second six-input summing amplifier 116. An out-of-step blocking signal (POSBR) is generated by an out-of-step blocking relay of the type shown and described in our co-pending European Patent Application (Agents' Ref: 11RCO4716) corresponding to U.S. patent application No. 120,149 entitled "OUT-OF-STEP BLOCKING UNIT" and which is incorporated by reference in this detailed description as if fully set forth herein. The out-of-step blocking signal POSBR is applied to an inverting input of the second six-input summing amplifier 116. The output of the second six-input summing amplifier 116 is coupled to a non-inverting input of a sixth two-input summing amplifier 146. A bias signal having an adjustable magnitude is coupled to an inverting input of the sixth two-input summing amplifier 146. The output of the sixth two-input summing amplifier 146, which is a signal having a magnitude which is substantially equal to the algebraic sum of the magnitude of the signal applied to the inverting and non-inverting inputs, is coupled to the input of a third "integrator" circuit 148. The third "integrator" circuit 148 is the same type as the previously described first "intergrator" circuit 126. The output of the third "integrator" circuit 148 is coupled to the input of a fourth level detector 150. The fourth level detector 150 is the same type as the previously described second level detector 128. The fourth level detector 150 provides an output signal (PD1) when the magnitude of the input signal exceeds a predetermined level which, in the preferred embodiment, is 60mv to provide a threshold to overcome extraneous signals. The PD1 signal is utilized in the system as a circuit breaker trip signal. The positive sequence distance relay of the present embodiment operates as follows. Assuming the normal situation where there are no faults on the AC electrical power transmission line, the MI₀F, I₀Z₁ and I₀ZT signals are essentially equal to zero because under normal load conditions the phase currents are balanced and the zero sequence current (I o ) is substantially equal to zero. The ΔV₁ signal is also essentially equal to zero as there is no change in the positive sequence voltage during normal load conditions. The RTCON signal is at a logic zero and therefore restraint bias is being supplied to the summing amplifiers 112, 114, and 116 via switches 118 and 120. The magnitude of the I A1 S signal is proportional to the magnitude of the positive sequence load current on the protected system. The I A1 S signal leads the V A1 signal by approximately the replica impedance angle since the positive sequence voltage and current on the protected system are substantially in phase for a normal load condition. Because the V A1 and I A1 S signals are substantially 90° out of phase, the coincidence logic circuit, 62, switches MI₁ZT and MI₁Z₁ for 90° and I₁ZT and I₁Z₁ for the second 90°. The net inputs to the integrators 126, 140 and 148 are in the restraint direction and there is no output from the level detectors 128, 142 and 150. Assuming now a single phase fault within zone one of the protected region. During the fault condition, the positive sequence voltage and current on the system are substantially out of phase by the transmission line impedance angle with the voltage leading the current. Thus, the signals V₁ and I A1 S are substantially in phase and the coincidence logic output causes the MI₁ZT, and MI₁Z₁ signals to be switched into their respective circuits while the I₁ZT and I₁Z₁ signals are substantially equal to zero. Thus, an operate signal is applied to the summing stages 108 and 116. The associated fault detector operates causing the RTCON signal to go to a logic one and thereby remove the bias signals from the summing amplifiers 112, 114, and 116. During a single line to ground fault an unbalance exists in the currents in the protected transmission system which causes a zero sequence current to be produced by the summing amplifier 16. This zero sequence current signal in turn produces the signals I o ZT and I o Z₁, which provide restraint signals to the summing amplifiers 108 and 116. These added restraint signals prevent the PDT and PD1 units from operating on single line to ground faults. Assuming now there is a three-phase fault within zone one of the protected region. During the fault condition, the positive sequence voltage and current on the system are substantially out of phase by the transmission line impedance angle with the voltage leading the current. Thus, the signals V₁ and I A1 S are substantially in phase and the coincidence logic output causes the MI₁ZT, and MI₁Z₁ signals to be switched into their respective circuits while the I₁ZT and I₁Z₁ signals are substantially equal to zero. Thus an operate signal is applied to the summing stages 108 and 116. The associated fault detector operates causing the RTCON signal to go to a logic one and thereby remove the bias signals from the summing amplifiers 112, 114, and 116. During a three phase fault no substantial unbalance exists in the currents in the protected transmission line; therefore there is essentially no zero sequence current and the signals I o ZT and I o Z₁ are substantially zero. For a fault within the zone one relay reach, the magnitude of the MIZ₁ signal is larger than the magnitude of the V₁ restraint signal and the net input into the PD1 integrator 148 is in the operate direction. When the level of the integrator output is greater than the level detector setting a PD1 output will be produced. Because the reach of the Zone 1 unit is always less than the reach of the overreaching unit, the PDT will also produce an output for this fault. Assuming now there is a three phase fault in the reverse direction (behind) the relay. During the fault condition, the positive sequence voltage and current on the system are substantially out of phase by the transmission line impedance angle with the voltage lagging the current. Thus the signals V₁ and I A1 S are substantially 180° out of phase and coincidence logic output causes the I₁ZT, and I₁Z₁ signals to be switched into their respective circuits while the MI₁ZT and MI₁Z₁ signals are substantially equal to zero. Thus an operate signal is applied to the summing stage 110. The associated fault detector operates causing the RTCON signal to go to a logic one and thereby remove the bias signals from the summing amplifiers 112, 114, and 116. During a three phase fault no substantial unbalance exists in the currents in the protected transmission line and therefore there is essentially no zero sequence current and the signals I o ZT and I o Z₁ are substantially zero. For a fault within the blocking unit reach, the magnitude of the I₁ZT signal is larger than the magnitude of the V₁ restraint signal and the net input to the PDB integrator 140 is in the operate direction. When the level of the integrator output is greater than the level detector setting, a PDB output is produced. An additional operate signal is applied to the summing amplifier 114 by the ΔV₁ signal on the occurrence of a fault. This signal insures fast operation even on some external faults where the magnitude of the IZT operate signal may be small. After the PDB unit operates, an additional operate bias signal is added in via switch 144 to ensure a continuous blocking signal for external faults. Finally, it is assumed that there is a three-phase fault in the forward direction beyond the first zone but within the reach of the overreaching relay, PDT. During the fault condition, the positive sequence voltage and current on the system are substantially out of phase by the transmission line impedance angle with the voltage leading the current. Thus, the signals V₁ and I A1 S are substantially in phase and coincidence logic output causes the MI₁ZT, and MI₁Z₁ signals to be switched into their respective circuits while the I₁ZT and I₁Z₁ signals are substantially equal to zero. Thus an operate signal is applied to the summing stages 108 and 116. The associated fault detector operates causing the RTCON signal to go to a logic one and thereby remove the bias signals from the summing amplifiers 112, 114, and 116. During a three phase fault no substantial unbalance exists in the currents in the protected transmission line; therefore there is essentially no zero sequence current and the signals I o ZT and I o Z₁ are substantially zero. For a fault within the overreaching relay reach, the magnitude of the MIZT signal is larger than the magnitude of the V₁ restraint signal and the net input into the PDT integrator 126 is in the operate direction. When the level of the integrator output is greater than the level detector setting a PDT output will be produced. Because the assumed fault was beyond the zone one reach, the MI₁Z₁ signal will be less than the V₁ restraint signal and the net signal into the PD1 integrator 148 will be in the non-operate direction, thereby preventing a PD1 output. Use of an integrator and level detector combination for the positive sequence distance units has a number of advantages over the prior art phase angle comparator type units. Among these advantages are enhanced speed of operation for close-in severe faults. The speed of the relay system is primarily predicated on the need to prevent false tripping due to the transient overreach attributable to CCVT transient errors. One solution with phase angle comparators is to provide a fixed time delay that will override the maximum period that the CCVT transient can appear as a net operating signal. Other phase angle comparator type relays use a filter delay plus a fixed operating time imposed by the characteristic timer. The relay of the present embodiment substantially eliminates the fixed operating time associated with a characteristic timer, thereby permitting operating times in the order of two to three milliseconds for close-in severe faults that will be most critical to system stability. The operating time of the integrator level detector approach of the present embodiment can be estimated by: t=T RC ln[(|V R |+|V OP |)/|V OP |] where: V R equals the prefault restraint voltage. V OP equals the magnitude of (I fault Z relay -V). T RC equals the time constant of the integrator. ln indicates natural log. For example, in a distance unit where the restraint is limited to 0.5 per unit, T RC is 10 milliseconds, and the value of IZ-V is 1.5 per unit, the operating time will be approximately 2.9 milliseconds. The calculation assumes an average value of IZ-V. There will be a minor variation in operating time based on fault incidence angle, and there is a small filter delay in a low-pass filter incorporated in the positive sequence networks. Another advantage of the integrator/level detector approach of the present embodiment is the facility with which the relay unit can be modified to enhance the overall performance of the relay scheme. One example is the simple addition of a I₀Z R1 restraint signal in a single pole tripping and closing scheme. The I₀Z R1 restraint blocks the positive sequence distance unit from operating on single line to ground faults thus permitting the unit to initiate a three pole trip directly on interphase faults. The use of the intergrator/level detector approach of the present embodiment also adds to the security of the system as compared to prior art systems. The integrator/level detector combination will result in comparatively longer operating times on remote external faults. This increase in security is the probability that the external fault will be cleared before the relay can operate thus diminishing the possibility of a misoperation where a false channel operation might occur during the fault. As is known, the steady state coverage on the R-X diagram for positive sequence distance units must be restricted to prevent operation of the unit from maximum load flow. In the prior art schemes, the characteristic timer setting, associated with the phase angle comparator, is increased to produce a lens characteristic which moves the characteristic away from the maximum load impedance point as illustrated in Figure 4. The penalty incurred is an increase in the operating time of the unit. In the present embodiment, employing an integrator/level detector scheme, and utilizing the positive coincidence of V POL and I₁Z R as an operating signal, the negative coincidence of V POL and I₁Z R as one restraint with increased weighting compared to the positive coincidence, and V₁ as a second restraint to obtain a lenticular characteristic, results in little or no increase in operating time. However, for very heavy load flow, it may be necessary to increase the time constant of the associated integrator which will produce increase in operating time. A portion of the integration signal in the POSB out-of-step blocking relay is used as a restraint input into the PD1 relay. This additional restraint, after the inherent delays in the operation of POSB, increases the security of the PD1 relay on the transients associated with clearing an external fault just beyond the zone of the PD1 relay. As can be seen from the above detailed description, the present embodiment provides a positive sequence distance relay which has enhanced operating time based upon fault severity and which operates more quickly for close-in fault as compared to a remote end fault in the protected zone. The distance relay of the present invention also has improved discrimination between internal and external faults thereby increasing the reliability of the relay operation and the security of the protection system. It also has improved discrimination between internal and external faults on series capacitive compensated AC power transmission lines.

Claims: Protective relay for detecting faults within a predetermined overreach zone of a three phase power transmission line of an electrical power distribution system, comprising means for generating at least one relay output signal, said means comprising: (a) means (12,20) for receiving signals from the three phase power transmission line, which signals relate to the three phase voltages and currents; and characterized by (b) means for utilizing said signals relating to the three phase voltages and currents for generating at least one operate signal (MI₁ZT) having a first polarity and at least one restraint signal (I₁ZT) having second polarity opposite said first polarity, said means for generating said at least one operate signal and said at least one restraint signal comprising: (i) means (21,22) for generating a signal V₁ related to a positive sequence component of a phase voltage; (ii) means (38,42,38,60,64,30) for generating a polarizing signal V pol related to said V₁ signal; (iii) means (24,14,38,42,46,50,74) for generating a signal I₁Z₁ comprising a signal I₁ related to a positive sequence component of a phase current multiplied by a quantity Z₁, which corresponds to a replica impedance of a first protective zone of said power transmission line; and (iv) means (62,56,52,54,36,40,44,48) for comparing coincidence of said V pol and I₁Z₁ signals and generating at least a first operate signal MI₁ZT related to a first polarity of said I₁ signal multiplied by a quantity related to a replica impedance ZT of an overreach protected zone of said power transmission line, during coincidence of said V pol and I₁Z₁ signals, and generating at least a first restraint signal I₁ZT related to said I₁ signal multiplied by said overreach replica impedance Zt, said first restraint signal having a second polarity opposite said first polarity when V pol and I₁Z₁ are not coincident; (c) at least a first summing circuit means (108,112) for producing an output signal having a polarity and a magnitude which are related to the algebraic sum of the magnitude of said at least one operate signal and said at least one restraint signal coupled to the inputs of said summing circuit means, said at least one operate signal comprising said MI₁ZT signal and said at least one restraint signal comprising said I₁ZT signal and said V₁ signal; (d) at least a first integrator circuit means (126) having an input adapted to receive said output signal from said summing circuit means and an output; and (e) at least a first level detector means (128) for generating a relay output signal when an output signal from the output of said integrator circuit means is of said first polarity and has a magnitude which exceeds a predetermined level, said relay output signal from said first level detector means comprising an overreach trip signal PDT indicating a fault has occurred in said predetermined overreach zone. The protective relay in accordance with claim 1 wherein said means for generating said at least one operate signal and said at least one restraint signal comprises: (a) means (38) for generating a signal I₁Z comprising said I₁ signal multiplied by a quantity Z related to a predetermined portion of said replica impedance Z₁; and (b) means (30) for generating a polarizing signal V pol related to the difference between said V₁ and I₁Z signals. The protective relay in accordance with claim 2 additionally adapted for detecting faults within a predetermined first zone portion of said overreach zone of said three phase power transmission line, said relay additionally comprising second summing circuit means (116,146), second integrator circuit means (148) and second level detector means (50), wherein: (a) said means (50) for comparing coincidence of said V pol and I₁Z₁ signals generates (76) a second operate signal MI₁Z₁ related to the first polarity of said I₁ signal multiplied by a quantity related to a replica impedance Z₁ of said first zone, during coincidence of said V pol and I₁Z₁ signals, and generating a second restraint signal I₁Z₁ related to said I₁ signal multiplied by said first zone replica impedance Z₁, said second restraint signal having said second polarity, when V pol and I₁Z₁ are not coincident; and (b) said relay output signal from said second level detector means (150) comprises a first zone trip signal PDI indicating a fault has occurred in said predetermined first zone. The protective relay in accordance with claim 3 additionally adapted for generating a block signal PDB, said relay additionally comprising third summing circuit means (110,114), third integrator circuit means (140) and third level detector means (142), wherein: (a) said MI₁ZT and said I₁ZT signals, generated by said means (62) for comparing coincidence of said V pol and I₁Z₁, signals are coupled to said third summing circuit means (110,114) as a third restraint signal and a third operate signal respectively; and (b) said relay output signal from said third level detector means (142) comprises said blocking signal PDB indicating that a fault has occurred outside said predetermined overreach zone. The protective relay in accordance with claim 4 wherein the output signal of said first summing circuit means (108,112) is coupled to an input of said third summing circuit means (110,114) as a fourth restraint signal. The protective relay in accordance with claim 5 additionally comprising means (70,48,50,34) for increasing the magnitude of the I₁ZT, MI₁ZT, I₁Z₁ and V₁ signals from first levels to second, higher levels when the magnitude of the V pol signal exceeds a predetermined level. The protective relay in accordance with claim 6 wherein said V₁ signal is coupled to an input of each of said first, second and third summing circuit means (112,114,116) as a fifth restraint signal. The protective relay in accordance with claim 7 additionally comprising: (a) means for generating a sixth restraint signal; and (b) means for coupling said sixth restraint signal to an input of each of said first, second and third summing circuit means (110,114,108,112,116,146) during unfaulted conditions and removing said sixth restraint signal from said inputs when a fault occurs in said three phase power transmission line. The protective relay in accordance with claim 8 additionally comprising: (a) means (134) for delaying said V₁ signal by a predetermined amount; (b) means (136) for producing a signal ΔV₁ which is substantially equal to the V₁ signal minus the delayed V₁ signal; and (c) means (138) for coupling said V₁ signal to an input of said third summing circuit means (110,114) as a fourth operate signal. The protective relay in accordance with claim 9 additionally comprising: (a) means (80,84) for generating a signal I o ZT comprising a signal I o related to a zero sequence component of a phase current multiplied by said ZT replica impedance quantity; and (b) means for coupling (92,94) said I o ZT signal to an input of said first summing circuit means (108,112) as a seventh restraint signal. The protective relay in accordance with claim 10 additionally comprising: (a) means (78) for generating a signal I o Z₁ comprising said I o signal multiplied by said Z₁ replica impedance quantity; and (b) means (82,86,88,90) for coupling said I o Z₁ signal to an input of said second summing circuit means (116,146) as an eighth restraint signal. The protective relay in accordance with claim 11 additionally comprising means for generating a fifth operate signal which is applied to an input of said third summing circuit means (110,114) upon generating of said PDB signal. The protective relay in accordance with claim 12 additionally comprising: (a) means for receiving an out-of-step blocking signal POSBR from an out-of-step blocking relay; and (b) means coupling said POSBR signal to an output of said second summing circuit means (116,146) as a ninth restraint signal. The protective relay in accordance with any preceding claim wherein the or each integrator circuit means (126,148 or 140) comprises an operational amplifier providing the input and output of the circuit means and and a feedback circuit connected between said input and said output, said feedback circuit comprising resistance means and capacitance means electrically connected in parallel.

Inventors: WILKINSON STANLEY BRUCE, WILKINSON, STANLEY BRUCE
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1988
Main classification: H02H1
IPC codes: H02H3, H02H7