Semiconductor circuit device

Abstract: There is an R-S flip-flop circuit (I1, I2, Q1, Q2) having a threshold voltage of a first value (V₆₄₁). An input terminal of a Schmitt trigger Circuit (Q11, Q12, Q13, Q14, I3) having a second threshold voltage (V₆₄₂) lower than the first value and a third threshold voltage (V₆₄₃) higher than the first value is connected to an output terminal (Q) of the R-S flip-flop circuit.

Description: The present invention relates to a semiconductor circuit device and, more particularly, to a semiconductor circuit device which can prevent an output of a bistable circuit from becoming unstable. A bistable circuit has two output stable states. Fig. 1 shows an example of such a bistable circuit. This bistable circuit is an R-S flip-flop circuit comprising: a latch section consisting of two inverters I2 and I2; and N type MOS transistors Q1 and Q2 in which a set signal and a reset signal are supplied to each gate. Fig. 2 shows the operation characteristics of this flip-flop circuit. In this diagram, curve L1 indicates input and output characteristics of inverter I1 in the case where a Q output terminal is regarded as an input and a Q output terminal is regarded as an output. Curve L2 represents input and output characteristics of inverter I2 in the case where the Q output terminal is regarded as an input and the Q output terminal is regarded as an output. Each of cross points A, B, and C of curves L1 and L2 is a stable point of this flip-flop. At cross point A, the Q output terminal is set to the logic "1" level and the Q output terminal is set to the "0" level. At cross point C, the Q output terminal is set to the logic "0" level and the Q output terminal is set to the "1" level. At cross point B, both of the Q and Q output terminals are in a logically unstable state, i.e., they are set to the intermediate potential between the logics "0" and "1". This potential is almost equal to a threshold voltage value of the circuit. Therefore, when the reset signal is at the "0" level, and the set signal of the "1" level as shown in Fig. 3A is supplied to a gate of transistor Q1, the potential of the Q output terminal is set to the "1" level as shown in Fig. 3B. However, if the potential of a level lower than the "1" level as shown in, e.g., Fig. 3C or 3E was supplied to the gate of transistor Q1 due to the influence of noise and the like, the potential of the Q output terminal may be set to a logically unstable state as shown in Fig. 3D or 3F. If the potential of the Q output terminal became logically unstable due to the influence of noise and the like, an unexpected fluctuation in the circuit, which is provided at the next stage would occur. Causing the circuit to malfunction. In the article entitled "Schmitt trigger prevents clock train overlap", by R. R. Osborn in "Electronics", vol. 45, no. 14, July 3, 1972, page 86, a circuit is described in which the Q output of a flip-flop is connected to the input of a Schmitt trigger via a delay circuit. In Siemens Schaltbeispiele, Ausgabe 1976/77, Munich pages 172-175, an output of a flip-flop circuit is connected directly to a Schmitt trigger. EP-A-0154337 describes a transistor circuit with hysteresis operation. The circuit in accordance with Fig 3 of this docunent is similar to Fig. 8 of this application. It is an object of the present invention to provide a semiconductor circuit device in which an output of a bistable circut is prevented from becoming unstable due to the influence of noise and the like and the reliability of the operation is high. The object of the invention is solved by a semiconductor circuit device including a bistable circuit, comprising: a bistable circuit having threshold voltage of a first value; a Schmitt trigger circuit having a second threshold voltage and a third threshold voltage and outputting a voltage corresponding, to an output potential from said bistable circuit, and an output of the bistable circuit being connected directly to the input of the Schmitt trigger circuit characterized in that said second threshold voltage is lower than said first value, said third threshold voltage is higher than said first value and said Schmitt trigger includes a P-type MOS transistor and first and second N-type MOS transistors cornected in series between first and second potential sources, the gates of the P-type and the first and second N-type MOS transistors being commonly connected to the output of the bistable circuit, a connecting point of the first N-type MOS transistor and the P-type MOS transistor being connected to an inverter, the output of the inverter being the output of the device, drain and source of a third N-type MOS transistor being connected to the corresponding drain and source of the second N-type MOS transistor and the gate of the third N-type MOS transistor being connected to the output of the inverter. According to the semiconductor circuit device of the invention, if the output of the bistable circuit becomes logically unstable due to the influence of noise and the like, the output of the Schmitt trigger circuit is held at the preceding output level, whereas it is not fixed to the output potential of the bistable circuit, such that a highly reliabile output can be derived. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional bistable circuit; Fig. 2 is a diagram showing the operation characteristics of the bistable circuit shown in Fig. 1; Figs. 3A to 3F are diagrams showing the input and output characteristics of the bistable circuit shown in Fig. 1; Fig. 4 is a circuit diagram for explaining the first embodiment of a semiconductor circuit device according to the present invention; Figs. 5A to 5F are diagrams to be used in explaining the operation of the semiconductor circuit device shown in Fig. 4; Figs. 6 and 7 are circuit diagrams showing a semiconductor circuit device according to other embodiments of the invention, respectively; and Fig. 8 is a circuit diagram showing another example of a Schmitt trigger circuit. Fig. 4 shows a semiconductor circuit device 10 according to an embodiment of the present invention. This circuit constitutes an R-S flip-flop circuit comprising: a latch section consisting of inverters I1 and I2; and N type MOS transistors Q1 and Q2 to set or reset the latch section. An input terminal of a Schmitt trigger circuit is connected to a Q output terminal of this flip-flop circuit. Output voltage v out from the Schmitt trigger circuit is used as an output signal of the semiconductor circuit device. Threshold voltage V th1 of the flip-flop circuit is used in this case, when an input signal of the Schmitt trigger circuit falls threshold voltage V th2 is used, and when this input signal rises threshold voltage V th3 is used, all being set so as to satisfy the following relations. V th2 < V th1 < V th3 Further, it is desirable that the value of V th1 be set at an intermediate value level somewhere between V th2 and V th3 . The Schmitt trigger circuit is constituted as follows: P type MOS transistor Q11 and N type MOS transistors Q12 and Q13 are connected in a series between a terminal of power source potential V cc and a terminal of an earth potential V ss ; gates of transistors Q11, Q12, and Q13 are commonly connected to a Q output terminal; a connecting point of transistors Q11 and Q12 is connected to output terminal V out through inverter I3. Further, a drain and a source of another N type MOS transistor Q14 are mutually connected to a drain and a source of transistor Q12, respectively, a gate of transistor Q14 being controlled by an output of inverter I3, thereby obtaining the desired hysteresis characteristics. The operation of the semiconductor circuit device will now be described with reference to Fig. 5. If a set signal of the "1" level as shown in Fig. 5A is supplied to a gate of transistor Q1 when a reset signal is at the "0" level, the potential of the Q output terminal is set to the "1" level, so that output p otential V out of the Schmitt trigger circuit is also set to the "1" level as shown in Fig. 5B. On the other hand, in the case where the potential of the set signal is of a lower value than the "1" value level as shown in Figs. 5C and 5E, the output potential of terminal Q becomes logically unstable for the period of time mentioned above. Even if the potential of the Q output terminal at this time became threshold voltage Vth1 of the flip-flop circuit, this threshold voltage V th1 would still be of a lower value than the threshold voltage V th3 of the Schmitt trigger circuit at the leading time of the input signal. Therefore, the Schmitt trigger circuit is not influenced by the unstable output potential of the Q output terminal, and is held at its preceding output level. Namely, the "0" level is maintained as shown in Figs. 5D and 5F. On the other hand, if the signal of the level lower than the "1" is supplied as a reset signal when the set signal is at the "0" level, the potential of the Q output terminal will decrease from the "1" level and stop at the threshold value V th1 of the flip-flop circuit. However, the threshold voltage V th2 of the Schmitt trigger circuit is set so as to be of a lower value than V th1 , so that when the input signal falls, the output level of the Schmitt trigger circuit remains constant without being influenced by the unstable potential of the input signal. Therefore, even if the noises were input to the gate of transistor Q1 serving as a set input terminal or to the gate of transistor Q2 serving as a reset input terminal in the semiconductor circuit device such as to make the flip-flop circuit unstable, the output of the Schmitt trigger circuit can be prevented from becoming unstable due to the influence of the noise. A highly reliable output can be obtained. Figs. 6 and 7 show semiconductor circuit devices according to other embodiments of the invention, respectively. Fig. 6 shows an example of a circuit where the R-S flip-flop circuit is constituted by two NOR gates 11 and 12. Fig. 7 shows an example of a circuit in which the R-S flip-flop circuit is constituted by two NAND gates 13 and 14. Even in these semiconductor circuit devices, an effect similar to that in the device of Fig. 1 can be obtained by setting threshold voltage V th1 of the flip-flop circuit, threshold voltage V th2 when the input signal of the Schmitt trigger circuit falls, and threshold voltage Vth3 when this input signal rises, so as to satisfy the following relation: V th2 < V th1 < V th3 Fig. 8 shows another example of a Schmitt trigger circuit. This Schmitt trigger circuit is constituted in the following manner: P type MOS transistor Q22 is inserted as a load between a terminal of power source potential V cc and output terminal T2; N type MOS transistors Q23 and Q24, whose gates are commonly connected to input terminal T1, are connected in a series between output terminal T2 and a terminal of earth potential V ss . The potential at the series connecting point is changed by N type MOS transistor Q25 whose conduction is controlled by the potential of output terminal T2, thereby obtaining the desired hysteresis characteristics. If the foregoing relation among the three threshold voltages is satisfied and the Schmitt trigger circuit with the above constitution is used, a similar effect can be derived. Although the foregoing embodiments have only described the case in which the R-S flip-flop circuit was used, the invention can be also applied to a circuit such as J-K flip-flop, T flip-flop, or the like.

Claims: A semiconductor circuit device including a bistable circuit, comprising: a bistable circuit (I1, I2, Q1, Q2) having threshold voltage of a first value; a Schmitt trigger circuit (Q11, Q12, Q13, Q14, I3) having a second threshold voltage and a third threshold voltage and outputting a voltage corresponding to an output potential from said bistable circuit, and an output of the bistable circuit (I1, I2, Q1, Q2) being connected directly to the input of the Schmitt trigger circuit (Q11, Q12, Q13, Q14) characterized in that said second threshold voltage is lower than said first value, said third threshold voltage is higher than said first value and said Schmitt trigger circuit includes a P-type MOS transistor (Q11) and first and second N-type MOS transistors (Q12, Q13) connected in series between first and second potential sources (V CC , V SS ), the gates of the P-type and the first and second N-type MOS transistors (Q11, Q12, Q13,) being commonly connected to the output of the bistable circuit (I1, I2, Q1, Q2), a connecting point of the first N-type MOS transistor (Q12) and the P-type MOS transistor (Q11) being connected to an inverter (I3), the output of the inverter (I3) being the output of the device, drain and source of a third N-type MOS transistor (Q14) being connected to the corresponding drain and source of the second N-type MOS transistor (Q12) and the gate of the third N-type MOS transistor (Q14) being connected to the output of the inverter (I3). A semiconductor circuit device according to claim 1, characterized in that said first value is an almost intermediate value between said second and third values. A semiconductor circuit device according to claim 1 or 2, characterized in that said bistable circuit (I1, I2, Q1, Q2) is an R-S flip-flop circuit having a set input terminal and a reset input terminal.

Inventors: IMAI KIMIMASA, SHINYA HIROSHI, IMAI, KIMIMASA, SHINYA, HIROSHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: H03K3
IPC codes: H03K3