Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure

Abstract: A process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure. After the processing of polysilicon layers (14, 18), dielectric layers (12, 16, 20, 26), an epitaxial region (24) and a nitride layer (28), a second substrate (30) is bonded to the nitride layer (28) and the first substrate (10) is removed. This allows for an epitaxial region (24) which is isolated from the substrate (30).

Description: This invention generally pertains to a process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure. Generally, in semiconductor devices and the like, it is desirable to have a high performance device which takes up a relatively small amount of space. Commonly, semiconductor devices have suffered performance wise because there has been a relatively high amount of base-collector and collector-substrate capacitance. Additionally, defects which occur during growth of the epitaxial region result in decreased yield. Therefore, it is highly desirable that a semiconductor device having a relatively low capacitance along with a limited number of defects in the epitaxial region be manufactured. The present invention allows for the processing of a semiconductor device using a pedestal structure which utilizes a relatively small area. Further, the semiconductor device has an extremely high quality epitaxial region and capacitance is reduced due to a diffusion barrier dielectric which is disposed between silicon regions. The present invention pertains to an improved process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure A process in accordance with the present invention comprises the steps of: providing a first substrate; forming a first dielectric layer on said first substrate; forming a doped first polysilicon layer on said first dielectric layer; patterning and etching said doped first polysilicon layer; forming a second dielectric layer on said first polysilicon layer; forming a doped second polysilicon layer on said second dielectric layer; patterning and etching said doped second polysilicon layer; forming a third dielectric layer on said second polysilicon layer; etching an opening through said dielectric layers and said polysilicon layers, said opening extending to said first substrate; forming an epitaxial region on said first substrate in said opening; forming a last dielectric layer on said epitaxial region and said third dielectric layer, the invention being characterized by the following steps: bonding a second substrate to said last dielectric layer; inverting said semiconductor device; removing said first substrate; etching a plurality of contact openings in said semiconductor device; and forming electrical contacts in said contact openings. Thus, the present invention provides a process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure which implements a single bonding step of a wafer to achieve the silicon-on-insulator structure. The inversion also allows for the avoidance of defects in the epitaxial region itself. The inversion is performed without the fabrication of tubs so that each device uses less space and the semiconductor device layout may be varied. Additionally, a nitride layer may be formed on the last dielectric layer so as to act as a diffusion barrier between the collector and the new substrate thereby reducing the base-collector and collector-substrate capacitance and allows for a semiconductor device capable of a much higher performance. A further advantage provided by the invention is that the semiconductor device has improved isolation of the epitaxial region. Preferably, after the orginal substrate is removed, the epitaxial region is etched below the first dielectric layer. This allows for defects introduced in the epitaxial region during substrate removal to be removed. The process may be varied so that many types of semiconductor devices including PNP and NPN bipolar devices, vertical MOSFETS and horizontal MOSFETS may be fabricated using the present invention. A further advantage is that the process in accordance with the present invention allows for the highest quality material of the epitaxial region to be where the emitter will be processed. The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description, by way of example only, with reference to the accompanying drawings in which: FIGS. 1-15, 17, 19 and 20 are highly enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure during various steps of processing in accordance with the invention; and FIGS. 16, 18 and 21 are highly enlarged cross-sectional views of inverted silicon-on-insulator semiconductor devices having pedestal structures in accordance with the invention. Referring specifically to FIGS. 1-7, highly enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure are shown during initial stages of processing. Initially, a first substrate, 10, is provided. A first dielectric layer, 12, is then formed on first substrate 10. Next, a first polysilicon layer, 14, is deposited on first dielectric layer 12. Once first polysilicon layer 14 has been deposited, first polysilicon layer 14 is doped in a first conductivity type. In this embodiment, the first conductivity type is P+. Following the doping, first polysilicon layer 14 is patterned and etched. Next, a second dielectric layer, 16, is formed on first polysilicon layer 14. This is followed by the deposition of a second polysilicon layer, 18. Second polysilicon layer 18 is doped in a second conductivity type. In this embodiment, the second conductivity type is N+. It should be understood that first polysilicon layer 14 and second polysilicon layer 18 are doped in opposite conductivity types. Once the doping of second polysilicon layer 18 has been accomplished, second polysilicon layer 18 is patterned and etched in a predetermined manner. A third dielectric layer, 20, is now formed on second polysilicon layer 18. Referring specifically to FIGS. 8-11, highly enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure are shown during various stages of processing. Once third dielectric layer 20 has been formed, an opening, 22, is patterned and etched. Opening 22 extends to first substrate 10 through first dielectric layer 12, second dielectric layer 16, third dielectric layer 20, first polysilicon layer 14 and second polysilicon layer 18. Once opening 22 has been etched, an epitaxial region, 24, is grown therein. Epitaxial region 24 is selectively grown so that it grows upward from first substrate 10. During or directly following the growth of epitaxial region 24, a collector, 44, is implanted in epitaxial region 24. It should be understood that collector 44 will be of the same conductivity type as second polysilicon layer 18, here, N+. Following the implantation of collector 44, a fourth dielectric layer, 26, is formed on third dielectric layer 20 and epitaxial region 24. Next, a nitride layer, 28, is deposited on fourth dielectric layer 26. A second substrate, 30, is now bonded on nitride layer 28. Second substrate 30 may be bonded many ways however, epoxy bonding is commonly used. Other bonding methods may include deposition of an oxide layer (not shown) on nitride layer 28 before bonding. This process enables the silicon-on-insulator structure to be achieved using only one bonding step. Once second substrate 30 has been bonded to nitride layer 28, first substrate 10 may now be removed. Generally, first substrate 10 is removed by either grinding, etching or a combination of both grinding and etching. However, it should be understood that other methods of removing first substrate 10 may be employed. Following the removal of first substrate 10, epitaxial region 24 is reduced so that a first surface, 54, of epitaxial region 24 lies in plane which is below the uppermost surface, 56, of first dielectric layer 12 (see FIG. 11). This reduction allows for the removal of any defects formed during the removal of first substrate 10. Therefore, higher performance may be obtained because epitaxial region 24 is of a high quality. It should be understood that although the inverting step occurs following the removal of first substrate 10 in this embodiment, it may occur anytime after the deposition of nitride layer 28. Referring specifically to FIGS. 12-15, highly enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure are shown during various stages of processing. Following the inversion of the semiconductor device, a base, 46, is implanted in epitaxial region 24. Base 46 must correspond to the conductivity type of first polysilicon layer 14, P+ in this embodiment. FIG. 12 shows diffusion regions, 50, wherein the dopant of the conductivity type of first polysilicon layer 14 has diffused into epitaxial region 24 and base 46 of epitaxial region 24. Following the implantation of base 46, a sidewall spacer oxide layer 32, is formed on first oxide layer 12 and epitaxial region 24. Following the formation, sidewall spacer oxide layer 32 is partially etched over epitaxial region 24. This allows for the formation of sidewall spacers, 34. An emitter contact opening, 52, lies between sidewall spacers 34. Once sidewall spacers 34 have been processed, an emitter, 48, may be implanted in epitaxial region 24. Again, due to the reduction of epitaxial region 24, the emitter is very high quality epitaxial material. Generally, emitter 48 is of the same conductivity type as collector 44. Sidewall spacers 34 serve to reduce the size of emitter 48. The size of emitter 48 may be reduced even further than is shown depending upon how far sidewall spacers 34 reduce emitter contact opening 52. Following the formation of emitter 48, a first contact opening, 36, and a second contact opening, 38 are patterned and etched. First contact opening 36 extends to first polysilicon layer 14 while second contact opening 38 extends to second polysilicon layer 18. In this embodiment, first contact opening 36, second contact opening 38 and emitter contact opening 52 have contact polysilicon, 40, deposited therein. This is can be done by depositing contact polysilicon 40 in the contact openings until it is over the thick oxide of first oxide layer 12 and sidewall spacer oxide layer 32. Next, contact polysilicon 40 and the thick oxide are planarized and etched back. Following the deposition and planarization of contact polysilicon 40, contact polysilicon 40 is doped. Contact polysilicon 40 in first contact opening 36 is doped in the same conductivity type as first polysilicon layer 14. Contact polysilicon 40 in second contact opening 38 is doped in the same conductivity type as second polysilicon layer 18. Contact polysilicon 40 in emitter contact opening 52 is doped in the same conductivity type as emitter 48. The formation of emitter 48 may occur as contact polysilicon 40 in emitter contact opening 52 is doped rather than prior to the deposition of contact polysilicon 40. Once contact polysilicon 40 is doped, the device is annealed to insure proper diffusion. Referring specifically to FIG. 16, a highly enlarged cross-sectional view of an inverted silicon-on-insulator semiconductor device having a pedestal structure is shown. The device in this embodiment is bipolar. A plurality of metal contacts, 42, are processed on first contact opening 36, second contact opening 38, and emitter contact opening 52. Metal contacts 42 are processed by methods which are well known in the art. Referring specifically to FIGS. 17-18, highly enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure are shown during and following processing, respectively. This embodiment of the present invention shows a vertical MOS device. After opening 22 has been partially etched so that edges, 70, of second polysilicon layer 18 have been exposed, nitride edges, 58, remain on each exposed edge 70 of second polysilicon layer 18 following the formation and etching of a nitride edge layer (not shown). Next, opening 22 is etched through first polysilicon layer 14 to expose edges, 74, of first polysilicon layer 14. Then, oxide edges, 76, are grown on edges 74. Once this has been done, nitride edges 58 are removed so that edges 70 are exposed in opening 22. Oxide edges 76 serve to isolate first polysilicon layer 14 from epitaxial region 24. It should be understood that there are many ways in which nitride edges 58 and oxide edges 76 may be formed. In this embodiment of the present invention, sidewall spacers 34 (See FIG. 13) may or may not be utilized. They are not needed, however, they may be included so that there is minimal variance between the processing of a bipolar device and a vertical MOS device. Additionally, because FIG. 18 is an MOS device, it is shown to have a drain, 60, a source, 62, a gate, 64, and a bulk, 66. The processing steps of the vertical MOS device are otherwise essentially the same as those of the bipolar device. Referring specifically to FIGS. 19-21, highly-enlarged cross-sectional views of an inverted silicon-on-insulator semiconductor device having a pedestal structure are shown during and following processing, respectively. This embodiment of the present invention shows a horizontal MOS device. Following the reduction of epitaxial region 24, a gate oxide layer, 68, is formed on epitaxial region 24. FIG. 20 shows that this embodiment includes a third contact opening, 72. Third contact opening 72 extends to first polysilicon layer 14. FIG. 21 shows that third contact opening 72 becomes the contact for drain 60 while first contact opening 36 becomes the contact for source 62. Additionally, second contact opening 38 becomes the contact for bulk 66. It must be understood that drain 60 and source 62 must be completely separated. Again, sidewall spacers 34 may or may not be included for the same reasons discussed earlier. In the present invention, first dielectric layer 12, second dielectric layer 16, third dielectric layer 20 and fourth dielectric layer 26 may be comprised of an oxide, a nitride, or various combinations of oxides and nitrides. Additionally, it should be understood that this process of making an inverted silicon-on-insulator semiconductor device having a pedestal structure may be used to fabricate a multiplicity of devices on a single substrate. The pedestal structure of the present invention enables a semiconductor device which is more compact to be processed. Further, nitride layer 28 serves as a diffusion barrier between collector 44 and second substrate 30. Because of the improved isolation of epitaxial region 24 in the present invention, base-collector and collector-substrate capacitance is greatly reduced and the result is much higher performance in the semiconductor device.

Claims: A process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure made by the steps of, providing a first substrate (10); forming a first dielectric layer (12) on said first substrate (10); forming a doped first polysilicon layer (14) on said first dielectric layer (12); patterning and etching said doped first polysilicon layer (14); forming a second dielectric layer (16) on said first polysilicon layer (14); forming a doped second polysilicon layer (18) on said second dielectric layer (16); patterning and etching said doped second polysilicon layer (18); forming a third dielectric layer (20) on said second polysilicon layer (18); etching an opening (22) through said dielectric layers (12, 16, 20) and said polysilicon layers (14, 18), said opening (22) extending to said first substrate (10); forming an epitaxial region (24) on said first substrate (10) in said opening (22); forming a last dielectric (26) layer on said epitaxial region (24) and said third dielectric layer (20), the invention being characterized by the following steps: bonding a second substrate (30) to said last dielectric layer (26); inverting said semiconductor device; removing said first substrate (10); etching a plurality of contact openings (36, 38) in said semiconductor device; and forming electrical contacts (40) in said contact openings (36, 38). The process of claim 1 further comprising the steps of: forming a collector (44) in the epitaxial region (24) either during or after the growth of said epitaxial region (24); forming a base (46) in said epitaxial region (24); and forming an emitter (48) in said epitaxial region (24). The process of claim 2 wherein means (34) for limiting the emitter size is processed before the implantation of said emitter (48). The process of claim 1 further comprising the steps of: forming a gate oxide layer (68) on the epitaxial region (24); forming a gate (64) on said gate oxide layer (68); and forming a source (62) and a drain (60) in the first polysilicon layer (14), said source (62) and drain (60) not being physically or electrically connected. The process of claim 1, 2, 3, or 4 further comprising the step of forming a nitride layer (28) on said last dielectric layer (26). The process of claim 5 wherein the inverting step may be performed, anywhere between the depositing a nitride layer step and the patterning and etching step. The process of any preceding claim wherein the epitaxial region (24) is etched so that a first surface (54) of said epitaxial region (24) is in a plane below the plane which includes the first surface (56) of the first dielectric layer (12), said step occurring after the semiconductor device is inverted. The process of claim 2 further comprising the steps of: forming a sidewall spacer oxide layer (32) on the first dielectric layer (12) and the epitaxial region (24); and partially etching the portion of the said sidewall spacer oxide layer (32) which covers said epitaxial region (24) thereby forming sidewall spacers (34). The process of any preceding claim further including the step of forming oxide edges (76) in said opening (22) on said first polysilicon layer (14).

Inventors: KOURY DANIEL N JR, KOURY, DANIEL N., JR.
Applicants: MOTOROLA INC, MOTOROLA INC.
Application year: 1988
Main classification: H01L21
IPC codes: H01L29, H01L27, H01L21