Semiconductor memory capable of improving data rewrite speed

Abstract: A semiconductor memory device is disclosed which comprises, as shown in Fig. 1, a pair of column lines (BL₁, BL₁ ), memory cells (MC₁, MC₂) connected to the corresponding column lines, sense amplifier (10) con­ nected to the column lines, row lines (WL₀, WL₁) for selecting the memory cells in accordance with a row address signal, and first and second transistors (Q₁₀, Q₁₁) having their current paths connected between the column lines and a fixed potential supply terminal (14) supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors (Q₁₀, Q₁₁) are connected to the first and second row lines (WL₁₀, WL₁₁) for data rewrite operation which can be selected independently of the row line.

Description: The present invention relates to principally a semiconductor memory device and, in particular, a semiconductor memory device, such as an image memory device, for allowing data to be rewritten at high speed into memory cells. As an image memory device of this type, a dual port memory device has widely been employed which includes a random access memory (RAM) for allowing data access to be gained to any address and serial access memory (SAM) for allowing data to be accessed in a serial fashion. The general way of using the dual port memory is to enable an image display to be made by allowing data which are written into cells on a given row in RAM to be transferred to SAM and the data which are so transferred to be output from SAM in a serial fashion. It is necessary that, if all image data are to be cleared at a time for a short period of time, all the data transferred from RAM to SAM be set to the same contents, that is, "1s" or "0s". In other words, it is necessary that all the data which are randomly stored as a varying combination of "1s" or "0s" on a given row of RAM be rewritten as the same data at a time. In a memory array of a conventional RAM as shown in Fig. 3, a page mode is usually employed to allow cell data on a given row to be rewritten all as the same contents. As appreciated from a timing chart of Fig. 4, with a row address strobe signal RAS at a low level, a given row in RAM is selected to enable, for example, a row line WL₀. Then the column of RAM is sequentially selected by a column address strobe signal CAS . Upon enabling, for example, a column select signal CSL₁ by an address ADR, the data which is output from an I/O buffer is written into memory cell MC₁ via column line BL₁. In the page mode, the columns are sequentially selected to allow data to be written column by column into all those cells associated with the row line WL₀. This method is effective because is directly uses the RAM function. However, it takes too long a time to rewrite RAM data as set forth above. That is, according to this method a time Cn × Tpc is required in rewriting those data on a given row, where Cn: the number of columns in a memory array and Tpc: the page mode cycle time Some data rewriting system is also employed to obtain those cell data on the row as all "0s" or all "1s" at a time instead of writing data column by column as in a page mode. This system may be used in an ordinary RAM, such as the memory array of a type shown in Fig. 3, in which case the operation timing is as shown in Fig. 5. That is, the system is of such a type that, subsequent to selecting a row in accordance with the row address with a row address strobe signal RAS set to a low level, each column is selected irrespective of the row address and then data "1s" or "0s" are caused to be written from an I/O buffer into all the cells which are connected to one row. By the use of this system all the cell data on the row which are associated with an ordinary RAS cycle time can be set to the same level and data write operation can be achieved at high speed on that system. However, this system encounters a problem as set forth above. Where use is made of a system capable of writing all associated data into those cells on a given row at a time, a write-in buffer of a greater capability is required to prevent an error upon the write-in of data. As a result, that buffer becomes very large in size. Furthermore, at the write time a fairly large current temporarily flows, causing a power source-induced noise. It is also difficult to combat the aforementioned noise problems. Prior art document EP-A-0 172 112 which forms the basis of the preamble of claim 1 discloses a semiconductor memory device having a data inverting circuit for selectively inverting an input/output data of a sense amplifier in such a way that the charging states of respective memory cells connected to the two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells can be cleared at the same time. Further, prior art document "Patent Abstracts of Japan", Vol. 11, No. 260 (P-608), August 22, 1987, and JP-A-62 065 288 describes a semiconductor memory device wherein a storage cell in the intersection between one word line selected through a line address decoding circuit by an address signal inputted from the external and a bit line selected through a column address decoding circuit similarly is selected from a storage cell array where storage cells are arranged in a matrix, and read from or write to this storage cell is performed. OR circuits which operate OR between decoded results and an all set/reset request signal are provided following line address decoding circuit and column address decoding circuit, and the word line and the bit line are selected by OR signals of OR circuits. Thus, data "1", or "0" is written in all storage cells simultaneously. It is object of the present invention to provide a semiconductor memory device, such as a semiconductor image memory device, which rewrites the data of memory cells all at a time for simultaneous clearing of images. To solve this object the present invention provides a semiconductor memory device as specified in claim 1. A semiconductor memory device as shown in Fig. 1, comprises a pair of column lines BL₁, BL₁ , memory cells MC₁, MC₂ connected to the column lines, switching transistors Q₁, Q₂ having their conductive paths opened and closed, row lines WL₀, WL₁ for selecting the memory cells in accordance with a row address signal, and first and second transistors Q₁₀ and Q₁₁ having their current paths connected between the column lines and fixed potential supply terminal 14 which is supplied with a positive power source potential or a ground terminal, in which first and second data rewrite row lines WL₁₀ and WL₁₁ are connected to the gates of first and second transistors and can be selected independently of the row lines and sense amplifier 10 is provided which is connected to the column lines. In the semiconductor memory device, a potential on the column line can be set to a low or a high level by selecting the data rewrite row lines. By so doing, the same data can be written into the memory cells on a selected row all at a time without the need of forcedly writing data via a write-in buffer into the memory cells. Such a write method is called as "a flash write". As a result, this semiconductor memory device can set image data to an initial state all at a time without the need of providing any bulky buffer of larger capacity as encountered in the above conventional semiconductor memory device and without involving a power source noise induced at the time of writing. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a semiconductor memory device; Fig. 2 is a timing chart for explaining a data rewrite operation on the semiconductor memory device shown in Fig. 1; Fig. 3 is a circuit diagram showing a conventional semiconductor memory device; Figs. 4 and 5 are a timing chart for explaining a data rewrite operation on the conventional semiconductor memory device; Fig. 6 is a circuit diagram, different from that in Fig. 1, showing a further semiconductor memory device; Fig. 7 is a circuit diagram showing an embodiment of the present invention; Fig. 8 is a pattern concept diagram showing the circuit diagram in an IC form; and Fig. 9 is a circuit diagram showing another embodiment of the present invention. The embodiments of the present invention will be explained below with reference to the accompanying drawings. In the semiconductor memory device shown in Fig. 1, circuit elements on one column are shown for brevity's sake, noting that the other columns have the same configuration as that of Fig. 1. That is, as in the conventional semiconductor memory device of Fig. 3, memory cells MC₁ and MC₂ to be selected by row lines (WL₀ and WL₁), respectively, as well as N-channel MOS transistors Q₁₀ and Q₁₁ for data rewrite operation, are connected to column lines (a pair) BL₁ and BL₁ , respectively, in the semiconductor memory device. Memory cell MC₁ is constituted by N-channel MOS transistor Q₁ connected at its gate to row lines WL₀ and capacitor C₁. Memory cell MC₂ is constituted by N-channel MOS transistor Q₂ connected at its gate to row line WL₁ and capacitor C₂. N-channel MOS transistor Q₁₀ for data rewrite operation is connected, at its current path, between column line BL₁ and a ground terminal or a positive power source terminal and, at its gate, to row line WL₁₀ which is provided for data rewrite operation. N-channel MOS transistor Q₁₁ is connected, at its current path, between column line BL₁ and a ground terminal and at its gate to row line WL₁₁. Row lines WL₁₀ and WL₁₁ can be selected independently of row lines WL₀ and WL₁ which select those associated memory cells. For the other columns, two N-channel MOS transistors for data rewrite operation are connected in the same fashion as set forth above with row lines WL₁₀ and WL₁₁ connected in a similar way. The pair of column lines BL₁ and BL₁ are connected to common data line I/O, I/O via sense amplifier 10 and column select circuit 12. Column select circuit 12 is constituted by N-channel MOS transistors Q₂₀ and Q₂₁ and switching controlled by column select signal CSL which is enabled in accordance with the contents of the column address. The data rewrite operation of the semiconductor memory device (Fig. 1) will be explained below with reference to the timing chart shown in Fig. 2. Let it be assumed that 14 denotes a ground potential. The circuit operation will be explained below in connection with writing "0" data into memory cells on each column which is connected to row line WL₀. First with the row address strobe signal RAS set to a low level the corresponding row address is taken up. This is an ordinary operation. If the flash write mode is selected at the WE state upon the fall of the strobe signal RAS , row line WL10 is also selected until sense amplifier 10 is operated. As a result, transistors Q₁ and Q₁₀ are rendered conductive. A potential on column BL is determined by a capacitance of capacitor C₁, capacitance C b on column line BL₁ and drive capability of transistor Q₁₀. Where, for example, data "1" is being stored in the memory cell MC₁ with a charge accumulated on capacitor C₁, unless transistor Q₁₀ is rendered conductive, a potential on column line BL₁ becomes higher than a precharging potential, that is, a level involved before the enabling of row line WL₀. If, however, at the time of selecting row line WL₀, row line WL₁₀ is also selected to place transistor Q₁₀ in the conductive state, then the charge which is accumulated on capacitor C₁ is discharged into a ground terminal via column line BL₁ and transistor Q₁₀ so that a potential on column line BL₁ becomes smaller in level than the potential involved at the precharging time. When, in this state, sense amplifier 10 is driven, column line BL₁ and BL₁ can be set to the low and high potential levels, respectively. The row address strobe signal RAS being placed back in the high voltage level, both row lines WL₀ and WL₁₀ are rendered in the non-selective state to allow data "0" to be written into memory cell MC₁. Similarly, data "0" is written into memory cells on the respective row line, all at a time, which are connected to row line WL₀. Although the semiconductor memory device has been explained as writing data "0" into all the memory cells on the respective row line at a time, it can equally be applied to the case where, if associated cell data are "0", data "0" are rewritten onto these cells on the associated row. Where, on the other hand, data "1" is written into memory cell MC₁, row lines WL₀ and WL₁₁ need only to be selected simultaneously. Data "0" being stored in memory cell MC₁, the potential on column line BL₁ is dropped, upon the selection of row line WL₀, down to a predetermined level which is determined by a capacitance division at the location of memory cell MC₁ and column line BL₁. Since, however, row line WL₁₁ is enabled, transistor Q₁₁ is turned ON, causing column line BL₁ to be placed at a lower level than that at column line BL₁. Upon the subsequent driving of sense amplifier 10, column lines BL₁ and BL₁ are placed at the high and low potential level, respectively. It is, therefore, possible to write "1" into memory cell MC₁. Data "1" being initially stored in memory cell MC₁, needless to say, the rewriting of data "1" can further be facilitated. Although an explanation has been made in connection with memory cell MC₁ on the column line BL₁ side, the same thing can also be true of the memory cell, such as MC₂, on the column line BL₁ side. In the memory device as set forth above, the same data can be rewritten into all cells on any row, at a time, during an ordinary RAS cycle. Since the present semiconductor memory device is not of such a type that data is not forcedly rewritten into the memory cells from a write-in buffer, the current drive capability of that buffer need not be set to an unnecessarily great extent. It is possible, to perform a data rewrite operation at high speed without involving the aforementioned power source-induced noise, bulkiness of the write-in buffer, and so on. In the normal data write operation, the normal row lines have only to be selected without selecting the data rewrite row lines WL₁₀ and WL₁₁. A similar data rewrite operation can be performed even in the case where one terminal 14 of the data rewrite transistor is connected to a positive power source terminal instead of being connected to the ground terminal. In this case, however, the convents of the rewrite data are the opposite to those set out above, upon the selection of row lines WL₁₀ and WL₁₁. As one practical application, first and second row lines WL₁₀ and WL₁₁ for data rewrite operation are employed, as shown in Figs. 6 and 8, in a revised circuit pattern of the conventional memory device. As shown in Fig. 8, the addition of the aforementioned data write-only lines to the revised memory device results in column lines BL and BL of a different length and hence in an unbalanced static capacitance relative to the respective column lines. This causes a poor margin in terms of the detection function of sense amplifier 10. This is an ordinary operation. If the flash write mode is selected at the WE state upon the fall of the strobe signal RAS , row line WL10 is also selected until sense amplifier 10 is operated. As shown in Fig. 7, therefore, switching transistors Q₇ and Q₈ are inserted partway between the column lines and the fixed data write-only lines and, except in the case where the fixed data are flash-written with the use of the aforementioned row lines, the aforementioned transistors are turned OFF so as to prevent a possible unbalanced static capacitance relative to the respective column lines. By so doing, the degradation of the "sense margin" is improved. In this connection it is to be noted that the aforementioned transistors thus inserted are of a MOS type and that the write data supply terminals are grounded or connected to a positive power terminal. As shown in Fig. 8, a buffer A may be connected to data input terminal to receive an input signal. As shown in Fig. 9, a signal line F/WG which is connected to the gates, and shared between, transistors Q7 and Q8 receives a gate input signal at the flash-write time and is selected at the time of a flash-write mode immediately subsequent to the selection of the row line. The signal line F/WG serves to provide a drive signal for WG data transfer to the aforementioned switching transistors. In connection with Fig. 9, an explanation will be given of how to write "1" data into all cells on row line WL₀. The data to be written there is determined prior to the start of the write-in cycle. In this case, the inverter input signal F/WD IN goes low because data "1" is written into associated cells. Select row line WL₀ is selected in this case. Before the drive of sense amplifier 10, signal F/WG goes high and a potential on column line BL is raised due to the drive capability of inverter A₁. Thereafter, sense amplifier 10 is driven so that the potential on the column line is determined. The potential on the column line naturally becomes equal to a power source potential and select row line WL₀ is placed in the non-selected state. Data "1" is written into the corresponding cell capacitance C1. Where the data "0" is to be written into all cells on row line at a time, an input signal F/WD IN to inverter A₁ goes high so that the aforementioned write operation can be achieved. According to the present invention a semiconductor memory device, such as an image memory device in particular, is obtained which can rewrite data at high speed without involving a power source-induced noise as well as the bulkiness of the write-in buffer.

Claims: A semiconductor memory device comprising a pair of column lines (BL₁, BL₁ ), memory cells (MC₁, MC₂) connected to the associated column lines, respectively, a sense amplifier (10) connected to said pair of column lines and driving the lines of said pair of column lines to opposite potential levels at a data write time and row lines, (WL₀, WL₁) for simultaneously selecting the memory cells connected to said pair of column lines in accordance with a corresponding address signal, writing means including switching transistors (Q7, Q8) for writing data "1" or "0" into the memory cells (MC₁, MC₂), said pair of column lines (BL₁, BL₁ ) being connected to corresponding write data supply terminals (IN, IN ) via said switching transistors which are turned ON at said data write time and turned OFF at the other time, characterized in that one of said write data supply terminals (IN, IN ) is connected to a corresponding one of said switching transistors (Q7, Q8) via an inverter (A₁) which is supplied with write-in data and the other write data supply terminal (IN, IN ) is placed in an electrically floated state. The semiconductor memory device according to claim 1 characterized in that said switching transistors (Q10, Q11) have their current paths connected between said pair of lines (BL₁ BL₁ ) and their connection node connected to a fixed potential supply terminal (14) supplied with a positive power supply potential or a ground potential, and said first and second transistors (Q10, Q11) are connected at their gates to first and second data rewrite row lines (WL₁₀, WL₁₁) which can be selected independently of said row lines. The semiconductor memory device according to claim 1 or 2, characterized in that said memory cells (MC₁, MC₂) each comprise a transistor (Q1 or Q2) and capacitor (C₁ or C₂). The semiconductor memory device according to claim 1, characterized in that said write data supply terminals (IN, IN ) are grounded or connected to a positive source terminal. The semiconductor memory device according to claim 1, characterized in that a common signal line (F/WG) is connected to the gates of said switching transistors (Q7, Q8). The semiconductor memory device according to claim 5, characterized in that when a potential on said common line (F/WG) becomes a predetermined level subsequent to the selection of said column and row lines and a potential on said column line (BL) becomes a predetermined level, said sense amplifier sets said potential on said column line to a predetermined level to allow predetermined data "0" or "1" to be written into associated cells.

Inventors: KIRYU MASAKAZU C O PATENT DIVI, MAGOME KOICHI C O PATENT DIVIS, OHSHIMA SHIGEO C O PATENT DIVI, SAHARA HIROSHI C O PATENT DIVI, TODA HARUKI C O PATENT DIVISIO, KIRYU, MASAKAZU C/O PATENT DIVISION, MAGOME, KOICHI C/O PATENT DIVISION, OHSHIMA, SHIGEO C/O PATENT DIVISION, SAHARA, HIROSHI C/O PATENT DIVISION, TODA, HARUKI C/O PATENT DIVISION
Applicants: TOSHIBA KK, TOSHIBA MICRO CUMPUTER ENG, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION
Application year: 1988
Main classification: G11C7
IPC codes: G11C11, G11C7