RECEIVER

Abstract: The tuning circuit is served with the station selecting data in synchronism with the clock signals and is tuned to a desired broadcasting frequency. A detecting circuit determines whether the tuning circuit is selecting the station or not. A switching circuit automatically stops the generation of clock signals from the microcomputer when the station selecting operation of the tuning circuit is finished by the output of the detecting circuit.

Description: The present invention relates to a receiver, such as an FM or AM radio receiver or a television receiver. The invention is more particularly concerned with a receiver of the type comprising means for changing a desired broadcast frequency; a microcomputer having a clock signal generator and which is responsive to the desired frequency changing means and operable to supply station selecting data which is indicative of the desired broadcast frequency and which is clocked by the clock signal; and tuning means including a phase-locked-loop which receives the clocked station selecting data and tunes the receiver to the desired broadcast frequency. An example of an FM radio receiver of this type is shown in Fig. 1. A somewhat similar receiver, but for television, is described in patent specification US-A-4,525,866. An FM broadcast signal (in a range of 76 to 90 MHz in Japan) received at an antenna 1 is supplied to a front end 2. An intermediate frequency signal delivered from the front end 2 is supplied through an intermediate frequency amplifier 3 to an FM detector 4. A stereo mixed-wave signal delivered from the FM detector 4 is supplied to a stereo multiplex decoder (stereo demodulator) 5 by which left and right audio signals are developed at output terminals 6L and 6R. Reference number 7 denotes a PLL (phase-locked-loop) circuit. As is well known (not shown in detail), a local oscillation signal Fout from the front end 2 is divided by N in a 1/N frequency-divider provided within the PLL circuit 7 and compared with a reference oscillation signal. The resulting error signal therefrom is supplied through a low-pass filter to the front end 2 as a tuning control voltage Vt. Reference numeral 8 designates a controller that might be formed of a microcomputer. The fact that the dividing ratio of the 1/N frequency-divider in the PLL circuit 7 can be controlled by the controller 8 is carried out by using the system disclosed in patent specifications US-A-4,592,078 and US-A-4,525,866 and such operation therefore need not be described in detail. The controller 8 is connected with a crystal oscillator 9 forming a clock signal generator which generates a clock signal with frequency of several MHz, for example, 4 MHz. One and the other ends of the crystal oscillator 9 are grounded via capacitors 10 and 11, respectively. A key input apparatus 12 is connected to the controller 8, and a station selection or the like is carried out by operating the key switch of the key input apparatus 12. When a station is selected, the controller 8 supplies data indicative of N for the frequency-dividing ratio 1/N to the PLL circuit 7, thus changing the frequency-dividing ratio 1/N to select the station. In practice, the data indicative of N corresponding to the receiving frequency is supplied from the controller 8 to the PLL circuit 7 in synchronism with the clock signal. After the data N having a predetermined number of bits is transferred, a latch signal is supplied thereto so that the data N is latched in a data register connected to the 1/N frequency-divider in the PLL circuit 7, and thus the frequency-dividing ratio 1/N is changed to select the station. A display apparatus 13 is connected to the controller 8, and the display apparatus 13 is supplied with display data when a station is selected and so on. The display displays a channel of a station selected or the like. In practice, display data is supplied from the controller 8 to the display apparatus 13 in synchronism with the clock signal and the latch signal is finally supplied thereto, whereby the display apparatus 13 latches and displays the display data. The controller 8 supplies a switching signal of, for example, narrow band and wide band to the intermediate frequency amplifier 3 so that the band width thereof is controlled. In the FM radio receiver of the example shown in Fig. 1, during the reception, the controller 8 successively generates clock signals so that the harmonic components of the 4 MHz clock signal are supplied to the front end 2. There is a risk that a beat interference with the receiving frequency will be caused. To avoid such a defect, in the art there is a limitation that a substrate for a signal system and a substrate for a digital system such as the microcomputer of the like have to be spaced apart from each other. Further, there is a problem that a power source voltage is fluctuated by the clock signal and the fluctuated component of the power source voltage is contained in the output audio signal as a noise, thus a sound quality being deteriorated. In view of the above aspects, the present invention intends to improve an S/N ratio during reception and to increase freedom with which substrates or the like may be located. In accordance with the present invention, a receiver of the above-mentioned general type is characterised by: a circuit for detecting whether or not the desired broadcast frequency is being changed; and a switching circuit responsive to the frequency change detecting circuit for stopping the generation of the clock signal for the microcomputer when the desired broadcast frequency is not being changed whilst permitting the phase-locked-loop to remain in a closed loop. Therefore, the generation of clock signals from the microcomputer is automatically stopped when the station selection operation is finished, and so the generation of clock signals is stopped during the normal reception. Thus, it is possible to provide a receiver in which upon reception, the harmonic components of the clock signal can be avoided from being supplied to the front end with no beat interference. Also, the power source voltage can be prevented from being fluctuated by the clock signal. Patent application JP-A-49131336 describes a receiver which includes a phase-locked-loop. The phase-locked-loop is a closed loop when a station is being selected. However, the operation of the phase-locked-loop is stopped and it becomes an open loop once the station has been selected. Accordingly, if there is any change of, for example, the capacitance of a varicap diode in a voltage controlled oscillator of the tuning means caused by, for example, changing temperature, the receiver will drift out of tune. In contrast, in the present invention, the phase-locked-loop remains in a closed loop once a station has been selected. Specific embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing an example of the prior art; Fig. 2 is a block diagram showing an embodiment of the present invention; Figs. 3 and 4 are waveform diagrams used to explain the embodiment; and Fig. 5 is a diagram showing in part another embodiment of the present invention. EXPLANATION ON REFERENCE NUMERALS Reference numeral 2 represents the front end, 3 the intermediate frequency amplifier, 4 the FM detector, 5 the stereo multiplex decoder, 7 the PLL circuit, 8 the controller, 9 the crystal oscillator, 12 the key input apparatus, 13 the display apparatus, and 23, 25 and 26 the integrators. An embodiment of the present invention will hereinafter be described with reference to Fig. 2. In Fig. 2, like parts corresponding to those of Fig. 1 are marked with the same references and therefore need not be described in detail. Referring to the same figure, a junction between the crystal oscillator 9 forming the clock oscillator and the capacitor 10 is connected to the collector of an NPN transistor 21 for switching operation. The emitter of the transistor 21 is grounded. The key input apparatus 12 has a plurality of key switches which are respectively connected to the controller 8 at their one ends. The other ends thereof are connected to a voltage terminal +B. The one ends of the respective key switches of the key input apparatus 12 are connected to the input side of an OR circuit 22. The output side of the OR circuit 22 is grounded via a series circuit of a resistor 23a and a capacitor 23b forming an integrator 23. Reference numeral 23c designates a speed-up diode that is connected in parallel to the resistor 23a. The output side of the integrator 23, i.e., the junction between the resistor 23a and the capacitor 23b is connected to the input side of a NOR circuit 24. A latch signal Sℓ supplied from the controller 8 to the display apparatus 13 is grounded via a series circuit of a resistor 25a and a capacitor 25b forming an integrator 25. Reference numeral 25c designates a speed-up diode that is connected to the resistor 25a in a parallel relation. The output side of the integrator 25, i.e., the junction between the resistor 25a and the capacitor 25b is connected to the input side of the NOR circuit 24. The output side of the NOR circuit 24 is grounded via a series circuit of a resistor 26a and a capacitor 26b forming an integrator 26. Reference numeral 26c designates a speed-up diode that is connected to the resistor 26a in a parallel relation. The output side of the integrator 26 is connected to the base of the transistor 21. The signal produced at the output side of the integrator 26 is supplied, as a latch signal, to a latch circuit 27 which latches data to be supplied to the intermediate frequency amplifier 3 and the latch circuit carries out the latch operation at a timing changing from low level "0" to high level "1". Other elements are formed similarly to those of the example of Fig. 1. In this embodiment, a station is selected by operating a channel up-key or channel down-key of, for example, the key input apparatus 12 and this operation will be described. When the channel up-key or channel down-key is depressed, an output signal S1 from the OR circuit 22 goes to high level "1" during the period in which the channel up-key or channel down-key is depressed, as shown in Fig. 3A so that an output signal S2 from the integrator 23 is changed as shown in Fig. 3B. Also, when the channel up-key or channel down-key is depressed, the controller 8 continuously supplies data N to the PLL circuit 7, thus changing the dividing ratio, 1/N to select stations sequentially. At that time, the controller 8 continuously supplies display data to the display apparatus 13 which displays the channel of the selected station sequentially. To this end, the latch signal Sℓ supplied from the controller 8 to the display apparatus 13 is produced a plurality of times successively. In the illustrated case, the latch signal is produced four times. When the latch signal Sℓ is produced a plurality of times successively, the output signal S3 of the integrator 25 is changed as shown in Fig. 3D. Accordingly, Vth assumes a threshold value of the NOR circuit 24. Then, the output signal S4 from the NOR circuit 24 is presented as shown in Fig. 3E, and the output signal S5 of the integrator 26 is changed as shown in Fig. 3F. Consequently, the transistor 21 is turned OFF during the period T1 from a time point t1 where the channel up-key or channel down-key is depressed to a time point t2 immediately after the station selecting operation is finished so that the clock generator continues its operation. On the other hand, during other period, the transistor 21 is turned ON to allow the one end of the crystal oscillator 9 to be grounded so that the clock generator stops operating. Further, since at time point t2 the output signal S5 of the integrator 26 changes from low level "0" to high level "1", the latch operation of the latch circuit 27 is performed at this time point t2, preventing the data to the intermediate amplifier 3 from being changed during the period in which the generation of the clock signal is stopped. In this embodiment, such a case where, for example, a preset key of the key input apparatus 12 is depressed will be explained. In this case, if the preset key is depressed, the output signal S1 of the OR circuit 22 goes to high level "1" only during the period in which the preset key is being pressed as shown in Fig. 4A so that the output signal S2 from the integrator 23 is changed as shown in Fig. 4B. If the preset key is depressed, the controller 8 supplies the preset data N to the PLL circuit 7, thus changing the dividing ratio 1/N to select the station of the thus preset channel. At that time, display data is supplied from the controller 8 to the display apparatus 13 which displays the channel of the selected station. To this end, only one latch signal Sℓ is supplied from the controller 8 to the display apparatus 13 as shown in Fig. 4C. When the latch signal Sℓ is produced as described above, the output signal S3 of the integrator 25 is changed as shown in Fig. 4D. As a result, Vth assumes the threshold value of the NOR circuit 24. Then, the output signal S4 of the NOR circuit 24 is presented as shown in Fig. 4E so that the output signal S5 of the integrator 26 is changed as shown in Fig. 4F. Accordingly, the transistor 21 is turned OFF during the period T2 from a time point t3 where the preset key is depressed to a time point t4 just after the station selecting operation is finished so that the operation of the clock generator is continued. During other period, the transistor 21 is turned ON so that one end of the crystal oscillator 9 is grounded, thus the operation of the clock generator being stopped. Since at time point t4 the output signal S5 of the integrator 26 is changed from low level "0" to high level "1", the latch circuit 27 performs the latch operation at this time point t4. According to this embodiment, when other key switch of the key input apparatus 12 is depressed, the switching transistor 21 is turned OFF during a certain period of time from a time point where other key switch is depressed so that the generation of the clock signal is continued, thus the controller 8 being operated without trouble. According to this embodiment as described above, when the station selecting operation is ended, the generation of the clock signals from the controller 8 is automatically stopped so that during the reception, the generation of the clock signal is stopped. Accordingly, upon reception, the harmonic components of the clock signal can be avoided from being supplied to the front end 2 and the beat interference can be avoided. Thus, such a limitation or the like that the substrate for the signal system and the substrate for the digital system do not have to be spaced apart from each other is unnecessary, increasing the freedom in designing the receiver. Further, since upon reception the generation of the clock signal is stopped, the power source voltage can be prevented from being fluctuated by the clock signal, thus to avoid such a fluctuated component from being contained in the output audio signal as a noise. Hence, the sound quality (S/N ratio) can be improved. Fig. 5 illustrates another embodiment of the present invention. In the same figure, reference numeral 31 designates a crystal oscillator that forms a clock oscillator. One end of this crystal oscillator 31 is connected to the input side of an AND circuit 32 and the other end thereof is connected to the controller 8. The output side of the AND circuit 32 is connected to the other end of the crystal oscillator 31 via an inverter 33. A resistor 34 is connected to the inverter 33 in parallel. The output signal S5 from the integrator 26 is supplied through an inverter 35 to the AND circuit 32. This embodiment is constructed as described above and though not shown other elements are formed the same as those of the embodiment shown in Fig. 2. Also in this embodiment, when the output signal S5 goes to low level (see the period T1 in Fig. 3 and the period T2 in Fig. 4), the output signal from the inverter 35 goes to high level "1" so that the generation of the clock signal is continued. When on the other hand the output signal S5 goes to high level "1", the output signal from the inverter 35 goes to low level "0" so that the generation of the clock signal is stopped. As described above, also in this embodiment, when the station selecting operation is finished (see time point t2 in Fig. 3 and time point t4 in Fig. 4), the generation of the clock signal from the controller 8 is automatically stopped with action and effects similar to those of the embodiment of Fig. 2 being achieved. In the above-mentioned embodiment, the latch circuit 27 is adapted to prevent the data to the intermediate frequency amplifier 3 from being changed when the generation of the clock signal is stopped. This latch circuit is not need by a receiver in which this data is stored in a memory and cannot be changed. While the latch signal supplied from the controller 8 to the display apparatus 13 is utilized effectively in the above-mentioned embodiments, it is possible to utilize a latch signal supplied from the controller 8 to the PLL circuit 7. Further, such a variant is possible that the microcomputer itself detects that the transfer of the station selecting data is finished and stops the generation of the clock signal. While in the above-mentioned embodiments the present invention is applied to the FM radio receiver, the present invention can be similarly applied to an AM radio receiver, a television receiver or the like. According to the present invention as set forth above, when the station selecting operation is finished, the generation of the clock signals from the microcomputer is automatically stopped and upon reception, the generation of the clock signal is stopped. Therefore, during the reception, it is possible to avoid that the beat interference is caused by the input of the harmonic components of the clock signal. There is then an advantage that the substrates and the like can be located with increased freedom. Also, during the reception, the power source voltage can be prevented from being fluctuated by the clock signal and the noise caused by such a fluctuation can be avoided.

Claims: A receiver, comprising: means (12) for changing a desired broadcast frequency; a microcomputer (8) having a clock signal generator (9;31) and which is responsive to the desired frequency changing means and operable to supply station selecting data which is indicative of the desired broadcast frequency and which is clocked by the clock signal; and tuning means (2, 7) including a phase-locked-loop (7) which receives the clocked station selecting data and tunes the receiver to the desired broadcast frequency; characterised by: a circuit (22, 23, 24, 25, 26) for detecting whether or not the desired broadcast frequency is being changed; and a switching circuit (21;32) responsive to the frequency change detecting circuit for stopping the generation of the clock signal for the microcomputer when the desired broadcast frequency is not being changed whilst permitting the phase-locked-loop to remain in a closed loop. A receiver as claimed in Claim 1, wherein the phase-locked-loop comprises: a frequency divider which receives an output signal (Fout) of a local oscillator of the tuning means and the station selecting data and which provides a frequency-divided signal; means for latching the station selecting data supplied to the frequency divider; a reference oscillator providing a reference signal; a phase comparator for phase comparing the frequency-divided signal and the reference signal and supplying an error signal; and a low-pass filter for filtering the error signal and providing a tuning control voltage of the tuning means. A receiver as claimed in Claim 2, wherein the frequency change detecting circuit is operable to detect when the supply of station selecting data from the microcomputer to the phase-locked-loop has stopped. A receiver as claimed in Claim 3, wherein the frequency change detecting circuit is operable to detect a latching signal provided by the microcomputer to the latching means of the phase-locked-loop. A receiver as claimed in any preceding claim wherein the desired frequency changing means comprises a key input apparatus (12) and the frequency change detecting circuit includes a circuit (22, 23) for detecting a voltage changed by depressing a key of the key input apparatus. A receiver as claimed in any preceding claim, further comprising a display apparatus (13) which receives display data and a latch signal (Sℓ) from the microcomputer when the broadcast frequency is being changed and which latches the display data, and wherein the frequency change detecting circuit includes an integrator (25) for integrating the latch signal for the display data. A receiver as claimed in Claim 1 or 2, wherein the frequency change detecting circuit is provided by the microcomputer itself. A receiver as claimed in any preceding claim, wherein the clock generator comprises a crystal oscillator (31) connected between input and output terminals of an inverter (33), the switching circuit (32) being connected between one end of the crystal oscillator (31) and a reference potential point.

Inventors: SATO KAZUHIRO, SATO, KAZUHIRO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: H04B15
IPC codes: H03J1, H03J7