Digital signal processing system having two instruction memories accessed by a processor under control of host

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a digital signal processor comprising: a processor mainly for signal processing, having an internal writable instruction memory for storing instruction word specifying various internal operations, means for temporarily stopping and restarting the operation of the processor, an instruction memory storing instruction words to be written in the writable instruction memory, and a host processor connected to the processor, the stopping and restarting means, and the instruction memory to control the same. Description of the Prior Art Fig. 1 is a schematic block diagram of an exemplary conventional signal processor employing the digital signal processor (DSSP1) mainly for voice signal processing published in the preprint No. S10-1 for the Denshi Tsushin Gakkai Tsushin Bumon Zenkoku Taikai Symposium, 1985. In this example, the digital signal processor is controlled by a host processor. Referring to Fig. 1, there are shown a signal processor 82 mainly for signal processing, a host processor 81 for controlling the signal processor 82, an instruction memory selection signal 83, a reset signal 84 for initializing the signal processor 82, a program counter (PC) 85, an instruction address 86, an internal instruction memory 87, such as a ROM, storing instruction words, an external instruction memory 88 storing instruction words, a switching circuit 89 for selecting one of two instruction words according to the instruction memory selection signal 83, an instruction register (IR) 90 for holding an instruction word, a decoder 91 for decoding instruction words, an arithmetic unit 92 which carries out arithmetical operations, a control signal 93, a data memory 94 storing data to be subjected to signal processing operation, and data 95. Fig. 2 is a flow chart of assistance in explaining the operation of the signal processor. The operation of this signal processor will be described with reference to Figs. 1 and 2. Upon the connection of the signal processor to a power supply, first the host processor starts operation and gives a selection signal 83 to the signal processor 82 to specify the internal instruction memory 87 or the external instruction memory 88. The internal instruction memory 87 is selected when the logical value of the selection signal 83 is "0", while the external instruction memory 88 is selected when the logical value of the selection signal 83 is "1". Then, the host processor 81 gives the reset signal 84 to the signal processor 82. Upon the reception of the reset signal 84, the devices including the internal instruction register are initialized and the PC 85 is cleared. Then, the PC 85 gives an instruction address 86 specifying an address 0 to the internal instruction memory 87 of the signal processor 82 and to the external instruction memory 88 to read instruction words stored at the specified address 0 and the instruction words are given to the switching circuit 89. The switching circuit 89 selects either the instruction word read from the internal instruction memory 87 or the instruction word read from the external instruction memory 88 according to the selection signal 83 given thereto from the host processor 81 and gives the selected instruction word to the IR 90. The instruction word held by the IR 90 is decoded by the decoder 91 to provide control signals to the devices. The internal arithmetic unit 92 of the signal processor 82 is controlled by the control signal 93 provided by the decoder 91 to process the data 95 stored in the data memory 94 through arithmetical operations. The conventional signal processor needs a comparatively large-scale control program for complex signal processing and the capacity of the internal instruction memory 87 of the signal processor 82 is insufficient to store such a large-scale control program, and hence the external instruction memory 88 is necessary. When the external instruction memory 88 is employed, an input/output (I/O) device is necessary for transferring the internal signals of the signal processor 82 and the external signals through external terminals to provide the instruction address 86 and to receive instruction words. In such a case, a long time is necessary for reading instruction words from the internal instruction memory 87 because the instruction words are read through an additional device. Accordingly, a clock signal having a long period must be applied to the signal processor 82 when the external instruction memory 88 is employed, and the signal processor 82 must be initialized by the reset signal 84 after switching the instruction memories or the signal processor will malfunction. The internal instruction memory 87 of the signal processor 82 is a so-called mask ROM in which a program is written beforehand in fabricating the signal processor 82, and a special program for special processes are stored in the internal instruction memory 87. The conventional signal processor thus constituted needs to read instruction words from the external instruction memory in executing complex processes requiring additional time for reading instruction words from the external instruction memory to reduce the processing efficiency. Furthermore, since the internal instruction memory is a read-only memory, the change of the program after the completion of the signal processor is impossible and, when errors are found in the program or when the program needs correction, the signal processor needs to be changed for a new one, which deteriorates the efficiency of development and is uneconomical. SUMMARY OF THE INVENTION It is an object of the present invention to provide a flexible digital signal processor capable of readily changing the program on instruction from a host processor and capable of performing complex processes and other temporary processes without requiring many additional hardwares and without entailing the deterioration of the processing efficiency. In order to achieve the above objects, a digital signal processing system as defined in claim 1 is provided. Further advantageous embodiments are defined in the sub-claims. The digital signal processor according to the present invention as claimed incorporates a writable instruction memory as an internal instruction memory, and is controlled by instructions provided by a host processor for temporary stop and restart of operation, and for writing in and reading from the writable instruction memory. Accordingly, the operation of the digital signal processor is stopped temporarily by the host processor, and the operation of the digital signal processor is restarted for other process after the internal instruction memory of the digital signal processor has been rewritten. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an example of a conventional digital signal processor; Fig. 2 is a flow chart of assistance in explaining the operation of the digital signal processor of Fig. 1; Fig. 3 is a block diagram of a digital signal processor, in a first embodiment, according to the present invention; Fig. 4 is a flow chart of assistance in explaining the operation of the digital signal processor of Fig. 3; Fig. 5 is a block diagram of a digital signal processor, in a second embodiment, according to the present invention; and Fig. 6 is a flow chart of assistance in explaining the operation of the digital signal processor of Fig. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal processor, in a first embodiment, according to the present invention will be described hereinafter. Referring to Fig. 3 showing the internal verify of the digital signal processor for verifying the contents of the internal instruction memory thereof, there are shown a host processor 403, a signal processor 404, a hold request signal 405 requesting the temporary stop of instruction execution of the signal processor 404, a hold authorizing signal 406 for informing an external unit of the temporary stop of the signal processor 404, a program counter (PC) 407, an instruction memory control unit 408, a reloadable writable instruction memory 409, an instruction address 410, a switching circuit 411, a selection signal 412, an external instruction memory 413, instruction words 414 and 415, a comparing circuit 416, a result 417 of decision, and write end signal 418. The signal processor 404 has an arithmetic unit the same as that of the conventional signal processor, and hence the arithmetic unit is not shown in Fig. 3. Fig. 4 is a flow chart of assistance in explaining the operation of the signal processor. The operation of the signal processor 404 will be described hereinafter with reference to Figs. 3 and 4. When the content of a process to be executed by the signal processor 404 needs to be changed, the host processor 403 gives the signal processor 404 the hold request signal 405 requesting the temporary stop of instruction word execution. Upon the end of an instruction presently being executed after the reception of the hold request signal 405, the signal processor 404 provides the hold authorizing signal 406 to stop updating the PC 407 and to interrupt the execution of the instruction word temporarily. Then, the instruction memory control unit 408 provides the instruction address 410 specifying an address to be reloaded in the writable instruction memory 409, and the selection signal 412 to control the switching circuit 411 so that the instruction address 410 is selected. At the same time, the instruction address 410 is given also to the external instruction memory 413. Then, the external instruction memory 413 provides an instruction word 414, which is written in the writable instruction memory 409. The instruction word 414 written in the writable instruction memory 409 is read from the writable instruction memory 409. The instruction word 415 read from the rewritable instruction memory 409 and the instruction word 414 written in the same are compared by the comparison circuit 416 to decide whether or not the instruction words 414 and 415 coincide with each other. When the instruction word 414 is not written correctly in the rewritable instruction memory 409, the two instruction words do not coincide with each other. Then, a write error flag is set according to the result 417 of decision in the instruction memory control unit 408. This write error signal is not reset until all the write operations are completed. Thus, operation for writing one instruction word is completed. This operation is repeated until all the instruction words are rewritten. After all the instruction words have been rewritten, the status of the write error flag is examined. When the write error flag is set, the instruction word write operation is restarted after resetting the write error flag. When any write error flag is not set and the rewrite has been ended normally, a write end signal 418 is given to the host processor 403. Then, the host processor cancels the hold request signal 405 to cancel the temporary stop mode. Upon the cancellation of the hold request signal 405, the instruction memory control unit 408 of the signal processor 404 provides a selection signal 412 to make the switching circuit 411 select the instruction address of the PC 407, the instruction address of the PC 407 is updated, and then an instruction at an instruction address succeeding the instruction address of the last instruction word executed before the execution of instructions was stopped temporarily is executed. Thus the contents of the signal processing process can readily be changed by providing the signal processor with an internal rewritable instruction memory. The malfunction of the signal processor attributable to erroneous rewrite can be prevented by providing a verify circuit in the signal processor. Fig. 5 shows a signal processor in a second embodiment which is a modification of the signal processor of Fig. 3. This modified signal processor is provided externally with a decision circuit for deciding whether or not the contents of the writable instruction memory is correct. Fig. 6 is a flow chart of assistance in explaining the operation of the modified signal processor. The operation of the modified signal processor will be described hereinafter with reference to Figs. 5 and 6. When the contents of the process to be executed by the signal processor 422 needs to be changed, a host processor 421 provides a hold request signal 405 to stop updating a PC 407 so that the execution of instruction words is interrupted temporarily. Upon the reception of a hold authorizing signal 406, the host processor 421 gives an instruction address 410 to an external instruction memory 413 and the signal processor 422. An instruction word 414 read from the external instruction memory 413 is applied to a switching circuit 423, and then the instruction word 414 is applied to the signal processor 422 when a selection signal 424 is provided by the host processor 421. Then, the host processor 421 provides a write control signal 425 to instruct an instruction memory control unit 426 to give a selection signal 428 to the switching circuit 427, so that the instruction word 414 is written in a writable instruction memory 409. Then, the host processor 421 provides a read control signal 429 to read an instruction word 415, i.e., the written instruction word, from the writable instruction memory 409, and the instruction memory control unit 426 gives a selection signal 428 to the switching circuit 427 to apply the instruction word 415 to the switching circuit 423. The host processor 421 provides the selection signal 424 to apply the instruction word 415 to a comparison circuit 430. The comparing circuit 430 compares the instruction word 414 read from the external instruction memory 413 and the instruction word 415 read from the writable instruction memory 407, and then gives the result 431 of comparison to the host processor 421. When the two instruction words coincides with each other, the host processor executes operation for writing the next instruction word. When the two instruction word do not coincide with each other, the host processor performs the same instruction write operation again. After all the instruction words have been written, the host processor 421 cancels the hold request signal 405 to enable the signal processor 422 to restart the operation. In this embodiment, in reading an instruction word having a m x n (m is an integer not less than one and n is an integer not less than two) bit width from the external instruction memory and giving the instruction word to the signal processor, m x n pieces of external terminals are necessary. However, only m pieces of external terminals are necessary when the bits of the instruction word is divided into bit widths each of m bits and the instruction word is written in the internal writable instruction memory by repeating the write operation n times. For example, although thirty-two external terminals are necessary for writing an instruction word of thirty-two bits in the internal writable instruction memory in one writing operation, only eight external terminals are necessary for writing the instruction word in the internal writable instruction memory when the instruction word is divided into 8-bit widths and written by four writing cycles. Although this writing mode requires a write time four times the write time necessary for writing an instruction word in the internal instruction memory by a single writing operation, this writing mode is very effective when a limited number of external terminals are available. As apparent from the foregoing description, since the signal processor according to the present invention incorporates an internal writable instruction memory, and the operation of the signal processor is stopped temporarily by an instruction provided by the host processor to reload the internal instruction memory of the signal processor, the program stored in the signal processor can optionally be changed after the signal processor has been fabricated, which enhances the efficiency of development activities and is highly economical. Furthermore, the possibility of temporarily stopping the execution of an instruction during the signal processing operation to rewrite the program, and restarting the execution of the instruction after rewriting the program enable the signal processor to perform more complicated signal processing operations and diversifies the signal processing functions of the signal processor for flexible signal processing.

Claims: A digital signal processing system comprising: a processor (404; 422) mainly for signal processing, having an internal writable instruction memory (409) for storing instruction words (414, 415) specifying various internal operations; means for temporarily stopping and restarting the operation of the processor (404; 422); an instruction memory (413) storing instruction words (414) to be written in the writable instruction memory; and a host processor (403; 421) connected to the processor (404; 412), the stopping and restarting means, and the instruction memory (413) to control the same; characterized by further comprising means for temporarily stopping the operation of the processor (404; 422) in response to a command (405) provided by the host processor (403; 421), reading an instruction word (414) from the instruction memory (413) and writing the instruction word (414) in the writable instruction memory (409); and means (416; 421) for comparing an instruction word (414) read from said instruction memory (413), after the former instruction word (415) read from said instruction memory (413) has been written in said writable instruction memory (409), with the former instruction word (415) read from said writable instruction memory (409), deciding whether or not the former instruction word (415) and the latter instruction word (414) coincide with each other, and for providing the result (417) of decision of the comparison circuit (416), wherein the host processor (403; 421) performs a control operation to write an instruction word again in said writable instruction memory (409) when the former and latter instruction words (415, 414) do not coincide with each other, and wherein the operation of the processor (404; 422) is changed over by restarting the operation of the processor (404; 422) in response to a command (405) provided by the host processor (403; 421) after the instruction word (414) has been written in the writable instruction memory (409); The digital signal processing system according to claim 1, wherein an instruction address automatically generated by the processor (404) is applied to said instruction memory (413) in reading an instruction word (414) from said instruction memory (413) and writing the read instruction word (414) in said writable instruction (409); and said processor (404) is provided with a comparing circuit (416) as comparing and deciding means and an output means for providing the result (417) of decision of the comparing circuit (416). A digital signal processing system according to claim 1, wherein an instruction word (414) is read from said instruction memory (413) according to an instruction address (410) provided by said host processor (421) in reading the instruction word (414) from said instruction memory (413) and writing the instruction word (414) in said writable instruction memory (409), the instruction word (414) written in said writable instruction memory (409) according to an instruction address (410) and a write control signal (425) provided by said host processor (421) is read from said writable instruction memory (40) in response to a read control signal (429) provided by said host processor (421); and said host processor (421) compares the instruction word (414) read from said instruction memory (413) and the former instruction word (415) written in said writable instruction memory (409) and decides whether or not these instruction words (414, 415) coincide with each other. A digital signal processing system according to anyone of the preceding claims, wherein an instruction word (414) having an m x n bit width (m is an integer not less than one, n is an integer not less than two) is divided in m-bit widths and is read and written in n cycles of read and write operations in reading the instruction word (414) from said instruction memory (413) and writing the instruction word (414) in said writable instruction memory (409).

Inventors: KAMEYAMA MASATOSHI, KAMIZAWA KOH, KATOH YOSHIAKI, KINJO NAOTO, MURAKAMI TOKUMICHI, OHIRA HIDEO, KAMEYAMA, MASATOSHI, KAMIZAWA, KOH, KATOH, YOSHIAKI, KINJO, NAOTO, MURAKAMI, TOKUMICHI, OHIRA, HIDEO, KAMEYAMA, MASATOSHI, C/O MITSUBISHI DENKI K.K., KAMIZAWA, KOH, C/O MITSUBISHI DENKI K.K., Katoh, Yoshiaki, c/o MITSUBISHI DENKI K.K., KINJO, NAOTO, C/O MITSUBISHI DENKI K.K., MURAKAMI, TOKUMICHI, C/O MITSUBISHI DENKI K.K., OHIRA, HIDEO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1988
Main classification: G06F9
IPC codes: G06F15, G06F9, G06F13