SIGNAL READING CIRCUIT

Abstract: A signal reading circuit for reading out a signal (on Ct) as a voltage to a signal line through a read transistor (QS) and for outputting is provided. This circuit has a selecting circuit (103) to select and output the signal on the signal line (101) after the read transistor was turned on or off.

Description: BACKGROUND OF THE INVENTION The present invention relates to a signal reading circuit for reading out a signal as a voltage to a signal line through a read transistor and for outputting. Fig. 1A is a circuit diagram showing an example of a conventional signal reading circuit. Fig. 1B is a timing chart for explaining the operation. Fig. 1A, by setting a pulse  t to the high level for a predetermined period of time, a transfer transistor Q t is turned on, so that signals S₁, S₂, S₃, ... of sensors are transferred and accumulated into each capacitor C t . In this state, scan pulses ₁₁, ₁₂, ... are successively output from a shift register 102 to sequentially turn on read transistors Q s , thereby reading out the signals S₁, S₂, S₃, ... stored in the capacitors C t to a signal line 101. However, since the signal line 101 has a capacitance C h , the signals which are obtained by dividing the storage signals S₁, S₂, S₃, ... by the capacitance of the capacitor C t and the capacitance C h are read out to the signal line 101. As shown in Fig. 1B, pulses  s , ₁, and ₂ are input to the shift registor 102. The shift register 102 then outputs a scan pulse synchronously with the pulse ₁ by the start pulse  s . The signal read to the signal line 101 is output through an amplifier A. Whenever each signal is output, a reset transistor Q r is turned on, thereby resetting the signal line 101 to the earth potential. The pulse ₂ which is input to the shift register 102 is input to a gate electrode of the reset transistor Q r . The circuit elements and sensors shown in Fig. 1A are formed on the same semiconductor substrate. However, in the conventional example, the noise components by the scan pulses ₁₁, ₁₂, ... are added to the signal which is output from the amplifier A. Therefore, when this signal reading circuit is used in e.g., an image pickup apparatus, there is a problem such that those noise components appear as fixed pattern noises. This point will now be explained with reference to a waveform diagram of a signal line voltage V₀ in Fig. 1B. The signal components are omitted in the waveform of V₀ for convenience of explanation. First, for a period of time T c when the pulse ₂ is at the high level, the reset transistor Q r is turned on and the voltage V₀ of the signal line 101 is set to the earth potential GND. When the pulse ₂ falls to the low level and the transistor Q r is turned off, since an overlap capacitance C s2 exists, the trailing amount of the pulse ₂ is capacitively divided by C s2 and C h , so that the voltage V₀ of the signal line 101 decreases than the earth voltage GND by only the level corresponding to the trailing amount (oscillating component b). However, the amplitude of the oscillating component b is always constant because it depends on the capacitance C s2 . Next, when the scan pulse ₁₁ input to the transistor Q s synchronously with the pulse ₁ (for a period of time T t ), since the overlap capacitance C s of the transistor Q s exists, the leading amount of the scan pulse ₁₁ is capacitively divided by C s and C h , so that the voltage V₀ of the signal line 101 increases by only the level of the leading amount (the voltage V r ). The trailing amount is also capacitively divided, so that the voltage V₀ of the signal line 101 drops by only the level corresponding to the leading amount (voltage V t ) (oscillating component a). In this manner, the sensor signal S₁ is read out to the signal line 101 through the read transistor Q s and output from the amplifier A. Thus, the reset transistor Q r is again turned on by the pulse ₂. In a manner similar to the above, the sensor signals S₂, S₃, ... are sequentially output. However, the scan pulses ₁₁, ₁₂, ... which are output synchronously with the pulses ₁ are input to the gate of individual read transistor Q s , so that the following problems occur. That is, the overlap capacitances of the read transistors have a certain variation due to a variation in semiconductor processes. Therefore, the oscillating components a are not uniform. Assuming that a veriation of the capacitances C s is ΔC s , a variation in oscillating components a is Δv n = ΔC s · V  /(C s + C h ) When it is now assumed that C h = 5 pF C s = 0.02 pF ΔC s = C s x 0.01 V  = 5 V, the variation Δv n in oscillating components a becomes Δv n = 0.2 mV. This variation appears as a fixed pattern noise in the vertical direction on the image and causes the picture quality to deteriorate. SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal reading circuit which can solve the foregoing drawbacks in the conventional techniques. Another object of the invention is to provide a signal reading circuit which can reduce the fixed pattern noises. To accomplish these objects, according to claim 1, there is provided a signal reading apparatus comprising: (a) a plurality of signal sources (S₁, S₂, S₃, ...); (b) a plurality of accumulating means (C t ) each of which is provided for each of said signal sources for temporarily holding signals of said plurality of signal lines; (c) a plurality of switch means (Q s ) each of which is provided for each of said accumulating means (C t ) for reading out the signals stored in the accumulating means (C t ), one end of each of said switch means (Q s ) being connected to corresponding one of said accumulating means (C t ); (d) a capacitive load (101) connected commonly to one end of each of said plurality of switch means; (e) control means (102) for selectively making said plurality of switch means operative, and thereby sequentially leading the signals stored in said accumulating means (C t ) to said capacitive load (101); (f) clearing means (Q r ) for clearing the signals led to said capacitive load; and characterised in that the reading apparatus further comprises reading means (103) for reading out the signals held in the capacitive load (101) for a period of time after each of said switch means (Q s ) was made inoperative by said control means (102) and until the capacitive load (101) is cleared by said clearing means (Q r ). As mentioned above, at the voltage V₀ on the signal line shown in Fig. 1B, there is a variation in amplitudes of the oscillating components a due to the read transistors Q s . However, it has been confirmed by the experiments that the change voltage v r at the leading edge and the change voltage v t at the trailing edge are almost equal. Thus, the voltage V₀ of the signal line 101 before and after the oscillating components a is hardly concerned with the variation in oscillating components a. Each sensor signal is read out to the signal line 101 by the scan pulse through each read transistor Q s . The signal component remains so long as the signal line 101 is not reset by the reset transistor Q r . That is, the signal component exists on the signal line 101 for the period of time T s in the diagram. Therefore, as in the embodiment of the invention, when the signal on the signal line 101 is selected and output after the read transistor Q s was turned off, the signal can be read out without being influenced by the variation in oscillating components a. Since the amplitudes of the oscillating components b are almost constant, they do not become fixed pattern noises. The above objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a circuit diagram showing an example of a conventional signal reading circuit; Fig. 1B is a timing chart for explaining the operation of this circuit; Fig. 2A is a schematic constitutional diagram of the first embodiment of a signal reading circuit according to the invention; Fig. 2B is a timing chart for explaining the operation of the circuit of Fig. 2A; Fig. 3A is a schematic constitutional diagram of the second embodiment of a signal reading circuit according to the invention; Fig. 3B is a timing chart for explaining the operation of the circuit of Fig. 3A; and Fig. 4 is a schematic constitutional diagram of an image pickup apparatus using the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 2A is a schematic constitutional diagram of the first embodiment of a signal reading circuit according to the present invention. Fig. 2B is a timing chart for explaining the operation of this circuit. The constitutions of the transfer transistors Q t , accumulating capacitors C t , read transistors Q s , reset transistor Q r , signal line 101, and shift register 102 are as explained in Fig. 1A. The pulses ₁ and ₂ and the signal line voltage V₀ in Fig. 2B are also as described in Fig. 1B. In this embodiment, a sample and hold (S/H) circuit 103 is provided as selecting means for the signal line 101 separately from a semiconductor substrate on which sensors are formed. The signal line voltage V₀ after the scan pulse fell to the low level is sampled and held and output. That is, in the period of time T s in Fig. 2B, a pulse  sh is given to the S/H circuit 103 for a period of time T x before it is reset by the pulse ₂ after the elapse of the period of time T t , thereby holding the signal line voltage V₀ at that time. Thus, the influence by the fixed pattern noises due to the transistor Q s can be prevented. Fig. 3A is a schematic constitutional diagram of the second embodiment of a signal reading circuit according to the invention. Fig. 3B is a timing chart for explaining the operation of this circuit. The same parts and components as those in the first embodiment are designated by the same reference numerals. In this embodiment, the S/H circuit 103 consisting of a transistor Q sh is provided on the same semiconductor substrate as the sensors. An inverted pulse ₁ of a pulse ₁ is given to a gate electrode of the transistor Q sh . By forming the transistor Q sh in the sensor, the structure is simplified and the cost can be also reduced. First, the reset transistor Q r is turned on by a pulse  hc , thereby resetting the signal line 101 to the earth potential GND (for the period of time T c ). After the elapse of the period of time T c , the pulse  hc falls, so that the signal line voltage V₀ decreases to a level lower than the earth potential GND as mentioned above (oscillating component b). The pulse ₁ rises in response to the trailing edge of the pulse  hc . The scan pulse ₁₁ is input from the shift register 102 to the gate electrode of the transistor Q s synchronously with the leading edge of the pulse ₁. Simultaneously, the gate electrode of the transistor Q sh is set to the low level and the transistor Q sh is turned off. Therefore, the read transistor Q s is turned on for the period of time T t and the sensor signal S₁ is read out to the signal line 101 and held thereon. Subsequently, after the expiration of the period of time T t , when the pulse ₁ trails, the transistor Q sh is turned on. The signal existing on the signal line 101 for the period of time T s is output through the amplifier A. At this time, the signal line 101 includes no variation in oscillating components a due to the scan pulses ₁₁ as mentioned above. Then, after the elapse of the period of time T s , the reset pulse  hc rises and the reset transistor Q r is turned on, thereby resetting the signal line 101. The fixed pattern noises are also eliminated with this structure. Although the reset transistor Q r has been used to reset the signal line 101 in the embodiment, another reset transistor may be also provided on an output terminal. On the other hand, in place of the pulse ₁ , another pulse having a width narrower than the pulse ₁ may be also used. Fig. 4 is a schematic constitutional diagram of an image pickup apparatus using the first embodiment. In the diagram, an image pickup device 201 consisting of photosensors arranged in an area form is television scanned by a vertical scan portion 202 and a horizontal scan portion 203. A signal output from the horizontal scan portion 203 is output as a standard television signal through the S/H circuit 103 and a processing circuit 204. Drive pulses and the like of the vertical scan portion 202 and horizontal scan portion 203 and the pulse  sh and the like of the S/H circuit 103 are supplied by a driver 205. The driver 205 is controlled by a controller 206. The horizontal scan portion 203 comprises: the transfer transistors Q t , capacitors C t , read transistors Q s , reset transistor Q r , signal line 101, shift register 102, and the like in Fig. 2A. With the horizontal scan portion 203 and S/H circuit 103, the video signal without the fixed pattern noises as already explained is obtained and the picture quality can be improved. As described in detail above, the signal reading circuit according to the invention has a simple structure such that there is provided the selecting means for selecting and outputting the signal on the signal line after the read transistor was turned on or off. Therefore, the signal can be taken out without being influenced by the manufacturing variation or the like of the read transistors. Consequently, when the invention is used in, e.g., the image pickup apparatus, the image of a good quality without the fixed pattern noise can be derived.

Claims: A signal reading apparatus comprising: (a) a plurality of signal sources (S₁, S₂, S₃, ...); (b) a plurality of accumulating means (C t ) each of which is provided for each of said signal sources for temporarily holding signals of said plurality of signal lines; (c) a plurality of switch means (Q s ) each of which is provided for each of said accumulating means (C t ) for reading out the signals stored in the accumulating means (C t ), one end of each of said switch means (Q s ) being connected to corresponding one of said accumulating means (C t ); (d) a capacitive load (101) connected commonly to one end of each of said plurality of switch means; (e) control means (102) for selectively making said plurality of switch means operative, and thereby sequentially leading the signals stored in said accumulating means (C t ) to said capacitive load (101); (f) clearing means (Q r ) for clearing the signals led to said capacitive load; and characterised in that the reading apparatus further comprises reading means (103) for reading out the signals held in the capacitive load (101) for a period of time (T x ) after each of said switch means (Q s ) was made inoperative by said control means (102) and until the capacitive load (101) is cleared by said clearing means (Q r ). An apparatus according to claim 1, wherein said accumulating means (C t ) includes capacitors. An apparatus according to claim 1, wherein said control means (102) includes a shift register. An apparatus according to claim 1, wherein the timing for selectively making said plurality of switch means (Q s ) operative by said control means (102) and the timing for the operation of said clearing means (Q r ) are synchronised with each other. An apparatus according to claim 1, wherein said reading means (103) includes sampling and holding means. An apparatus according to claim 1, further including a signal output terminal, and wherein said reading means (103) includes switch means (Q sh ) arranged between said capacitive load (101) and said signal output terminal.

Inventors: HASHIMOTO, SEIJI
Applicants: CANON KABUSHIKI KAISHA
Application year: 1988
Main classification: G11C27
IPC codes: H04N5, G11C27, G11C19, H04N3