DYNAMIC MEMORY CIRCUIT WITH IMPROVED SENSING SCHEME

Abstract: A dynamic type memory circuit provided with an improved writing and refreshing functions executable at the same time is disclosed. The memory circuit includes a plurality of memory cell groups, a plurality of sense amplifier groups provided for the memory cell groups, a write circuit for operatively writing a write data to a plurality of memory cells in at least one memory cell groups and a plurality of sense amplifier activation circuits provided for the sense amplifier groups.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a dynamic memory circuit, and more particularly to a dynamic type semi-conductor memory circuit employing flip-flop type sense amplifiers. Dynamic memories are widely utilized in various fields as large capacity memories. A dynamic memory generally comprises a large number of memory cells in a matrix form of rows and columns, word lines in rows and digit lines in columns. In reading or refreshing operation, memory cells coupled to the selected word line cause small potential changes in the digit lines. Such small potential changes in the digit lines or digit line pairs are amplified by sense amplifiers and the amplified signals are rewritten into the memory cells coupled to the selected word line. In writing operation, a write data signal is applied via the selected digit line or digit line pair to the selected memory cell while the sense amplifier coupled to the selected digit line or digit line pair is enabled. The sense amplifier is generally comprised of a flip-flop type differential amplifier and the digit line of a lower potential in the digit line pair is discharged through the sense amplifier to a sense amplifier activation signal line in response to the change from a high level corresponding to a precharge level of the digit line to a low level in that line. Thus, the digit line of the lower potential becomes at the minimum level such as the ground potential thereby to achieve amplification or refresh of the read out signal of the selected memory cell. Recently, there has been proposed a memory in which columns are classified into a plurality of column blocks with the common rows and each column block is provided with a read-write circuit. In such memory, writing of data into one column block and refreshing of contents of memory cells of other column blocks are simultaneously performed. In the above operation, a relatively large signal is applied to the column block performing a write operation and therefore the state of the sense amplifier or amplifiers in the above column block are determined rapidly. While, small signals are produced on digit lines from the memory cells in other column blocks performing refresh operation. Therefore, sense amplifiers in the above other column blocks are required to discharge the lower potential of digit lines gradually to the sense amplifier activation signal line. However, the rapidly established states of the sense amplifiers in the column block performing write operation adversely affect the sense amplifier activation signal line to change the potential at that line to the low level in an unexpectedly short period of time. Therefore, the sense amplifiers in the above other column blocks fail to accurately amplifying small read-out signals on the digit line, resulting in insufficient or erroneous refresh operation. A dynamic memory circuit having all the features of the preamble of claim 1 is disclosed in EP-A 0 087 754. Also in this device simultaneous performance of a write operation by a sense amplifier and a refresh operation by another sense amplifier may result in an insufficient or erroneous refresh operation. It is therefore an object of the invention to provide an improved dynamic memory circuit in which both refresh operation and write operation can be simultaneously conducted stably without failure of refresh operation. This object is achieved by a dynamic memory circuit as defined in claim 1; the dependent claims are related to further developments of the invention. According to the present invention, each sense amplifier group associated to each memory cell group is provided with its own sense amplifier activation means. A plurality of sense amplifier activation means are provided separately and independently. Therefore, one associated to the memory cell group subjected to write operation is isolated from the other sense amplifier activation means associated to the memory cell group or groups subjected to refresh operation. The sense amplifiers of the sense amplifier group in the writing condition and the sense amplifiers of the sense amplifier groups in the refreshing condition can operate separately without affecting each other. BRIEF DESCRIPTION OF DRAWINGS: Fig. 1 is a schematic block diagram of a memory circuit according to a prior art; Fig. 2 is a schematic block diagram of a memory circuit according to an embodiment of the present invention; Fig. 3 is a schematic circuit diagram of a sense amplifier; Fig. 4 is a schematic block diagram showing a column decoder; and Fig. 5 is a timing diagram showing operations of the memory in Fig. 2: DETAILED DESCRIPTION OF THE INVENTION: Referring to Fig. 1, a dynamic memory circuit according to a prior art will be explained. A plurality of dynamic type memory cells MC are arranged at the intersections of word lines WL₁ - WL n in rows and digit lines in column in to form a memory matrix. A row decoder 1 receives row address signals R.A and selects one of the word lines. After one of the word lines, e.g. WL₁ is selected, the memory cells coupled to the selected word line WL₁ cause small potential change in the digit lines according to stored contents of the selected memory cells. Then, a control signal ₁ is energized to a high level to render a transistor QS conductive. As a result, a sense amplifier activation signal line SE is gradually discharged to the ground potential and the sense amplifiers 6-1 to 6-m discharge charges on the digit lines selectively to amplify the potentials of the digit lines. The amplified potentials on the digit lines are simultaneously write-back to the selected memory cells so that refresh of the selected memory cells is achieved. While a column decoder 2 selectively turns conductive one of column select transistors QY₁ - QY m in a column election circuit 3 according to content of column address signals so that the signal on the selected digit line is transmitted to a data bus line DB via the conductive transfer transistor and further outputted to a data terminal DT via an input/output circuit 5. Referring to Figs. 2 to 4, a dynamic memory circuit according to one embodiment of the invention will be explained below. A major circuit arrangement of the embodiment is shown in Fig. 2. As shown in Fig. 2, a plurality of dynamic memory cells MC are arranged into two memory arrays 11 and 12. The arrays 11 and 12 share the same word lines WL₁ - WL n in rows. On the other hand, K pairs of digit lines DLA, DLA and K pairs of digit lines DLB and DLB are separately provided in the arrays 11 and 12, respectively. The row decoder 1 selects one of the word lines according to the row address signals R.A in response to a timing signal ₁. A column selection circuit 3A includes K pairs of transfer gate transistors QYA, QYA coupled between K pairs of digit lines DLA, DLA and a pair of bus lines DBA, DBA . A column selection circuit 3B includes K pairs of transfer gate transistors QYB, QYB coupled between the K pairs of digit lines DLB, DLB and a pair of bus lines DBB, DBB . A column decoder 2A energizes or activates one of outputs YA1 - YAK in accordance with contents of row address signals C·A in response to a timing signal ₃ thereby to connect the pair of bus lines DBA, DBA to one pair of digit lines DLA, DLA via the conducting pair of transistors QYA, QYA when a flash write control signal FW₁ is at a high level. A column decoder 2B also selects one pair of transfer gate transistors QYB, QYB for electrical connection of the pair of bus lines DBB, DBB to the selected pair of digit lines DLB, DLB in accordance with the contents of column address signals C.A in response to ₃ when a flash write control signal FW₂ is at a high level. When the flash write control signal FW₁ and FW₂ are at a low level, the column decoders 2A and 2B activate all the outputs YA1 - YAK and all the outputs YB1 - YBK simultaneously irrespective of the column address signals, respectively, so that the pair of bus lines DBA, DBA and the pair of bus lines DBB, DBB are electrically connected to all the K pairs of digit lines DLA, DLA and all the K pairs of digit lines DLB, DLB , respectively. A read buffer 20A, a write register 22A, and a write driver 21 perform a read operation and a write operation for the array 11. Namely, the read buffer 20A generates an output signal at an input/output terminal DTA in accordance with the states of the bus lines DBA, DBA in response to a read control signal  R . The write register 22A holds the signal at DTA as a write data signal in response to a write control signal  W and determines the input levels of the write driver 21A. Similarly, a read buffer 20B, a write register 22B and a write driver 21B perform a read operation and a write operation with respect to the array 12. Color registers 23A and 23B have inputs coupled to the terminals DTA and DTB and outputs coupled to the inputs of the write drivers 21A and 21B, respectively and latch the levels of DTA and DTB in response to a control signal  A , respectively. Flash write control registers 24A and 24B have inputs coupled to DTA and DTB and latch the levels of DTA and DTB in response to a control signal  B , respectively. Inverters 25A and 25B receive the outputs of the control registers 24A and 24B and produces the control signals FW₁ and FW₂ , respectively in response to a flash write timing signal  FW , respectively. A sense amplifier activation gate or transistor QS₁ is coupled between a sense amplifier activation line SE1 coupled to the sense amplifiers 6A for the array and the ground potential and operatively changes the potential of the line SE1 to the ground in response to a control signal ₂ applied to the gate thereof, thereby to enable the sense amplifiers 6A. A transistor QS₂ is coupled between a sense amplifier activation line SE2 coupled to the sense amplifiers 6B for the array 12 and operatively discharges the line SE2 in response to ₃ thereby to enable the sense amplifiers 6B. Namely, the transistors QS₁ and QS₂ and the activation lines SE1 and SE2 serve as independent sense amplifier activating means for the arrays 11 and 12, respectively. A timing signal generator 40 includes an inverter 30 and delay stages 31 to 34 and generates a precharge signal  p and the timing signals ₁, ₂ and ₃ in response to a chip enable signal CE in a known way. An example of the sense amplifiers 6A and 6B is shown in Fig. 3. In Fig. 3, transistors Q₁ and Q₂ have gates and drains cross-coupled at a pair of nodes N₁ and N₂ and sources commonly connected to the activated line SE1 or SE2 to form a flip-flop and a pair of precharge transistors Q₃ and Q₃ controlled by  p . The nodes N₁ and N₂ are connected to a pair of digit lines DL and DL . An example of the column decoders 2A and 2B is shown in Fig. 4. First NAND gates 50-1 to 50-K receive column address signals A₀ ( A₀ ) - A N ( A N ) in their predetermined combinations and one first NAND gate whose inputs are all "1" level generates "0" (low) level output while other first NAND gates generate "1" (high) output signals. Second NAND gages 51-1 to 51-K receive the outputs of the first NAND gates 50-1 to 50-K and the control signal FW1 ( FW2 ) in common and one second NAND gate generates the "1" level output signal and other second NAND gates produce the "0" output signal when FW1 ( FW2 ) is at the high level. Source-follower transistors Q₁₀₋₁ to Q 10-K receive the outputs of the second NAND gates 51-1 to 51-K at their gates and selectively transmit the signal ₃ to the outputs YA1 (YB1) to YAK (YBK). When FW1 ( FW2 ) is at the "0" (low) level, all the outputs of the second NAND gates generate the "1" level outputs so that all the outputs YA1 - YAK are activated via Q₁₀₋₁ to Q 10-K in response to ₃. Next, with reference to Fig. 5, operations of the embodiment will be explained. First, a normal read operation will be explained through a time frame t₁ - t₇. At a time point t₁, CE changes from the high, inactive level to the low active level and the memory circuit enters into an active period. In response to this, the precharge signal  p falls in level at a time point t₂ and thereafter the timing signal ₁ rises in potential so that one of the word lines WL is selected and small signals from the memory cells MC coupled to the selected word line appear in the respective pairs of digit lines in the arrays 11 and 12. Then, at a time point t₄, the timing signal ₂ rises in potential and the transistors QS₁ and QS₂ are rendered conductive. As a result, the potentials of the activation lines SE1 and SE2 , which have been precharged to a predetermined precharge potential in response to  p , starts to fall gradually till t₄' so that the sense amplifiers 6A and 6B are enabled to amplify the potential difference in the respective digit line pairs. Then, at a time point t₅, the signal ₃ rises in potential and the output states of the column decoders 2A and 2B are determined. Thus, the signal at the selected digit line pair in the array 11 and the signal at the selected digit line pair in the array 12 are transmitted to the pair of bus lines DBA, DBA and the pair of bus lines DBB, DBB , respectively. At a time point t₆, the signal  R is raised in potential and the buffers 20A and 20B are enabled so that the signals on the bus line pairs DBA, DBA ; DBB, DBB are outputted to DTA and DTB, respectively. Then, at a time point t₇, CE rises to the high level to terminate the active period and the precharge signal  p is raised. Next, a flash write mode operation in which a flash write is made on the array 11 so that the same data is written into K memory cells coupled to the selected word line and a refresh operation is made on the array 12, is explained. The above mode of operation is conducted as follows. First, the data to be written to the array 11 is set in the color register 23A via DTA in response to  A and a flash write determination signal for determining whether the flash write is conducted or not, is stored in the control register 24A via DTA in response to  B . When the high ("1") level is stored in the register 24A, the low level of FW1 is produced from the inverter 25A in response to  FW so that all the outputs YA1 - YAK of the column decoder 2A is selected and the content of the register 23A is transmitted to all the selected memory cells via the driver 21A, the transfer gate transistors QYA, QYA and the bit line pairs DLA, DLA . The detailed explanation is made below. When CE becomes low in level at t₈,  FW and  A rise in potential so that a set cycle of the color registers 23A and 23B in the flash write cycle is initiated. In this case, DTA is at the high level and DTB is at the low level, and hence "1" and "0" are stored in the color registers 23A and 23B, respectively. While  p falls at t₉ and ₁ rises at t₁₀ and thereafter ₂ rises. Thus, one of the word lines in the arrays 11 and 12 is selected and the memory cells coupled to the selected word line are refreshed by the sense amplifiers 6A and 6B which are enabled by SE1 and SE2 falling in potential in response to ₂. Thereafter, CE is once reset to the high level at t₁₃ and the memory is reset. Then, CE falls again at t₁₄ and  FW and  B rise to start a flash write execution cycle. In this instance, DTA and DTB are at "1" and "0" which means that the array 11 is to be subjected to the flash write operation and the array 12 is subjected not to the flash write operation but to a refresh operation. The levels of DTA and DTB are latched in the registers 24A and 24B, respectively. Thus, FW1 is changed to the low level while FW2 remains at the high level. Accordingly, all the outputs of the column decoder 2A are to be at the selected ("1") level and the pair of bus lines DBA, DBA are electrically connected to all the pairs of digit lines DLA, DLA in the array at t₁₆, irrespective of contents of the column address signals C.A. While, the column decoder 2B activates only one of its outputs or none of them because of the high level of FW2 and any data from the array 12 is not outputted to DTB because  R and  W are at the inactive level. Then, after the fall of  p , ₁ rises at t₁₅ so that one of the word lines WL is selected. At a time point t₁₆, ₃ rises and all the outputs of the column decoder 2A are activated and the data stored in the register 23A is applied to all the pair of digit lines DLA, DLA via the driver 21A and the selection circuit 3A. In this instance, the transistors QS₁ and QS₂ are rendered conductive in response to ₂ and the activation lines SE1 and SE2 are to be discharged by the transistors QS₁ and QS₂. It should be noted that the states of the sense amplifiers 6A are rapidly determined by the driver 21A and the activation line SE1 is rapidly discharged by t₁₇. While, the activation line SE2 for the array 12 is gradually discharged because the potential differences in the respective pairs of digit lines DLB, DLB in the array 12 are small and the sense amplifiers 6B gradually amplify the above potential differences by t₁₈, which is after t₁₇. Accordingly, the activation line SE1 for the array 11 performing the flash write operation and the activation line SE2 for the array 12 performing the refresh operation are separated and driven by the separate transistors QS₁ and QS₂, respectively. Therefore, the sense amplifiers 6A and 6B can operate independently for the different purposes.

Claims: A dynamic memory circuit comprising a plurality of memory cell groups (11, 12), a plurality of sense amplifier groups (6A, 6B), each of said sense amplifier groups being provided for each one of said memory cell groups, a write circuit (22A, 22B) for operatively writing an input data signal to a plurality of memory cells in at least one of said memory cells groups, a plurality of sense amplifier control circuits (QS1, QS2), each of said sense amplifier control circuits being provided for one of said sense amplifier groups and operatively enabling the one sense amplifier group, characterized by means for enabling all said sense amplifier control circuits simultaneously, each sense amplifier group comprising a plurality of bistable differential sense amplifiers (SA), said sense amplifiers (SA) of each sense amplifier group having a common discharge transistor, and said write circuit being able to write a data signal into a plurality of memory cells in at least one of said memory cell groups while refreshing at least one of said remaining memory cell groups. The memory circuit according to claim 1, further comprising means for refreshing the memory cells of the remaining other memory cell group or groups other than the said at least one memory cell group. The memory circuit according to claim 1, in which each sense amplifier (SA) of each of said sense amplifier groups includes a flip-flop circuit and a precharge transistor (Q3 or Q4) for precharging an input/output node of said flip-flop circuit. The memory circuit according to claim 1, in which each of said amplifier control circuits (QS1, QS2) includes a control line ( SE1 , SE2 ) connected to the sense amplifiers (SA) of the associated sense amplifier group, said discharge transistor being coupled between said control line and a predetermined potential source.

Inventors: TOKUSHIGE, KAZUO
Applicants: NEC CORPORATION
Application year: 1988
Main classification: G11C11
IPC codes: G11C11