A register circuit

Abstract: A register circuit comprising a plurality of registers (R1...R7) commonly receiving a data signal (D(in)) and respective selections signals (A1...A7), each of the registers including a first input terminal (D) for receiving the data signal; a second input terminal (A) for receiving a corresponding one of the selection signals; an output terminal (Q) for outputting a stored data signal; a storing unit (M), connected to the output terminal, for storing the data signal; and a control unit (C), connected to the storing unit (M), the first input terminal (D), the second input terminal (A), and the output terminal (Q), for transferring the data signal to the storing unit when the data signal represents "1" and the selection signal is effective, and resetting the storing unit when the data signal represents "1" and the selection signal is not effective.

Description: In an existing register circuit including a plurality of registers each storing a predetermined number of bit data, each of the registers is constituted by a predetermined number of, for example, D-type flip-flop circuits, and an address signal is input to each of the registers. Also, the predetermined number of bit data is input to each of the registers. When one of the above address signals becomes effective, the above data input to each of the registers at that time is stored in the selected register receiving the effective address signal. In this connection, the data already stored in the remaining registers receiving address signals which are not effective is not changed but maintained as is. Thus, according to the above type of register circuit, it is only possible to independently control the data stored in the selected register receiving the effective address signal in accordance with the value of the above input data, and the data already stored in the remaining registers receiving the address signals which are not effective is maintained without change. Therefore, in the above register circuit, if a request is sent to set an effective data (i.e., "1") in a selected register, and to reset the remaining registers, each value of the data already stored in the registers must be monitored outside of the register circuit (e.g. each value of the above data must be successively read out to the outside or each value of the above data must be memorized at the outside by, for example, programming). Then, to write new data "1" or "0" to predetermined registers, it must be determined whether the value of the new data to be written to a predetermined register is different from that of the data already stored in the corresponding register, to prevent data "1" from being simultaneously set in more than one register (i.e. to prevent a double registration). Therefore, in the existing register circuit, a problem arises in that a very complicated process is necessary to set the effective data in a selected register and to reset the remaining registers without generating a double registration. The present invention has been created in view of the above-mentioned problem; an embodiment of the present invention may set the effective data in a selected register, and simultaneously, reset the remaining registers, to thus surely prevent a double registration at the registers without the need for the above complicated operation (i.e. without carrying out the above monitoring and writing operation). DE-A-1 487 826 discloses a register circuit having the features of the preamble of accompanying claim 1. In this register circuit, the control means (gate) receives a reset signal as a first input, together with a signal logically processed from the output of the storing means (flip-flop) as a second input. A selection signal is applied directly to the storing means. According to the present invention, there is provided a register comprising:- a first input terminal for receiving a signal having a set-value or a reset value; a second input terminal for receiving a selection signal; an output terminal for outputting a stored data signal; storing means having an input and an output, the output being connected to said output terminal and arranged to supply said stored data signal; and control means for said storing means, having at least a first input connected to said first input terminal, a second input connected to an output side of the register, and an output connected to the input of said storing means; characterised in that:- said first input terminal is arranged to supply an input data signal to the first input of the control means; the second input of the control means is connected to the output of said storing means so as to receive said stored data signal; and said control means has a third input connected to receive said selection signal; said control means being adapted to selectively transfer to said storing means either said stored data signal or said selection signal in dependence on the logic level of said input data signal. By means of the above arrangement, when the input data signal has a first logic level (e.g. "0"), the storage means is maintained in its existing state. When the input data signal has a second logic level (e.g. "1"), the state of the storage means is changed so as, in effect, to reflect the logic level of the selection signal. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a block diagram showing an example of an existing register circuit including a plurality of registers; Fig. 2 is a block diagram showing the overall construction of the register circuit according to one embodiment of the present invention; Fig. 3 is a circuit diagram showing a concrete example of the construction of a bit register included in the register circuit shown in Fig. 2; Fig. 4 is a block diagram showing the overall construction of the register circuit according to another embodiment of the present invention; and Fig. 5 is a block diagram showing the overall construction of an interruption controller in which the register circuit as shown in Fig. 4 is used. In order to clarify the background of the present invention, an existing register circuit comprising a plurality of registers is exemplified in Fig. 1. The register circuit shown in Fig. 1 comprises three registers (1-bit registers) R1′, R2′, and R3′, and address signals A1, A2, and A3 are input respectively to the registers R1′, R2′, and R3′. Also, data D(in) is input to each of the registers R1′, R2′, and R3′. Each of the registers R1′, R2′, and R3′ is constituted by, for example, a D-type flip-flop circuit. When one of the above address signals A1 to A3 (e.g., the address signal A1) becomes effective, i.e., becomes "1"), the data D(in) input to each of the registers at that time is stored in the selected register (e.g., the register R1′) receiving the effective address signal. For example, if the address signal A1 becomes effective (e.g., becomes "1") and the data D(in) input to the register R1′ at that time is "1", the data "1" is set in the register R1′, and as a result, the output D(OUT)1 of the register R1′ also becomes "1" (e.g., high potential level). On the other hand, if the address signal A1 becomes effective (e.g., becomes "1") and the data D(in) input to the register R1′ at that time is "0", the register R1′ is reset, and as a result, the output D(OUT)1 of the register R1′ becomes "0" (e.g., low potential level). In this connection, the data already stored in the remaining registers (e.g., registers R2′ and R3′) receiving address signals which are not effective (e.g., "0") is not changed (i.e., the already stored data is maintained as is, and as a result, the outputs D(OUT)2 and D(OUT)3 of the registers R2′ and R3′ are not changed. In other words, in the register receiving the effective address signal, the register is set or reset (i.e., the data stored in the register becomes "1" or "0"), in accordance with the value (i.e., "1" or "0") of the data D(in) input to the register. Also, in the register receiving address signals which are not effective, data already stored in the registers is not changed (i.e., the already stored data is maintained as is). Thus, according to the above type of register circuit, it is only possible to independently control the data stored in the selected register (i.e., to set or reset the selected register) receiving the effective address signal in accordance with the value of the above data D(in), and the data already stored in the remaining registers receiving the address signals which are not effective is maintained without change. In the above case, although each of the registers R1′, R2′, and R3′ is a one bit register, even if each of the above registers is storing a plurality of bit data, it is only possible to independently control the plurality of bit data stored in the selected register receiving the effective address signal in accordance with the plurality of bit data D(in) supplied to the selected register, and the data already stored in the remaining registers receiving the address signals which are not effective is not changed, as above-mentioned. Therefore, in the above register circuit, if a request is sent to set data "1" in a selected register and to reset the remaining registers, each value of the data already stored in the registers must be monitored outside of the register circuit (e.g., each value of the above data must be successively read out to the outside or each value of the above data must be memorized at the outside by, for example, programming). Then, to write new data "1" or "0" to predetermined registers, it must be determined whether the value of the new data to be written to a predetermined register is different from that of the data already stored in the corresponding register, to prevent data "1" from being simultaneously set in more than one register (i.e., to prevent a double registration). For example, in the circuit shown in Fig. 1, if a request is sent to write data "0", "1", and "0" in the registers R1′, R2′, and R3′, respectively, when the data "1", "0", and "0" is already stored in the registers R1′, R2′, and R3′, respectively, a read of the data already stored in the registers must be first carried out. Then, in the register R1′ in which the data "1" is already stored, the register R1′ is reset by supplying the effective address signal A1 and the data D(in) having the value "0" to the register R1′. Next, in the register R2′ in which the data "0" is already stored, the register R2′ is set by supplying the effective address signal A2 and the data D(in) having the value "1" to the register R2′. Therefore, in the existing register circuit as shown in Fig. 1, a problem arises in that the above complicated process is necessary to set the data which is effective (e.g., the data "1") in a selected register and to reset the remaining registers without generating a double registration. The present invention has been created in view of the above-mentioned problem, and Fig. 2 shows the entire construction of one embodiment of a register circuit according to the present invention. As shown in Fig. 2, the register circuit comprises a plurality of bit registers (in this case, seven bit registers R1 to R7), and address signals (bit selection signals) A1 to A7 are input respectively to the bit registers R1 to R7 through corresponding input terminals A. Also, data D(in) is input commonly to each of the bit registers R1 to R7 through corresponding input terminals D. When one of the address signals (bit selection signals) A1 to An (e.g., the signal A1) becomes effective (e.g., becomes "1"), the remaining address signals (e.g., the signals A2 to A7) become ineffective (e.g, become "0"). When the data D(in) which is effective (e.g., "1") is input to the bit registers R1 to R7 when one of the address signals (e.g., A1) is effective, the effective data D(in) is set in the bit register (e.g., R1) receiving the effective address signal (e.g., A1), and as a result, the output supplied from a corresponding output terminal Q (in this case, D(OUT)1) of the corresponding bit register becomes "1" (e.g., high potential level). On the other hand, in the remaining bit registers (in this case, R2 to R7) receiving the address signals which are not effective, the bit registers R2 to R7 are reset simultaneously with the setting of the effective data in the bit register R1 receiving the effective address signal, and as a result, the outputs supplied from corresponding output terminals Q (in this case, D(OUT)2 to D(OUT)7) of the remaining bit registers become "0" (e.g., low potential level). A gate signal G is also supplied to the bit registers R1 to R7, and each of the bit registers is set or reset as above-mentioned, or latched as is, when the gate signal G is supplied to the bit registers. Further, a set signal S is supplied to each of the bit registers R1 to R7, and the effective data (e.g., "1") is initially set in the bit registers when receiving the set signal S having a predetermined value (in this case, "1"). Also, a reset signal R is supplied to each of the bit registers R1 to R7, and the bit registers are initially reset when receiving the reset signal R having a predetermined value (in this case, "0"). Thus, it is possible to initially set or reset each of the bit registers, when electric power is supplied to each of the bit registers, for example, regardless of the supply of predetermined address signals and the effective data D(in). Figure 3 is a circuit diagram showing a concrete example of the construction of one of the bit registers (e.g., the bit register R1) included in the register circuit shown in Fig. 2. In Fig. 3, reference symbol C denotes a controlling circuit portion (control means) and reference symbol M denotes a register portion (storing means). The controlling circuit portion C comprises NAND gates C1, C3, and C4, and an inverter C2. The data D(in) and the address signal (the bit selection signal) A1 are input to the NAND gate C1. The data D(in) is also input to the inverter C2. The output signal from the inverter C2 is supplied to the NAND gate C3 as one input, and the output signal from a D type flip-flop circuit FF provided in the register portion M is fed back to the NAND gate C3 as another input. The output signals from the NAND gates C1 and C3 are input to the NAND gate C4. The register portion (storing means) M comprises the D type flip-flop circuit FF and inverters I1 and I2, and the output signal from the NAND gate C4 is input to the terminal D of the flip-flop circuit FF. The gate signal G is input to the terminal G of the flip-flop circuit FF through the inverter I1; the set signal S is input to the terminal S of the flip-flop circuit FF through the inverter I2; and, the reset signal R is directly input to the terminal R of the flip-flop circuit FF. The output Q of the flip-flop circuit FF is supplied from the output terminal thereof to the outside, as the output signal D(OUT)1. Thus, the state of the output Q of one of the bit registers (e.g., the bit register R1) produced when the data D(in), the corresponding address signal A (e.g., the address signal A1), the gate signal G, the set signal S, and the reset signal R , each having a predetermined value (i.e., "1" or "0") are input to the corresponding bit register (e.g., the bit register R1) is represented by a Truth Table, as shown in the following Table I. As shown in the third line of Table I, when the data D(in) and the address signal A, both of which are effective (i.e., "1"), are input to a predetermined bit register, the data "1" is set in the corresponding bit register (i.e., the output Q of the bit register becomes "1") when the effective gate signal G having the value "1" is input to the corresponding bit register. At that time, both the set signal S and the reset signal R are made ineffective (i.e., "0" and "1", respectively). Also, as shown in the second line of Table I, when the data D(in), which is effective (i.e., "1"), and the address signal A, which is not effective (i.e., "0"), are input to a predetermined bit register, the corresponding bit register is reset (i.e., the output Q of the bit register becomes "0") when the effective gate signal G having the value "1" is input to the corresponding bit register. At that time, both the set signal S and the reset signal R are made ineffective (i.e., "0" and "1", respectively). In this connection, in the existing register circuit as shown in Fig. 1, if the address signal A supplied to a predetermined bit register is not effective (i.e., "0"), the data already stored in the corresponding bit register is maintained without change, even if the effective data D(in) having the value "1" is supplied to the corresponding bit register, as above-mentioned. Also, as shown in the first line of Table I, when the data D(in) supplied to the bit registers is not effective (i.e., "0"), the data already stored in the bit registers (i.e., each output Q of the bit registers) is maintained without change, regardless of the value of the address signal A supplied to the respective register, and regardless of the supply of the effective gate signal G having the value "1". Of course, at that time, both the set signal S and the reset signal R are made ineffective. In this connection, in the type of register circuit as shown in Fig. 1, if the address signal A supplied to a predetermined bit register is effective (i.e., "1") and the data D(in) supplied to the corresponding bit register is not effective (i.e., "0"), the corresponding bit register is reset (i.e., the output Q of the corresponding bit register becomes "0"). Further, as shown in the fourth line of Table I, while the gate signal G supplied to the bit registers is not effective (i.e., "0"), the data already stored in the bit registers (i.e., each output Q of the bit registers) is maintained without change (i.e., is latched in the bit registers). Of course, at that time, both the set signal S and the reset signal R are made ineffective. Further, as shown in the fifth line of Table I, when the reset signal R supplied to a predetermined bit register becomes effective (i.e., "0"), the corresponding bit register is initially reset (i.e., the output Q of the bit register is initially set to "0"). At that time, the set signal S is made ineffective (i.e., "0"). Also, as shown in the sixth line of the Table I, when the set signal S supplied to a predetermined bit register becomes effective (i.e., "1"), the corresponding bit register is initially set (i.e., the output Q of the bit register is initially set to "1"). In this connection, the symbol "*" shown in the above Table I means that the value of the corresponding data (or signal) has no influence on the result of the output Q of the bit register. Figure 4 shows the entire construction of another embodiment of the register circuit according to the present invention. As shown in Fig. 4, the register circuit comprises n rows x m columns of bit registers (in this case, seven rows x seven columns of bit registers R11 to R17, R21 to R27, ..., R71 to R77) arranged in a matrix state. A bit selection signal (corresponding to an address signal) BS1 is input to the bit registers R11 to R17 arranged in the first row of the bit registers, a bit selection signal BS2 is input to the bit registers R21 to R27 arranged in the second row of the bit registers, and so on until a bit selection signal BS7 is input to the bit registers R71 to R77 arranged in the seventh row of the bit registers. Also, data D(in)1 is input to the bit registers R11 to R71 arranged in the first column of the bit registers, data D(in)2 is input to the bit registers R12 to R72 arranged in the second column of the bit registers, and so on until data D(in)7 is input to the bit registers R17 to R77 arranged in the seventh column of the bit registers. Accordingly, when the effective data (e.g., "1") is input at the time that one of the bit selection signals BS1 to BS7 is effective (e.g., "1"), the effective data is set in the bit register to which the effective data and the effective bit selection signal are input, and the remaining bit registers arranged in the same column as that of the bit register in which the above effective data is set are reset simultaneously with the setting of the above effective data in the above bit register. For example, if the bit selection signal BS1 becomes effective (in this case, "1") and the effective data D(in)1 is input to the bit registers R11 to R71 when the effective data "1" is set in the bit register R21, for example, the effective data "1" is set in the bit register R11 to which the effective bit selection signal BS1 and the effective data D(in)1 are input, and as a result, the output D(OUT)11 of the bit register R11 becomes "1" (e.g., high potential level). Simultaneously, the bit register R21 is automatically reset as the bit selection signal BS2 is made ineffective (i.e., "0") at that time, and as a result, the output D(OUT)21 of the bit register R21 becomes "0" (e.g., low potential level). Accordingly, in the bit registers arranged in the same column (e.g., the bit registers R11 to R71), the effective data "1" is set in only one of the selected bit registers (e.g., the bit register R11), and at that time, the remaining bit registers (in this case, the bit registers R21 to R71) are reset. Namely, in the above case, the output D(OUT)11 of the bit register R11 becomes "1" and the outputs D(OUT)21 to D(OUT)71 of the bit registers R21 to R71 become "0". Accordingly, it is possible to prevent a double registration in each column of the bit registers, without the need for a complicated operation. In the above circuit shown in Fig. 4, although the gate signal G, the set signal S, and the reset signal R are not shown, these signals are supplied to each of the bit registers as shown in Fig. 2. In this connection, the gate signal may be commonly supplied to each of the bit registers to determine the timing for setting or resetting predetermined bit registers. Also, the set signal and the reset signal may be separately supplied to each of the bit registers to initially and independently set or reset each of the bit registers. Therefore, by using the register circuit shown in Fig. 4, it is possible to correctly register interruption priority orders for interruption signals input from a plurality of systems positioned at the outside, for example. Namely, when the interruption priority orders for seven systems (i.e., first to seventh systems) are registered in the register circuit as shown in Fig. 4, the register circuit is constructed so as to input the data D(in)1 to D(in)7 each corresponding to one of the interruption signals supplied from the first to the seventh systems and the bit selection signals BS1 to BS7 each corresponding to one of the interruption priority orders for the first to the seventh systems. Therefore, if the effective data D(in)1 is input when the bit selection signal BS1 is effective, the effective data D(in)1 (i.e., the data "1") is set in the bit register R11 (i.e., the output D(OUT)11 of the bit register R11 becomes "1"), and as a result, the interruption priority order for the first system becomes the first order. Similarly, if the effective data D(in)7 is input when the bit selection signal BS2 is effective, the effective data D(in)7 (i.e., the data "1") is set in the bit register R27 (i.e., the output D(OUT) 27 of the bit register R27 becomes "1"), and as a result, the interruption priority order for the seventh system becomes the second order. By carrying out a similar operation, each interruption priority order for the first to the seventh systems may be selectively registered in one of the bit registers arranged in a predetermined column of the register circuit. In this connection, it is of course possible for the user to freely change the above order of the interruption priority for each system by carrying out the above operation. Figure 5 shows the entire construction of a interruption controller 1 including the register circuit shown in Fig. 4. An interruption signal from each of systems (e.g., from each of the above first to seventh systems) is input to an interruption conversion portion 12 through an input portion 11. A level management register 13 comprises the register circuit as shown in Fig. 4. The address signals (e.g., the bit selection signals BS1 to BS7 as shown in Fig. 4) are input through an address bus to the register circuit and the data D(in) (e.g., the data D(in)1 to D(in)7 as shown in Fig. 4) are input through a data bus to the register circuit. Therefore, the interruption priority orders for the above systems may be registered in predetermined bit registers arranged in a separate column of the bit registers, when the user supplies the effective data and the effective bit selection signal to each of the predetermined bit registers, as in the register circuit shown in Fig. 4. It is of course possible for the user to freely change the order of the interruption priority for each system by supplying predetermined effective data and predetermined bit selection signals through the address bus and the data bus to the register circuit. Thus, if the interruption signal from one of the above systems (e.g., the first system) is input to the interruption conversion portion 12, a comparison between the input interruption signal and the outputs of the level management register 13 corresponding to the outputs of the above register circuit is carried out. Accordingly, the order of the interruption priority of the input interruption signal (e.g., the interruption signal from the first system) is detected, and the output signal having a level corresponding to the detected order of the interruption priority is supplied to the CPU 2 through the output portion 14. In this connection, if a plurality of interruption signals from more than one of the above systems are simultaneously input to the interruption conversion portion 12, the interruption conversion portion 12 detects which interruption signal has the highest order of interruption priority among the input interruption signals, and the output signal having a level corresponding to the detected highest order of the interruption priority is supplied to the CPU 2 through the output portion 14. Then, the CPU 2 acknowledges the interruption for the interruption signal supplied to the CPU 2 and the interruption acknowledge signal is transmitted from the CPU 2 to the discrimination circuit 15. The discrimination circuit 15 detects the acknowledge level corresponding to the interruption priority order for the acknowledged interruption signal and sends back a predetermined signal corresponding to the detected result to the system from which the acknowledged interruption signal is transmitted. As above-mentioned, by means of the present invention, in the register circuit comprising a plurality of bit registers, it is possible to set the effective data in only a selected bit register, and simultaneously reset the remaining bit registers, and thus prevent a double registration of the bit registers without the need for a complicated operation. As a result, it is, for example, possible to correctly register the interruption priority orders for the interruption signals input from a plurality of systems, and further, to freely change the order of the interruption priority for each system, if desired.

Claims: A register (R1, R2, ...; R11, R12, ...) comprising:- a first input terminal (D) for receiving a signal having a set-value or a reset value; a second input terminal (A) for receiving a selection signal (A1, A2, ...; BS1, BS2, ...); an output terminal (Q) for outputting a stored data signal (D(out)1, D(out)2, ...); storing means (M) having an input and an output, the output being connected to said output terminal (Q) and arranged to supply said stored data signal (D(out)1, D(out)2, ...); and control means (C) for said storing means (M), having at least a first input connected to said first input terminal (D), a second input connected to an output side of the register, and an output connected to the input of said storing means (M); characterised in that:- said first input terminal (D) is arranged to supply an input data signal (D(in); D(in)1, D(in)2, ...) to the first input of the control means (C); the second input of the control means (C) is connected to the output of said storing means (M) so as to receive said stored data signal; and said control means (C) has a third input connected to receive said selection signal (A1, A2, ...; BS1, BS2, ...); said control means (C) being adapted to selectively transfer to said storing means (M) either said stored data signal (D(out)1, D(out)2, ...) or said selection signal (A1, A2, ...; BS1, BS2, ...) in dependence on the logic level of said input data signal (D(in); D(in)1, D(in)2, ...). A register according to claim 1, wherein said control means (C) comprises:- a first NAND gate (C1) receiving the input data signal (D(in)) and the corresponding selection signal (A); a second NAND gate (C3) receiving the stored data signal (D(out)1, D(out)2, ...) and an inverted signal of the input data signal (D(in)); and a third NAND gate (C4) receiving outputs of the first and second NAND gates (C1, C3) and being connected to said storing means (M). A register according to claim 1 or 2, wherein said storing means (M) comprises a flip-flop circuit (FF) connected to said control means (C), and means ( R ) for initially setting the flip-flop to a predetermined state. A register circuit comprising a plurality of registers (R1, R2, ...; R11, R21, ...; R12, R22, ...) each as claimed in claim 1, 2, or 3, wherein the registers are arranged to receive a common input data signal (D(in); D(in)1, D(in)2, ...) and to receive respective selection signals (A1, A2, ...; BS1, BS2, ...). A register circuit as claimed in claim 4, wherein, in use, only one of said selection signals (A1, A2, ...; BS1, BS2, ...) is effective at a time, whereby when said input data signal (D(in); D(in)1, D(in)2, ...) has the set value, the storing means (M) of that one of the registers receiving the effective selection signal stores the input data signal, and the storing means (M) of all the other registers are reset. A register circuit comprising a plurality of registers (R11, R12, ...; R21, R22, ...) each as claimed in claim 1, 2, or 3, wherein each of said registers receives an input data signal (D(in)1, D(in)2, ...), said plurality of registers are divided into a plurality of groups (R11 ...R71; R12, ...R72; ...), and each of said groups receives a corresponding one of the input data signals (D(in)1, D(in)2, ...). A register as claimed in claim 1, 2, or 3, or a register circuit as claimed in claim 4, 5, or 6, wherein the set value of the input data signal (D(in); D(in)1, D(in)2, ...) represents a "1".

Inventors: FUJIYAMA HIROYUKI, NISHIKAWA SINJI, FUJIYAMA, HIROYUKI, NISHIKAWA, SINJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G11C7
IPC codes: G11C11, H03K17, H03K3, G11C7, G06F9