Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective substraction procedure

Abstract: The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. The effective subtraction operation can be accelerated by using two methods of execution depending on whether the absolute value of the difference between the arguments of the exponents, ABS{DELTA(E)} is ≦1 or >1. The procedure for ABS{DELTA(E)}≦1 requires more major process steps than the situation where ABS{DELTA(E)}>1. To accelerate only the procedure having more major process steps, the two least significant bits of both exponent arguments are examined and based on the examination, the lengthier procedure can be initiated in parallel with the process step determining the value of ABS{DELTA(E)}. When the lengthier procedure is determined to be inappropriate based on the determined value, the results of the lengthier process can be discarded. Otherwise, the lengthier process, already in progress, is continued.

Description: RELATED U.S. PATENT APPLIATIONS The following U.S. Patents are related to the present invention. APPARATUS AND METHOD FOR EXECUTION OF FLOATING POINT OPERATIONS, invented by Sridhar Samudrala, Victor Peng and Nachum Moshe Gavrielov, U.S. Patent 4,849,923 filed June 27, 1986 and assigned to the assignee of the present Applications. APPARATUS AND METHOD FOR ACCELERATION OF EFFECTIVE SUBTRACTION PROCEDURES BY THE APPROXIMATION OF THE ABSOLUTE VALUE OF THE EXPONENT ARGUMENT DIFFERENCE, invented by Paul Edward Gronowski, Victor Peng and Nachum Moshe Gavrielov, having U.S. Patent No. 4,858, 165, and assigned to the assignee of the present Application. BACKGROUND OF INVENTION 1. Field of the Invention This invention relates generally to data processing systems and, more particularly, to the apparatus for executing the floating point operations of a data processing system. 2. Description of the Related Art Data processing systems are typically provided with the capability of manipulating numerical quantities stored in the floating point format. A system using a floating point format is disclosed in the document US-A-4,639,887. In the floating point format, a numerical quantity is represented by a fraction value and by an argument value. The argument value represents the power to which the exponent base is raised, while the fraction value represents the number multiplying the exponential portion of the number. The principal advantage of the floating point format is the range of numbers that can be manipulated in the data processing systems without instituting extraordinary procedures or conventions. A floating point processor capable of advantageously using the invention disclosed herein is described in "The MicroVAX 78132 Floating Point Chip" by William R. Bidermann, Amnon Fisher, Burton M. Leary, Robert J. Simcoe and William R. Wheeler, Digital Technical Journal, No. 2, March, 1986, pages 24-36. The floating point format has the disadvantage that the execution of addition and subtraction operations in this data format is more complex and requires a greater time period than the same operation in the standard integer data format. This complexity is a result of having to align the fractions prior to addition or subtraction so that exponents are identical and then, potentially having to normalize the resulting quantity, i.e., shifting the fraction portion of the resulting quantity until a logic "1" is stored in the most significant position and the argument of the exponent is adjusted accordingly. Referring now to Fig. 1, the addition and subtraction operations are defined in terms of effective addition and effective subtraction operations which more correctly identify related operation sequences. The addition and subtraction operations 101 are grouped into an effective addition operation 102 and an effective subtraction operation 103. The effective addition operation 102 includes the operations of adding operands that have the same sign and subtracting operands that have different signs. The effective subtraction operation 103 includes the addition of operands with differing signs and the subtraction of operands with the same sign. Referring next to Fig. 2, the steps in performing the effective subtract operation according to the related art is shown. In step 201, the difference in the exponents is determined. Based on the difference in exponents, the logic signals representing the smaller operands are shifted until the arguments of the exponents representing the two operands are the same, i.e., the operand fractions are aligned. The aligned quantities are then subtracted. If the resulting quantity is negative, then the 2's complement must be calculated, i.e., the subtrahend was larger than the minuend. The most significant non-zero bit position (ie., the leading logic "1" signal is determined and based on this bit position, the resulting quantity operand, is normalized, the leading logic "1" signal is shifted to the most significant bit position and the argument of the exponent is adjusted accordingly. As will be clear to those familiar with the implementation of floating point operations, the seven steps of the effective subtraction operation of Fig. 2 can require a relatively long time for their execution. Another prior art example of an apparatus for performing a floating point operation may be found in an article by S.R. Levine, from the IBM Technical Disclosure Bulletin, Vol. 15, No. 7, Dec. 1972, pp2162. However, said IBM article by Levine does not provide a technique for acceleration of the subtraction operation in a floating point unit in a controlled manner based on two least significant signals. A need has therefore been felt for a procedure and associated apparatus for accelerating the effective subtraction operation. FEATURES OF THE INVENTION It is an object of the present invention to provide improved data processing system. It is a feature of the present invention to provide improved apparatus for the execution of floating point operations. It is another feature of the present invention to provide a technique for acceleration of the effective subtraction operation in a floating point unit. It is a more particular feature of the present invention to provide a selection circuit for controlling operation of the effective subtraction operation based on the two least significant bit signals of the operand exponent arguments. SUMMARY OF THE INVENTION The aforementioned and other features are accomplished, according to the present invention, by providing a floating point execution unit a relatively fast procedure for performing an effective subtraction operation when the absolute value of the difference between operand exponent arguments is greater than 1. When this difference is less than or equal to 1, than a longer procedure is employed. To expedite the effective subtraction operation, the longer procedure is initiated prior to determination of the operand exponent argument difference. Apparatus for comparing the two least significant bit positions of the exponent arguments of two operands permits the correct operands to be used in the longer procedure. This longer procedure is continued until a complete difference between the two exponent arguments is determined. Then the procedure currently being executed can be continued, if, based on the complete operand exponent argument difference, the executing procedure is the correct procedure. Otherwise the executing procedure is replaced by the correct procedure. The invention in its broad form resides in a floating point execution apparatus as in claim 1, and a method of executing a floating point operand operation as generally recited in claim 5. Other features of the present invention will be understood upon reading of the following description along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates the relationship between the addition and subtraction operations and the effective addition and the effective subtraction operations. Figure 2 illustrates the steps for performing the effective subtraction operation according to the related art. Figure 3 illustrates the two procedures into which the effective subtraction operations are divided in order to accelerate their execution. Figure 4 illustrates the steps in the effective subtraction operation when the absolute value of the difference of the exponent arguments is greater than one. Figure 5 illustrates the steps in the effective subtraction operation when the absolute value of the difference of the exponent arguments is less than or equal to one. Figure 6 is a table illustrating all combinations of the two least significant bits for the two exponent arguments and the operation on the associated operand fractions resulting from the combinations. Figure 7 illustrates the apparatus needed to implement the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures Fig. 1 and Fig. 2 have been described with reference to the related art. Referring to Fig. 3, the effective subtraction operation can be accelerated by first considering the situation where the absolute value of the difference in the arguments of the exponents of the two operands, or the absolute value of DELTA(E), is ≦1 (i.e., is 0 or 1) or is >1 (i.e., all other values), that is, ABS{DELTA(E)}≦1 or ABS{DELTA(E)}>1. Referring next to Fig. 4, the situation where ABS{DELTA(E)}>1 is examined in more detail. Comparing Fig. 4 with Fig. 2, the determining the difference in the arguments of the exponents is performed in each case, in step 201 and in step 401. In step 402 as compared with step 202, the alignment operation requires a relatively large shifter. However, because the larger operand is identified, the subtraction operation, performed in steps 203 and 403 can be performed to insure that a positive resultant quantity is obtained by the operation, obviating, in the process of illustrated in Fig. 4, the necessity of a step equivalent to the step 204 for the negation of the resulting operand. Because of the amount of the difference between operands, the result that the normalization will require a shift of at most one bit position for the resulting operand. A one bit position shift does not require a separate step and the detection of the leading logic "1" signal in step 404A, the normalization in step 404B and the rounding operation in step 404C can be considered a single time consuming step 404 rather than three time consuming steps (i.e., step 205, 206 and 207) in Fig. 2. Referring next to Fig. 5, the technique for reducing the time to execute (i.e., accelerating) the effective subtraction operation when ABS{DELTA(E)}≦1 is shown. In step 501, the difference in the exponent arguments is determined. Because of the small difference in the arguments, the alignment of the fractions in step 502 can be performed without requiring a separate step (or "on the fly") before performing the subtraction step 503. The negation step 504 can be required, but either the normalization step 506 or the rounding step 507 is required but not both. The procedure reduces the seven major steps to five major steps by the floating point apparatus. Comparing the procedures in Fig. 4 and Fig. 5, the effective subtraction operation when ABS{DELTA(E)}≦1 appears to have five major steps, the procedure for ABS{DELTA(E)}>1 has only four major steps. In order to reduce the time to perform the five major steps, the following procedure can be employed. When the assumption is made that ABS{DELTA(E)}≦1, then this procedure can be initiated in parallel to the step of determining the difference in the exponent arguments. Thus the lengthier procedure will have been begun before criterion is established. When the criterion is determined, then the longer procedure already in progress can be continued. Otherwise the shorter procedure can be instituted. However, referring to Fig. 5, the alignment step 502 can have three implementations depending on the result of the difference in arguments of the exponents. In order to utilize the accelerated effective subtraction, an expedited procedure must be developed to determine which of the three alignment procedures should be utilized. The present invention examines only the two least significant bits (lsbs) of the argument of the exponent to provide this determination. Referring next to Fig. 6, all the possible combinations for the two least significant bits of each argument is explicitly shown. The ABS{DELTA(E)} = 0 for exponents illustrated in Examples 1,6, 11, and 16. In these cases, the operation performed in step 503 of Fig. 5 is FRACTION A - FRACTION B of the operands. In Examples 2, 7, 12, and 13, DELTA(E)=-1, indicating that the FRACTION A must be shifted one position to the right so that the operation performed in step 503 of Fig. 5 is FRACTION B - FRACTION A /2. In the Examples 4, 5, 10, and 15 of Fig. 6, DELTA(E)=1. The operation performed as a result of the identification of this value is a shifting of FRACTION B for the alignment step of 502 and the step 503 will be FRACTION A - FRACTION B /2. Finally, for the bit positions in the argument of the exponents having the values illustrated by Examples 3, 8, 9, and 14 wherein ABS{DELTA(E)}>1, the procedure illustrated in Figure 4 is the correct procedure and involves only four major steps. Referring next to Fig. 7, the apparatus required to accelerate the effective subtraction operation when ABS{DELTA(E)}≦1 is illustrated. The two least significant bits of the exponent argument E A and the two least significant bits of the exponent argument E B are applied to detection logic 72. The detection logic 72 selects the appropriate operation to be performed on the two operands as determined by Fig. 6. The FRACTION A and FRACTION B signal groups, applied to the selection logic 71 are shifted where appropriate and applied to the input terminals of the subtraction unit 73 as determined by the output signals of the detection logic 72. (The X A =FRACTION A or =FRACTION A /2 and X B =FRACTION B or =FRACTION B /2.) 2. Operation of the Preferred Embodiment The present invention accelerates the effective subtraction procedure by determining which of two procedures is appropriate. The invention then adds additional apparatus to permit the longer of two possible procedures to begin execution in parallel with the determination of which of the two procedures is correct. When the longer of the two procedures is correct, then the execution of the longer procedure, already begun, continues. The additional apparatus permits a rapid selection of the three possible subroutines implementing the longer procedure. The additional apparatus controls the operand fractions used in the longer (Fig. 5) procedure based on a comparison the 2 least significant bits of the two operand exponent arguments. When the shorter of the two procedures is correct, the execution of the longer procedure is discontinued and execution of the shorter procedure begun. The additional equipment to implement the invention is minimal while an improvement in the worst case execution time can be achieved. The invention has application to a variety of floating point execution procedures such as the IEEE P754 standard. In the preferred embodiment, the floating point execution unit operates under microprocessor control.

Claims: A floating point execution unit including addition means for performing an addition operation involving two initial operands in a floating point format in which operands with differing signs are subtracted and operands with the same sign are added, and a subtraction means for performing a subtraction operation involving two operands in a floating point format in which operands with differing signs are added and operands with the same sign are subtracted, said subtraction means including: difference means for determining an exponent difference between operand exponent arguments, alignment means for aligning operand fractions, said operand fraction alignment being operated by shifting a subtrahend operand fraction a number of bit positions determined by said exponent difference, subtrahend and minuend operand fractions being determined based on said exponent difference, a subtraction unit for subtracting said subtrahend operand fraction from said minuend operand fraction, characterized in that said alignment means and said subtraction unit initiates a first substraction procedure in which the operand fractions are selected among the initial operand fractions and a shifted version of said initial operand fractions in accordance with the comparison result of the two least significant bits of the operand exponent arguments, said first substraction procedure being initiated prior to the completion of said exponent difference determining with the assumption that said exponent difference has an absolute value less than or equal 1, in that said substraction unit and said alignment means discontinue said first substraction procedure and initiate a second substraction procedure if said completed exponent difference is determined to be greater than 1, wherein said exponent difference between operand exponent arguments determines the subtrahend operand fraction and the minuend operand fraction, and the number of bit positions said subtrahend operand fraction is shifted by said alignment means, otherwise, said substraction unit continues said first substraction procedure whereby the longer substraction procedure is initiated before the shorter one. The floating point execution unit of Claim 1 wherein said subtraction means includes a selection means responsive to said exponent arguments for determining operand fractions used in said first procedure. The floating point execution unit of Claim 2 wherein said selection means is responsive to two least significant bits of said exponent arguments of said operands. The floating point execution unit of Claim 3 wherein said selection means can cause a selected operand fraction to be divided by two. A method of executing a floating point operand operation including an addition operation involving two initial operands in a floating point format in which operands with differing signs are subtracted, and operands with the same sign are added, and including a subtraction operation involving two operands in a floating point format in which operands with differing signs are added and operands with the same sign are subtracted, said subtraction operation comprising the steps of: determining an exponent difference between exponent arguments of two operands; aligning operand fractions by shifting a subtrahend operand fraction by a number of bit positions determined by said exponent difference, subtrahend and minuend operand fractions are determined based on said exponent diffence subtrating said subtrahend operand fraction from said minuend operand fraction, characterized by the steps of initiating a first substraction procedure in which the operand fractions are selected among the initial operand fractions and a shifted version of said initial operand fractions in accordance with the comparison result of the two least significant bits of the operand exponent arguments, said first substraction procedure being initiated prior the completion of said exponent difference determining step with the assumption that said exponent difference has an absolute value less than or equal 1, in that said substraction unit and said alignment means discontinue said first substraction procedure and inititiate a second substraction procedure if said completed exponent difference is determined to be greater than 1, said exponent difference between operand exponent arguments determining; (i) the substrahend operation fraction and the minuend operand fraction and, (ii) the number of bit positions which said subtrahend operand fraction is shifted by said alignment means, otherwise continuing said first subtraction procedure, whereby the longer subtraction procedure is intitiated before the shorter one. The method of executing a floating point operand effective subtract operation of Claim 5 further comprising the step of dividing a selected operand fraction by two for predetermined results of said comparing step.

Inventors: GAVRIELOV NACHUM MOSHE, MAHESHWARI VIJAY, SAMUDRALA SRIDHAR, GAVRIELOV, NACHUM MOSHE, MAHESHWARI, VIJAY, SAMUDRALA, SRIDHAR
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1988
Main classification: G06F7
IPC codes: G06F7