GALOIS FIELD ARITHMETIC UNIT

Abstract: An arithmetic unit for checking and correcting code error that is used for recording and reproducing data onto or from a me­ dium such as an optical disc. Since this unit allows operation of Galois field to be repeated recurrently, it makes possible to conduct ordinary correction of unknown error of the error position even for the codes having a large minimum distance and to effect erasure correction for the known error position using an external pointer etc., at high speeds and efficiently.

Description: TECHNICAL FIELD The present invention relates to a code error detect and correct apparatus employed in a case where data recording and playback operations are effected on a medium such as an optical disk in which even for a code system having a large value of the minimum or hamming distance, an ordinary correction of an error of which the error position or location is unknown and an erasure correction of an error of which the error position is known, for example, by use of an external pointer can be efficiently accomplished at a high speed. BACKGROUND ART Recently, development of a data recording and playback apparatus using an optical disk has been vigorously conducted. When compared with a magnetic disk, the optical disk memory is capable of storing therein a greater amount of data; however, there exists a disadvantage that the recording medium is attended with a high raw error rate. In consequence, there has been generally known a method in which in a recording operation, a check code is added to an information code as data do as to configure a code word such that the code word is recorded as an error detect and correct code on an optical disk, so that in a playback operation, an error of the information code is detected and is corrected by use of the check code thus added thereto. As such an error detect and correct code, attention has been recently given to the Reed-Solomon code with a hamming or minimum distance being set to about 17, d = 17. In the Reed-Solomon code above, after a parity computation by encoding data is effected as encoding operation, the data is written in a medium together with the parity such that after reading the data therefrom, a decoding operation is effected on the data, namely, a syndrome computation, an error count estimation, a computation of coefficients for an error location polynomial, an error location computation, and an error value computation are accomplished in a sequential fashion. In this case, the number of correctable errors is (d - 1)/2 (ordinary correction) in a case where the error locations are unknown and is d - 1 (erasure correction) in a case where the error location are known. In addition, when a portion (= L) of error positions is known and there also exist errors for which the positions are unknown, the errors for which the maximum number of unknown error positions is t (= (d - L - 1)/2 + L) can be corrected together with the L errors for which the error positions are known. According to an article, On Decoding BHC Codes, G. David Forney Jr., IEEE Trans. IT-11, pp. 549-557, 1965; there has been introduced, for example, a computing method of σ i,L employed to attain a modified syndrome Tk; however, an algorithm to obtain an error value is considerably complicated. In an item A of page 553 in the article above, there is described an example of an algorithm in which based on the modified syndrome, error positions which have been unknown are obtained so as to compute coefficients of an error location polynomial together with the error location by use of a pointer; thereafter, error values are attained for the error locations or positions which have been unknown so as to obtain error values corresponding to the error locations associated with the pointer. In general, the iterative or repeating operation is easily adapted to an erasure algorithm, and in a case of a product code often used, codes having a short distance are combined such that an error detection is achieved by use of one of the codes and an erasure correction is effected by use of the other one of the codes; or, even for codes having a long distance, it is easier to effect the erasure correction after the error locations are obtained. As described above, a method of attaining the error value when there exist errors for which the error locations are known and those for which the error locations are unknown has been found in an article; however, it has been known that the amount of computations is greatly increased when the minimum or hamming distance of the codes becomes to be great, and hence the realtime correction cannot be effected in a practical case. In addition, although there may be disposed a dedicated hardware to increase the operation speed, the amount of the circuits increases too much, which leads to a problem that the practicability is decreased. DISCLOSURE OF THE INVENTION It is therefore an object of the present invention to provide a Galois field arithmetic unit which can effect a high-speed processing and which minimizes the amount of the hardware thereof, thereby solving the problems above. In order to achieve the object above, according to the present invention as defined in the appended independent claims 1 and 2, for error correction linear codes having a hamming distance d in which the codes are constituted with a element of a Galois field (GF(2 r )), a modified syndrome T k (T o ... T d-2-L ) is obtained by use of a syndrome associated with S o to S d-2 and the numbers of L known error locations from X o to X L-1 , such that the procedure like that of the foregoing article is employed for computation up to a point where the unknown error locations are computed. In fact, this prior art discloses a Galois field arithmetic unit in a data transmission system in which a code word of error correction linear codes having hamming distance of d includes elements of a Galois field GF(2 r ) and a receive code word and error location numbers thereof are received as inputs thereto comprising a syndrome generate circuit for generating syndromes ranging from S o to S d-2 in response to the received inputs, first compute means to attain, for L known error location numbers from X o to X L-1 , coefficients of an error location polynomial σ i,j = σ i, j-1 * X j-1 + σ i-1, j-1 by assuming that σ j,j = 1 under conditions that 0<=j<=L, j running for errors having a known position, J>=i>=0, and variables for which the subscript in the right side of the expression does not satisfy the inequality are 0 and second compute means to compute the modified syndrome T k for k ranging from 0 to d - 2 - L by use of the σ i,j attained from said first compute means and the syndromes produced from said syndrome generate circuit according to T k = i=o Σ L σ i,L x S k+i . In accordance with the invention, from the σ i,j computed when the modified syndrome is obtained, the intermediate result P j is obtained from so that the error value is computed by use of the correction syndrome like in the ordinary correction to attain an intermediate value Y L,L ... Y L+t-1,L so as to compute by use of the intermediate value of the error value, the error location x i associated with the pointer, and the intermediate result P j . In addition, to the subsequent Y j-1,j-1 associated with j-1, the computation result attained by assuming Y i,j+1 /(X i + X j ) = Y i, j in the right side of the formula above and the computation result Y j,j of the left side, thereby finally attaining the error values Y₀ ... Y L-1 ... Y L-1+t . According to the present invention, in the encoding or decoding operation of the Reed-Solomon code by use of the procedure above, after the syndrome of the code word is computed, there are given a location assumed to be associated with an error and a known error location indicated by the pointer so as to achieve a repeating operation including a sequence of the multiplication, division, and addition of a Galois field, thereby conducting an error correction including an encoding or erasure of the check code. Since the number of computations of this procedure is greatly reduced as compared with the conventional method, this procedure is applicable to a case where a realtime processing is required; moreover, the amount of circuits is considerably minimized, which also enables the processing above to be effected. BRIEF DESCRIPTION OF DRAWINGS Fig. 1a is a block diagram showing a first embodiment according to the present invention, Fig. 1b is a flowchart showing the operation of first compute means employed in the first embodiment of Fig. 1a, Fig. 1c is a flowchart showing operations of second, third, and fourth compute means adopted in the first embodiment of Fig. 1a, and Figs. 1d and 1e are flowcharts showing operations of fifth and sixth compute means adopted in the first embodiment of Fig. 1a. In addition, Fig. 2a is a block diagram showing a second embodiment according to the present invention, Fig. 2b, is a flowchart showing operations of first and seventh compute means adopted in the second embodiment of Fig. 2a, and Fig. 2c is a flowchart showing operations of second, third, and fourth compute means adopted in the second embodiment of Fig. 2a. Furthermore, Fig. 2d is a flowchart showing operations of fifth and eighth compute means adopted in the second embodiment of Fig. 2a. In addition, Fig. 3 is a circuit diagram showing details of a syndrome generate circuit. BEST MODE FOR CARRYING OUT THE INVENTION Referring now to the drawings, description will be given of a Galois field arithmetic unit as an embodiment according to the present invention. Fig. 1a is a block diagram of a first embodiment according to the present invention. Fig. 1b is a flowchart showing the operation of first compute means employed in the first embodiment of Fig. 1a. In addition, Fig. 1c is a flowchart showing operations of second, third, and fourth compute means adopted in the first embodiment of Fig. 1a. Furthermore, Figs. 1d and 1e are flowcharts showing operations of fifth compute means adopted in the first embodiment of Fig. 1a. In Fig. 1a, 52 indicates a syndrome generate circuit and 53 is a code word memory circuit. Reference numeral 54 designates a Galois field arithmetic circuit for executing operations of a Galois field by use of a microprogram at a high speed. In addition, a signal detect circuit in an optical disk drive detects a drop out so as to effect a detection thereof with an error location to be associated with a pointer. For the error location, a value of an error location counter operative according to a code recording format in a decoding is written from an input/output bus of the code word memory circuit 53 in a vector representation. Moreover, the code word memory circuit 53 is connected via an input/output bus to a decode circuit and a modulation circuit in the optical disk drive or to a host computer interface circuit. Fig. 3 is a circuit diagram showing details of the syndrome generate circuit. The configuration of Fig. 3 includes a logical product gate circuit 1 associated with a total of eight bits, an input change-over switch logic circuit 2, 0-th to fifth 8-bit register circuits 3 to 8, a 15-th 8-bit register circuit 18, 0-th to fifth change-over switch logic circuits 19 to 24, 15th switch logic circuit 34, and α⁰ to α⁵ Galois field multiply circuits 35 to 40. In addition, 51 denotes a Galois field add circuit (exclusive OR logical sum gate circuit). In Fig. 3, sixth to 14th circuit components are omitted. Next, description will be given of the operation of the syndrome generate circuit. In this example, the operation is accomplished in GF(2⁸). First, a receive word sent from the decode circuit is fed to and is then stored in the code word memory circuit 53 for a decoding operation thereof. Thereafter, the receive word is fed from the code word memory circuit 53 to the syndrome generate circuit 52. An initial setup is beforehand effected by means of the logical product gate 1 and the input change-over switch logic circuit 2 so that the contents of the 8-bit register circuits 3 to 18 include 0 element. Subsequently, the receive word of n symbols from the decode circuit accumulated in the code word memory circuit 53 is inputted via a data terminal DATA to the logical product gate circuit 1. The logical product gate circuit 1 is activated when data is supplied from the data terminal. Outputs therefrom are fed to the Galois field add circuit 51 (exclusive OR logic unit), and at the same time, the input change-over switch circuit 2 is changed over so that the outputs are added to values of multiplication results fed back from the Galois field multiply circuits 35 to 50, thereby completing input operations of n symbols. Thereafter, the contents of the 8-bit registers 3 to 18 are selected through the change-over switch logic circuits 19 to 34 so as to attain syndromes S₀ to S₁₅. In this embodiment, since there is adopted a Reed-Solomon code of the hamming distance d = 17, the number of syndromes is d - 2, namely, 15 symbols. The syndromes S₀ to S₁₅ are supplied to the Galois field arithmetic circuit 54. The Galois field arithmetic circuit 54 includes first to sixth compute means. In the first compute means, known error location numbers X₀ to X L-1 are received as pointers from the code word memory circuit 53 so as to compute σ i,j and then to store the computed result. The value of σ i,j is used in a process to attain the modified syndrome T k and the error value Y j,o . Details about the operations are shown in the flowchart of Fig. 1b. In the second compute means, based on the value of σ i,j attained from the first compute means and the syndrome read from the syndrome generate circuit 52, the modified syndrome T k is computed. Details about this operation is shown in a flowchart 55 of Fig. 1c. In the third compute means, the error location polynomial σ t (z) and the error evaluation polynomial η t (z) are obtained from the correction syndrome determined in the second compute means. Details about this operation is shown in a flowchart 56 of Fig. 1c. In addition, the fourth compute means is used to obtain the unknown error location numbers X L ... X L+t-1 from the error location polynomial σ t (z) determined by the third compute means, which corresponds to a portion 57 of the flowchart of Fig. 1c. The fifth compute means is a section to obtain the error value intermediate values Y L,L ... Y L,L+t-1 by assigning the error locations attained by the fourth compute means to the error evaluation polynomial η t (z), which corresponds to the flowchart 58 of Fig. 1b. The sixth compute means is employed to compute the error value Y i,0 from σ i,j attained by the first compute means and the error value intermediate values Y L,L ... Y L,L+t-1 determined by the fifth compute means, and details thereabout is shown in Figs. 1d and 1e. A portion 59 of the flowchart of Fig. 1d and a portion 59 of the flowchart of Fig. 1e respectively show the first and second halves of the computation of the error value Y i,0 . A reference numeral 60 indicates a flowchart portion to conduct a final error correction. In this process, the error location numbers are converted from the vector representation into the power expression such that an address is presented in the code word memory circuit 53 so as to read an error symbol to be added to the computed error value, thereby writing the resultant value again in the same position of the code word memory circuit 53. Details of the operations of the first embodiment of the Galois field arithmetic unit configured as described above will be described with reference to Figs. 1a to 1e and Fig. 3. Assume here that a total of nine values exist for the objective error values Y j, 0, namely, errors of J = 8 to 6 for which the error locations are unknown and errors of j = 5 to 0 for which the error locations are known. Under conditions that 0 ≦ j ≦ L and J ≧ i ≧ 0 for j and that variables for which the subscript does not satisfy the inequality on the right side are 0, assuming σ j,j = 1, such that for σ i,j = σ i,j-1 × X j-1 + σ i-1,j-1 j is varied from 0 to L and for each value of j, i is changed under the conditions above so as to sequentially effecting the computation procedure, thereby storing the resultant σ i,j . This is because for the computation of σ i,j , it is necessary to adopt the values of σ i,j-1 and σ i-1,j-1 attained in the previous process and because this σ i,j is necessary when the error value is to be computed. Next, based on the σ i,j thus obtained and the syndrome, computation is achieved for the modified syndrome for the values of k ranging from 0 to d-2-L, such that by handling the T k like the syndrome in the ordinary error correction of errors for which the error location numbers are unknown, there are obtained through said Euclid decoding algorithm an error location polynomial σ t (z) for t errors associated with unknown error location numbers and an error evaluation polynomial η t (z) of the intermediate value of the error value. Thereafter, the error locations attained through the Chien's algorithm to compute the error location numbers from the error location polynomial are assigned to the error location polynomial σ t (z) and an error evaluation η t (z) of the intermediate value of the error value so as to obtain the error value intermediate values Y L+t-1,L ... Y L,L , thereby determining the error value from the flowchart 59. In the operations above, there are employed computation formulas for the respective values as follows. Y 5,5 = Y 8,6 /(X₈ + X₅) + Y 7,6 /(X₇ + X₅) + Y 6,6 /(X₆ + X₅) + P₅ where, P₅ = S₅ + σ 4,5 × S₄ + σ 3,5 × S₃ + σ 2,5 × S₂ + σ 1,5 × S₁ + σ 0,5 × S₀ σ 4,5 = X₀ + X₁ + X₂ + X₃ + X₄ = 1 + X₄ + σ 3,4 σ 3,5 = (X₀ + X₁ + X₂ + X₃) × X₄ + (X₀ + X₁ + X₂) × X₃ + (X₀ + X₁) × X₂ + X₀ × X₁ = σ 3,4 × X₄ + σ 2,4 σ 2,5 = ((X₀ + X₁ + X₂) × X₃ + (X₀ + X₁) × X₂ + X₀ × X₁) × X₄ + (X₀ + X₁) × X₂ + X₀ × X₁) × X₃ + X₀ × X₁ × X₂ = σ 2,4 × X₄ + X 1,4 σ 1,5 = (((X₀ + X₁) × X₂ + X₀ × X₁) × X₃ + X₀ × X₁ × X₂) × X₄ + X₀ × X₁ × X₂ × X₃ = σ 1,4 × X₄ + σ 0,4 σ 0,5 = X₀ × X₁ × X₂ × X₃ × X₄ = σ 0,4 × X₄ + O Y 4,4 = Y 8,5 /(X₈ + X₄) + Y 7,5 (X₇ + X₄) + Y 6,5 /(X₆ + X₄) + Y 5,5 /(X₅ + X₄) + P₄ where, Y 8,5 = Y 8,6 /(X₈ + X₅) Y 7,5 = Y 7,6 /(X₇ + X₅) Y 6,5 = Y 6,6 /(X₆ + X₅) P₄ = S₄ + σ 3,4 × S₃ + σ 2,4 × S₂ + σ 1,4 × S₁ + σ 0,4 × S₀ σ 3,4 = X₀ + X₁ + X₂ + X₃ = 1 × X₃ + σ 2,3 σ 2,4 = (X₀ + X₁ + X₂) × X₃ + (X₀ + X₁) × X₂ + X₀ × X₁ = σ 2,3 × X₃ + σ 1,3 σ 1,4 = ((X₀ + X₁) × X₂ + X₀ × X₁) × X₃ + X₀ × X₁ × X₂ = σ 1,3 × X₃ + σ 0,3 σ 0,4 = X₀ × X₁ × X₂ × X₃ = σ 0,3 × X₃ + O Y 3,3 = Y 8,4 /(X₈ + X₃) + Y 7,4 /(X₇ + X₃) + Y 6,4 /(X₆ + X₃) + Y 5,4 /(X₅ + X₃) + Y 4,4 /(X₄ + X₃) + P₃ where, Y 8,4 = Y 8,5 /(X₈ + X₄) Y 7,4 = Y 7,5 /(X₇ + X₄) Y 6,4 = Y 6,5 /(X₆ + X₄) Y 5,4 = Y 5,5 /(X₅ + X₄) P₃ = S₃ + σ 2,3 × S₂ + σ 1,3 × S₁ + σ 0,3 × S₀ σ 2,3 = X₀ + X₁ + X₂ = 1 × X₂ + σ 1,2 σ 1,3 = (X₀ + X₁) × X₂ + X₀ × X₁ = σ 1,2 × X₂ + σ 0,2 σ 0,3 = X₀ × X₁ × X₂ = σ 0,2 × X₂ + O Y 2,2 = Y 8,3 /(X₈ + X₂) + Y 7,3 /(X₇ + X₂) + Y 6,3 /(X₆ + X₂) + Y 5,3 /(X₅ + X₂) + Y 4,3 /(X₄ + X₂) + Y 3,3 /(X₃ + X₂) + P₂ where, Y 8,3 = Y 8,4 /(X₈ + X₃) Y 7,3 = Y 7,4 /(X₇ + X₃) Y 6,3 = Y 6,4 /(X₆ + X₃) Y 5,3 = Y 5,4 /(X₅ + X₃) Y 4,3 = Y 4,4 /(X₄ + X₃) P₂ = S₂ + σ 1,2 × S₁ + σ 0,2 × S₀ σ 1,2 = X₀ + X₁ = 1 × X₁ + σ 0,1 σ 0,2 = X₀ × X₁ = σ 0, 1 × X₁ + O Y 1,1 = Y 8,2 /(X₈ + X₁) + Y 7,2 /(X₇ + X₁) + Y 6,2 /(X₆ + X₁) + Y 5,2 /(X₅ + X₁) + Y 4,2 /(X₄ + X₁) + Y 3,2 /(X₃ + X₁) + Y 2,2 /(X₂ + X₁) + P₁ where, Y 8,2 = Y 8,3 /(X₈ + X₂) Y 7,2 = Y 7,3 /(X₇ + X₂) Y 6,2 = Y 6,3 /(X₆ + X₂) Y 5,2 = Y 5,3 /(X₅ + X₂) Y 4,2 = Y 4,3 /(X₄ + X₂) Y 3,2 = Y 3,3 /(X₃ + X₂) P₁ = S₁ + σ 0,1 × S₀ σ 0, 1 = X₀ Y 0,0 = Y 8,1 /(X₈ + X₀) + Y 7,1 /(X₇ + X₀) + Y 6,1 /(X₆ + X₀) + Y 5,1 /(X₅ + X₀) + Y 4,1 /(X₄ + X₀) + Y 3,1 /(X₃ + X₀) + Y 2,1 /(X₂ + X₀) + Y 1,1 /(X₁ + X₀) + P₀ where, Y 8,1 = Y 8,2 /(X₈ + X₁) Y 7,1 = Y 7,2 /(X₇ + X₁) Y 6,1 = Y 6,2 /(X₆ + X₁) Y 5,1 = Y 5,2 /(X₅ + X₁) Y 4,1 = Y 4,2 /(X₄ + X₁) Y 3,1 = Y 3,2 /(X₃ + X₁) Y 2,1 = Y 2,2 /(X₂ + X₁) P₀ = S₀ At intermediate points of the 0=th error value Y 0,0 attained here, other error values, namely, the first to eighth values are obtained at the same time as follows. Y 1,0 = Y 1,1 /(X₁ + X₀), Y 2,0 = Y 2,1 /(X₂ + X₀), Y 3,0 = Y 3,1 /(X₃ + X₀), Y 4,0 = Y 4,1 /(X₄ + X₀), Y 5,0 = Y 5,1 /(X₅ + X₀), Y 6,0 = Y 6,1 /(X₆ + X₀), Y 7,0 = Y 7,1 /(X₇ + X₀), Y 8,0 = Y 8,1 /(X₈ + X₀), Incidentally, has been assumed in this computation. As described above, in order to obtain Y j,o , the computation of Y j,j is accomplished in a range of j from L-1 to 0. Also in a case where, for attaining the error value, the computation of Y j,j is accomplished according to the formula of like in the computation of σ i,j , it is required to use a computation result of Y i,j+1 , namely, Y i,j = Y i,j+1 /(X i + Y j ) associated with j + 1 of a previous process in the computation process of Y j,j in a range of j from the maximum value of L - 1 to 0. In consequence, when Y i,j+1 /(X i + Y j ) is computed, the result is to be stored in the memory in any such that in the subsequent process, the content of the memory is read therefrom so that the updated value is written again therein. It is convenient to achieve the sequential computations in the procedure above. The new result of the Y j,j thus attained is also written in the memory. When j = 0 results in the repetitious computations as describe above, Y j,0 , namely, the error value is stored in the memory. Furthermore, in an operation to obtain the error value, the σ i,j already determined is read out again so as to be used in the computation. Incidentally, in the computation of Y j,j , it is effective to achieve a multiplication of 1/(X i + Y j ) by use of a reprocical ROM. Referring next to the drawings, description will be given of the Galois field arithmetic unit as a second embodiment according to the present invention. Fig. 2a is a block diagram of the second embodimently according to the present invention. Fig. 2b is a flowchart showing the operations of the first and seventh compute means of the second embodiment and Fig. 2c is a flowchart showing the operations of the second, third, and fourth compute means of the second embodiment, which is basically idential to the flowchart of Fig. 1c; however, in a flowchart portion 55, the computation of the correction syndrome T₀ is not achieved because the computation has already been completed. In addition, Fig. 2d is a flowchart showing the operations of the fifth and eighth compute means of the second embodiment. In Fig. 2a, 52 is a syndrome generate circuit, which is identical to that shown in Fig. 3 and 53 indicates a code word memory circuit. Furthermore, 62 designates a Galois field arithmetic circuit which executes operations of a Galois field by use of a microprogram at a high speed. In Fig. 2b, the first and seventh compute means are combined in this application such that σ i,j computed in the first compute means is kept remained in the register so as to be multiplied by S i , thereby computing the intermediate value P j and a portion T₀ of the correction syndrome to be stored thereafter. Furthermore, in Fig. 2c, the correction syndromes T₁, ..., T d-L-2 are obtained in the similar manner to that employed in Fig. 1c such that the Euclid decoding method of 56 is effected to attain an error location polynomial σ t (Z) associated with t errors for which the error location numbers are unknown and an error evaluation polynomial η t (z) of the intermediate value of the error value to be attained. Thereafter, by effecting a flowchart 58 of Fig. 2d in which the error locations determined through the Chien's algorithm of 57 are assigned to the error location polynomial σ t (z) and an error evaluation polynomial η t (z) of the intermediate value of the error value to be attained, the intermediate values of the error value Y L+t-1,L ... Y L,L are obtained so as to determine the error value by use of a flowchart 61. In 61 of Fig. 2d, the error value Y j,0 is finally computed from the intermediate value P j and the error location numbers stored by use of the seventh compute means of Fig. 1b. Referring to Figs. 2a to 2d and Fig. 3, description will be given of a method employed in the second embodiment of the Galois field arithmetic unit configured as described above. It is assumed that for the error values Y j,0 , there exist nine values associated with errors for J = 8 to 6 for which the error locations are unknown and errors for j = 5 to 0 for which the error location are known. For the computation formula of the respective values, like in the first embodiment, in order to obtain Y j,0 , the computation of Y j,j is conducted for a range of j from L - 1 to 0; however, prior to this computation, it is favorable with respect to the efficiency to obtain the value of P j-1 from the intermediate value P₀. That is, when attaining P j , the computation procedure of σ i,j is set as σ i,j = σ i,j-1 × X j-1 + σ i-1,j-1 such that at the same time, from the attained σ i,j and the syndrome S i , the following computation is achieved. The intermediate value P j thus obtained is stored in another location of the memory. Incidentally, the L-th intermediate value is determined here as follows. Subsequently, like the case of the first embodiment, the remaining modified syndromes and intermediate values of error value Y L+t-1,L ... Y L,L are attained so as to compute the following formula. Also in this case, in the similar fashion to that of the first embodiment, there is employed Y i,j+1 , namely, the computation result of a preceding process in the Y j,j in the range of j from the maximum value L - 1 to 0 as follows. Y i,j = Y i,j+1 /(X i + X j ) In the sequential computation above, when j = 0 results, the memory is loaded with Y j,0 , namely, the objective error value. In a case where the error location numbers are known by use of other means as described above, the erasure correction can be effectively accomplished by using the location numbers in the computation formula; and in a range where the code distance is acceptable, the correction can be systematically accomplished through the procedure described above. As the computation in this procedure, there are required 1.5 × L² + t² multiply operations. Incidentally, in the first embodiment according to the present invention, the multiplication of the 0 element can be omitted by assuming that the result is the 0 element, which is also the case for the multiplication of one. In addition, it is naturally considerable to assign values while achieving the condition judgement, for example, the 0 element is adopted at an intermediate point of the computation in place of an operation to set the initial value. Furthermore, when a sequential computation is to be conducted, it is possible to effect the computation with some results kept remained in devices such a registers. Moreover, these computations may be executed by use of an ordinary microprocessor, and since the multiplication of a Galois field is ordinarily carried out by use of a logarithmic table, the algorithm according to the present invnetion is particularly efficient in the computation. Incidentally, for the parity computation in the encoding operation as well as for the syndrome computation, a considerably high-speed processing is required, and hence also in a case where such processing is effected by the software, there is employed a hardware achieving a parallel operations in many cases. Even in a case where a high-speed processing is necessary, it is also possible to achieve these processing operations including the correction in a softwarewise manner at a speed similar to the speed of the hardware by use of a microprogramming scheme, namely, the processing need not be effected in a purely hardwarewise fashion. If an erasure correction is conducted in a case where the receive information words up to c′ n-1 , c′ n-2 ... c′ d-1 are correct and 0 element errors take place in c′ d-1 , c′ d-3 ... c′₀ associated with d-1 parity words to be generated and are lost as a result, the decoding operation effected by inputting the 0 element on assumption that the error location numbers designate parity positions is exactly equivalent to an operation to accomplish an encoding operation on the information words. That is, if the erasure correction can be carried out by a microprogram at a high speed, it is also possible to achieve the encoding operation at the similar speed. In this situation, when the check word is to be supplied to the syndrome generate circuit of Fig. 3, the 0 element need only be inputted after setting the logical product gate circuit 1 to the active state. In this case, it is assumed that the number t of the unknown errors is 0 and the number L of the known errors is d - 1. In this fashion, only the syndrome compute circuit may be implemented by a dedicated hardware so as to omit the encoding circuit. INDUSTRIAL APPLICABILITY As described above, according to the present invention, it is possible to execute the ordinary correction and the erasure correction at a high speed by use of the syndrome generate circuit and the code word memory circuit in the code error detect and correct apparatus. In consequence, a decoding operation can be practically accomplished on a recording medium having a high value of the raw error rate in apparatuses such as an optical disk device requiring a high speed operation and a high performance, which leads to a considerably advantageous effect.

Claims: A Galois field arithmetic unit in a data transmission system in which a code word of error correction linear codes having hamming distance of d includes elements of a Galois field GF(2 r ), and is utilized for a data transmission, and a receive code word and error location numbers thereof are received as inputs thereto comprising: a syndrome generate circuit for generating syndromes ranging from S₀ to S d-2 in response to the received inputs first compute means for attaining, for L known error location numbers from X₀ to X L-1 , coefficients of an error location polynomial σ i,j = σ i,j-1 × X j-1 + σ i-1,j-1 by assuming that σ j,j = 1 under conditions that 0 ≦ j ≦ L, J ≧ i ≧ 0 and variables for which the subscript in the right side of the expression does not satisfy the inequality are 0; second compute means for computing modified syndrome T k for k ranging from 0 to d - 2 - L by use of the σ i,j attained from said first compute means and the syndromes produced from said syndrome generate circuit according to third compute means operating by use of an error correction algorithm such as a Euclid decoding algorithm in which by using the modified syndrome T k as a syndrome, coefficients of an error location polynomial for t errors associated with unknown error location numbers and coefficients of an error evaluation polynomial of intermediate values of an objective error value are obtained; fourth compute means operating by use of a root solving algorithm such as the Chien's method to attain the error location numbers from the error location polynomial associated with the unknown errors; fifth compute means for computing intermediate values of the error value ranging from Y L,L to Y L+t-1,L by assigning the t error location values obtained by said fourth compute means in the error location polynomial associated with the unknown errors and the error evaluation polynomial; and sixth compute means in which the Y j,0 as all error values for the L + t known and unknown error location numbers, Y j,j is computed by changing j from L - 1 to 0 under condition of i ≦ j according to thereafter, in an expression to attain Y j-1,j-1 for j - 1, a computation result of the right side of the expression above with a condition below Y i,j+1 /(X i + X j ) = Y i,j and a computation result of the left side, Y j,j are assigned, thereby effecting the operation until final error values Y 0,0 ... Y L-1,0 ... Y L-1+t,0 are obtained. A Galois field arithmetic unit in a data transmission system in which a code word of error correction linear codes having hamming distance of d includes elements of a Galois field GF(2 r ), and is utilized for a data transmission, and a receive code word and error location numbers thereof are received as inputs thereto comprising: a syndrome generate circuit for generating syndromes ranging from S₀ to S d-2 in response to the received inputs; first compute means for attaining, for L known error location numbers from X₀ to X L-1 , coefficients of an error location polynomial σ i,j = σ i,j-1 × X j-1 + σ i-1,j-1 by assuming σ j,j = 1 under conditions that 0 ≦ j ≦ L, J ≧ i ≧ 0 and variables for which the subscript in the right side of the expression does not satisfy the inequality are 0; seventh compute means operative, when σ i,j is obtained through a computation process thereof for j by said first compute means under conditions of 0 ≦ j ≦ L, J ≧ i ≧ 0, to store therein a syndrome S i and an intermediate result P j attained from and when the conditions are set as j = L and J ≧ i ≧ 0, to replace P L with so as to store therein a correction syndrome T₀ thus attained for k = 0; second compute means for computing a modified syndrome T k for k ranging from 0 to d - 2 - L by use of the σ i,j attained from said first compute means and the syndromes produced from said syndrome generate circuit according to third compute means operating by use of an error correction algorithm such as a Euclid decoding method in which by using the modified syndrome T k as a syndrome, coefficients of an error location polynomial for t errors associated with unknown error location numbers and coefficients of an error evaluation polynomial of intermediate values of an objective error value are obtained; fourth compute means operating by use of a root solving algorithm such as the Chien's method to attain the error location numbers from the error location polynomial associated with the unknown errors; fifth compute means for computing intermediate values of the object error value ranging from Y L,L to Y L+t-1,L by assigning the t error location values obtained by said fourth compute means in the error location polynomial associated with the unknown errors and the error evaluation polynomial; and eighth compute means in which for Y j,0 as all error values for the L + t known and unknown error location numbers, Y j,j is computed by changing j from L - 1 to 0 according to thereafter, in an expression to attain Y j-1,j-1 for j - 1, a computation result of the right side of the expression above with a condition below Y i,j+1 /(X i + X j ) = Y i,j and a computation result of the left side, Y j,j are assigned, thereby effecting the operation until final error values Y 0,0 , ... Y L-1,0 ... Y L-1+t,0 is obtained.

Inventors: MURAI KATSUMI, USUI MAKOTO, MURAI, KATSUMI, USUI, MAKOTO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: G06F11
IPC codes: H03M13, G06F7