Time-division multiplex switching network and time switch

Abstract: A time switch comprising a plurality of input highways (521, 522), a plurality of output highways (523, 524), a memory (511) consisting of a plurality of areas respectively assigned to said input highways (521, 522), a plurality of write means (503, 504) for writing data signals on said input highways (521, 522) in said memory (511) in accordance with a first control signal, and a plurality of read means (506, 507) for reading out the data signals from said memory (511) in accordance with a second control signal.

Description: The present invention relates to a time-division multiplex switching network in a time-division broadband exchange, and to a time switch. In a time-division broadband exchanger using signals having frequencies of several hundreds of MHz or higher, signal delays in the wiring pose a problem. In order to solve this problem, an exchanger employing a frame synchronization technique is known. An arrangement of the conventional time-division broadband exchange is described in US-A-4 894 821. In the conventional time-division broadband exchange, in order to solve the problem of signal delays in the wiring, a frame synchronization signal generator adds a frame synchronization signal to data signals on an input highway. The exchange is constituted by a plurality of input highways, a plurality of output highways, a space switch arranged between the input highways and the output highways for, performing signal exchange between the input and output highways, the frame synchronization signal generators for providing the corresponding input highways with the frame synchronization signals, respectively, a plurality of multiplexers connected in series with each of the input highways for multiplexing the data signals and the frame synchronization signal, respectively, a plurality of demultiplexers connected in series with each of the output highways for demultiplexing signals on the output highways, respectively, a control memory for controlling the space switch, and a plurality of phase difference detectors arranged at the input terminal of the space switch. The phase difference detector controls an output frame phase of the frame synchronization signal generator so that the frame phase of each input highway is aligned with the reference phase of the space switch. In this manner, the entire switching network can be synchronously operated while compensating for signal delays. However, since this exchange is constituted by the multiplexers, demultiplexers and the space switch, exchange of the data signals multiplexed on the highways on the time base cannot be performed. Therefore, when multiple stages of exchanges are to be connected, the blocking probability of the space switches is increased. Thus, it is difficult to constitute a large-capacity exchange. US-A-4 470 139 discloses a switching network for use in a time division multiplex system for switching digital signals carried in time slots on N incoming busses to time slots on M outgoing busses. The switching network comprises a plurality of storage means being divided into N first groupings of M storage means each, each said first grouping being responsive to a respective incoming bus, and each outgoing bus being responsive to a respective one of M second groupings of said storage means. Each said second grouping comprises N storage means, one from each of said first groupings. EP-A-0 224 311 describes a switching system which requires a plurality of data memories. Each data memory stores the data words of all input lines. It is an object of the present invention to provide a time-division multiplex switching network which can eliminate the conventional drawbacks and can constitute a large-capacity exchange which serves as both a time switch and a space switch while automatically absorbing signal delays in the wiring. It is another object of the present invention to provide a time switch which can eliminate the conventional drawbacks and minimize memory size. The above objects are achieved by the time switch according to the claims. A time switch according to the present invention comprises: a plurality of input highways, each of said highway having time slots; a plurality of output highways, each of said highway having time slots; a single memory consisting of a plurality of areas, each area comprising a plurality of memory cells for storing the data coming from one of time slots of said input highways; a plurality of write means for simultaneously writing data signals on said time slots of said input highways in said single memory in a parallel fashion in accordance with a first control signal by keeping one data to one memory cell relationship; and a plurality of read means for reading out the data signals from said memory in accordance with a second control signal. An embodiment of the present invention will be described hereinafter with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing an arrangement of a matrix switch; Fig. 2 is a block diagram showing switching network; Fig. 3 is a block diagram showing an equivalent circuit of a switching network shown in Fig. 2; Fig. 4 is a block diagram showing another switching network Fig. 5 is a block diagram showing an equivalent circuit of a switching network shown in Fig. 4; and Fig. 6 is a block diagram showing an embodiment of a time switch according to the present invention. The embodiment shown in Fig. 1 exemplifies a basic switch consisting of two input highways and two output highways. In Fig. 1, time switches 120, 130, 140, and 150 are arranged at four cross points between input highways 105 and 115 and output highways 181 and 191. The internal circuits of the time switches 140 and 150 are omitted from Fig. 1. Four signals, i.e., three data signals and one frame synchronization signal are multiplexed on each of the input highways 105 and 115 and the output highways 181 and 191. The arrangement will be described below. A multiplexer 100 multiplexes a frame synchronization signal F I output from a frame synchronization signal generator 101 and data signals input at input terminals 102, 103, and 104 under the control of the output from a counter 106, and outputs the multiplexed signal onto the input highway 105. A multiplexer 110 multiplexes a frame synchronization signal F I output from a frame synchronization signal generator 111 and data signals input at input terminals 112, 113, and 114 under the control of the output from a counter 116, and outputs the multiplexed signal onto the input highway 115. In each of the input highways 105 and 115, the frame synchronization signal F I is assigned to a first time slot. The input highway 105 is connected to the input terminals of the time switches 120 and 140, and the input highway 115 is connected to the input terminals of the time switches 130 and 150. The output terminals of the time switches 120 and 130 are connected to the output highway 181, and the output terminals of the time switches 140 and 150 are connected to the output highway 191. One end of the output highway 181 is connected to a frame synchronization signal generator 180 for generating a frame synchronization signal F O , and the other end thereof is connected to input terminals of a frame synchronization circuit 165 and a demultiplexer 160. The frame synchronization circuit 165 detects the frame synchronization signal F O on the output highway 181, and resets a counter 166. The demultiplexer 160 demultiplexes an input signal under the control of the output signal from the counter 166, and outputs the frame synchronization signal F O from an output terminal 161 and data signals from output terminals 162, 163, and 164. One end of the output highway 191 is connected to the output terminal of a frame synchronization signal generator 190 for outputting the frame synchronization signal F O , and the other end thereof is connected to the input terminals of a frame synchronization circuit 175 and a demultiplexer 170. The output terminal of the frame synchronization circuit 175 is connected to the input terminal of a counter 176. The frame synchronization circuit 175 detects the frame synchronization signal F O on the output highway 191, and resets the counter 176. The demultiplexer 170 demultiplexes an input signal under the control of the output signal from the counter 176, and outputs the frame synchronization signal from an output terminal 171 and data signals from output terminals 172, 173, and 174. Inside the time switch 120, the input terminal thereof is connected to a write data terminal WD of a data memory 123 and the input terminal of a frame synchronization circuit 121. The output terminal of the time switch 120 connected to the output highway 181 is connected to a read data terminal RD of the data memory 123 and the input terminal of a frame synchronization circuit 122. The output terminal of the frame synchronization circuit 121 is connected to a reset terminal WR of a counter 124. The frame synchronization circuit 121 detects the frame synchronization signal F I on the input highway 105, and resets the counter 124. The output terminal of the counter 124 is connected to a write address input terminal WA of the data memory 123. The output terminal of the frame synchronization circuit 122 is connected to a reset terminal RR of a counter 126. The frame synchronization circuit 122 detects the frame synchronization signal F O from the output highway 181, and resets the counter 126. The output terminal of the counter 126 is connected to an address terminal of a control memory 125. The output terminal of the control memory 125 is connected to a read address terminal RA of the data memory 123. Frame synchronization circuits 131 and 132, a data memory 133, and counters 134 and 136 of the time switch 130 have the same arrangements and functions as those of the frame synchronization circuits 121 and 122, the data memory 123, and the counters 124 and 126 of the time switch 120, and the connections thereamong are the same as those in the time switch 120. The time switch 140 is the same as the time switch 120, and the time switch 150 is the same as the time switch 130. An operation of the matrix switch shown in Fig. 1 when the input terminal 103 is connected to the output terminal 164 will be described hereinafter. The frame synchronization signal generators 101 and 111 output the frame synchronization signal F I . The multiplexer 100 multiplexes the frame synchronization signal F I in a time slot 1 of the input highway 105 and a data signal A in a time slot 3 thereof in accordance with the output from the counter 106. The multiplexer 110 multiplexes the frame synchronization signal F I in a time slot 1 of the input highway 115 in accordance with the output from the counter 116. The frame synchronization circuit 121 of the time switch 120 resets the counter 124 at the time slot position of the frame synchronization signal F I multiplexed on the highway 105. Thus, since the frame phase of the input highway 105 input to the data memory 123 is aligned with the frame phase of the write address WA, the counter 124 outputs "3" using a time slot 3, and the data signal A is written at an address #3 of the data memory 123. Similarly, the data signal A is written at an address #3 of the time switch 140. A control system (not shown in Fig. 1) writes, in advance, data "3" at an address #4 of the control memory 125 of the time switch 120 and a read inhibition code X at an address #1 thereof, and writes the read inhibition code X at addresses #1 and #4 of a control memory 135 of the time switch 130. The frame synchronization signal generators 180 and 190 respectively output frame synchronization signals F O to the output highways 181 and 191 for every frame. The frame synchronization circuit 122 of the time switch 120 detects the frame phase on the output highway 181 in accordance with the frame synchronization signal F O , and resets the counter 126 in the time slot in which the frame synchronization signal F O is multiplexed. Thus, the frame phase of a control signal input to the data memory 123 is aligned with the frame phase of the output highway 181. Thus, the control memory 125 outputs the data "3" stored at the address #4 to the read address input RA of the data memory 123 at a time slot 4 of the output highway 181. The data memory 123 outputs the data signal A onto the output highway 181. Since the control memory 125 inhibits read access of the data memory 123 at the time slot 1, the frame synchronization signal F O multiplexed on the output highway 181 will not collide with the data signals. The frame synchronization circuit 132 of the time switch 130 detects the frame phase on the output highway 181 in accordance with the frame synchronization signal F O , and resets the counter 136 at the time slot 1. Thus, the frame phase of a control signal input to the data memory 133 is aligned with the frame phase of the output highway 181. since the control memory 135 inhibits read access of the data memory 133 at the timeslots 1 and 4, the frame synchronization signal F O and the data signal A multiplexed on the output highway 181 will not collide with other data signals. The frame synchronization circuit 165 detects the frame phase on the output highway 181 using the frame synchronization signal F O , and resets the counter 166 at the time slot in which the frame synchronization signal F O is multiplexed. Thus, the phase of the control signal input to the demultiplexer 160 is aligned with the frame phase of the output highway 181. The demultiplexer 160 outputs the data signal A multiplexed in the time slot of the output highway 181 to the output terminal 164. Since the data signal A is also written at an address #3 of a data memory of the time switch 140, the data signal A can be output to the output terminals 171 to 174 of the demultiplexer 170. That is, the basic switch shown in Fig. 1 serves as a 6 x 6 matrix switch. As described above, according to this example, the frame synchronization signals F I are provided to the time-division multiplexed signals on the input highways 105 and 115, the frame phases of the input highways 105 and 115 of the time switches 120 and 130 are detected, and the counters 124 and 134 are reset in synchronism with the phases of the input highways 105 and 115. The frame phases of the input highways 105 and 115 of the data memories 123 and 133 are aligned with that of the write address WA. Thus, the data signals can be written at correct addresses regardless of the signal delays due to the input highways 105 and 115. The frame synchronization signals F O are provided to the data signals on the output highways 181 and 191, the frame phase of the output highway 181 connected to the time switches 120 and 130 is detected, and the counters 126 and 136 are reset in synchronism with the phase of the output highway 181. The frame phases of the control signals input to the data memories 123 and 133 are aligned with that of the output highway 181. Thus, the data signals can be output to the correct time slots regardless of the signal delays in the output highways 181 and 191. The data memories 123 and 133 are operated not only simply as phase conversion switches but also as elastic storages between the input and output highways. Thus, the data signals can be time-division exchanged between a plurality of highways regardless of the frame phase difference between the input and output highways. In the description of this example , the data memories are subjected to sequential write access and random read access. However, the data memories may be subjected to random write access and sequential read access to constitute the switching network. Fig. 2 shows another switching network. The same reference numerals in Fig. 2 denote the same parts as in Fig. 1. In Fig. 2, basic switches 201, 202, 203, and 204 have the same arrangement, and are arranged in a matrix. Each of the basic switches 201 to 204 has two input highways and two output highways, and time switches 120, 130, 140, and 150 having the same arrangements as those in Fig. 1 are connected at the cross points between the input and output highways in the same manner as in Fig. 1. One end of each output highway of each of the basic switches 201 to 204 receives a frame synchronization signal S 'from a corresponding one of frame synchronization signal generators 214, 215, 216, 217, 218, 219, 220, and 221. The two input highways of each of the basic switches 201 and 203 are connected to the output terminals of corresponding multiplexers 226, 227, 228, and 229 each of which multiplexes one frame synchronization signal S and three data signals. The other end of each output highway of the basic switches 201 and 203 is connected to a corresponding one of the input highways of the basic switches 202 and 204 in one-to-one correspondence. The two output highways of each of the basic switches 202 and 204 are connected to the input terminals of corresponding demultiplexers 230, 231, 232, and 233. Each of the demultiplexers 230 to 233 outputs one frame synchronization signal S and three data signals. With the above connections, a two-stage link time-division switching network can be constituted. A case will be described below wherein a data signal A applied to an input terminal 236 is output to an output terminal 258 in the switching network shown in Fig. 2. A frame synchronization signal generator 210 periodically generates the frame synchronization signal S. The multiplexer 226 outputs the frame synchronization signal S onto a highway 1001, and multiplexes the data signal A applied to the input terminal 236 in a time slot 2. Frame synchronization signal generators 214 and 215 periodically output frame synchronization signals S onto output highways 1003 and 1004, respectively. Time switches 120 and 140 store the data signal A on the input highway 1001 at addresses #2 of their data memories. The time switch 140 outputs the data signal A to a time slot 1 on the output highway 1003. In this manner, the time-division multiplexed signal output from the highway 1003 of the basic switch 201 is applied to an input highway 1031 of the basic switch 204. Time switches 120 and 140 of the basic switch 204 store the data signal A multiplexed in the time slot 1 of the input highway 1031 at addresses #1 of their data memories. The time switch 120 of the basic switch 204 outputs the data signal A to a time slot 3 on an output highway 1034 in accordance with control data. The demultiplexer 232 demultiplexes the time-division multiplexed signal obtained on the highway 1034, and outputs the data signal A to the output terminal 258. Fig. 3 shows a space-division equivalent switching network of the time-division switching network shown in Fig. 2. The basic switches 201 to 204 shown in Fig. 2 can be respectively represented by 6 x 6 matrix switches 31, 32, 33, and 34. The space-division equivalent switching network shown in Fig. 3 has a structure in which a primary switch consisting of the matrix switches 31 and 32 and a secondary switch consisting of the matrix switches 33 and 34 are triple-link connected. Fig. 4 is a block diagram showing still another embodiment of the present invention. The same reference numerals in Fig. 4 denote the same parts as in Fig. 2. In this embodiment, in order to increase a switching capacity of the time-division switching network, a junction time-division switching network is constituted using the 2-stage link time-divion switching network in the embodiment of Figs. 2 and 3 as a basic switch group. More specifically, a primary switch group consisting of basic switch groups 301 and 302 and a secondary switch group consisting of basic switch groups 302 and 304 are junction-connected through highways. Fig. 5 is a space-division equivalent switching network of the time-division switching network shown in Fig. 4. In the space-division equivalent switching network shown in Fig. 5, a primary switch group consisting of basic switch groups 301 and 303 and a secondary switch group consisting of basic switch groups 302 and 304 are connected by a triple-junction connection technique. According to the embodiment of the present invention as described above, a high-speed time-division switching network can be constituted without considering signal delays in the wiring in design. A time-division switching network with a large switching capacity can be constituted without using space switches having a large matrix size. Fig. 6 is a block diagram showing a time switch according to an embodiment of the present invention. The time switch shown in Fig. 6 comprises: a counter 501; a demultiplexer 535 for demultiplexing a control data signal input from an input terminal 531 in accordance with a control signal input from a control terminal 532; a control memory 510 for receiving four outputs #0 to #3 from the demultiplexer 535 and outputting four data; a multiplexer 505 for multiplexing and outputting the four data from the control memory 510 in accordance with the control signal from the counter 501; a demultiplexer 536 for demultiplexing a control data signal input from an input terminal 533 in accordance with a control signal input from a control terminal 534; a control memory 512 for receiving outputs #0 to # 3 from the demultiplexer 536 and outputting four data; a multiplexer 508 for multiplexing and outputting the four data from the control memory 512 in accordance with the output from the counter 501; a demultiplexer 503 for demultiplexing an input signal from an input highway 521 in accordance with the output from the counter 501; a demultiplexer 504 for demultiplexing an input signal from an input highway 522 in accordance with the output from the counter 501; a data memory 511 for receiving the outputs from the demultiplexers 504 and 503 and outputting eight data; a multiplexer 506 for multiplexing the eight data output from the data memory 511 in accordance with the output from the multiplexer 505 and outputting the multiplexed data onto an output highway 523; and a multiplexer 507 for multiplexing the eight data output from the data memory 511 in accordance with the output from the multiplexer 508 and outputting the multiplexed data onto an output highway 524. An operation of the time switch shown in Fig. 6 will be described below with reference to a case wherein data signals A and B multiplexed in time slots 0 on the input highways 521 and 522 are output to a time slot 2 on the output highway 524 and a time slot 1 on the output highway 523. The data signal A multiplexed in the time slot 0 on the input highway 521 is stored at an address #0 of the data memory 511 in accordance with the output from the counter 501. When a control system (not shown) outputs data "0" to the control data input terminal 533 and data "2" to the control terminal 534, the demultiplexer 536 writes data "0" at an address #2 of the control memory 512. When the output from the counter 501 is "2", i.e., when the time slot number on the output highway 524 is "2", the multiplexer 508 outputs data "0" written at the address #2 of the control memory 512. The multiplexer 507 outputs the data signal A written at the address #0 of the data memory 511 onto the output highway 524 in accordance with the data "0" from the multiplexer 508. Similarly, the data signal B multiplexed in the time slot 0 on the input highway 522 is output to a time slot 1 on the output highway 523. As described above, in this embodiment, since the demultiplexers 503 and 504 are provided to the input highways 521 and 522, respectively, the data signals on the input highways 521 and 522 are simultaneously written at different addresses of the data memory 511. Since the multiplexers 506 and 507 are provided to the output highways 523 and 524, respectively, the data signals A and B written in the data memory 511 can be read out onto the output highways 524 and 523, respectively. In this manner, the time switch having a switching capacity twice that of the conventional time switch can be constituted by a memory having the same operation speed as that of the conventional time switch. In this embodiment, the data memory consisting of a plurality of areas assigned to corresponding input highways is used, and sequential write access and random read access are performed. However, a data memory consisting of a plurality of areas assigned to corresponding output highways may be used, so that random write access and sequential read access can be performed to constitute a time switch.

Claims: A time switch comprising: a plurality of input highways (521, 522), each of said highway having time slots; a plurality of output highways (523, 524), each of said highway having time slots; a single memory (511) consisting of a plurality of areas, each area comprising a plurality of memory cells for storing the data coming from one of time slots of said input highways (521, 522) ; a plurality of write means (503, 504) for simultaneously writing data signals on said time slots of said input highways in said single memory (511) in a parallel fashion in accordance with a first control signal by keeping one data to one memory cell relationship; and a plurality of read means (506, 507) for reading out the data signals from said memory (511) in accordance with a second control signal. A time switch according to claim 1, wherein each of said plurality of write means (503, 504) writes the data signal from one of the input highways (521, 522) in one area of said memory (511), and each of said plurality of read means (506, 507) reads out the data signal to a time slot of one of the output highways (523, 524) from any areas of said memory (511) indicated by the second control signal. A time switch according to claim 1, wherein each of said plurality of write means (503, 504) writes the data signal from one of the input highways (521, 522) in any areas of said memory (511) indicated by the first control signal, and each of said plurality of read means (506, 507) reads out the data from one area of said memory (511) to a time slot of said one of the output highways (523, 524).

Inventors: SHIN-ICHIRO HAYANO, SHIN-ICHIRO, HAYANO, SHIN-ICHIRO, HAYANO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H04Q11
IPC codes: H04Q11