Electrically erasable and programmable read only memory using stacked-gate cell

Abstract: An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or same as UV-EPROM. Erasure operating is performed by applying negative voltage to control gate so as to inject hall into the floating gate (4).

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an electrically erasable and programmable read only-memory (EEPROM). Description of the Background Art An EEPROM according to the preamble of claim 1 is known from the document EP-A-0 023 782. For erasing the information as stored in the cells of such a floating gate EEPROM, several techniques are known. The document EP-A-0 108 681 describes a method for selectively erasing single cells. The document EP-A-0 052 566 describes a method for simultaneously erasing a a plurality of memory cells forming a block by using a bipolar voltage generator and by applying erase/write voltages to word lines connected to the control gates of the memory cells. The document EP-A-0 209 812 describes an EEPROM comprising word lines which are connected to the control gates of the memory cells, and which are connected to a word line decoder via a transferring MNOS transistor being formed in a well region of the semiconductor region. SUMMARY OF THE INVENTION It is the object of the present invention to provide an EEPROM having low power consumption in its erasure operation. The EEPROM of the present invention is defined by the features of claim 1. It comprises an especially arranged decoder. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given here below and from the accompanying drawings of the preferred embodiment of the invention. In the drawings: Fig. 1 is a section of a memory cell forming part of the preferred embodiment of an EEPROM according to the present invention; Figs. 2(A) and 2(B) show a negative voltage generator circuit, in which Fig. 2(A) shows the structure of the negative voltage generator circuit and Fig. 2(B) shows a circuit diagram of the equivalent circuit of the device of Fig. 2(A); Fig. 3 is a circuit diagram of a preform of a row decoder employed in the preferred embodiment of an EEPROM; Fig. 4 is a circuit diagram of a comparative example of one of typical constructions of the conventional row decoder; Fig. 5 is a circuit diagram of row decoder as used in the preferred embodiment of an EEPROM; and Fig. 6 is a chart showing waveforms of control signals for erasure. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, the preferred embodiment of an erasable programmable nonvolatile memory device according to the present invention will be described herebelow with reference to Figs. 1 to 3. Fig. 1 shows a cross section of a memory cell forming a part of the preferred embodiment of the erasable programmable nonvolatile memory device. As will be appreciated from Fig. 1, the memory cell in the preferred embodiment of the erasable programmable nonvolatile memory device has a stacked gate structure. Namely, as seen from Fig. 1, an N type source region 2 and an N type drain region 3 are formed on a P type semiconductor substrate 1. A floating gate 4 is formed above a channel between the source region 2 and the drain region 3 and opposes to the channel via a gate insulation layer 5. A control gate 6 is formed above the floating gate 4 in opposition to the latter via a gate insulation layer 7. To the control gate, a control gate voltage V cg is applied. Similarly, to the drain region 3, a drain voltage V d is applied. As will be seen from Fig. 1, the shown structure of the memory cell employed in the preferred embodiment of the erasable programmable nonvolatile memory device according to the present invention is the same as that in an UV-EPROM. In order to write in a program in the memory cell set forth above, a predetermined voltage, e.g.+7 to +12V of drain voltage V d is applied to the drain region 3. Simultaneously, a predetermined voltage, e.g. +12.5V, of the control gate voltage V cg is applied to the control gate 6. By this, an avalanche current is created to flow between the drain region 3, the source region 2 and the semiconductor substrate 1. The avalanche current further generates a substrate current in the semiconductor substrate 1. As a result, hot electrons are injected into the floating gate 4 via a pinch off region formed in the vicinity of the drain region 3. The process of programming set forth above is identical to that in the UV-EPROM. In reading out the written data from the memory cell, a positive voltage is applied the control gate 6. In case that the memory cell has a written data, the floating gate 4 is charged by a negative voltage. Therefore, when the positive voltage is applied to the control gate 6, the memory cell is maintained in non-conductive state due to the presence of the negative voltage in the floating gate 4. On the other hand, when the memory cell has no written data, the channel region between the source region 2 and the drain region 3 is converted into N type by the positive voltage applied to the control gate 6. Thus, the memory cell becomes conductive. Therefore, by applying the positive voltage to the control gate, and discriminating whether the corresponding memory cell is conductive or non-conductive, data can be read out. This process of reading out the written data is also identical to that in the UV-EPROM. In erasure operation of an UV-EPROM, ultraviolent ray is irradaited on the UV-EPROM for exciting the electrons in the floating gate 4 with an energy great enough to move them over the insulating layers 5 and 7; they are then absorbed in the insulating layers 5 and 7. In contrast to this, the erasure in the shown embodiment of the erasable programmable nonvolatile memory device according to the present invention, is performed by applying a predetermined negative voltage, e.g. -3 to -10V, to the control gate 6. Simultaneously, a drain voltage V d equivalent to that applied in writing is applied to the drain region 3. This causes electrical erasure of the written data in the memory cell. Namely, when the negative voltage V cg is applied to the control gate 6, the gated junction breakdown voltage at the PN junction between the drain region 3 and the substrate 1 is lowered so that the PN junction is easily caused to have a breakdown. At this condition, the drain voltage V d equivalent to that applied in writing is applied to cause breakdown in the PN junction below the floating gate 4. At the same time, in the pinch off region, pairs of electrons and holes are generated. Because of the negative voltage of the control gate voltage V cg , the electric field formed in the memory cell is opposite to that generated in the writing operation. As a result, holes in the pinch off region are injected in to floating gate 4 to lower the charge level in the floating gate to zero or approximately zero. As is well known, the gate insulating layer 5 formed by an oxide layer, has high energy barrier properties so as not to allow injection of holes to the floating gate. However, the energy level of the holes generated by breakdown is sufficiently high that holes are injected over the energy barrier of the insulating layer 5. Furthermore, since the amount of holes and electrons, in other words, the number of carriers, generated upon breakdown at the PN junction, is relatively large. Therefore, erasure can be completed at a relatively short period. Practically, the period required for erasure by applying the negative voltage as the control gate voltage V cg is equivalent to the writing in period. As set forth, since the shown embodiment of the stacked gate structure EEPROM performs erasure by applying the negative voltage to the control gate 6 and positive voltage to the drain region 3, by selecting the word line, to which the control gate is connected, and the bit line, to which the drain region is connected, each memory cell can be selectively erased. This means that the shown embodiment of EEPROM allows to selectively erase each bit. In addition, since the floating gate 4 holding written data is charged at the negative charge, the absolute value of the negative control gate voltage V cg required for forming an electric field suitable for injecting holes into the floating gate 4 can be reduced in the magnitude of the negative charge in the floating gate. As set forth, in the shown embodiment of the erasable programmable nonvolatile memory device, i.e. EEPROM, according to the invention, erasure operation is performed by applying the negative voltage for the control gate 6. Of course, it is possible to connect the control gate 6 to an external negative voltage source for erasure operation. However, connecting the control gate to the external negative voltage source requires an additional terminal, thereby increasing the number of pins for interfacing. Therefore, it is advantageous to form a negative voltage generator circuit in the memory device. The preferred construction of a negative voltage generator circuit employed in the shown embodiment of the EEPROM is shown in Figs. 2(A) and 2(B). As shown in Fig. 2(A), the negative voltage generator circuit is formed on the semiconductor substrate 1. An N type semiconductor region 8 is formed on the P type semiconductor substrate. In the N type semiconductor region 8, P channel MOS transistors Tr₂ and Tr₃ are formed. These MOS transistors Tr₂ and Tr₃ are connected in series to each other. One end of the series circuit is connected to ground. The other end of the series circuit is connected to a word line WL. As is well known, the word line WL is connected to control gates 6 of respective memory cell. At the junction between the MOS transistors Tr₂ and Tr₃, one end of a capacitor C₁ is connected. The other end of the capacitor C₁ is connected to a source of pulses varying their levels between 0V to 5V. The transistors Tr₂ and Tr₃ and the capacitor C₁ form a charge pump circuit for transferring negative voltage through the word line WL. In practice, at the leading edge of the HIGH level pulse varying from 0V to 5V, the MOS transistor Tr₃ is turned ON. By this, a level at the junction between the MOS transistors Tr₃ and Tr₂ becomes zero or approximately zero including a level shift for V th . Then, at the trailing edge of the HIGH level pulse varying from 5V to 0V, the MOS transistor Tr₃ is turned OFF and the MOS transistor Tr₂ is turned ON. By this, the source level of the MOS transistor Tr₂ is lowered according to lowering of the pulse level and becomes minus. Assuming the level shift V th of the MOS transistors Tr₂ and Tr₃ is 1V, the negative voltage in a level of -3V to -5V can be generated. If a greater negative voltage is required, a plurality of charge pump circuits may be formed and connected in series. Another N type semiconductor region 9 is formed on the P type semiconductor substrate 1. A transferring P channel MOS transistor Tr₁ is formed in the N type semiconductor region 9. This transferring MOS transistor Tr₁ is provided for avoiding direct connection between the word line WL and the semiconductor substrate 1. Namely, the charge level in the word line WL becomes negative in relation to the charge level of the semiconductor substrate 1. When the charge of the word line WL is directly transferred to the N type semiconductor region 9, the negative voltage for erasure operation causes forward bias at the PN junction between the P type semiconductor substrate 1 and the N type semiconductor region 9 to establish direct connection. The MOS transistor Tr₁ prevents the negative voltage in the word line WL from leaking to the P type semiconductor substrate. Practical application of the negative voltage generator circuit set forth above is shown in Fig. 3. As seen from Fig. 3, the negative voltage generator circuit is coupled with a row decoder. This circuit construction is compared with the row decoder circuit employed in the conventionally known UV-EPROM. As seen from Figs. 3 and 4, the row decoder circuit includes N channel MOS transistors Tr₄, Tr₅, Tr₆ and Tr₇ which receive address signals from a pre-decoder (not shown). The row decoder also has a P channel MOS transistor Tr₈ serving as a load for the N channel transistors Tr₄, Tr₅, Tr₆ and Tr₇. These MOS transistors Tr₄, Tr₅, Tr₆, Tr₇ and Tr₈ form a decoding section. The row decoder circuit further includes a CMOS inverter constituted by an N channel MOS transistor Tr₉ and a P channel MOS transistor Tr₁₀. The CMOS inverter inverts the output signal V N1 of the decoding section. The CMOS inverter is connected to the word line WL via an N channel MOS transistor Tr₁₁ and the transferring P channel MOS transistor Tr₁ for transferring the output of the CMOS inverter therethrough. The N channel MOS transistor Tr₁₁ is designed to be driven by an erasure command Erase . In practical operation, the N channel MOS transistor Tr₁₁ is normally maintained ON state and turned into OFF state in response to the erasure command Erase . The junction between the MOS transistors Tr₁₁ and Tr₁ is connected to the output of the decoding section constituted by the N channel MOS transistors Tr₄, Tr₅, Tr₆ and Tr₇ via an N channel transistor Tr₁₂. The N channel transistor Tr₁₂ is designed to be controlled by the erasure command Erase to be turned ON by the erasure command for inverting the logic of the voltage V N2 . A CMOS inverter for inverting the voltage V WL on the word line WL is formed by a P channel MOS transistor Tr₁₄ and an N channel MOS transistor Tr₁₅. The output of this CMOS inverter is applied to a gate of a P channel MOS transistor Tr₁₃ disposed between a V PP /V CC terminal and the word line WL. The circuit constituted by the MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅ is designed for selectively applying V PP to the word line WL during programming and V CC during reading out. The charge pump circuit including the P channel MOS transistors Tr₂ and Tr₃ and the capacitor C₁ is connected to ground via an N channel MOS transistor Tr₁₆. The N channel MOS transistor Tr₁₆ is controlled by the erasure command Erase . The capacitor C₁ is also connected to a NOR gate NOR₁ which receives an erasure pulse at one input terminal and the word line voltage V WL of the word line WL. The following table shows the voltage levels at respective nodes in various operation modes. READ WRITE ERASE S N S N S N V PP /V CC 5V 5V V PP V PP 5V 5V V N1 0V 5V 0V 5V 0V 5V V N2 5V 0V V PP OV 0V 5V V WL 5V V thp V PP V thp - 5V SOURCE (CELL) 0V 0V OV OV F1 F1 ERASE 0V 0V 0V 0V 5V 5V It should be noted that, in the table above, S represents selected and N represents not selected. V PP /V CC represents V PP /V CC terminal in the row decoding system, for example V PP is +12.5V and V CC is 5V. Source is a source of cell array. V thp is a threshold voltage of the P channel MOS transistor Tr₁, - represents a negative voltage, F1 is a floating state. It should be noted, F1 can be replaced by 5V. In the circuit construction of Fig. 3, the row decoder circuit operates as follows. In response to an erasure command, the MOS transistor Tr₁₁ is turned OFF and the MOS transistor Tr₁₂ is turned ON, which state of the transistors is alternative to that in the normal state. Therefore, the logic is reversed. Therefore, the voltage V N2 becomes 0V when selected and +5V when not selected. This causes the word line voltage V WL on the word line WL to be negative. Fig. 6 shows a modification of the row decoder circuit of Fig. 3, which is applicable for the preferred embodiment of the erasable programmable nonvolatile memory device according to the invention. The shown modification improves the performance of the row decoder circuit of Fig. 3. Namely, in the row decoder of Fig. 3, when one word line WL is not selected, the voltage level in the non-selected word line becomes not zero because of voltage shifted by the threshold voltage V thp of the transferring MOS transistor Tr₁. This causes leak current in the non-selected blank memory cell in writing and reading. Furthermore, in erasure operation, since the word line voltage becomes 5V, the non-selected blank memory cell is apt to be turned ON. For avoiding this, the source is made open or floating. Or, in the alternative, the voltage level at the source has to be risen to +5V (+V CC ). In addition, during erasure operation, in the former embodiment, current tends to flow through the non-selected word line and the charge pump circuit to the ground. This increases power consumption for erasure operation. The row decoder of Fig. 5 is designed to latch word lines by recognizing selected word lines and non-selected word lines before performing erasure operation. In the erasure operation, the charge in respective word lines WL is initially discharged to set at 0V. Thereafter, the negative voltage for erasure is applied for the selected word lines WL. Fig. 6 shows the wave forms of control signals E₁, E₂ and E₃ used in this modification. The signal levels of these control signals E₁, E₂ and E₃ during writing and reading are maintained at 0V. In this modification, it is not required to reverse the logic in the word lines WL between write/read mode operation and erasure mode operation. In the shown circuit construction, the MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅ basically operate to adjust the word line voltage V WL to V PP during programming operation and to V CC during reading operation. In the shown embodiment, these MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅ serve for latching signals on the word lines to store information of selected word lines and non-selected word lines. Namely, when the control signal E₁ turns into HIGH level, the MOS transistor Tr₁₈ is turned OFF. At this, the signals on respective word lines WL are latched by the MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅. With a certain delay of the leading edge of the HIGH level control signal E₁, the HIGH level control signal E₂ rises. In response to rising of the HIGH level control signal E₂, the MOS transistor Tr₁₁ is turned OFF. Simultaneously, the MOS transistor Tr₁₇ is turned ON to allow the charge in a respective word line WL to be discharged. By this the voltage level at a respective word line WL is set at 0V. Thereafter, the HIGH level control signal E₃ rises to turn the transferring MOS transistor Tr₁ OFF. At this condition, according to the output of the circuit of the MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅, the charge pump circuit is selectively operated according to the charge pulse ø generated by the circuit of the MOS transistors Tr₁₃, Tr₁₄ and Tr₁₅ to feed a negative voltage for the selected word lines. It should be appreciated that, in the modification shown in Fig. 6, the threshold voltage level V th of the transferring MOS transistor Tr₁ is also set at 0 ± 0.2V Here, in erasure of the erasable programmable nonvolatile memory device, such as EEPROM by injecting holes into the floating gate, it is essential to avoid that holes are excessively injected into the floating gate. Otherwise, a cell current will flow in the control gate even when the voltage at the non-selected word line is controlled at 0V. This can be avoided by fabricating the control gate as proposed in ISSCC Digest, page 76 to page 77, 1987. However, this may prevent the integration from being satisfactorily high. Therefore, in the preferred embodiment, erasure operation is performed by adjusting V CC at approximately 4V for 10 to 100 microseconds. Subsequently a blank check is performed. Erasure and blank check operations are repeated for several cycles. When a sufficient blank condition cannot be obtained after given cycles of erasure and blank check operation, the V CC level is slightly risen. Since the absolute value of the negative voltage is proportional to the source power V CC , the negative voltage can be controlled by adjusting V CC . Such process is effective for avoiding creation of excessive holes. In addition, writing operation is performed by writing utilizing a 0.1 to 1 miliseconds width write pulse and subsequently perform verification, and repeating writing and verifying for several cycles. As set forth, the shown embodiment of the erasable programmable nonvolatile memory device according to the present invention is enabled to electrically erase the written data. Therefore, even when the EEPROM is fabricated on the plastic package, write test can be performed after assembling. This clearly improves liability of the products. Furthermore, since as illustrated hereabove, the construction of each memory cell is identical to that one of a UV-EPROM, high integration can be obtained for allowing the memory device to be compact comparable with the UV-EPROM. While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modifications to the shown embodiments which can be embodied within the scope of the appended claims.

Claims: An EEPROM comprising: a plurality of memory cells each one including: -- a semiconductor region (1); -- a source region (2) and a drain region (3) formed in said semiconductor region; -- a channel region formed between said source and drain regions; -- a floating gate (4) formed above said channel region; -- a first insulating layer (5) disposed between said channel region and said floating gate; -- a control gate (6) formed above said floating gate; and -- a second insulating layer (7) disposed between said floating gate and said control gate; and voltage applying means for applying a positive voltage to said control gate (6) for injecting electrons into said floating gate (4) for writing, and for applying a negative voltage to said control gate (6) for injecting holes into said floating gate (4) for erasure; characterized in that said voltage applying means is connected to said control gates (6) of said memory cells via word lines which are connected to a word line decoder (Fig. 5) via a transferring MOS transistor means (Tr₁₃, Tr₁₄, Tr₁₅) being formed in a well region of said semiconductor region (1); and said word line decoder is arranged to perform the following steps in an erasure operation: -- the state of each word line, i. e. the state "selected" or the state "unselected", is latched before the erasure operation; -- then the word lines are separated from the decoder and discharged; and -- the erasure voltage is applied only to the word lines for which the state "selected" has been latched. An EEPROM as set forth in claim 1, wherein said voltage applying means comprises a negative voltage source means fabricated in a package common with said memory cells.

Inventors: ARAKAWA HIDEKI, ARAKAWA, HIDEKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: G11C16
IPC codes: H01L21, G11C16, H01L29, H01L27, G11C17