Processing system for branch instruction

Abstract: A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.

Description: BACKGROUND OF THE INVENTION The invention relates to a processing system for a branch instruction in data processing. Data processing systems for the handling of branch instructions are known from US 3,490,005, EP-A-0 198 214, and from the "Proceedings of the 1982 International Conference on Parallel Processing" 24.08.1994 in the article by M.F.Grohoski and J.H.Patel starting page 248-252. The data processing system as disclosed in US-A-3,490,005 has parallel execution units and an instruction unit containing instruction buffer registers. When an instruction loop is containable within these registers, the system automatically operates in a loop mode whereby the instruction loop is repetitively decoded and executed, without refetching any instructions from storage, until the condition creating the loop is no longer satisfied. EP-A-0 198 214 discloses a signal processor utilizing a three-phase instruction pipeline. That is, at any given time, one instruction is being fetched from an instruction store while the previously fetched instruction is being decoded for execution and the previously decoded instruction is being executed. All instructions, except the Branch instructions, require three machine clock cycles to fetch, decode and execute, although the execution rate is one instruction per machine cycle. An instruction being fetched is not visible to the control logic of the machine. An instruction first becomes visible only after it is placed in an Instruction Decode Register at the end of the fetch cycle. Each instruction fetched from a program store is first placed in the Instruction Decode Register; a new instruction is loaded into the Instruction Decode Register on each clock time. Instructions in the Instruction Decode Register are examined and decoded in a decoder logic during the machine cycle that follows and the results are loaded into an Execute Register at the next clock time. Branches also require one machine cycle for instruction fetch and are decoded during the second machine cycle, but an Instruction Address Register is loaded with the branch-to address, assuming the branch is taken, at the end of the second cycle. The above-referenced article by M.F. Grohoski and J.H. Patel presents two models of an instruction execution pipeline incorporating an instruction prefetching strategy. One model ignores operand accessing and thus models a computer system with separate program and data memories. The second model accounts for operand accessing. With an analytical model described in this article, except for jump instructions, all decoded instructions enter an execution pipeline, where several units are required to complete execution. If the decoded instruction is an unconditional branch the instruction word at the target of the jump is requested immediately by a decoder, and decoding ceases until the target instruction returns from the memory. The pipeline will see the full memory latency time, since there was no opportunity for target prefetching. SUMMARY OF THE INVENTION It is an object of the invention to provide a high-speed processing system for a branch instruction. This object is satisfied by the processing system set forth in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a processing system for a branch instruction according to a first embodiment of this invention. Fig. 2 is a timing diagram of operation of the processing system of Fig. 1. Fig. 3 is a block diagram of a processing system for a branch instruction according to a second embodiment of this invention. Fig. 4 is a timing diagram of operation of the processing system of Fig. 3 in the case where a branch is taken. Fig. 5 is a timing diagram of operation of the processing system of Fig. 3 in the case where a branch is not taken. Fig. 6 is a block diagram of the instruction decoder of Fig. 1. Fig. 7 is a flowchart of operation of the instruction decoder of Figs. 1 and 6. Fig. 8 is a flowchart of operation of the instruction decoder of Fig. 3. DESCRIPTION OF THE FIRST PREFERRED EMBODIMENT With reference to Fig. 1, a processing system for a branch instruction includes a cache 1 holding instructions which can be read out at a high speed. In Fig. 1, an unconditional branch instruction flows along arrows composed of broken lines. An instruction pre-fetch counter 2 outputs an address to the cache 1 to precedently fetch a corresponding instruction from the cache 1 to a FIFO (First-In First-Out) type instruction buffer 3. The instruction buffer 3 has four stages. It should be noted that the instruction buffer 3 may have only one stage or the number of stages of the instruction buffer 3 may differ from four. In general, the address outputted from the pre-fetch counter 2 is periodically updated so that instructions are sequentially transferred from the cache 1 to the instruction buffer 3. During the address updating process, the instruction pre-fetch counter 2 counts up the address by a value corresponding to the number of bytes of the related instruction. The instruction buffer 3 sequentially receives instructions from the cache 1 and queues the instructions. An instruction decoder 4 sequentially receives instructions from the instruction buffer 3 and decodes the instructions, thereby deriving commands from the decoded instructions. As will be made clear hereinafter, the instruction decoder 4 has several control functions. It should be noted that lines of transmission of control signals from the instruction decoder 4 to other elements are omitted from Fig. 1. A FIFO type execution command buffer 5 queues commands outputted from the instruction decoder 4. The execution command buffer 5 has two stages. It should be noted that the execution command buffer 5 may have only one stage or the number of stages of the execution command buffer 5 may differ from two. An execution unit 6 sequentially receives commands from the execution command buffer 5 and executes the commands. An instruction decoding counter 7 generates an address corresponding to an instruction to be subsequently processed in the instruction decoder 4. The address generated by the instruction decoding counter 7 is periodically updated. During the address updating process, the instruction decoding counter 7 counts up the address by a value corresponding to the number of bytes of the related instruction. A FIFO type program counter buffer 8 queues addresses which are sequentially outputted from the instruction decoding counter 7. The program counter buffer 8 has four stages. It should be noted that the program counter buffer 8 may have only one stage or the number of stages of the program counter buffer 8 may differ from 4. In general, addresses stored in the program counter buffer 8 correspond to instructions which are being subjected to a decoding process, a process or information in a first stage of the execution command buffer 5, a process or information in a second stage of the execution command buffer 5, and an execution process respectively. An adder 9 is controlled by the instruction decoder 4 in response to a branch instruction. Specifically, the adder 9 adds an address outputted from the instruction decoding counter 7 and a displacement supplied from the instruction buffer 3, and thereby generates a new address corresponding to an instruction which is located at a downstream end or destination of a branch related to the branch instruction. The instruction which is located at the destination of the branch is called a branch destination instruction. The execution of commands by the execution unit 6 should jump from the branch instruction to the branch destination instruction while skipping instructions located between the branch instruction and the branch destination instruction. It should be noted that, in this embodiment, the branch instruction is prevented from entering the execution unit 6 and from being processed by the execution unit 6. The branch destination address is transferred to the counters 2 and 7. In cases where a branch is absent from a series of instructions, the processing system of Fig. 1 operates as follows. An instruction is fetched from the cache 1 in accordance with an address generated by the instruction pre-fetch counter 2 and is stored into the instruction buffer 3. This is called an instruction pre-fetch process. The instruction pre-fetch counter 2 updates the present address and specifically generates a new address by counting up the present address by a value corresponding to the number of bytes of the instruction just transferred to the instruction buffer 3. The instruction pre-fetch counter 2 holds the new address until it is updated. Such processes are periodically reiterated so that instructions are sequentially transferred from the cache 1 to the instruction buffer 3. The instruction decoder 4 fetches an instruction from a bottom of the instruction buffer 3 and decodes the fetched instruction. The instruction decoder 4 derives an execution command or commands from the fetched instruction and transfers the derived command or commands to the execution command buffer 5. When the command or commands are transferred to the execution command buffer 5, the instruction decoding counter 7 counts up the address by a value corresponding to the number of bytes of the decoded instruction and thereby generates a new address corresponding to an instruction to be decoded subsequently. While the instruction decoder 4 is processing an end word of an instruction, a header address of an instruction to be decoded subsequently is set in the instruction decoding counter 7. Such processes are periodically reiterated so that instructions are sequentially transferred from the instruction buffer 3 to the instruction decoder 4 and are sequentially decoded therein. In addition, execution commands are sequentially transferred from the instruction decoder 4 to the execution command buffer 5. Each time the decoding of one instruction is completed, the instruction decoder 4 allows a header address of a subsequent instruction to be transferred from the instruction decoding counter 7 to the program counter buffer 8. The execution unit 6 fetches a command or commands from a bottom of the execution command buffer 5 and executes the fetched command or commands. Such processes are periodically reiterated so that commands are sequentially transferred from the execution command buffer 5 to the execution unit 6 and are sequentially executed thereby. An address held in a bottom of the program counter buffer 8 corresponds to an instruction having a command which is currently executed by the execution unit 6. Each time the execution of a command or commands of one instruction is completed, the address in the bottom of the program counter buffer 8 is discarded and is replaced with a new address. Operation of the processing system of Fig. 1 on a series of instructions including a branch instruction will be described hereinafter with reference to Fig. 2. During a first cycle C0, a first instruction A0 is fetched from the cache 1 in accordance with an address generated by the instruction pre-fetch counter 2 and is stored into a bottom of the instruction buffer 3. This is called an instruction pre-fetch process. The instruction pre-fetch counter 2 updates the address and specifically generates a new address by counting up the present address by a value corresponding to the number of bytes of the instruction A0. The instruction pre-fetch counter 2 holds the new address until it is updated. It is now assumed that the new address corresponds to an unconditional branch instruction BRA. During a cycle C1 following the cycle C0, the branch instruction BRA is transferred from the cache 1 to the instruction buffer 3 in the pre-fetch process while the instruction decoder 4 fetches the instruction A0 from the instruction buffer 3. The instruction A0 is decoded by the instruction decoder 4 so that a command or commands are derived from the instruction A0. The command or commands related to the instruction A0 are transferred to the execution command buffer 5. Simultaneously, the instruction decoding counter 7 generates an address corresponding to an instruction to be decoded subsequently and holds the generated address. During a cycle C2 following the cycle C1, an instruction A1 subsequent to the branch instruction BRA is transferred from the cache 1 to the instruction buffer 3 in the pre-fetch process while the instruction decoder 4 fetches the branch instruction BRA from the instruction buffer 3. The branch instruction BRA is decoded by the instruction decoder 4. The branch instruction BRA generates a command related to address calculation but does not generate any command to the execution unit 6. During the cycle C2, the command or commands related to the instruction A0 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction A0 are determined. Furthermore, the pre-fetch process is interrupted. During a cycle C3 following the cycle C2, an instruction A2 subsequent to the instruction A1 is transferred from the cache 1 to the instruction buffer 3 in the pre-fetch process while the instruction decoder 4 fetches the instruction A1 from the instruction buffer 3. The instruction A1 is decoded by the instruction decoder 4. During the cycle C3, the branch instruction BRA is subjected to effective address calculation in which an address of an instruction B0 located at a downstream end or destination of this branch is determined. Specifically, the instruction decoder 4 activates the adder 9. The adder 9 adds the address of the branch instruction BRA and a displacement attached to the branch instruction BRA and thereby generates a new address corresponding to the branch destination instruction B0. The adder 9 receives the branch instruction address and the displacement from the instruction decoding counter 7 and the instruction buffer 3 respectively. The instruction decoder 4 interrupts the normal counting-up operations of the counters 2 and 7, and transfers the address of the branch destination instruction B0 from the adder 9 to the counters 2 and 7. Accordingly, the address of the branch destination instruction B0 is set in the counters 2 and 7. During the cycle C3, the execution unit 6 fetches the command or commands of the instruction A0 from the execution command buffer 5 and executes the fetched command or commands. During a cycle C4 following the cycle C3, the instruction decoder 4 allows the pre-fetch counter 2 to output the address of the branch destination instruction B0 to the cache 1 so that the branch destination instruction B0 is transferred from the cache 1 to the instruction buffer 3 in the pre-fetch process. The instruction decoder 4 initializes the instruction buffer 3 before the branch destination instruction B0 is stored into the instruction buffer 3. During the cycle C4, the instruction decoder 4 fetches the instruction A2 from the instruction buffer 3 and then decodes the instruction A2. The instruction decoder 4 disables the instruction A2 which is being decoded. In addition, the instruction decoder 4 disables the instruction A1 which was decoded. Specifically, the instruction A1 in the effective address calculation stage is disabled while the command or commands related to the instruction A1 and stored in the execution command buffer 5 are cancelled. The instruction decoder 4 allows the instruction decoding counter 7 to output the header address of the branch destination instruction B0 to the program counter buffer 8. In the program counter buffer 8, the header address of the branch destination instruction B0 is written over the address of the branch instruction BRA. As understood from the previous description, the branch destination instruction B0 immediately follows the instruction A2 in the pre-fetch process so that an instruction or instructions located between the instructions A2 and B0 are prevented from undergoing the pre-fetch process. In this way, an unnecessary waste of the pre-fetch process is decreased. During a cycle C5 following the cycle C4, the instruction decoder 4 fetches the branch destination instruction B0 from the instruction buffer 3 and decodes the branch destination instruction B0. The instruction decoder 4 derives a command or commands from the branch destination instruction B0 and transfers the derived command or commands to the execution command buffer 5. During a cycle C6 following the cycle C5, the command or commands related to the branch destination instruction B0 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction B0 are determined. During a cycle C7 following the cycle C6, the execution unit 6 fetches the command or commands of the branch destination instruction B0 from the execution command buffer 5 and then executes the fetched command or commands. An address held in the bottom of the program counter buffer 8 corresponds to an instruction having a command or commands which are currently executed by the execution unit 6. Each time the execution of the command or commands related to one instruction is completed, the address in the bottom of the program counter buffer 8 is discarded and is replaced with a new address. As described previously, after the instruction decoder 4 decodes the branch instruction BRA and then performs effective address calculation related to the branch instruction BRA, the instruction decoder 4 enables the fetch of the branch destination instruction B0 without waiting the end of the execution of the command or commands of the instruction A0. Accordingly, the branch destination instruction B0 is promptly prepared. After the execution of the command or commands of the instruction A0 is completed, the command or commands of the branch destination instruction B0 start to be executed. The instruction decoder 4 disables the instruction A1 which was decoded and also disables the instruction A2 which is being decoded. As understood from the previous description, in the case where a branch instruction BRA is present, the branch instruction BRA is completely processed within the instruction decoder 4 and is prevented from reaching the execution unit 6. The instruction decoder 4 enables the calculation of the address of a branch destination instruction B0 in independently parallel with the execution of commands of a preceding instruction by the execution unit 6. In addition, the instruction decoder 4 enables the high-speed preparation of the branch destination instruction B0 in independently parallel with the execution of commands of the preceding instruction by the execution unit 6. Furthermore, the instruction decoder 4 performs the decoding of the branch destination instruction B0 in independently parallel with the execution of commands of the preceding instruction by the execution unit 6. In the case where four or more execution cycles are necessary to complete the execution of the command or commands related to the instruction A0, the branch instruction BRA outwardly corresponds to "0" cycle and thus there is no overhead due to the branch. Accordingly, the branch instruction BRA, the branch destination instruction B0, and the subsequent instructions are processed at high speeds. This embodiment will be further described with reference to Figs. 6 and 7. As shown in Fig. 6, the instruction decoder 4 includes a combination of an instruction analyzing section 4A, a command generating section 4B, and a decoding control section 4C. The instruction analyzing section 4A is preferably composed of a programmable logic array, and analyzes instructions inputted into the instruction decoder 4. The command generating section 4B is preferably composed of a read-only memory (ROM). The decoding control section 4C outputs control signals to the command generating section 4B in accordance with results of analyzation of instructions which are supplied from the instruction analyzing section 4A. In the case of an instruction other than a branch instruction, the command generating section 4B derives a command or commands from a signal outputted by the instruction analyzing section 4A which corresponds to the instruction. In this case, the derived command or commands are outputted to the execution command buffer 5. In the case of a branch instruction, the command generating section 4B produces various commands in response to the control signals from the decoding control section 4C. In this case, the commands are outputted to the elements executing the instruction pre-fetch process, and the elements executing the effective address calculation. The decoding control section 4C is preferably composed of a combination of discrete logic components. The decoding control section 4C may be composed of a sequencer, a controller, or a simple processor. The decoding control section 4C includes a sub section 4D for the control of the branch processing. Fig. 7 shows a control sequence executed by the branch processing control section 4D. As shown in Fig. 7, a first block 61 of the control sequence determines whether or not a currently-inputted instruction is a branch instruction BRA. When the currently-inputted instruction is not the branch instruction BRA, the control sequence advances to steps of normal processing. When the currently-inputted instruction is the branch instruction BRA, the control sequence advances to a block 62. The block 62 allows commands to be outputted to the elements executing the instruction pre-fetch process. These commands are designed so as to interrupt the instruction pre-fetch process. Then, the block 62 allows commands to be outputted to the elements executing the effective address calculation. These commands are designed so as to calculate an address of a branch destination instruction B0. A block 63 following the block 62 allows a command to be outputted to an effective address calculator (not shown). This command is designed so as to perform effective address calculation in which an address or addresses of data to be processed by an instruction A1 are determined. In addition, the block 63 enables the address of the branch destination address B0 to be stored into the instruction pre-fetch counter 2 and the instruction decoding counter 7. A block 64 following the block 63 enables the instruction pre-fetch process to be started. The block 64 initializes the instruction buffer 3 and then stores the branch destination instruction B0 into the instruction buffer 3. The block 64 disables a state of the effective address calculation on the instruction A1. In addition, the block 64 disables a subsequent instruction A2 which is being decoded. The block 64 enables the address of the branch destination address B0 to be written over the address of the branch instruction BRA in the program counter buffer 8. A block 65 following the block 64 enables the effective address calculation process for the branch destination instruction B0. In addition, the block 64 disables a state of the effective address calculation on the instruction A2. After the block 65, the control sequence advances to steps of normal processing. DESCRIPTION OF THE SECOND PREFERRED EMBODIMENT With reference to Fig. 3, a processing system for a branch instruction includes a cache 10 holding instructions which can be read out at a high speed. In Fig. 3, a conditional branch instruction and a corresponding branch destination instruction flow along arrows composed of broken lines. An instruction pre-fetch counter 11 outputs an address which is used in precedently fetching a corresponding instruction from the cache 10. In order to update the address outputted from the pre-fetch counter 11, the pre-fetch counter 11 counts up the address by a value corresponding to the number of bytes of the related instruction. An address register 12 temporarily holds an address of a branch destination instruction which is calculated after a corresponding branch instruction is decoded. Instructions other than a branch destination instruction are sequentially transferred from the cache 10 to a FIFO (First-In First-Out) type instruction buffer 13. The instruction buffer 13 has four stages. It should be noted that the instruction buffer 13 may have only one stage or the number of stages of the instruction buffer 13 may differ from four. The instruction buffer 13 sequentially receives instructions from the cache 10 and cues the instructions. A branch instruction buffer 14 temporarily holds a branch destination instruction which is read out from the cache 10. An instruction decoder 15 sequentially receives instructions from the instruction buffer 13 and the branch instruction buffer 14 via selector 24 and then decodes the instructions, thereby deriving commands from the decoded instructions. As will be made clear hereinafter, the instruction decoder 15 has several control functions. It should be noted that lines of transmission of control signals from the instruction decoder 15 to other elements are omitted from Fig. 3. A FIFO type execution command buffer 16 cues commands outputted from the instruction decoder 15. The execution command buffer 16 has two stages. It should be noted that the execution command buffer 16 may have only one stage or the number of stages of the execution command buffer 16 may differ from two. An execution unit 17 sequentially receives commands from the execution command buffer 16 and executes the commands. An instruction decoding counter 18 generates an address corresponding to an instruction to be subsequently proecessed in the instruction decoder 15. The address generated by the instruction decoding counter 18 is periodically updated. During the address updating process, the instruction decoding counter 18 counts up the address by a value corresponding to the number of bytes of the related instruction. An address register 19 temporarily holds an address of a branch destination address which is calculated after the corresponding branch instruction is decoded. A FIFO type program counter buffer 20 cues addresses which are sequentially transferred from the instruction decoding counter 18 and the address register 19 via a selector 26. The program counter buffer 20 has four stages. It should be noted that the program counter buffer 20 may have only one stage or the number of stages of the program counter buffer 20 may differ from four. In general, addresses stored in the program counter buffer 20 correspond to instructions which are being subjected to a decoding process, a process or information in a first stage of the execution command buffer 16, a process or information in a second stage of the execution command buffer 16, and an execution process respectively. An adder 21 is controlled by the instruction decoder 15 in response to a branch instruction. Specifically, the adder 21 adds an address outputted from the instruction decoding counter 18 and a displacement supplied from the instruction buffer 13, and thereby generates a new address corresponding to a branch destination instruction. The branch destination address is transferred to the address registers 12 and 19, and is also transferred to the counters 11 and 18 via selectors 22 and 25. The selector 22 serves to select an input to the pre-fetch counter 11. A selector 23 serves to select an input to the cache 10. The selector 24 serves to select an input to the instruction decoder 15. The selector 25 serves to select an input to the instruction decoding counter 18. The selector 26 serves to select an input to the adder 21. In cases where a branch is absent from a series of instructions, the processing system of Fig. 3 operates as follows. An instruction is fetched from the cache 10 in accordance with an address generated by the instruction pre-fetch counter 11 and is stored into the instruction buffer 13. This is called an instruction pre-fetch process. The instruction pre-fetch counter 11 updates the present address and specifically generates a new address by counting up the present address by a value corresponding to the number of bytes of the instruction just transferred to the instruction buffer 13. The instruction pre-fetch counter 11 holds the new address until it is updated. Such processes are periodically reiterated so that instructions are sequentially transferred from the cache 10 to the instruction buffer 13. The instruction decoder 15 fetches an instruction from a bottom of the instruction buffer 13 via the selector 24 and decodes the fetched instruction. The instruction decoder 15 derives an execution command or commands from the fetched instruction and transfers the derived command or commands to the execution command buffer 16. When the command or commands are transferred to the execution command buffer 16, the instruction decoding counter 18 counts up the address by a value corresponding to the number of bytes of the decoded instruction and thereby generates a new address corresponding to an instruction to be decoded subsequently. While the instruction decoder 15 is processing an end word of an instruction, a header address of an instruction to be decoded subsequently is set in the instruction decoding counter 18. Such processes are periodically reiterated so that instructions are sequentially transferred from the instruction buffer 13 to the instruction decoder 15 and are sequentially decoded therein. In addition, execution commands are sequentially transferred from the instruction decoder 15 to the execution command buffer 16. Each time the decoding of one instruction is completed, the instruction decoder 15 allows a header address of a subsequent instruction to be transferred from the instruction decoding counter 18 to the program counter buffer 20 via the selector 26. The execution unit 17 fetches a command from a bottom of the execution command buffer 16 and executes the fetched command. Such processes are periodically reiterated so that commands are sequentially transferred from the execution command buffer 16 to the execution unit 17 and are sequentially executed thereby. An address held in a bottom of the program counter buffer 20 corresponds to an instruction having a command which is currently executed by the execution unit 17. Each time the execution of a command or commands of one instruction is completed, the address in the bottom of the program counter buffer 20 is discarded and is replaced with a new address. The operation of the processing system of Fig. 3 will be further described with reference to Fig. 4. In cases where a conditional branch instruction is taken, the processing system of Fig. 3 operates as follows. During a first cycle C0, a first instruction A0 is fetched from the cache 10 in accordance with an address generated by the instruction pre-fetch counter 11 and is stored into a bottom of the instruction buffer 13. This is called an instruction pre-fetch process. The instruction pre-fetch counter 11 updates the address and specifically generates a new address by counting up the present address by a value corresponding to the number of bytes of the instruction A0. The instruction pre-fetch counter 11 holds the new address until it is updated. It is now assumed that the new address corresponds to a conditional branch instruction Bcc. During a cycle C1 following the cycle C0, the branch instruction Bcc is transferred from the cache 10 to the instruction buffer 13 in the pre-fetch process while the instruction decoder 15 fetches the instruction A0 from the instruction buffer 13. The instruction A0 is decoded by the instruction decoder 15 so that a command or commands are derived from the instruction A0. The command or commands related to the instruction A0 are transferred to the execution command buffer 16. Simultaneously, the instruction decoding counter 18 generates an address corresponding to an instruction to be decoded subsequently and holds the generated address. During a cycle C2 following the cycle C1, an instruction A1 subsequent to the branch instruction Bcc is transferred from the cache 10 to the instruction buffer 13 in the pre-fetch process while the instruction decoder 15 fetches the branch instruction Bcc from the instruction buffer 13. The branch instruction Bcc is decoded by the instruction decoder 15. During the cycle C2, the command or commands related to the instruction A0 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction A0 are determined. Furthermore, the pre-fetch process is interrupted. During a cycle C3 following the cycle C2, an instruction A2 subsequent to the instruction A1 is transferred from the cache 10 to the instruction buffer 13 in the pre-fetch process while the instruction decoder 15 fetches the instruction A1 from the instruction buffer 13. The instruction A1 is decoded by the instruction decoder 15. During the cycle C3, the branch instruction Bcc is subjected to effective address calculation in which an address of an instruction B0 located at a downstream end or destination of this branch is determined. Specifically, the instruction decoder 15 allows a displacement to be transferred from the instruction buffer 13 to the adder 21 via the selector 24. The displacement is attached to the branch instruction Bcc. In addition, the instruction decoder 15 allows the address of the branch instruction Bcc to be transferred from the instruction decoding counter 18 to the adder 21 via the selector 26. Furthermore, the instruction decoder 15 activates the adder 21. The adder 21 adds the address of the branch instruction Bcc and the displacement and thereby generates a new address corresponding to the branch destination instruction B0. The address of the branch destination instruction B0 which is outputted from the adder 21 is stored into the address registers 12 and 19. The selectors 22 and 25 are controlled to prevent the address of the branch destination instruction B0 from being written into the counters 11 and 18. The instruction decoder 15 interrupts the instruction pre-fetch operation so that the instruction A2 remains in the bottom of the instruction buffer 13. During the cycle C3, the execution unit 17 fetches the command or commands of the instruction A0 from the execution command buffer 16 and executes the fetched command or commands. During a cycle C4 following the cycle C3, the instruction decoder 15 allows the address of the branch destination instruction B0 to be outputted from the address register 12 to the cache 10 via the selector 23. As a result, the branch destination instruction B0 is fetched from the cache 10 and is stored into the branch instruction buffer 14. The branch destination instruction B0 is not stored into the instruction buffer 13. At a final stage of the cycle C4, the instruction pre-fetch counter 11 holds an address of an instruction which is to be fetched subsequently to the instruction stored in the instruction buffer 13. In addition, the address register 12 holds the address of the branch destination instruction B0. The instruction decoding counter 18 holds the address of the instruction A1 which follows the branch instruction Bcc. The address register 19 holds the address of the branch destination instruction B0. The bottom of the instruction buffer 13 holds the instruction A2 which follows the instruction A1. The branch instruction buffer 14 holds the branch destination instruction B0. In this way, the instructions A2 and B0 are prepared in the buffers 13 and 14 respectively. The instruction A2 is to be executed when the branch instruction Bcc is not taken. The instruction B0 is to be executed when the branch instruction Bcc is taken. After the instructions A2 and B0 are prepared, the decoder 15 waits the determination of a condition flag of the instruction A0 in the execution unit 17 and interrupts the operations of the elements except the execution unit 17. During a cycle C5 following the cycle C4, after the condition flag of the instruction A0 is determined in the execution unit 17, the instruction decoder 15 judges whether or not a condition of the branch instruction Bcc is satisfied to take the branch instruction Bcc. In the case where the branch instruction Bcc is taken, the instruction decoder 15 changes the selector 24 so that the instruction decoder 15 fetches the branch destination instruction B0 from the branch instruction buffer 14 via the selector 24. The instruction decoder 15 initializes the instruction buffer 13. The instruction decoder 15 changes the selector 22 so that the header address of the branch destination instruction B0 is transferred from the address register 12 to the instruction pre-fetch counter 11 via the selector 22. The instruction decoder 15 changes the selector 25 so that the header address of the branch destination instruction B0 is transferred from the address register 19 to the instruction decoding counter 18 via the selector 25. The instruction decoder 15 changes the selector 26 so that the header address of the branch destination instruction B0 is transferred from the instruction decoding counter 18 to the program counter buffer 20 via the selector 26. In the program counter buffer 20, the header address of the branch destination instruction B0 is written over the address of the branch instruction Bcc. The instruction decoder 15 enables the instruction pre-fetch process to be started. The instruction decoder 15 decodes the branch destination instruction B0 and thus derives a command or commands from the branch destination instruction B0. The derived command or commands are transferred to the execution command buffer 16. The instruction decoder 15 disables the instruction A1 which was decoded. As understood from the previous description, the branch destination instruction B0 immediately follows the instruction A2 in the pre-fetch process so that an instruction or instructions located between the instructions A2 and B0 are prevented from undergoing the pre-fetch process. In this way, an unnecessary waste of the pre-fetch process is decreased. During a cycle C6 following the cycle C5, the command or commands related to the branch destination instruction B0 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction B0 are determined. During a cycle C7 following the cycle C6, the execution unit 17 fetches the command or commands of the branch destination instruction B0 from the execution command buffer 16 and then executes the fetched command or commands. An address held in the bottom of the program counter buffer 20 corresponds to an instruction having a command or commands which are currently executed by the execution unit 17. Each time the execution of the command or commands related to one instruction is completed, the address in the bottom of the program counter buffer 20 is discarded and is replaced with a new address. As described previously, after the instruction decoder 15 decodes the branch instruction Bcc and then performs effecitve address calculation related to the branch instruction Bcc, the instruction decoder 4 enables the fetch of the branch destination instruction B0 and waits the end of the execution of the command or commands of the instruction A0. When the execution of the command or commands of the instruction A0 is completed and the related flag is determined, the branch instruction Bcc is taken and the branch destination instruction B0 is promptly transferred to the instruction decoder 15. The instruction decoder 15 disables the instruction A1 which is located between the branch instruction Bcc and the branch destination instruction B0. The operation of the processing system of Fig. 3 will be further described with reference to Fig. 5. In cases where a conditional branch instruction is not taken, the processing system of Fig. 3 operates as follows. During a period from a first cycle C0 to a fifth cycle C4, the operation of the processing system is similar to that in the case where the conditional branch instruction is taken. During a cycle C5 following the cycle C4, the instruction decoder 15 changes the selector 24 so that the instruction decoder 15 fetches the instruction A2 from the instruction buffer 13 via the selector 24. The instruction A2 follows the instruction A1. The instruction decoder 15 changes or holds the selectors 22, 23, 24, 25, and 26 to or in states which occur during the absense of a branch instruction. The header address of the instruction A2 is transferred from the instruction decoding counter 18 to the program counter buffer 20. In the program counter buffer 20, the header address of the instruction A2 is written over the branch instruction Bcc. The instruction decoder 15 decodes the instruction A2 and thus derives a command or commands from the instruction A2. The derived command or commands are transferred to the execution command buffer 16. The command or commands of the preceding instruction A1 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction A1 are determined. During a cycle C6 following the cycle C5, the command or commands related to the instruction A2 are subjected to effective address calculation in which an address or addresses of data to be processed by the instruction B0 are determined. The execution unit 17 fetches the command or commands of the instruction A1 from the execution command buffer 16 and then executes the fetched command or commands. During a cycle C7 following the cycle C6, the execution unit 17 fetches the command or commands of the instruction A2 from the execution command buffer 16 and then executes the fetched command or commands. An address held in the bottom of the program counter buffer 20 corresponds to an instruction having a command or commands which are currently executed by the execution unit 17. Each time the execution of the command or commands related to one instruction is completed, the address in the bottom of the program counter buffer 20 is discarded and is replaced with a new address. As described previously, after the instruction decoder 15 decodes the branch instruction Bcc and then performs effective address calculation related to the branch instruction Bcc, the instruction decoder 15 enables the fetch of the branch destination instruction B0 and waits the end of the execution of the command or commands of the instruction A0. When the execution of the command or commands of the instruction A0 is completed and the related flag is determined, the branch instruction Bcc is not taken and the instruction A2 which was prepared is promptly transferred to the instruction decoder 15. The preceding instruction A1 is transmitted to a subsequent stage. As understood from the previous description, in the case where a conditional branch instruction Bcc is present, the branch instruction Bcc is completely processed within the instruction decoder 15 and is prevented from reaching the execution unit 17. The instruction decoder 15 enables the calculation of the address of a branch destination instruction B0 in independently parallel with the execution of commands of a preceding instruction by the execution unit 17. In addition, the instruction decoder 15 enables the high-speed preparation of each of the branch destination instruction B0 and the non-branch instruction in independently parallel with the execution of commands of the preceding instruction by the execution unit 17. The instruction decoder 15 holds the decoding process and the command generation suspended until a branch condition is determined. Furthermore, the judgment of the branch condition is performed within the instruction decoder 15. Accordingly, the branch instruction Bcc, the branch destination instruction B0, and the subsequent instructions are processed at high speeds. This embodiment will be further described with referene to Fig. 8. The instruction decoder 15 is similar to the instruction decoder 4 of Figs. 1 and 6 except for design changes indicated hereinafter. As shown in Fig. 8, a first block 71 of the control sequence determines whether or not a currently-inputted instruction is a conditional branch instruction Bcc. When the currently-inputted instruction is not the branch instruction Bcc, the control sequence advances to steps of normal processing. When the currently-inputted instruction is the branch instruction Bcc, the control sequence advances to a block 72. The block 72 allows commands to be outputted to the elements executing the instruction pre-fetch process. These commands are designed so as to interrupt the instruction pre-fetch process. Then, the block 72 allows commands to be outputted to the elements executing the effective address calculation. These commands are designed so as to calculate an address of a branch destination instruction B0. A block 73 following the block 72 allows a command to be outputted to an effective address calculator (not shown). This command is designed so as to perform effective address calculation in which an address or addresses of data to be processed by an instruction A1 are determined. In addition, the block 73 enables the address of the branch destination address B0 to be stored into the registers 12 and 19. The block 73 controls the instruction decoding counter 18 so that the instruction decoding counter 18 performs the count-up process and that the instruction decoding counter 18 generates an address corresponding to the instruction A1. A block 74 following the block 73 enables the branch destination instruction B0 to be stored into the instruction buffer 13. The block 74 suspends operations other than operation of the execution unit 17 and maintains a current state. After the block 74, the control sequence advances to a block 75. The block 75 judges whether or not a condition flag of the execution unit 17 is determined. When the condition flag is not determined, the block 75 is repeated. When the condition flag is determined, the control sequence advances to a block 76. The block 76 determines whether or not the branch is taken. When the branch is taken, the control sequence advances to a block 77. When the branch is not taken, the control sequence advances to a block 78. The block 77 allows the branch destination instruction B0 to be fetched from the branch instruction buffer 14 and enables the branch destination instruction B0 to be decoded. The block 77 enables the instruction pre-fetch process to be started. In addition, the block 77 disables a state of the effective address calculation. The block 77 allows the address of the branch destination instruction B0 to be stored into the instruction pre-fetch counter 11 and the instruction decoding counter 18. The block 77 enables the address of the branch destination instruction B0 to be written over the address of the branch instruction Bcc in the program counter buffer 20. After the block 77, the control sequence advances to steps of normal processing. The block 78 allows an instruction A2 to be fetched from the instruction buffer 13 and enables the branch destination instruction A2 to be decoded. The block 78 enables the instruction pre-fetch process to be started. In addition, the block 77 enables the address of the branch destination instruction B0 to be written over the address of the branch instruction Bcc in the program counter buffer 20. After the block 77, the control sequence advances to steps of normal processing.

Claims: A processing system for a branch instruction, comprising: a memory (1) for storing instructions including a branch instruction; a decoder (4); means (3) for sequentially transmitting instructions from the memory (1) to the decoder, wherein the decoder (4) sequentially decodes the instructions and derives commands from the respective instructions; an execution unit (6); means for sequentially transferring the commands from the decoder (4) to the execution unit (6), wherein the execution unit (6) sequentially executes the transferred commands; means included in the decoder (4) for detecting the branch instruction; said system being characterized by means included in the decoder (4) for preventing a command of the branch instruction from being transferred to the execution unit (6); and means included in the decoder (4) for allowing commands of the instructions except the branch instruction to be transferred to the execution unit (6). A processing system according to claim 1 wherein: the memory (1) for storing instructions includes a branch instruction and a corresponding branch destination instruction; and further comprising: an instruction pre-fetch address register (2) for storing a periodically updated address and supplying the address to the memory (1) for reading said instructions from the memory (1); an instruction buffer (3) for receiving said instructions from the memory (1) and sequentially storing said instructions read from the memory (1) by use of the periodically updated address in the instruction pre-fetch address register, the instruction decoder (4) receiving the instructions from the instruction buffer (3) for decoding said instructions and for generating commands in response thereto; means for interrupting a normal operation of the fetching means and forcing the fetching means to fetch the branch destination instruction to the instruction decoder (4) when the branch instruction is detected by the detecting means in the instruction decoder (4); and a calculator (9) for calculating a branch destination address; wherein, after an unconditional branch instruction has been decoded by the instruction decoder (4), the instruction decoder (4), in parallel with the execution of commands of a preceding instruction by the execution unit (6), enables the calculator (9) to calculate the address of a branch destination instruction, transfers the address of the branch destination instruction from the calculator (9) to the instruction pre-fetch address register (2), allows the pre-fetch address register (2) to output the address of the branch destination instruction to the memory (1), so that the branch destination instruction is transferred from the memory (1) to the instruction buffer (3) in a pre-fetch process, fetches the branch destination instruction from the instruction buffer (3) and decodes the branch destination instruction such that, in the case where four or more execution cycles are necessary to complete the execution of the command or commands related to the preceding instruction, there is substantially zero overhead due to the branch being handled. A processing system according to claim 2, said processing system further comprising a program counter buffer (8) for receiving addresses of instruction subjected to processing or execution, wherein, after the unconditional instruction has been decoded and the address of the branch destination instruction has been calculated, the instruction decoder (4) enables the address of the branch destination instruction to be written over the address of the branch instruction previously received by said program counter buffer (8).

Inventors: KIMURA KOZO, KIYOHARA TOKUZO, MATSUZAKI TOSHIMICHI, KIMURA, KOZO, KIYOHARA, TOKUZO, MATSUZAKI, TOSHIMICHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: G06F9
IPC codes: G06F9