PHASE DIFFERENCE DETECTING APPARATUS

Abstract: A phase difference-detecting apparatus for detecting a relative distance between a pair of focused images obtained from subject luminous flux passed through an objective lens (5) to thereby judge a focusing state of the objective lens (5), comprises a first light-receiving section constituted by picture elements arranged in a row so as to receive a first one of the focused images; a first signal reading-out section for transferring, in a predetermined direction, signals generated in the respective picture elements of the first light-receiving section, and at the same time, outputting the signals in parallel to each other through floating gates of a CCD; a first signal-­ generating device (1) including the first light-receiving device, the first signal reading-out device, and conversion device for converting the signals output in parallel from the first signal reading-out section into a first time series signal and outputting the first time series signal; a second light-receiving section constituted by picture elements arranged in a row to receive a second one of the focused images; a second signal reading-out section for transferring, in a predetermined direction, signals generated in the respective picture elements of the second light-receiving section, and at the same time outputting the signals in parallel to each other through floating gates of a CCD. In addition, a second signal-generating device (2) is provided including the second light-receiving device, the second signal reading-out device and a converting device for converting the signals output in parallel from the second signal reading-out section into a second time-series signal which has a predetermined quantity of relative movement relative to the first time series signal and outputting the second time series signal.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference detecting apparatus which is suitably applicable, for example, to an automatic focal point detecting device of a camera, and particularly relates to a phase difference detecting apparatus for performing operation processing for phase difference detection through analog signal processing. 2. Description of Related Art A conventional phase difference detecting apparatus will be described in relation to an automatic focal point detecting device of a camera. A condenser lens, a separator lens and a phase difference detecting apparatus are positioned in sequence in the rear of a film equivalent plane located in the rear of an objective lens. The phase difference detecting apparatus is provided with a pair of image sensors constituted by CCDs or the like for photoelectrically converting a pair of subject images focused by the separator lens, and an operation circuit for operating on a phase difference between the pair of subject images on the basis of electric signals generated through the photoelectric conversion so as to judge the focus state. That is, a signal B(k) to be operated on which is time-serially output from one of the image sensors and a signal R(k) to be operated on which is time-serially output from the other image sensor are subject to differential operation on the basis of the following equation (1) to thereby calculate values H(1), H(2)...H(ℓ), so that the focus state and the quantity of focal displacement are detected on the basis of a distribution pattern of the correlative values. H(ℓ) = | B(k) - R(K+ℓ-1) | (1) where ℓ is an integer not smaller than 1 which shows a quantity of relative movement between the signals B(K) and R(k). Such a phase difference detecting apparatus is also described in EP-A3-00259887, claiming an earlier priority date as the present application, and being published after the priority date of the present application. Another kind of phase difference detecting apparatus is known from US-AS-4178098. In the circuit described in this reference, charges corresponding to an image are generated in two spaced-apart sensors. The generated charges in each of the sensors are serially shifted and output into sample and hold circuits. Electrical signals corresponding to the charges are output from the sample and hold circuits to analog shift registers, from which they are provided in parallel to a coincidence detecting circuit, in which a phase coincidence detection is carried out. In contrast to the present invention, this coincidence detection circuit either multiplies corresponding signals from the two sensors in parallel and adds the respective results, or generates and adds absolute difference values of corresponding signals of the two sensors. It is the object of the present invention to provide a phase difference detecting apparatus in which operation processing can be executed at a high speed and with high accuracy and which can be constituted by an IC with a simple arrangement. This object is solved by the features of claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the present invention will be apparent from the following description taken in connection with the accompanying drawings, wherein: Fig. 1 is a block diagram illustrating a basic arrangement of an embodiment of the phase difference detecting apparatus according to the present invention; Fig. 2 is a schematic diagram illustrating the details of the basic arrangement in Fig. 1 when applied to an automatic focal-point detecting device apparatus; Fig. 3 is a block diagram illustrating an embodiment of the first and second signal generating means of Fig. 1; Fig. 4 is a schematic diagram illustrating the arrangement of the light receiving section, the storage section and the shift register section of the first and second signal generating means of Fig. 3; Fig. 5 is a sectional view illustrating a main part of the first and second signal generating means for explaining the principle of the operation thereof; Fig. 6 is a circuit diagram illustrating the arrangement of the operation means of Fig. 1; Fig. 7 is a timing chart for explaining the operation of the operation means of Fig. 6; and Fig. 8 is an explanatory diagram illustrating the principle of judgment of the state of focus on the basis of a pattern of distribution of the correlative values obtained by this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the phase difference detecting apparatus according to the present invention will be described with reference to the drawings. Fig. 1 is a block diagram illustrating a basic arrangement which is constituted by first and second signal generating means 1 and 2 for respectively generating a pair of signals R and B to be operated on a phase difference between which is to be detected, an operation means 3 for performing the same processing of differential operation as the above-mentioned equation (1), and a synchronizing signal-generating means 4 for controlling the operation of the entire apparatus. Although this phase difference detecting apparatus may be applied to various usages since it is generally capable of detecting a phase difference between a pair of signals to be operated on, the embodiment will be described as to a case in which the phase difference detecting apparatus is applied to an automatic focal point detecting device of a camera for photography, for a video system, or the like. The arrangement will be described, first. In Fig. 2, a condenser lens 7 and a separator lens 8 are disposed in the rear of a film equivalent plane 6 which is in turn disposed in the rear of an objective lens 5 provided in an optical system of a camera, and a first and a second signal generating menas 1 and 2 are provided in a focal plane of the separator lens 8. At the first and second signal generating means 1 and 2, charge-storage devices disclosed in Japanese Patent Applications No. 61-212720, No. 61-212721 and No. 61-222211 previously filed by the inventor of this application, or the like, may be used. Fig. 3 shows the case where a reference image sensor and a reference reading-out section and a base image sensor and a base reading-out section disclosed in No. 61-222211 are used as the first signal generating means 1 and the second signal generating means 2, respectively. Referring to Fig. 3, the arrangement will be described. In Fig. 3, the first signal generating means 1 includes a light receiving section 22 having a plurality of photoelectric conversion elements constituted by photodiodes D r1 - D rn for receiving one of the focused images from the separator lens 8, and the second signal generating means 2 includes a light receiving section 23 having a plurality of photoelectric conversion elements constituted by photodiodes D b1 - D bn for receiving the other focused image from the separator lens 8. The light receiving sections 22 and 23 are separated from each other by a predetermined distance and extended in the direction perpendicular to the optical axis. A storage section 24 and a shift register section 26 are successively provided to follow the light receiving section 22 and a storage section 25 and a shift register section 27 are successively provided to follow the light receiving section 23. That is, the storage section 24 and the shift register section 26 are constituted by CCDs (charge coupled devices) respectively including charge transfer elements T r1 - T rn and C r1 - C rn respectively corresponding to the photoelectric conversion elements D r1 - D rn , while the storage section 25 and the shift register section 27 are constituted by CCDs respectively including charge transfer elements T b1 - T bn and C b1 - C bn respectively corresponding to the photoelectric conversion elements D b1 - D bn . The storage section 24 receives in parallel signal charges generated in the conversion elements D r1 -D rn and transfers in parallel the received signal charges to the shift register section 26, while storage section 25 receives in parallel signal charges generated in the conversion elements D b1 - D bn and transfers in parallel the received signal charges to the shift register section 27. The one shift register section 26 transfers the charges in the direction of the shift register section (called in the following "horizontal direction") as indicated by an arrow. Although the operation of the shift register sections 26 and 27 will be described later, the other shift register section 27 is arranged so as not to transfer the charges in the horizontal direction. The reference numerals 28 and 29 represent conductive layers which are formed on the surfaces of channel sections for transferring the signal charges from the light receiving sections 22 and 23 to the storage sections 24 and 25 respectively. The conductive layers are formed of polysilicon layers to act as potential barriers respectively. The reference numerals 30 and 31 represent transfer gates 30 and 31 for controlling the movement of the signal charges respectively. Further, floating gates F r1 - F rn are formed adjacently to the charge transfer elements C r1 - C rn respectively, and are connected to a reset terminal RES through MOS FETs M r1 - M rn each having a gate supplied with a control signal CE and to a common connection point Pr through MOS FETs Q r1 - Q rn for performing multiplex operation to channel change-over signals CH 1 - CH n applied to their gates. On the other hand, floating gates F b1 -F bn are formed adjacently to the charge transfer elements C b1 - C bn respectively, and are connected to a reset terminal RES through MOS FETs M b1 - M bn each having a gate supplied with a control signal CE and to a common connection point Pb through MOS FETs Q b1 - Q bn for performing multiplex operation in response to channel change-over signals CH 1 - CH n applied to their gates. The connection points are connected to output terminals P ro and P bo through impedance conversion circuits 32 and 33 respectively. The impedance conversion circuits 32 and 33 have the same construction as each other. The circuit 32 is constituted by MOS FETs I r1 and I r2 with their drain-source circuits connected in series to each other between a power source V DD and an earth terminal, and an MOS FET I r3 connected in parallel to the gate-source circuit of the MOS FET I r1 for clamping the common connection point Pr to the power source V DD upon application of a refresh signal ø R , while the circuit 33 is constituted by MOS FETs I b1 and I b2 with their drain-source circuits connected in series to each other between the power source V DD and the earth terminal, and an MOS FET I b3 connected in parallel to the gate-source circuit of the MOS FET I b1 for clamping the common connection point Pb to the power source VDD upon application of a refresh signal ø R . The gate of each of the MOS FETs I r2 and I b2 is biased to a predetermined potential. Next, referring to Fig. 4, description will be made about the positional relationship of the shift register sections 26 and 27 and the floating gates F r1 -F rn and F b1 - F bn . In the first signal generating means 1, each of the set of photoelectric conversion elements constituting the light receiving section 22 and the set of charge transfer elements constituting each of the storage section 24 and the shift register section 26 is forty-eight in number. The forty-eight elements in each set are provided at equal pitch widths W and grouped into a first, a second and a third block I R , II R and III R , the four elememts located at one side belonging to the first block I R , the four elements located at the other side belonging to the second block II R , the remainder 40 elements belonging to the third block III R . The floating gates F r1 - F r40 are provided correspondingly to the charge transfer elements C r1 - C r40 belonging to the third block III R and grouped into a fourth and a fifth block IV R and V R including the thirty-two floating gates F r1 - F r32 and the remainder eight floating gates respectively. The respective one ends of the forty floating gates F r1 - F r40 are connected to the reset termial RES through the MOS FETs M r1 , M r2 , ..., and the floating gates F r1 - F r32 of them are connected commonly to the connection point Pr through the MOS FETs Q r1 - Q rn , as seen in Fig. 3. That is, only the parts belonging to the third and fourth blocks III R and IV R of Fig. 4 are illustrated as representative in the first signal generating means 1 in Fig. 3, while the parts belonging to the other blocks I R , II R and V R which are the preparatory areas to be actuated to transfer the signal charges in the horizontal direction are omitted in Fig. 3. In the second signal generating means 2, on the other hand, each of the set of photoelectric conversion elements constituting the light receiving section 23 and the set of charge transfer elements constituting each of the storage section 25 and the shift register section 27 is forty in number. The forty elements in each set are provided at equal pitch widths W (equal to those in the first signal generating means 1) and grouped into a first, a second and a third block I R , II B and III B , the four elements located at one side belonging to the first block I B , the four elements located at the other side belonging to the second block II B , the remainder 32 elements belonging to the third block III R . The floating gates F b1 - F b32 are provided correspondigly to the charge transfer elements C b1 - C b32 belonging to the third block III B . The respective one ends of the floating gates F b1 - F b32 are connected to the MOS FETs M b1 - M bn and Q b1 - Q bn in Fig. 3. That is, the second signal generating means is illustrated in Fig. 3 as to belong to the third block III B of Fig. 4. The light receiving section 22 is formed separately from the optical axis by a distance of ℓ₁, and the light receiving section 23 is formed separately from the optical axis by a distance ℓ₂ (= ℓ₁ + 4W), that is, a distance obtained by adding a four-pitches width 4W to the distance ℓ₁. The phase difference detecting apparatus according to the present embodiment is constituted by an IC as a semiconductor integrated circuit device, and the structures of the signal generating means 1 and 2 and the floating gates shown in Figs. 3 and 4 will be described with reference to a schematic sectional view of Fig. 5. In Fig. 5, a plurality of N⁺-type layers are formed in a portion of a P-type diffusion layer (P-well) formed in a surface portion of an N-type semiconductor substrate to thereby form the photoelectric conversion elements of the light receiving section 22(23). Transfer gate electrode layers constituting the respective charge transfer elements of the barrier section 28 (29) and the storage section 24 (25), a gate electrode layer constituting the transfer gate 30 (31), and transfer gate electrode layers constituting the respective charge transfer elements of the shift register section 26 (27) are provide side by side on the semiconductor substrate through an SiO₂ layer (not shown). Further, an electrode layer Aℓ to be clamped to the power source V DD and polysilicon layers constituting the floating gates F r1 - F rn and F b 1 - F bn are laminated adjacently to the shift register section 26 (27). The electrode layer Aℓ is formed to cover the whole of the upper surfaces of the floating gates F r1 - F rn and F b1 - F bn formed in plurality. The MOS FETs M r1 - M rn and M b1 - M bn are connected to the one ends of the respective floating gates. The potential of a reset signal ø FG applied to the reset terminal RES is made equal to the power source V DD and te floating gates F r1 - F rn (F b1 - F bn ) are clamped to the poewer source V DD through the MOS FETs M r1 - M rn (M b1 - M bn ) by a "H"-level control signal CE. If the MOS FETs M r1 - M rn (M b1 - M bn ) are then turned off again, a deep potential well is formed in the semiconductor substrate as indicated by a dotted line in Fig. 5 so that the signal charges of the shift register section 26 (27) flow into the areas under the floating gates. The voltage changes are produced in the respective floating gates F r1 - F rn (F b1 - F bn ) correspondingly to the respective charge quantities of the flowed signal charges so that a pattern of image focused on the light receiving section 22 (23) can be detected as voltage signals. On the other hand, if the MOS FETs M r1 - M rn (M b1 -M bn ) are turned on to thereby make the floating gates F r1 - F rn (F b1 - F bn ) "L"-level after the reset terminal RES has been made equal to the earth potential, the potential well in the areas under the floating gates becomes so shallow that the signal charges can be returned to the shift register section 26 (27) again. Since the movement of the signal changes is achieved non-destructively, the reading out of signal charges can be repeated. The signals thus generated through the floating gates F r1 - F rn (F b1 - F bn ) are converted into a time series signal R(k) (B(k)) by the multiplex operation of the MOS FETs Q r1 - Q rn (Q b1 - Q bn ), and the time series signal R(k) (B(K)) are output to the output terminal P rO (P bO ). Next, referring to Fig. 6, the arrangement of the operation means 3 shown in Fig. 1 will be described hereunder. The operation means 3 is constituted by a switching-capacitor integrator. A signal line extended from the output terminal P rO of the first signal generating means 1 (with reference to Fig. 3) is connected to an inversion input terminal of a differential integrator 42 through a series connection of a switching element 40, a capacitive element C s1 , and a switching element 41, the opposite ends of the capacitive element C s1 being connected to an earth terminal through switching elements 43 and 44 respectively. On the other hand, a signal line extended from the output terminal P bO of the second signal generating means 2 (with reference to Fig. 3) is connected to the inversion input terminal of the differential integrator 42 through a series connection of a switching element 45, a capacitive element C s2 and a switching element 46, the opposite ends of the capacitive element C s2 being connected to an earth terminal through switching elements 47 and 48 respectively. A switching element 50 and a capacitive element C I connected in parallel to each other are connected between the inversion input terminal and an output terminal 49 of the differential integrator 42. Further, inversion and non-inversion input terminals of an analog comparator 51 are respectively connected to the signal lines extended from the output terminals P rO and P bO , and an output terminal of the analog comparator 51 is connected to an input terminal of a channel selection circuit 52 which generates selection signals ø₁, ø₂, KA and KB for controlling "ON" and "OFF" of the switching elements 40, 41, 43, 44, 45, 46, 47 and 48. The analog comparator 51 outputs a polarity signal S gn which has an "H"-level when the levels of the signals to be operated are in the relationship of R(k) ≧ B(k) and has an "L"-level when R(k) < B(k), so that the voltage levels of the selection signals ø₁, ø₂, KA and KB are determined on the basis of the level of the polarity signal S gn . Next, the operation of the thus arranged operation means 3 will be described with reference to the timing charge of Fig. 7. First, after the switching element 50 has been turned "ON" by a reset signal ø RST applied from a not-shown reset means to thereby discharge unnecessary charges in the capacitive element C I , the switching element 50 is turned "OFF" so that the operation shown in Fig. 7 is started. The signals R(k) and B(k) to be operated on are output, respectively, from the first and second signal generating means 1 and 2 with a predetermined period as shown in the diagram (A) of Fig. 7. When the signals to be operated on are in the relationship of R(k) ≧ B(k), for example, in a period from a point of time t₁ to a point of time t₂, the polarity signal S gn becomes "H" so that the selection signals ø₁, ø₂, KA and KB of rectangular waves as shown in the respective diagrams (B), (C), (D) and (E) of Fig. 7 are generated. Then, the selection signals ø₁ and ø₂ are generated in a timing so that both of the signals KA and KB do not become "H" simultaneously. If the signals to be operated are in the relationship of R(k) < B(k), for example, in a period from a point to time t₃ to a point of time t₄, on the other hand, the polarity signal S gn becomes "L" so that the selection signals KA and KB whose phases are opposite to those in the period from the point of time t₁ to the point of time t₂. The selection signals ø₁ and ø₂ are generated in a constant timing independently of the level of the polarity signal S gn . The switching elements 44, 48, 40 and 47 are made to be "ON" by those selection signals ø₁, ø₂, KA and KB in a fore-half period T F1 of the period t₁ - t₂ so that the capacitive element C S1 is charged with the signal R(k) to be operated while the unnecessary charges of the capacitive element C S2 are discharged. Next, in a rear-half period T R1 of the period t₁ - t₂, the switching elements 43 and 41 are made to be "ON" so that the charges of the capacitive elements C S1 and C S2 are combined, and simultaneously the switching elements 45 and 46 are turned "ON" and the switching elements 47 and 48 are turned "OFF" so that the signal B(k) to be operated is supplied through the capacitive element C S2 to the differential integrator 42. Consequently, a charge q(k) as shown in the following equation (2) is stored in the capacitive element C I . q(k) = (C I /C S1 )·R(k) - (C I /C S2 )·B(k) (2) On the other hand, when the signals to be operated on are in the relationship R(k) < B(k), for example, in the period from t₃ to t₄, the switching elements 44, 48, 43 and 45 are "ON" in a fore-half period T F2 of the period t₃ - t₄ so that the capacitive element C S2 is charged with the signal B(k) to be operated on and the unnecessary charges of the capacitive element C S1 are discharged. Next, in a rear-half period TR₂ of the period t₃ - t₄, the switching elements 47 and 46 are "ON" so that the charges of the capacitive elements C S2 and C I are combined, and simultaneously the switching elements 40 and 41 are turned "ON" and the switching elements 43 and 44 are turned "OFF" so that the signal R(k) is supplied to the differential integrator 42 through the capacitive elements C S1 . Consequently, a charge q(k) as shown in the following equation (3) is stored in the capacitive element C I . q(k) = (C I /C S2 )·B(k) - (C I /C S1 )·R(k) (3) As seen from the above equations (2) and (3), the charges corresponding to the value obtained by subtracting one of the signals to be operated on having a small level from the other having a large level is stored in the capacitive element C I in the operation means, and therefore if the processing is repeatedly carried out on the time series signals R(1)....R(n) and B(1)....B(n) to be operated, an absolute value H of the difference between these signals is obtained as a voltage signal at the output terminal 49 as shown in the following equation (4). After completion of the operation of the above equation (4) in the first and second signal generating means 1 and 2 of Fig. 3, the signal charges held by the shift register section 26 of the first signal generating means 1 are shifted by one pitch to the signal charges of the other shift register section 27, and the signal charges of the respective shift register sections 26 and 27 which are displaced in phase relative to each other are time serially read out again so as to be subject to the operation processing of the above equation (4). Then, the signal charges of the shift register sections 26 and 27 are displaced in phase relative to each other and subject to the processing repeatedly. The displacement in phase corresponds to the above-mentioned quantity of relative movement ℓ, and the correlative value when the quantity of movement ℓ is sequentially changed can be obtained as the following equation (5) and can be detected as a voltage signal from the output terminal 49. That is, this equation (5) corresponds to the above-mentioned equation (1), and the correlative values H(1), H(2)..., H(ℓ) can be obtained through analog signal processing. Then, the phase difference can be detected on the basis of a pattern of distribution of these correlative values. For example, the diagrams (a) - (c) of Fig. 8 show the patterns of the correlative values in the case where the apparatus is applied to an automatic focal-point detecting device in a camera. Assuming that the state in focus is obtained in the case of the diagram (a) of Fig. 8 in which the maximum correlative value is obtained in the condition of the quantity of relative movement ℓ = 4, it is possible to judge the state to be "ahead focus" when the maximum correlative value is obtained at the quantity of relative movement smaller (ℓ=2) than the above case, and to be "behind focus" when the maximum correlative value is obtained at the quantity of relative movement larger (ℓ=6) than the above case. In the phase difference detecting apparatus in which a relative distance between a pair of focused images obtained from subject luminous flux passed through a taking lens is detected to thereby judge the state of focus of the taking lens, according to the present invention, as described above, signals generated by photoelectric conversion of the respective focused images are stored in CCDs and are non-destructively output through floating gates provided on the CCDs, so that it is not necessary to separately provide a large-scale memory to make it possible to reduce the size of the apparatus. Moreover, since the method of charge-couple by means of capacitive elements is used to calculate the correlative values of the output signals, it is possible to perform the operation at a high speed and accurately. Further, since the circuit arrangement is simple and the relative accuracy of the capacitive elements can be improved if the semiconductor integrated circuit technique is used, the phase difference detecting apparatus according to the present invention can be suitably produced in the form of a semiconductor integrated circuit.

Claims: A phase difference detecting apparatus for detecting the relative position of two images of a subject obtained through a separator lens (8), said apparatus comprising: a first signal generating means including: a first light-receiving section (22) constituted by photoelectric conversion elements (D r1 -D rn ) arranged in a row so as to receive a first one of said images; a first signal reading-out section (24,26,C r1 -C rn ,F r1 -F rn ), for shifting, in a predetermined direction along the row of said conversion elements, signals generated in said respective conversion elements of said first light-receiving section and at the same time outputting said signals in parallel to each other; and means (M r1 -M rn ,Q r1 -Q rn ) for converting said signals output in parallel from said first signal reading-out section into a first time series signal and outputting said first time series signal (R k ) and outputting after a shift by a predetermined pitch, a shifted first time series signal (R k+1 ); a second signal generating means including: a second light-receiving section (23) constituted by photoelectric conversion elements (D b1 -D bn ) arranged in a row so as to receive a second one of said images; a second signal reading-out section (25,27,C b1 -C bn ,F b1 -F bn ) for transferring, in a predetermined direction along the row of said conversion elements, signals generated in said respective conversion elements of said second light-receiving section and at the same time outputting said signals in parallel to each other; means (M b1 -M bn ,F₁-F bn ) for converting said signals output in parallel from said second signal reading-out section into a second time series signal which has a predetermined phase shift relative to said first time series signal and outputting said second time series signal (B k ); characterised by: switching-capacitor integrator means (42,50) including a plurality of capacitive elements (C s1 ,C s2 ,C I ) and switching elements (40,41,43,44,47,48) for intermittently connecting said capacitive elements to each other, and for receiving said first and second time series signals; and control means (51) for comparing the amplitudes of said first and second time series signals with each other to thereby generate control signals (₁,2,K A ,K B ) controlling said switching elements (40,42,43,44,47,48) to cause said switching-capacitor integrator means (42,50) to generate an integrated value (H) of the absolute value of the differences between said first and second time series signals and to cause said switching-capacitor integrator means to generate, as a correlation value corresponding to the phase difference between the two images, an integrated value (H ) on the basis of said first and second time series signals (R (k) ,B (k) ), whereby said first time series signal (R (k) ) is shifted by a predetermined number of said pitches.

Inventors: BABA, SHIGENORI, MIIDA, TAKASHI, OZAKI, NOZOMU, TAKASAKA, KUNIMITSU
Applicants: FUJI PHOTO FILM CO., LTD.
Application year: 1988
Main classification: G03B3
IPC codes: G03B13, G02B7, G01J9