Data processor having expanded operating functions

Abstract: A data processor is disclosed which includes a program memory storing a string of instruction, a program counter producing address data for designating a memory location of the program memory storing an instruction to be executed, an instruction decoder decoding the instruction read-out from the program memory and producing a first control signal, and an execution unit executing a first operation in response to the first control signal. The processor further includes a control signal generation circuit detecting that the address data from the program counter takes a specific content and producing a second control signal in response thereto. The processor thus executes a second operation responsive to the second control signal in parallel to the first operation.

Description: The present invention relates to a data processor and, more particularly, to such a processor in which a program memory for storing a string of instructions and an execution unit for decoding and executing each instruction are provided in a single semiconductor chip. In a data processor fabricated on a single semiconductor chip such as a single-chip microcomputer or a single-chip peripheral controller for a disk drive, a display unit, etc., the operable functions thereof are determined by instructions stored in a program memory provided in the processor. That is, the processing capability is restricted by the number and the bit length of instructions which are stored in the program memory, or by the capacity of the program memory. If the number of instructions and/or the bit length of each instruction is increased for expanding the processing capability, a structural design change is required wherein the memory capacity of the program memory and/or the bit length of a program counter must be enlarged. For this reason, even when a version-up processor is developed in which new operating functions are added to the previously developed processor or in which a part of the functions of the previously developed processor is improved, the new design of such version-up processor requires a long time of duration. Moreover, the addition of new instructions increases the numbers of reading-out and decoding operations, so that the processing speed is lowered. IBM Technical Disclosure Bulletin, vol. 16, No. 11, April 1974, page 3723, discloses a memory device with read-only store alteration. To this end the device includes an associative storage which is addressed simultaneously with a read-only storage. This associative storage contains predetermined addresses plus corresponding mask data bits, and whenever a corresponding address selects a storage position of the read only storage, the contents of that storage position are selectively modified by an exclusive OR circuit supplied with the mask bits from the associative storage. By this technique it is possible, for example, to repair deffective storage positions or to change or substitute instruction data from the main storage. It is an object of the invention to provide a data processor providing an improvement for expanding and enhancing the processing functions without changing either the number of instructions stored in the program memory or the code or bit length of these instructions. Another object of the invention is to provide a data processor to which new processing data functions can be added without lowering the processing speed. These objects are achieved by a data processor as defined in claim 1; the dependent claims relate to further developments of the invention. The processor of the present invention provides means for producing the second control signal for additional processing functions or improvement in the processing functions, this means operating independently of the instruction decoding means but being responsive only to the specific address data supplied to the program memory. Accordingly, the processing functions can be expanded without changing the memory capacity of the program memory and the bit length and code of each instruction. Moreover, as the execution means simultaneously executes the first and second instructions, the processing speed is not lowered. The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a preferred embodiment of the present invention; Fig. 2 is a circuit diagram representing the detailed construction of the respective blocks shown in Fig. 1; and Fig. 3 is a circuit diagram illustrating another preferred embodiment of the present invention. Referring now to Fig. 1, a data processor according to a preferred embodiment of the present invention is formed as a semiconductor integrated circuit and includes a program memory 1 which is a read-only memory (ROM), for example, storing a string of instructions for a program. A program counter 3 produces address data for designating a memory location of instructions stored in the program memory 1 to be executed. The address data read-out from the program counter 1 is supplied via a signal line 9 to an address decoder 2 which in turn produces a decoded address signal supplied to the program memory 1 via a signal line 11. Thus, one memory location of the program memory 1 is designated to read-out an instruction code stored in the program memory 1. The designated location is transferred to an instruction register 4 via a signal line 12. The instruction register 4 temporarily stores the instruction code read-out from the memory 1 and supplies it to an instruction decoder 5 which produces a set of first control signals 15 to 21 in accordance with it. Selective ones of these first control signals 15 to 21 take an active level. The first control signals 15 to 21 are supplied to an execution unit 30, so that a predetermined operation responsive to the instruction read-out from the memory 1 is performed by the unit 30. In particular, the first control signals 15 and 16 are used to control a circuit 8 included in the execution unit 30. The data processor shown in Fig. 1 further includes a control signal generation circuit 6 in accordance with the present invention. This circuit 6 receives at least a part of address data produced by the program counter 3 via a signal line 10 to detect whether or not the received address data is coincident with pre-selected address data. When the address data from the program counter 3 is coincident with the pre-selected address data, the circuit 6 generates a second control signal 14. In the present embodiment, this second control signal 14 is used for the same purpose as the control signal 16, and, therefore, the first and second control signals 16 and 14 are supplied to an OR gate 7 the output signal 18 of which being supplied to the circuit 8. Assuming that the control signal 16 is produced in response to the instruction designated by a first address data from the program counter 3, the circuit 6 generates the second control signal 14 when the program counter 3 produces a second address data that is different from the first address data. Accordingly, the signal 18 used for controlling the circuit 8 is generated when the program counter 3 produces either of the first address data or the second address data. Moreover, the second address data from the program counter 3 designates the location in the memory 1 to derive an instruction that changes the level of the control signal 19, for example, to an active level. Consequently, the execution unit 30 performs the processing operation in response to the control signal 19, simultaneously with the control of the circuit 8 by the signal 18. Furthermore, since the second control signal 14 is generated in response to the address data from the program counter 3, an increase in the number of instructions in the program memory 1 or in the code or bit length of each instruction is not required. Thus, the set of first control signal 15 to 21 from the instruction decoder 5 and the second control signal 14 from the circuit 6 are produced independently of each other in response to one address data from the program counter 3. These first and second control signals are processed in the same instruction execution cycle, resulting in no lowering of the execution speed. Cn the other hand, if the second control signal 14 is employed separately from the first control signals 15 to 21, the OR gate 7 may be omitted to supply the second control signal 14 directly to the execution unit 30. Referring to Fig. 2, there is shown a detailed circuit construction of the respective blocks of Fig. 1 in order to further describe the features and operations of the present invention. The program counter 3 produces the address data of three bits A₀, A₁ and A₂. The true and complementary signals thereof are supplied to the address decoder 2. The program memory 1 stores eight kinds of instructions shown in the following table 1. Each instruction consists of three bits I₀, I₁ and I₂: Address Instruction Code Control Signal Taking Active Level A₀ A₁ A₂ I₀ I₁ I₂ 0 0 0 0 0 0 20 1 0 0 1 1 1 19 0 1 0 0 1 0 21 1 1 0 1 1 0 17, 14 0 0 1 0 1 1 15 1 0 1 1 0 1 16 0 1 1 0 1 1 15 1 1 1 1 1 0 17 The control signal generation circuit 6 is composed of three-input NOR gate 61 which receives the complement of the first address bit A₀, the complement of the second address bit A₁ and the true bit of the third address bit A₂. Therefore, the control signal generation circuit 6 generates the second signal 14 when the program counter 3 produces the address data of "110". This address data is used to read the instruction code of "110" from the program memory 1 and activates the control signal 17. In the initial state, the program counter 3 is reset to "000", and hence the program stored in the memory 1 is executed from the memory location "0". The instruction code "000" stored in the memory location "0" is read-out from the memory 1 and then transferred to the register 4. The instruction decoder 5 decodes the instruction "000" so that the execution unit 30 performs the operation based upon the active level control signal 20. When the instruction execution is completed, the content of the program counter 3 is incremented to designate the next memory location "1" of the memory 1. When the program counter 3 now produces the address data of "110", the control signal 17 takes an active level, so that the execution unit 30 executes "CALL" instruction. Simultaneously, the second control signal 14 takes the active level to set a flip-flop 81 forming the circuit 8. As a result, the data processing is performed by use of the set output of the flip-flop 81. In subsequence, in response to the instructions stored in the memory locations "5", "6' and "7", the control signals 16, 15 and 17 are respectively activated, so that the corresponding data processings are performed by the execution unit 30. Thus, the flip-flop 81 is reset by the instructions stored in the memory locations "4" and "6" of the program memory 1 and further set by the address data of "110" from the program counter 3 independently of the instruction decoder 5. The address data "110" reads out the "CALL" instruction. Namely, the set condition of the flip-flop 81 and the "CALL" instruction are executed in the same cycle. Next, one example of the data processing will be. described below. The data processor performs a serial data transfer function in which data to be transferred is read-out from a source device in a byte unit and checked to have a correct form in the byte unit. In this case, the data checking operation is carried out in response to the instruction for requesting the next byte data to the source device. In construction shown in Fig. 2, the flip-flop 81 is set by the instruction for next byte data transfer. The set output of the flip-flop 81 is thus employed for starting the data checking operation. When the last byte data is requested to be read from the source device and then transferred to a destination device, the byte data to be transferred is no longer present in the source device. That is, the flip-flop 81 is not set so that the data checking for the last byte data is carried out. However, by setting the address data of "110" into the program counter 3, the flip-flop 81 is set parallel to the execution of the "CALL" instruction which is to be executed after the serial data transfer, so that the data checking operation for the last byte data is carried out. There is no change in the number and code of instructions to keep the processing speed high. Referring to Fig. 3, there is shown another embodiment of the present invention wherein the same constituents as those shown in Figs. 1 and 2 are denoted by the like reference numerals to omit the further description thereof. In this embodiment, the address decoder 2 is designed to have a function as the control signal generation circuit 6 shown in Figs. 1 and 2, and therefore the circuit 6 is omitted. More specifically, the address decoder 2 receives the address data from the program counter 3. When the address data takes a value of "110", the address decoder 2 produces an active level selection signal for designating the memory location "3" of the program memory 1. This selection signal is led out as the second control signal 14 and then transferred to the OR gate 7. As a result, the "CALL" instruction is executed together with a setting of the flip-flop 81. As described above, according to the present invention, since control signal or signals can be generated from the address data produced by the program counter, a change in the memory capacity of the program memory and in the instruction form are not required. Moreover, two instructions are executed simultaneously, and hence the high speed data processing is carried out. Even if the content of the program memory is read-out to reproduce the program, the reproduced program does not perform the complete processing operations by itself without the circuit configuration according to the present invention, so that the protection of a program can be attained in consequence. The present invention is not limited to the above embodiments, but may be changed and modified. For example, two or more second control signals can be generated in response to two or more specific address data from the program counter, respectively.

Claims: A data processor comprising a program memory (1) storing a plurality of instructions at respective memory locations thereof, a program counter (3) producing address data (9) whose content is changed in a predetermined order, address decoder means (2) responsive to said address data for producing an access signal (11) for making access to one memory location of said program memory (1), instruction decoder means (5) responsive to the instruction read out from the memory location accessed by said access signal (11) for producing a set of first control signals (15,16,17,19-21), and execution means (30) for executing the instruction in response to the set of first control signals, wherein said processor further comprises producing means (6) responsive to said address data (9) for producing a second control signal (14) independently of said set of first control signals when said address data (9) takes a predetermined content, and wherein said execution means (30) further executes another instruction in response to said second control signal in the same instruction execution cycle as the instruction responsive to the set of first control signals. The data processor as claimed in claim 1, characterized in that said producing means includes a control signal generation circuit detecting that said address data takes said predetermined content to produce said second control signal (14). The data processor as claimed in claim 1, characterized in that said producing means includes a control signal generation circuit responsive to said access signal (11) for producing said second control signal (14).

Inventors: ONO KAZUHIKO, ONO, KAZUHIKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G06F9
IPC codes: G06F15, G06F9, G06F21