Data processing device

Abstract: A data processing device having a buffer (3) for prefetching a plurality of instructions, the buffer (3) is constructed by including two switching areas (A, B) enabling a switching and one common area (C) connecting to one of the two switching areas (A, B), as unconnected switching area of the two switching areas (B, A) is used exclusively for prefetching a destination instruction of a conditional jump instruction, so that the destination instruction is prefetched to the unconnected switching area (B, A) by a switching operation, and thus flexibility is increased, when the jump instructions are continued. Further, a number of prefetching destination instructions is determined so that a bottleneck in an instruction process is avoided, and thus the capacity of the two switching areas (A, B) is reduced the hard ware scale is not enlarged.

Description: The present invention relates to a data processing device, more particularly, to a data processing device using an instruction prefetch system. The processing speed of a data processing device, e.g., a microprocessor unit, has become much higher due to the use of pipeline processing, etc. In the pipeline process, however, a plurality of processes are carried out in parallel, and therefore, the speed is too slow to enable the data processing device to successively fetch instructions one by one from a storage portion by one process. To solve this problem, "an instruction prefetch" is carried out, to increase the processing speed and thus avoid a bottleneck in the processing of instructions. In the instruction prefetch, a plurality of continuous instructions are read from an external memory and stored in an internal instruction buffer, and an instruction to be processed is fetched from the buffer when necessary. Note, in the processing by the data processing device, usually the continuous instructions are successively carried out in accordance with the address numbers thereof, but in a different kind of processing, a conditional branch processing is carried out. Namely, in the conditional branch processing, a condition of a conditional jump instruction is discriminated, and another instruction at another address is carried out when the condition of the conditional jump instruction is fulfilled. In such a conditional branch processing, an instruction to be carried out cannot be stored in the buffer by a discriminated result of the conditional jump instruction, and therefore, in this case, the instruction must be fetched again from the external memory, and thus a bottleneck in the instruction processing occurs during the time required for this fetch and the processing speed is lowered. The conventional methods of conditional branch processing are indicated, for example, as follows: (I) When a condition of a conditional jump instruction is not fulfilled by a discriminated result of the condition thereof, a next instruction is carried out. When the condition is fulfilled , a prefetch instruction buffer is cleared and a destination instruction (branch-target instruction) of the conditional jump instruction is read from a memory and prefetched into the instruction buffer. (II) A first prefetch instruction buffer and a second prefetch instruction buffer having the same capacities are provided, and in a normal state, one of the instruction buffers (for example, the first buffer) is used. When a conditional jump instruction is detected, a destination instruction is read from a memory and is stored to the second prefetch instruction buffer, and when a discriminated result of the condition thereof indicates a branch condition, the second prefetch instruction buffer is selected and the first prefetch instruction buffer is cleared. Conversely, when a discriminated result of the condition of the conditional jump instruction does not indicate a branch condition, the first prefetch instruction buffer is selected and the second prefetch instruction buffer is cleared. (III) Furthermore, in the above case (II), one of the buffers is used as an exclusive prefetch instruction buffer and the capacity thereof is kept to a minimum, so that a hardware scale thereof is kept small. In the case of (I), when the discriminated result of the condition of the conditional jump instruction is a branch condition, in this method the buffer must be cleared and a destination instruction read, and thus it is difficult for this method to avoid a bottleneck in the instruction processing. Next, in the case of (II), a bottleneck in an instruction processing can be avoided, but another problem arises in that two buffers having the same capacities must be provided, and thus the hardware scale thereof becomes very large. On the other hand, in the case of (III), a bottleneck in an instruction processing can be avoided, and a hardware scale thereof kept to a minimum, since the capacity of the exclusive prefetch instruction buffer is determined by a destination instruction. Nevertheless, in this case (III), when conditional jump instructions are continued, for example, a condition of a first conditional jump instruction is fulfilled and a second conditional jump instruction appears, and just after instructions of the second conditional jump instruction are stored in the exclusive prefetch instruction buffer, it is difficult for this method to flexibly carry out these instructions. For example, if a condition of the second conditional jump instruction is not fulfilled, the instructions just after the second conditional jump instruction should not be cleared, whereby the exclusive prefetch instruction buffer is not cleared and a destination instruction of the second conditional jump instruction cannot be fetched into the exclusive prefetch instruction buffer. Therefore, in this method the instructions from the exclusive prefetch instruction buffer must be transferred to a normal buffer, and thus it is difficult in this method to avoid a bottleneck in an instruction processing. Furthermore, a branch instruction control system is provided for reducing the quantity of hardware, to decrease the delay and to realize a high-speed machine cycle by carrying out the prefetch control for a destination instruction while a branch instruction is being processed, as disclosed in Japanese Unexamined patent Publication No. 60-117336. But, in this Japanese Patent Publication No. 60-117336, instructions read from an instruction memory means, e.g., a main memory or a instruction cache memory, are momentarily stored to a plurality of instruction word registers (IWR), the instruction word registers are connected directly to a multiplexer (MPX) and to the input of a plurality of instruction buffer registers (IBR), and the instructions stored in the IWR and IBR are selected by the MPX and applied to a pipeline system. In this branch instruction control system, however, the instructions are not written and read by using a write pointer and a read pointer as a register file configuration, but are written or read by using a shift register configuration. Therefore, the quantity of hardware in this branch instruction control system cannot be less than that needed when using a register file configuration. In consideration of the above-mentioned problems, it is desirable to provide a data processing device for carrying out instructions with flexibility and without large scale hardware, when conditional jump instructions are carried out. US-A-3 614 747 discloses a data processing device having the features of the preamble of claim 1. According to the present invention, there is provided a data processing device comprising: a buffer, for storing instructions fetched from a memory, said buffer having at least a first area and a second area; a decoder means, connected to said buffer, for receiving and decoding said instructions stored in said buffer; and a control means, connected to said buffer and said decoder means, for controlling the areas of said buffer; characterised in that said buffer has a common area in addition to said first and second areas, and in that said control means controls a combination of said first, second and common areas such that said common area is combined with one of the first and second areas to form a combined area for storing continuous instructions fetched from the memory; wherein when a conditional jump instruction is detected, a destination instruction corresponding to said conditional jump instruction is stored into the other of said first and second areas; and when a condition of said conditional jump instruction is fulfilled, the other of said first and second areas is combined with said common area to re-form the combined area. Thus, in the present invention, in the buffer portion, one of the two switching areas is combined with the common area and the instructions from the memory are prefetched to the combined area, during a normal state for carrying out continuous instructions. On the other hand, when a conditional jump instruction (for example, a Branch on Condition Code: Bcc instruction) is detected, the destination instruction read from the memory to the other switching area which is not combined with the common area is prefetched. Further, when a branch condition of a conditional jump instruction is fulfilled, the instructions prefetched in the one of the two switching areas and the common area which form the combined area are invalidated, and the other of the two switching areas of an unconnected area is combined with the common area. Consequently, a destination instruction is prefetched in accordance with a detection of a conditional jump instruction and the branch instruction is carried out when a branch condition of the conditional jump instruction is fulfilled. Further, (since) a prefetched instruction in the one switching area which is released from the common area is invalid, the one switching area becomes a new area for storing a new destination instruction. Therefore, the instructions are carried out with flexibility when conditional jump instructions are continued (processed). Furthermore, the capacity of the each switching area is determined so that a bottleneck in an instruction processing is avoided, and is suitable for a number of destination instructions, so that the capacity of the buffer is not enlarged and a hardware scale is made small. The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: Figure 1 is a block diagram illustrating an embodiment of a data processing device according to the present invention; Fig. 2 is a circuit diagram illustrating an example of a write pointer portion shown in Fig. 1; Fig. 3 is a circuit diagram illustrating an example of a read pointer portion shown in Fig. 1; Fig. 4 is a conceptual drawing explaining a mode of operation thereof; Fig. 5 is a block diagram explaining examples of a normal instruction sequence including a branch on condition code instruction and a destination instruction sequence of the branch condition code instruction in a memory portion; Fig. 6 is a block diagram explaining the case wherein the branch on condition code instruction is not realized; and Fig. 7 is a block diagram explaining the case wherein the branch on condition code instruction is realized. An embodiment of a data processing device according to the present invention will be explained in detail with reference to the drawings. Figure 1 is a block diagram illustrating an embodiment of a data processing device according to the present invention. First, the construction of the present example will be explained. A microprocessor unit 1 comprises a memory interface 2, an instruction prefetch buffer 3, a write pointer portion 4, a read pointer portion 5, an instruction decoder 6, a running portion 7, an instruction prefetch control portion 8, and an address counter 9. The memory interface 2 is connected to a memory M, such as an external memory or a cache memory, wherein instructions are stored in accordance with an address number. When an instruction fetch control signal S 1 from the control portion 8, described below, is input to the memory interface 2, reference is made to an address counter value Ac of the address counter 9, described below, and an instruction at a specific address indicated by the counter value Ac is fetched and transferred to a data bus. The instruction prefetch buffer portion 3 has a plurality of storage areas (in this embodiment, six storage areas) IB0 - IB5, and these areas are divided into three areas. Namely, a switching area (A) is formed by the storage areas IB0 and IB1, a switching area (B) is formed by the storage areas IB4 and IB5, and a common area (C) is formed by the storage areas IB3 and IB4. Each of the storage areas IB0 - IB5 has, for example, an 8-byte configuration and a valid bit. The switching area (A) of the storage areas IB0 and IB1, the switching area (B) of the storage areas IB4 and IB5, and the common area (C) of the storage areas IB2 and IB3 are connected or combined in accordance with a most significant bit of each pointer value Wp, Rp of the write pointer portion 4 or the read pointer portion 5. Namely, the common area (C) is connected to the switching area (A) or the switching area (B), when the common area (C) is connected to the switching area (A), connected (combined) area are formed by the common area (C) and the switching area (A), and an unconnected (uncombined) area is formed by the switching area (B). In a normal state, instructions from the memory M are prefetched to the connected areas of the common area (C) and the switching area (A). In the instruction decoder portion 6, described below, when a conditional jump instruction, for example, a Bcc instruction, (hereinafter, called a Bcc instruction) is detected, a destination instruction is fetched from the memory M in accordance with a counter value Ac indicated by the Bcc instruction and is written to the unconnected area (B). Namely, many instructions which include the above destination instruction are prefetched to the unconnected area of the switching areas (B). Conversely, if the common area (C) is connected to the switching area (B), the connected areas are formed by the common area (C) and the switching area (B), and the unconnected area is formed by the switching area (A). In a normal state, instructions from the memory M are prefetched to the connected areas of the common area (C) and the switching area (B). When a Bcc instruction is detected by the instruction decoder portion 6, a destination instruction is prefetched to the unconnected area of the switching areas (A). The write pointer portion 4 comprises a write pointer 10 formed by a plurality of bits (in this embodiment, three bits are used, and hereinafter, this embodiment is explained by these three bits), a bit save register 11 having bits corresponding to low order bits (in this embodiment, two low order bits are used, and hereinafter, this embodiment is explained by these two bits), and an inverter 12 for inverting a most significant bit of the write pointer 10, if necessary. The write pointer portion 4 designates the connected areas formed by the common area (C) and the switching area (A) or the common area (C) and the switching area (B). Namely, the write pointer 10 of the write pointer portion 4 changes the values of the two low order bits of the three bits "0 0", "0 1", "1 0", "1 1" or "1 1" to "0 0", cyclically as a wraparound, in accordance with a control signal S 2 from the instruction prefetch control portion 8. Note, the most significant bit of the write pointer 10 is used for switching the above switching areas (A) and (B) to the common area (C) of the buffer portion 3. For example, when the most significant bit of the write pointer 10 is "0", the switching area (A) is connected to the common area (C). Therefore, the instructions fetched from the memory M are written to the switching are a (A) and the common area (C), i.e., the instructions fetched from the memory M are written to a designated storage area of the storage areas IB0 - IB3 in accordance with the two low order bits of the write pointer 10. Further, the write pointer 10 designates one of the storage areas IB0 - IB3 of the connected areas (A) and (C), and the instructions from the memory M are prefetched to the designated storage area of the connected areas (A) and (C), in a normal state. When a conditional jump instruction is detected by the instruction decoder portion 6, the write pointer 10 designates a storage area IB4 or IB5 of the unconnected area (B) and a destination instruction of the conditional jump instruction is prefetched from the memory M to the designated storage area IB4 or IB5 of the unconnected area (B). Conversely, when the most significant bit of the write pointer 10 is "1", the switching area (B) is connected to the common area (C), the storage areas IB2 - IB5 of the connected areas are designated successively, and the instructions read out from the memory M are prefetched to the designated storage area of the connected areas (B) and (C), in a normal state. when a conditional jump instruction is detected by the instruction decoder 6, the write pointer 10 designates a storage area IB0 or IB1 of the unconnected area (A), and a destination instruction of the conditional jump instruction is prefetched from the memory M to the designated storage area IB0 or IB1 of the unconnected area (A). Figure 2 is a circuit diagram illustrating an example of the write pointer portion 4 shown in Fig. 1. As shown in Fig. 2, the write pointer portion 4 is constructed, for example, by a plurality of logic gate circuits, an adder INC, and five D-type flip-flop circuits. The write pointer 10 includes the logic gate circuits operated by the signals below, and three D-type flip-flop circuits for outputting three bits of the write pointer. The signals applied to the write pointer 10 are, for example, a BCC signal indicating a branch on condition instruction, a BRA signal indicating a branch always instruction, a RESET signal for resetting the bits of the write pointer 10, and a BRFAIL signal indicating that the branch condition is not fulfilled. Further, a CLK signal is applied to each clock terminal CLK of the flip-flop circuits. The bit save register 11 includes two D-type flip-flop circuits for saving the two low order bits of the three bits. The adder INC is used for increasing the two low order bits of the three bits by +1. When a Bcc instruction is detected and a destination instruction is fetched, the BCC signal is made ON, the most significant bit WP2 is inverted, and the two low order bits WP1, WP0 are cleared. At the same time, the two low order bits WP1, WP0 are stored in the bit save register 11 of the two D-type flip-flop circuits, to save the contents of the two low order bits if the branch condition is not fulfilled. When the branch condition of the Bcc instruction is not fulfilled, the BRFAIL signal is made ON, the most significant bit WP2 is inverted, and the two low order bits WP1, WP0 are copied from the contents of the bit save register 11. When the Bcc instructions are continued and both the BRFAIL signal and the BCC signal are made ON at the same time, the most significant bit WP2 is not inverted, and the two low order bits WP1, WP0 are cleared. When a BRA instruction is detected, all three bits WP2, WP1, WP0 are cleared. A WPINC signal is made ON and the two low order bits WP1, WP0 are incremented by +1, when a write process for one storage area IB0 - IB5 in the buffer portion 3 is carried out. Note, Table 1 indicates the relationships between a pointer value Wp of the write pointer 10 and the storage areas IB0 - IB5. Note, the content of Table 1 can be applied to a pointer value Rp of the read pointer 13. POINTER VALUE Wp, Rp OF WRITE POINTER AND READ POINTER AREA DESIGNATED BY POINTER VALUE AREA MOST SIGNIFICANT BIT TWO ORDER LOW BITS 0 0 IB0 (A) 0 1 IB1 0 1 0 IB2 (C) 1 1 IB3 0 0 IB4 (B) 0 1 IB5 1 1 0 IB2 (C) 1 1 IB3 Next, when the Bcc instruction is detected by the instruction decoder portion 6, described below, the two low order bits of the write pointer 10 are saved to the bit save register 11, and then the two low order bits of the write pointer 10 are cleared by writing "0" and the most significant bit thereof is inverted. For example, when the most significant bit before inversion is "0", one area of the switching area (A) and the common area (C) is designated, a storage area IB4 of the unconnected switching area (B) is first designated in accordance with the inversion of the most significant bit (for example, "0" - "1" and the clearing of the two low order bits. Next, the two low order bits are incremented by +1, so that the next storage area IB5 is designated. Therefore, when the Bcc instruction is detected, two words of destination instructions, for example, are prefetched into the storage areas IB4 and IB5. Note, when the most significant bit is "0", the two destination instructions are prefetched into the storage areas IB0 and IB1. The read pointer portion 5 has almost the same configuration as the above described write pointer portion 4, except that the bit save register 11 is not provided at the read pointer portion 5. Namely, the read pointer portion 5 comprises a read pointer 13 formed by a three bits configuration, and an inverter 14 for inverting a most significant bit of the read pointer 13, if necessary. A read area of the instruction prefetch buffer portion 3 is designated in accordance with a pointer value Rp of the pointer 13. The pointer value Rp of the two low order bits is cyclically changed as a wraparound in accordance with a control signal S 3 from the instruction prefetch control portion 8, and the most significant bit thereof is inverted, if necessary. Figure 3 is a circuit diagram illustrating an example of the read pointer portion 5 shown in Fig. 1. As shown in Fig. 3, the read pointer portion 5 is constructed, for example, by a plurality of logic gate circuits, an adder INC, and three D-type flip-flop circuits. The read pointer 13 includes the logic gate circuits for operating the signals below, and three D-type flip-flop circuits for outputting three bits of the read pointer. The signals applied to the read pointer 13 are, for example, a BRSUC signal indicating a fulfillment of the branch condition, a BRA signal indicating a branch always instruction, and a RESET signal for resetting the bits of the read pointer 13. Further, a CLK signal is applied to each clock terminal CLK of the flip-flop circuits. The read pointer portion 5 does not include the bit save register provided for the write pointer portion 4. The adder INC is used for increasing the two low order bits of the three bits by +1. When the branch condition of the Bcc instruction is fulfilled, the BRSUC signal is made ON, the most significant bit RP2 is inverted, and the two low order bits RP1, RP0 are cleared. In the case of a BRA instruction, all three bits RP2, RP1, RP0 are cleared. An RPINC signal is made ON and the two low order bits RP1, RP0 are incremented by +1, when all of the content of one storage area IB0 - IB5 in the buffer portion 3 is read out. In the instruction decoder 6, an instruction is read out from the instruction prefetch buffer 3 by a designation of the pointer 13 and is decoded, and the result is sent to the running portion 7. When the instruction read out from the instruction prefetch buffer portion 3 is a Bcc instruction, a command for a discriminate processing of a branch condition is output to the running portion 7, and a branch instruction detect signal S 4 indicating a branch instruction is output to the instruction prefetch control portion 8. In the running portion 7, various processes are carried out in accordance with a notification from the instruction decoder 6, and when the command for the discriminate processing is input, a discrimination of whether or not the branch condition is fulfilled is carried out and a decision signal S 5 indicating a result of the discrimination is output to the instruction prefetch control portion 8. Generally, the instruction prefetch control portion 8 monitors the existence or non-existence of an empty area by determining a difference between a pointer value Wp of the write pointer 10 and a pointer value Rp of the read pointer 13. When an empty area exists, an instruction fetch signal S 1 and a control signal S 6 are output, and an instruction from the memory M is prefetched to the empty area. Further, when a branch instruction detect signal S 4 from the instruction decoder 6 is input, the write pointer portion 4 is controlled and a write area of the instruction prefetch buffer 3 is switched and connected to the switching area (A) or (B) which is not connected to the common area (C), and a destination instruction formed, for example, by two words, is stored to the switched areas. Note, a pointer value Rp of the read pointer 13 is maintained and the connected areas of the buffer portion 3 are designated to a read side, until a discriminate signal S 5 is input from the running portion 7, i.e., a result of a discrimination of the conditions is input. Therefore, a destination instruction is not read from the buffer portion 3 until the discriminate signal S 5 is input. When the discriminate signal S 5 is input, and this discriminate signal S 5 indicates that the branch condition has been fulfilled, the control signal S 3 is output, the most significant bit is inverted, and the two low order bits are cleared, and the switching area (A) or (B) where the destination instruction is stored is designated to the read side. Consequently, when the branch condition is fulfilled, the destination instruction is fetched to the instruction decoder 6, and a branch processing is carried out. The address counter portion 9 comprises an address register 15 and an address save register 16, and a register value of the address register is output as an address counter value Ac of the address register 15. Further, in the address register 15, a register value is updated in accordance with a control signal S 6 from the instruction prefetch control portion 8, and a register value is also updated to a value indicted by a destination branch address signal As, when the destination branch address signal As is input. Note, a register value before updating is saved to the address save register 16 and the previous register value is returned to the address register 15 when the branch condition is not fulfilled. Next, a mode of operation is explained. First, a concept of the operation is explained with reference to Fig. 4. Generally, a prefetch of an instruction is divided into two cases; one using a continuous instruction processing and the other using a branch instruction (which includes a conditional jump instruction and a unconditional jump instruction). A normal continuous processing instruction is, for example, prefetched to a connection relationship of a switching area (A) and a common area (C) as shown in state 1. When a branch instruction is detected during a continuous processing, the destination instruction is prefetched to a switching area (B) which is not related to the connection relationship. When a connection relationship as shown in state 2 is established, the above switching areas (A) and (B) are changed. When the detected branch instruction is a conditional jump instruction, the condition thereof is discriminated to determine whether or not the condition is fulfilled, and when the condition is not fulfilled, the continuous instructions are carried out in keeping with the connection relationship of the state 1 or 2. On the other hand, when the condition is fulfilled, the connection relationship is changed and a new connection relationship is established, that is, the switching area (A) or the switching area (B) to which the destination instruction has been prefetched is connected to the common area (C) and carries out the destination instruction now considered to be a continuous instruction. The above description indicates that the state 1 is changed to the state 2 when the condition is fulfilled. As a result, the unconnected switching area (A) or (B) is then used for prefetching a destination instruction, and if branch instructions are continued, the instructions can be flexibly carried out. Furthermore, the capacity of each of the switching areas (A) and (B) can be small enough to allow a fetch of the destination instruction (for example, 2 words) without generating a bottleneck in the processing, and thus the total capacity of the buffer 3 is not increased. Next, an operation of this embodiment is described. First, a prefetch of a normal instruction processing not accompanied by a branch instruction will be explained. Note, in the instruction prefetch buffer 3, at this stage, the switching portion (A) is connected to the common portion (C) and instructions are prefetched to the storage area IB0 only. Therefore, a present pointer value Wp of the write pointer 10 indicates Wp = 001, and if an instruction of the IB0 is not read, a pointer value Rp of the read pointer 13 indicates Rp = 000. In this state, an instruction designated by the read pointer value Rp of the storage area IB0 is read by the instruction decoder 6, and the read instruction is decoded. As a result, when the instruction is a normal instruction not accompanied by a branch instruction, the running portion 7 carries out a specific processing in accordance with the decoded result of the instruction. Empty areas of the instruction prefetch buffer 3 (in this case, the storage areas IB1 - IB3 are empty) are confirmed by the instruction prefetch control portion 8 in accordance with a difference between the write pointer value Wp and the read pointer value Rp, an address control signal S 6 is output to the address register 15, and an address counter value Ac is incremented by +1, so that instructions are prefetched to the empty areas. As described above, an instruction designated by an address of the address counter value Ac is fetched from the memory M by the memory interface 2, and the fetched instruction is transferred to the instruction prefetch buffer 3 through a data bus. The transferred instruction is prefetched to the storage area IB1 in accordance with the write pointer value Wp = 001. When a prefetch of the instruction to the storage area IB1 is completed, an increment of the write pointer value Wp and a count up of the read pointer value Rp is carried out, and a plurality of instructions are prefetched to the storage area IB0 - IB3 of the connected switching area (A) and the common area (C) in the instruction prefetch buffer 3. Further, the prefetched instruction is successively read from the storage areas IB0 - IB3 to the instruction decoder 6, and a new instruction is prefetched to an empty area produced by the reading process. On the other hand, when a Bcc instruction is detected by the instruction decoder 6, a present write pointer value Wp is saved to the bit save register 11 and an address counter value Ac is saved to the address save register 16. The address counter value Ac is renewed by a destination branch address signal As, the most significant bit of the write pointer 12 is inverted, the two low order bits are cleared, and an unconnected area is designated for prefetching by the write pointer value Wp. Consequently, a destination instruction is prefetched to the unconnected switching area (B). In this case, a discrimination result of the condition in the destination instruction is not produced, the read pointer value Rp is maintained as the same value, and a read side area is designated to a connecting side. Figure 5 is a block diagram explaining examples of a normality instruction sequence including a branch on condition code instruction and a destination instruction sequence of the branch on condition code instruction in a memory. In Fig. 5, references S0 - S3 and T1 - T3 denote address counter values which correspond to one cycle of the pipeline system, and references P, Bcc, N1 - N5, and B1 - B5 denote instructions. The counter values S0 - S3 are in a normal prefetch cycle, i.e., these instructions P, Bcc and N1 - N5 are continuous instructions and these continuous instructions are carried out successively in accordance with the address numbers thereof when a branch condition of the Bcc instruction is not fulfilled. Conversely, the counter values T1 - T3 are in a branch prefetch cycle, and a destination instruction of the Bcc instruction and continuous instructions thereof are included in the cycle T1, i.e., the instruction B1 corresponds to the destination instruction of the Bcc instruction and these instructions B2 - B4 are continuous instructions, and these continuous instructions are carried out successively when a branch condition of the Bcc instruction is fulfilled. Note, the above instructions P, Bcc, N1 - N5, and B1 - B5 are variable length instructions, and thus each of the instructions may not be prefetched in the same cycle or to one storage area IB0 - IB5 . For example, the instruction N3 is divided into two cycles S1 and S2, i.e., a front portion of the instruction N3 is prefetched to one storage area and a rear portion of the instruction N3 is prefetched to the other storage area. Next, the case of a detection of a Bcc instruction is explained with reference to Figs. 6 and 7. When a branch condition of a Bcc instruction is not fulfilled. The destination branch address signal As is returned by a register value saved in the address save register 16, and the write pointer value Wp is also returned by a value of the save register 11. Therefore, in the post-prefetch processes, the connecting side switching area (A) and the common area (C) are used, i.e., the processing state is returned to a normal state of carrying out continuous instructions. Figure 6 is a block diagram explaining the case wherein a condition of the branch on condition code instruction is not fulfilled. As shown in Fig. 6, in a first cycle of a first step in a five step pipeline system the instruction P is decoded (DC), in a second cycle of the first step an effective address is calculated (AC), and in a third cycle of the first step an operand of the instruction P is fetched (OF). Further, in a fourth cycle of the first step an operation of the instruction P is executed (EX), and in a fifth cycle of the first step the operand of the instruction P is written and a condition codes are generated (OW). In a first cycle of a second step, which corresponds to the second cycle of the first step, for example, the Bcc instruction is decoded (DC). In a second cycle of the second step an effective address is calculated (AC), and in a third cycle of the second step a destination instruction of the Bcc instruction is fetched (IF). Further, in a fourth cycle of the second step a branch condition of the Bcc instruction is checked or discriminated (CHK). Note, in the first and second cycles (DC, AC) of the second step, which correspond to the second and the third cycles (AC, OF) of the first step in a five step pipeline system, address counter values are indicated as S1 and S2 in the normal prefetch cycle, and in the third and fourth cycles (IF, CHK) of the second step, which correspond to the fourth and fifth cycles (EX, OW) of the first step in a five step pipeline system, address counter values are indicated as Tl and T2 in the branch prefetch cycle. Further, in the fifth cycle of the second step, which corresponds to a fourth cycle (EX) of the third step in a five step pipeline system, an address counter value is indicated as S3 in the normal prefetch cycle, since a branch condition of the Bcc instruction is not fulfilled. In this case, the write pointer 10 designates the storage areas IB0, IB1, IB2, IB4, IB5 and IB3 by the two low order bits thereof, i.e., the write pointer 10 designates the connected storage areas IB0, IB1 and IB2 until the third cycle (IF) of the second step, the write pointer 10 then designates the unconnected storage area IB4 and IB5 in order to prefetch a destination instruction of the Bcc instruction, and then the write pointer 10 designates the connected storage area IB3, since the branch condition of the Bcc instruction is not fulfilled. Therefore, in the second cycle (AC) of the first step, an instruction N2 and a front portion of an instruction N3 are prefetched from the memory M to the storage area IB1 by designation of the write pointer 10. Similarly, in the third cycle (OF) of the first step corresponding to the second cycle (AC) of the second step, a rear portion of the instruction N3, an instruction N4, and a front portion of an instruction N5 are prefetched from the memory M to the storage area IB2 by the designation of the write pointer 10. Next, in the fourth cycle (EX) of the first step corresponding to the third cycle (IF) of the second step, a destination instruction B1 is prefetched from the memory M to the storage area IB4, which is an unconnected storage area. In the fifth cycle (OW) of the first step corresponding to the fourth cycle (CHK) of the second step, an instruction B2 and an instruction B3 are prefetched from the Memory M to the storage area IB5 . However, after the fourth cycle (CHK) of the second step, the storage area IB4 and IB5 are invalidated, since the branch condition of the Bcc instruction is not fulfilled. Further, in the fifth cycle of the second step corresponding to a fourth cycle (EX) of a third step and a fifth cycle of the third step, a rear portion of the instruction N5 is prefetched from the memory M to the storage area IB3, which is a connected storage area, since the branch condition of the Bcc instruction is not fulfilled. In the above description, in the first cycle (DC) of the second step, the read pointer 13 designates an instruction start position of the connected storage area IB0 (0, 1), and in the second, third fourth and fifth cycles of the second step, the read pointer 13 designates instruction start positions of the connected storage areas (0, 3), (1, 0), (1, 2) and (1, 4), respectively. Note, the read pointer 13 does not designate a start position of the unconnected storage areas IB4 and IB5 , since the branch condition of the Bcc instruction is not fulfilled. When a branch condition of a Bcc instruction is fulfilled . The most significant bit of the read pointer value Rp is inverted, and a read area is switched to the side for a prefetch of the destination instruction. Therefore, an instruction of the destination branch is read to the instruction decoder 6, so that a branch processing is carried out. The next continuous instruction is prefetched to the switching area (B) and the common area (C), which are now in a connected relationship, and the previous prefetched instructions of these areas become invalid. Further, the switching area (A) which is now unconnected is secured for prefetching future destination instructions, and thus if the Bcc instruction are continued, the destination instruction is prefetched to the switching area (A) of the unconnected side, so that it can be flexibly corresponded when the continuous Bcc instructions are detected. Furthermore, a capacity of each of the switching area (A) or the switching area (B) is determined such that a bottleneck in an instruction processing is avoided, and is suitable for a number of destination instructions, so that a total capacity of the instruction prefetch buffer 3 is not enlarged and the hardware scale is reduced. Note, when an unconditional jump instruction such as a BRA instruction is detected by the instruction decoder 6, a destination branch address signal As is loaded to the address register 15 and an address counter value Ac is updated. Further, in the case of the unconditional jump instruction, the connecting switching areas (A) or (B) and the common area (C) can be designated for prefetching a destination instruction by clearing the write pointer value Wp and read pointer value RP. Figure 7 is a block diagram explaining the case wherein, the branch on condition code instruction is fulfilled. As shown in Fig. 7, the first to fifth cycles of the first step and the first to fourth cycles of the second step are the same as that of Fig. 6. In a first cycle of a second step, which corresponds to the second cycle of the first step, the Bcc instruction is decoded (DC), in a second cycle of the second step an effective address is calculated (AC), and in a third cycle of the second step a destination instruction of the Bcc instruction is fetched (IF). Further, in a fourth cycle of the second step a branch condition of the Bcc instruction is checked or discriminated (CHK). Note, in the first and second cycles (DC, AC) of the second step, which correspond to the second and the third cycles (AC, OF) of the first step in a five step pipeline system, address counter values are indicated as S1 and S2 in the normal prefetch cycle, and in the third and fourth cycles (IF, CHK) of the second step, which correspond to the fourth and fifth cycles (EX, OW) of the first step in a five step pipeline system, address counter values are indicated as T1 and T2 in the branch prefetch cycle. Further, in the fifth cycle of the second step which corresponds to a fourth cycle (EX) of the third step in a five step pipeline system, an address counter value is indicated as T3 in the normal prefetch cycle, since a branch condition of the Bcc instruction is fulfilled. In this case, the write pointer 10 designates the storage areas IB0, IB1, IB2, IB4, IB5 and IB2 by the two low order bits thereof, i.e., the write pointer 10 designates the connected storage areas IB0, IB1 and IB2 until the third cycle (IF) of the second step, the write pointer 10 then designates the unconnected storage area IB4 and IB5 in order to prefetch a destination instruction of the Bcc instruction, and then the write pointer 10 designates a new connected storage area IB2, since the branch condition of the Bcc instruction is fulfilled. Note, the storage areas IB2 and IB3 of the common area (A) are newly connected to the storage areas IB4 and IB5 of the switching area (B) in accordance with the most significant bit of the write pointer 10. Therefore, in the second cycle (AC) of the first step, an instruction N2 and a front portion of an instruction N3 are prefetched from the memory M to the storage area IB1 by the designation of the write pointer 10, and similarly, in the third cycle (OF) of the first step corresponding to the second cycle (AC) of the second step, a rear portion of the instruction N3, an instruction N4, and a front portion of an instruction N5 are prefetched from the memory M to the storage area IB2 by the designation of the write pointer 10. Next, in the fourth cycle (EX) of the first step corresponding to the third cycle (IF) of the second step, a destination instruction B1 is prefetched from the memory M to the storage area IB4 which is an unconnected storage area in this cycle. In the fifth cycle (OW) of the first step corresponding to the fourth cycle (CHK) of the second step, an instruction B2 and an instruction B3 are prefetched from the memory M to the storage area IB5. Further, in the fifth cycle of the second step corresponding to a fourth cycle (EX) of a third step, the switching area (A) formed by the storage areas IB0 and IB1 is separated from the common area (C) formed by the storage areas IB2 and IB3, and the switching area (B) formed by the storage areas IB4 and IB5 is newly connected to the common area (C) in accordance with the most significant bit of the write pointer 10, since the branch condition of the Bcc instruction is fulfilled. In the above description, in the first cycle (DC) of the second step, the read pointer 13 designates an instruction start position of the connected storage area IB0 (0, 1), and in the second, third, fourth and fifth cycles of the second step, the read pointer 13 designates instruction start positions of the connected storage areas (0, 3), (1, 0), (1, 2) and (4, 1), respectively. Note, the read pointer 13 designates a start position of the newly connected storage areas IB4 and IB5 by inverting the most significant bit thereof, since the branch condition of the Bcc instruction is fulfilled. In this state, if a next Bcc instruction is detected, the above processes are carried out by inverting the switching area (A) of the storage area IB0 and IB2 to the switching area (B) of the storage IB4 and IB5 . In accordance with the present invention, a buffer is constructed by including two switching areas enabling a switching and one common area connected to one of the two switching areas, an unconnected switching area of the two switching areas is made exclusive for a prefetch of a destination instruction, so that destination instructions of jump instructions are prefetched to each of the two switching areas by switching, and thus flexibility is increased, when the jump instructions are C continued. Further, a number of prefetch destination instructions is determined so that a bottleneck in an instruction process is avoided, and thus the capacities of the two switching areas are reduced and the hardware scale is not enlarged.

Claims: A data processing device comprising: a buffer (3), for storing instructions fetched from a memory (M), said buffer (3) having at least a first area (A) and a second area (B); a decoder means (6), connected to said buffer (3), for receiving and decoding said instructions stored in said buffer (3); and a control means (4, 5, 8), connected to said buffer (3) and said decoder means (6), for controlling the areas of said buffer (3); characterised in that said buffer (3) has a common area (C) in addition to said first and second areas (A, B), and in that said control means controls a combination of said first, second and common areas (A, B, C) such that said common area (C) is combined with one of the first and second areas to form a combined area (A, C; B, C) for storing continuous instructions fetched from the memory (M); wherein when a conditional jump instruction is detected, a destination instruction corresponding to said conditional jump instruction is stored into the other of said first and second areas (B, A); and when a condition of said conditional jump instruction is fulfilled, the other of said first and second areas (B, A) is combined with said common area (C) to re-form the combined area. A data processing device according to claim 1, wherein said conditional jump instruction is a branch on condition code (Bcc) instruction. A data processing device according to claim 1, wherein said first and second areas (A, B) and said common area (C) are formed by a plurality of storage areas (IBO, IB1; IB4, IB5; IB2, IB3), and said first and second areas (A, B) have the same capacities. A data processing device according to claim 3, wherein said each storage area (IB0 - IB5) includes a valid bit, and when the instructions fetched from said memory (M) are written to a designated storage area (IB0 - IB5), the corresponding valid bit is set. A data processing device according to claim 3, wherein said each storage area (IB0 - IB5) includes a valid bit, and when the instructions prefetched from said memory (M) are read from a designated storage area (IB0 - IB5), the corresponding valid bit is cleared. A data processing device according to claim 1, wherein said control means includes a write pointer portion (4), connected to said buffer (3), for switching the combination of said first, second and common areas (A, B, C) and designating an area for writing the instructions fetched from said memory (M). A data processing device according to claim 6, wherein said write pointer portion (4) designates said combined area (A, C; B, C) in a normal state, and when a conditional jump instruction is detected, said write pointer portion (4) designates an uncombined area (B, A) formed by the other of said first and second areas (A, B) for writing thereto a destination instruction corresponding to said conditional jump instruction fetched from said memory (M). A data processing device according to claim 6, wherein said write pointer portion (4) comprises a write pointer (10) connected to said buffer (3) and formed by a plurality of bits, a bit save register (11) connected to said write pointer (10) for saving low order bits of said write pointer (10), and an inverting circuit (12) connected to said write pointer (10) for inverting a most significant bit of said write pointer (10). A data processing device according to claim 8, wherein the most significant bit of said write pointer (10) is used for switching a combination of said first, second and common areas (A, B, C), and the low order bits of said write pointer (10) are used for designating an area for writing the instructions fetched from said memory (M). A data processing device according to claim 1, wherein said control means includes a read pointer portion (5) connected to said buffer (3) for switching the combination of said first, second and common areas (A, B, C), and designating an area for reading the instructions therefrom. A data processing device according to claim 10, wherein said read pointer portion (5) designates said combined area (A, C; B, C) in a normal state; and when a conditional jump instruction is detected and a condition of said conditional jump instruction is fulfilled, said read pointer portion (5) designates an uncombined area (B, A) formed by the other of said first and second areas, for reading therefrom a destination instruction corresponding to said conditional jump instruction. A data processing device according to claim 10, wherein said read pointer portion (5) comprises a read pointer (13) connected to said buffer (3) and formed by a plurality of bits, and an inverting circuit (14) connected to said read pointer (13) for inverting a most significant bit of said read pointer (13). A data processing device according to claim 12, wherein a most significant bit of said read pointer (13) is used for switching a combination of said first, second and common areas (A, B, C), and low order bits of said read pointer (13) are used for designating said area for reading the instructions therefrom. A data processing device according to claims 8 and 12 combined, wherein said areas (A, B, C) are combined in accordance with a write pointer value (Wp) of said write pointer (10) and a read pointer value (Rp) of said read pointer (13).

Inventors: OHSHIMA TOSHIHARU, OHSHIMA, TOSHIHARU, OHSHIMA, TOSHIHARU C/O MR. AOKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G06F9
IPC codes: G06F9