ELECTRONIC TREMOLO DEVICE

Abstract: An electronic tremolo device for an electric guitar in which an actuator is mounted on the guitar so as to be manually adjusted by a musician playing the instrument. A control signal is produced which is representative of the position of the actuator, and an original audio signal produced by the guitar is processed on the basis of that control signal. The processed audio signal comprises at least one component the frequency of which is related to the frequency of the original audio signal and to the position of the actuator.

Description: ELECTRONIC TREMOLO DEVICE The present invention relates to an electronic tremolo device for an electric guitar. Electric guitars are known which incorporate a tremolo lever or arm movement of which stretches the guitar strings. If one of the strings is plucked the frequency of the signal which it generates can be adjusted by movement of the tremolo arm. The guitar may be played normally if the tremolo arm is left in a datum position to which it is returned by springs when released. The known tremolo devices have found wide acceptance but their use does cause problems as the tuning of the guitar strings tends to be adversely affected by repeated use of the tremolo arm. The effects obtained with tremolo devices are considered valuable and similar effects have been simulated in synthesizers of the type which are widely available. In a synthesizer rather than relying upon a signal derived directly from the string of a guitar the tremolo effect is obtained by appropriate processing of a signal originating in, for example, an electronic oscillator. Synthesizers are capable of providing substantially all tremolo effects which might be desired but such devices are expensive and cannot be easily used by musicians familiar only with conventional stringed guitars. It is an object of the present invention to provide an electronic tremolo device. According to the present invention there is provided an electronic tremelo device for an electric guitar, comprising an actuator for mounting on a guitar such that a musician playing the guitar can manually adjust the position of the actuator, means for producing a control signal representative of the position of the actuator, and means responsive to the control signal for processing an original audio signal produced by the guitar, the processing means producing a processed audio signal comprising at least one component the frequency of which is related to the frequency of the original audio signal and the position of the actuator. Thus,- in accordance with the present indention, a signal derived directly from the guitar strings is processed to produce an audio signal which can be substantially equivalent to that which would be obtained if the tension in the guitar string was adjusted. It is not necessary however to provide any mechanism for adjusting string tension and therefore the tuning of the guitar is not adversely affected. Furthermore, as to the musician the device is entirely analogous to a conventional tremolo arm it can be used by any musician familiar with guitars fitted with conventional tremolo arms. The processing means may produce more than one processed audio signal and the or one or more of the processed signals may be delivered to an appropriate amplifier either in isolation from the original audio signal produced by the guitar or after mixing with that original audio signal. A variety of effects can accordingly be obtained. The actuator may be a simple lever or arm the position of which is sensed by a potentiometer. Further effects may also be obtained by for example incorporating a switch which automatically produces a processed signal the frequency of which differs from the frequency of the original audio signal produced by the guitar by a predetermined amount, for example by one or more octaves. The processing means may comprise a first circuit which writes digital samples of the original audio signal to a memory, and a second circuit which reads stored digital samples from the memory to produce the processed audio signal, the actuator controlling the difference between the write and read rates to determine the frequency difference between the original and processed audio signals. Preferably, a clock circuit controls the first and second circuits, the clock circuit alternately enabling and disabling the first and second circuits such that when the first circuit is enabled the second circuit is disabled, and when the first circuit is disabled the second circuit is enabled. The first circuit writes digital samples to the memory in a predetermined address order, and the second circuit reads digital samples from the memory in the said predetermined address order, comprising means for preventing the reading of a digital sample from the memory address last written to immediately before or after the reading of a digital sample from the address first written to. The preventing means comprises means for detecting where the current read and write addresses are within a predetermined range of addresses from each other, means for identifying addresses to which the same digital samples have been written, and means responsive to the detecting means for advancing the current read address from one identified address to another to increase the said range. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block circuit diagram of a first embodiment of the present invention; Fig. 2 is a block circuit diagram of a second embodiment of the present invention; Fig. 3 illustrates the operation of read and write contention logic circuitry of the system of Fig. 2; and Fig. 4 illustrates the operation of circuitry intended to avoid "overtaking of current read and write addresses. Referring to Fig. 1, an audio input signal is applied to input 1, the audio signal appearing on input 1 (hereinafter referred to as the original audio signal) being derived from the strings of a guitar in an entirely conventional manner. Thus the original audio signal is identical to the signal which would be produced by an ordinary electric guitar not fitted with a conventional tremolo arm. The original audio signal is applied via a pre¬ amplifier 2 and a low pass filter 3 to a compressor 4 which delivers a "clean" analogue signal to a sample/ADC circuit 5. The compressor 4 provides at its output an analogue signal which retains the full shape and complexity of the waveform at its input but in which the high frequencies are attenuated and the overall voltage variation is reduced. The output of the sample/ADC circuit 5 is applied to a memory 6 controlled by a multiplexer- read/write select circuit 7. The multiplexer 7 controls the memory such that either data from the sample/ADC circuit 5 is written into the memory or data previously written into the memory is read out to a latch/DAC circuit 8. The speed at which data is read out may be the same as the speed at which it is written in if no tremolo effect is required or may be different in which case a tremolo effect is obtained. The output of the latch/DAC is an analogue representation of the digital signal read into the latch and is passed via a low pass filter 9, an expander 10 and a mixer pre-amp 11 to an audio output 12. The signal appearing at the audio output 12 is reproduced in a conventional manner. The original audio input applied to input 1 may be mixed with the processed audio signal in mixer/ pre-amp 11, the mixer being controllable by manual switches (not shown) so that either the signal at output 12 is either entirely made up of signals derived from the output of the latch/DAC 8, or entirely signals received directly from the input 1, or a mixture of the two. The multiplexer is controlled by a read clock 13 and a write clock 14 the frequencies of which are stabilized by phase locked loop 15 linked to the clocks by logic circuits 16. The frequency of the read clock 13 is also dependent upon the setting of a potentiometer 17 the setting of which is dependent upon the position of a tremolo arm (not shown) which can be manipulated by a person playing the guitar. A read address counter 18 is normally responsive to the output of the read clock 13 and controls the speed at which data stored in the memory 6 is read out to the latch/DAC circuit 8. A write address counter 19 is responsive to the output of the write clock 14 and controls the speed at which sampled information is read into the memory 6 from the sample/ADC circuit 5. Thus as the rate at which data is written to the memory 6 is proportional to the fixed output of the write clock 14 by manipulation of the tremolo arm the speed at which that data is read out and hence the frequency of the resultant audio signal can be controlled in a predictable manner. With the arrangement described above the frequency of the audio signals resulting from processing of data in the memory and associated circuits is dependent upon the -setting of the potentiometer 17. It may be desirable however to select a predetermined frequency change independent of the setting of the potentiometer 17 and for this purpose the octave select circuit 20 is provided. This enables an effect to be obtained which is equivalent to increasing the number of strings of the guitar by mixing processed signals .shifted in frequency by one octave with the original audio input signals. Frequency shifts of more than or less than one octave could be provided if desired. An external port 21 may also be provided to enable additional effects to be obtained. For example circuits providing "chorus" and "phase" effects. Furthermore the external port 21 could be used to deliver driving signals to a synthesizer or the like. Referring now to Fig. 2, this illustrates in block diagram form a preferred embodiment of the present invention. This avoids two particular problems associated with the embodiment of Fig. 1, these being related to read/write contention and read/write overtaking. The contention problem arises because of the variable read rate which means that read and write signals are asynchronous. It can happen that read and write operations will be attempted simultaneously with the result that data will be corrupted. The overtaking problem arises again because of the variable read rates. Assuming that the memory can store 2n samples in addresses 1 to 2n and samples are read into the memory in the order 1, 2 , 3 ....2n, 1, 2, 3 and so on, samples are read out in the same order. Assuming that at any one time the last address written to was addressed number n, then the samples in addresses n and n=l will not be directly related as they were taken in moments in time spaced apart by 2n multiplied by the sampling rate. If the n and n=l samples are read out sequentially an audible discontinuity will be heard unless by chance the two samples are the same or very similar. Such an effect will be apparent each time the current read address passes the current write address in either direction. Referring in detail to Fig. 2, an audio input 22 receives an analogue audio signal which is passed via a high pass filter 23 and preamplifier 24 to an ADC 25. The ditigal output of the ADC 25 is applied via a data bus 26 to a data memory 27. Data is read out from memory 27 via bus 26 to a DAC 28 and an external output port 29. The DAC output is applied via an amplifier 30 and a low pass filter 31 to a mixer 32. The mixer 32 also received the analogue output of the pre-amp 24 and provides an analogue output at terminal 33. Thusfar the system is very similar to that of Fig. 1. The control of the memory 27 is however different to overcome the contention and overtaking problems outlined above. A write clock 34 is the master clock for the system and operates at a stable frequency, for example 31.25kHz. To avoid over complication of Fig. 2 , all the connections between the clock 34 and other illustrated components are not shown. In particular, there are connections which are not shown between the clock 34 and the ADC 25, the clock 34 and read/write contention logic circuits 35 and 36 and the clock 34 and read/write contention logic circuits 37 and 38. The circuits 35 and 36 control memories 27, and the circuits 37 and 38 control a memory 39. The ADC samples the audio input at a fixed rate determined by the clock 34, and data is read out from the memory 27 at a rate determined by a read clock 40 the frequency of which is controllable by the user. The two rates may be the same or different. The circuits 35 and 36 are controlled by the clock 34 to effectively divide the operation of the memory 27 into "write only" time slots alternating with "read only" time slots as illustrated in Fig. 3. One read and one write operation typically occur in write clock period of 32 ps, that is a 16μs write period indicated by numeral 41 is followed by a 16 ps read period indicated by numeral 42. During a write time slot data is written to the memory, the data being written to the next memory address in a predetermined recirculating order. During each read time slot data is read out of the memory from the next address in the same predetermined order. This time " slot approach is a simple solution to the abovementioned contention problem as read and write operations cannot occur simultaneously. It does result however in data being read out in a discontinuous manner. These discontinuities are not perceivable to the human ear however and accordingly do not represent a problem. Referring now to Fig. 4, the abovementioned overtaking problem will be explained in greater detail-. The circular area represents the memory space of the memory 27 which typically would have 8192 addresses notionally divided into eight sections labelled 1 to 8 each of 1024 addresses. Each address receives a respective data sample, data being written to and read from the memory in a predetermined order one section at a time. The broken line 43 represents the progress of write operations through the memory, and the broken line 44 represents the progress of read operations through the memory. As is apparent from Fig. 3, these operations can proceed at different speeds and thus the spacing between the lines 43 and 44 is variable. If the read rate is faster than the write rate, the line 44 will eventually overtake line 43. If the read rate is slower than the write rate, the line 43 overtakes the line 44. When this occurs, data is read from consecutive addresses to which data has been written which results from the most recent write operation and the oldest write operation still recorded in the memory. This will generally result in a discontinuity the magnitude of which is usually sufficient to cause a perceivable "click" in the output. To overcome this problem, the system operates to detect an imminent risk of overtaking occuring, and to "jump" read operations through the memory between addresses storing similar data. The resultant discontinuity in read operations is not perceivable. In detail, a data zero detection logic circuit 45 detects each sample written to the memory 27 which represents a positive going zero voltage in the analogue input. The memory address to which this sample is written is determined by write address counter 46 and that address is loaded into a write address latch 47. The output of the circuit 45 clocks the data zero address via bus 48 into memory 39, the address being written into memory 39 only if the logic circuit 37 indicates a "write" time slot. The memory 39 provides eight address, each intended to store the address in memory 27 of the first data zero sample stored in a respective one of the eight sections of the memory 27. One possible spread of such addresses is indicated by the broken lines in Fig. 4. An address decode logic circuit 50 and a detection logic circuit 51 detect when data writing and reading operations enter a fresh section of the memory. When writing to a new section is detected, the address of the next data zero sample to be detected is written to the appropriate address in memory 39. When reading from a new section is detected, the current read and write addresses are compared. If reading is taking place from an address (the current read address) of a memory section which is not spaced from the memory section to which writing is taking place (the current write address) by at least two complete sections this is considered to represent a potential "overtaking" problem. Once a potential overtaking problem is detected, the system is set up to jump from its normal address reading order. The next data zero address from which reading will take place is loaded into latch 52 (the "jump" address) and that jump address is compared with the current read address by a comparator 53. The data zero address of the section four sections in advance of the current writing address is also loaded into latch 54 (the target address). In the example illustrated in Fig. 4, the jump address is the data zero address 49 of section 7, and the target address is the data zero address 49 of section 5. When reading reaches the jump address, the target address is downloaded from latch 52 to read address counter 54. The read address counter is normally clocked by read clock 40 at a rate selected by a first input 55 (key select) and a second pitch control input 56 (tremolo arm position). Downloading the target address causes the output of counter 54 to jump to the target address but then to continue being clocked by clock 40. As the jump and target addresses contain substantially the same data there is no perceivable effect. Accordingly overtaking is avoided without any audible side effects. The circuit of Fig. 2 can be implemented using conventional semiconductor chip components arranged in a variety of configurations.

Claims: CLAIMS 1. An electronic tremolo device for an electric guitar, comprising an actuator for mounting on a guitar such that a musician playing the guitar can manually adjust the position of the actuator, means for producing a control signal representative of the position of the actuator, and means responsive to the control signal for processing an original audio signal produced by the guitar, the processing means producing a processed audio signal comprising at least one component the frequency of which is related to the frequency of the original audio signal and the position of the actuator. 2. An electronic tremolo device according to claim 1, comprising means for selectively mixing the said original and processed signals. 3. An electronic tremolo device according to claim 1 or 2, wherein the actuator is a pivotally supported lever and a potentiometer controlled by the lever, the said control signal being related to the electrical resistance of the potentiometer. 4. An electronic tremolo device according to any preceding claim, comprising switch means actuable to produce a control signal which is effective to maintain a fixed frequency difference between the original and processed audio signals. 5. An electronic tremolo device according to any preceding claim, wherein the processing means comprises a first circuit which writes digital samples of the original audio signal to a memory, and a second circuit which reads stored digital samples from the memory to produce the processed audio signal, the actuator controlling the difference between the write and read rates to determine the frequency difference between the original and processed audio signals. 6. An electronic tremolo device according to claim 5, comprising a clock circuit which controls the first and second circuits, the clock circuit alternately enabling and disabling the first and second circuits such that when the first circuit is enabled the second circuit is disabled, and when the first circuit is disabled the second circuit is enabled. 7. An electronic tremolo device according to claim 5 or 6, wherein the first circuit writes digital samples to the memory in a predetermined address order, and the second circuit reads digital samples from the memory in the said predetermined address order, comprising means for preventing the reading of a digital sample from the memory address ' last written to immediately before or after the reading of a digital sample from the address first written to. 8. An electronic tremolo device according to claim 7, wherein the preventing means comprises means for detecting when the current read and write addresses are within a predetermined range of addresses from each other, means for identifying addresses to which the same digital samples have been written, and means responsive to the detecting means for advancing the current read address from one identified address to another to increase the said range. 9. An electronic tremolo device substantially as hereinbefore described with reference to the accompanying drawings.

Inventors: CAWSON JEREMY, HOOD RONALD JOHN, MOSS JACK WILLIAM, CAWSON, JEREMY, HOOD, RONALD, JOHN, MOSS, JACK, WILLIAM
Applicants: FLASHSTANDS LIMITED
Application year: 1988
Main classification: G10H3
IPC codes: G10H1, G10H3