IMPEDANCE MEASURING APPARATUS

Abstract: A digital sine-wave generating means (39), which includes at least one sine waveform memory (41), is read out by the output of a phase accumulator (32) to generate a first digital sine wave, a second digital sine wave and a digital cosine wave. The first digital sine wave is converted by a D-A converter (47) into an analog signal and then supplied to a measuring object (53). The output of the measuring object and the second digital sine wave are multiplied in a first multiplying type D-A converter (55), and the output of the measuring object and the digital cosine wave are multiplied in a second multiplying type D-A converter (56). The outputs of the first and second multiplying type D-A converters are respectively integrated by first and second integrators (61, 62) for a period which is an integral multiple of the sine wave period.

Description: BACKGROUND OF THE INVENTION The present invention relates to an impedance measuring apparatus which permits high-speed, high-precision measurement of an impedance transfer function of a measuring object at low and even ultra-low frequencies. Fig. 1 shows in block form a conventional synchronous detection type impedance measuring apparatus, in which a square-wave generator 11 provides 0°-phase and 90°-phase square waves at terminals 12 and 13, respectively. The 0°-phase square wave at the terminal 12 is applied to a low-pass filter 14 to obtain a sine-wave output, which is amplified by an amplifier 15 and then applied to a measuring object 16. The current output I x of the measuring object 16 is converted by a current-voltage converter 17 into a voltage signal, which is provided to synchronous detectors 18 and 19. The voltage signal is multiplied by the square waves from the terminals 12 and 13 for synchronous detection. The outputs of the synchronous detectors 18 and 19 are integrated by integrators 21 and 22, respectively, to obtain integrated outputs R ℓ and I m , which are selectively applied to an A-D converter 24 for conversion into digital form. Letting the resistance value of a feedback resistor 25 of the current-voltage converter 17 be represented by R, the A-D converter 24 yields a digital vector voltage R·I x = R ℓ + jI m . Provided that the low-pass filter 14 provides an output S i1 of a frequency f c as shown in Fig. 2A, the measuring object 16 and the current-voltage converter 17 produce distortions S i2 , S i3 , ... as shown in Fig. 2A. On the other hand, the spectrum of a square wave contains relatively large odd higher harmonics as shown in Fig. 2B. Consequently, the above-mentioned distortions are synchronously detected by the higher harmonics in the synchronous detectors 18 and 19 and appear at their outputs. In short, the conventional measuring apparatus has a disadvantage that distortions by the measuring object 16 and the current-voltage converter 17 directly appear as measurement errors. Another possible impedance measuring apparatus is such as depicted in Fig. 3. The output voltage of a sine-wave generator 26 is applied as an input voltage V in to the measuring object 16, and its current output I x is converted by the current-voltage converter 17 into a voltage signal, which is further converted by an A-D converter 27 into digital form. The digital signal is subjected to Fourier transformation by a Fourier transformer 28, obtaining an output S b corresponding to -R·I x . On the other hand, the input voltage V in from the sine-wave generator 26 is converted by an A-D converter 29 into a digital signal, which is Fourier-transformed by a Fourier transformer 31, obtaining an output S a corresponding to the input voltage V in . Thus, Z x = V in /I x = -R·S a /S b can be obtained. This impedance measuring apparatus is free from the influence of the distortions by the measuring object 16 and the current-voltage converter 17, but since the A-D converters 27 and 29 convert waveforms into digital signals, they are required to be high-speed and high-precision, and hence are expensive. Further, difficulties are encountered in high-speed operation because of the digital Fourier transformation. Where an error is contained in the transfer characteristic of the measuring system, a reference element is connected in place of the measuring object 16, the transfer characteristic of the measuring system is measured, and the measured results are used to perform a corrective operation of the output of the A-D converter 24 for the error in the transfer characteristic of the measuring system in the case of the measuring object 16 being connected. It is customary to learn the physical state of a measuring object at the atomic level by measuring its temporal impedance variations while causing abrupt transient change in bias voltage, magnetic field, temperature etc. In such a case, a very quick transient impedance is measured, but a computing element which performs the above-said corrective operation cannot respond to such a quick transient impedance. The prior art therefore employs a sampling system in which the transient response of the measuring object is repeated and the timing for measurement is shifted little by little accordingly. This sampling system has the defect of consuming much time for measurement. In the case where a parasitic capacitance 30 is present in the measuring circuit as shown in Fig. 1, it is a general practice in the prior art to measure the output in the absence of the measuring object 16 and subtract the value of this output from a measured value obtained in the presence of the measuring object 16. With this system, however, the range of measurement of the impedance of the measuring object 16 and the accuracy of analysis are limited owing to limitations on the dynamic ranges of the current-voltage converter 17, the synchronous detector 18, the integrator 21 and the A-D converter 24. That is, when current flowing through the measuring object 16 is small relative to a parasitic current flowing through the parasitic capacitance 30, the ratio of the parasitic current to the dynamic range of each of the current-voltage converter 17, the synchronous detector 18, the integrator 21 and the A-D converter 24 is large, reducing the accuracy of measurement. The document EP-A-0 268 447 (prior art according to Art. 54 (3) EPC) discloses a frequency response analyzing apparatus comprising a counter as address generating means, digital sine-wave generating means which includes waveform memory means which is read out at a sampling frequency using the addresses output from the address generating means to generate successive samples of a first digital sine wave, successive sample values of a second digital sine wave and successive sample values of a digital cosine wave, a D/A converter for converting the successive sample values of the first digital sine wave into an analog signal at the sampling frequency, means for applying the analog signal to a measuring object for deriving therefrom an output current, current-voltage converter means which converts the output current of said applying means into a voltage, a first multiplying type D/A converter for multiplying the output voltage of said current-voltage converter and the successive sample values of the second digital sine wave, a second multiplying type D/A converter for multiplying the output voltage of said current-voltage converter and the successive sample values of the digital cosine wave, a first integrator for integrating the output of said first multiplying type D/A converter and a second integrator for integrating the output of said second multiplying type D/A converter. In this prior art, a stimulus to be applied to the device under measurement is generated by successively reading out sine-wave samples stored in memory and converting them into an analog signal. The analog response signal from the device under measurement is multiplied by the multiplying type D/A converters with digital sample data of a sine wave and a cosine wave read out from a sine memory and a cosine memory. The outputs of the multiplying type D/A converters are subjected to integration to produce spectrum components of the response signal. The document "Technisches Messen", Vol. 53, No. 6, 1986, pages 220 to 228, discloses an impedance measuring apparatus using a digitally implemented Wheastone Bridge circuit, wherein two digitally synthesized sine waves with different phases are used to balance the bridge. It is therefore an object of the present invention to provide an impedance measuring apparatus in which a measurement error is free from the influence of distortions by a measuring object and a current-voltage converter. Another object of the present invention is to provide an impedance measuring apparatus which is low-cost and capable of high-speed measurement. Another object of the present invention is to provide an impedance measuring apparatus which permits measurement of a transient impedance in a short time. Yet another object of the present invention is to provide an impedance measuring apparatus which is capable of high precision measurement without being affected by a parasitic impedance. These objects are achieved with an impedance measuring apparatus as claimed. According to the present invention, digital sine-wave generating means including at least one sine waveform memory is read by the output of a phase accumulator, thereby generating a first digital sine wave, a second digital sine wave and a digital cosine wave. The first digital sine wave is converted by a D-A converter into an analog signal, which is applied to a measuring object. The output of the measuring object and the second digital sine wave are multiplied in a first multiplying type D-A converter, and the output of the measuring object and the digital cosine wave are multiplied in a second multiplying type D-A converter. The outputs of the first and second multiplying type D-A converters are integrated by first and second integrators, respectively, for a period which is an integral multiple of the period of the sine wave. Between the phase accumulator and first digital sine-wave generating means or between the phase accumulator and second digital sine-wave generating means a variable phase shifter is provided, and further, amplitude adjusting means is provided for adjusting the amplitude of the analog signal converted from the first digital sine wave. Phase adjustment data is added by the phase adjusting means to the output of the accumulator and a sine wave having a phase corresponding to the output of the phase adjusting means is produced by third sine-wave generating means. The amplitude of the output sine wave is adjusted by the amplitude adjusting means, and the amplitude-adjusted sine wave is supplied to a current-voltage converter, wherein it is added to the current output of the measuring object. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a conventional impedance measuring apparatus; Fig. 2A is a graph showing the output spectrum of a current-voltage converter used in Fig. 1; Fig. 2B is a graph showing the spectrum of a rectangular wave in Fig. 1; Fig. 2C is a graph showing the spectrum of the output of a sine waveform memory employed in the present invention; Fig. 3 is a block diagram illustrating a possible impedance measuring apparatus based on the prior art; Fig. 4 is a graph, for explaining the measurement of a transient impedance according to the prior art; Fig. 5 is a block diagram illustrating an impedance measuing apparatus; Fig. 5A shows variation in address 5A generated by a phase accumulator 32; Fig. 5B shows overflow signal 5B generated by the phase accumulator 32; Fig. 6 is a block diagram showing a modification of digital sine-wave generating means 39 used in Fig. 5; Fig. 7 is a diagram, for explaining the operation of the modified digital sine-wave generating means depicted in Fig. 6; Fig. 8 is a block diagram illustrating a first embodiment of the present invention; Fig. 9 is a timing chart showing the operation of a control section 87; Fig. 10 is a diagram showing a partially modified form of the embodiment depicted in Fig. 8; Fig. 11 is a block diagram illustrating a second embodiment of the present invention; Figs. 12A to 12C are diagrams showing various examples of an impedance to be measured and a parasitic impedance; and Fig. 13 is a block diagram illustrating a partially modified form of the embodiment depicted in Fig. 11. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 5 illustrates in block form an impedance measuring apparatus in which a phase accumulator 32 is provided. Upon each application of a clock, the phase accumulator 32 cumulatively adds a digital value n applied thereto and outputs a digital value shown as an analog waveform 33 in Fig. 5A to an address bus 34, and upon each occurrence of an overflow of its internal accumulator, the phase accumulator 32 outputs a pulse 36 to a terminal 35 as shown in Fig. 5B. The output of an oscillator 37 is frequency divided by a variable frequency divider 38 down to 1/mth thereof, and a clock of the divided frequency f s is applied to the phase accumulator 32. The output of the accumulator 32 to the address bus 34 is applied to a digital sine-wave generator 39. The digital sine-wave generator 39 in this example is provided with a first sine waveform memory 41, a second sine waveform memory 42 and a cosine waveform memory 43. Digital values from the address bus 34 are provided as addresses to the memories 41, 42 and 43 to read out their stored contents, which are loaded by the clock into latch circuits 44, 45 and 46. The output of the latch circuit 44 is converted by a D-A converter 47 into an analog signal, which is applied to a low-pass filter 48 and is then amplified by an amplifier 49, as required. The analog signal is provided to an adder 52, wherein it is added, as required, with a DC bias from a terminal 51, and the added output is supplied as an input to a measuring object 53. The output current I x of the measuring object 53 is converted by a current-voltage converter 54 into a voltage output V out . The voltage output V out is applied as an analog reference voltage to each of first and second multiplying type D-A converters 55 and 56. The first and second multiplying type D-A converters 55 and 56 are supplied at their data input terminals with the outputs of the latch circuits 45 and 46. The outputs of the first and second multiplying type D-A converters 55 and 56 are provided to first and second integrators 61 and 62 via switches 57 and 58, respectively. The outputs of the first and second integrators 61 and 62 are provided via a change-over switch 63 to an A-D converter 64. The pulses provided at the terminal 35 of the phase accumulator 32 are counted by a cycle counter 65, and by the output 66 of the cycle counter 65, reset switches 67 and 68 of the first and second integrators 61 and 62 are turned ON for a short period of time, thereby resetting the integrators 61 and 62. For a predetermined period of time k/f c (where f c is the frequency of the pulse 36 and k is an integer) after the resetting, the switches 57 and 58 connect, by the output 69 of the counter 65, the output sides of the first and second multiplying type D-A converters 55 and 56 to the first and second integrators 61 and 62. In the time interval between the trailing edge of the output 69 and an instant immediately before the reset pulse 66 the outputs of the first and second integrators 61 and 62 are converted by the A-D converter 64 to digital values. The outputs of the first and second multiplying type D-A converters 55 and 56 are as follows: V out (t)Sin(ωt) and V out (t)Cos(ωt) where ω = 2πf c . The outputs of the first and second integrators 61 and 62 are as follows: By selecting the integration time so that t₂ - t₁ = k/f c , the outputs R ℓ and I m resulting from the Fourier transformation of the output V out are obtained. The output R ℓ + jI m of the A-D converter 64 is proportional to the current I x flowing through the measuring object 53. V out = R·I x = R ℓ + jI m where R is the resistance value of a feedback resistor 71 of the current-voltage converter 54. Consequently, the impedance Z x of the measuring object 53 can be obtained as follows: where V in is the amplitude of the sine wave which is fed to the measuring object 53 and α ˙ is a corrective vector of the measuring system. The signals for detecting the output V out of the current-voltage converter 54, that is, the outputs of latch circuits 45 and 46, have such spectra as shown in Fig. 2C. A spectrum S b1 which coincides with the spectrum S i1 in Fig. 2A of the output from the measuring object is a component effective for detection. Spectra S b2 , S b3 , ... coincide with those of distortions by the measuring object 53 and the current-voltage converter 54 and appear as measurement errors, but they are very small, usually 1/1000 or less, and hence they are not so serious. Spectra S c1 and S c2 are unwanted spectra which occur at a frequency mf s ±f c (where m = 1, 2, ...). When a ratio f s /f c is set to a fraction, for instance, 10.24, then these spectra will not appear as measurement errors, because they do not coincide with the spectra of distortions by the measuring object 53 and the current-voltage converter 54. In the case where the integration period t₂ - t₁ is not set to an integral multiple of 1/f c and an integral multiple of 1/f s , for example, 400/f c = 4096/f s , the spectral components S c1 and S c2 are observed as truncation errors in the Fourier transformation. The truncation error decreases in inverse proportion to the integer k in the integration period t₂ - t₁ = k/f c and the ratio f s /f c , and consequently, the error is less than 0.1% when f s /f c = 10.24 and k = 10, for example. The transfer function of the measuring object 53 can be measured by employing a voltage-voltage converter in place of the current-voltage converter 54 in Fig. 5. The digital sine-wave generating means 39 in Fig. 5 may also be constructed as shown in Fig. 6. The output P of the phase accumulator 32 is applied to a phase shifter 72, from which 0°- and 90°-shifted outputs are provided alternately with each other as depicted in Fig. 7a. These outputs are applied as addresses to a sine waveform memory 73, from which a sine wave of a 0° phase angle and a sine wave leading it by a phase angle of 90°, i.e. a cosine wave, are read out alternately. The cosine wave is latched in a latch circuit 74 by a pulse shown in Fig. 7b. The sine wave is latched in a latch circuit 75 by a pulse shown in Fig. 7c, and at this time, the output of the latch circuit 74 is latched in a latch circuit 76. The output of the latch circuit 75 is provided to the D-A converter 47 and the first multiplying type D-A converter 55, whereas the output of the latch circuit 76 is provided to the second multiplying type D-A converter 56. The output R ℓ of the first integrator 61 in Fig. 5 is a conductance component of the impedance Z x of the measuring object 53, and the output I m of the second integrator 62 is a receptance component. These outputs R ℓ and I m may also be observed directly on an oscilloscope. Fig. 8 illustrates a first embodiment of the present invention, in which the parts corresponding to those in Fig. 5 are identified by the same reference numerals. In this embodiment the output at the terminal 34 of the phase accumulator 32 is added to phase shift data ϑ in a variable phase shifter 81 and then supplied to the first sine waveform memory 41. The output of the low-pass filter 48 is applied to the amplifier 49 after being multiplied by amplitude data A in a multiplying type D-A converter 82 which serves as phase adjust means. The output of the amplifier 49 is provided to a DC bias select circuit 83, the output of which is, in turn, applied to a selected one of the measuring object 53 and a reference element 84 via a change-over switch S₁. The output currents of the measuring object 53 and the reference element 84 are selectively applied via a switch S₂ to the current-voltage converter 54 for conversion into voltage form. The outputs of the multiplying type D-A converters 55 and 56 are supplied via switches S₄ and S₅ to the integrators 61 and 62, respectively. The outputs of the integrators 61 and 62 are sample-held in sample hold circuits 85 and 56, the outputs of which are, in turn, selectively fed to the A-D converter 64 via a switch 63. A switch S₃ of the DC bias select circuit 83 is controlled by the output of a control section 87, and as shown in Fig. 9, reset switches S₆ and S₇ of the first and second integrators 61 and 62 are temporarily turned ON to initialize them, after which the switches S₄ and S₅ are turned ON to perform the integration for the period k/f c (where k is an integer), and then switches S₈ and S₉ are temporarily turned ON, sample-holding the integrated outputs of the integrators 61 and 62. In a calibration mode, the switches S₁ and S₂ are connected to the reference element 84. The reference element 84 is a pure resistance element of a preknown resistance value Zr. In this state, the phase shift data ϑ is provided to the variable phase shifter 81 and the phase of the sine wave which is applied to the reference element 84 is controlled by adjusting the phase shift data ϑ so that the susceptance component I m available from the second integrator 62 is reduced to zero. Further, the amplitude data A which is input into the multiplying type D-A converter 82 serving as amplitude adjust means is controlled, by which the amplitude of the sine wave to be applied to the reference element 84 is controlled so that the conductance component R ℓ available from the first integrator 61 assumes a predetermined value a/Zr (where a is a real number). In this way, the corrective vector angle is reduced to zero, and consequently, by connecting the switches S₁ and S₂ to the measuring object 53 in a measurement mode, the conductance Gx and the capacitance Cs of the measuring object 53 are directly read as Gx = R ℓ /a and Cx = I m /aω, respectively, where ω is the angular frequency of a test signal and a is a proportional coefficient which is determined in the calibration mode. Fig. 10 illustrates a modified form of the embodiment depicted in Fig. 8. In Fig. 10 the output of the phase accumulator 32 is fed directly to the first sine waveform memory 41 and it is provided via a variable phase shifter 80 to the second sine waveform memory 42 and the cosine waveform memory 43. Fig. 11 illustrates another embodiment of the present invention, in which the parts corresponding to those in Fig. 5 and the foregoing embodiment are identified by the same reference numerals. The output of the A-D converter 64 is provided to a controller (a CPU) 88, through which it is displayed on a display 89 as required. The output of the phase accumulator 32 is supplied to a phase adjuster (a phase shift adder) 91, wherein it is added with phase adjust data ϑ. The output of the phase adjuster 91 is applied as an address to a sine waveform memory 92, and the read output of which is latched in a latch circuit 93 by the output clock of the frequency divider 38. The output of the latch circuit 93 is converted by a D-A converter 94 into an analog signal, which is applied via low-pass filter 95 to a reference input of a multiplying type D-A converter 96 forming an amplitude adjust means. The multiplying type D-A converter 96 is supplied at its digital input with amplitude adjust data A, and the input analog signal is amplitude-adjusted and then output. This output is supplied to the input of the current-voltage converter 54 via an amplifier 97, a resistor 98 and a switch S₈. The outputs of the amplifier 49, the current-voltage converter 54 and the amplifier 96 are detected by detectors 99, 101 and 102, respectively, and their output levels are provided to the A-D converter 64 via the change-over switch 63. By the output of the CPU 88 the switches S₁, S₂, S₈ and 63 are controlled and the amplitude adjust data A and the phase adjust data ϑ are controlled. Next, a description will be given of procedures for measurement in various cases. In the case where the measuring object 53 is a capacitance element and its capacitance C x is smaller than a parasitic capacitance C f of the measuring system as shown in Fig. 12A, the measuring object 53 is removed to provide an open circuit state, the switches S₁ and S₂ are connected to the side M, the switch S₈ is turned ON and then the phase adjust data ϑ and the amplitude adjust data A are adjusted by the CPU 88 so that the outputs V₄ and V₅ of the integrators 61 and 62 are reduced to zero. As a result of this, the vector of current flowing across the parasitic capacitance C f is cancelled by the output current of the amplifier 97. By connecting the measuring object 53 in this state, only current flowing across the measuring object 53 will be converted by the current-voltage converter 54 into voltage. In the case where a parasitic conductance G is connected in parallel to the capacitance C x desired to be evaluated and G » ωC (where ω is the measuring angular frequency) as shown in Fig. 12B, the switches S₁ and S₂ are connected to the side C and the switch S₈ is turned ON. The phase adjust data ϑ and the amplitude adjust data A are controlled by the CPU 88 so that the outputs V₄ and V₅ of the integrators 61 and 62 are both reduced to zero. In other words, the state in which the angle of the current vector is zero is detected. Let the phase adjust data ϑ and the amplitude adjust data A at that time be represented by ϑ₀ and A₀, respectively. Next, the switches S₁ and S₂ are connected to the side M (i.e. the measuring object 53 side) and only the amplitude adjust data A is adjusted by the CPU 88 so that the output V₃ of the current-voltage converter. 54 becomes sufficiently small. That is, current by the component of the parasitic conductance G is cancelled by the output of the amplifier 97. From the outputs V₄ and V₅ of the integrators 61 and 62 which are observed at this time the capacitance C x and the parasitic conductance G are obtained as follows: where V₁ is the output level of the amplifier 49, K is a detection · integration gain, R a is the resistance value of a feedback resistor 103 of the current-voltage converter 54 and Z r is the resistance value of the reference resistance element 84. If the amplitude adjust data A is so adjusted as to minimize the output V₃, then the output V₄ of the integrator 61 will be substantially zero and the parasitic conductance G will be given as follows: In the case where a parasitic capacitance C and a conductance G x desired to be evaluated are connected in parallel and G x « ωC as shown in Fig. 12C, the switches S₁ and S₂ are connected to the side C, the switch S₈ is turned ON and the phase adjust data ϑ and the amplitude adjust data A are controlled by the CPU 88 so that the outputs V₄ and V₅ of the integrators 61 and 62 are reduced to zero. That is, the state in which the angle of the current vector is zero is obtained. Let the phase adjust data ϑ and the amplitude adjust data A at this time be represented by ϑ₀ and A₀, respectively. The switches S₁ and S₂ are changed over to the side M and the phase adjust data is set to ϑ₀ + 90°. Only the amplitude data A is adjusted by the CPU 88 to make the integrator output V₃ sufficiently small. In other words, current flowing across the parasitic capacitance C is cancelled by the output of the amplifier 97. From the integrator outputs V₄ and V₅ which are observed at this time, the conductance G x and the parasitic capacitance C are obtained as follows: Letting the number of bits of the phase accumulator 32, the set value of phase increment data and the frequency of the input clock of the phase accumulator 32 be represented by m, n₁ and f s (Hz), the measuring angular frequency ω becomes as follows: By changing the set value n₁ the measuring angular frequency ω can be varied. Letting the number of bits of the phase adjust data and the number of bits of the phase adjust means (the phase shift adder) 91 be represented by n₂ and r, respectively, the phase shift amount ϑ becomes as follows: Thus, the phase can be adjusted with high resolution and with high precision. It is also possible to control the amplitude value of the current adding vector by an analog feedback as shown in Fig. 13; namely, the current-voltage conversion coefficient is controlled by the output of the detector 101 so that the output is minimized. As described above, the impedance measuring apparatus of the present invention does not employ any high-speed, high-precision A-D converters, and hence is less expensive than the conventional apparatus shown in Fig. 3. The apparatus of the present invention does not call for the digital Fourier transformation, and hence operates at high speed. Moreover, the apparatus of the present invention permits high precision measurement, because it is free from the influence of distortion by the measuring object and the current-voltage converter. According to the prior art depicted in Fig. 1, the pass characteristic of the low-pass filter 14 must be changed for making the measuring frequency variable and it is difficult to make the measuring frequency variable. According to the present invention, however, even if the measuring frequency is changed, the spectra S c1 and S c2 in Fig. 2C vary only slightly, and consequently, the filter characteristic of the filter for removing them need not be made variable and the measuring frequency f c can easily be changed. Besides, according to the embodiment of the present invention shown in Fig. 8, in the calibration mode the phase shifter 81 or 80 are controlled to adjust the output of the phase accumulator 32 and its amplitude is adjusted by the amplitude adjust means 82, compensating the transfer characteristic of the measuring system. By this, the admittance of the measuring object 53 is measured without the need of correcting the outputs of the first and second integrators 61 and 62. Since no correction by operation is needed, a transient response of impedance can be measured. According to the embodiment shown in Fig. 11, the parasitic current is cancelled by adding the phase-adjusted current and the amplitude-adjusted current at the input side of the current-voltage converter 54, the current-voltage converter 54 and the vector detecting means 104 are supplied with only the current desired to be measured, and consequently, its dynamic range can be utilized effectively, permitting high precision measurement.

Claims: An impedance measuring apparatus comprising: address generating means for generating a series of addresses and comprising a phase accumulator (32) for repeatedly adding a given value to produce a series of digital values as the addresses, digital sine-wave generating means (41-46) which includes waveform memory means (41, 42, 43) which is read at a sampling frequency using the addresses output from said phase accumulator (32) to generate successive sample values of a first digital sine wave, successive sample values of a second digital sine wave and successive sample values of a digital cosine wave; a D-A converter (47) for converting the successive sample values of the first digital sine wave into an analog signal at the sampling frequency; a variable phase shifter means (80, 81) for causing an addition of phase difference between the first digital sine wave and both the second sine wave and the cosine wave; an amplitude adjust means (82) provided in the output side of said D-A converter (47) for adjusting the amplitude of the analog signal; a selective applying means (S₁, S₂) for applying the amplitude adjusted analog signal selectively to a measuring object (53) or a reference element (84) and deriving selectively therefrom an output current; a current-voltage converter (54) which converts the output current of said selective applying means into a voltage; a first multiplying type D-A converter (55) for multiplying the output voltage of said current-voltage converter (54) and the successive sample values of the second digital sine wave; a second multiplying type D-A converter (56) for multiplying the output voltage of said current-voltage converter (54) and the successive sample values of the digital cosine wave; a first integrator (61) for integrating the output of said first multiplying type D-A converter (55) for a period of time which is an integral multiple of the sine wave period; and a second integrator (62) for integrating the output of said second multiplying type D-A converter (56) for a period of time which is an integral multiple of the sine wave period. The impedance measuring apparatus of claim 1, wherein the digital sine-wave generating means comprises a first sine waveform memory (41) which is read out by the output of the phase accumulator (32) to generate the first digital sine wave, a second sine waveform memory (42) which is read out by the output of the phase accumulator to generate the second digital sine wave, and a cosine waveform memory (43) which is read out by the output of the phase accumulator to generate the digital cosine wave. The impedance measuring apparatus of claim 2, wherein said variable phase shifter means (81) is provided between said phase accumulator (32) and said first sine waveform memory (41) and adds a phase value to the output of said phase accumulator to be applied to said first sine waveform memory. The impedance measuring apparatus of claim 1, wherein the amplitude adjust means is a multiplying type D-A converter which multiplies the analog signal by amplitude data. The impedance measuring apparatus of claim 2, wherein said phase shifter means (80) is provided between said phase accumulator (32) and both said second sine waveform memory and said cosine waveform memory (42, 43). An impedance measuring apparatus comprising: address generating means for producing a series of addresses and comprising a phase accumulator (32) for repeatedly adding a given value to produce a series of digital values as the addresses; digital sine-wave generating means (41-46) which includes waveform memory means (41-43) which is read at a sampling frequency using the addresses output from said phase accumulator (32) to generate successive sample values of a first digital sine wave, successive sample values of a second digital sine wave and successive sample values of a digital cosine wave; a D-A converter (47) for converting the successive sample values of the first digital sine wave into an analog signal at the sampling frequency; a selective applying means (S₁, S₂) for applying the analog signal selectively to a measuring object (53) or a reference element (84) and deriving selectively therefrom an output current; a current-voltage converter (54) which converts the output current of said selective applying means (S₁, S₂) into a voltage; a first multiplying type D-A converter (55) for multiplying the output voltage of said current-voltage converter (54) and the successive sample values of the second digital sine wave; a second multiplying type D-A converter (56) for multiplying the output voltage of said current-voltage converter (54) and the successive sample values of the digital cosine wave; a first integrator (61) for integrating the output of said first multiplying type D-A type converter (55) for a period of time which is an integral multiple of the sine wave period; a second integrator (62) for integrating the output of said second multiplying type D-A converter (56) for a period of time which is an integral multiple of the sine wave period; a phase adjust means (91) for adding phase adjust data to the output of said phase accumulator (32); a cancelling sine wave generating means (92, 93, 94) for generating a cancelling sine wave of a phase corresponding to the output of said phase adjust means (91); an amplitude adjust means (96) for adjusting the amplitude of the output cancelling sine wave of said cancelling sine wave generating means (92-94); and an adding means (S₈) for supplying the output of said amplitude adjust means to the input of said current-voltage converter (54) for cancelling a parasitic current in the output current of said selective applying means (S₁, S₂). The impedance measuring apparatus of claim 6, wherein said cancelling sine-wave generating means (92-94) includes a sine waveform memory (92) which is read out by the output of said phase adjust means (91) and a second D-A converter (94) for converting the output of said sine Waveform memory (92) into an analog signal of the cancelling sine wave. The impedance measuring apparatus of claim 7, further including a first detector (99) for detecting the output level of first mentioned said D-A converter (47), a second detector (101) for detecting the output level of said current-voltage converter (54), and a third detector (102) for detecting the output level of said cancelling sine-wave generating means (92-94).

Inventors: KITAYOSHI, HITOSHI
Applicants: ADVANTEST CORPORATION
Application year: 1988
Main classification: G01R27
IPC codes: G01R27