Correction arrangement for an amplifier

Abstract: Correction arrangement, for an amplifier, with two correction circuits (CS1,PM2,NM3/2,CS2,NM4,PM4/3) each connected in parallel across the output stage (PM1,NM1) of the amplifier provided with an input differential amplifier stage (A1), with two differential amplifiers (A2/3) constituting an intermediate stage and with the output stage constituted by the series connection of a PMOS transistor (PM1) and an NMOS transistor (NM1) the junction point (VOUT) of which is connected to the input stage via a feedback circuit (FC). Each correction circuit is able to measure the DC current (I1;I2) through an output transistor (PM1, NM1), to compare a measuring DC current (I3;I4) derived from this measured DC current with a reference DC current (I5;I6) and to change the DC voltage on the gate of the other output transistor (NM1;PM1) in function of the difference and to thus produce a correcting function on the amplifier through the feedback circuit.

Description: The present invention relates to a correction arrangement for an amplifier which includes two differential amplifiers whose outputs are coupled to the control electrodes of respective output transistors of opposite conductivity type which constitute an output stage and are coupled in series between the poles of a DC voltage source and the junction point of which constitutes the output of the amplifier, said arrangement including at least one measuring means for measuring the DC current through one of the output transistors and for providing a measuring DC current which is a measure of this measured DC current, and a feedback arrangement connecting the amplifier output to the inputs of the two differential amplifier stages. Such a correction arrangement is already known from the published French patent application FR-A-2453538. This known correction arrangement, for instance the one shown in detail in Fig. 4 thereof, stabilizes the operating point of the two output transistors Q3b, Q4b via the feedback arrangement R1, R2 and furthermore prevents excessive current consumption of these output transistors in their quiescient state by controlling the DC currents flowing through the latter transistors. The latter control consists in measuring the currents flowing through Q3b and Q4b so producing proportional measuring currents in transistors Q5 and Q6 respectively which are then combined via Q7, Q9 and Q8, Q10 into a current If having a value equal to the product of the mentioned measuring currents. The desired control operation is then obtained by feeding the current If back to junction points 20a and 20b of a preamplification stage. The known correction arrangement in this way is rather complicated and, moreover, uses relatively much hardware due to the fact that two correction operations are performed by separate feedback circuits and due to the fact that circuitry has to be provided to calcualte the product of the output currents. An object of the present invention is to propose a correction arrangement of the above known type but which is less complicated and provides the desired correction operation with less hardware. This object is achieved due to the fact that said arrangement further includes at least one correction circuit which is provided with one said measuring means, with means for comparing said measuring DC current of said one output transistor with a reference constant DC current thereby producing a difference DC current and with means for changing the DC voltage on a control electrode of another of said output transistors in function of said difference DC current by injecting this difference DC current into the junction between this control electrode and the output of the differential stage coupled thereat. In this way the correction arrangement is adapted to measure independently one of the output currents and achieve a correction operation based on said independent measurement. The correction arrangement is therefore less complicated because the output currents no longer have to be combined in order to calculate the product of two such measuring currents. Moreover is the correction operation associated to this measurement achieved via the known feedback arrangement coupling the junction point of the output transistors to the inputs of the amplifier without the need for a separate circuit. Finally it is to be noted that such correction is already obtained with only one correction circuit precisely because the correction on one output transistor is independent from the correction on the other output transistor. From the above reasons it is clear that the present correction arrangement is both less complicated and that it uses less hardware to arrive at a desired correction operation. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein: Fig. 1 represents an amplifier and an associated correction arrangement according to the invention; Figs. 2 and 3 represent the intermediate stage differential amplifiers A2 and A3 of Fig. 1 in more detail : The circuit represented in Fig. 1 operates with the supply voltages VDD=5 Volts; VSS = 0 Volt and VAG = 2.5 Volts and includes a class AB amplifier AMP and an associated correction arrangement CC. The amplifier AMP includes an input stage differential amplifier A1 whose plus input constitutes the input IN of the amplifier and whose output V is connected to the minus inputs of two differential amplifiers A2 and A3. Together these amplifiers constitute an intermediate stage and their plus inputs are connected to the voltage VAG. The intermediate stage differential amplifiers A2 and A3 are used for amplifying the positively and negatively directed input signals respectively. The outputs V' and V'' of these amplifiers A2 and A3 are connected to the gate electrode of PMOS transistor PM1 and NMOS transistor NM1 respectively, the source-to-drain path of PM1 and the drain-to-source path of NM1 being connected in series between the DC supply voltages VDD and VSS. The transistors PM1 and NM1 together form the class AB output stage of the amplifier and their junction point is the output VOUT thereof. This output is coupled back, on the one hand to the plus inputs of A2 and A3 via a compensation capacitor C and, on the other hand, to the minus input of A1 via a negative feedback circuit FC. The latter is constituted by a voltage divider comprising a series resistance R1 and a shunt resistance R2 connected to VAG. The correction arrangement CC includes two similar correction circuits which include a constant current source CS1; CS2 and MOS transistors PM2, NM2/3; NM4, PM4/3 respectively. The constant current source CS1 and NMOS transistor NM2 form a series circuit which is connected across the output stage PM1, NM1. The output transistor PM1 is connected in current mirror configuration with NMOS measuring transistor NM2 via PMOS transistor PM2 and the diode connected NMOS transistor NM3. The dimensions of PM1/2 and NM2/3 are so chosen that the DC current I3 which is thus obtained in NM2 by mirroring of the DC current I1 in PM1, is equal to kI1, with e.g. k = 1 / 20 . The constant DC reference current which is provided by CS1 is designated I5. In a similar way the series connection of PMOS measuring transistor PM3 and constant current source CS2 is connected in parallel across the output stage. The output transistor NM1 is connected in current mirror configuration with PMOS transistor PM3 via NMOS transistor NM4 and the diode connected PMOS transistor PM4. The DC current I4 in PM3 obtained by mirroring the DC current I2 in NM1, via NM4 and PM4, is for instance equal to K′I2, with k′ = 1 / 20 . The constant reference DC current which is provided by CS2 is designated I6. As will become clear later each correction circuit CS1, PM2, NM3/2, CS2, NM4, PM4/3 includes: measuring means PM2, NM3, NM2 and NM4, PM4, PM3 for measuring the current I1; I2 and for generating in the measuring transistor NM2; PM3 a measuring DC current I3; I4 which is a measure of this measured DC current I1; I2; means CS1, NM2 and PM3, CS2 for comparing the measuring DC current I3; I4 with the DC reference DC current I5; I6 and for modifying the gate DC voltage V″; V′ in function of the thus obtained difference DC current, due to which a correction operation is then performed via the feedback circuit FC. It should be noted that two correction circuits are provided in order that the current I1 should be corrected in the same way as the current I2 and vice versa. However, a correction operation is already performed by one correction circuit. The intermediate stage differential amplifiers A2 and A3 are shown in detail in Fig. 2 and Fig. 3 respectively. The intermediate stage differential amplifier A2 includes two input transistors NM5 and NM6 whose gates constitute the minus and plus input of the amplifier. The source-to-drain paths of two PMOS transistors PM5 and PM6 which are branched in current mirror configuration are connected in series with the drain-to-source paths of NM5 and NM6 respectively and a common constant current source CS3. The junction point of PM5 and NM5 constitutes the output V′ of A2. The intermediate stage differential amplifier A3 is similar to A2 and includes PMOS transistors PM7/8, NMOS transistors NM7/8 and constant current source CS4. The gates of PM7 and PM8 are the minus and plus inputs of A3 respectively and the junction point of PM7 and NM7 constitutes the output terminal V″ of A3. Both correction circuits of the correction arrangement operate in a similar way and for this reason only the operation of correction circuit CS1, PM2, NM3/2 is described. In the rest condition of the circuit, i.e. in the absence of an input signal, and under normal circumstances equal currents I1 and I2 flow in PM1 and NM1 respectively and VOUT=0. The measuring DC current I3 mirrored in transistor NM2 by transistors PM2 and NM3 is then equal to the reference DC current I5 of the constant current source CS1 so that the gate DC voltage V″ is then not influenced by the correction circuit CC. This means that in the amplifier A3 the current of PM7 completely flows through NM7. It is now assumed that in the rest condition of the circuit the DC current I2 through PM1 is too large so that an excessive current consumption could be produced. This is for instance the result of an offset producing a too small output voltage V′ of A2 or gate voltage V′ of PM1. For this reason the current I3 mirrored in the measuring transistor NM2 by the measuring means PM2, NM3, NM2 is too large, as a consequence of which the current balance at the junction point V″ of CS1 and NM2 is broken. The additional difference DC current dI3=I3-I5 flowing through NM2 has therefore to be produced by the amplifier A3. As a consequence a decrease is produced of the output DC voltage V″ of this amplifier A3 and therefore of the gate DC voltage V″ of transistor NM1. Due to this the current I2 through NM1 decreases and this leads in its turn to an increase of the output voltage VOUT. As a consequence the feedback circuit FC, the amplifier A1 and the differential amplifiers A2 and A3 produce an increase of the output voltages V′ and V″ of A2 and A3. This gives rise to a decrease of I1 and an increase of I2 and this results in its turn in a decrease of VOUT. An equilibrium is reached when the current balance in point V″ is restored, i.e. when dI3=0. In this case also VOUT is again zero. It is clear that a too small current I1 which could produce cross-over distortion is corrected in a similar way and also until the current balance in point V′ is restored.

Claims: Correction arrangement (CS1, PM2, NM3/2; CS2; NM4; PM4/3) for an amplifier (AMP) which includes two differential amplifier stages (A2, A3) whose outputs (V', V'') are coupled to the control electrodes of respective output transistors (PM1, NM1) of opposite conductivity type which constitute an output stage and are coupled in series between the poles (VDD, VSS) of a DC voltage source and the junction point of which constitutes the output (VOUT) of the amplifier, said arrangement including at least one measuring means (PM2, NM3/2; NM4, PM4/3) for measuring the DC current (I1; I2) through one of the output transistors (PM1; NM1) and for providing a measuring DC current (I3; I4) which is a measure of this measured DC current (I1; I2), and a negative feedback arrangement (FC, A1) connecting the amplifier output (VOUT) to the inputs of said two differential amplifier stages (A2, A3), characterized in that said arrangement further includes at least one correction circuit (CS1, PM2, NM3/2; CS2, NM4, PM3/4) which is provided with one said measuring means (PM2, NM3/2; NM4, PM4/3), with means (CS1, NM2; PM3, CS2) for comparing said measuring DC current (I3; I4) of said one output transistor (PM1, NM1) with a reference constant DC current (I5; I6) thereby producing a difference DC current and with means for changing the DC voltage on a control electrode of another (NM1; PM1) of said output transistors in function of said difference DC current by injecting this difference DC current into the junction between this control electrode and the output of the differential stage coupled thereat. Correction arrangement according to claim 1, characterized in that said measuring means (PM2, NM3/2; NM4, PM4/3) are coupled to said output transistor (PM1; NM1) and produce said measuring DC current (I3; I4) in a measuring transistor (NM2; PM3) and that the series connection of said measuring transistor (NM2; PM3) and a constant current source (CS1; CS2) providing said reference DC current (I5; I6) is connected in parallel across said output stage (PM1, NM1), the junction point (V''; V') of said measuring transistor and said constant current source which together constitute said comparison mean being directly connected to the control electrode of said other output transistor (NM1; PM1). Correction arrangement according to claim 2, characterized in that the nominal value of the measuring DC current (I3; I4) is equal to said reference DC current (I5; I6). Correction arrangement according to claim 2, characterized in that said measuring means (PM2, NM3/2; NM4, PM4/3) couple said one output transistor (PM1; NM1) with said measuring transistor (NM2; NM3) via a current mirror circuit (PM1/2, NM3/2; NM1/4, PM4/3). Correction arrangement according to claim 1, characterized in that said correction arrangement includes two (CS1, PM2, NM3/2; CS2, NM4, PM4/3) of said correction circuits which are each able to measure the DC current (I1, I2) in a respective output transistor (PM1; NM1) and to change the DC voltage (V'', V') on the control electrode of the respective other output transistor (NM1; PM1) in function thereof. Correction arrangement according to claim 1, characterized in that said amplifier further includes an input stage differential amplifier (A1) with a plus input constituting the input (IN) of the amplifier, with a minus input with which the amplifier output (VOUT) is connected via a feedback circuit (FC) and with an output (V) coupled to the inputs of the two differential amplifiers (A2, A3), said input stage (A1) and said feedback circuit (FC) constituting said feedback arrangement. Correction arrangement according to claim 6, characterized in that the minus inputs of said differential amplifiers (A2; A3) are connected to the output (V) of the input stage (A1), whilst their plus outputs are connected to a common DC voltage (VAG). Correction arrangement according to claim 7, characterized in that said common DC voltage (VAG) is equal to VSS and VDD being the DC voltages of said poles. Correction arrangement according to claim 1, characterized in that each of said two differential amplifiers (A2; A3) is constituted by two input transistors (NM5/6; PM7/8) whose gates constitute the inputs and whose source-to-drain paths are each connected in series with the source-to-drain path of other transistors (PM5/6; NM7/8) mutually connected in current mirror configuration, said two series connections further including a common constant current source (CS3; CS4) which is coupled with the source electrodes of said input transistors (NM5/6; PM7/8) and a junction point of the drain electrodes of an input transistor (NM5; PM7) and another transistor (PM5; NM7) constituting the output of the differential amplifier (A2; A3). Correction arrangement according to one of the claims 1 to 9, characterized in that said transistors are MOS transistors. Correction arrangement according to claim 1, characterized in that said amplifier is a class AB amplifier.

Inventors: RABAEY DIRK HERMAN LUTGARDIS C, SEVENHANS JOANNES MATHILDA JOS, RABAEY, DIRK HERMAN LUTGARDIS CORNELIUS, SEVENHANS, JOANNES MATHILDA JOSEPHUS
Applicants: ALCATEL NV, BELL TELEPHONE MFG, ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENNOOTSCHAP
Application year: 1988
Main classification: H03F3
IPC codes: H03F3, H03F1