A LOW NOISE INTEGRATED ACTIVE LOAD CIRCUIT

Abstract: This invention is a low noise active load circuit for a bipolar integrated circuit. The circuit includes a first (V CC ) and second (14) terminal, a resistor (R L ), a first transistor (Q L1 ) and a plurality of second transistors (Q L2 ). The emitter of the first transistor is coupled to the first terminal, the base is coupled to the base and collector each of the second transistors and to the resistor. The collector of the first transistor is coupled as a load to the application circuit (12). The emitter of each of the second transistors is coupled to the first terminal. The resistor is coupled to the second terminal.

Description: Field of the Invention This invention relates to the field of bipolar integrated circuits. More particularly, this invention relates to the field of low noise active load circuits in bipolar integrated circuits. Background of the Invention Electronic noise is an undesirable side effect of the operation of electronic circuits. Device switching and p-n junction operation are common sources of electronic noise in integrated circuits. It is an object of the present invention to provide an active load circuit for an integrated circuit which has reduced noise introducing properties. It is another object of the present invention to provide an active load circuit for an integrated circuit which does not appreciably increase the surface of the integrated circuit. Accordingly, the invention proposes a low noise integrated active load circuit comprising: a. a first terminal ( ); b. a second terminal ( ); c. a third terminal ( ); d. a first bias resistor having a first resistor terminal and a second resistor terminal said first resistor terminal coupled to said second terminal; e. a first transistor (Q L1 ) having a first collector, a first base and a first emitter, said first emitter coupled to said first terminal and said first collector coupled to said third terminal; and f. a plurality of second transistors ( ) each having a second collector, a second base and a second emitter, each of said second emitters coupled to said first terminal, each of said second bases coupled to said first base, to each of said second collectors and to said second resistor terminal. Preferably the load circuit has a first terminal which is a power supply, a second terminal which is a ground node and a third terminal which loads an external circuit. A first bipolar transistor has its emitter coupled to the first terminal and its collector coupled to the third terminal. A pluraLity of second transistors each have an emitter coupled to the first terminal, base and collector coupled to the base of the first transistor and to a load resistor. The load resistor is also coupled to ground. Brief Description of the Drawings The invention will now be described with reference to several exemplary embodiments of the invention illustrated in the accompanying drawings; in which: Figure 1 is a circuit diagram illustrating a prior art active load and a photodiode preamplifier application circuit. Figure 2 is a circuit diagram illustrating a prior art method of lowering the noise of Figure 1, but utilizing excess chip area. Figure 3 is a circuit diagram illustrating a preferred embodiment of the present invention. Figure 4 is a circuit diagram illustrating an equivalent circuit indicating sources of noise. Figure 5 is a circuit diagram illustrating an equivalent circuit indicating sources of noise in reference to an AC signal ground. Figure 6 is a circuit diagram illustrating a single high current gaIn transistor and a noise source. Figure 7 is a circuit diagram illustrating an equivalent circuit with localized noise sources. Figure 8 is a circuit diagram illustrating an alternate embodiment of the present invention. Detailed Description of the Preferred Embodiment The active load circuit 10 shown in Figure 1 introduces electronic noise into the application circuit 12 that it loads. The active load circuit 10 has a voltage supply V CC , load transistor Q L1 , load transistor Q L2 , bias resistor R L and circuit ground 14. Q L1 and Q L2 are PNP transistors. The emitter of Q L1 is coupled to the voltage supply V CC . The collector of transistor Q L1 is coupled to the loading node 16. The base of transistor Q L1 is coupled to the base and collector of transistor Q L2 and to one terminal of the resistor R L . The emitter of transistor Q L2 is coupled to the voltage supply V CC . The other terminal of the resistor R L is coupled to ground 14. The application circuit 12 shown in the prior art Figure 1 is a photodiode preamplifier circuit. The anode terminal of the photodiode 18 is coupled to ground 14 and the cathode terminal of the photodiode 18 is coupled to the base of transistor Q₂ and to one terminal each of the feedback resistor R F and the feedback capacitor C F . The emitter of transistor Q₂ is coupled to a first biasing voltage level V E . The collector of transistor Q₂ is coupled to the emitter of transistor Q₁. The base of transistor Q₁ is coupled to a second biasing voltage supply V B . The collector of transistor Q₁ is coupled to loading node 16 and to the input of the gain-of-one amplifier 20. The output of the amplifier 20 is coupled to the output 22 of the photodiodepreamplifier circuit 12 and to the other terminal of each of the feedback resistor R F and the feedback capacitor C F . The output 22 is used to drive external circuitry which is not shown. Referring to Figure 2 one can see a technique to reduce the noise introduced by the load circuit. A load resistor R L replaces the active load circuit 10 of Figure 1 and is coupled between the power supply V CC and the collector of transistor Q₁. Also such a resistive load must typically be a very high resistance, on the order of several hundred kΩ requiring much surface area on an integrated circuit. The base of transistor Q₁ is coupled to a biasing voltage V B and the emitter is coupled to the collector of transistor Q₂. The base of traNsistor Q₂ is coupled to an input voltage V IN and the emitter is coupled to a biasing voltage V E . If the circuit of Figure 2 is designed to require a load current of 5 µA, the resistor is 76 kΩ . Because the cost of manufacturing an integrated circuit is directly related to the area of the circuit, each of these prior art techniques of reducing noise resulting from an active load is undesirable. Where such techniques have been utilized typically the integrated circuit designer has required the user to attach an external resistor rather than integrating the large resistance into the device. The preferred embodiment of the present invention shown in Figure 3 is described relative to the same application circuit 12 shown in the prior art circuit of Figure 1. The anode terminal of photodiode 18 is coupled to ground 14 and the cathode terminal of photodiode 18 is coupled to the base of transistor Q₂ and to one terminal of feedback resistor R F and feedback capacitor C F . The emitter of transistor Q₂ is coupled to a voltage level V E . The collector of transistor Q₂ is coupled to the emitter of transistor Q₁. The base of transistor Q₁ is coupled to voltage supply V B . The collector of transistor Q₁ is coupled to loading node 16 and to the input of the gain-of-one op amp 20. The output of op amp 20 coupled to the output 22 of the photodiode preamplifier circuit 12 and to the other terminal of the feedback resistor R F and the feedback capacitor C F . The novel active load circuit 10A of the present invention has a voltage supply V CC , load transistor Q L 1 a plurality of load transistors Q L2A , through Q L2G , load resistor R L and circuit ground 14. Q L1 and Q L2A through Q L2G are PNP transistors. The emitter of Q L1 is coupled to the resistor R W . The resistor R W is also coupled to the voltage supply V CC . The collector of transistor Q L1 is coupled to the loading node 16 of circuit 12. The bases of each transistor Q L2A through Q L2G is coupled to each other base and each collector of transistors Q L2A through Q L2G and to one terminal of resistor R L . Each emitter of transistor Q L2A through Q L2G is coupled to voltage supply V CC . Each base and collector of each transistor Q L2A through Q L2G is coupled to the base of transistor Q L1 and to one terminal of resistor R L . The other terminal of resistor R L is coupled to ground 14. The active load circuit 10A of Figure 3 of the present invention operates to reduce the noise introduced into the application circuit 12. As will be clearly understood from the discussion below each component of the active load circuit 10A contributes to the noise introduced into the application circuit 12. The current mirror configuration of the active load circuit 10A reflects the noise generated by the transistors Q L2A through Q L2G and the resistor R L , which are not directly coupled to the application circuit 12, into the application circuit. By forming a plurality of transistors Q L2A through Q L2G such that the current carrying capacity of the side of the current mirror not coupled to the application circuit 12 is greater than the current carrying capacity of the side of the mirror which is so coupled, the amount of noise introduced into the application circuit 12 is reduced proportional to the ratio of those current carrying capacities. The noise generated in the circuit of Figure 3 responsive to the active load is derived as described below. It is assumed for this derivation that the resistance R W = ⊘Ω. The gain, β, of each of the transistors is very large; assume that β → ∞. Therefore, the noise attributable to each of the base currents is negligible and ignored. The noise sources which contribute to the noise seen at node 16 and ultimately at the output 22 are shown in Figure 4. The circuit of Figure 4 has the same components as in Figure 3 and are configured in the same fashion. The emitter of Q L1 is coupled to the voltage supply V CC . The collector of transistor Q L1 is coupled to the loading node 16. The base of transistor Q L1 is coupled to the base and collector of each transistor Q L2A through Q L2G and to one terminal of the resistor R L . The emitter of each transistor Q L2A through Q L2G is coupled to the voltage supply V CC . The other terminal of the resistor R L is coupled to ground 14. The collector of NPN transistor Q₁ is coupled to node 16, the base to a biasing voltage V B and the emitter is coupled to the collector of NPN transistor Q₂. The base of transistor Q₂ is driven by an input voltage V IN . V IN is controlled by the remainder of the application circuit and photodiode not shown in Figure 4. The emitter of transistor Q₂ is coupled to a biasing voltage supply V E . The sources of noise are shown in Figure 4 as ten current sources and a voltage source. I NQL1 is coupled across transistor Q L1 between its collector and emitter. I NQL2A through I NQL2G are coupled across the collector and emitter of each transistor Q L2A through Q L2G , respectively. V NRL , a noise voltage, is coupled between resistor R L and ground 14. I NQ1 is coupled across transistor Q₁ between its collector and emitter. I NQ2 is coupled across transistor Q₂ between its collector and emitter. DC voltages represent short circuits to AC signals. Thus, from an AC signal analysis standpoint, any of the noise sources referenced to a DC voltage supply should be referenced to AC signal ground 15. For this reason the circuit analysis for the noise signals relative to the circuit of Figure 3 and Figure 4 as seen at node 16 are shown as modified in Figure 5. The emitter of Q L1 is coupled to the voltage supply V CC . The collector of transistor Q L1 is coupled to the loading node 16. The base of transistor Q L1 is coupled to the base and collector of each transistor Q L2A through Q L2G and to one terminal of the resistor R L . The emitter of each transistor Q L2A through Q L2G is coupled to the voltage supply V CC . The other terminal of the resistor R L is coupled to ground 14. The collector of NPN transistor Q₁ is coupled to the node 16, the base to a biasing voltage V B and the emitter is coupled to the collector of NPN transistor Q₂. The base of transistor Q₂ is driven by an input voltage V IN . V IN is controlled by the application circuit 12 shown in Figure 3 not shown in Figure 5. The emitter of transistor Q₂ is coupled to a biasing voltage supply V E . Each of the noise sources coupled to a DC voltage supply in Figure 4 is shown in Figure 5 to be coupled to the AC signal ground 15. Current source I NQL1 is coupled between the collector of transistor Q L1 and AC signal ground 15. The current sources I NQL2A through I NQL2G are coupled between the collector of each transistor Q L2A through Q L2G , respectively, and AC signal ground 15. Voltage source V NRL is coupled between resistor R L and circuit ground 14. Current source I NQ1 is not coupled to a DC voltage and so remains coupled across the collector and emitter of transistor Q₁. Current source I NQ2 is coupled between the collector of transistor Q₂ and AC signal ground 15. Since β for Q₁ is large the noise introduced by Q₁ is cancelled out. Referring to Figure 6, the collector of transistor Q is coupled to a supply voltage V supply . The emitter of transistor Q is coupled to an ideal current source I E . Transistor Q₂ is assumed to operate as the ideal current source I E . The ideal current source is coupled to ground. A biasing voltage V bias is coupled to the base. A current source, I N , (i.e. I N noise current source) is shown coupled between the emitter and collector of the transistor Q. Applying Kirchoff's current law and the basic fundamentals of bipolar transistors yields the result that the current I example is equal to the sum of the noise signal I N and α Q * I N as shown by: I example = - I N + ( α * I N ) + ( α * I E ) Because β → ∞, α ≃ 1. Therefore, I example ≃ I E . Note that I N is cancelled. For this reason, the noise attributable to transistor Q₁, I NQ1 , has no effect on the total noise attributable to the circuit active load I N shown in Figure 5. Referring again to Figure 5, Q₁ is in common base configuration. Therefore, the emitter current is approximately equal to the collector current in Q₁. The emitter current in Q₁ is exactly equal to the collector current in Q₂. Thus, the noise attributable to Q₂ is reflected into node 16. The noise attributable to Q L1 is coupled to node 16. The voltage noise source V NRL may be configured as a current source, relative to the resistance of resistor R L , which is applied to the collector of transistor Q L2A through Q L2G . Because QLI and Q L2A through Q L2G are each configured as a one-toone current mirror the noise attributable to QL2 A through Q L2G and to the resistor R L are also reflected into node 16. All the noise sources in the circuit of Figure 3 relative to the active load can be analyzed as if they were applied to node 16 as shown is Figure 7. The emitter of Q L1 is coupled to the voltage supply V CC . The collector of transistor Q L1 is coupled to the loading node 16 of circuit 12. The base of transistor Q L1 is coupled to each base and collector of transistor Q L2A through Q L2G and to one terminal of the resistor R L . The emitter of each transistor Q L2A through Q L2G is coupled to the voltage supply V CC . The other terminal of the resistor R L is coupled to ground 14. The collector of NPN transistor Q₁ is coupled to the node 16, the base to a biasing voltage V B and the emitter is coupled to the collector of NPN transistor Q₂. The base of transistor Q₂ is driven by an input voltage V IN . V IN is controlled by the remainder of the application circuit and photodiode not shown in Figure 7. The emitter of transistor Q₂ is coupled to a DC voltage supply V E . Ten current supplies are thus shown coupled between node 16 and AC ground 15. Those current supplies are I NQL1 , I NQL2A through I NQL2G , I NQ2 and √ 4kTR L / R L which are coupled between the node 16 and AC signal ground 15. By applying Ohm's law and relying upon the fact that R L » 1/g mQL2 the noise current attributable to the resistor R L is approximately equal to the square root of 4kTR L divided by R L . Because the introduction of noise is a random occurrence the statistical value of the noise appearing at node 16 is given by the square root of the sum of the squares of each individual noise source. Thus, the noise IN is described by the equation: Because the transistors Q L2A through Q L2G are designed to be identical the current through each of the transistors Q L2A through Q L2G must be identical so that I NQL2A = I NQL2B = · · · = I NQL2G . Therefore, the equation above can be written as: or in general; in the above n=7 Because of the current mirror configuration of the active load circuit, the current through each of the transistors Q L2A through Q L2G is identical to the current through transistor Q L1 . It is clear, therefore, that the noise power for each of the transistors Q L2A through Q L2G is reduced by 1/7² (the number of transistors Q L2A through Q L2G ) upon being reflected through the current mirror of transistor Q L1 and Q L2A through Q L2G . For the same reason, the noise power associated with resistor R L is also reduced by 1/7². If I QL1 is selected to be 5µA and V CC = 5V, R L must equal 122.9KΩ. I N = 1.85 pA/√ Hz . For a similar 5µA current the prior art circuit would have a noise current I N ≈ 2.19 pA/√ Hz . This is 84% of the noise from the active load circuit of the prior art. The noise was lowered by 1.5 dB. Note by increasing n noise (I N ) will decrease. An alternative embodiment of the present invention is shown in Figure 8. The circuit of Figure 8 utilizes the same application circuit 12 as used in Figure 1 and Figure 3. The active load circuit shown in Figure 8 includes a voltage supply V CC a plurality of transistors Q L1A through Q L1D , a plurality of transistors Q L2A through Q L2D , a load resistor R L , a biasing resistor R W and a circuit ground 14. Each of the transistors Q L1A through Q L1D and Q L2A through Q L2D are PNP transistors. The emitter of each of the transistors Q L2A through Q LID is coupled to a terminal of biasing resistor R W . Each collector of transistors Q L1A through Q L1C is coupled to ground. The collector of transistor Q L1D is coupled to loading point 16. The base of each of the transistors Q L1A through Q L1D is coupled to each base and each collector of transistor Q L2A through Q L2D . The emitter of each of the transistors Q L2A through Q L2D is coupled to the second terminal of biasing resistor R W and to the voltage supply V CC . The collector of each of the transistors Q L2A through Q L2D is coupled to resistor R L . Resistor R L is also coupled to circuit ground 14. Each of the transistors Q L1A through Q L1D and Q L2A through Q L2D are preferably designed to be identical. The same assumptions and reasoning used to derive the noise power factor I N in the preferred embodiment circuit of Figures 3-7 are applied to derive the noise power factor for the alternate embodiment of the present invention shown in Figure 8. A noise power source is coupled across each of the transistors Q L1A through Q L1D , Q L2A through Q L2D , Q₁ and Q₂. As described above, the noise source across Q₁ has no effect on the output of the circuit due to the high beta of the transistors. Two voltage noise sources are coupled in series with resistor R W and resistor R L , respectively. Each of the noise sources is reference to a DC voltage level and as such can be analyzed with reference to an AC signal ground 16. The transconductance of the circuit is affected by the value of biasing resistor R W . The current through each transistor Q L2A through Q L2D is 25µA. The current through each transistor Q L2 is greater than the current through each transistor Q L1 because of the biasing resistor R W . The transconductance of the transistors Q L1A through Q L1D , g mQL1 , is 20µA/kT/q. The transconductance of the transistors Q L2A through Q L2D , g mQL2 , is 100µA/kT/q. The current I NQ2 is the sum of the noise through each of the transistors Q L2A through Q L2D . The noise current for the circuit of Figure 8 is: where n = number of transistors Q L1 and Q L2 . In Figure 8, n=4. If the collector current through each transistor Q L2A to Q L2D = 25µA then by setting R L = 43KΩ and V CC = 5v, with R W = 2000Ω then the collector current through transistor Q L1D = 5µA. Thus, I N = 1.69 pA/√ Hz . This is 77% of the noise current in the prior art circuit. This is a 2.25 dB reduction. It is clear from the foregoing discussion that the noise introduced from the active load can be reduced by increasing the number of transistors in parallel in the active load circuit. The present invention may be practiced without identically duplicating the resistor or transistor values or without duplicating the number of parallel load transistors show in the examples above. Many alternative implementations maybe utilized which embody the basis of the present invention. It is important that the bipolar transistor voltage V BE be matched for each of the transistors Q L1A through Q L1N and for transistors Q L2A through Q L2N (where N is the number of Q L1 or Q L2 transistors). By appropriate selection of transistors it is possible to practice the present invention with discrete components. The present invention is ideally suited to be manufactured by monolithic integrated circuit techniques. The present invention is better practiced by building individual transistors on an integrated circuit and coupling them as shown in the circuits of Figure 3 or Figure 8. However, the preferred method of forming these transistors is to form transistors Q L1A through Q L1N with a single emitter diffusion, a single base diffusion and N collector diffusions formed in the base diffusion, one collector for each transistor. Q L2A through Q L2N are similarly formed. This latter technique clearly reduces the amount of surface area utilized on the integrated circuit for the active load over the prior art technique of adding a large resistance. An improved low noise integrated active load has been disclosed for bipolar integrated circuits.

Claims: A low noise integrated active load circuit comprising: a. a first terminal (V CC ); b. a second terminal (14); c. a third terminal (16); d. a first bias resistor (R L ) having a first resistor terminal and a second resistor terminal said first resistor terminal coupled to said second terminal; e. a first transistor (QL1A-D) having a first collector, a first base and a first emitter, said first emitter coupled to said first terminal and said first collector coupled to said third terminal; and f. a plurality of second transistors ( QL2A-G ) each having a second collector, a second base and a second emitter, each of said second emitters coupled to said first terminal, each of said second bases coupled to said first base, to each of said second collectors and to said second resistor terminal. The low noise integrated active load circuit according to claim 1 wherein said first terminal is coupled to a voltage supply. The low noise integrated active load circuit according to claim 1 or 2 wherein said second terminal is coupled to a ground potential. The low noise integrated active load circuit according to claim 1,2 or 3 wherein said third terminal is coupled to an external circuit (12)> The low noise integrated active load circuit according to claim 4 wherein said first transistor and each of said second transistors is a PNP bipolar transistor. The low noise integrated active load circuit according to claim 5 further comprising a third transistor (Q L1A-C , fig 8) having a third collector, a third base and a third emitter, said third transistor being a PNP transistor, said third emitter coupled to said first emitter, said third base coupled to said first base and said third collector coupled to said second terminal. The low noise integrated active load circuit according to claim 4 wherein said first transistor and each of said second transistors is an NPN bipolar transistor. The low noise integrated active load circuit according to claim 7 further comprising a third transistor (Q LIA-C ) having a third collector, a third base and a third emitter, said third transistor being an NPN transistor, said third emitter coupled to said first emitter, said base coupled to said first base and said third collector coupled to said second terminal. The low noise integrated active load circuit according to any preceding claim wherein a second bias resistor (R W ) is coupled between said first emitter and said first terminal.

Inventors: QUAN, RONALD
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1988
Main classification: H03F1
IPC codes: H03F3, H03F1, G05F3