SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract: A semiconductor integrated circuit device is pro­ vided which comprises a first charge pumping circuit (1) comprising a plurality of MOS transistors (T1, T2, ..., Tn) cascade-connected between an input voltage node (IN1) and a booster output node (OUT1), where, of all associated nodes, those odd-numbered nodes receive one (1) of first and second clock signals (1, 2) through a corresponding capacitor (C1) and those even-numbered nodes (N1, N3, ... Nn-2) receive the other clock signal (2) through a corresponding capacitor (C2), a second charge pumping circuit (2) comprising a plurality of MOS transistors (T1a, T2a, ..., Tna) cascade-connected bet­ ween the input voltage node (IN1) and the booster output node (OUT2) and equal in number to those of the first charge pumping circuit (1) where, of all associated nodes, those odd-numbered nodes (N2a, N4a, ..., Nna-1) receive one (2) of first and second clock signals (1, 2) through a corresponding capacitor (2) and those even-numbered nodes (N1a, N3a, ..., Nna-2) receive the other clock signal (1) through a corresponding capaci­ tor (C4) and the gates of the respective MOS transistors (T1a, T2a, ..., Tna) are connected to the gate of the corresponding MOS transistors (T1, T2, ..., Tn), and a high resistive element (3) connectd to an output ter­ minal of said first charge pumping circuit (1).

Description: The present invention relates to a semiconductor IC (integrated circuit) device including an internal booster circuit for internally boosting up a power source voltage as supplied from an outer voltage source. An electrically erasable, programmable read only memory (EEPROM) requires a high voltage of, for example, about 20 V for data alteration and erasure of memory cells. A recent EEPROM is designed to internally boost up a power source voltage (usually 5 V) coming from an outer source, not to directly use an external high voltage. Since the user need not prepare any high voltage source, the EEPROM becomes more user-friendly. Fig. 1 shows a conventional charge pumping circuit which is employed as an internal booster circuit for EEPROM. Between input voltage node IN and booster output node OUT a plurality of N channel enhancement type MOS (insulated gate type) transistors T1 to Tn are cascade-circuited each having its gate connected directly to its drain. A clock signal 1 of a first phase is supplied via capacitor C1 to the node of each of the odd-numbered transistors T1 to Tn, while a clock signal 2 of a second phase is supplied via capacitor C2 to the node of each of the even-numbered transistors. Respective capacitors C1 and C2 have a common capacitive values. As will be appreciated from Fig. 2, the clock signals 1 and 2 are not synchronized with each other and their amplitude level is equal to that of power source voltage V DD , noting that the power source voltage V DD is applied to input voltage node IN. In the internal booster circuit shown in Fig. 1, with the clock signal 1 at a high level, a voltage on node Ni is boosted up to the power source voltage V DD level when the clock signal 1 is supplied via capacitor C1 to that node. Transistor Ti whose gate is connected to node IN is turned ON and a voltage on a subsequent stage node Ni+1 is boosted up by a level: V DD - V TH - Q C where: V TH : the gate threshold voltage of transistor Ti, Q : the amount of charge transferred from node Ni to node Ni+1, and C : the capacitive value of capacitors C1, C2. With the clock signal 1 at a low level, transistor Ti is turned OFF. When the clock signal 2 goes high, a voltage on a subsequent stage node Ni+1 is boosted up by a level V DD . That is, upon receipt of the clock signals 1, 2, the booster circuit boosts up a voltage at a rate of V DD - V TH - Q C per pair of nodes. Through the repetitive charge pumping operation, a predetermined boost-up voltage output emerges on a final booster output node OUT. Since, in practice, the gate threshold voltage Vth of transistor Ti is increased by a back bias effect in the boost-up process, the booster circuit fails to boost up the voltage at a rate of V DD - V TH - Q C = 0 . Fig. 3 shows a relation between a current output supplied and a boost-up output of the charge pumping circuit. As shown in Fig. 3, a current output supplied becomes very small when the power source voltage V DD is small. There is an increasing tendency that EEPROMs will be incorporated into a portable electronic apparatus. A battery power source of about 3 V is usually employed in that application. For a voltage level lower than about 3 V (battery power source), however, the conventional internal booster circuit fails to exhibit an adequate current supply capacity. Prior art document IEEE Journal of Solid State Circuits, Vol. sc-19, No. 1, February 1984, pages 135-143, discloses a charge pump and regulator circuit. In this circuit a charge pump consisting a G-stage MOS transistors and connected to a first input node generates a nominal voltage of 24 V. This voltage is regulated down to prevent junction breakdown. The regulator connected to earth consists of eight MOS transistors which provide an output voltage of 20 V. A current mirror formed by three of these MOS transistors forces other MOS transistors to operate at nearly the same voltage. It is an object of the present invention to provide a semiconductor IC circuit equipped with an internal booster circuit which, upon driving EEPROM's with a low voltage source, such as a battery, can assure a high current supply capacity which has otherwise not been obtained in a conventional booster circuit. To solve this object the present invention provides a semiconductor integrated circuit device as specified in claim 1. A first charge pumping circuit comprises a plurality of MOS transistors cascade-connected between an input voltage node and a booster output node with the gate of the MOS transistor connected to the drain thereof, where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals of a different phase through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor. A second charge pumping circuit comprises a plurality of MOS transistors cascade-connected between the input voltage node and the booster output node and equal in number to those of the first charge pumping circuit where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals of a different phase through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor and the gate of the respective MOS transistors is connected to the gate of the corresponding MOS transistors. A high resistive element is connected to an output terminal of said first charge pumping circuit. Since, according to the present invention, the first charge pumping circuit is connected at its output terminal to the high resistive element and hence there is almost no external current loss, it is possible to obtain a considerably high boost-up voltage even if a low-voltage source is employed. Furthermore, the respective stage transistor of the second charge circuit is driven by a voltage on a corresponding stage node of the first charge pumping circuit and hence a high current supply capacity can be obtained from an output terminal of the second charge pumping circuit. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit showing a conventional booster circuit; Fig. 2 is a waveform diagram showing clock signals of a different phase to be applied to the internal booster circuit; Fig. 3 shows a relation between a boost-up voltage and an external supply current in the internal booster circuit; and Fig. 4 is a circuit diagram showing an internal booster circuit for an EEPROM according to the present invention. The embodiment of the present invention will be explained below in more detail with reference to the accompanying drawings. Fig. 4 shows an internal booster circuit incorporated into a semiconductor circuit, such as an EEPROM. In Fig. 4, 1 and 2 show first and second charge pumping circuits, respectively, with high resistive element 2 connected between a boost-up voltage output node OUT1 of first charge pumping circuit 1 and a ground potential terminal. First charge pumping circuit 1 comprises a plurality of MOS transistors T1 to Tn cascade-connected between input voltage node IN1 and output node OUT1 with their gate connected to a corresponding drain. Of nodes N1 to Nn-1 provided between transistor T1 and transistor Tn, those odd-numbered nodes Ni (i=1, 3, ...) receive a clock signal 1 of a first phase via capacitor C1 and those even-numbered nodes Ni (i=2, 4, ...) receive a clock signal 2 via capacitor C2. Second charge pumping circuit 2 comprises a plurality of MOS transistors T1a to Tna cascade-connected between input voltage node IN2 and booster voltage output node OUT2 and equal to those of first charge pumping circuit 1. Clock signals 1 and 2 are alternately applied, respectively via capacitors C1 and C2, to corresponding ones of nodes N1a to Nna-1 provided between transistors T1a and Tna. The gates of transistors T2a ... Tna in second charge pumping circuit 2 are connected to the corresponding gates of transistors T2 ... Tn in first charge pumping circuit 1. The same input voltage (usually a power source voltage V DD externally supplied from EEPROM) is applied to input voltage nodes IN1 and IN2 of charge pumping circuits 1 and 2, respectively. The gates of first stage transistors T1 and T1a are connected to input voltage nodes IN1 and IN2, respectively, and connected substantially in common with each other. The clock signals 1 and 2 are mutually not so overlapped with respect to each other as in the conventional circuit and have an amplitude level equal to the power source voltage V DD . The first charge pumping circuit 1 performs substantially the same operation as the conventional counterpart, but high resistive element 3 is connected to output node OUT1 and hence almost no outer current loss occurs. As a result, an amount of charge, Q, transferred from one transistor to another adjacent one is very small and a voltage V DD - V TH - Q C to be boosted at the respective stage node is nearly equal to V DD - V TH . Since, therefore, there is almost no external current loss, even if an input voltage V DD is as low as, for example, about 3 V, first charge pumping circuit 1 can obtain an adequate boost-up voltage as shown in Fig. 3. In second charge pumping circuit 2, the gates of transistors T2a ... Tna are connected to the gates of corresponding stage transistors in the first charge pumping circuit, in place of being connected to the drains of transistors T2a ... Tna in the second charge pumping circuit. As a result, a high gate voltage is applied to the gate of transistors T2a ... Tna as compared to the drain voltage on the side of input voltage node IN2. Since, of a boost-up voltage V DD - V TH - Q C , a voltage portion V TH never occurs, the boost-up voltage at the respective stage becomes V DD - Q / C and it is possible to obtain an adequate boost-up voltage output in the case of an amount of charge, Q, being greater, that is, in the case where there is a greater external current loss.

Claims: A semiconductor integrated circuit device equipped with an internal booster circuit, comprising: a first boost-up circuit (1) connected to a first input voltage node (IN1) to receive a power source voltage (V DD ); and a second boost-up circuit (2) including a plurality of MOS transistors (T1a ... Tna), characterized in that the gates of said MOS transistors (T1a ... Tna) receive a voltage boosted up by the first boost-up circuit (1) and adapted to compensate for a voltage-drop resulting from a respective threshold voltage of the MOS transistors (T1a ... Tna); and a high resistive element is connected to an output node (OUT1) of the first boost-up circuit to prevent a current loss from the first boost-up circuit (1) to an outside. The semiconductor integrated circuit device according to claim 1, in which said first boost-up circuit constitutes a first charge pumping circuit (1) comprising a plurality of MOS transistors (T1 ... Tn) connected in a cascaded fashion and connection nodes (N1 ... Nn-1) between the MOS transistor (T1) and the MOS transistor (Tn) serve as a plurality of boost-up stages and said second boost-up circuit constitutes a second charge pumping circuit constitutes a second charge pumping circuit (2) comprising a plurality of cascade-connected MOS transistors (T1a ... Tna) equal in number to those of said first charge pumping circuit (1) and the respective gate of said MOS transistors (T1a ... Tn-1) receives a corresponding boost-up voltage from a corresponding one of said connection nodes (N1 ... Nn-1) of said first charge pumping circuit. The semiconductor integrated circuit device according to claim 2, in which said boost-up circuit (1) constitutes an internal boost-up circuit comprising a plurality of MOS transistors (T1 ... Tn) cascade-connected between said first input node (IN1) and said high resistive element (3) with the gate of the MOS transistor connected to the drain of the same transistor, in which, of nodes (N1 ... Nn-1) between the MOS transistor (T1) and the MOS transistor (Tn), those odd-numbered nodes receive one of first and second signals of a different phase through a corresponding capacitor (C1 or C2) and those even-numbered nodes receive the other signal through a corresponding capacitor (C2 or C1). The semiconductor integrated circuit device according to claim 2, in which said second boost-up circuit constitutes a charge pumping circuit (2) comprising said plurality of MOS transistors (T1 ... Tn) cascade-connected between a second input voltage node (IN2) and a second booster output node (OUT2) and equal in number to those of said first boost-up circuit, in which, of nodes (N1a ... Nna) provided between the MOS transistor (T1a) and the MOS transistor (Tna), those odd-numbered nodes receive one of first and second signals of a different phase through a corresponding capacitor (C1 or C2) and those even-numbered nodes receive the other signal through a corresponding capacitor (C2 or C1) and the respective gate of said MOS transistors (T1a ... Tna) is connected to a corresponding boost-up stage of said first charge pumping circuit (1).

Inventors: TSUJIMOTO, JUN-ICHI PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: H02M3
IPC codes: H02M3, H01L29, H01L21, H01L27