CHIP TEST CONDITION SELECTION APPARATUS

Abstract: A microprocessor integrated circuit chip includes a plurality of functional areas containing a large number of widely distributed signal sources. An on-chip selection network is distributed on the chip which enables the selection of signals from the large number of sources under microinstruction control without any decrease in chip performance. The network includes an access bus which is distributed to the functional areas as a function of the concentration of signals provided by the sources. Individual decoders are strategically located on the chip and connect in common to a control bus. Each decoder connects to a plurality of switches for linking the sources of a functional area to the access bus. A selector circuit terminates the access bus at one end. Under microprogram control, the selector circuit is enabled to select which final source signal is applied to the functional area containing branching circuits for selecting a next microinstruction to be executed by the microprocessor.

Description: BACKGROUND OF THE INVENTION Field of Use This invention relates to integrated circuit chip devices and more particularly to selecting signals from a plurality of sources located on an integrated circuit chip. Prior Art As well known, today's integrated circuit chips are becoming more and more complex as they are designed to provide greater processing capabilities. In the case of microprocessor chips, a particularly complex area is the branch control or address generation circuitry. These circuits are required to select an address specifying the next instruction to be executed by the microprocessor. In order to provide flexibility, such selection is based upon the occurrence of conditions occurring within a current processing cycle of operation. The conditions correspond to signals received from other sections or parts of the microprocessor chip. In the past, such next address generation or branching circuits have been implemented using combinations of matrices or multiplexer circuits. An example of such an arrangement is disclosed in U.S. Patent No. 3,955,180. While this approach has been useful in implementing microprogrammed processors constructed from discrete components, it can be wasteful of chip area unless the sources of the signals requiring examination are concentrated within a few areas. From US-A-4 414 625 the preselection of condition signals from different signal groups by multiplexers with a subsequent selection of a single condition signal is known. Thus, it has been found that in complex chips where large numbers of signal sources requiring examination are widely distributed over the entire area of the chip, large areas normally have to be allocated for making such signal selections. Chip space requirements are further increased where the chip includes several processing elements. An example of such an arrangement is disclosed in the related patent of Thomas F. Joyce, et al. entitled, "Multiprocessors on a Single Semiconductor Chip", EP-A-0 197 559, filed on April 10, 1986. Accordingly, it is a primary object of the present invention to provide an apparatus which permits the on-chip selection of signals generated by a large number of widely distributed sources. It is a further object of the invention to provide an apparatus which permits on-chip signal selection without any decrease in microprocessor performance. The above objects are achieved by the apparatus of the present invention set out in claim 1. The present invention provides for the on-chip selection of signals received from a large number of sources which are distributed throughout the area of a microprocessor integrated circuit chip. In the preferred embodiment, the area of the chip is divided into a plurality of functional areas or regions. A decoder circuit is strategically located in at least one functional area as close as possible to the sources of signals within the area. A plurality of lines of an access bus are distributed throughout the chip functional areas as a function of the concentration of the source signals within each area for transmitting the source signals to a predetermined part of the chip for final selection. The apparatus of the invention further includes a number of pluralities of linking switches, each plurality for connecting the sources of a functional area to the access bus. The linking switches which are constructed from pass transistors are enabled by signals from its associated decoder circuit to apply source signals to the access bus lines. Each decoder circuit is connected in common to a control bus which distributes a set of control signals to all decoder circuits. In the preferred embodiment, the set of control signals corresponds to a predetermined portion of a test control field of the chip's microinstruction word. To facilitate layout and performance efficiency, the control bus is positioned adjacent to the access bus. At the rear of back part of the chip, the access bus lines are terminated in a selector circuit. The selector circuit, in response to signals from an associated selector decoder circuit, selects the final output signal from one of the sources specified by the test control field for use by the chip's address generation circuits in selecting the next microinstruction to be executed by the microprocessor. In the preferred embodiment, the selector decoder circuit is connected to receive other signals from the test control field in addition to signals from indicator storage circuits which define the type of operation currently being performed by the microprocessor. This is done in order to service local conditions and to resolve any testing conflicts. In the preferred embodiment, the microprocessor chip includes separate processors for executing binary, decimal and floating point operations. The types of operations performed by these processors are described in the related copending patent application of Thomas F. Joyce, et al. titled, "Microprocessors on a Single Semiconductor Chip". In operation, in response to the control signals applied by the control bus, the decoders associated with the areas, enable their respective linking switches to apply signals from the corresponding sources to different predetermined ones of the access bus lines for final selection by the selector circuit. In the preferred embodiment, as a function of the type of operation being performed and the states of the signals from the test control field, the selector decoder generates an output signal which conditions the selector circuit to select the bus access line which is to provide the final source signal to be examined or tested by the microprocessor next address generation circuits. Additionally, the selector circuit also includes input means for enabling the selection of signals from local sources which do not require connection to the access bus. Thus, the arrangement of the present invention also provides for the selection of signals from localized as well as remotely located sources. The arrangement of the present invention reduces considerably, the chip area required to carry out the selection of a source signal from the large number of sources widely distributed throughout the chip. Since each line of the access bus can be assigned a number of source signals, this provides additional flexibility. In the preferred embodiment, the number of source signals which can be connected to each line corresponds to 2 n wherein n is the number of bits of the test field decoded by the decoder circuits. The use of redundant decoder circuits minimizes the number of interconnections required to be made to the decoder output lines. It has been found that the use of such strategically placed decoder circuits minimizes the amount of chip area in contrast to having to distribute the output lines of a single decoder. It will be appreciated that the arrangement of the present invention provides for a large number of possible source signal selections corresponding to the number of bus access lines times 2 n . While not all of the possible assignments of each line may be required, the arrangement provides added flexibility in handling source signal conflicts. The number of lines included in the access bus corresponds to the maximum number of signals which can occur within a given microprocessor cycle of operation. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying drawings. DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram illustrating the floor plan or layout of the chip which incorporates the teachings of the present invention. Figure 2 shows in greater detail, the construction of the chip of Figure 1. Figure 3 shows in greater detail, the organization of the on-chip selection apparatus of the present invention. Figures 4a through 4d show in greater detail, different portions of the apparatus of the present invention shown in Figure 2. Figure 5 shows the microinstruction word format used in conjunction with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 illustrates the functional layout of an integrated circuit microprocessor chip 10 which incorporates the principles of the present invention. Chip 10 includes within it a plurality of defined functional areas or sections containing the different functional elements which comprise microprocessor 10. As shown, the major functional areas or sections include a prefetch area 10-1, a general, CIP and SIP indicator area 10-4, a register file area 10-5, a SIP area 10-8, a CIP area 10-10, a binary ALU and shifter area 10-12 and a counter area 10-14. Other areas of chip 10 include the ROS control area 10-20, a major branch area 10-22, a BP port area 10-24, in addition to data selection areas 10-7 and 10-13. The prefetch area 10-1 includes an instruction prefetch unit for prefetching instructions from a cache or main memory. The SIP area 10-8 includes a scientific instruction processor (SIP) for performing scientific operations involving floating point exponent operations, the CIP area 10-10 includes a commercial instruction processor (CIP) for performing commercial operations involving decimal operands and the binary add and shifter area 10-12 includes a binary processing unit and shifter unit for processing binary and hexadecimal operands. The indicator area 10-4 includes the indicators used by the binary, CIP and SIP processors. The register file area 10-6 includes file addressing circuits and a plurality of register files for storing operands, exponents and work register information. The counter area 10-14 includes a program counter and five other counters used by the different processors. Major branch area 10-22 includes a branch unit for decoding instructions. ROS control area 10-20 includes the various register flip-flops for storing the bits of each microinstruction word read out of a read only store (ROS) located off chip and the next address logic circuits for generating the ROS address specifying the next microinstruction word to be read out from the ROS and transferred to chip 10 for execution. Area 10-20 also receives signals from a pair of mode flip-flops CF6 and CF7 which store information defining the type of operation being performed by microprocessor chip 10. The CF6 and CF7 flip-flops are part of a CF (0-7) register which resides in indicator area 10-4. The CF6 and CF7 flip-flops are used by ROS control area 10-20, for purposes not related to testing, as well as by the test branch area 10-30. In addition to the above, chip 10 of the preferred embodiment includes a test branch area 10-30. As shown, the front of this area runs vertically along functional areas 10-6 through 10-14 and has two legs which extend outward in a horizontal direction at points located near the middle and at the rear of chip 10. The first leg is located adjacent to functional areas 10-2 and 10-4 while the second leg is located near functional areas 10-20 and 10-22 as shown. The test branch area is located close to the signal sources included within the functional areas as a function of the concentration of the signals being provided by the sources. The rear portion of test branch area 10-30 is positioned close to ROS control area 10-20 which receives the final output signal provided by the selection circuits of the present invention included within area 10-30. Figure 2 shows in greater detail, the construction of certain portions of chip 10. The various functional areas are designated by the same reference numbers as used in Figure 1. The various elements included within test branch area 10-30 are also outlined in Figure 2. These elements are illustrated in schematic form in Figure 3. As seen from Figures 2 and 3, the test branch area 10-30 includes a 17 line access bus 10-300, a control bus 10-301, a back end selector circuit 10-302, a back end selector decoder circuit 10-304, a plurality of decoder circuits 10-306a through 10-306e and a plurality of linking switches 10-308a through 10-308f. A different one of the decoder circuits 10-306 is strategically located adjacent a different functional area as shown in Figure 3. The linking switches 10-308 are positioned adjacent to each decoder close to the signal sources. These switches are used to link or connect the signal sources within a functional area to access bus 10-300. Each of the decoder circuits 10-306a through 10-306e connect in common to control bus 10-301 at different points as shown. Signals corresponding to ROS data register bits 6-8 are applied to control bus 10-301 from the flip-flop register stages of a ROS data register which are distributed along the periphery of chip 10 as shown in Figure 1. The back end selector 10-302 terminates access bus 10-300 as shown and is connected to receive as inputs, the outputs of selector decoder 10-304. Additionally, the selector 10-302 has additional inputs which connect to local signal sources included within major branch area 10-22. The selector decoder 10-304 is connected to receive as inputs, signals corresponding to ROS data register bits 3-8 from area 10-20 and signals equivalent to those of mode control flip-flops CF6 and CF7 from indicator area 10-4. As seen from Figures 2 and 3, the arrangement of elements which comprise the on-chip selector network of the present invention simplify chip layout while at the same time are constructed so as not to affect microprocessor performance. In greater detail, with reference to Figure 2, the lines of the access bus 10-300 and control bus 10-301 are constructed from metal lines. The line connections between the linking switches 10-308 and access bus 10-300 are constructed from polysilicide material eliminating the need for an additional chip layer while still providing the required transmission speed. The specific series of related images which represent the three dimensional pattern or topography of semiconductor chip 10 do not form a part of the present invention but are protected as a mask work under the Semiconductor Chip Protection Act of 1984. Different ones of the elements of Figures 2 and 3 are shown in greater detail in Figures 4a through 4d. More particularly, Figure 4a shows a representative portion of link switches 10-308e which includes a plurality of enhancement FET devices or pass transistors 10-3082 through 10-3088. Each FET connects or links a different source within the prefetch unit to one of the access bus lines TBR0 through TBR16. As shown, more than one source (i.e., FR0 through FR12) can be connected to the same access bus line (i.e., TBR0). The maximum number of sources which can connect to a single line is a function of the number of decoder outputs or 2 n where n is the number of control bus inputs. The control terminal of each pass transistor connects to one of the output terminals of its associated decoder (i.e., 10-306e). Figure 4b illustrates a representative section of decoder 10-306. As shown, decoder 10-306 is constructed as a programmable logic array (PLA) using enhancement, native and depletion mode FETS. The signals corresponding to RDR bits 6-8 are decoded to produce an output on any one of eight output lines SEL0 through SEL7. Figure 4c illustrates the construction of selector decoder 10-304. The input signals from the mode control flip-flops and RDR register stages CF6 through RDR8 are applied to a corresponding number of input buffer circuits. These circuits produce pairs of complementary outputs which are applied to the control terminals of certain enhancement mode FETS arranged in a matrix array. The decoder 10-304 decodes the eight input signals into 23 unique outputs for enabling selector 10-302 of Figure 4d. As seen from Figure 4d, selector 10-302 includes a plurality of enhancement mode FETS, each having its control terminal connected to a different one of the outputs of selector decoder 10-304 and its drain terminal connected to either a different one of access bus lines 10-300 or one of the local sources within major branch area 10-22 as shown. The source terminal of each FET connects in common to the input of a buffer circuit which also connects to a voltage source VCC through a depletion FET as shown. The buffer circuit is connected to provide an output signal on output line TB which corresponds to the selection of a final signal source. The line TB connects as an input to the microprocessor's next address logic circuits. The numerical values included in Figures 4a through 4d represent the ratios selected for constructing the different FETS to meet the desired performance requirements of chip 10. For the purpose of the present invention, the circuits shown in Figures 4a through 4d can also be constructed from standard integrated circuit elements. DESCRIPTION OF OPERATION The operation of the on-chip test selector network will now be described with particular reference to Figures 2 and 3 and the microinstruction word of Figure 5. As previously mentioned, the on-chip selector of the present invention is designed to select for testing, a single condition from a large number of possible conditions. In the preferred embodiment, there are approximately 103 different conditions provided from a number of widely distributed sources which are required to be examined. From an analysis of these conditions, it was determined that a maximum of 17 conditions are required to be examined within a current cycle of operation. Accordingly, test conditions were assigned to different lines of access bus 10-300 as indicated in the following table. The above abbreviations are used to designate the following functional units: Prefetch Unit = PFU Gen, Indicators = GIND CT Counters = CTCTRS Mode File = MF Binary ALU = BALU DP Counters = DPCTRS Shifter = SHFT Commercial Inst. Proc. = CIP Scientific Inst. Proc. = SIP Control Flops = CF * Designates negation of signal. In accordance with the present invention, each line of access bus 10-300 is arranged to be selected as a function of the states of mode control flip-flops CF6 and CF7 and RDR bits 3-6. The selection of these lines is accomplished as shown in the following table. During each cycle of operation, the off-chip ROS reads out a 67-bit microinstruction word which includes a test selection field shown in Figure 5. This word is transferred to the RDR register stages within chip 10. RDR bits 6-8 are applied to the lines of control bus 10-301. In response to the states of RDR bits 6-8, each of the decoders 10-306a through 10-306e is identically enabled to force the same one of its output terminals to a binary ONE state. This in turn enables each of the FET pass transistors connected to that decoder output terminal within each of the linking switches 10-308a through 10-308f to connect its associated signal source to a corresponding one of the access bus lines TBR0 through TBR16. The conditions are assigned so that only one source is enabled to provide a signal to an access bus line even when more than one source is connected to the same line. The signals from the selected sources are transmitted along bus 10-300 and are received by back end selector 10-302 as seen from Figure 3. At this time, signals from local sources are also applied to other inputs of selector 10-302. The selector decoder 10-304 is conditioned by another portion of the test field of the microinstruction word of Figure 5 which corresponds to RDR bits 3-5 and the states of control flip-flops CF6 and CF7 to select the access bus line and connected signal source which is to provide the final output signal to be tested. For example, when RDR bits 6-8 have the value "02", decoder 10-306e causes one of the pass transistors of linking switches 10-308e to connect as a source, register stage FR8 of the microprocessor's prefetch unit to line TBR0. At the same time, decoder 10-306e causes an overflow flip-flop BALUOVF to be connected as a source to line TBR1. The other sources assigned the value "02" are also connected to the lines as specified in the line assignment table. When states of mode control flip-flops CF6 and CF7 are 00 and RDR bits 3-5 are also ZEROS, selector 10-302 is enabled to select line TBR0 as shown in the select code table. As seen from this table, the state of RDR bit 6 is used only in four cases where there are condition conflicts. The other RDR bits 7 and 8 are used in the selection of signals from the local sources contained in major branch area 10-22. The selection is made as illustrated in the following table. From the above, it is seen how the present invention is able to provide on-chip selection of test conditions based upon signals received from a large number of sources widely distributed over the area of a microprocessor chip. The invention by employing redundant decoders strategically placed within different functional areas of the chip reduces the amount of chip area devoted to interconnections. The buses and the lines connecting the signal sources utilized by the invention are selected so as to maximize microprocessor performance. It will be obvious to those skilled in the art that many changes may be made to the preferred embodiment. For example, the locations and number of decoders and other elements of the selector of the present invention may be varied as a function of the chip's organization and the type of signals being selected for testing.

Claims: Selection circuit on an integrated circuit chip including a plurality of functional sections for providing different functions of a processor, each such section generating a plurality of signals; said selection circuit comprising a plurality of decoders (10-306 a-e), each decoder being disposed proximate to a respective one of said functional sections, each such decoder receiving a plurality of control signals (RDR 6-8) at a corresponding plurality of input leads and delivering an output signal (SEL 0-7) on one of a plurality of output leads; a control bus (10-301) distributed on said chip for connection to the input leads of all of said decoders for delivering said control signals (ROR 6-8) to said decoders; a multi-line (TBR 0-16) signal bus (10-300) distributed on said chip to be proximate to all of said functional sections; a plurality of switches (10-308 a-f), each switch being disposed proximate to a respective one of said functional sections, each of said switches being connected to receive the plurality of signals (MREG i, FR ij, etc.) generated by the respective functional section proximate thereto, each of said switches having a plurality of output leads connected to respective leads of said signal bus, and each of said switches being connected to the output leads of the decoder proximate to the respective functional section and controlled by the output signals delivered on said decoder output leads to transmit selected ones of said respective functional section signals to said signal bus leads; and a selector (10-302) having a plurality of input terminals connected to respective leads of said signal bus, a plurality of control terminals connected to receive respective control signals (SQWT, SAWS, etc.), and an output lead (TB); said selector being controlled by the control signals received at the control terminals thereof to transmit the signal carried by a selected one of the leads of said signal bus to said selector's output lead (TB). The selection circuit of claim 1 further comprising selector decoder means being located adjacent to said selector and adjacent to at least one of said functional sections, said selector decoder means being connected to said selector and to receive control signals and said selector decoder means in response to said control signals, enabling said selector to select said output signal from one of said plurality of signals selected for connection to said signal bus for application to said one of said functional sections. The selection circuit of claim 2 wherein said one functional area includes address generation logic circuit means and a predetermined number of said signal bus lines corresponds to the maximum number of conditions which are required to be tested within a microprocessor cycle of operation for the generation of a next address by said address generation logic circuit means as a function of said output signal. The selection circuit of claim 1 wherein each of said decoders has a plurality of outputs, said plurality corresponding to the maximum number of different signals which are assignable to each of said predetermined number of signal bus lines and wherein said apparatus further includes conductor means for selectively connecting predetermined ones of said decoder outputs to different ones of said plurality of switches for applying signals from corresponding ones of said signals to said signal bus lines for testing without conflict conditions within said functional sections. The selection circuit of claim 4 wherein each of said switches include a FET pass transistor having input and a pair of output terminals, each input terminal being connected to a different one of said decoder outputs and a different one of said pair of output terminals being connected to one of said signal bus lines and to one of said signals respectively, said pass transistor in response to an enabling signal from said decoders, connecting said signal to said one signal bus line to enable testing of a condition generated by said signal. The selection circuit of claim 5 further comprising a corresponding number of conductor lines, each conductor line connecting said different one of said output terminals to said signals. The selection circuit of claim 2 wherein said selector is located adjacent to another one of said functional sections which includes a plurality of local signals, said selector having a first plurality of inputs, each input connected to a different one of said signal bus lines and a second plurality of inputs, each input being connected to a different one of said plurality of local signals, said selector being enabled by said control signals to select said output signal from said plurality of local signals in addition to said signals connected to said signal bus. The selection circuit of claim 9 wherein said another one of said functional sections contains branching circuits. The selection circuit of claim 1 wherein said signal bus lines are distributed over a predetermined rectangular shaped area extending from the front to back of said chip.

Inventors: HESLIN, PETER M.
Applicants: BULL HN INFORMATION SYSTEMS INC.
Application year: 1988
Main classification: G06F9
IPC codes: G06F9