HIGH-SPEED ELECTRONIC CIRCUIT HAVING A CASCODE CONFIGURATION

Abstract: Disclosed is a high-speed electronic circuit having a cascode circuit configuration and provided with a bias current source (CS0) between an emitter and a base of a load transistor (Q) in the cascode circuit configuration for compensating a base-emitter voltage (VBE) of the transistor to eliminate an adverse affect of a charging and discharging at a stray capacitor (C) which can be connected between the base and the emitter of the transistor. An interface circuit, a level shift circuit, a level shift discrimination circuit, a signal distribution circuit, a signal synthesization circuit and a frequency band control circuit, which are applied by the high speed electronic circuit, are also disclosed.

Description: DESCRIPTION High-speed Electronic Circuit Having a Cascode Configuration Technical Field * The present invention relates to an electronic 5 circuit having a cascode configuration. More * * particularly, it relates to an electronic circuit able to operate at a high speed and/or having a wide frequency band. Background Art 10 Recent technology advances in data processing systems, such as high speed data communication systems, require improved electronic circuits able to process data at a high speed and/or at a wide frequency band. In particular, for example, in an optical-fiber data 15 communication system, a very high speed data transmission of more than 1.6 giba-bits per second (Gbs) has been attempted, to increase a transmission " rate to a propagation speed limit of an optical fiber cable which has a very wide frequency range. 20 To achieve a high speed operation, a wide frequency margin, and a high stability, a variety of consideration, such as a careful selection of circuit elements applied to such electronic circuits, a design of a best circuit arrangement, a rejection of adverse 25 affects by, for example, a stray capacitance and a stray inductance, must be taken into account. Various types of electronic circuits have been applied to such high ^ speed data transmission systems, as an interface circuit, a level shift circuit, a discrimination 30 circuit, etc. However, these prior art electronic circuits still do not provide a satisfactory performance. The prior art electronic circuits will be described with reference to specific examples. DISCLOSURE OF THE INVENTION 35 An object of the present invention is to provide an improved electronic circuit having a high speed operation time, a wide frequency range and/or a great stability. Another object of the present invention is to provide an improved interface circuit able to operate at a high speed. Still another object of the present invention is to provide an improved level shift circuit having a great stability at a high frequency range. Yet another object of the present invention is to provide an improved discrimination circuit able to discriminate a signal level with a high accuracy. Another object of the present invention is to provide an improved signal distribution circuit having many fan-outs. Another object of the present invention is to provide an improved signal synthesization circuit having many fan-ins. Another object of the present invention is to provide an improved frequency band control circuit having a wide frequency controllable range. According to a first aspect of the present invention, there is provided a high speed electronic circuit including: a current drive circuit including at least one input transistor, an emitter thereof being operatively grounded and a base thereof receiving an input signal; a load transistor circuit including at least one load transistor, an emitter thereof being connected to a collector of the input transistor and a base of the load transistor being operatively grounded; and a bias current source connected to the emitter, a current supplied from the bias current being supplied to the load transistor to maintain a base-emitter voltage of the load transistor when the load transistor is turned off at a base*emitter transistor of the load transistor when the load transistor is turned on. The bias current source comprises a current-mirror type current source circuit connected between the emitter of the load transistor and ground. Or, the bias current source comprises at least one resistor connected between the emitter of the load transistor and ground. The high speed electronic circuit, further includes a bias voltage source connected between the base of the load transistor and ground. According to a second aspect of the present invention, there is also provided an interface circuit including at least one load resistor in addition to the high speed electronic circuit, the load resistor being connected to a collector of the load transistor for outputting a voltage signal corresponding to the input signal, and at least one transfer line connected between a collector of the input transistor in the current drive circuit and the emitter of the load transistor. The input signal is a data signal logically changing between a high level and a low level. The current drive circuit includes an input transistor and a input resistor, a base of the input transistor receiving the input signal, and the input resistor being connected between an emitter of the input transistor and ground. The load transistor circuit includes a load transistor, an emitter thereof being connected to a collector of the input transistor, and a collector thereof being connected to the load resistor to output the output signal from a point at which the collector and the load resistor are commonly connected. The current-mirror type current source circuit includes a first current source transistor a collector of which is connected to the emitter of the load transistor, a first current source resistor supplied with a power supply at a first terminal thereof, a second current source transistor a collector of which is connected to a second terminal of the first current source resistor and a base thereof, bases of the first and second current source transistors being commonly connected, and second and third current source transistors connected between emitters of the first and second current source transistors and ground, respectively. Or, the current source circuit includes a current resistor connected between the emitter of the load transistor and ground. The current drive circuit includes first and second input transistors connected in parallel and differen¬ tially-operating in response to two input signals connected to bases thereof, and a current source connected between emitters of the first and second input transistors and ground. The load transistor circuit includes a first and second load transistors, an emitter of the first load transistor being connected to a collector of the first input transistor, an emitter of the second load ransistor being connected to a collector of the second input transistor, and bases of the first and second load transistors being commonly connected and operatively grounded. The interface circuit also include two load resistors connected to collectors of the first and second load transistors, respectively, to output two output signals from points at which collectors and the load resistors are commonly connected. The current-mirror type bias current source circuit includes first to third current source transistors connected in parallel, collectors of the first and second current source transistors being respectively connected to the emitters of the first and second load transistors, a first current source resistor supplied with a high voltage power supply at a first terminal, a second terminal thereof being connected to a collector of the third current source transistor, a base of the third current source transistor being connected to a base thereof, which is commonly connected to bases of the first and second current source transistors, and second to fourth current source resistors respectively connected between emitters of the first to third current source transistors and ground. Or, the source circuit comprises two resistors connected between the emitters of the load transistors and ground, respectively. According to a third aspect of the present 5 invention, there is further provided a level shift -*> circuit, further including a load resistor circuit including at least one load resistor connected to collectors of the load transistor, in addition to the high speed circuit, and characterized in that the bias 10 current source connected between the emitter and the base of the load transistor includes at least one current source supplying current(s) passing through the load resistor, to shift a level of the output signal by a value defined by the current and a resistance of the 15 load resistor. Many modifications of the level shift circuit can be obtained similar to those of the interface circuit. According to a fourth aspect of the present invention, there is provided a signal discrimination 20 circuit further including a latch circuit in addition to the level shift circuit, the latch circuit being connected to the load resistor circuit, and wherein the current drive source is formed as a differential-operation type circuit, the load transistor 25 circuit comprises two load transistors connected in parallel and two current sources connected to the two load transistors for changing voltage drops as level shift values at the load resistors. According to a fifth aspect of the present 30 invention, there is provided a signal distribution circuit as an application of the electronic circuit, wherein each of a plurality of the load transistor circuits and each of a plurality of load resistors is connected in series, the series-connected circuits are 35 connected in series, the current drive circuit and the bias current source are connected in parallel each other and connected to an end of the circuits which are connected the load transistor circuits and the load resistors in series. Or, according to a fifth aspect of the present invention, there is also provided a signal distribution circuit as an application of the electronic circuit, wherein each of a plurality of the load transistor circuits and each of a plurality of load resistors is connected, the series-connected circuits are connected in parallel, the current drive circuit and the bias current source are connected in parallel, and connected to a commonly connected point of the parallel-connected circuits. According to a sixth aspect of the present invention, there is provided a signal synthesization circuit, as an application of the electronic circuit, wherein a plurality of the current drive circuits are connected in parallel, each current drive circuit receiving an input signal to be synthesized, the load transistor circuit and a load resistor is connected in series to output a synthesized signal, and the bias current source and the emitter of the load transistor in the load transistor circuit are connected to a commonly connected point of the parallel connected current drive circuits. According to a seventh aspect of the present invention, there is provided a frequency band control amplification circuit including: an amplification circuit including at least one amplification transistor and at least one emitter resistor connected between an emitter of the amplification transistor and ground, a base of the amplification transistor receiving an input signal; a load transistor circuit including at least one load transistor, a base of thereof being operatively grounded, and an emitter thereof being operatively grounded, and an emitter thereof being connected to a collector of the amplification transistor; at least one load resistor connected between a collector of the load transistor and a high voltage supply; and a frequency control circuit having a capacitance, and connected to the commonly connected point of the collector of the amplification transistor and the emitter of the load transistor. An output signal is output from the commonly connected point of the collector of the load transistor and the load resistor, and a frequency band of the output signal is varied in response to the " capacitance of the frequency control circuit. Brief Description of Drawings Figures la to Id are circuit diagrams of prior art interface circuits; Figs. 2a and 2b are graphs representing frequency characteristics of the interface circuits shown in Figs, la to Id; Fig. 3 is a principle circuit diagram of an interface circuit forwarding to an interface circuit according to the present invention; Fig. 4 is a graph representing a frequency characteristic of the interface circuit shown in Fig. 3; Figs. 5a and 5b are specific circuit diagram of the interface circuit shown in Fig. 3; Figs. 6a and 6b are graphs representing rising and trailing wave forms of an output signal in Fig. 3; Figs. 7a and 7b are circuit diagrams explaining the rising and trailing operation of the interface circuit shown in Fig. 3; Figs. 8a and 8b are circuit diagrams showing the principle of an interface circuit in accordance with the present invention; Figs. 9a and 9b are graphs representing rising and trailing wave forms of an output signal in Figs. 8a and 8b; Figs. 10a to lOd are circuit diagrams of embodiments of an interface circuit in accordance with the present invention; Figs. 11 and 12 are circuit diagrams of prior art level shift circuits; Fig. 13 is a graph representing the frequency characteristic of the level shift circuit shown in Fig. 11; Fig. 14 is a circuit diagram showing the principle of a level shift circuit in accordance with the present invention; Figs. 15 to 18 are circuit diagrams of embodiments of a level shift circuit in accordance with the present invention; Figs. 19 to 23a and 23b are views representing a signal discrimination of a signal discrimination circuit of the present invention; Fig. 24 is a circuit diagram showing the principle of a signal discrimination circuit of the present invention; Figs. 25 to 27 are circuit diagrams of embodiments of the signal discrimination circuit in accordance with the present invention; Figs. 28 and 29 are circuit diagrams of prior art signal distribution circuits; Figs. 30 and 31 are circuit diagrams showing the principle of signal distribution circuits in accordance with the present invention; Figs. 32 to 37 are circuit diagrams of embodiments of signal distribution circuits in accordance with the present invention; Figs. 38 and 39 are circuit diagrams of prior art signal synthesization circuits; Fig. 40 is a circuit diagram showing the principle of a signal synthesization circuit in accordance with the present invention; Figs. 41 to 43 are circuit diagrams of embodiments of a signal synthesization circuit in accordance with the present invention; Fig. 44 is a block diagram of an optical repeater; Figs. 45 and 46 are circuit diagrams of prior art frequency band control and amplification circuits; Fig. 47 is an equivalent circuit of the frequency band control and amplification circuits shown in Figs. 45 and 46; Fig. 48 is a graph representing a frequency characteristic of the circuit shown in Fig. 47; Fig. 49 is a circuit diagram showing the principle of a frequency band control and amplification circuit in accordance with the present invention; Fig. 50 is a graph representing a frequency characteristic of the frequency band control and amplification circuit shown in Fig. 49; Figs. 51 to 53 are views showing a circuit diagram, an equivalent circuit diagram, and a graph of a frequency characteristic of an embodiment of the present invention; Figs. 54 and 55 are circuit diagrams of modifications of the circuit shown in Fig. 51; Figs. 56 to 58 are views showing a circuit diagram, an equivalent circuit diagram, and a graph of a frequency characteristic of another embodiment of the present invention; Figs. 59 and 60 are circuit diagrams of modifications of the circuit shown in Fig. 56; Figs. 61 to 63 are views showing a circuit diagram, an equivalent circuit diagram, and a graph of a frequency characteristic of still another embodiment of a frequency band control signal in accordance with circuit of the present invention; Figs. 64 to 66 are circuit diagrams of modifications of the circuit shown in Fig. 61; and Figs. 67 and 68 are circuit diagrams of yet other embodiments of a frequency band control and amplification circuit in accordance with the present invention. Best Mode for Carrying Out the Invention First, an interface circuit, as one of the electronic circuits of the present invention, will be described. Before describing the interface circuit of the present invention, prior art interface circuits will be described with reference to the drawings. Figures la to Id show prior art interface circuits. Figure la shows an open-emitter type interface circuit, Fig. lb shows an emitter-follower type interface circuit. Fig. lc shows an open-collector type interface circuit, and Fig. Id shows a differential-operation and open-collector type interface circuit. In the drawings, reference CHI denotes a transmission side integrated circuit (IC) chip, CH2 denotes a reception side IC chip, Q, Q- and Q 2 denote npn-type transistors, R, R-- and R.- denote resistors, CS denotes a constant current source, l r 5.- and l- denote data transmission lines, and C, C 1 and C- denote stray capacitors. The IC chip CHI is provided at a data transmission side, the IC chip CH2 is provided at a data reception side, and the data transmission line(s) λ or Jl- and J_ 2 ^- s ( are ) provided therebetween. The stray capacitor(s) C or C. and C~ may be connected to the data transmission line(s) I or £... and l~ ~ The open-emitter type interface circuit shown in Fig. la is a voltage signal propagation type interface circuit. An input impedance of the transmission side IC chip CHI is low, and an input impedance of the reception side IC chip IC2 is high. A frequency band f_ 3dB at which a gain is lowered by 3 dB is expressed by the following formula: f -3dB = 2 C 3 -r E •* ' (1) where, C„ represents a capacitance of the stray capacitor(s) C or C~ and C 2 , and r represents an emitter resistance of the transistor(s) Q or Q- and Q n . Figure 2a shows a frequency characteristic of the open-type interface circuit shown in Fig. la. In the drawing, curve CV1C_L shows a frequency characteristic when the stray capacitance C_ is 0.5 pF, and curve CV1, shows a frequency characteristic when the stray capacitance C g is 5 pF. Since the emitter resistance r„ is small, an affect due to the stray capacitor is reduced and a frequency band where a gain is lowered by 3 dB is broad, but a distortion, such as peaking occurs. The emitter-follower type interface circuit shown in Fig. lb also suffers from the above defect. In Figs, lc and Id, since the load resistor(s) R- or R-- and R- 2 is (are) connected to the stray capacitor(s) in parallel, the frequency f_ 3d _ is expressed as follows: f = (2) -3dB 2 L -C S • " { ' where, R L represents a resistance of the load resistor(s) R 1 or R- 1 and R-t 2 « Figure 2b shows a frequency characteristic of the interface circuits shown in Figs, lc and Id. In Figs. 2b, curves CV2 , CV2 fe , and CV2 show frequency characteristics where the stray capacitance C g are 0.1 pF, 0.5 pF and 1.0 pF, respectively. The resistance R_ of the load resistor(s) R, or R-- and R-, 2 can not be made too small because an output signal(s) S ouτ or S QUT1 and S ou _ 2 having a predetermined amplitude must be provided, an affect due to the stray capacitance C„ can not be eliminated, as shown in Fig. 2b. The inventors of the present application devised a novel interface circuit which definitely eliminates the above adverse affect due to the stray capacitance ("Interface circuit", filed on June 20, 1986 at Japan P.O. and published on January 6, 1988, as JPA 63-1211). Figure 3 shows a principle interface circuit, which comprises a current drive source ID in a transmission side IC chip CHI, and, an npn-type transistor Q in which ' a base is grounded and an emitter is connected to the current drive source ID through a transfer line £, and a load resistor R in a reception side IC chip CH2. A stray capacitor C may be connected to the transfer line l . A current I, which is extracted from the current drive source ID is defined by the following formula: τ A α ~ x c-. + 1 r g m m ... (3) where, I__- is a current supplied by the stray capacitor C, and I is a current supplied by the transistor Q. An output voltage V QUT of an output signal S QUT is expressed as follows: V OUT = R L βI gm ••• (4) where, is a resistance of the load resistor R. AA vvoollttaacge V c generated at the stray capacitor C is expressed by where, C g is a capacitance of the stray capacitor C, and gm_ is a mutual conductance of the transistor Q. Accordingly, from the above formulas (3) to (5), the output voltage V QUT of the output signal S QUT is expressed by the following formula: As a result, a frequency f_ 3dB _ a gain which is lowered by 3 dB, is expressed by the following formula: Figure 4 shows a graph of a frequency characteristic of the interface circuit shown in Fig 3. In the drawing, curves CV3 and CV3-, show the frequency characteristics when the stray capacitances C„ are 1 pF and 5 pF, respectively. More concretely, when a DC current component of the current drive source ID is 2 mA, a resistance: l/g„m is 13 Ω and, when the stray capacitance C g is 1 pF, the frequency f_ 3dB is 12 Giga-Hertz (GHz). Apparently, this interface circuit shown in Fig. 3 is not substantially affected by the stray capacitance C g of approximately 1 pF on s signal transfer at approximately 10 GHz. Figures 5a and 5b show specific circuits of the interface circuit of shown in Fig. 3. The circuit shown in Fig. 5a comprises the current drive source ID consisting of an npn-type transistor Q, and an emitter resistor R, having a terminal connected to an emitter of the transistor Q- and another terminal connected to a low voltage supply V„ E which may be ground. The circuit also comprises ah npn-type transistor Q 2 having an emitter connected to a collector of the transistor Q- through the transfer line % and a base supplied with a bias voltage supply V„ , and a load resistor R 2 connected between a high voltage supply V__ and a collector of the transistor Q 2 . At the IC chip CHI, an input signal S χN is supplied to a base of the transistor Q- , and at the IC chip CH2, an output signal S OUT ^ s out P ut fr ° m a point at which the load resistor R~ and the collector of the transistor Q- are commonly connected. The stray capacitor C is connected to the transfer line ϋ . Note that the interface circuit shown in Fig. 5a is formed by a "cascode configuration", since the emitter of the transistor Q- is grounded through the resistor R 1 , the collector of the transistor Q- and the emitter of the transistor Q 2 are connected, and the base of the transistor Q 2 is grounded through the bias voltage supply g. In general, a cascode amplifier having the above configuration is used for a high frequency amplification, because an input signal side and a load side are separated and an internal feedback is small, and thus a high speed operation can be established. A total gain of the cascode amplifier is equal to a gain of a load transistor, because a load at a first step is a resistor of an input transistor in the second step, i.e., an emitter resistance r„ of the input transistor which is very small. In JPA 63-1211, the above high speed operation feature of the cascode configuration, and the elimination of the affection due to the stray capacitor by a Miller effect, obtained by grounding the base of the load transistor are used for an interface are used for an interface circuit operable at a high frequency. In Fig. 5b, the current drive source ID is constructed by differential operation transistor pair Q-- and Q 12 and a constant current source CS. The load (output) circuit also includes a pair of transistors Q 21 and Q 22 , a pair of load resistors R 21 and R 22 , and the bias voltage supply V β . Emitters of the transistors Q_- and Q 12 are grounded through the constant current source CS, and bases of the transistors Q,- and Q~~ are grounded through the bias vol_. g e s ppx V B . A_ o_d_ ng _ y , Ms inters circuit shown in Fig. 5b has a cascode configuration. Nevertheless, the interface circuit described in J A 63-1211 still suffers from the affect of a large stray capacitance at a high frequency when the input signal S IN has a large amplitude, for example, 800 mV or more. Figures 6a and 6b show graphs of response characteristics of the interface circuit shown in Fig 3, obtained by simulation. Figure 6a shows rising wave forms of the output signal S QUT to a drive signal, i.e., the input signal S_ N , represented by curve DW, and Fig. 6b shows trailing (falling) wave forms to the drive signal. In Fig. 6a, curves CV4 to CV4, show rising wave forms of the output signal S QUT when the stray capacitances are 0.1 pF, 0.5 pF, 1.0 pF and 5.0 pF, respectively. The variation of rising times is small, but a large ringing appears due to the stray capacitance. In Fig. 6b, curves CV5 to CV5, show trailing wave forms of the output signal S QUT when the stray capacitance are β.O pF, 0.1 pF, 0.5 pF and 1.0 pF, respectively. The start points of the trailing are greatly varied due to the stray capacitance, and the ringing is also large. The above defects will be discussed with reference to the circuits shown in Figs. 7a and 7b, corresponding to the interface circuit shown in Fig. 3. First, an operation when the input signal S TN having a large amplitude and changed from low level to high level is supplied to the current drive source ID will be described with reference to Fig. 7a. Upon receipt of the high level input signal S- N , the current drive source ID, more specifically the transistor in the current drive source, is turned ON. As a result, the load transistor Q is also turned ON, and supplies an on current I QN to the current drive source ID. A voltage V βE between the base and the emitter of the transistor Q is varied in response to a current flowing through the base and the emitter, i.e., the on current I 0N^ When the current is equal to or higher than 0.1 mA, the base-emitter voltage V__ of the load transistor Q is approximately 0.8 V. A voltage V. between the transfer line I and ground is V. = V„ - V B „ , where V_ denotes a base voltage of the transistor Q. When the flow of the on-current I QN occurs, the stray capacitor C is discharged until the voltage V„ becomes V_ - V„_ , and this distorts the rising wave form as shown in Fig. 6a. Second, an operation when the input signal S IN is changed from high level to low level will be described with reference to Fig. 7b. The input transistor in the current drive source ID is turned OFF, and the load transistor Q is turned OFF. As a result, an off current I QFF supplied from the load transistor Q to the current drive source ID becomes approximately 0 mA, and the voltage V βE becomes 0 V. Consequently, the voltage V. on the transfer line SL becomes V B . The stray capacitor C is charged until the voltage (V β - V βE ) becomes V_ a.. This distorts the trailing wave form as shown in Fig. 6b. Namely, the voltage V. on the transfer line is varied by the voltage V βE = 0.8 V, and the stray capacitor C is discharged or charged in response to the change of the transfer line voltage V,. A delay time t, of the trailing edge and the rising edge can be expressed by the following formula; = _ CSVBi • _ (8) d X d where, I, represents a current passing through the current drive source ID. Now, a principle of an interface circuit of the present invention will be. described with reference to Figs. 8a and 8b. The interface circuits shown in Figs. 8a and 8b eliminate the change of the transfer line voltage V. , and thus eliminate the charging and discharging of the stray capacitor C, to shorten the rising time and the trailing time. In Fig. 8a, the interface circuit includes a current drive source ID in a transmission side IC chip CHI. The interface circuit also includes, at a reception side IC chip CH2, a load (output) transistor Q and a load resistor R. Between the chips CHI and CH2, a transfer line λ is provided, and a stray capacitor C can ^ connected to the transfer line l . The current drive circuit ID includes an input transistor (not shown) , an emitter thereof being grounded. A base of the load transistor Q is connected to a collector of the input transistor, and a base thereof is grounded. The above circuit construction is substantially the same as that of the interface circuit shown in Fig. 3, and thus the interface circuit shown in Fig. 8a has a cascode configuration. In addition to the above circuit configuration, the interface circuit shown in Fig. 8a includes a bias current source CS Q connected between the emitter and the base of the load transistor Q in the reception side IC chip CH2. The bias current source CS Q provides a constant current I cg corresponding to a current I βE flowing through the base and the emitter of the load transistor, i.e., the above on-current I ON , Q when the transistor Q is turned ON, for cancelling the current I BE « Namely, the constant current I cg has an amplitude sufficient to prevent the change of the voltage V. on the transfer line , i.e., to prevent the change of the base-emitter voltage V_ E of the load transistor and has a polarity which is the reserve of a polarity of the on current I QN - In other words, the constant current- I_ g generates a voltage between the base and the emitter of the transistor Q opposite to the base-emitter voltage V βE of the load transistor Q when the load transistor Q is turned ON. In general, the constant current I_, g may be 0.5 mA or higher. Taking a margin into consideration, the constant current I cg may be 0.5 mA. The bias current source CS Q always provides the constant current I„ s to the load transistor Q to suppress the change of the base-emitter voltage V_ E , so that the voltage V. on the transfer line I is not changed regardless of the change of the status of the load transistor Q, i.e., the change between the ON state and the OFF state, of the load transistor Q. Accordingly, the charging and discharging of the stray capacitor C are avoided, and generation of the distortion of the rising signal and the trailing signal is prevented. As shown in Fig. 8b, the bias current source CS Q can be provided at the transmission side IC chip CHI. Since the bias current source CS Q is connected between the base and the emitter of the load transistor Q, the operation is same to that described above. In Figs. 8a and 8b, by providing the bias current source CS Q , a DC level of the output signal S ouτ can be made low than that of the interface circuit shown in Fig. 3, and thus the resistance R_ of the load resistor R should be greater than that of the load resistor shown in Fig. 3. In addition, a current flowing through the load transistor Q may be increased, and a capacity of the load transistor Q may become larger than that of the transistor shown in Fig. 3. However, note that an amplitude of the output signal S QUT , per se, is not changed, regardless of the provision of the bias current source CS Q . Figures 9a and 9b show the characteristic curves of the interface circuits shown in Figs. 8a and 8b obtained by simulation. Figure 9a shows a rising characteristic. In Fig. 9a, curves CV6 to CV6, represent the rising characteristics corresponding to the change of the drive signal, i.e., the input signal S- N , represented by curve DW, when the stray capacitances C g are 0.1 pF, 0.5 pF, 1.0 pF, and 5.0 pF. These curves CV6 to CV6, correspond to the curves CV4 to CV4, in Fig. 6a. Compared with these, as shown in Fig. 6a, the character¬ istics shown by the curves CV4 cL to CV4C when the stray capacitances are 0.1 pF, 0.5 pF, and 1.0 pF are greatly varied therebetween, but on the other hand, as shown in Fig. 9a, the characteristics shown by the curves CV6 3. to CV6c are not varied each other. This means that the transfer line I in the interface circuit shown in Fig. 8a can install at a short distance or a long distance without any circuit adjustment. The character¬ istics shown by the curves CV7a to CV7c_ mean the same thing. Figures 10a to lOd show circuit diagrams of an embodiment of the interface circuit in accordance with the present invention. The interface circuits shown in Figs. 10a and 10b are the open-collector type interface circuits corresponding to the interface circuit shown in Fig. 5a. In Fig. 10a, the bias current source CS Q is formed by a current-mirror type current source composed of npn-type transistor Q- and Q . , resistors 3 and R, , and a resistor 5 . The current-mirror type current source, per se, is well known. In Fig. 10b, the bias current source CS Q is formed by a resistor R g . The interface circuits shown in Figs. 10c and lOd are differential-operation and open-collector type interface circuits corresponding to the interface circuit shown in Fig. 5b. In Fig. 10c, the bias current source CS Q is formed by a current-mirror type constant current source composed of npn-type transistor Q 31 , Q 32 and Q . , and resistors R 3 , , R 32 , R . and R^. In Fig. lOd, the bias current source CS Q is formed by two resistors Rg- and 62 . The interface circuits shown in Figs. 10a to lOd can be provided with the bias current source CS Q at the transmission side IQ chip CHI. When the input signal S IN is a high frequency repetition signal, such as a clock signal,. in the base-grounded interface circuit shown in Fig. 3, a wave form distortion may not occur, since a charge accumulated in the stray capacitor is not fully discharged, and the base " emitter voltage V βE is not substantially changed. But, when the input signal S IN is a data signal which may be formed by continuous one's data or continuous zero's data, a wave form distortion can occur at a transient state where an end of the continuous one's data is followed by a first of the continuous zero's data, or vice versa. In this case, the interface circuit of the present invention is preferably used. In particular, the interface circuit of the present invention is very useful when forming interfaces, such as an interface between circuits in a gate array integrated circuit chip wherein a wiring pattern capacitance is considerably large, and an interface between chips wherein a bonding pad capacitance can not be neglected. According to the interface circuit of the present invention, since the frequency characteristic and the wave response characteristic are not affected by the stray capacitor, a high speed data transmission can be achieved. Second, a level shift circuit of the present invention will be described. In the case of a data processing at a high speed, a level shift of a DC bias level of a signal by a predetermined voltage is required. For example, in an amplification circuit, a DC level of an input signal can be shifted to a level equal to a reference voltage by using the level shift circuit. Figure 11 shows a prior art differential-operation type level shift circuit. In the drawing, the level shift circuit includes a pair of differential-operation transistors Q- and Q 2 , a first current source CS- consisting of a transistor Q- and a resistor R 3 , a second current source CS 2 consisting of a transistor Q . and a resistor R 4 , a third current source CS 3 consisting of a transistor Q- and a resistor R 5 , output emitter follower transistors Q g and Q_ , and resistors R- , 2 , R g and R-. Upon receipt of input signals S_ N1 and S IN2 at bases of the transistors Q 1 and Q 2 , a pair of differential-operated output voltages V- and V 2 are respectively extracted from points at which collectors of the transistors Q- and Q- and the load resistors R- and R 2 are commonly connected, and supplied to bases of the transistors Q g and Q 7 . Output signals S QUT1 and S QUT2 having voltages V 3 and V. , respectively, are output from points collectors of the transistors . and Q- and the resistors R g and R_ are commonly connected. The voltages V- and V 3 , and the voltage V 2 and V^ have the following relationships: is a current passing through the transistor Q . , and I 2 is a current passing through the transistor Q 5 . Namely, the output voltages V 3 and V 4 are shifted from the voltage V- and V 2 by (V βE + I-Rg) and (V βE + I 2 R 7 ). In this level shift circuit, the levels to be shifted can be easily changed continuously by changing the currents I- and I 2 of the current sources CS 2 and CS-. Figure 12 shows a prior art diode-type level shift circuit. In the drawing, n-series connected transistors, for example, Q-- , each connected between a collector and a base and functioning as a diode, are connected between transistors g and Q . . Similarly, n-series connected transistors, for example, Q 2 - , each connected between a collector and a base and functioning as a diode, are connected between transistors Q_ and Q- . In the drawing, the following relationships stand: V 1 = (n+l)V BE + V 3 ... (11) V 2 = (n+l)V BE + V 4 ... (12) where, V βE is a base-emitter voltage of the diode-functioning transistor. Namely, by changing the number of the diode-changing transistors, a level shift voltage (n+l)V E can be stepwisely changed. Figure 13 shows a graph of frequency characteristics of the level shift circuits shown in Figs. 11 and 12. In the level shift circuit shown in Fig. 11, due to the resistors R g and R 7 at the emitter follower circuits and stray capacitors which can be connected to the emitter follower circuits, as shown in Fig. 13, the frequency characteristic is reduced, and accordingly, a wave response characteristic is reduced. As a result, the level shift circuit in Fig. 11 can not be applied to a high speed circuit. The level shift circuit shown in Fig. 12 has the same problem as that described above. In general, in order to realize a high speed operation level shift circuit without a distortion of a wave form, several design techniques can be utilized, for example, reducing the resistances of the series-connected resistors R g and R 7 , reducing capacitances of the stray capacitors, and arranging a circuit construction in which the stray capacitors are replaced by other portions directly affecting the characteristic. 'Nevertheless, these countermeasures are limited in practice. Conversely, a circuit providing a bias current source CS Q in addition to the cascode configuration as shown in Figs. 8a and 8b prevents a distortion of a wave form of a output signal and the reduction of a variety of characteristics, due to the stray capacitance. In this invention, the above feature is used to form a high speed level shift circuit without the reduction of the frequency characteristic and the wave response characteristic. Figure 14 shows a principle circuit diagram of a level shift circuit in accordance with the present invention. The level shift circuit includes a pair of differential-operation transistors Q-- and Q- 2 , and a constant current source CS- connected between collectors of the transistors Q-- and Q- 2 and a low voltage line V_, E which may be ground. The level shift circuit also includes load resistors R 21 and R 22 , load transistors Q 2 - and Q 22 , a bias voltage supply V β , and level shift current sources CS 2 and CS 3 . The emitters of the transistors Q-- and Q- 2 are grounded through the constant current source CS., , collectors of the transistors Q-- and Q- 2 are connected to emitters of the transistors Q 2 - and Q 22 , and bases of the transistors Q 2 - and Q 22 are grounded through the bias voltage supply V β . Accordingly, the above circuit has a cascode configuration. In addition, the variable current sources CS 2 and CS 2 corresponding to the bias current source CS Q shown in Fig. 8a are connected between the emitters of the transistors Q 2 - and Q 22 and the low voltage line V„„ , which is ground. A differential-operation pair circuit, corresponding to the current drive circuit ID in Fig. 8a, consisting of the transistors Q-- and Q- 2 and the constant current sources CS- receives voltage input signals S_ Nl and S_ N2 , and changes to currents I 3 and I. flowing therethrough. The currents I 3 and I. are varied in response to the voltages of the input signals S IN - and S χN2 . The constant current source CS- supplies a current of a sum of and I.. The above currents I 3 and I 4 are made flow through the load resistors R 21 and R 2 - , resulting in voltage drops V 2 - = I 3 « R 2 - and V 22 = wn i ch are output signals S ou _- and S ourj , 2 . In addition, currents I- and I 2 supplied by the level shift current sources CS 2 and CS 3 are made flow through the load resistors R 2 - and R 22 , resulting in further voltage drops V..- = l 'R 2 l and- V 22 = I 2" R 22" These voltage drops V L - and V L2 are level-shifted values. Since the currents I- and I 2 can be changed by adjusting the current sources CS 2 and CS 3 , the level shift voltages V L; , and V^ can be continuously changed. The basic condition of the interface circuits shown in Figs. 8a and 8b and Figs. 10a to lOd can be applied to the level shift circuit shown in Fig. 14, except for the variable level shift current sources CS 2 and CS 3 . Therefore, the features of the interface circuit are maintained in the level shift circuit. A basic difference between the interface circuit and the level shift circuit of the present invention is the provision of the constant bias current source CS Q and the variable level shift current sources CS 2 and CS 3 . However, if the level shift circuit can be used for shifting at a constant level, the current sources CS 2 and CS 3 can be formed as constant current sources. Figures 15 to 18 show circuit diagrams of embodiments of a level shif circuit in accordance with the present invention. In Fig. 15, the constant current source CS- is composed of an npn-transistor Q 3 and a resistor R 3 , and supplies a current corresponding to (I 3 + I.) . The current sources CS 2 and CS 3 are formed by a current-mirror type current source circuit consisting of npn-type transistors Q . , Q 5 , and Q- Q , and resistors R 4 ' R 5 ' R 10 ' and R ll * The tra nsistors Q . and Q - and the transistors R. and R- are defined to supply the current I- and I 2 . In this embodiment, the current sources CS 2 and CS- are constant current sources, and the level shift is fixed. In Fig. 16, the current source CS- consists of a transistor Q 3 and a resistor R- , the current source CS 2 consists of a resistor R- Q , a transistor Q- Q , a resistor R- 1 , a transistor Q. , and a resistor R. , and the current source CS 3 consists of a transistors Q- and Q-- , and resistors R 5 and R 12 * τ * ιe current source CS 2 and the current source CS 3 are current-mirror type current sources. By changing a control voltage V_, supplied to the current source CS 3 , a level of an output signal S QUT2 can be continuously changed. But, since the current source CS 2 is a constant current source, a level-shift of an output signal S ouτ - is fixed. The level shift circuit shown in Fig. 17 is a modification of the level shift circuit shown in Fig. 16. In the drawing, the constant current source CS- is formed by a current-mirror type current source consisting of a resistor R- Q , transistors Q- Q and Q 3 , and resistors R-- and R 3 . The current sources CS 2 and CS 3 are formed by a variable current-mirror type current source consisting of transistors Q 4 , Q 5 , and Q-- , and resistors R 4 , R 5 and R--. By changing a control voltage V_ supplied to the current sources CS 2 and CS 3 , the levels of both of the output signals S ouτ - and S QUT2 can be continuously shifted. In Fig. 18, the constant current source CS- is formed by a current-mirror type current source consisting of transistors Q- and Q- Q , and resistors R 10 ' R 3 ' ~- ~~ R ll* The current sources CS 2 and CS 3 are variable resistors R 4 and Rj.. The levels of both of the output signals S QUT - and S_ uτ2 can be freely shifted by adjusting the resistances of the resistors R 4 and R e . Third, a signal discrimination circuit of the present invention will be described. The signal discrimination circuit can be applied, for example, to a repeater in an optical data transmission system. In the repeater, as shown in Fig. 19, an optical to electrical (OE) converted signal is equalized and amplified at an equalizing amplifier 10, and a clock signal is extracted at a timing circuit 14. The equalized signal is discriminated by a timing signal from the timing circuit 14 at a signal discriminal circuit 12, and the discriminated signal is reproduced at a reproduction circuit 16. As shown in Fig. 20, a discriminating level can be varied by adjusting a variable resistor R y ^* τ ^ e equalizing amplifier 10 outputs an equalized signal SlOA and a discriminating threshold voltage signal S10B. As shown in Fig. 21, the equalized signal S10A, having a distorted eye-pattern by an optical shock and a shifted timing, is discriminated by a threshold level L at the discrimination circuit 12, and a high level signal is output when the equalized signal is higher than the threshold level L at a clock timing, and alternatively, a low level signal is output. In order to adjust the threshold level to a maximum level in response to variations, such as a drift of the circuit, or noise, the threshold level L is adjusted by the variable resistor ^- , and the discrimination circuit 12 discriminates the equalized signal SlOA by using the adjusted threshold level signal S10B. In the optical transmission system, a very high speed signal processing is required. Such a high speed signal processing requires an improvement of a wave form response and a prevention of cross-talk. The improvement and the prevention, in general, require to reduce a gain at the equalizing amplifier, and to reduce an amplitude of the equalized signal. This amplitude reduction lowers the discrimination sensitivity. In general,-when an amplitude is small, and thus the discrimination sensitivity is low, the differential-operation type discrimination is preferable, but is difficult to adjust the discrimination level. Namely, since a normal polarity signal shown in Fig. 22a and an inverted polarity signal shown in Fig. 22b are used in the differential-operation discrimination, the discrimination threshold level L is determined at a center level. In the optical transmission system, a center of the eye-pattern tends to be shifted to a low level, and a free level shifting is required in the discrimination used by the differential-operation type circuit. In addition, the differential-operation type circuit has an advantage in that a deadband of the discrimination defined by a low limit LL and a upper limit UL shown in Fig. 21 is reduced by a half. The present invention provides a signal discrimination circuit which is formed by a differential-operation type circuit, operates at a high speed, has a high discrimination sensitivity, and can adjust the discrimination threshold level. Figure 24 shows a principle of the signal discrimination circuit in accordance with the present invention. A basic circuit configuration of the signal discrimination circuit shown in Fig. 24 is similar to the level shift circuit shown in Fig. 14, except that a flip-flop FF is provided. Accordingly, a description of the basic circuit configuration and operation thereof is omitted. Currents I 4 and I 5 , which are made to flow through load resistors R 2 - and R 22 , load transistors Q 2 - and Q 22 , a pair of differential-operation transistors Q-- and Q- 2 and a current source CS- , respectively, are varied in response to input signals S IN - and S IN2 . These currents I 4 and I 5 generate voltage drops defined by (R 21 I 4 ) and (R 22 ~~ - ) at the ad resistors R 2 - and R 22 « In addition, currents I 2 and I 3 , which respectively flow through the load resistors R--, and R 22 , the load transistors Q 2 - and Q 22 , and current sources CS 2 and CS 3 , are defined by only the current sources CS 2 and CS 3 and generate voltage drops defined by (R 2 - I 2 ) and (R 22 I.,). These voltage drops (R 2 - I 2 ) and (R 22 I 3 ) indicate shift levels. Referring to Figs. 23a and 23b, a level SL, or a level SL^. is shifted by (R 2 - I 2 - R 22 I 3 )/2 from the discrimination threshold level L. The level shifted output signals S ouτ - and S OUT2 are out P ut to the fϋ -flop FF. The current sources CS 2 and/or CS 3 are formed to supply variable currents I 2 and I 3 in response to a level shift value. in the signal discrimination circuit shown in Fig. 24, all of the features of the level shift circuit shown in Fig. 14 are maintained. Figure 25 shows a specific circuit diagram of an embodiment of the signal discrimination circuit in accordance with the present invention. In Fig. 25, emitter-follower transistors Q- and Q g are provided to output signals S 3 and S 4 therethrough. The constant current source CS- is formed by a current-mirror type current source circuit consisting of transistors Q. 2 and Q 7 and resistors R„ , R g and R 3 - The current source CS 2 is formed by a current-mirror type current source circuit consisting of a transistor Q g , a resistor R 4 , the common resistors R g and R g , and the common transistor Q 12 - The current source CS 3 is formed by a current-mirror type current source circuit consisting of transistors Q g and Q- 3 and resistors 5 and R 10 - A current source CS 4 for the emitter-follower transistors Q c and Q g is formed by a current-mirror type current source circuit consisting of transistors Q 1Q and Q-- , resistors R g and 7 , the common resistor Rg , the common transistor Q- 2 and the common resistor R g . in the drawing, the current source CS 3 can change the current I- by adjusting a control voltage V_ , and can shift the level of the signal S 4 . The current source CS- supplies a constant current I 2 , and accordingly, the shift level of the signal S 3 is constant. Figures 23a and 23b show the level shift by the circuit shown in Fig. 25, and the signal discrimination therefor. Figure 26 shows a block diagram of an embodiment of the flip-flop FF shown in Fig. 24. The flip-flop FF includes a master latch circuit ML driven, by a clock CLK and a slave latch circuit SL driven by an inverted clock CLK. Figure 27 shows a specific circuit diagram of the flip-flop FF shown in Fig. 26. In the drawing, reference V g denotes a reference voltage supply, CS 4 to CS g denote current sources. The operation will be briefly described. When the signal S- is higher than the signal S. , and when the clock CLK is at a high level higher than a voltage from the reference voltage supply V g , a transistor Q . Q is turned ON, a transistor Q 4 - is turned OFF, a transistor Q. g is turned OFF and a transistor Q 47 is turned ON, thus outputting a signal S r having a low level and a signal S g having a high level. Also, a transistor Q 43 is turned ON, a transistor Q . . is turned OFF, and a transistor Q 45 is turned OFF. When the clock CLK becomes low level, the transistor Q 42 is turned OFF, the transistor Q 45 is turned ON, the transistor Q 43 is turned ON, and the transistor Q 44 is turned OFF, and thus the signal S 5 is maintained at a high level and the signal S g at a low level. That is, a latch function is achieved. The above latched statuses are updated in response to the levels of the input signals S 3 and S 4 when the clock CLK becomes high level. Accordingly, the flip-flop FF shown in Fig. 27 functions as a discrimination circuit which reads data in response to the levels of the input signals S 3 and S. at a change time of the clock CLK, with a narrow pulse width of the clock CLK. Referring to Fig. 25, since the level shift of the signal S 3 is constant and the level of the signal S 4 is shifted, the discrimination threshold level L is shifted by a half (1/2) of the level shift of the signal S 4 . Also, the dead band of the discrimination shown in Fig. 21 is narrowed by a half. Referring to Figs. 19, 20 and 25, the signals SlOA and S10B correspond to the input signals S IN1 and S_ N2 , and the circuit shown in Fig. 25 including the flip-flop FF corresponds to the signal discrimination circuit 12. The clock CLK in Fig. 27 is supplied from the timing circuit 14 shown in Fig. 19. As described above, the signal discrimination circuit of the present invention is formed by a combination of the level shift circuit, which is differential-operated and can shift the levels of the differential-input signals S TN - and S IN2 , and a latch circuit, such as the flip-flop FF, latching the level-shifted output signals S QUT - and S_ uτ2 . The signal discrimination circuit of the present invention can adjust the discrimination threshold level L and has a narrow dead band. The narrow dead band brings a reduction of an amplitude of the equalized signal, resulting in a prevention of cross-talk. In addition, since all of the features of the level shift circuit shown in Fig. 14 are maintained, the signal discrimination circuit of the present invention can operate at a high speed will improving the frequency characteristic and the wave form response characteristic. In particular, the signal discrimination circuit is preferably used for discriminating the OE converted signal because the free level shift is effective for discriminating a center eye-pattern lowered due to an optical shock. Fourth, a signal distribution circuit of the present invention will be described. Figure 28 shows a prior art signal distribution circuit. In the drawing, a signal sending circuit 10 is a differential-operation pair type circuit consisting of resistors R 5 - and 52 , transistors Q 5 - and Q 52 and a constant current source CS c - j . Two parallel-connected emitter-follower circuits, which consist of a transistor Q 10 - and a constant current source CS- 0 - , and a transistor Q 102 and a constant current source CS- Q2 , respectively, are connected to a collector of the transistor Q 52 « Two circuits 20A and 20B, which receive distributed signals follow the emitter-follower circuits. When receipt of two input signals S IN - and S_ N2 , one of which may be a reference signal, a difference between the two input signals S_ N - and S IN2 is amplified and output as an output signal S 3 . The output signal S- is supplied to bases of the transistors ^101 an(i ^102 ' and ' out P ut signals, each of which is lowered by a base-emitter voltage V B „ of each of the transistors Q- 0 - and Q- Q2 , are supplied to the circuits 20A and 20B. In Fig. 28, since the base-emitter capacitors (not shown) are connected to the resistor R 5 - in parallel, a frequency characteristic of the signal distribution circuit is distorted. In addition, the input impedance of the circuits 20A and 20B adversely affects a voltage drop at the resistor R ,. As a result, the signal distribution circuit does not have sufficient fan-outs. Figure 29 also shows a prior art signal distribution circuit. In the drawing, a single emitter-follower circuit consisting of the transistor Q- Q - and the constant current source CS- Q - is provided to supply two distributed signals to the circuits 20A and 20B. Since the input impedance of the circuits 20A and 2OB are connected to an output terminal of the emitter-follower transistor Q 101 , the frequency characteristic often may be fluctuated. In addition, the mutual status change of the circuits 20A and 20B adversely affects the signal distribution circuit. Also, this signal distribution circuit does not provide sufficient fan-outs. Figures 30 and 31 are circuit diagram showing the principle of the signal distribution circuits in accordance with the present invention. The signal distribution circuit shown in Fig. 30 includes a current drive source ID having at least one transistor, an emitter of which is operatively grounded and a base of which receives an input signal S_ N , and series-connected base-grounded transistor circuits, for example, a base-grounded transistor circuit composed of a base-grounded transistor Q 2 - and a resistor 2 - . An emitter of each base-grounded transistor circuit is operatively connected to a collector of the transistor in the current drive source ID. Accordingly, the above circuit configuration is formed as a cascode configuration. In addition, a bias current source BC is connected between each emitter of the base-grounded transistor, for example, Q 27 and ground. In addition, as an option, a plurality of emitter-follower circuits, each, for example, an emitter-follower circuit composed of an emitter-follower transistor Q 101 and a current source CS- Q - , can be connected to collectors of the base-grounded transistors. The circuits 20A to 20G are also connected to the emitter-follower circuits. The signal distribution circuit shown in Fig. 30 changes the voltage input signal S χN to a current signal I passing through the series-connected base-grounded transistor circuits. Each voltage drop generated at each load resistor, for example, R 2 - , is supplied to the base of a corresponding emitter-follower transistor, for example, Q-ι 01 , to distribute the input signal S JN . In the drawing, since the emitter-follower circuits and the circuits 20A to 20G do not distribute the signals, the frequency characteristic is not distorted and the adverse affect due to the circuits 20A to 20G is avoided. In addition, the load resistors are separated by the base-grounded transistors, and thus the frequency characteristic is not adversely affected by the stray capacitors. Furthermore, by providing the. bias current source BC, the adverse affect due the stray capacitance superimposed on the voltage of the transfer lines Jl is fully eliminated. As a result, the signal distribution circuit shown in Fig. 30 operates at a high speed without a distortion of the frequency characteristic and the wave form response characteristic, and can provide many fan-outs regardless of the superimposition of the stray capacitance. The signal distribution circuit shown in Fig. 31 includes the current drive source ID, parallel-connected base-grounded transistor circuits, and the bias current source BC. Optionally, a plurality of emitter-follower circuits and the circuits 20A to 20C are provided. The operation of the signal distribution circuit is similar to that of the signal distribution circuit shown in Fig. 30. The features of the signal distribution circuit shown in Fig. 31 are also similar to those of the signal distribution circuit shown in Fig. 30. Comparing the signal distribution circuits shown in Figs. 30 and 31, in the signal distribution circuit shown in Fig. 30, a high voltage V cc is higher than that of the signal distribution circuit shown in Fig. 31, and the amplitudes of the distributed signals are the same. Conversely, in the signal distribution circuit shown in Fig. 31, each amplitude of the distributed signals is 1/n, where n represents the number of base-grounded transistor circuits. Figures 32 to 37 show circuit diagrams of embodiments of the signal distribution circuits shown in Figs. 30 and 31. The signal distribution circuits shown in Figs. 32 and 33 correspond to the signal distribution circuit shown in Fig. 30. The bases of base-grounded transistors Q , Q 22 , Q 21& , Q 21b , Q 22a and Q 22b are grounded through bias voltage supply circuits V β - and V β2 . Emitters of transistors Q 3 - , Q-- , and Q- 2 are grounded through a resistor R 5 - functioning as the current source and a current source CS--. In Fig. 32, the bias current source BC is formed by a resistor R 4 - . Since the signal distribution circuit shown in Fig. 33 is differentially operated, two bias current sources BC_ and BC. are provided. The signal distribution circuits shown in Figs. 36 to 37 correspond to the signal distribution circuit shown in Fig. 31. In Figs. 34 and 35, the bias current source BC is formed by a current-mirror type current source circuit. The signal distribution circuit shown in Fig. 37 is differentially operated. Fifth, a signal synthesization circuit of the present invention will be described. Figures 38 and 39 show prior art signal synthesization circuits. The operation of these signal synthesization circuits is well known, and thus a description thereof is omitted. In the signal synthesization circuit shown in Fig. 38, emitter-follower outputs of transistors Q 3Q and Q . Q are connected to a circuit 40. The signal synthesization circuit shown in Fig. 38 suffers from the same defects as those of the signal distribution shown in Fig. 29. Also, the signal synthesization circuit shown in Fig. 39 suffers from defects similar to those of the signal distribution circuit shown in Fig. 28, since base-collector capacitors of transistors Q 3Q and Q 4Q are connected to a load resistor R in parallel. In particular, a signal synthesization circuit of the present invention overcomes the above defects of the load resistor commonly used type signal synthesization circuit shown in Fig. 39. Figure 40 ≤hows a circuit diagram showing the principle of a signal synthesization circuit in accordance with the present invention. The signal synthesization circuit includes a plurality current drive sources ID- to ID provided in correspondance to the number of input signals S N - to S IN to be synthesized, a base-grounded transistor Q, a load resistor R, and a bias current source BC. Each current drive source ID includes a transistor, an emitter thereof being operatively grounded, and a base thereof receiving the input signal S χN . As is apparent, the signal synthesization circuit is basically formed by a combination of the cascode configuration circuit and the current source BC. in the Fig. 40, the current drive circuits ID- to ID change the voltage input signals S IN - to S χN to current signals I- to I , and the current signals I- to I are synthesized at a common connected point as I. = I- + I- + ... + I . The synthesized current signal I- i s changed to a voltage V Q at the load resistor R. This voltage V Q is supplied to a circuit 40. Since the base-grounded transistor Q separates a connection between the current drive sources ID-1 to IDn„ and the load resistor R, the adverse affect due to a stray capacitance on the current drive sources ID- to ID is prevented. In addition, since output impedances of the current drive sources ID- to ID are high, a mutual interface between the current drive sources ID 1 to ID is substantially avoided. Furthermore, the provision of the bias current source BC eliminates the adverse affect due to the stray capacitor connected to the transfer line SL . As a result, the signal synthesization circuit shown in Fig. 40 provide many fan-ins, and operates at a high speed without a distortion of the frequency characteristic. Figures 41 to 43 show circuit diagrams of embodiments of the signal synthesization circuit in accordance with the present invention. The configuration and the operation of these signal synthesization circuits are apparent from the above description. Sixth, a frequency band control and amplification circuit of the present invention will be described. Figure 44 shows a block diagram of a repeater in an optical data transmission system. In Fig. 44, reference 1 denotes an optical signal to electric (OE) signal converter, 2 denotes an amplifier, 3 denotes a timing circuit, 4 denotes a discriminator, 5 denotes a signal driver, and 6 denotes a laser. The repeater is similar to the repeater shown in Fig. 19. To improve a S/N, a frequency band control amplification circuit which controls a frequency band is provided in the amplifier 2. Also, to suppress a ringing, a frequency band control circuit is also provided in the timing circuit 3. Figure 45 shows an amplifier including a prior art frequency band control circuit. A resistor R E is connected to an emitter of a transistor, and a load resistor R L is connected to a collector. Furthermore, a variable capacitor C is connected to the load resistor R_ in parallel. Actually, the variable capacitor C -^ is realized by a voltage controlled variable capacitance diode D and a variable voltage supply V D , as shown in Fig. 46. Figure 47 shows an equivalent circuit diagram of the amplifier having the frequency band control amplification circuit shown in Figs. 45 and 46. Figure 48 shows a graph of a frequency characteristic of the amplifier 2 having the frequency band control circuit. A variable capacitance range of the variable capacitor diode D is narrow and can not be adjusted to zero. Due to a limitation of an amplification of the transistor, the resistance of the load resistor R^. can not be made small. Consequently, as shown in Fig. 48, minimum and maximum frequencies f MIN and f j .^ are low and a control frequency band between the minimum and maximum freq^uencies f„M τ I„N and f„MA, v X is narrow. The curve fA, * M.,P, represents a maximum frequency band of the amplifier. Figure 49 is a circuit diagram showing the principle of a frequency band control and amplification circuit of the present invention. The frequency band control amplification circuit includes an amplification transistor TRI, a resistor Rg , a load transistor TR2, a load resistor R_ , a bias voltage supply V β , and a frequency-band control portion 8. An emitter of the transistor TRI is grounded through the resistor R_ , a collector of the transistor TRI is connected to an emitter of the transistor TR2, and a base of the transistor TR2 is grounded through the bias voltage supply V β . Accordingly, the frequency band control amplification circuit has a cascode circuit configuration 7. The load resistor R_ is connected between a high voltage supply V__ and a collector of the transistor TR2. The transistor TR2 has an emitter resistance re defined by re = 1/g 3 m , where gm represents a mutual conductance of the transistor TR2. A base of the transistor TRI receives an input signal S χN having a voltage V--. , and an output signal S QUT having a voltage v ouτ ^ s out P ut ro a common connected point of the resistor R, and the collector of the transistor TR2. An amplitude of the output signal S QUT is varied in response to the voltage V IN of the input signal S IN and an amplification of the transistor TRI. The frequency-band control portion 8 is connected to a common connected point of the collector of the transistor TRI and the emitter of the transistor TR2. The frequency-band control portion 8 includes a variable capacitance component and/or means for changing the emitter resistance re of the transistor TR2. This variable capacitance component functions as a stray capacitance discussed above. Note that this variable capacitance component is connected between the emitter of the transistor TR2 and ground, and not connected to the load resistor R L in parallel. Accordingly, a frequency band of the output signal S ouτ is not directly affected by the variable capacitance component. The capacitance in question is substantially connected to the emitter resistor having a resistance r , of the transistor TR2, in parallel, and defines a frequency f_ of the transistor TR2 functioning as a current source for the load resistor R_. In other words, in this invention, the variable capacitor corresponding to the stray capacitor is added t control the frequency band of the output signal S QUT by using the nature of the stray capacitance. Naturally, the bias current source BC is not provided in this invention. The frequency f_ is determined by the following formula: 2τιτ » C (13) V In addition to a change of the capacitance C v , by changing the emitter resistance r of the transistor TR2 through the frequency-band control portion 8, the above frequency f_ can be controlled. This is apparent from the formula (13). Figure 50 shows a graph representing a frequency characteristic of the frequency band control amplification circuit shown in Fig. 49. The curve ^w m indicates a frequency characteristic of the cascode amplification circuit 7. The frequency band of the output signal S ouτ controlled by the frequency band control amplification circuit shown in Fig. 49 is determined by a low frequency either the above defined frequency f or a frequency on curve ay rp - In the frequency band control amplification circuit, by controlling the capacitance CL. of the frequency control portion 8 and/or the emitter resistance r , the frequency characteristic of the frequency f_ can be controlled. Supposing that the frequency range lies between f MJN and f^ , i.e., f MIN < f < f^ , by selecting the capacitance CL. and/or the emitter resistance re to be f M MA,„X > fA * ,MP-, ,' the cascode circuit 7 can control the frequency band between f MIN and f ^^ , as shown in Fig. 50. In this way, the frequency band control amplification circuit shown in Fig. 49 can freely control the frequency band at a wide frequency range. Figure 51 shows a circuit diagram of a first embodiment of a frequency band control amplification circuit in accordance with the present invention. In the drawing, the frequency-band control portion 8 comprises only a variable capacitor CL. connected between the emitter of the load transistor TR2 and ground. Figure 52 shows an equivalent circuit of the frequency band control amplification circuit shown in Fig. 51. The transistor TRI functions as a current drive source ID, discussed above, supplying a current-defined by V TN /R_ , and the load transistor TR2 functions as a current source, which supplies a current defined by ζ 3 m. _B,„M , for the load resistor RT_J. Figure 53 shows a graph of a frequency characteristic of the frequency band control amplification circuit shown in Fig. 51. In the drawing, f_ represents an actual controllable frequency range. Figure 54 shows a circuit diagram of a more specific frequency band control amplification circuit. In the drawing, the frequency-band control portion 8 comprises a voltage-controlled type variable capacitance diode D and a variable voltage supply V D . The capacitance of this single ended variable capacitor circuit is controlled by changing a voltage of the variable voltage supply V_. Figure 55 shows a circuit diagram of another more specific frequency band control amplification circuit. In the drawing, the cascode circuit 7 is formed as an differential-operation type cascode circuit, and the frequency-band Control portion 8 comprises two parallel-connected voltage-controlled type diodes Dl and D2, a current source CS8, a voltage control transistor TR8, and a variable resistor R8. The capacitances of the diodes Dl and D2 are controlled by changing the variable resistor R8. The bias voltage supply for supplying the bias voltage V β to bases of load transistors TR21 and TR22 is realized by a transistor TRg. Figure 56 shows a circuit diagram of a second embodiment of a frequency band control amplification circuit in accordance with the present invention. In the drawing, the frequency-band control portion 8 comprises a capacitor C and a variable DC current type current source 9. By changing a sink current I g - r - r r (= I E ) flowing to the emitter of the load transistor TR2, the emitter resistance r is changed in accordance with the following formula: V T r e = i • • • (14) where, V_ represents a thermal voltage. V τ = KT/q ... (15) where, K represents a Bol zmann constant, T represents an absolute temperature, and q represents a charge of an electron. Figure 57 shows a graph of an equivalent circuit of the frequency band control amplification circuit shown in Fig. 56. Namely, by changing the emitter resistance r of the transistor TR2, which is a parameter for determining the frequency f_ defined by the formula (13) , the actual frequency band fcl can be controlled as shown in Fig. 58. Figures 59 and 60 are circuit diagrams of more specific frequency band control amplification circuits. In Fig. 59, the ' variable DC current type current source 9 is a variable resistor R gI tK and in Fig. 60, the variable DC current type current source 9 is a - variable current-mirror type current source. By changing a variable resistor R gINK in the current source 9, sink currents I gINK flowing to the emitters of the load transistors TR21 and TR22 are changed, and emitter resistances re of the load transistors TR21 and TR22 are changed. Figure 61 shows a circuit diagram of a third embodiment of a frequency band control amplification circuit in accordance with the present invention. In the drawing, the frequency-band control portion 8 comprises a variable capacitor C„ and a variable current source 9. This embodiment is a combination of the first ■ and second embodiments described with reference to Figs. 51 and 56. Figure 62 is an equivalent circuit diagram of the frequency band control amplification circuit shown in Fig. 61. Figure 63 shows a graph representing a frequency characteristic of the frequency band control amplification circuit shown in Fig. 61. Figures 64 to 66 are circuit diagrams of more specific frequency band control amplification circuits of the third embodiment shown in Fig. 61. Circuit elements in the frequency-band control portions 8 in Figs. 64 to 66 are a combination of the circuit elements described above. Figure 67 shows a circuit diagram of a fourth embodiment of a frequency band control amplification circuit in accordance with the present invention. In the drawing, the frequency-band control portion 8 comprises parallel-connected transistors TR31 and TR32 and a variable current source CS V - Base-emitter capacitors C BE of the transistors TR31 and TR32 are connected between the emitters of the transistors TR21 and TR22, the bases of which are grounded through the bias voltage supply V β , and ground. The base-emitter capacitances C BE can be changed by changing currents through the transistors TR31 and TR32. The variable current source CS V is provided to supply the currents. Collectors of the transistors TR31 and TR32 are commonly connected to the high voltage supply V cc . Figure 68 shows a circuit diagram of a fifth embodiment of a frequency band control amplification circuit in accordance with the present invention. In the drawing, the frequency-band control portion 8 comprises parallel-connected transistors TR31 and TR32, resistors R91 and R92 connected between collectors of the transistors TR31 and TR32 and the voltage supply V__ , and a variable current source CS V « Base•collector capacitors C BC of the transistors TR31 and TR32 are connected between the emitters of the transistors TR21 and TR22, the bases of which are grounded through the bias voltage supply V β , and the voltage supply V_ c . The base•collector capacitances C C can be changed by changing currents through the transistors TR31 and TR32. The variable current source CS V is provided to supply the currents. Throughout the above description, it should be understood that a common circuit configuration of the present invention is the high speed electronic circuit having the cascode circuit configuration and an additional circuit(s) , such as the bias current source for eliminating the stray capacitance, or the frequency-band control portion for adding the capacitance component or changing the emitter resistance of the load transistor in the cascode circuit, both varying the frequency band. Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims. Industrial Applicability The high speed electronic circuit and many circuits, such as the interface circuit, the level shift circuit, which are applications of the high speed electronic circuit, can be applied to a variety of electronic circuit systems requiring a high speed operation with an improved frequency characteristic, wave form response characteristics, stability and/or a wide frequency band.

Claims: CLAIMS 1. A high speed electronic circuit comprising: a current drive circuit (ID) including at least one input transistor, an emitter thereof being operatively grounded and a base thereof receiving an input signal ( S IN ); a load transistor circuit including at least one load transistor, an emitter thereof being connected to a collector of said input transistor and a base of said load transistor being operatively grounded; and a bias current source (CS Q ) connected to said emitter, a current supplied from said bias current source being supplied to said load transistor to maintain a base*emitter voltage (V βE ) of said load transistor when said load transistor is turned off at a base-emitter voltage of said load transistor when said load transistor is turned on. 2. A high speed electronic circuit according to claim 1, wherein said bias current source (CS Q ) comprises a current-mirror type bias current source circuit connected between said emitter of said load transistor (Q) and ground. 3. A high speed electronic circuit according to claim 1 or 2, further comprising a bias voltage source (v B ) connected between said base of said load transistor (Q) and ground. 4. A high speed electronic circuit according to claim 1, wherein said bias current source (CS Q ) comprises at least one resistor (R g ) connected between said emitter of said load transistor and ground. 5. A high speed electronic circuit according to claim 1 or 4, further comprising a bias voltage source (V β ) connected between said bias of said load transistor and ground. 6. An interface circuit according to claim 1, further comprising at least one load resistor (R) connected to a collector of said load transistor for outputting a voltage signal (S QUT ) corresponding to said input signal (S TN ), and at least one transfer line (£) connected between a collector of said input transistor in said current drive circuit (ID) and said emitter of said load transistor (Q) . 7. An interface circuit according to claim 6, wherein said input signal is a data signal logically changing between high level and low level. ° 8. An interface circuit according to claim 7, wherein said current drive circuit (ID) includes said input transistor (Q-) and an input resistor (R-), a base of said input transistor receiving said input signal (S IN ), and said input resistor being connected between an emitter of said input transistor and ground, wherein said load transistor circuit includes said load transistor {Q 2 ), an emitter thereof being connected to a collector of said input transistor, and a collector thereof being connected to said load 0 resistor (R 2 ) to output said output signal (S our „) from a point at which said collector and said load resistor are commonly connected, and wherein said current-mirror type bias current source circuit (CS Q ) includes a first current 5 source transistor (Q 31 ) a collector of which is connected to said emitter of said load transistor, a first current source resistor (R 5 ) supplied with a power supply ( cc ) at a first terminal thereof, a second current source transistor (Q 32 ) a collector of which is 0 connected to a second terminal of said first current source resistor and a base thereof, bases of said first and second current source transistors being commonly connected, and second and third current source resistors (R 3 and R 4 ) connected between emitters of said first and 5 second current source transistors and ground, respectively. 9. An interface circuit according to claim 7, wherein said current drive circuit (ID) includes said input transistor (Q-) and an input resistor (R-), a base of said input transistor receiving said input signal (S IN ), and said input resistor being connected between an emitter of said input transistor and ground, wherein said load transistor circuit includes a load transistor (Q 2 ), an emitter thereof being connected to a collector of said input transistor, and a collector thereof being connected to said load resistor (R 2 ) to output said output signal (S QUT ) from a point at which said collector and said load resistor are commonly connected, and wherein said current source circuit (CS Q ) includes a current resistor (R g ) connected between said emitter of said load transistor and ground. 10. An interface circuit according to claim 7, wherein said current drive circuit (ID) includes a first and second input transistors (Q- j i and Q 12 ) connected in parallel to differentially operate in response to two input signals (S IN - and S IN2 ) connected to bases thereof, and a current source (CS) connected between emitters of said first and second input transistors and ground, wherein said load transistor circuit includes a first and second load transistors (Q 2ι and Q 22 ) / an emitter of said first load transistor being connected to a collector of said first input transistor, an emitter of said second load transistor being connected to a collector of said second input transistor, and bases of said first and second load transistors being commonly connected and operatively grounded. wherein further provided two load resistors (R 2 and R 22 ) are connected to collectors of said first and second load transistors, respectively, to output two output signals (S ouτ - and S QU _ 2 ) from points commonly connected said collectors and said load resistors, and wherein said current-mirror type bias current source circuit (CS Q ) includes a first to third current source transistors (Q 31 , Q 3 and Q . ) , connected in parallel, collectors of said first and second current source transistors being respectively connected to said emitters of said first and second load transistors, a first current source resistor (R 5 ) supplied with a power supply ( cc ) at a first terminal, a second terminal thereof being connected to a collector of said third current source transistor, a base of said third current source transistor being connected to a base thereof which is commonly connected to bases of said first and second current source transistors, and second to fourth current source resistors (R 31 , R 32 and R 4 ) respectively connected between emitters of said first to third current source transistors and ground. 11. An interface circuit according to claim 7, wherein said current drive circuit (ID) includes a first and second input transistors (Q-i-i and Q-ι 2 ) connected in parallel to differentially operate in response to two input signals (S IN1 and S IN2 ) connected to bases thereof, and a current source (CS) connected between emitters of said first and second input transistors and ground, wherein said load transistor circuit includes a first and second load transistors (Q 21 and Q 22 ) / an emitter of said first load transistor being connected to a collector of said first input transistor, an emitter of said second load transistor being connected to a collector of said second input transistor, and bases of said first and second load transistors being commonly connected and operatively grounded, wherein two load resistors (R 21 and 22 ) are provided and connected to collectors of said first and second load transistors, respectively, to output two output signals (S ouτ - and S QU _ 2 ) from points commonly connected said collectors and said load resistors, and wherein said current-mirror type bias current source circuit (CS Q ) comprises two resistors (R g - , R g2 ) connected, between said emitters of said load transistors and ground, respectively. 12. A level shift circuit according to claim 1, further comprising a load resistor circuit including at least one load resistor (R 2 -ι , R 2 ) connected to collectors of said load transistor (Q) in said load transistor circuit, and wherein said bias current source (CS Q ) connected between said emitter and said base of said load transistor comprises at least one current source (CS 2 , CS 3 ) supplying current(s) passing through said load resistor to shift a level of said output signal by a value defined by said current and a resistance, of said load resistor. 13. A level shift circuit according to claim 12, wherein said current drive circuit (ID) includes an input transistor (Q-) and a input resistor (R-), a base of said input transistor receiving said input signal (S- N ), and said input resistor being connected between an emitter of said input transistor and ground, wherein said load transistor circuit includes a load transistor (Q 2 ), an emitter thereof being connected to a collector of said input transistor, and a collector thereof being connected to said load resistor (R 2 ) to output said output signal (S ou _) from a point at which said collector and said load resistor are commonly connected, and wherein said current-mirror type bias current source circuit (CS Q ) includes a first current source transistor (Q 31 ) a collector of which is connected to said emitter of said load transistor, a first current source resistor (R 5 ) supplied with a power supply (V c _) at a first terminal thereof, a second current source transistor (Q 32 ) a collector of which is connected to a second terminal of said first current source resistor and a base thereof, bases of said first and second current source transistors being commonly έ connected, and second and third current source transistors (R 3 and R 4 ) connected between emitters of said first and second current source transistors and ground, respectively. 14. A level shift circuit according to claim 12, 0 wherein said current drive circuit (ID) includes an input transistor (Q-) and a input resistor (R-) , a base of said input transistor receiving said input signal (S τ „), and said input resistor being connected between an emitter of said input transistor and ground, 5 wherein said load transistor circuit includes a load transistor (Q 2 ) / an emitter thereof being connected to a collector of said input transistor, and a collector thereof being connected to said load resistor (R 2 ) to output said output signal (S ouτ ) from a 0 point at which said collector and said load resistor are commonly connected, and wherein said bias current source circuit (CS Q ) includes a current resistor (R g ) connected between said emitter of said load transistor and ground. 5 15. A level shift circuit according to claim 12, wherein said current drive circuit (ID) includes a first and second input transistors (Qii and Q 12 ) connected in parallel to differentially operate in response to two input signals (S IN - and S IN2 ) connected to bases 0 thereof, and a current source (CS) connected between emitters of said first and second input transistors and ground, wherein said load transistor circuit includes a first and second load transistors (Q 21 and 5 Q 22 )' an emitter of said first load transistor being connected to a collector of said first input transistor, an emitter of said second load transistor being connected to a collector of said second input transistor, and bases of said first and second load transistors being commonly connected and operatively grounded, wherein two load resistors (R 21 and R 22 ) are provided and connected to collectors of said first and second load transistors, respectively, to output two output signals (S outrl and S QUT2 ) from points at which said collectors and said load resistors are commonly connected, and wherein said current-mirror type bias current source circuit (CS Q ) includes a first to third current source transistors (Q 31 , 3 and Q . ) , connected in parallel, collectors of said first and second current source transistors being respectively connected to said emitters of said first and second load transistors, a first current source resistor ( e) supplied with a power supply ( cc ) at a first terminal, a second terminal thereof being connected to a collector of said third current source transistor, a base of said third current source transistor being connected to a base thereof which is commonly connected to bases of said first and second current source transistors, and second to fourth current source resistors ( 3 -ι , R 32 and R 4 ) respectively connected between emitters of said first to third current source transistors and ground. 16. An interface circuit according to claim 12, wherein said current drive circuit (ID) includes a first and second input transistors (Q-i-i and Q η2 ) connected in parallel to differentially operate in response to two input signals (S IN - and S IN2 ) connected to bases thereof, and a current source (CS) connected between emitters of said first and second input transistors and ground, wherein said load transistor circuit includes a first and second load transistors (Q 2 and Q 22 ), an emitter of said first load transistor being connected to a collector of said first input transistor, an emitter of said second load transistor being connected to a collector of said second input transistor, and bases of said first and second load transistors being commonly connected and operatively grounded, wherein two load resistors (R 2ι and R 22 ) are provided and connected to collectors of said first and second load transistors, respectively, to output two output signals (S ouτ - and S QU 2 ) from points commonly connected said collectors and said load resistors, and wherein said current-mirror type bias current source circuit (CS n ) comprises two resistors (R g - , Rg 2 ) connected between said emitters of said load transistors and ground, respectively. 17. A signal discrimination circuit according to claim 12, further comprising a latch circuit (FF) connected to said load resistor circuit, wherein said current drive source (ID) is formed as a differential-operation type circuit, said load transistor circuit comprises two load transistors connected in parallel and two current sources (CS 2 , CS 3 ) connected to said two load transistors for changing voltage drops as level shift values at said load resistors. 18. A signal discrimination circuit according to claim 17, wherein a first current source (CS 2 ) in said load transistor circuit comprises a current-mirror type current source circuit. 19. A signal discrimination circuit according to claim 18, wherein said first current-mirror type source circuit is connected to a variable voltage supply (V-,) to change a current supplied therefrom. 20. A signal discrimination circuit according to claim 17, wherein a second current source (CS 3 ) in said load transistor circuit comprises a current-mirror type current source circuit. 21. A signal discrimination circuit according to claim 20, wherein said second current-mirror type source circuit is connected to a variable voltage supply (V c ) to change a current supplied therefrom. 22. A signal distribution circuit according to claim 1, wherein each of a plurality of said load transistor circuits and each of a plurality of load resistors is connected in series, said series-connected circuits are connected in series, said current driver circuit (ID) and said bias current source (BC) are connected in parallel each other and connected to an end of said circuits which are connected said load transistor circuits and said load resistors in series. 23. A signal distribution circuit according to claim 22, further comprising a plurality of emitter follower circuits, each connected to each commonly connected point of said load resistor and a collector of said load transistor in said load transistor circuit. 24. A signal distribution circuit according to claim 1, wherein each of a plurality of said load transistor circuits and each of a plurality of load resistors is connected, said series-connected circuits are connected in parallel, said current drive circuit (ID) and said bias current source (BC) are connected in parallel, and connected to a commonly connected point of said parallel-connected circuits. 25. A signal distribution circuit according to claim 24, further comprising a plurality of emitter-follower circuits, each connected to each commonly connected point of said load resistor and a collector of said load transistor in said load transistor circuit. 26. A signal synthesization circuit according to claim 1, wherein a plurality of said current drive circuits (ID. to ID ) are connected in parallel, each current drive circuit receiving an input signal (S IN ) to be synthesized, said load transistor circuit and a load resistor (R) is connected in series to output a synthesized signal (V Q ), said bias current source (BC) and said emitter of said load transistor (Q) in said load transistor circuit are connected to a commonly connected point of said parallel connected current drive circuits. 27. A frequency band control amplification circuit comprising: an amplification circuit including at least one transistor (TRI) and at least one resistor (R_ connected between an emitter of said transistor and ground, a base of said transistor receiving an input signal (S IN ); a load transistor circuit including at least one load transistor (TR2), a base of thereof being operatively grounded; and an emitter thereof being connected to a collector of said transistor; at least one load resistor (R, ) connected between a collector of said load transistor and a voltage supply (V--) ; and frequency-band control means (8) , operatively connected to said commonly connected point of said collector of said transistor and said emitter of said load transistor, for controlling a capacitance between said emitter of said load transistor and ground, an output signal (S QUT ) being output from said commonly connected point of said collector of said load transistor and said load resistor, and a frequency band of said output signal being varied in response to the capacitance of said variable capacitor circuit. 28. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises a variable capacitor. 29. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises a variable capacitive diode (D) a cathode of which is connected to said emitter of said load transistor (TR2) , and a variable voltage supply (V D ) connected to an anode of said variable capaσitive diode, a capacitance of said variable capacitive diode being varied in response to a voltage from said variable voltage supply. 30. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises a variable current source ^siNK^ connected to said emitter of said load transistor (TR2) to supply a current which varies an emitter resistance of said load transistor. 31. A frequency band control amplification circuit according to claim 30, wherein said variable current source comprises a variable resistor. 32. A frequency band control amplification circuit according to claim 30, wherein said variable current source comprises a current-mirror type variable current source. 33. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises a capacitor and a variable current source d SτNK ), said capacitor and said variable current source being connected in parallel, and said variable current source supplying a current to said emitter of said load transistor (TR2) to vary an emitter resistance of said load transistor. 34. A frequency band control amplification circuit according to claim 33, wherein said variable current source comprises a variable resistor. 35. A frequency band control amplification circuit according to claim 33, wherein said variable current source comprises a current-mirror type variable current source. 36. A frequency band control amplification circuit according to claim 30, wherein said capacitor is a capacitor having a constant capacitance. 37. A frequency and control amplification circuit according to claim 36, wherein said variable current source comprises a current-mirror type variable current source. 38. A frequency band control amplification circuit according to claim 30, wherein said capacitor is a capacitor having a capacitance which is variable. 40. A frequency band control amplification circuit according to claim 39, wherein said variable capacitor comprises a variable capacitive diode (D) a cathode of which is connected to said emitter of said load transistor (TR2) , and a variable voltage supply (V D ) connected to an anode of said variable capacitive diode, a capacitance of said variable capacitive diode being varied in response to a voltage from said variable voltage supply. 41. A frequency band control amplification circuit according to claim 40, wherein said variable current source comprises a variable resistor. 42. A frequency band control amplification circuit according to claim 40, wherein said variable current source comprises a current-mirror type variable current source. 43. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises at least one transistor (TR21, TR22) a base of which is connected to said emitter of said load transistor, a collector of which is directly connected to a voltage supply ( cc ) , and at least one variable current source (CS V ) connected to an emitter of said added transistor and supplying a variable current to said added transistor to vary a capacitance between said base and emitter of said added transistor. 44. A frequency band control amplification circuit according to claim 43, wherein said variable current source comprises a variable resistor. 45. A frequency band control amplification circuit according to claim 43, wherein said variable current source comprises a current-mirror type variable current source. 46. A frequency band control amplification circuit according to claim 27, wherein said frequency-band control means comprises at least one transistor (TR21, TR22) a base of which is connected to said emitter of said load transistor, at least one resistor connected between a collector of said added transistor and a voltage supply (V_ c ) , and at least one variable current source (CS„) connected to an emitter of said added transistor and supplying a variable current to said added transistor to vary a capacitance between said base and collector of said added transistor. 47. A frequency band control amplification circuit according to claim 46, wherein said variable current source comprises a variable resistor. 48. A frequency band control amplification circuit according to claim 46, wherein said variable current source comprises a current-mirror type variable current source. 49. A frequency band control amplification circuit according to claim 27, wherein said amplification circuit is formed by a differential-operation type transistor circuit, and said load transistor circuit comprises two parallel-connected transistors, and comprising two load resistors connected between collectors of said load transistors and said voltage supply. 50. A frequency band control amplification circuit according to claim 49, further comprising two bias voltage sources (V β ) , each connected between a base of said load transistor and a low voltage supply.

Inventors: AMEMIYA IZUMI, HAMANO HIROSHI, IHARA TAKESHI, KITASAGAMI HIROO, YAMAMOTO TAKUJI, AMEMIYA, IZUMI, HAMANO, HIROSHI, IHARA, TAKESHI, KITASAGAMI, HIROO, YAMAMOTO, TAKUJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H03K19
IPC codes: H03F1, H03F3, H03K5, H03K19