GENERATOR OF RESET PULSES UPON THE RISE OF THE POWER SUPPLY FOR CMOS-TYPE INTEGRATED CIRCUITS

Abstract: The generator comprises an input stage (I) constituted by means for dividing the voltage between the power supply and the ground, having a node constituting the output of the input stage, and by a positive-feedback threshold loop, driven by another node of said divider means to make the voltage in said output node rise sharply when the voltage in said other node exceeds said threshold; a first Schmitt trigger (T1) driven by the voltage rise front supplied by said input stage (I); and a former of output pulses (F) comprising a second Schmitt trigger driven by circuital means adapted to directly apply to the second Schmitt trigger the voltage front arriving from the first Schmitt trigger (T1) and to restore the original voltage level with a preset delay.

Description: The present invention relates to a generator of reset pulses upon the rise of the power supply (power-on reset), for CMOS-type integrated circuits. In a large variety of integrated circuits, a series of initialization operations is required when the circuit is switched on or restarts its operation after an accidental and unforeseen power cut. For devices to which an external clock on which to synchronise these operations is not supplied, a power-on reset circuit, adapted to generate one or more pulses which start the initialization operations (reset pulses) is required. For good operation, a power-on reset generator must correctly react whether the supply voltage rises slowly or sharply. This constitutes a problem, due to the difficulty of producing a circuit which detects with the same certainty transitions with widely different rise times. Power-on reset generators are furthermore required not only to act at the moment of initial switching on, but also in the case of successive brief power interruptions, which may have corrupted the data stored in the circuit. On this subject, the minimum time of duration of the power supply interruption (minimum break-time) is critical. The recovery time, i.e. the minimum time required by the generator to reset to conditions capable of intervening in the case of a new break, is also critical. In the CMOS integrated circuits being dealt with, it is also important that the current consumption be as reduced as possible. Known power-on circuits achieve one or the other of the abovesaid purposes, but not all thereof simultaneously, showing shortcomings either for the excessive consumption of current, or for the excessively long recovery time, or for the narrow range of accepted rise times. The essential aim of the invention is therefore to provide a power-on reset generator of the type described above, which simultaneously satisfies all the abovementioned requirements to a greater extent than known circuits. The above described aim, together with other objects and advantages which will become apparent hereinafter, are achieved by the invention with a generator of reset pulses upon the rise of the power supply in CMOS integrated circuits, characterized in that it comprises: a) an input stage (I) comprising resistive voltage divider means (M1-M5) across the power supply, having a higher voltage node (A) and a lower voltage node (C), and normally open switch means (M8) between the power supply (V cc ) and said higher voltage node, the switch means being controlled by said lower voltage node to short-circuit said higher voltage node to the supply voltage when said lower voltage node reaches a predetermined threshold voltage, whereby the voltage at said higher voltage node rises substantially to the supply voltage; b) a first inverting Schmitt-trigger (T1), driven by the higher voltage node of the input stage and having a switching threshold lower than the value of the supply voltage; c) a first capacitor (C1) connected between said higher voltage node of the input stage and ground; d) an output stage (F) driven by the output of said first Schmitt-trigger (T1) and comprising circuit means (U1-U4, M10-M12, C2, T2) for producing a pulse of a predetermined duration at each switching of the first Schmitt-trigger. A preferred embodiment of the invention, given by way of example, is now described with reference to the accompanying drawings, wherein: figure 1 is block diagram of the generator according to the preferred embodiment of the invention; figure 2 is a circuit diagram of an input stage of the generator of figure 1; and figure 3 is a circuit diagram of an output pulse former constituting a part of the generator of figure 1. With reference to figure 1, the generator according to the preferred embodiment of the invention comprises an input stage I, fed and driven by the supply voltage V cc (typically 5 V), which generates a voltage signal V A to drive a Schmitt trigger T1, the output voltage front V f whereof drives in turn an output pulse former F, the output signal whereof V r constitutes the desired power-on reset pulse. The detailed diagram of the input stage I is shown in figure 2. A chain of five transistors, respectively M1, M2, M3, M4, M5, all diode-connected, act as means for dividing the voltage between the power supply V cc and the ground. The transistors M2, M3, M4 M5 are natural, while the transistor M1 has a raised threshold with high resistance, to reduce the current in the divider. The node C between the transistors M3 and M4 is connected to the gate of a transistor M6, with source connected to the ground and drain leading to the power supply V cc through a diode-connected load transistor M7. The drain B of the transistor M6 drives the gate of a P-channel transistor M8, the source whereof is biased by the node A between the transistors M1 and M2, which node in turn is connected to the node between a diode-connected transistor M9 and a capacitor C1 towards the ground. When V cc rises starting from zero, the voltages V A and V c in the nodes A and C rise according to the division imposed by the chain of transistors M1-M5. When the node C reaches the threshold value of the transistor M6 (this occurring for values of V cc generally comprised between 3.5 and 4.5 V), a positive feedback is triggered which causes the sharp rise of the voltage V A approximately to V cc . The Schmitt trigger T1 detects the state transition of the input stage I, switching its own output V f to a low value. In the former of output pulses F, of which the circuit diagram is shown in figure 3, a cascade of three inverters U1, U2, U3 acts as delayer for the voltage front V f arriving from the Schmitt trigger T1 (not shown in figure 3). The output node of U3 is connected at one side to the gate of a transistor M10 leading to a P-channel load transistor M11, on the other to the input of an inverter U4 with a capacitor C2 shunted on the output, again acting as delay circuit, which drives a transistor M12 in series to M10. The drain of M10 drives a final Schmitt trigger T2 which supplies in output the pulse V r . In the circuit of figure 3, M10 is normally off, while M12 is on, therefore the source of M11 is normally high. When the gate of M10 rises, the source of M11 drops, making the trigger T2 switch. With delay determined by U4 and C2, the transistor M9 is subsequently switched off, interrupting the current towards the ground in the transistor M11, and thus making the source thereof rise again, with consequent re-switching of the trigger T. Thus the trigger T2 is switched twice by the same front, first by direct effect of the signal on the transistor M10, then by delayed effect through the transistor M12. The result is a pulse having a duration which depends on the delay introduced by U4 and C2. The Schmitt triggers T1 and T2 are both of a conventional type, known in the field. For rising V cc , the input stage has high impedance, with the time constant of the node A depending on the series connection of the transistors M1-M5 and on the capacitor C1, which appropriately delays the switching of the trigger T1. This delay is essential to ensure that the trigger T1 is correctly reset, even for extremely rapid wavefronts, with its output at high logical level. The circuit is thus capable of reacting to steeper fronts than those actually allowed by the parasite capacities associated with the supply node. For dropping V cc , the input stage has a very low impedance, since M9 rapidly discharges the node A, and the Schmitt trigger T1 is reset to a condition for generating a new pulse when V A assumes the value of the negative tripping threshold. It should be furthermore noted that in the pulse former of figure 3 there are no conductive paths between the power supply and the ground except during the generation of the pulse. In the input stage, normally only the divider M1-M5 absorbs current, but this current is small, by virtue of the high resistance of M1. The Schmitt triggers do not consume power except during switching. Therefore the total consumption of the circuit is extremely reduced. A preferred embodiment of the invention has been described, but it is understood that it is susceptible to equivalent modifications and variations on the part of the expert in the field, according to the given teachings.

Claims: A generator of reset pulses upon the rise of the power supply in CMOS integrated circuits, characterized in that it comprises: a) an input stage (I) comprising resistive voltage divider means (M1-M5) across the power supply, having a higher voltage node (A) and a lower voltage node (C), and normally open switch means (M8) between the power supply and said higher voltage node, the switch means being controlled by said lower voltage node to short-circuit said higher voltage node to the supply voltage when said lower voltage node reaches a predetermined threshold voltage, whereby the voltage at said higher voltage node rises substantially to the supply voltage; b) a first inverting Schmitt-trigger (T1), driven by the higher voltage node of the input stage and having a switching threshold lower than the value of the supply voltage; c) a first capacitor (C1) connected between said higher voltage node of the input stage and ground; d) an output stage (F) driven by the output of said first Schmitt-trigger (T1) and comprising circuit means (U1-U4, M10-M12, C2, T2) for producing a pulse of a predetermined duration at each switching of the first Schmitt-trigger. The generator of reset pulses according to claim 1, characterized in that the switch means (M6, M7, MR) comprises a first transistor (M8) having a drain connected to the voltage supply, a source connected to the higher voltage node of the voltage divider means, and a gate driven by an amplifier (M6, M7) having an input connected to the lower voltage node of the voltage divider means. The generator of reset pulses according to claim 1 or 2, characterized in that the voltage divider means comprises five diodes (M1-M5) connected in series to each other, said higher voltage node (A) being the junction between the first and second diode from the voltage supply, and said lower voltage node (C) being the junction between the third and fourth diode from the voltage supply. The generator of reset pulses according to one of claims 1 to 3, characterized in that the circuit means for producing a pulse comprises: a) an AND gate (M10, M12) having a first and a second input, and driving a second Schmitt-trigger (T2); b) a monostable device (U4, C2, M12) driving the first input of the AND gate; and c) signal transfer means (U1, U2, U3) driven by the output of said first inverting Schmitt-trigger (T1) and having an output driving both said monostable device and said second input of the AND gate. The generator of reset pulses according to claim 4, characterized in that the AND gate comprises a second transistor (M10) having a drain connected to a load (M11), the source and gate of the second transistor being the first and second input of the AND gate. The generator of reset pulses according to claim 5, characterized in that the monostable device comprises a first inverter (U4) having an output driving the gate of a third transistor (M12) connected with common source, and having its drain connected to the source of said second transistor, the gate of the third transistor being also connected to ground through a second capacitor (C2). The generator of reset pulses according to one of claims 4 to 6, characterized in that the signal transfer means comprises a cascade of three further inverters (U1, U2, U3)

Inventors: DALLABORA, MARCO, GASTALDI, ROBERTO, NOVOSEL, DAVID
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: H03K17
IPC codes: H03K17