ERROR CORRECTING CODE FOR B-BIT-PER-CHIP MEMORY WITH REDUCED REDUNDANCY

Abstract: A reduced redundancy error correction and detection code is shown for memory organized with several bits of the data word on each chip. This package error correction and detection will correct all errors on any one chip and detect errors on more than one chip. A certain arrangement of an ECC matrix is first created for a symbol size code greater than the number of bits per chip. Thereafter certain columns of the matrix are removed to create the final code having a symbol size the same as the number of bits per chip. A specific example of an 80 bit code word is shown having 66 data bits and 14 check bits for a 4-bit-per-chip memory.

Description: Background Of The Invention This invention relates to error detection and correction and in particular to symbol error correction. A symbol is a subset of adjacent bits in a data word and the term package error detection and correction is sometimes used. In particular, this invention relates to reduced redundancy symbol error detection and correction code which has particular application to a memory organized on a b-bit per chip basis where the symbol size is b. Applicants earlier U.S. Patent number US-A-4,464,753 which is assigned to the same assignee as this application shows a general scheme for package error correction and an application to a symbol size of 2. U.S. Patent number 3,634,821 also shows a b-adjacent code. Applicants earlier U.S. Patent number US-A-4,509,172 assigned to the same assignee as this application shows a code for package error detection with reduced redundancy. However, this patent does not show package error correction and is different from the present invention. A package error correction system for a 4 bit per package memory is shown in U.S. Patent number US-A-4,617,664 assigned to the same assignee as this invention. This patent does not shown two symbol error detection, however. In addition, the present invention represents a reduced redundancy over the system shown in the patent. A summary of error-correcting codes is given in the article by CHEN et al "Error-correcting codes for semiconductor memory applications: A state of the art review" published in the IBM Journal of Research and Development, 28(2), March 1984, pp 124-134. U.S. Patent number US-A-4,661,955 assigned to the same assignee as the present invention, shows a system for detecting and eliminating soft errors in a package ECC. The IBM Technical Disclosure Bulletin also contains articles dealing with package error detection or correction. In particular, "SEC-DED Codes With Package Error Detection Ability", November 1979, pages 2356-2359; "Optimized Error Correction/Detection For Chips Organized Other Than By-1", March 1982, pages 5275-5276 and "Dual-Mode Error Correction and Error Detection", June 1985, pages 55-58 illustrate the state of the art but do not anticipate the present invention. Known also from the prior art is the puncturing and shortening of cyclic codes. This is described in "Error-correcting codes" by W. Wesley Peterson and E. J. Weldon, Jr., Massachusetts Institute of Technology, Cambridge, second edition, 1972, pp 213, 240 and 241 and also in "Error-correction coding for digital communications" by George C. Clark and J. Bibb Cain Plenum Press, New York and London, 1981, pp 84-85. Because of the cost of a system, such as a memory, is dependent on the number of bits required for error detection and correction, any reduction in the resource required for the system will produce a cost savings. Therefore, it is desirable to have an improved error correction and detection system with reduced redundancy to save on costs in a system, such as a memory. Summary of The Invention This invention is a symbol or package error correcting and detecting code having a reduced redundancy. An embodiment of the code is shown in connection with four bit-per-chip memories where an SSC-DSD (single symbol correction - double symbol detection) code is shown for 66 data bits with 14 extra bits to form an 80 bit code word. This represents a savings of 2 redundancy bits as compared to the prior art. Thus, there may be two additional data bits in an 80 bit code word. The code according to the invention is formed by first preparing the general form H matrix for a b-bit-per package SSC-DSD code according to the prior art where the symbol size is b, the code length is bN where there are N packages and the number of check bits is r. Then this general form H matrix is converted to a standard form H(s) matrix where the first non-zero bxb submatrix of each of the N b-column groups of the matrix is the bxb identity matrix. The new code is constructed from H(s) by removing the same set of e columns from each b-column group of the H(s) matrix to form an intermediate matrix H(I) where e is the number of reduced bits from the general H matrix SSC-DSD code. Finally, remove the e all zero rows from the matrix H(I) just formed to create a resultant matrix H(r) with symbol size b-e and code length (b-e)N and the number of check bits equal to r-e. The Drawings FIGURES 1A and 1B, viewed in left to right relationship, represent an error correction and detection code matrix for producing check bits for a particular example of a code according to the invention. FIGURES 2A and 2B, viewed in left to right order, represent a resultant matrix for error correction and detection according to the present invention. FIGURE 3 shows the mapping of bit positions to memory chips for a 4-bit per chip memory using the code shown in FIGURES 2A and 2B for a particular embodiment according to the present invention. FIGURE 4 is a block diagram of part of the circuit for the i symbol where i = 1 or 4 - 20 for generating error signals and identifying uncorrectable errors (UEs) for a code in a system according to an embodiment of the present invention as shown in FIGURES 2A and 2B and organized as shown in FIGURE 3. FIGURE 5 is a block diagram of the remainder of the circuit for the i symbol where i = 2 and 3 shown in FIGURE 4 according to the present invention. FIGURE 6A is the H(i) matrix, where i = 20, for multiplication with the S1 signal as shown in FIGURE 4 according to the present invention. FIGURE 6B is the logic required to perform the multiplication of the matrix shown in FIGURE 6A by the S1 signal as shown in FIGURE 4 according to the present invention. Description of the Preferred Embodiment A computer memory designed with an error correcting code (ECC) is conventionally organized in a one-bit-per-chip fashion with respect to the ECC words. This organization guarantees that at most one bit of an ECC word would be corrupted by a chip failure. The class of SEC-DED (single error correcting and double error detecting) codes are normally used to control the errors in the one-bit-per-chip memory systems. The trend in memory chip design has been toward denser and bigger chips. The designs of memory chips that can store 4 megabits and 16 megabits have already been reported. If 4 megabit chips are used to design a one-bit-per-chip memory system with an 8 data byte bandwidth, the minimum system capacity would be 32 megabytes. However, many systems do not require 32 megabytes of storage. As a result, the system designer would be forced to store multiple bits of the same ECC word in the same memory chip. Another advantage of a multiple-bit-per-chip memory organization is that a fewer number of chips has to be powered on at a time. In the future, it will be common for memory systems to be organized in a b-bit-per-chip fashion, where b is greater than one. In a b-bit-per-chip memory organization, a chip failure would generate a symbol error, an error pattern consisting of one to b errors, in the data word. The conventional SEC-DED codes would not be able to effectively control symbol errors. Also, if b is greater than 2, a symbol error may be miscorrected by an SEC-DED code. Thus, there is a potential of losing data integrity. The appropriate ECC for a b-bit-per-chip memory design is the class of SSC-DSD codes that can correct all single symbols errors and detect all double symbol errors in an ECC word, where a symbol error is a b-bit error pattern generated from a chip failure. An SSC-DSD code is capable of correcting all the errors generated from any single chip failures and detecting all the errors generated from two chip failures. A technique is described for the construction of SSC-DSD codes that are more efficient than previous known codes. That is, a new code requires a fewer number of check bits for the same amount of data bits, or a new code can protect more data bits with the same number of check bits as compared to a known SSC-DSD code. For an example, a known SSC-DSD code for 64 data bits and b=4 requires 16 check bits. A comparable new code according to this invention requires only 14 check bits. As another example, for b=4 and 20 check bits, the most efficient known SSC-DSD code can protect 2036 data bits, while a new code according to this invention with 19 check bits can protect 4081 data bits. A code word of an SSC-DSD code consists of N b-bit symbols, or bN bits. Let C = (C1, C2, ..., CN) be a code word, where each component Ci, 1 ≦ i ≦ N, of C is a symbol of b-bit pattern. The code word must satisfy a set of linear equations that can be expressed as: H · C t = 0 mod 2, (1) where C t is the transpose of C, and H, the parity check matrix of the code, is a binary matrix with bN columns. The columns of H can be divided into N b-column groups. If the rank of H is equal to r, then the code has r check bits and bN-r data bits. The code is conventionally denoted as a (bN, bN-r) code, where bN is the code length and bN-r is the number of data bits. The symbol weight of a vector is the number of nonzero symbols in the vector. The symbol distance of two vectors is the number of symbol positions in which the two vectors are different. The minimum symbol distance of a code is the minimum of the symbol distance between any two code words of the code. A code is an SSC-DSD code if the minimum symbol distance of the code is equal to or greater than four. The parity check matrix of a known code constructed according to the prior art has the following general form: where each of the b x b submatrix T ij is either an all zeros matrix or a power of the companion matrix of a primitive polynomial of degree b. For an example, the companion matrix of the primitive polynomial 1 + x + x⁴ is: All 15 distinct powers of this companion matrix are shown in Table 1. Note that T⁰ is the identity matrix and T* is used to denote the all zeros matrix. Note, also that the inverse of T is T⁻¹=T¹⁴, and T -i =T 15-i . Table 2(A) shows the general parity check matrix, in terms of T of Table 1, for a (44,32) SSC-DSD code with symbol size b = 4. Table 2(B) shows the parity check matrix in standard form to be explained later. A word W read from the memory at a particular location may not be the same as the code word C originally written into the same location, because errors may be generated from physical failures. The difference between W and C is defined as the error pattern E. Let W = (W₁, W₂, ..., W N ) and E = (E₁, E₂, ..., E N ) Then W = C + E, and E i = W i - C i for 1 ≦ i ≦ N. From (1), we have The vector S is called the error syndrome. The vector S is calculated from the parity check matrix H and the word W read from the memory, and it is independent of the original code word C that was stored in the memory. If there is no error in W, i.e. E = 0, then S is an all zero vector. On the other hand, if S is not an all zero vector, then errors in W are detected. In this case, the error correction process is to determine first the error pattern E, then to recover the original code word C by the bit-by-bit exclusive or (XOR) operation of W and E, which is equivalent to saying C = W - E. The parity check matrix of an SSC-DSD code with symbol size b and code length bN is said to be in a standard form if the first non-zero bxb submatrix of each of the N b-column groups of the matrix is the b x b identity matrix. If the parity check matrix H is first generated in the general form of equation (2) above, the matrix can be transformed into a standard form using the following algorithm. 1. Set j = 0. 2. Let j=j+1. If j > N, exit. 3. Let k be the smallest integer i, 1 ≦ i ≦ R, such that T ij is a non-zero matrix. Replace T ij by T ij · (T kj )⁻¹ mod 2 for k ≦ i ≦ R, where (T)⁻¹ denotes the inverse of matrix T. 4. Go back to step 2. Applying the algorithm, the parity matrix of Table 2(A) can be transformed into a standard form as shown in Table 2(B). If the original parity check matrix defines an SSC-DSD code, the transformed matrix in standard form also defines an SSC-DSD code with the same number of check bits. A new code is now constructed from a known code. Let H be the parity check matrix of a known (b′N, b′N-r) SSC-DSD code with a symbol size of b′. The number of check bits for the code is equal to r. The procedure to construct a new SSC-DSD code with a symbol (b′-e)=b is as follows: 1. Transform matrix H into a standard form. 2. Delete consistently the same set of e columns from each b′-column group of the matrix in standard form H(s). Then delete the e all zeros rows from the resultant matrix. Let H(r) be the final resultant matrix. Then H(r) is the parity check matrix of an SSC-DSD code with symbol size (b′-e)=b and code length (b′-e)N. The number of check bits is equal to r-e. In general, e can be 1 or greater than 1. If the fourth column of each of the 11 column groups of the matrix in Table 2(B) is deleted, and the fourth row of the matrix is also deleted, the matrix becomes the form shown in Table 3. The new matrix defines a (33,22) SSC-DSD code with symbol size b=3. Table 4 shows the parameters of some new and more efficient SSC-DSD codes that can be constructed from the technique described in this section. A memory system is to be organized in 4 bits per chip, and an SSC-DSD code is to be used to protect 66 data bits. A previously known code would require 16 check bits. From Table 4, a new code of length 136 with 14 check bits can be constructed. This code can be shortened to protect 66 data bits, resulting in a (80,66) code that saves 2 check bits as compared to the best previously known code. Also for an 80 bit code word, two additional data bits may be provided. The construction of a (80,66) SSC-DSD code with b=4 is described below. The primitive polynomial 1 + x² + x⁵, is used along with its companion matrix. Let b′=5, R=3, and N=34. The parity check matrix of the form (2) can be designed to define an SSC-DSD code with a symbol size of 5. The entries of the parity check matrix are powers of T or the 5 x 5 all zeros matrix. Only 20 of the 34 column groups are selected to form the following matrix. Let H be the 15 x 100 binary matrix obtained from the mapping of the above matrix according to the following rules: map * into a 5 x 5 all zeros matrix, and map i into T i , for 0 ≦ i ≦ 30, where T is the matrix of (4). Matrix H defines a (100,85) SSC-DSD code with b′=5. Now, delete the fourth row of H and delete also every other fifth column of H. The resultant matrix H2 is shown in FIGURE 2. This 14 x 80 matrix is the parity check matrix of a (80,66) SSC-DSD code with b=4. In memory system design, it may be desirable to check byte parity in a speedy way. In this case, it is also desirable to be able to include some byte parities as interim results in the generation of ECC check bits. Byte parities do not need to be generated to transfer data. For this consideration, we permute the columns of the matrix in FIGURE 2 to obtain the matrix H1 in FIGURE 1. Matrix H1 will be used to generate the ECC check bits. Refer to matrix H1, any set of 14 bit-positions can be designated as the locations of check bits as long as the corresponding 14 columns of H1 form a non-singular matrix, i.e., those 14 columns are linearly independent. Designate positions 1-12, 21 and 30 as ECC check bit positions. Note that each of the first four ECC check bits can be obtained from the parities of two data bytes (the vertical lines in H1 define the data byte boundaries). For example, ECC bit 4 is the sum (XOR) of byte parity of bits 40-48 and the byte parity of bits 73-80. Matrix H1 provides rules for the generation of the fourteen ECC check bits. From (1), the XOR sum of a code word at the positions indicated by the ones in each row of H1 has to be equal to 0. Thus, the rows of H1 define 14 equations that a code word has to satisfy. The ECC check bits are derived from these equations. For example, check bit 5 is the XOR sum of data bits at positions 15, 17, 19, 20, 23, 26-28, 35, 38-40, 43, 46, 48, 51, 52, 55, 56, 58, 61, 66, 68, 72, 78 and 79. The syndrome of a code word read from the memory is the XOR of the ECC bits read directly from the memory and the ECC bits generated from the data read from the memory. It can be verified that the syndromes of errors in all single chips are nonzero and distinct and the syndromes of errors in all double chips are not the same as any one of the correctable error syndromes. If the fourteen syndrome bits are all zeros, no error is assumed. If the syndrome is nonzero, there are errors in the code word. In this case, the chip positions and bit positions of the errors have to be identified. All double chip errors and some multiple chip errors will be detected as UE (uncorrectable errors). In the following description, the first four bits of the syndrome are called S1 and the last ten bits of the syndrome are called S2. The matrix of FIGURE 2 is used for processing the syndrome in error correction. The matrix is divided into 20 submatrices, one for each chip, of four columns. Each submatrix consists of a 4x4 identity matrix and a 10x4 matrix H(i) for i = 1, 2, ..., 20. To check if a chip i is in error, H(i) is multiplied by S1, and the resultant ten bit pattern is compared with S2. If there is a total agreement, chip i is in error and S1 is the four bit error pattern within chip i. If there is a disagreement, then chip i is error-free. FIGURE 3 shows the assignment of code word bit positions to chips for this embodiment. The block diagram of FIGURE 4 shows the logic for the identification of errors in chip i for i=1 and 4-20. FIGURE 5 shows the logic for chips 2 and 3. If the syndrome is nonzero and there is no error indicator in each of the twenty chips, then the UE signal should be on for an uncorrectable error. The multiplication H(i) by S1 can be implemented with an XOR tree. FIGURE 6B is an illustration of the multiplication for i = 20. H(i=20) is shown in FIGURE 6A. The 1-10 individual output bits are shown at the bottom of the XOR blocks while the 1-4 input bits are shown at the top. Parameters of Some New SSC-DSD Codes No. of Check Bits Symbol Size b Code Length of Best Known Codes Code Length of New Codes 14 4 18x4 34x4 15 3 133x3 257x3 18 3 650x3 1025x3 19 4 257x4 1025x4

Claims: Reduced redundancy Error Checking and Correcting (ECC) code in a b-bit-per-package memory system obtainable by a) determining the general form H parity check matrix of the corresponding single symbol correction-double symbol detection SSC-DSD code with symbol size b' and code length b'N where there are N packages and the number of check bits is r; b) converting the general form H matrix of step a) into the standard form matrix H(s) where the first nonzero b'xb' submatrix of each of the N b'-column groups of the matrix is the b'xb' identity matrix; c) constructing the new code from H(s) by: i) first deleting consistently the same set of e columns from each b'-column group of the H(s) matrix where e is the number of reduced bits from the general H matrix SSC-DSD code, ii) then deleting the e all zeroes rows from the matrix formed in step c) i) to create a resultant matrix H(r) with symbol size (b'-e) = b and code length (b'-e)N and the number of check bits equal to r-e. The ECC code of claim 1 wherein b=4, N=20, code length equals 80 and number of check bits equals 14 and the matrix H1 for generation of the code is: and the matrix for error correction and detection is: The ECC code of claim 1 wherein e is equal to one. Package error correction and detection code in a 4-bit per chip memory having N chips obtainable by first, creating a known error correcting code matrix having a 5-bit symbol length for N packages and a code word length of 5N, second, rearranging the code matrix created in the first step so that the first nonzero 5x5 submatrix of each of the N 5-column groups of the matrix is the 5x5 identity matrix, third, deleting the same 1-column groups from each 5-column group of the matrix formed in the second step, and finally, deleting one all zero row from the matrix formed in the third step to create a resultant matrix with symbol size 4 and code length 4N.

Inventors: CHEN, CHIN-LONG
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H03M13
IPC codes: H03M13, G06F11