AMPLIFIER ARRANGEMENT

Abstract: A signal voltage applied between the input terminals (3, 4) is converted by means of a differential amplifier (T₇-T₁₀) into two phase-opposed signal currents which are inverted by means of a differential-to-single-­ ended converter (10) into a single-ended signal current. The converter (10) comprises a first and a second transistor (T₁, T₂) with a common gate electrode and a third and a fourth transistor (T₃,T₄) also with a common gate electrode, whilst the drain electrode of the third transistor (T₃) is connected to the common gate electrode of the first and the second transistor (T₁, T₂). The common gate electrode of the third and the fourth transistor (T₃, T₄) is main­ tained at a voltage which is equal to the sum of one threshold voltage and two saturation voltages by means of a fifth transistor (T₅) whose gate electrode is connected to the drain electrode and to a bias current source (I₂). The output (5) of the amplifier can be driven by means of this converter (10) up to two saturation voltages of the negative supply terminal (1).

Description: The invention relates to an amplifier arrangement comprising a differential amplifier having two input terminals for receiving an input voltage and a differential-to-single-ended converter having an output terminal for supplying an output current, said converter including a first and a second transistor of a first conductivity type whose source electrodes are coupled to a first supply terminal and whose gate electrodes are coupled together, and a third and a fourth transistor of the first conductivity type arranged in cascode with the first and the second transistor, respectively, and having their gate electrodes coupled together, the gate electrode of the first transitor being coupled to the drain electrode of the third transistor, said differential amplifier including a fifth and a sixth transistor of a second conductivity type opposite to the first conductivity type whose gate electrodes are coupled to the input terminals and whose source electrodes are coupled to a common terminal which is coupled by means of a first current source to a second supply terminal, and a seventh and a eighth transistor of the second conductivity type which are arranged in cascode with the fifth and the sixth transistor respectively, the arrangement also including a bias circuit for biassing the gate electrodes of the third and the fourth transistor at a voltage which is substantially equal to the sum of one threshold voltage and two saturation voltages, said bias circuit including a ninth transistor of the first conductivity type whose source electrode is coupled to the first supply terminal and whose gate electrode is coupled to the common gate electrode of the third and fourth transistor and to its drain electrode. An amplifier arrangement of this type can be generally used as an operational amplifier having a relatively high gain and a relatively large bandwidth. Such an arrangement can be particularly used in video circuits, switched capacitor circuits and sample and hold circuits. Such an amplifier arrangement is known from the US Patent 4,477,782 Figure 3. In this known amplifier arrangement the current through the ninth transistor is supplied by a further transistor of the second conductivity type having its source connected to the junction point of the drain of the fifth transistor and the source of the seventh transistor and having its interconnected gate and drain electrodes connected to both the gates of the seventh and eighth transistor and to the interconnected gate and drain electrodes of the ninth transistor. The further and the seventh transistor have equal dimensions in order to assure equal currents to flow in the branch constituted by the ninth transistor and the branch constituted by the third and the first transistor. By proper selection of the dimensions of the transistors in the differential-to-single-ended converter the gate electrodes of the third and fourth transistor are biassed at a voltage which is substantially equal to the sum of one threshold voltage and two saturation voltages. The output terminal can then be driven up to two saturation voltages with respect to the voltage at the first supply terminal. This yields, particularly at low supply voltages, a wide voltage swing at the output terminal. This known current supply to the ninth transistor has several drawbacks. It limits to an amplifier arrangement in which the gate electrodes of the cascode arranged seventh and eighth transistor are interconnected and biassed at the same voltage as the gates of the third, fourth and ninth transitor. The known current supply is also dependent on the signal current and is not fixed. A third drawback is that the currents in both main signal current branches are not equal any more. This causes offset which has to be compensated for by proper selection of the dimensions of the fourth and second transistor. This complicates the design and reduces the accuracy of the amplifier arrangement. It is an object of the invention to provide an amplifier arrangement not having the afore-mentioned drawbacks. According to the invention an amplifier arrangement of a type described in the opening paragraph is characterized in that the drain electrode of the ninth transistor is coupled to the second supply terminal by means of a second current source. The ninth transistor is directly biassed from the second power supply terminal by means of the second current source. The current intensity of this source and the dimensions of the ninth transistor are selected to be such that the gate-source voltage of the ninth transistor is substantially equal to the sum of the threshold voltage and the saturation voltage of the fourth transistor and the saturation voltage of the second transistor. This bias is fixed, independent of signal current, enables different biassing methods for the gate electrodes of the cascode arranged seventh and eighth transistors and allows equal dimensions in all transistors of the dual-to-single-converter yielding a simpler and more accurate amplifier arrangement. A first embodiment of an amplifier arrangement according to the invention may further be characterized in that a tenth transistor of the first conductivity type is arranged in series with the ninth transistor, the gate electrode of the ninth transistor being coupled to the gate electrode and to the drain electrode of the tenth transistor. The ninth transistor will be generally biassed at a lower current than the second and fourth transistors in order to obtain a low dissipation. To realise the desired bias voltage the channel length of the ninth transistor should be larger than that of the second and fourth transistors. The spread in the channel length of transistors occurring due to process variations thereby influences the gate-source voltage of the ninth transistor and hence the bias voltage in a different way than the gate-source voltages of the second and fourth transistor. By splitting the ninth transistor into two transistors, e.g. the ninth and the tenth transistor, each having a shorter channel length, the bias voltage variations occurring due to process variations are substantially equal to the variations of the voltages of the second and fourth transistors so that the minimum output voltage at the output terminal has become substantially independent of these process variations. A second embodiment of an amplifer arrangement according to the invention may be characterized in that the gate electrodes of the seventh and the eighth transistor are coupled together and in that an eleventh transistor of the second conductivity type is arranged between the common terminal of the source electrodes of the fifth and the sixth transistor and the common gate electrode of the seventh and the eighth transistor, the drain of the eleventh transistor being connected to the eleventh transistor's gate electrode and to the first supply terminal by means of a third current source. The gate electrodes of the seventh and the eighth transistor are biassed by means of the eleventh transistor at a substantially fixed voltage with respect to the common terminal of the source electrodes of the fifth and sixth transistor. A further embodiment may be characterized in that a twelfth transistor of the first conductivity type is arranged in series with the eleventh transistor, said twelfth transistor having its source electrode coupled to the common gate electrode of the seventh and the eighth transistor and having its gate electrode coupled to the second supply terminal. Due to the twelfth transistor the voltage difference between the common terminal of the source electrodes of the fifth and the sixth transistor and the coupled gate electrode of the seventh and the eighth transistor remain substantially constant over a large input d.c. voltage range. A suitable further embodiment may be characterized in that the third current source is constituted by a thirteenth transistor of the first conductivity type whose source electrode is coupled to the first supply terminal and whose gate electrode is coupled to the gate electrode of the ninth transistor. A third embodiment of an amplifier arrangement according to the invention may be characterized in that the arrangement is formed as an integrated circuit on a substrate of a first conductivity type in which the fifth and the sixth transistors are arranged in a zone of a second conductivity type which is connected to the second supply terminal and in which the seventh and the eighth transistors are arranged in separate, zones of the second conductivity type which are connected to the drain electrodes of the fifth and the sixth transistor, respectively, and in that the gate electrodes of the seventh and eighth transistor are connected to the gate electrodes of the fifth and the sixth transistor, respectively. In this embodiment the so-called back-gate effect is used according to which the threshold voltage of a transistor increases as the bulk voltage increases. By connecting the zone in which the fifth and the sixth transistors are formed to a higher voltage than the zones in which the seventh and the eighth transistors are formed, the fifth and the sixth transistors acquire a higher threshold voltage than the seventh and the eighth transistors. This difference is so large that the gate electrodes of the seventh and the eighth transistors can be connected without any problem to the gate electrodes of the fifth and the sixth transistors. A fourth embodiment of an amplifier arrangement according to the invention in which this back-gate effect is also used may be characterized in that the arrangement is formed as an integrated circuit on a substrate of a first conductivity type in which the fifth and the sixth transistors are arranged in a zone of the second conductivity type which is connected to the second supply terminal and in which the seventh and the eighth transistors are arranged in a common zone of the second conductivity type which is connected to the common terminal of the source electrodes of the fifth and the sixth transistors, and in that the gate electrodes of the seventh and the eighth transistors are connected to the gate electrode of the fifth and the sixth transistors, respectively. The invention will now be described in greater detail by way of example with reference to the accompanying drawings in which Fig. 1 shows a first embodiment of an amplifier arrangement according to the invention, Fig. 2 shows a second embodiment of an amplifier arrangement according to the invention, Fig. 3 shows a third embodiment of an amplifier arrangement according to the invention, Fig. 4 shows a fourth embodiment of an amplifier arrangement according to the invention, Fig. 5 shows a fifth embodiment of an amplifier arrangement according to the invention, and Fig. 6 shows a sixth embodiment of an amplifier arrangement according to the invention. Corresponding components have the same reference numerals in these Figures. Fig. 1 shows a first embodiment of an amplifier arrangement according to the invention. It comprises two P-channel transistors T₇ and T₈ arranged as a differential pair whose common source terminal 6 is connected to the positive supply terminal 2 by means of a current source I₁. The gate electrodes of transistors T₇ and T₈ are connected to input terminals 3 and 4 for receiving an input voltage. Two P-channel transistors T₉ and T₁₀ are arranged in cascode with transistors T₇ and T₈, respectively. The transistors T₉ and T₁₀ have a common gate electrode which is maintained at a substantially fixed voltage with respect to the so-called common-mode voltage at the common source terminal 6 by means of a P-channel transistor T₁₁ whose drain electrode is connected to the gate electrode and to the negative supply terminal 1, in this embodiment ground, by means of a current source I₃. A signal voltage applied between the input terminals 3 and 4 is converted by the differential amplifier T₇-T₁₀ into two phase opposed signal currents which can in principle be taken from the drain electrodes of the transistors T₉ and T₁₀. As is known, the cascode transistors T₉ and T₁₀ increase the bandwidth of the amplifier arrangement because the Miller effect of the drain-gate capacitance of the transistors T₇ and T₈ is eliminated. Besides, the output impedance and hence the gain of the amplifier arrangement is increased thereby. The drain electrode of transistor T₉ is coupled to both the drain electrode of transistor T₁₀ and to the output terminal 5 of the amplifier arrangement by means of a differential-to-single-ended converter 10 which converts the differential signal currents in the drain leads of transistors T₉ nand T₁₀ into a single-ended output current at output terminal 5. The converter 10 has two N-channel transistors T₁ and T₂ whose source electrodes are connected to the supply terminal 1 and whose gate electrodes are connected together and to the drain electrode of transistors T₉. Two N-channel transistors T₃ and T₄ are arranged in cascode with transistors T₁ and T₂, respectively. The gate electrodes of these transistors are connected together and are biassed at a fixed voltage with respect to ground by means of a bias circuit. This circuit is constituted by an N-channel transistor T₅ whose source electrode is connected to ground and whose gate electrode is connected to the drain electrode and to the common gate electrode of transistors T₃ and T₄. The drain electrode of transistor T₅ is connected to the positive supply terminal 2 by means of a current source I₂. The transistors T₁ and T₂ of the converter 10 constitute a current mirror which mirrors the current flowing through transistor T₄. The d.c. component therein compensates the d.c. component of the current through transistor T₁₀, whilst the phase-opposed signal currents result in an output signal current which is twice as large. Due to the cascode transistors T₄ and T₁₀ the amplifier arrangement acquires a high output impedance and hence a large gain. Moreover, the cascode transistors T₄ and T₁₀ eliminate the Miller effect of the drain-gate capacitance which is otherwise present between the output terminal 5 and the gate electrode of transistor T₂ and the gate electrode of transistor T₈, respectively. Consequently the amplifier arrangement acquires a large bandwidth. The transistors T₃ and T₉ render the arrangement symmetrical and decrease the d.c. offset at the output. The current intensity of the current source I₂ and the dimensions of transistor T₅ are chosen to be such that the gate-source voltage of transistor T₅ is substantially equal to the sum of the threshold voltage and the saturation voltage of transistor T₄ and the saturation voltage of transistor T₂. The saturation voltage is the minimum drain- source voltage which is required to bias a transistor in its saturation range. Since the gate-source voltage of transistor T₄ is equal to the sum of its threshold voltage and its saturation voltage, the voltage at the source electrode of transistor T₄ is then at least equal to the saturation voltage of transistor T₂ so that the voltage at the output terminal 5 can become at least equal to the sum of the saturation voltages of transistor T₂ and T₄. The output terminal 5 may therefore be driven up to two saturation voltages, that is to say, up to substantially 400 mV of the negative supply terminal ¹ without a loss of gain. Fig. 2 shows a second embodiment of an amplifier arrangement according to the invention. The bias circuit for biassing the common gate electrode of transistors T₃ and T₄ now includes and N-channel transistor T₆ which is arranged in series with transistor T₅ and whose drain electrode is connected to its gate electrode and to the gate electrode of transistor T₅. In the arrangement of Fig. 1 transistor T 5 will be generally biassed at a lower current than the transistors T₂ and T₄ in order to obtain a low dissipation. To realise the desired bias voltage the channel length of transistor T₅ should be larger than that of transistors T₂ and T₄. The spread in the channel length of the transistors occuring due to the process variation thereby influences the gate-source voltage of transistor T₅ and hence the bias voltage in a different way than the gate-source voltages of transistor T₄ and transistor T₂. By splitting transistor T₅ into two transistors T₅ and T₆ each having shorter channel lengths, the bias voltage variations occuring due to process variations are substantially equal to the variations of the voltages of the transistors T₂ and T₄ so that the minimum ouput voltage swing has become substantially independent of these process variations. In this embodiment current source I₃ is formed advantageously by an N-channel transistor T₁₃ whose source is connected to ground terminal 1 and whose gate electrode is connected to the gate electrode of transistor T₅ which is at a fixed voltage with respect to ground. Fig. 3 shows a third embodiment of an amplifier arrangement according to the invention. In this embodiment the series arrangement of a P-channel transistor T₁₁ whose gate electrode is connected to the drain electrode and an N-channel transistor T₁₂ whose gate electrode is connected to the positive supply terminal 2 is arranged between the common source terminal 6 and the common gate electrode of the transistors T₉ and T₁₀. The common gate electrode of the transistors T₉ and T₁₀ is maintained by this arrangement at a fixed voltage with respect to the terminal 6 over a large input d.c. voltage range. In face, the gate-source voltage variations of transistor T₁₁ occurring in the case of input d.c. voltage variations are compensated by oppositely occurring variations of the drain-source voltage of transistor T₁₂ so that the sum of these voltages remains substantially constant. Fig. 4 shows a fourth embodiment of an amplifier arrangement according to the invention. In this embodiment it is not necessary to use a separate bias circuit to bias the common gate electrode of the transistors T₉ and T₁₀ at a substantially fixed voltage with respect to the terminal 6, but the gate electrodes of transistors T₉ and T₁₀ are connected to the gate electrodes of transistors T₇ and T₈, respectively. In this arrangement use is made of the so-called back-gate effect which causes the threshold voltage of a transistor to increase as the voltage between the source electrode and the bulk material in which the transistor is formed increases. In this embodiment the arrangement is integrated on a P-type substrate. The transistors T₇ and T₈ are formed in an N-well 20 which is connected to the positive supply terminal 2 and the transistors T₉ and T₁₀ are formed in N-wells 30 and 40 which are connected to the source electrode of the relevant transistor. Since the source-bulk voltage of transistors T₇ and T₈ is high and that of transistors T₉ and T₁₀ is zero, the threshold voltage of transistors T₇ and T₈ is larger than that of transistors T₉ and T₁₀. The difference between these threshold voltages is present between the source and drain electrodes of transistors T₇ and T₈. Although the source-bulk voltage of transistors T₇ and T₈ is dependent on the input d.c. voltage, this voltage difference is sufficiently large over a relatively large range to drive transistors T₇ and T₈ into saturation so that these transistors can convey a sufficiently large current. The threshold voltage of transistors T₇ and T₈ is, for example substantially equal to 1.4 V over a relatively large range, whilst the threshold voltage of transistors T₉ and T₁₀ is equal to 1.0 Volt. Fig. 5 shows a fifth embodiment of an amplifier arrangement according to the invention. In this embodiment the transistors T₉ and T₁₀ are not arranged in separate N-wells but in one common N-well 40 which is connected to the common source terminal 6. The gate electrodes of transistors T₉ and T₁₀ are again connected to the gate electrodes of transistors T₇ and T₈. In this embodiment both the source-bulk voltage of the transistors T₇ and T₈ and the source-bulk voltage of the transistors T₉ and T₁₀ is dependent on the input d.c. voltage. The source-bulk voltage of transistors T₇ and T₈ is then larger than the source-bulk voltage of the transistors T₉ and T₁₀ so that the threshold voltage of transistors T₇ and T₈ is always larger than that of transistors T₉ and T₁₀. The difference between these voltages is present between the source and drain electrodes of transistors T₇ and T₈ and is larger than the saturation voltage of these transistors over a relatively reasonably large range of the input d.c. voltage so that these transistors can convey a relatively large current. The arrangement of Fig. 5 is built up very symmetrically. This arrangement is very suitable for use as a buffer amplifier. Fig. 6 shows a sixth embodiment of an amplifier arrangement according to the invention. In this embodiment the transistors T₉ and T₁₀ are arranged in a common N-well 40 which is connected to the common terminal 6 of the source electrodes of the transistors T₇ and T₈. The gate electrodes of the transistors T₉ and T₁₀ are interconnected and are connected to the gate electrode of input transistor T₇. This arrangement substantially has the same properties as the arrangement of Fig. 5, but it is built up less symmetrically. The amplifier arrangement of Fig. 6 is particularly suitable for use in an inverting amplifier in which a first capacitor is connected to the input 4 and a second capacitor is arranged between the input 4 and the output 5. If the arrangement of Fig. 5 is used in such an amplifier, the drain-gate capacitance of transistor T₁₀ influences the gain. When using the arrangement of Fig. 6 in such an amplifier, this effect does not occur and the gain is only determined by the first and the second capacitor. The invention is not limited to the embodiments shown and many variations within the scope of the invention are possible to those skilled in the art. The bias circuit for biassing the common gate electrode of the transistors T₃ and T₄ may be formed in any other way than in the manners shown, provided that this voltage is at least equal to the sum of one threshold voltage and two saturation voltages. The differential amplifier may also be built up in any other way than in the manner shown. In the embodiments of Fig. 5 and 6 the common N-well of the transistors T₉ and T₁₀ may in principle also be connected to the source electrode of transistor T₉. Finally, the amplifier arrangement may of course also be formed with transistors of the opposite conductivity type.

Claims: 1. An amplifier arrangement comprising a differential amplifier having two input terminals for receiving an input voltage and a differential-to-single-ended converter having an output terminal for supplying an output current, said converter including a first and a second transistor of a first conductivity type whose source electrodes are coupled to a first supply terminal and whose gate electrodes are coupled together, and a third and a fourth transistor of the first conductivity type arranged in cascode with the first and the second transistor, respectively, and having their gate electrodes coupled together, the gate electrode of the first transistor being coupled to the drain electrode of the third transistor, said differential amplifier including a fifth and a sixth transistor of a second conductivity type opposite to the first conductivity type whose gate electrodes are coupled to the input terminals and whose source electrodes are coupled to a common terminal which is coupled by means of a first current source to a second supply terminal, and a seventh and a eighth transistor of the second conductivity type which are arranged in cascode with the fifth and the sixth transistor respectively, the arrangement also including a bias circuit for biassing the gate electrodes of the third and the fourth transistor at a voltage which is substantially equal to the sum of one threshold voltage and two saturation voltages, said bias circuit including a ninth transistor of the first conductivity type whose source electrode is coupled to the first supply terminal and whose gate electrode is coupled to the common gate electrode of the third and fourth transistor and to its drain electrode, characterized in that the drain electrode of the ninth transistor is coupled to the second supply terminal by means of a second current source. 2. An amplifier arrangement as claimed in Claim 1, characterized in that a tenth transistor of the first conductivity type is arranged in series with the ninth transistor, the gate electrode of the ninth transistor being coupled to the gate electrode and to the drain electrode of the tenth transistor. 3. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the gate electrodes of the seventh and the eighth transistor are coupled together and in that an eleventh transistor of the second conductivity type is arranged between the common terminal of the source electrodes of the fifth and the sixth transistor and the common gate electrode of the seventh and the eighth transistor, the drain of the eleventh transistor being connected to the eleventh transistor's gate electrode and to the first supply terminal by means of a third current source. 4. An amplifier arrangement as claimed in Claim 3, characterized in that a twelfth transistor of the first conductivity type is arranged in series with the eleventh transistor, said twelfth transistor having its source electrode coupled to the common gate electrode of the seventh and the eighth transistor and having its gate electrode coupled to the second supply terminal. 5. An amplifier arrangement as claimed in Claim 3 or 4, characterized in that the third current source is constituted by a thirteenth transistor of the first conductivity type whose source electrode is coupled to the first supply terminal and whose gate electrode is coupled to the gate electrode of the ninth transistor. 6. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the arrangement is formed as an integrated circuit on a substrate of a first conductivity type in which the fifth and the sixth transistor are arranged in a zone of a second conductivity type which is connected to the second supply terminal and in which the seventh and the eighth transistor are arranged in separate zones of the second conductivity type which are connected to the drain electrodes of the fifth and the sixth transistor, respectively, and in that the gate electrodes of the seventh and eighth transistor are connected to the gate electrodes of the fifth and the sixth transistor, respectively. 7. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the arrangement is formed as an integrated circuit on a substrate of a first conductivity type in which the fifth and the sixth transistor are arranged in a zone of the second conductivity type which is connected to the second supply terminal and in which the seventh and the eight transistor are arranged in a common zone of the second conductivity type which is connected to the common terminal of the source electrodes of the fifth and the sixth transistor, and in that the gate electrodes of the seventh and the eight transistsor are connected to the gate electrode of the fifth and the sixth transistor, respectively. 8. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the arrangement is formed as an integrated circuit on a substrate of a first conductivity type in which the fifth and the sixth transistor are arranged in a zone of a second conductivity type which is connected to the second supply terminal and in which the seventh and the eighth transistor are arranged in a common zone of the second conductivity type which is connected to the common terminal of the source electrodes of the fifth and the sixth transistor, and in that the gate electrode of the seventh transistor is connected to the gate electrode of the eighth transistor and to the gate electrode of the fifth transistor.

Inventors: BOUDEWIJNS, ARNOLDUS JOHANNES JULIANA
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1988
Main classification: H03F3
IPC codes: H03F3