Apparatus and method for transferring information

Abstract: A data bus and data bus protocol for transferring messages is presented. The bus protocol signals the end of one message and the beginning of another without using a reset line or the header/trailer scheme. Message separators (1-1) identify the end of one message and the beginning of another. The present invention transmits message separators (1-1) and message data bits (1-3) on the same line and in alternating fashion. The present invention transmits the messages separators (1-1) during a first interval (1-11, 1-15, 1-19..) and message data bits (1-3) during a second interval (1-13, 1-17, 1-21..) The first and second intervals can be the first half cycle (1-5) and second half cycle (1-7) of a clock signal sent on a clock line. When the message separator has a first polarity (1-9), the message data bits following it continue an existing command. When the message separator has a second polarity (1-11, 1-31...), the message data bits following it begin a new message.

Description: FIELD OF THE INVENTION The invention relates to the field of information transfer. In particular, the invention relates to the field of data buses. BACKGROUND OF THE INVENTION Serial data buses send data bits on one line. Additional lines may be included for transmitting clock, handshaking, and reset signals that indicate, among other things, when the data line output has stabilized and is no longer switching from one state to another. Additionally, data buses use these lines to separate messages. The HPIB, a parallel data bus, has special lines to indicate the beginning and the end of a message. Some serial data buses use a reset line to identify the beginning and end of message. Other serial data buses eliminate the reset lines by using a header/trailer scheme to identify new messages. One serial data bus combines the clock and the data on one line and uses a separate reset line to identify the beginning and end of messages. Hardware is used to extract the clock signal. Once the clock signal is extracted it is used to extract the data. This scheme has the disadvantage of requiring extensive hardware to extract the clock signal from the data/clock line. Also this scheme requires a reset line. A separate line for signalling the beginning of a new message has several disadvantages. In addition to the reset wire, hardware is needed to drive the wire, to send the information, and to receive the information. This additional hardware increases computer system cost and increased computer system failure rate. Using headers and trailers to identify the beginning and end of messages has the disadvantage of increasing the amount of time required to send a message and consuming bus bandwidth (where bandwidth is the maximum possible number of signal transitions per second). Headers and trailers have the further disadvantage of requiring the message to be encoded so that the header or trailer cannot occur in a message. Message encoding further decreases bus bandwidth. JP-A-61141232 (Sony Corp.) describes, referring to the abstract, 2-way serial data communication on a single line between a master and a slave set. Successive transmit and receive time intervals are defined on the communication line, the transmit and receive intervals occurring in pairs, successive pairs being separated by a pause interval in which no data communication takes place. The transmit interval for the master set (i.e. the receive interval for the slave set) is signified by a first master bit being transmitted. The subsequent receive interval for the master set (i.e. the transmit interval for the slave set) is signified by a second master bit being transmitted. SUMMARY OF THE INVENTION The present invention provides a method for transferring a message comprising the steps of: sending a message classifier during a first interval; sending a message data bit during a second interval; and sending the message classifier and the message data bit on the same line; characterised by the message classifier indicating the continuation of a message when the message classifier has a first polarity, and the message classifier indicating the beginning of a new message when the message classifier has a second polarity, and further characterised by: using a clock to delineate the first interval and the second interval, wherein the first half of the clock cycle is used for the first interval, and the second half of the clock cycle is used for the second interval. The present invention also provides apparatus for transferring a message comprising: an interval designator means for dividing time into alternating first and second intervals; a message classifier generator means for transmitting a message classifier during said first interval; and a data line for carrying said message classifiers during said first interval and data bits of said message during said second interval; characterised in that the message classifier indicates the continuation of a message when the message classifier has a first polarity and indicates the beginning of a new message when the message classifier has a second polarity, and further characterised in that said interval designator means is a clock transmitted on a clock line, the first half of the clock cycle being used for the first interval, and the second half of the clock cycle being used for the second interval. As illustrated in the preferred embodiment described below, the invention signals the end of one message and the beginning of another without using a reset line or the header/trailer scheme. Message separators identify the end of one message and the beginning of another. The present invention transmits message separators and message data bits on the same line and in alternating fashion. The present invention transmits the message separators during a first interval and message data bits during a second interval. The first and second intervals are defined by the first half cycle and second half cycle of a clock signal sent on a clock line. When the message separator has a first polarity, the message data bits following it continue an existing command. When the message separator has a second polarity, the message data bits following it begin a new message. The present invention can be implemented as a precharged data bus. In this configuration, a bus master transmits the message separators during the first interval and the message data bits during the second interval to various bus slaves. The bus master announces a new message by discharging the data line during the first interval. This produces message separators having a second polarity. The bus master announces the continuation of an existing message by precharging the data line during the first interval. This produces message separators having a first polarity. The method and apparatus for transferring information according to the present invention has the advantage of requiring less hardware. The hardware reduction decreases system cost and failure rate. When the present invention is implemented as a precharged data bus, it obtains an unambiguous message separator without reducing the data rate or adding additional hardware. This unambiguous message separator results from the bus master's exclusive control of the data line. If any erroneous bus operation occurs when the message separators are sent, the erroneous operation will immediately cease. Additionally, when the present invention is implemented as a precharged data bus, it obtains the benefits of a precharged data bus. These benefits arise because only the bus master can send messages. The benefits include reduced bus contention, reduced hardware since only the bus master sends messages, and 1/3 the bus capacitance. The reduced bus capacitance allows the bus to run three times faster. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows the transmission of messages and message separators according to the preferred embodiment of the present invention. Figure 1B shows the transmission of message and message separators according to an alternate embodiment of the invention. Figure 2 shows an apparatus that transmits messages and message separators according to the preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION This description assigns two part numbers to the elements. The first part refers to the figure number and the second part refers to the element. The method according to the preferred embodiment of the present invention sends message data bits 1-3 and message separators 1-1, 1-9 on the same precharged data line. The message separators 1-1, 1-9 are transmitted during the first interval 1-5 and the message data bits 1-3 are transmitted during the second interval 1-7. The clock signal creates the first interval 1-5 and the second interval 1-7. The precharged data line, in accordance with the preferred embodiment of the invention, is shown in Figure 1A. When continuing a message, the precharged data line is precharged during the first interval 1-5 to produce the message separator 1-1 having a first polarity. When beginning a new message, the precharged data line is discharged during the second interval 1-1 to produce the message separator 1-9 having a second polarity. Message data bits 1-3 are always sent during the second interval 1-7. Thus, in the preferred embodiment of the invention, one message separator 1-1 is sent for each message data bit 1-3. The method and apparatus according to the preferred embodiment of the invention is implemented in a system similar to that shown in Figure 2. Figure 2 represents a memory system with a block memory architecture described in United States Patent Application, High Yield Semiconductor Memory Devices , Serial Number 847,411 filed on April 3, 1986 and incorporated herein by reference. This memory system has a memory system controller 2-1 and numerous memory block controllers 2-3. Each memory block controller 2-3 controls a block of memory. The memory system controller 2-1 controls all of the memory block controllers 2-3. In the preferred embodiment of the present invention, the precharged data line and clock line are connected between the memory system controller 2-1 and the memory block controllers 2-3. The memory system controller 2-1 is the bus master and the memory block controllers 2-3 are the bus slaves. Only the bus master, the memory system controller 2-1, can precharge the data line during the first interval 1-5 to create the message separators 1-1. If this memory system has six different commands, than three bits are required to identify the commands. Figure 1A shows the transmission of a message separator 1-11 having a second polarity. This message separator 1-11 identifies the beginning of a new message, a reset. The following message data bit 1-13 is a zero and is followed by a message separator 1-15 of the first polarity which signifies the continuation of the present message. The next two message data bits 1-17 and 1-21 0 and 1 complete the command 001. The two message data bits 1-25 and 1-29 are the data. The data is followed by a message separator 1-31 having a second polarity that identifies the end of the present message and the beginning of the next command.

Claims: A method for transferring a message comprising the steps of: sending a message classifier (1-1) during a first interval (1-5); sending a message data bit (1-3) during a second interval (1-7); and sending the message classifier (1-1) and the message data bit (1-3) on the same line; characterised by the message classifier (1-1) indicating the continuation of a message when the message classifier (1-1) has a first polarity, and the message classifier (1-1) indicating the beginning of a new message when the message classifier (1-1) has a second polarity, and further characterised by using a clock to delineate the first interval (1-5) and the second interval (1-7), wherein the first half of the clock cycle is used for the first interval (1-5), and the second half of the clock cycle is used for the second interval (1-7). A method according to claim 1 further comprising the step of: transmitting the message classifier (1-1) and the message data bits (1-3) on a pre-charged data line; pre-charging the pre-charged data line during the first interval (1-5) to transmit the message classifier (1-1) that signals the continuation of the present message; and discharging the pre-charged data line during said first interval (1-5) to transmit the message classifier (1-1) that signals the beginning of a new message. A method according to claim 2 further comprising the steps of: beginning the transmission of the new message during the second interval (1-7) when the message classifier (1-1) has the second polarity; and continuing the transmission of the present message during the second interval (1-7) when the message classifier (1-1) has the first polarity. Apparatus for transferring a message comprising: an interval designator means for dividing time into alternating first (1-5) and second (1-7) intervals; a message classifier generator means for transmitting a message classifier (1-1) during said first interval (1-5); a data line for carrying said message classifiers (1-1) during said first interval (1-5) and data bits (1-3) of said message during said second interval (1-7); characterised in that the message classifier (1-1) indicates the continuation of a message when the message classifier (1-1) has a first polarity and indicates the beginning of a new message when the message classifier (1-1) has a second polarity, and further characterised in that said interval designator means is a clock transmitted on a clock line, the first half of the clock cycle being used for the first interval (1-5), and the second half of the clock cycle being used for the second interval (1-7). Apparatus according to claim 4 wherein: said message classifier generator means is a bus master (2-1). Apparatus according to claim 5 wherein: said bus master (2-1) precharges said data line during said first interval (1-5) to produce said message classifier (1-1) having a first polarity. Apparatus according to claim 5 or 6 wherein: said bus master (2-1) discharges said data line during said first interval (1-5) to produce said message classifier (1-1) having a second polarity. Apparatus according to claim 5, 6 or 7 further comprising: a bus slave (2-3) connected to said data line for receiving said message classifiers (1-1) and said message data bits (1-3).

Inventors: EATON STEVEN G, EATON, STEVEN G.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1988
Main classification: H04L12
IPC codes: H04L29, G06F13