ACTIVE MATRIX LIQUID CRYSTAL DISPLAY DEVICE

Abstract: Liquid crystal is sealed in between a pair of opposed first and second transparent substrates, picture element electrodes, gate buses, and source buses (19) are formed on the first transparent substrate (11), and thin film transistors are each disposed at one of the intersections of the source and gate buses, thereby constituting an active matrix liquid crystal display element. On the first transparent substrate (11) there are provided capacitive electrodes (31) respectively opposite the source buses (19), with an insulating layer interposed therebetween (33), and the capacitive electrodes (31) are connected to a common potential point (32).

Description: BACKGROUND OF THE INVENTION The present invention relates to an active matrix liquid crystal display device which is composed of an active matrix liquid crystal display element in which picture element electrodes are arranged in a maxtrix form in a liquid crystal cell and electric charges are charged into and discharged from the picture element electrodes by thin film transistors to provide a display, and a driver for driving the liquid crystal display element. A conventional liquid crystal display element of this kind has such a structure as shown in Fig. 1, in which a pair of transparent substrates 11 and 12 as of glass are disposed opposite but adjacent each other, with a spacer 13 interposed between their marginal edges, and liquid crystal 14 is sealed in between the transparent substrates 11 and 12, constituting a liquid crystal cell 10. On the inside surface of the transparent substrate 11 a plurality of picture element electrodes 15 are provided and a thin film transistor 16 is disposed, as a switching element, adjacent each picture element electrode 15, the thin film transistor 16 having its drain connected to the picture element electrode 15. On the inner surface of the other transparent substrate 12 a transparent common electrode 17 is disposed in opposing relation to the plurality of picture element electrodes 15. As shown in Fig. 2, the picture element electrodes 15 square in shape are arranged in a matrix form on the transparent substrate 11, a gate bus 18 is disposed adjacent and along each row arrangement of the picture element electrodes 15, and a source bus 19 is similarly disposed adjacent and along each column arrangement of the picture element electrodes 15. At each intersection of these gate and source buses 18 and 19 the thin film transistor 16 is provided, which has its gate connected to the gate bus 18, its source connected to the source bus 19 and its drain connected to the corresponding picture element electrode 15. By applying voltage across selected ones of the gate and source buses 18 and 19, only that one of the thin film transistors 16 to which the voltage is applied is conducted, charging the picture element electrode 15 connected to the drain of the conducted thin film transistor 16. As a result, a voltage is applied across the liquid crystal 14 only between the charged picture element electrode 15 and the common electrode 17, by which only that portion of the liquid crystal 14 is made transparent or opaque, thus providing a selective display. The display can be erased simply by discharging the stored charges from the conducted picture element electrode 15. For such selective control of the thin film transistors 16, a plurality of outputs of a gate driver 21 which is able to drive the gate buses 18 individually are connected thereto and outputs of a source driver 22 are connected to the source buses 19, respectively. A one-latch-type source driver typically used as the source driver 22 is simple-structured, but when the product of the source input capacitance value and the resistance value between adjacent source buses is small, crosstalk will be produced between the source buses 19, leading to the deterioration of the display characteristic such as lowering of the contrast of a display. US-A-4 581 619 describes a liquid crystal device which comprises a first electrode connected to a terminal of a thin film transistor, a second electrode forming a common electrode and a liquid crystal interposed therebetween. On the first electrode is further provided an opposing conductor film through an insulating film, whereby a charge storage capacitor is formed. Because of the charge storage capacitor, an effective voltage applied across the liquid crystal is kept at a high level, whereby an optical signal with good contrast is given to the image bearing member. In this the device, a capacitor is provided between the picture element electrode and an opposing conductor film. EP-A-0 181 598 describes an active matrix-type display device including thin film transistors as switching elements arranged in the form of a matrix array on a substrate such as a glass plate and used to directly drive a liquid crystal at respective picture elements. Capacitors are provided connected between source lines to the TFT'S and ground for holding the signal applied to the respective source line. The capacitors are provided in a separate source drive circuit away from the display panel. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an active matrix liquid crystal display device which is free from the above-said defect of the prior art. The object of the invention is solved by an active matrix liquid crystal display device as defined in Claim 1. As mentioned above, according to the present invention, the desired electrostatic capacitance is formed by providing the capacitive electrodes in opposing relation to the source buses in the liquid crystal cell, and the source input capacitance becomes large accordingly. In consequence the product of the source input capacitance value and the resistance value between adjacent source buses also becomes large, making it difficult for crosstalk to be generated between the source buses. In addition, since the capacitive electrodes for increasing the source input capacitance are disposed opposite the source buses, even relatively large capacitance values can easily be obtained with no particular necessity of increasing the area of the liquid crystal cell. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view showing a portion of a prior art liquid crystal cell; Fig. 2 is an equivalent circuit diagram of the prior art liquid crystal display device; Fig. 3A is a plan view showing capacitive electrodes 31 employed in the device according to the present invention; Fig. 3B is a sectional view of Fig. 3A; Fig. 4 is a sectional view showing an insulating layer 33 formed over the capacitive electrodes 31; Fig. 5A is a plan view showing source buses 19 formed on the insulating layer 33; Fig. 5B is a sectional view of Fig. 5A; Fig. 6 is an equivalent circuit diagram of the principal part of the device of the present invention; and Figs. 7A to 7C are schematic diagrams illustrating another example of the principal part of the device of the present invention, Fig. 7A being its plan view, Fig. 7B its right side view and Fig. 7C its sectional view. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figs. 3A, 3B to 5A, 5B show a sequence of steps involved in the fabrication of the principal part of an example of the liquid crystal display device according to the present invention. In Figs. 3A and 3B the transparent substrate 11 is the one of the substrates of the liquid crystal cell 10 depicted in Fig. 1. The transparent substrate 11 carries the picture element electrodes 15, the thin film transistors 16, the gate buses 18 and the source buses 19, though not shown. In this embodiment such capacitive electrodes 31 as depicted in Figs. 3A and 3B are each formed on the substrate 11 in opposing relation to one end portion of each source bus 19 (on the side of a connection terminal, for example) to be formed. The capacitive electrodes 31 are connected to a common potential point via a common potential point connection line 32 which extends in the direction of arrangement of the capacitive electrodes 31 for connecting them together. The common potential point connection line 32 is formed simultaneously with the formation of the capacitive electrodes 31. As shown in Fig. 4, a SiO₂, SiN x or similar insulating layer 33 is deposited all over the surface of the substrate 11, covering the capacitive electrodes 31 and the common potential point connection line 32. Next, the source buses 19 are formed on the insulating layer 33 in opposing relation to the capacitive electrodes 31, respectively, as depicted in Figs. 5A, 5B. Usually the picture element electrodes 15, the thin film transistors 16 and the gate buses 18 are formed on the insulating layer 33 in that order, though not shown. Thus, an electrostatic capacitance is provided between each capacitive electrode 31 and the corresponding source bus 18, and the electrostatic capacitance is connected to the common potential point via the common potential point connection line 32; and so that the input electrostatic capacitance of each source bus increases accordingly. In other words, as shown in Fig. 6, an electrostatic capacitance element 34 is connected between the common potential point and each connection line which interconnects the liquid crystal cell 10 and the source driver 22, and the electrostatic capacitance element 34 is formed by the source bus 19 and the capacitive electrode 31 in the liquid crystal cell 10. In the case where the thin film transistor 15 includes a semiconductor layer formed of a material which has a photoconductive characteristic, such as amorphous silicon, the semiconductor layer is shielded from external light, by depositing a light shielding layer as of chromium or like metal on the substrate 11 and then forming an insulating layer, the picture element electrodes, the thin film transistors, etc. in a sequential order. The light shielding layer and the capacitive electrodes 31 can be formed at the same time. By forming the insulating layer 33 simultaneously with the formation of the insulating layer for the light shielding layer, the fabrication of the structure for increasing the source bus input capacitance does not call for any additional manufacturing steps therefor. Figs. 7A to 7C illustrate the principal part of another embodiment of the present invention. The illustrated structure is produced by the steps of forming the source buses 19 on the substrate 11, forming an insulating layer 35 all over the surface of the substrate 11 and the source buses 19, and forming the capacitive electrodes 31 on the insulating layer 35 in partly opposing relation to the source buses 19, along with the common potential point connection line 32 for connecting the capacitive electrodes 31 to the common potential point. In general, the picture element electrodes 15 and the source buses 19 are concurrently formed, which is followed by the formation of the thin film transistors 19 for interconnecting them. The thin film transistors 16 are each produced by forming a semiconductor layer, a gate insulating film and a gate electrode in that order. Accordingly, simultaneous formation of the gate insulating film and the insulating layer 35 and simultaneous formation of the gate electrode and the capacitive electrodes 31 will save the necessity of involving any particular manufacturing steps for providing the electrostatic capacitance which increases the source bus input capacitance. In the case where a time constant for sufficiently reducing crosstalk between adjacent source buses (the product of the source input capacitance value and the resistance value between adjacent source buses) is, for instance, 600 µs or more, and the insulating resistance between source buses of the assembled display devices are as small as 20 MΩ by some cause, it is necessary that the source input capacitance be designed to be 30 pF or more. Since the source input capacitance is usually on the order of 10 pF, however, an electrostatic capacitance of 20 pF needs only to be provided as the electrostatic capacitance between the source bus 19 and the capacitive electrode 31. In concrete terms, for example, where a narrower one of the pair of opposing source bus 19 and capacitive electrode 31 is 0.11 mm wide, the capacitive electrode 31 is 2.2 mm long the insulating layer (an SiO₂ layer, in this example) 33 is 0.4 µm thick, a capacitance of about 20 pF is obtained. The capacitive electrode 31, 1.1 mm long, may also be provided at either end of each source bus 19 in opposing relation thereto. As described above, according to the present invention, a capacitive electrode is disposed opposite each source bus to form an electrostatic capacitance therebetween, by which the source input capacitance can be made large. This reduces crosstalk between adjacent source buses, offering an active matrix liquid crystal display device of an excellent display characteristic. In addition, the electrostatic capacitance for increasing the source input capacitance is included in the liquid crystal cell, and the area of the liquid crystal cell need not be increased therefor. Incidentally, the inclusion of this electrostatic capacitance as an IC in the source driver 22 is attended with the defect of a marked increase in the area of the source driver 22. Furthermore, no particular manufacturing steps are needed for obtaining the electrostatic capacitance intended to increase the source input capacitance, as described previously. It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of the present invention.

Claims: An active matrix liquid crystal display device in which: liquid crystal (14) is sealed in between a pair of opposed first and second transparent substrates (11, 12); picture element electrodes (15) are arranged in a matrix form on the inner surface of the first transparent substrate (11); a gate bus (18) is disposed along each row of the picture element electrodes (15); a source bus (19) is disposed along each column of the picture element electrodes; a thin film transistor (16) is provided at each intersection of the gate and source buses (18, 19) and the gate, source and drain of the thin film transistor are respectively connected to the gate bus, the source bus and the picture element electrode corresponding to the thin film transistor, whereby a liquid crystal element is constituted; and a plurality of outputs of a source driver (22) are respectively connected to the source buses and corresponding capacitors (34), each capacitor being connected between a respective source bus (10) and a common potential point, characterized in that each capacitor is formed on the transparent substrate (11) with a desired electrostatic capacitance between the corresponding capacitive electrode (31) and the corresponding source bus (19), the capacitive electrodes (31) being provided in opposing relation to the source buses (19), respectively, with an insulating layer (33 or 35) sandwiched therebetween. The device of claim 1, wherein a common potential point connection line (32) is provided along the direction of arrangement of the capacitive electrodes (31), for connecting them to the common potential point. The device of claim 1, wherein the capacitive electrodes (31) are disposed closer to the first transparent substrate than the source buses (19). The device of claim 3, wherein a light shielding layer of metal is disposed opposite the thin film transistors, the light shielding layer and the capacitive electrodes (31) are formed simultaneously and an insulating layer between the light shielding layer and the thin film transistors and the insulating layer (32) are formed simultaneously. The device of claim 1, wherein the capacitive electrodes (31) are disposed on the side of the isolating layer (35) opposite from the first transparent substrate (11) relative to the source buses (19). The device of claim 5, wherein the insulating layer (35) is formed simultaneously with gate insulating films of the thin film transistors and the capacitive electrodes (31) are formed simultaneously with gate electrodes (18) of the thin film transistors (16).

Inventors: SUNATA, TOMIHISA C/O HOSIDEN ELECTRONICS CO.,LTD., UKAI, YASUHIRO C/O HOSIDEN ELECTRONICS CO.,LTD., YUKAWA, TEIZO C/O HOSIDEN ELECTRONICS CO.,LTD.
Applicants: HOSIDEN CORPORATION
Application year: 1988
Main classification: G02F1
IPC codes: G02F1, G09F9, H01L29, H01L21, H01L27