HIGH-SPEED ANALOG MULTIPLIER - ABSOLUTE VALUE DETECTOR

Abstract: A high-speed analog multiplier circuit (Figs. 3-6) for multiplying two analog inputs (X, Y) comprises a signum gen­ erator (21) having an X input multiplier (at 26, 27) and having an output connected to a high-speed electronic switch (22) A Y analog input multiplicand (at 28) is also connected to the high-speed electronic switch (22) and the output of the elec­ tronic switch (32, 33) having a positive input (33), a negative input (32) and a resultant output (24) for producing the sign­ num function (X) times Y. The electronic switch (22) is operated by the signum generator (21) so that the presence of a high Q output from the signum generator (21) is effective to connect the Y multiplicand input (28) to the positive input (33) of the differential amplifier (23) and that the presence of a high Q input (27) from the signum generator (21) is effective to connect the Y multiplicand input (28) to the negative input (32) of the differential amplifier (23).

Description: Background of the Disclosure 1. Field of the Disclosure This disclosure relates to high-speed analog multipliers. More particularly, this disclosure relates to a novel analog multiplier which employs a minimum number of high-speed logic devices for producing multiplied analog voltage results or alternatively distortion free absolute voltage values of analog inputs. 2. Description of the Prior Art Analog multipliers are known to be relatively slow devices and heretofore have been limited to a speed of around 25 megahertz before distortion renders the output unusable. Absolute value detectors, such as full wave bridge rectifiers, have been limited to the same range of frequencies of around 25 megahertz at the output and even then distortion is present and so that such circuits are not useful where extreme accuracy is desired. Absolute value detectors have been produced employing full wave rectification of an A.C. signal produced across the secondary coil of a transformer from an input signal applied to the primary coil of the transformer. While such rectifiers save at least two diodes over a full wave bridge rectifier, such devices are slower and have an output which is distorted not only by the diodes but by the inductive reactance of the transformer. High-speed full wave rectifiers which employ diodes are limited to the operable frequency of the diodes and further are limited to the distortion characteristics or efficiency of the type of diode being employed. Presently, commercially available diodes are subject to distortion which limits their use to a level below their maximum operable frequency. It is well known that there is an accompanying DC offset when employing diodes in full wave rectifiers. Further, since diode rectifiers employ a plurality of diodes, operation of unmatched diodes at high-speed causes amplitude distortion due to imperfect balance of the diodes. It is possible to manufacture diodes which can be operated at higher speeds than those which are generally commercially available. However, the distortion and DC offset will always be present when using diodes and a full wave rectifier. It would be extremely desirable to provide a high-speed analog multiplier which is also operable as an absolute value detector or a high-speed chopper for producing distortion free output signals. Summary of the Invention It is a principal object of the present invention to provide a high-speed analog multiplier. It is another primary object of the present invention to provide a high-speed analog multiplier which is operable as an absolute value detector to produce absolute analog voltage values. It is another principal object of the present invention to provide a high-speed analog multiplier which is operable as a high-speed chopper for producing distortion free chopped voltage signal outputs. It is another object of the present invention to provide a high-speed analog multiplier whose speed of operation is only limited by the speed of operation of the semiconductor devices used to perform the switching operation. INTENTIONALLY LEFT BLANK According to these and other objects of the present invention there is provided an analog signal processing circuit as claimed in Claim 1. Brief Description of the Drawings Figure 1 is a circuit diagram of a prior art full wave diode rectifier; Figure 2 is a waveform diagram of the output voltage of the rectifier of Fig. 1; Figure 3 is a schematic diagram of the preferred embodiment of the present invention high-speed analog multiplier; Figure 4 is a truth table of the input signum generator shown in Fig. 3; Figure 5 is a circuit diagram of the preferred embodiment signum generator; Figure 6 is a circuit diagram of the preferred embodiment high-speed electronic switch and differential amplifier which can be employed in the embodiment of Fig. 3; and Figure 7A thru 7E is a plurality of waveforms showing the analog voltages present at the input and output of the Fig. 3 preferred embodiment high-speed analog multiplier. Description of the Preferred Embodiment Refer now to Figure 1 showing a prior art full wave diode rectifier comprising diodes D1 through D4. An AC generator 11 is connected across input lines 12 and 13 to input points 14 and 15 of the diode bridge. The output points 16 and 17 of the diode bridge produce a DC rectified current on output line 18 across the load resistor R L . Refer now to Fig. 2 showing a DC rectified waveform which appears on output line 18 of Fig. 1. It will be noted that the negative excursion of the sinusoidal input from AC generator 11 is inverted and appears as a positive excursion sinusoidal pulse thus producing a DC voltage V L whose absolute value is the peak of the positive and negative excursions of the sinusoidal input. Refer now to Fig. 3 showing a schematic block diagram of the preferred embodiment of the present invention high-speed analog multiplier 20. The multiplier 20 comprises at the input a component 21 which is a signum generator coupled to a high-speed electronic switch 22 which in turn is coupled to a difference or summing circuit 23 to produce a result or resultant sum equal to signum (X) · Y. The X input 25 is connected through a switch S2 to the input of the signum generator 21 to produce a real value Q output and an inverted value Q output on lines 26 and 27 which are connected to the electronic switch 22. The X input is discussed hereinafter as the multiplier input and a second Y analog input on line 28 is also connected to the electronic switch 22. A normally open switch S1 forms a shunt across the X and Y inputs and when closed is employed to produce the absolute value of the analog input X at the output 24 as will be explained in greater detail hereinafter. When the switch S1 is closed and the switch S2 is open, it is possible to obtain the absolute value of Y at the output 24. A switch S3 is provided in the Q output of generator 21 in order to remove the signum generator effectively from the circuit for special operations which will be discussed hereinafter. Electronic switch means 22 is shown having electronic switches 29 and 31 with their poles in the center position. Diagramatically, the four possible values of Q are shown opposite the contacts of the switches 29 and 31 illustrating that the pole of switch 29 will be connected to the Q H contact when the Q output of generator 21 is high. Similarly, when the Q output of generator 21 is high, the pole of switch 31 is in its lower position and connected to ground. When the Q output is high, the Q H contacts are connected to the poles of the switches 29 and 31 and the switch 29 is connected to ground and the switch 31 is connected to the Y analog input on line 28. Thus, it will be understood that electronic switches making connections to either a low reference or a Y analog input voltage can be implemented and the switches can be operated by the signum generator 21 which, effectively positions the pole switches 29 and 31 to the correct input values being applied on lines 32 and 33 and to the differential amplifier 23 to produce the multiplied value sgn (X) · Y. The novel analog high-speed multiplier is operable in an absolute value detector mode. When switch S1 is closed the output on line 24 is the sgn (X) · X or the absolute value of X. Similarly, when switch S1 is closed and switch S2 is open the output on line 24 is sgn (Y) · Y or the absolute value of Y. In another preferred mode of operation, an analog value may be applied to the input 28 as a Y analog input and a high-speed clock applied to the X input on line 25 to produce sgn (X) · Y where the square wave X produces a chopped output as will be explained in greater detail hereinafter. Refer now to Fig. 4 showing a truth table for the signum generator 21 of Fig. 3. When the value shown as the value of X is greater than zero, the signum of X output is binary 1. When the value of X is zero, the signum of X output is also zero. However, when the value of X goes below zero and is negative, the signum of X is a binary minus one. It is well known by those skilled in the art that the truth table of Fig. 4 may be implemented in high-speed hardware. Refer now to Fig. 5 showing a simplified embodiment circuit diagram for a signum generator 21. A reference voltage input on line 34 is applied to comparator 35. The X analog input on line 25 is applied to the second input of comparator 35 to produce the aforementioned real Q and inverted Q outputs as discussed hereinbefore with regards to Figures 3 and 4. The comparator 35 may be implemented with high-speed gallium arsenide transistors in several different ways with logic circuits. Refer now to Fig. 6 showing a circuit diagram of the preferred embodiment electronic switch 22 which may be employed in the Fig. 3 embodiment. Electronic switch 22 is shown comprising field effect transistors T1, T2, T3 and T4 having source gate and drain connections. The Y input 28 is connected to the source of transistors T1 and T3. The Q output of the signum generator 21, shown as input 26 for the Q output, is connected to the gate of transistors T1 and T2. The inverted Q or Q output of signum generator 21 on line 27 is connected to the gates of transistors T3 and T4. When the value of Q on line 26 goes high, the value of Q on line 27 is automatically the reverse or low input. The high value on line 26 closes transistor T1 connecting the Y input on line 28 to line 33 connected to the plus input of the differential amplifier 23. Similarly, the high Q output on line 26 closes transistor T2 connecting the ground to input line 32 of differential amplifier 23. In similar manner, when the Q input on line 27 goes high it closes transistors T3 and T4 connecting the Y input to the line 32 negative input of differential amplifier 23 and the ground connection of transistor T4 to the input line 33 of the positive side of differential amplifier 23. It will be understood that transistors T1 through T4 are being switched by the input values Q and Q when the value of X is sensed as being less than or greater than zero. Thus, the transistors are being switched at the crossover nodes of the sinusoidal or analog inputs producing high-speed operations to connect the Y input on line 28 to an inverting or non-inverting differential amplifier 23 to produce an actual analog multiplication sgn (X) · Y or the absolute value of X or Y depending on the inputs. Further, it will be understood that when the X input is a square wave clock, the values of Q and Q on lines 26 and 27 are switching on the leading and trailing edges of the clock to produce a chopped output as will be explained in detail with regards to Fig. 7. Refer now to Figs. 7A to 7E showing waveforms of the analog voltages present at the input and output of the Fig. 3 and Fig. 6 embodiments. Figure 7A shows a sinusoidal analog input as applied to the Y input line 28 and Fig. 7B shows a 90 degree phase shifted sinusoidal wave being applied to the X input line 25 which is identified as a cosine wave. All different types of analog input waveforms may be applied to the input lines 28 and 25 to produce the multiplied result on line 24. When the cosine input on line 25 is applied to the signum generator 21 it produces a square wave or clocked output as shown in Figure 7C at line 26. This clock output, resulting from the phase shifted sinusoidal input on line 25, produces a chopped output on line 24 as shown in Fig. 7D. Each waveform is producd by a pulse transition. It is also possible to apply a square wave clock to line 25 at the X input to produce the same or similar chopped output on line 24 as shown in Fig. 7D. When switch S1 is closed and switch S2 is open and the analog input Y on line 28 shown in Figure 7A is applied, a full wave rectified output of the analog value of Y is produced at the output line 24 which is the sgn (Y) · Y or the absolute value of Y. Further, when switch S2 and S1 are both closed and the cosine value shown in Figure 7B is applied to the X input line 25 a similar full wave rectified output will be produced on line 24 which is the sgn (X) · X which is the absolute value of X and is identical to Figure 7E except it is phase shifted 90 degrees. Having explained Figure 7 employing sine and cosine waves, it will be appreciated that the analog inputs on the X and Y lines 25 and 28 may take any analog form. And that the multiplication resultant which occurs on output line 24 is distortion free because the switches of the electronic switch 22 only serve to perform a multiplying operation and in no way affect the vector value of the analog voltage. When employing the novel multiplier as an absolute value detector there is no diode distortion as occurs with full wave diode rectifiers nor are there any harmonics of the type associated with the operation of diodes at high-speeds so that the present invention does produce the true absolute value without distortion or DC offset.

Claims: An analog signal processing circuit having a reference signal input (X or Y) and a detected signal input (Y) coupled to an electronic switch (22) controlled by the reference signal input, characterized in that: the processing circuit comprising a high speed analog multiplier having an analog multiplicand (Y) coupled to the input of a distortion free high speed electronic switch means (22), and a high speed generator/comparator (21) having an input multiplier (X or Y) and a pair of switch control outputs (Q and Q ) coupled to the input of said electronic switch means (22), and amplifier means (23) having a positive input (33) and a negative input (32) coupled to outputs from said electronic switch means (22) so that the presence of (Q) in the high voltage state at the input of said electronic switch means (22) connects the multiplicand input (Y) to the positive input (33) of said amplifier means (23) and connects the negative input (32) to a predetermined reference voltage; and the presence of ( Q ) in the high voltage state at the input of said electronic switch means (22) connects the multiplicand input (Y) to the negative input (32) of said amplifier means (23) and connects the positive input (33) of said amplifier means (23) to said predetermined reference voltage, whereby the multiplication product (X.Y) at the output (24) of said amplifier means is free of distortion and capable of frequencies in excess of 25 megahertz. An analog signal processing circuit as set forth in claim 1 wherein said generator/comparator (21) comprises a signum generator (21). An analog signal processing circuit as set forth in claim 1 wherein said amplifier means (23) comprises a differential amplifier (23). An analog signal processing circuit as set forth in claim 2 which further includes means for connecting said X input to said Y input, and the product output of said amplifier means (23) is a value signum (X) . Y and is operable as an absolute value detector. An analog signal processing circuit as set forth in claim 1 wherein said electronic switch means (22) comprises a plurality of semiconductor switches (T1-T4) having their gates (G) controlled by said Q and said Q outputs from said signum generator (21). An analog signal processing circuit as set forth in claim 5 wherein said semiconductor switches (T1-T4) each comprise high-speed field effect transistors. An analog signal processing circuit as set forth in claim 6 wherein said high speed field effect transistors comprise, a first pair of transistors (T1, T4) having their outputs connected together and to the positive input of said amplifier means (23), and a second pair of transistors (T2, T3) having their outputs connected together and to the negative input of said amplifier means (23), said switch control output (Q) being connected to the gate of one of said transistors (T1, T2) of one of each pair of said transistors (T1, T4 and T2, T3), said switch control output ( Q ) being connected to the gate of the other ones of said transistors (T3, T4) of each pair of said transistors, said multiplicand input (Y) being connected to an input of one of said transistors (T1, T3) of one of each pair of said transistors (T1, T4 and T2, T3), said reference voltage being connected to an input of other ones of said transistors (T2, T4) of each pair of transistors, and whereby said high speed multiplier circuit performs the analog multiplication of multiplier (X) times the multiplicand (Y) to produce the analog result signum (X) . (Y). An analog signal processing circuit as set forth in claim 1 wherein the multiplicand input (Y) is an analog voltage input. An analog signal processing circuit as set forth in claim 1 wherein the multiplier input (X) and the multiplicand input (Y) are both analog voltage inputs. An analog signal processing circuit as set forth in claim 1 wherein said multiplier input (X) is hard wire connected to said multiplicand input (Y) and the circuit produces the analog result signum (X) . X equal to the absolute value of X. An analog signal processing circuit as set forth in claim 7 which further includes an electronic switch (S2) in series in the multiplier (X) input. An analog signal processing circuit as set forth in claim 7 which further includes an electronic switch (S3) in one of said outputs (Q, Q ) from said generator/comparator (21). An analog signal processing circuit as set forth in claim 3 which further includes a shorting bus (S1) for connecting the multiplier input (X) to the multiplicand input (Y) of said generator/comparator (21) so that the output of said differential amplifier (23) detects the absolute value of X. An analog signal processing circuit as set forth in claim 13 wherein said generator/comparator (21) performs a signum function output on the multiplier input (X) wherein the value of (Q) at the output is either a one (1) or a minus one (-1). An analog signal processing circuit as set forth in claim 14 wherein the value of (Q) is always one when the analog value of X is greater than zero.

Inventors: KEATE, CHRISTOPHER, R.
Applicants: UNISYS CORPORATION (A DELAWARE CORP.)
Application year: 1988
Main classification: G06G7
IPC codes: G06G7, H03D1