APPARATUS FOR GENERATING A CURSOR PATTERN ON A DISPLAY

Abstract: An apparatus for generating a cursor pattern on a display (1) includes a frame buffer memory (2) for storing a display pattern. The frame buffer memory (2) is provided with an addressable memory section (3) for storing data representing the cursor pattern. A first register (6) is coupled to the memory section (3) for successively receiving and storing lines of the cursor pattern data, while a second register (7) is coupled to the frame buffer memory (2) for successively receiving and storing lines of display pattern data. A logic means (14) is provided for receiving and logically combining corresponding lines of cursor pattern data and display pattern data, and a counter (9) is provided for controlling the timing of the flow of data from the first register (6) to the logic means (14).

Description: APPARATUS FOR GENERATING A CURSOR PATTERN ON A DISPLAY Technical Field The present invention relates to an apparatus for generating a cursor pattern on a display, and more particularly to an apparatus including a frame buffer memory for storing data relating to a display pattern. Background Art Cursors are shape, color or brightness differences in the representation on the video display which relate the user's activity to information within the work station or computer system. Cursors can be as small as a single pixel in a bit mapped display or, as is more common, may comprise multiple pixels arranged into an informative pattern such as a clock, an arrow, an index finger or a hand. Cursors are most often created by software routines which temporarily move the underlined information off the screen and replace that information with a cursor pattern. Software generated cursors degrade in performance when the cursor or screen patterns either move or are subject to windowing. Hardware implemented cursors which presently exist require additional high speed memories of significant size to store the complete two dimensional cursor pattern, and control logic or microprocessor operations to insert such patterns in synchronism with the scan of the frame buffer data. U.S. Patent No. 4,454,507 is directed to the superposition of vector cursors composed of lines. The cursor generation system therein requires a high speed external memory of significant size, in that the complete cursor pattern is stored in a supplemental memory. A further teaching of cursor generation is set forth in U.S. Patent No. 4,668,947 where predefined cursor shapes are stored externally and interjected into the displayed pattern during the scan of the frame buffer by address jumps to a supplemental high speed memory. The implementation of the patent requires not only the external high speed memory but means for tracking both the X and Y axes of the bit mapped display in order to identify the locations where cursor information is to be inserted. Disclosure of the Invention It is an object of the present invention to provide a simple apparatus for generating the cursor pattern, and which generates a cursor pattern unaffected by frame buffer display pattern changes. According to the present invention there is provided an apparatus for generating a cursor pattern on a display, including a frame buffer memory for storing a display pattern, characterized by said frame buffer memory having an addressable memory section for storing data representing the cursor pattern, first data storing means for successively storing lines of the cursor pattern data, second data storing means for successively storing lines of display pattern data, logic means for receiving and logically combining corresponding lines of cursor pattern data and display pattern data, and control means for controlling the timing of the flow of data from said first data storing means to said logic means. The first data storing means may comprise a register coupled to said addressable memory section for receiving therefrom a string of data bits representing the cursor pattern for a line of said display. Similarly the second data storing means may comprise a shift register coupled between said frame buffer memory and said logic means. In a preferred embodiment said frame buffer memory is a dual port random access memory array, and said first data storing means is operable during the horizontal blank time of said display. In another embodiment said control means is a counter arranged to determine that time at which said logic means commences to receive data from said first data storing means. Brief Description of the Drawings Embodiments of the present invention will now be described by way of examples, with reference to the accompanying drawings in which: Fig. 1 schematically illustrates a functional block diagram of a bit mapped video display system embodying the present invention. Fig. 2 is a schematic illustrating the frame buffer allocation both specially and temporally. Fig. 3 schematically illustrates the formation of a cursor pattern and a cursor outline in the context of the present embodiment. Best Mode for Carrying Out the Invention Attention is now directed to Fig. 1 of the drawings, where there is shown in block diagram form an embodiment of the present invention suitable to generate and control a cursor for a bit mapped video display of otherwise conventional form. The cursor generation architecture depicted in Fig. 1 creates a hardware type cursor overlay using a temporary buffer to store 48 cursor data bits and a column position counter to synchronize with the frame buffer raster scan. The full pattern of the cursor is stored in a non-displayed section of the frame buffer at an address coincidence with the row location within the video display. Consequently, every row line of the bit mapped display has associated therewith a corresponding 48 bit long strip of cursor information. The cursor information is read into the 48 bit temporary buffer from the non-display section of the frame buffer by raster line during the horizontal blanking time following the raster scan of the previous line. As preferably implemented with a dual port video memory system, the data in the frame buffer for the next line to be displayed is transferred during such horizontal blank time to a video display shift register. Thereafter, during the actual scan of the buffered line, the clock synchronized transfer of video display shift register data to the video display is selectively modified by logical combinations with the cursor strip data by action of a counter operated to identify the beginning and end locations of the cursor strip within raster line. This operation is repeated for each line of displayed frame. The particularized functional blocks in Fig. 1 can now be referenced to the functional objectives set forth above in the context of the depicted preferred embodiment. As shown in Fig. 1, the video display 1 has a pixel capability of 1024x800. The characteristics of the pixels are defined by bits stored in the frame buffer dynamic random access memory (DRAM) array 2. Memory array 2 is a dual port video memory having an addressable size greater than the pixel count of display 1, the non-displayed portion generally represented by the section 3. Conceptually, an embodiment of the present invention could be applied to a bit mapped display system using a single port video memory. Such implementation would, however, be somewhat impractical given the limited blank time available for pattern changes to be introduced by the computer. The particular architecture embodied in Fig. 1 includes a pair of 24x1 cursor registers 4 and 6, a conventional 1024x1 video display shift register 7, a master source of clock signals 8, a cursor strip positioned counter 9, a logic lookup table 14, and conventional buffer and synchronization and scan control devices generally depicted as blocks 16 and 17. Fig. 2 schematically illustrates the spatial and temporal allocation of the frame buffer for the present embodiment. Frame buffer 2 is comprised of a bit mapped video display memory segment which stores the actual frame pattern for the video display, as well an addressable but non-displayed cursor strip memory segment. Addressing of the cursor strip memory segment is related by line to the video displayed memory segment. The availability of such non- displayed segment of the frame buffer arises, as commonly known, from the arrangement memory in binary increments numerically different than the pixel count of the video display. The generation of a cursor, such as pointer 18 on video display 1, begins with the generation of a cursor block outline and the further definition of an internal pattern of the cursor by the computer. The pattern so defined is loaded into cursor strip memory segment 3 during the conventional frame buffer writing operation. The line address of the cursor is matched to the line location within the video display at which the cursor is to appear. The column location of the cursor is defined by a coarse cursor strip positioned reference number which is operable to start at 8 pixel position increments. As so defined, there exist data representing a cursor in non-displayed frame buffer which is aligned by row or line to its intended location in the video display frame and aligned at 8 pixel increments by column address entered into cursor strip position counter 9. At the conclusion of each raster line scan, during the horizontal blank time, 48 bit long strips of cursor data for the next succeeding line of the video display are shifted from frame buffer memory segment 3 to registers 4 and 6. At the beginning of the next raster scan cycle, the corresponding line of video data in the frame buffer is transferred in conventional manner by row into video display shift register 7. Consequently, at that time, the data representing the video pattern for the next succeeding raster line is resident in video display shift register 7, the cursor data for the same line is resident in registers 4 and 6, and data representing the cursor strip column location resides in position counter 9. Upon the commencement of the next scan and synchronous therewith, clock 8 shifts from register 7 the video data by pixel to logic lookup table 14. For those pixel positions where no cursor data is to be superimposed, cursor pattern register 4 and 6 are disabled by cursor strip position counter 9. Counter 9 is incremented at 8 pixel steps synchronous to clock 8. The clock synchronize raster scan continues across video display 1 using the data in shift register 7 until cursor strip position counter 9 identifies the starting location for the cursor data block. Thereafter, for an interval of 24 pixel positions, logic lookup table 14 receives not only the originally defined video display shift register data but cursor outline data from register 4 and cursor pattern data from register 6. The cumulative logic effects, as defined by the desired boolean relationship established in block 14, are actually transmitted to video display 1 through buffer 16. After such 24 clock cycles, cursor registers 4 and 16 are effectively disabled to return the pattern of display 1 to that stored in video display shift register 7 alone. The cycle is repeated with the conclusion of the raster line, and the onset of the horizontal blanking time, with the transfer of 48 bits of data representing the next line of cursor. Fig. 3 illustrates the generation of a cursor, including a cursor outline 19 and a cursor pattern 21. The rows of the outline and pattern pixels match the video display, while the column location is defined by the computer identified during the raster scan by the position counter 9 at intervals of 8 pixels. For instance, in the context of Fig. 3, the cursor outline and resident internal pattern can start at any column which is a multiple of 8 pixel positions and will conclude 24 pixel positions later. As shown, the outline begins at a pixel position m and concludes with a position m+24. Positioning of the cursor pattern 21 within cursor outline 19 at single pixel increments is performed by the computer during the generation of the pixel pattern. For example, as shown at 22, the pattern may be shifted within the outline during the generation of the pattern with reference to the outline. Thereby, the actual pattern of the cursor may be positioned within the full one pixel precision of the video display for so long as the line length of the pixel pattern is 8 pixel positions shorter than the length of the pixel outline. In the context of Fig. 3, full column position precision can be retained for a pattern composed of 16 or fewer pixel columns. Increasing the sizes of registers 4 and 6 in Fig. 1 concurrently increases the new length of the cursor patterns which can be generated. On the other hand, such extensions of cursor dimensions do consume additional area in non-displayed frame buffer segment 3. For the present arrangement the cursor data is allocated a memory space of 48x800. Such a segment is well within the reserved of the 131072x8 frame buffer 2, in that the memory associated directly with the pixel count of the video display 1 leaves approximately 230,000 bits of addressable memory unused. Note that the defined 48x800 strip of non- displayed frame buffer allocated to pixel data consumes approximately 40,000 bits of such residual memory. The use of logic lookup table 14 in Fig. 1 to introduce a boolean relationship into the pattern actually transmitted to video display 1, based on a combination of the originally defined video display pattern, the cursor outline, and the cursor pattern, provides the user with the ability to overlay the cursor in a visible form irrespective of the background. For instance, a black cursor pattern placed on a black background would not be visible, while a black cursor pattern framed within a white cursor outline and placed against a black background would be perceivable. An XOR implementation of a cursor outline is an example of a popular approach to retaining a cursor pattern irrespective of the background. In another embodiment of the present invention that the cursor strip of 24 pixels line length is fully capable of extending in the column direction from the top of the video display to the very bottom of the video display. Consequently, the cursor can be configured and logically combined in a pattern of up to 24x800 pixels dimension. This provides the use with a great degree of flexibility when compared to the commonly utilized 16x16 size cursor blocks, especially given the need for 512 bits of additional high speed video memory to implement even such small cursor patterns. In the composite, an embodiment of the present invention provides an architecture by which the non-displayed frame buffer section 3 can be utilized to store a relatively elaborate cursor pattern extending the full height of the screen while using a relatively short bit length buffer, is implemented to logically combine cursor data with frame buffer pattern data, overlays complex frame buffer patterns notwithstanding the presence of windows or scrolling, and provides these features without unduly burdening the computer with elaborate software manipulations or transfers of frame data to temporary store.

Claims: CLAIMS : 1. An apparatus for generating a cursor pattern on a display (1), including a frame buffer memory (2) for storing a display pattern, characterized by said frame buffer memory (2) having an addressable memory section (3) for storing data representing the cursor pattern, first data storing means (6) for successively storing lines of the cursor pattern data, second data storing means (7) for successively storing lines of display pattern data, logic means (14) for receiving and logically combining corresponding lines of cursor pattern data and display pattern data, and control means (9) for controlling the timing of the flow of data from said first data storing means (6) to said logic means (14). 2. An apparatus according to claim 1, characterized by said first data storing means (6) comprising a register (6) coupled to said addressable memory section (3) for receiving therefrom a string of data bits representing the cursor pattern for a line of said display (1). 3. An apparatus according to claim 1 or claim 2, characterized by said second data storing means (7) comprising a shift register (7) coupled between said frame buffer memory (2) and said logic means (14). 4. An apparatus according to any one of claims 1 to 3, characterized in that said frame buffer memory (2) is a dual port random access memory array, and said first data storing means (6) is operable during the horizontal blank time of said display (1). 5. An apparatus according to any one of claims 1 to 4, characterized in that said control means (9) is a counter arranged to determine the time at which said logic means (14) commences to receive data from said first data storing means (6).

Inventors: GARRETT BILLY WAYNE JR, GARRETT, BILLY, WAYNE, JR.
Applicants: NCR CO, NCR CORPORATION
Application year: 1988
Main classification: G09G1
IPC codes: G09G5