INTEGRATED CMOS CIRCUIT COMPRISING A SUBSTRATE BIAS VOLTAGE GENERATOR

Abstract: In CMOS integrated circuits, "latch-up" problems will soon arise if no special steps are taken. A means for counteracting a "latch-up" state consists inter alia in applying a substrate bias voltage. In an integrated circuit according to the invention, an externally clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2 V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially curing measuring and testing procedures, in which no external clock signal is supplied.

Description: The invention relates to a CMOS circuit integrated on a substrate, comprising a functional circuit for performing a function under control of an external clock signal received from an input terminal the CMOS circuit also comprising comparator means for comparing a substrate bias voltage with a reference voltage, the comparator means being coupled to switching means, for switching on/off an integrated oscillator, the integrated oscillator feeding first substrate bias voltage pumping means. An integrated CMOS circuit, in which a substrate bias voltage generator is included, is known from European Patent 0029681 published on January 28 th 1987. Another substrate voltage bias generator is known from the Japanese Kokai 59-193056. This circuit has a negative substrate bias voltage and comprises a comparator circuit, which switches the internal oscillator off when the substrate bias voltage becomes too high. In this way the bias voltage level is regulated. Substrate bias voltage generators are used in CMOS circuits in order to avoid that they pass into the so-called "latch-up" state. If no substrate bias voltage generators are used, this "latch-up" state is very liable to be attained. In a CMOS process with n wells used frequently, both n - and p - type transistors are implemented, as a result of which parasitic thyristors are also formed. If one or more of these thyristors are ignited at junction points in a circuit and at different areas in a substrate, said junction points of the circuit are held at a fixed voltage by these thyristors. This results in that the circuit operates no longer correctly and has passed into a "latch" state. When a substrate bias voltage is produced, it is ensured that it is much more difficult for the thyristors to ignite. In general, a substrate bias voltage generator consists of a capacitive pump controlled by a ring oscillator. The ring oscillator is also used for producing the clock frequency, which is utilized to control the further circuits in the integrated circuits. However, the "latch-up" sensitivity now depends upon the clock frequency because, if a higher clock frequency is used, the pump of the substrate bias voltage generator must also operate more rapidly in order to be able to compensate for the substrate currents increased by the higher clock frequency. Many integrated CMOS circuits, however, have an input terminal for supplying a clock signal having a frequency derived by the user of the circuit because the circuit must fit into a system deigned by the user or because the circuit can operate in different modes, in which event different clock frequencies are required for the different modes. An example thereof is a memory circuit serving to store teletext information in television applications. The clock frequency for the memory is then also determined by the 625 or 525 image line system used in television applications. An oscillator for controlling the charge pump of the substrate bias voltage generator is not integrated in such integrated circuits. The charge pump is then controlled by the clock pulses which are externally applied to the circuit. In European Patent Application N. 0022870, an integrated circuit is described which contains such a charge pump controlled by externally applied clock pulses for compensating leakage current in proportion to the clock frequency. In addition, it contains a charge pump which is controlled by a continuously running internal oscillator for compensating the residual junction leakage currents at very low clock frequencies. This arrangement, however, is not capable of adapting to surges in leakage current when the external clock is not supplied. When the integrated circuit is tested by the user, a clock frequency is not always supplied. If in this case tests are carried out, no substrate bias voltage is produced. as a result of which an increased "latch-up" sensitivity is obtained. Further, when the circuit is developed, nevertheless one or several parts of the circuit may unexpectedly pass into the "latch-up" state during measuring procedures on the first manufactured silicon wafers with the CMOS circuit, as a result of which substrate currents will flow, which cause the substrate bias voltage to decrease. This results in that even larger parts of the integrated circuit pass into the "latch-up" state, etc. Ultimately, no measurements can any longer be carried out on the integrated circuit. The invention has for its object to provide an integrated CMOS circuit, in which measures are taken, due to which, even in the absence of the clock frequency, when the circuit is tested by the user or when measurements are carried out on the circuit during the development of the product, a "latch-up" state cannot occur as yet. The integrated CMOS circuit according to the invention is therefore characterized in that the clock input is also coupled for controlling second substrate bias voltage pumping means during normal operation, the first integrated substrate bias voltage pumping means operating additionally to, and compensating a drop in the voltage produced by, the second substrate bias voltage pumping means, when the external clock signal is not supplied. An integrated COS circuit comprising such an oscillator and such a substrate bias voltage pump has the advantage that, if the substrate bias voltage is not more negative than a voltage to be adjusted, for example -2.2 V, this bias voltage generator is automatically switched on. As a result, additional substrate currents can be compensated during normal operation, but the substrate bias voltage generator may also operate for hundred per cent, if during testing by the user or during measurement of the integrated circuit no clock pulses are supplied during its development. The integrated circuit according to the invention will be described with reference to an example shown in a drawing, which shows a substrate bias voltage generator. In an integrated CMOS circuit according to the invention, an oscillator O is used, which can be switched on and off by switching means S , while further provision is made of a comparator circuit CO comparing the substrate bias voltage V BB produced with a reference voltage and a charge pump PU for producing the substrate bias voltage V BB , which pump PU is controlled by the output of the oscillator O . The oscillator O comprises a number of series-connected amplifier circuits 1 and 6 and 8 to 11, an amplifier that can be switched on and off by the switching means S being connected between the amplifier circuits 6 and 8. The switching means S with amplifier circuit used here constitute a NOR gate comprising two series -connected PMOS transistors and two parallel-connected NMOS transistors. The P-transistor P15 and the N-transistor N15 of the NOR gate become the amplifier circuit forming part of the ring oscillator O , which comprises the inverters 1 to 11. The transistors P16 and N14 of the NOR gate constitute the switching means S, by which the ring oscillator O is switched on or off. The output of the inverter 11 is connected to the input of a driver stage 12, which controls the substrate bias voltage pump PU. Substrate bias voltage pumps PU are known per se and need not be described further. The comparator circuit CO comprises a voltage divider connected between the supply voltage V DD and the substrate voltage V BB . The voltage divider comprises three transistors connected in series, whilst, starting from V DD , a PMOS transistor P13, whose gate electrode is connected to earth, an NMOS transistor, whose gate electrode is also connected to earth, and a second PMOS transistor, whose gate electrode is connected to the substrate bias voltage V BB , are successively connected in series. A junction point 15 between the drains of the PMOS transistor P13 and the NMOS transistor N12 is connected to an input of the inverter 13, whose output controls the switching means S or the transistors P15 and N14. The operation of the comparator circuit is as follows. The transistors P13 and P20 are always conducting and form with the NMOS transistor N12 a voltage divider if this transistor N12 is also conducting. The dimensions of these three transistors P13, N12 and P20 are chosen so that the input voltage of the inverter 13 is always sufficiently low at a sufficiently low substrate voltage to cause the output to be high. This results in that the transistor P15 is cut off and the transistor N14 of the switching means S is conducting. Therefore, the oscillator O is switched off. If now the substrate bias voltage V BB is no longer sufficiently negative, in other words becomes more positive, the NMOS transistor N12 will be cut off because its gate electrode is connected to earth. The voltage between the gate electrode and the main electrode at the junction point 14 between the NMOS transistor 12 and the PMOS transistor 20 is then no longer higher than the threshold voltage of the NMOS transistor N12. The NMOS transistor N12 will thus be cut off and the junction point 15 is charged via the conducting PMOS transistor P13. Therefore, if the voltage at the junction point 15 exceeds the threshold voltage of the inverter 13, the output of this inverter 13 will change over from high to low. Therefore, the PMOS transistor P15 of the switch S becomes conducting and the NMOS transistor N14 of the switch S is cut off. The oscillator O is thus switched on. Therefore, via the driver 12 and the charge pump PU, charge is pumped to the substrate so that the substrate threshold voltage V BB becomes more negative. The oscillator O continues to operate until a sufficiently negative substrate bias voltage V BB is produced. During the decrease of the substrate bias voltage, the voltage at the junction point 14 between the transistors N12 and P20 also further decreases so that the gate-source voltage of the transistor N12 will increase. If now a sufficiently negative substrate bias voltage V BB is reached, the transistor N12 will again become current conducting so that the junction point 15 is discharged. The input of the inverter 13 is discharged from a high potential to a low potential so that the output of the inverter 13 obtains a high output level and consequently switches off the oscillator O via the switching means S comprising the transistors P15 and N14. The known charge pump PU has a capacitance C connected between the inverter 12 and a junction point C1 and two NMOS transistor N10 and N11, which are connected between the junction point C1 and earth and the substrate, respectively. The two transistors N10 and N11 are used in known manner as diodes. The pump capacitance C of, for example, 10 pF is charged via the NMOS transistor N10 (the output of the inverter 12 is high) and is discharged via the transistor N11 to the substrate. During the discharge, however, the transistor N11 will behave like a bipolar transistor because the source of the transistor N11 becomes more negative than the substrate (at V BB ), which then acts as a base. However, the transistor N10 behaves in the same manner so that the transistor N10 is switched off as MOS field effect transistor, it is true, but is current-conducting as a bipolar element. If the transistors N10 and N11 are of the same size, half of the charge stored in the capacitance C will be drained by the transistor N10. The charge pump PU has an efficiency of only 50 %. If now the transistor N11 is made larger than the transistor N10 (for example width/length of N11 = five times width/length of the transistor N10), the efficiency can be improved( in the example up to 80 %).

Claims: A CMOS circuit integrated on a substrate, comprising a functional circuit for performing a function under control of an external clock signal received from an input terminal, the CMOS circuit also comprising comparator means (C0) for comparing a substrate bias voltage (VB) with a reference voltage, the comparator means (C0) being coupled to switching means (N14, P15), for switching on/off an integrated oscillator (0), the integrated oscillator (0) feeding first integrated substrate bias voltage pumping means ( PU ), characterized in that the clock input is also coupled for controlling second substrate bias voltage pumping means during normal operation, the first substrate bias voltage pumping means ( PU ) operating additionally to, so as to compensate a drop in the voltage produced by, the second substrate bias voltage pumping means, when the external clock signal is not supplied. An integrated CMOS circuit as claimed in Claim 1, characterized in that the integrated oscillator is a ring oscillator of a number of series-connected inverter stages, an inverter stage constituting together with the switching means a NOR gate. A CMOS circuit as claimed in Claim 1 or 2, characterized in that the comparator means (C0) comprise an inverter (13) and a series-combination of a first PMOS transistor (P13), an NMOS transistor (N12) and a second PMOS transistor (P20) connected as a diode included between the positive supply voltage (V DD ) and the substrate voltage (V BB ), the first PMOS (P13) and the NMOS transistor (N12) being connected by their gate electrodes to earth, a junction point (15) of their drains being connected to the input of the inverter (13) and the diode (P20) being connected between the NMOS transistor (N12) and the substrate. A CMOS circuit integrated on a substrate, according to Claim 1, characterized in that the first substrate bias voltage pumping means comprises a capacitance (C) between a first junction point (C1) and an output of the internal oscillator (0), includes a first NMOS transistor (N10) connected as a diode between the first junction point (C1) and earth and includes a second NMOS transistor (N11) connected as a diode between the first junction (C1) point and the substrate, wherein the width/length ratio of the second transistor (N12) is larger than the width/length ratio of the first transistor (N10). An integrated CMOS circuit as claimed in Claim 4, characterized in that the width/length ratio of the second transistor (N12) exceeds that of the first transistor (N10) by a factor 5.

Inventors: SLOB, ARIE, VAN DER SANDEN, CORNELIS GERARDUS LEONARDUS MARIA, VEENDRICK, HENDRICUS JOSEPHIUS MARIA
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1988
Main classification: G05F3
IPC codes: H03K3, H01L27, H01L21, H02M3, G05F3, G11C11