AN ELECTRONIC ADAPTER BOARD FOR VERY HIGH RESOLUTION GRAPHICS

Abstract: An electronic adapter board for very high resolution graphics, being of a type intended for installation in personal computers to enable operation of such computers as very high resolution graphic terminal units, comprises a graphic microprocessor (3) having inputs connected to the computer via an interface circuit (4), connected between a pair of data buses (5, 6) and an address bus (7), and a control bus (12), a group (32) of video dynamic memories (38) output connected to the microprocessor (3), a logic circuit (40) for binary-to-quinary logic transcoding connected between the microprocessor (3) and the group of video memories (38) to perform an address conversion to such memories (38) of the graphic coordinates of a picture being processed.

Description: AN ELECTRONIC ADAPTER BOARD FOR VERY HIGH RESOLUTION GRAPHICS FIELD OF THE INVENTION This invention relates to an electronic adapter board for very high resolution graphics, being of a type intended for installation in personal computers to enable such computers to function as very high resolution graphic terminal units and comprising a graphic microprocessor having inputs connected to the computer via a control bus and an interface circuit connected between a pair of data buses and an address bus, as well as a group of video dynamic memories output connected to the microprocessor. The invention is also concerned with a method of addressing the video memories of said electronic board. BACKGROUND ART Modern personal computers, such as of the type known by the trade name IBM XT/AT have gained widespread acceptance by all of the most advanced technology branches. Such computers usually come equipped with a display screen having a 16-color graphic resolution and a display pattern of 640 x 350 pixels, that is 640 video dots on the horizontal and 350 video dots on the vertical which are addressable individually within a group of video memories. However, a graphic resolution of this kind is inade q uate to meet growing demands from design, architectural, computer art, and the like offices, for which it would be desirable to - have the data processing capabilities of such computers combined with high performance when operating as large-capacity graphic stations. Known are electronic adapter boards intended for installation in conventional personal computers to convert them into high resolution graphic terminal units. To that end, such com p uters are further equipped with a high resolution display screen. Such prior electronic boards, while substantially achieving their objective, are still beset with a series of well-recognized drawbacks as pointed out herein below. A first drawback is that those boards require a large number of video memories which are tied to the size of the display pattern to be driven , in terms of horizontal and vertical pixels. In addition, they cannot drive two different monitors simultaneously, and accordingly, the user cannot command a full view of the diagram while working on a detail thereof. Another drawback is that any zooming effects to have a detaHl of the diagram or an area of the screen enlarged are only to be achieved at a slow pace because such boards include a software program directed to perform recalculation operations for the picture regions to be enlarged. A further drawback of graphic boards according to the prior art is that they cannot fully utilize the graphic capabilities of a high resolution display screen where a computer in which they are installed is used with management-type software programs. More specifically, where a computer equipped with a high resolution display is used to operate on the most prevalent of the management software programs currently available on the market, known graphic boards perform a so-called CGA/EGA emulation of a standard type video terminal. To do so, however, they only utilize a portion of the high resolution display screen. SUMMARY OF THE INVENTION The technical problem that underlies this invention is o provide an electronic adapter board for high resolution graphics, SUBSTITUT which has such structural and performance characteristics as to overcome the cited drawbacks with which prior graphic boards are beset. This problem is solved by a board as indicated being characterized in that it comprises a transcoding logic circuit for conversion from binary Logic.: to quinary logicrconnected between the graphic microprocessor and the group of video memories, said logic circuit being capable of performing a conversion of the addressing of the graphic coordinates of a picture being processed into said memories. The invention is also concerned with a method of addressing the video memories of an electronic adapter board intended for installation in a personal computer to be enabled as a very high resolution graphic terminal unit, characterized in that it comprises, at each memory addressing as effected through a graphic microprocessor incorporated to said board, a binary to quinary logic transcoding step carried ' out on said addressing. The features and advantages of an electronic adapter board according to the invention will become apparent from the following detailed description of an embodiment thereof, to be taken by way of illustration and not of limitation in conjunction with the accompanying drawings. DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a block diagram representing the electronic board erf thts " iπveττrϊo7f ϊr. s ' c ' fTematTc " form; and Figures 2 to 7 are respective sche atical detail views of the electronic board shown in Figure 1. DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to the drawing views, the numeral 1 generally and schematically designates an electronic adapter board for SUBSTITUT - 4 - very high resolution graphics. The board 1 is intended for installation in a personal computer, not shown because to conventional design, such as one of the type known in the trade as IBM XT/AT or another compatible type therewith. That computer will identified hereinafter as the host computer. The board 1 is incorporated to the host computer and electrically connected thereto by means of a quick-action, connector including a female member, not shown because conventional, on the computer and a cluster of reed contact terminals 14 on the board. The board 1 comprises an arithmetic/logic unit 2 consisting of a graphic microprocessor 3, shown in Figure 2, of a type avait-able commercially as TMS 34010 which operates on thirtytwo bits. That microprocessor 3 coordinates and synchronizes the functions of the electronic components which make up the board 1. and is connected to the host computer via an interface logic circuit 4. That interface circuit 4 comprises a pair of data transceivers, respectively indicated at A and B, being each interposed by its inputs and outputs between a series of eight data transmission lines or data buses 5 and 6. The microprocessor 3 has a group of sixteen data inputs, each connected.electrically to a respective line in said data buses, 5 and 6. The interface 4 further comprises a combinatoriaUnetwork C, specifically a programmable -.guarded. logi c circuit a -.ths type * commonly referred to as PLA (Programmable Logic Array), which is input connected to an address bus 7. The transceivers A and B are operatively linked to said combinatorial network C, and include additional inputs S and 9, SUBSTITUTE SHEET respectively connected to corresponding outputs 10 and 11 of said PLA C. The PLA C comprises further outputs control outputs HU and HL connected to the microprocessor 3, and an output CS connected, via a buffer F, to a control bus 12 which forms a further connection of the microprocessor 3 to the host computer. The data buses 5 and 6, address bus 8, and control bus 12 are all led to said contact reeds 14 for connection to the host computer. Advantageously, a cluster of parallel switches 13 are provided for releasably interconnecting homolog lines in the data buses 5 and 6 so as to make the board 1 compatible with host 'computers operating on eight b-fts. The board 1 also comprises anr ' internal 8ata " bus ~ 15, address bus 16, and control bus 17 for connection to and communication between the microprocessor 3 and the other electronic components of the board 1. In particular, the microprocessor 3 comprises sixteen outputs connected to the address bus 16, which is connected to the inputs of a second programmable logic circuit P of the PLA type which is output connected to a storage cell Q in feedback relationship. That circuit P has further inputs connected to outputs of the microprocessor 3 by the control bus 17, and is provided with a pair of outputs LD 8 and LD 9 connected to the address inputs of local dunamic memories of the RAM type. Thus, the addressing of such memories 18 is linked operatively to said logic circuit P, whilst for data loading, they are connected to the internal data bus 15. Such memories 18 are, in turn, conventionally connected SUBSTITUTE SHEET to the control bus 17 as well as to a bus 25 connected to the output of a control circuit 30 in a transcoder 40 to be described. The board 1 also comprises program memories 19 of the EROM type whose outputs are connected to the data bus 15, which memories are operative to store up software programs to be loaded into the local RAM's 18 on energizing the board to effect the CGA/EGA emulation to be described. For completeness sake, it should be noted that at the output of the microprocessor 3, the address bus 16 includes a branch-off 16a connected to the input of a divider 20 of the data bus 15. In particular, that divider 20 is composed of a pair of multiplexers G and H, each comprising a cluster of eight outputs for data rebu ld and connected back to a corresponding cluster of eight connection lines which form the sixteen-line main internal data bus 15. In addition, the branch-off 16a is also connected to the inputs of a logic decoder and control circuit 30 consisting, in particular, of a pair of a pair of decoders I and L, the former, I, of which has outputs connected to a bus LA, whilst the Latter, L, has outputs connected directly to the respective inputs of a pair of programmable logic circuits N and GG of the PLA type effective to supply control signals, over the bus 25 to groups 46 of high-speed memories in a look-up table 45 handling the display colors. Advantageously in accordance with the invention, and with particular reference to the embodiment shown in Figure 3, the board 1 is provided with a binary-to-quinary logic transcoding circuit 40. More in detail, there are provided first AB and second AC SUBSTITUTE SHEET read-only logic memories of the high-speed PROM type, being both input connected to the bus LA. Also provided is a decoder AA having inputs connected to both the bus LA and the address bus 16. The outputs of the decoder AA and the PROM AB are connected to a set or group of video memories 32 of the dynamic RAM type via respective buses Va and Vb. The buses Va and Vb, being each eight-bit buses, jointly constitute the sixteen-line bus V connected to those memory set 32. The logic transcoding circuit 40 includes, moreover, a programmable logic circuit AD of the PLA type having inputs directly connected to the outputs of the second PROM memory AC. That PLA AD has a cluster of five outputs, respectively denoted by t ' e references Vc1 and Vc5, which are connected, in turn, to the set 32 of video memories 38. More particularly, those outputs are operative to issue control signals for each subgroup 35 of the video RAM's 38 to effect a change of addressing based on the timing of the display'columns. With specific reference to the embodiment of Figure 4, there are shown schematically a group of eight memories 38 from the set 32 of video memories. Advantageously, the board 1 of this invention comprises a set 32 of forty video memories 38 only. That group or set 32 is divided into five subgroups 35 each made up of eight memories 38. With particular reference to Figure 4, there are shown a subgroup 35 of eight video memories of the RAM type, each input connected to the bus V from the logic transcoding circuit 40. Each memory group 35 is, in turn, split into two subgroups 35a and 35b, each composed of four storage cells. A pair of SUBS U-f-k -rø - respective buses SA and SB connects the outputs of each memory 38 in each respective subgroup, 35a and 35b. Further, to an input of the first memory 38 in each subgroup, 35a or 35b, there is connected an output VC of the PLA AD of the circuit 40. Accordingly, the board 1 will include five groups 35 in all of RAM video memories of the kind shown in Figure 4, with each group connected at their output to a bus pair, e.g. of the kind of SA and SB. Each pair of homologous buses are parallel connected to the inputs of corresponding programmable logic circuits LL of the PLA type effective to perform a pre-multiplation of each pixel pair output by each group 35 of video memories 38. Each circuit LL comprises a pair of PLA's, such as LLa and LLb i-n Figure 5, each input connected to the corresponding bus SA. Each group 42 of PLA's LL is input connected to a look-up table managing the display colors. That look-up table consists of a group 45 of ten high-speed dynamic memories of the RAM type, as denoted, for example, by the references HA and HB in Figure 5. These memories are arranged in five pairs 46, each pair having inputs connected directly to respective outputs of each group 42 of PLA's LL, via corresponding buses QA, QB, QC, QD, and QE. Advantageously, each pair 46 of said RAM's are output connected to a corresponding bus, in Figure 5 there being shown buses XA, XB, XC, XD, and XE each composed of thirteen link lines such that one, 54, of such lines can be connected to a second monitor 65 to drive a monochrome display screen. The look-up table 45 further comprises storage units 52 connected in said color buses, denoted by the references XA to XE, which are connected, at the look-up table output, to a corresponding series of flip-flop storage cells MA operative to perform a re-timing. At the output of such cells MA, there are a series of additional corresponding buses, denoted by the references YA, YB, YC, YD, and YE, which are connected'in "parallel with said buses XA to XE to corresponding inputs of a shift register 50 formed of logic circuits of the TTL type. That shift register 50 incorporates, as the final stage of the tristates, not shown because conventional, operative to effect the multiplexing final step. • W-ith particular reference to Figure 6, a circuit 60 will be described which is used for timing the board 1. That circuit 60 is connected to an internal synchronizer 62 and adapted to come into operation during the steps of enlargement of some detail of the display picture according to the user's own requirements. That circuit 60 comprises a programmable divider SC1 and a demultiplexer SD1. The last-named component, SD1, has a pair of inputs, ZC1 and ZC0, for receiving control pulses. That demultiplexer SD1 is output connected, via a storage cell SB1, to a synchronization input 58 of the shift register 50. Advantageously, and with particular reference to the embodiment of Figure 7, the board 1 incorporates a gate 70 and CGA/EGA emulation logic 71. Said gate 70 and logic 71 consist essentially of a pair of programmable logic circuits TA and TB of the PLA type, connected to each other and input connected to the data bus 5 SUBSTITUTESHEET and the address bus 7. The second PLA, TB, is also connected to the control bus 12. That second PLA has an output RY connected to the control bus 12 and operative to supply an interrupt signal to the microprocessor of the host computer. That second PLA has further outputs LTA and LTB directly connected to the microprocessor 3 to transmit, in turn, interrupt signals effective to signify the arrival of data to be processed. Also provided is an additional output RD, in turn connected to the host computer and operative to supply the latter with a start signal after the microprocessor 3 has gained control of said data to be processed. - -The operation of the electronic board 1 will be now described with particular reference to the method of addressing the video memories 38. The microprocessor 3 coordinates and synchronizes the functions of the various electronic components of the board 1. More specifically, the picroprocessor 3 receives on its input data from the host computer to be processed through the data buses 5 and 6. The PLA C of the interface 4 decodes data of the address bus 7 from the host computer and enables, through its outputs 10 and 12, the transceivers A and B to read and/or write the data buses 5 and 6 to and from the m croprocessor 3. The PLA C also generates, on the outputs HU and HI, respective control signals to the microprocessor 3, and on the output CS, a further control signal effective to signify the host computer, via the control bus 12, of that the data communication has been enabled in either the sixteen- or eight-bit SUBSTITUTE SHEET mode . The graphic microprocessor 3 communicates instead with the several components of the board 1 through the internal data and address buses 15 and 16, respectively, and the control bus 17. In particular, for managing the local RAM memories 18 refreshing in the board 1, the microprocessor will activate the programmable logic circuit PLA P through the address bus 16 and control bus 17, which outputs, with the assistance of the storage cell , the addressing control signals to said local memories 18. The microprocessor 3 will read/write the group 32 of forty video memories 38 via the data bus 15. Through said video memories 38, the board 1 of this invention can drive a video array or map of 1280 pixels on the horizontal and 1024 pixels on the vertical. It will be recalled that each pixel forms the basic element of a display picture, that is the smallest dot to be individually identifiable and addressable by the microprocessor 3 by means of a memory word or byte consisting of eight bits. Since the number 1280 is not a power of two, in order to address 1280 pixels, the microprocessor is to operate on no less than 2048 addresses, the latter number being the first power of two above 1280. Accordingly, it would require as many as forty eight video memory units instead of the forty memories provided by the board 1. Thus, the first step of the inventive method consists of a transcoding operation from binary Logic into quinary logic by means of the logic circuit 40. For the purpose, the PROM's SUBSTITUTESHEET 88/01092 - 12 - " AD and AC are activated to convert the binary coordinates of the display pixel into quinary coordinates, i. e. coordinates based on multiples of five; in addition, the PLA AD will generate on its five outputs enable signals to enable loading of data directed to five respective groups 35 of eight memories 38 each within said group 32. In other words, the address bus LA is replaced by the address bus V, which allows of re-addressing the video memories in five subgroups. This solution also achieves an advantageous parallelism with five parallel output routes for the signal also permitting of subsequent processing of five pixel pairs at a time via the buses SA, SB, etc. from each subgroup 35 of eight video memories 38. The look-up table 45 manages the colors of the high-resolution display screen and an additional monochrome monitor. For the purpose, the additional connection line of each thirteen-line color bus, XA, XB, XC, XD, XE, is used. This thirteenth line 54 is connected to drive the second, monochrome monitor 65 with a single monochrome bit for each screen pixel. The remaining twelve bits of each color bus are directed to coding with four bits per color the pixels of the high resolution display screen, while retaining high chromatic capabilities for that screen. The Logic information of the color buses from the look-up table, following re-timing by the flip-flop memories MA, is processed by the shift register 50 applying a multiplexing step. Advantageously, the working frequency of the logic circuits TTL which form the register 50 is half the pixel display frequency. $ π UBc3sTITUTE SHEET - 13 - The operation of the board 1 during the step of enlarging details of the display picture, or so-called zoom effect, will be now described. According to the signals received on the inputs 2C1 and ZCO, the demultiplexer SD1 of the timing circuit 60 may output a frequency approximately equal to one half that used during normal operation. This new frequency is applied, via the memory SB1, to the synchronization input 58 of the shift register 50, which will halve the frequency of its own operating cycle. Thus, the displaying of each pixel can be extended over a time period twice as long to result in a lenghtening effect of the picture. In this way, the important advantage is secured of achieving the zoom effect by a simple change of the displaying frequency of the video picture. As for the CGA/EGA emulation step, the emulation gate 70 will signify to the graphic microprocessor the occurrence of a data passage judged for handling by the board 1. That gate 70 is connected in substantially bypass fashion in the input buses 5 and 7 and generates interrupt signals to the microprocessor 3, via the outputs LTA and LTB, on the passage of data to be handled as identified by means of a suitable resident program in EPR0M. The PLA TB of the gate 70 will also generate an interrupt signal on the output RY for the host computer, thereby to synchronize the different rates of operation of the microprocessor 3 and the host computer. Once the data have been acquired, the microprocessor 3 will re-activate the normal data ' management process by the host SUBSTITUTESHEET computer via the output RD. Thus, the invention solves the technical problem and affords a number of advantages. A first major advantage is that this electronic adapter board uses a much " reduced number of video memories, while still enabling video maps of 1280 x 1024 pixels in 256 colors to be displayed. Another major advantage is that the board of this invention allows of a second, monochrome monitor to be driven in parallel with the high resolution monitor, thus affording for the user the faculty to work on a detail while commanding a general view of the whole diagram. Further advantages are that the zoom effect for enlarging details of a displayed diagram is achieved by a hardware route at a high speed; in addition, this board enables operation with the most widely used management software packs and in CGA/EGA emulation, while utilizing the capacity of the high resolution display screen. SUBSTITUTE SHEE

Claims: CLAIMS 1. An electronic adapter board (1) for very high resolution graphics, being of a type intended for installation in personal computers to enable such computers to function as very high resolution graphic terminal units and comprising a graphic microprocessor (3) having inputs connected to the computer via a control bus (12) and an interface circuit (4) connected between a pair of data buses (5,6) and an address bus (7), as well as a group (32) of video dynamic memories (38) output connected to said microprocessor- .(3), -characterized in that it comprises a transcoding logic circuit (40) for conversion from binary Logic to quinary Logic connected between the graphic microprocessor (3) and and said group (32) of video memories, said logic circuit (40) being capable of performing a conversion of the addressing of the graphic coordinates of a picture being processed into said memories (38). 2. A board according to Claim 1, characterized in that said logic circuit (40) comprises first (AB) and second (AC) programmable read-only memories of the ROM type, a decoder (AA) associated with said first memory (AB), a programmable logic circuit (AD) of the PLA type output connected to said second memory (AC), said first and second memories and said decoder (AA) having respective inputs connected to a corresponding address bus (LA) connected to the microprocessor (3), said decoder (AA) and said first memory (AB) having outputs connected via a bus (V) to said video memories (38), and said programmable Logic circuit (AD) having, in turn, outputs, each connected to a subgroup (35) in said group (32) of video memories. 3. A board according to Claim 1, characterized in that SUBSTITUTE said interface circuit (4) comprises a pair of transceivers ( A,B), each intervening on a corresponding data bus (5,6), and a programmable logic circuit (C) of the PLA type having inputs connected to said address bus (7), said transceivers being operatively Linked to said programmable logic circuit. 4. A board according to Claims 1 and 3, characterized in that it comprises a cluster of switches effective to releasably interconnect homologous Lines in said data buses (5,6) between said interface circuit (4) and the microprocessor (3) to make that board compatible with computers operating either in the sixteen- or eight-bit mode. 5. A board according to Claim 1, characterized in that it further comprises a second programmable Logic circuit (P) of the PLA type having inputs connected to outputs of the microprocessor via an ' address bus (16) and a control bus (17) internal of said board, as well as Local dynamic memories (18) having address inputs operatively linked to outputs (LD8,LD9) of said logic circuit (P) . 6. A board according to Claim 1, characterized in that it comprises a group (45) of high-speed dynamic memories (48) cascade connected to said group (32) of video memories (38) and operative to manage the colors of the display screen, said dynamic memories (48) being output connected to a color bus provided with an additional line (54) for connection to a second monitor. 7. A board according to Claim 6, characterized in that said color bus comprises thirteen connection lines one ( 54 ) of which is connected to said monochrome monitor (65). 8. A board according to Claim 6, characterized in that SUBSTITUTE SHEET each color bus is parallel connected, via a respective re-timing storage cell, to a corresponding input of a shift register (50). 9. A board according to Claim 1, characterized in that said group (32) includes forty of said video memories (38). 10. An electronic adapter board (1) for very high resolution graphics, being of a type intended for installation in personal computers to enable such computers to function as very high resolution graphic terminal units and comprising a graphic microprocessor (3) having inputs connected to the computer via a control bus (12) and an interface circuit (4) connected between a pair of data buses (5,6) and an address bus (7), as well as a group (32) of video dynamic memories (38) output connected to said microprocessor *.(2 , character zed in that it comprises an internal timing circuit composed of a programmable divider (SC1) and a multiplexer (SD1) which is output connected to said shift register (50) and acts thereon to lower the operating cycle frequency. 11. An electronic adapter board (1) for very high resolution graphics, being of a type intended for installation in personal computers to enable such computers to function as very high resolution graphic terminal units and comprising a graphic microprocessor (3) having inputs connected to the computer via a control bus (12) and an interface circuit (4) connected between a pair of data buses (5,6) and an address bus (7), as well as a group (32) of video dynamic memories (38) output connected to said microprocessor (3), characterized in that it comprises a CGA/EGA emulation gate (70) composed of first (TA) and second (TB) programmable logic circuits of the PLA type connected to each other and input connected to said data SUBSTITUTE SHEET (5) and address (7) buses, said second PLA (TB) being also input and output connected to the control bus (12) to supply processing interrupt signals both to the microprocessor (3) and said computer. 12. A method of addressing the video memories (38) of an electronic adapter board (1) intended for installation in a personal computer to be enabled as a very high resolution graphic terminal unit, characterized in that it comprises, at each addressing of said memories as effected through a graphic microprocessor (3) residing in said board (1), a binary to quinary logic transcoding step carried out on said addressing.

Inventors: NICCOLINI MARCELLO, NICCOLINI, MARCELLO
Applicants: INFOTRONIC SPA, INFOTRONIC S.P.A.
Application year: 1988
Main classification: G09G1
IPC codes: G06F3, G09G5