MAGNETIC HEAD DRIVE CIRCUIT

Abstract: A magnetic head drive circuit for driving a coil (L) of the magnetic head performing opto-magnetic recording, is disclosed. Switching elements (2, 4, 5; 8, 9, 10) are actuated on the basis of driving signals for commutatingly connecting three power sources (3, ground, 6) presenting three different potentials to both ends of the coil (L) of the magnetic head such that the potential difference across the ends of the coil at the time of magnetic field inversion is larger than that at the time of generation of a stationary magnetic field to render the rise time of the current flowing in the coil sufficiently short.

Description: This invention relates to a magnetic head drive circuit for driving a magnetic head for effecting opto-magnetic recording. A magnetic field modulation method of recording information on an opto-magnetic disk, has been proposed which makes rewriting possible, as shown for example in fig 1 of the accompanying drawings. With this method, a perpendicular magnetisation film 101a of an opto-magnetic disk 101 is irradiated with a constant laser beam emanating from an optical pickup 102 to elevate the temperature of the perpendicular magnetisation film 101a to higher than the curie temperature. A magnetic field induced by a magnetic head 103 is modulated by recording signals so that magnetic patterns associated with the patterns of changes of said magnetic field are left on the perpendicular magnetisation film 101a for recording the information. When recording by the magnetic field modulation system, using the rectangular recording signals as shown at A in fig 2, the current flowing in a coil 103a of the magnetic head 103 has an integrated waveform having a certain time constant, as shown at B in fig 2. The magnetic field produced by the magnetic head 103 has an integrated waveform approximately the same as that of the current waveform, as shown at C in fig 2. In fig 2 Id and Hd denote the driving current and the intensity of the associated magnetic field, respectively. In general, when recording using the magnetic field modulation system, it is necessary for the magnetic field produced by the magnetic head to be of the intensity required for recording and for the rise time of the magnetic head and hence that of the current to be sufficiently short. As an example, it is assumed that the drive circuit as shown in fig 3 is employed, wherein the intensity of the magnetic field Hd is 200 µ e, the rise time t is 0.1 µ s, the drive current Id is 1A, and the inductance of the coil 104 of the magnetic head is 5 µ H. With the inductance L of the coil 104 of the magnetic head and the resistance R of the resistor 105, the rise time t is given by the formula t=L/R, it being assumed that the rise time t is equal to the time constant. By substituting the aforementioned condition t=0.1 µ s and L=5 µ H in the above formula, the resistance R is found to be equal to 50 ohms. Hence, the drive voltage Vd supplied by the voltage source 106 is Vd = 1(A) x 50 (ohms) = 50V so that the power consumption amounts to a large value of 50W. Therefore, if the rise time is reduced sufficiently, the power consumption is inconveniently increased. Thus, with a view to providing a magnetic drive head circuit having a sufficiently short rise time of the current flowing in the magnetic head coil, and a lower power consumption, there has been proposed in JP-A-63-94405 assigned to the present Applicant a magnetic head driving circuit comprising a dc source adapted to supply current to a coil of a magnetic head performing an opto-magnetic recording, at least two switching elements turned on and off by recording signals, and an auxiliary coil positioned between the dc source and the coil of the magnetic head and having an inductance sufficiently larger than the inductance of the magnetic head coil, wherein the switching elements are alternately turned on and off for switching the sense of the current flowing in the magnetic head coil. An illustrative embodiment of this previously proposed magnetic head drive circuit is explained by referring to figure 4. In this fig, the one end, point a , of a head coil 91 is connected via auxiliary coil 92 to a power source 93, while being grounded via switching element 94. The other end of the head coil 91, point b , is connected via auxiliary coil 95 to the power source 93, while being grounded via switching element 96. Each of the auxiliary coils 92 and 95 has an inductance sufficiently larger than that of the head coil 91. A signal input terminal 97 is connected to the switching element 96 and, via inverter 98, to the switching element 94. The opening and closure of these switching elements 94 and 96 are controlled by recording signals Sig supplied to the signal input terminal 97, such that, when one of the switching elements causes the one end of the head coil 51 to be grounded, the other switching element isolates the other end of the head coil 91 from ground. In the above described magnetic head driving circuit, when the digital recording signal Sig composed of a high level (H) component and a low level (L) component as shown at A in fig 5 is supplied to the signal input terminal 97, the switching element 94 is controlled by a control signal which is a replica of the recording signal Sig inverted by the inverter 98, as shown at B in fig 5, such that when the control signal is at a high (H) level, the one end of the head coil 91 is grounded. The switching element 96 is also controlled by a control signal shown at C in fig 5 and which is a replica of the recording signal Sig, such that when the control signal is at a high (H) level, the other end of the head coil 91 is grounded. By the operation of the switching elements 94 and 96 which is brought about by the recording signal Sig, the current supplied from the source 93 flows from the one end, point a , to the other end, point b , of the head coil 91 or vice versa to ground. It is to be noted that, at the moment of switching of the switching elements 94 and 96, or of inversion of the magnetic field of the head coil 91, there is induced in the auxiliary coil 92 a high voltage Va shown at D in fig 5 at the one end, point a , of the head coil 51 or a high voltage Vb shown at E in fig 5 at the other end, point b , of the head coil 91. Hence, the current Iab shown at F in fig 5 flows in the head coil 91. However, in the above described head drive circuit, the current flowing in the head coil 91 at the time of the generation of the stationary magnetic field is caused to fluctuate considerably as shown at F, f in fig 5, resulting in worsening of the recording characteristics. It is therefore necessary to render the current during the generation of the stationary magnetic field constant by the use of a waveform shaping circuit. For example, as shown by broken lines in fig 4, a waveform shaping circuit consisting of a series connection of a resistor 99 and a capacitor 100 is connected in parallel with the head coil 91 and a current is caused to flow through the resistor 99 and the capacitor 100 as shown at G in fig 4, so that a current Iab′ shown at fig 4 having good recording characteristics is produced at the head coil 91. However, with the use of the above described waveform shaping circuit, the resistor 99 consumes a large amount of electrical power so that power consumption is increased with the resulting head evolution and hence the provision of special heat radiation means is necessitated to dissipate the evolved heat. It is therefore a principal object of the present invention to provide a magnetic head drive circuit whereby opto-magnetic recording with good recording characteristics may be accomplished without the necessity of connecting a waveform shaping circuit component, including a resistor, in parallel with the head coil. According to the present invention, there is provided a magnetic head drive circuit comprising first and second power sources presenting respective different potentials for supplying current to a coil of a magnetic head adapted for carrying out opto-magnetic recording, first commutating means adapted for connecting each of said power sources to one end of said coil, and second commutating means adapted for connecting each of said power sources to the other end of said coil, the arrangement being such that each of said commutating means is actuatable on the basis of a recording signal such that said power sources presenting the respective different potentials are connected in a commutating fashion to the ends of said coil so that a potential difference is applied across said coil during the period of magnetic field inversion which is larger than the potential difference across the coil during the following period of generation of stationary magnetic field; characterised by including first and second switching means each operable to connect the coil to a third power source and actuatable on the basis of said recording signal to supply current from said third power source to said coil between periods of inversion by actuation of said first and second commutating means to maintain the current flowing through the coil between said periods substantially at a constant level. As will become apparent from the following description the present invention can provide a magnetic head driving circuit wherein the potential difference between both ends of the head coil at the time of inversion of the magnetic field becomes larger than the same potential difference at the time of generation of a stationary magnetic field and which has a reduced power consumption. The present invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:- Fig 1 is a diagrammatic view for understanding the magnetic field modulation system for performing opto-magnetic recording. Fig 2 is a time chart for understanding the magnetic field modulation system shown in fig 1. Fig 3 is a circuit diagram showing the prior art example of the magnetic head drive circuit. Fig 4 is a circuit diagram showing the construction of the magnetic head drive circuit according to the assignee's co-pending patent application. Fig 5 is a time chart for understanding the operation of the magnetic head drive circuit. Fig 6 is a circuit diagram showing the construction of a magnetic head driving circuit according to a first embodiment of the present invention. Fig 7 is a time chart for understanding the operation of the first embodiment of the magnetic head driving circuit. Fig 8 is a circuit diagram showing the construction of a control signal generating circuit employed in the first embodiment of the magnetic head driving circuit. Fig 10 is a circuit diagram showing the construction of a magnetic head driving circuit according to a second embodiment of the present invention. Fig 11 is a time chart for understanding the operation of the second embodiment of the magnetic head driving circuit. Fig 12 is a circuit diagram showing a magnetic head riving circuit according to a third embodiment of the present invention. Fig 13 is a time chart for understanding the operation of the third embodiment of the magnetic head driving circuit. By referring to the drawings, preferred illustrative embodiments of the present invention will be explained in detail hereinbelow. Fig 6 shows a magnetic head driving circuit according to a first embodiment of the present invention. Referring to this fig, a head coil 1 is a coil of a magnetic head adapted to perform opto-magnetic recording by the magnetic field modulation system, and has an inductance L. The one end, point a , of the head coil 1 is connected via switching element 2 to the positive dc source 3, while being connected to the ground via switching element 4. The one end, point a , of the head coil 1 is connected via switching element 5 directly and via diode 7 to a negative dc source 6. The other end, point b , of the head coil 1 is connected via switching element 8 to the positive dc source 3, while being grounded via switching element 9. This other end, point b , of the head coil 1 is connected via switching element 10 directly and via diode 11 to the negative dc source 6. Each of the switching elements 2, 4, 5, 8, 9 and 10 has its control input end connected to a control signal generating circuit 20. To this circuit 20 are connected a signal input terminal 21 and a clock pulse input terminal 22. It will be noted that the potential difference between the positive dc source 3 and the negative dc source 6 is very large; for example, the potential (+V) of the dc source 3 is about +5 to 10V, whereas the potential (-V) of the dc source 6 is about -50 to -100V. In the present embodiment, ground potential is used as the 0(V) potential source. The operation of the magnetic head drive circuit of the first embodiment is explained by referring to the time chart shown in fig 7. The control signal generating circuit 20 generates control signals Sig 1 to Sig 6 for the switching elements 2, 8, 5, 10, 4 and 9 shown at C to H in fig 2, from a digital recording signal Sig 0 shown at A in fig 7, supplied to a signal input terminal 21, which signal rises at the timing t₅ and falls at the timing t₁, and a clock pulse CK shown at B in fig 7, supplied to a clock pulse input terminal 22, by a signal processing as later described. The control signal Sig 1 for the switching element 2 is a signal which is a replica of the recording signal Sig 0, while the control signal Sig 2 for the switching element 8 is a signal having the opposite polarity to the recording signal Sig 0. The control signal Sig 3 for the switching element 5 is a pulse signal which goes high (H) for one pulse interval for each falling of the recording signal Sig 0. The control signal Sig 4 for the switching element 10 is a pulse signal which goes high (H) for one pulse interval for each rising of the recording signal Sig 0. The control signal Sig 5 for the switching element 4 is a pulse signal having a number of pulses corresponding to the low (L) level width of the recording signal Sig 0, while the control signal Sig 6 for the control element 9 is a pulse signal having a number of pulses corresponding to the high (H) level width of the recording signal Sig 0. The switching elements 2, 8, 5, 10, 54 and 9 are turned on each time the control signal Sig 1 to Sig 6 goes high (H) to complete the circuit. Directly before the falling of the recording signal Sig 0, that is, directly before the timing t₁ in fig 7, the switching element 2, to which the control signal Sig 1 is supplied, is turned on, with the remaining switching elements 8, 5, 10, 4 and 9 being turned off. At this time, the potential Va at the one end, point a , of the head coil 1 is +V, as shown at I in fig 7, by the positive dc source 3 to which the point a is connected via switching element 2. The potential Vb at the other end or point b of the head coil 1 is in the course of rising to +V, as shown at J in fig 7, since the charges at the point a will flow thereto via head coil 1. As the switching element 2, to which the control signal Sig 1 is supplied, is turned off and the switching element 8, to which the control signal Sig 2 is supplied, is turned off, with the falling of the recording signal Sig 0, that is, at the timing t₁ shown in fig 7, the potential Vb at the point b becomes +V by virtue of the connection via switching element 8 to the positive dc source 3. Since the switching element 2 is turned off and hence a current is no longer supplied by the positive dc source 3 to the point a , while a current flows from the point a to the points b as a result of the flyback of the inductance L of the head coil 1, the potential Va at the point a is decreased acutely. Since this potential difference is caused by the inductance L, the current Iab of the head coil 1 is not changed as shown at K in fig 7. When the lowering of the potential Va at the point a reaches -V, the diode 7 is turned on and the potential of the point a is stabilised at -V by the negative dc source 6. Also the potential a is fixed at -V by the negative dc source 6, since the switching element 5, to which the control signal Sig 3 is supplied, is turned on at the timing t₂. At the rise time of the recording signal Sig 0, that is, at the time of inversion of the magnetic field of the magnetic head at the timing t₅ shown in fig 7, the switching element 8 supplied with the control signal Sig 2 performs the same operation as that of the switching element 2, the switching element 10 supplied with the control signal Sig 4 performs the same operation as that of the switching element 5 and the diode 11 performs the same operation as that of the diode 7. Hence, the operation of the magnetic head during magnetic head inversion with the rising of the recording signal Sig 0, that is, at the timing t₅ in fig 7, is similar to that of the magnetic head during magnetic filed inversion with the falling of the recording signal Sig 0, that is, at the timing t₁ shown in fig 7. That is to say, during the inversion of the magnetic field of the magnetic head, a large potential is produced across the both ends of the head coil 1 due to the potential +V supplied by the positive dc source 3 and the potential -V supplied by the negative dc source 6, son that the sense of the current Iab flowing in the head coil 1 can be changed with a sufficiently short rise time. The operation of the magnetic field during the generation of the stationary magnetic field, with the recording signal Sig 0 at the low (L) level, will now be explained. When the switching element 5, to which the control signal Sig 3 is supplied, is turned off at the timing t₃, electrical charges are moved from the point b to the point a by the flyback of the inductance L of the head coil 1, so that the potential Va at the point a promptly approaches +V. From this time on, the current Iab flowing in the head coil 1 is gradually decreased. When the switching element 4 supplied with the control signal Sig 5 is turned on at the timing t₄, the point a is grounded and, the current Iab is again increased at a gradient associated with the potential difference across both ends of the head coil 1. By optimising the operational timing of the switching element 4, the current Iab flowing in the head coil 1 can be maintained at a substantially constant level. Since the switching element 10 to which the control signal Sig 4 is supplied performs the same operation as that of the switching element 5, and the switching element 9 to which the control signal Sig 6 is supplied performs the same operation as that of the switching element 4, the operation of the magnetic head during the time of generation of the stationary magnetic field with the recording signal Sig 0 at the high (H) level is similar to that of the magnetic head during the time of generation of the stationary magnetic head with the recording signal Sig 0 at the low (L) level. That is, during the time of generation of the stationary magnetic field of the magnetic head, the head coil 1, the one end of which, that is, point a or point b , is supplied with the potential +V from the aforementioned dc source 3, has its other end, that is, point b or point a , periodically rounded, so that a potential difference is produced across both ends of the head coil 1 thereby producing the approximately constant current Iab in the head coil 1. Hence the magnetic head drive circuit is designed to produce a larger potential difference across both ends of the head coil 1 during inversion of the magnetic field of the magnetic head, which is due to the potential +V supplied by the positive dc source 3 and the potential -V supplied by the negative dc source 6, and the potential difference across both ends of the head coil 1 during generation of the stationary magnetic field of the magnetic head, which is due to the potential +V supplied by the positive dc source 3 and the potential due to the ground potential, with the result that the rise time of the current flowing in the head coil 1 may be sufficiently shortened and the power consumption reduced without the necessity of connecting a waveform shaping circuit component, such as a resistor, in parallel with the head coil 1. It will be noted that FET's or transistors may be used as the switching elements and the diodes 7 and 11 can be omitted, their functions being provided by parasitic diode action especially when the FET's are employed as the switching elements 5 or 10. Fig 8 shows the control signal generating circuit 20. In this figure, a digital recording signal Sig 0 shown at A in fig 9 is supplied via signal input terminal 21 to the control signal generating circuit. This signal Sig 0 falls at the timing t₁ and rises at the timing t₅, similarly to the recording signal Sig 0 shown in fig 7. A clock pulse CK as shown at B in fig 7 is also supplied via clock pulse input terminal 22 at the circuit 20. The recording signal Sig 0 is outputted from the control signal generating circuit 20 as the aforementioned control signal Sig 1, while being simultaneously supplied to inverters 23, 24 and to a falling edge detection circuit 25. The clock pulse CK is supplied to falling edge detection circuit 25 and a rising edge detection circuit 30 and to a first delay circuit 34. The falling edge detection circuit 25 is composed of an inverter 26, an AND gate 27 and a D-type flip-flop 28. The flip-flop 28 forms an output signal shown at C in fig 9, from the aforementioned recording signal Sig 0 and clock pulse CK, to supply the output signal to an input end of the AND gate 27. This AND gate 27 in turn forms, from the output signal of the flip-flop 28 and a negation signal of the aforementioned recording signal Sig 0, shown at D in fig 9, supplied from the inverter 26, a falling detection signal, shown at E in fig 9, rising at the falling timing t₁ of the recording signal Sig 0. The negation signal of the aforementioned recording signal Sig 0, shown at D in fig 9, outputted from the inverter 24, is outputted as the control signal Sig 2 from the control signal generating circuit 20, while being simultaneously supplied to the inverter 29 and to the falling edge detection circuit 30. Similarly to the falling edge detection circuit 25, the rising detection circuit 30 is composed of an inverter 31, an AND gate 32 and a D-type flip-flop 33. The flip-flop 33 forms an output signal, shown at F in fig 9, from the aforementioned negation output of the recording signal Sig 0 and clock pulse CK, to supply an output signal to an input of the AND gate 32. The AND gate 32 in turn forms and outputs a rising detection signal shown at G in fig 9 from the output signal of the flip-flop 33 and the aforementioned recording signal Sig 0, shown at A in fig 9, supplied from the inverter 31, which rising detection signal rises at the timing t₅ of the falling edge of the negation signal of the recording signal Sig 0, that is, at the rising edge of the recording signal Sig 0. The first delay circuit 34 causes the clock pulse CK to be delayed to form the signal shown at H in fig 9 to supply the signal to a second delay circuit 35 and to an AND gate 36. The second delay circuit 35 causes a signal supplied from the first delay circuit 35 to be delayed to supply a signal shown at I in fig 9 to the aforementioned AND gate 36. This AND gate 36 outputs a logical output of the aforementioned delayed clock pulses, which logical output, shown at J in fig 9, represents a reference pulse governing the periods of the aforementioned control signals Sig 3 to Sig 6. The output of the inverter 23 is supplied to an AND gate 39. The output of the falling detection circuit 25 is supplied to an AND gate 37 while being supplied via inverter 41 to the AND gate 39. The output of the inverter 25 is supplied to an AND gate 40. The output of the falling edge detection circuit 30 is supplied to the AND gate 38, while being supplied via inverter 42 to the aforementioned AND gate 40. The output of the AND gate 36 is supplied to the aforementioned AND gate 37, 38, 39 and 40. These AND gate 37 to 40 output logical products of the respective input signals, that is, the aforementioned control signals Sig 3 to Sig 6, shown at K to N in fig 9. That is, the output signal Sig 3 of the AND gate 37 is a pulse signal going high (H) only for one clock pulse duration at each falling edge of the recording signal Sig 0, while the output signal Sig 4 of the AND gate 38 is a pulse signal going high (H) only for one clock pulse duration at each rising edge of the recording signal Sig 0. The output signal Sig 5 of the AND gate 39 is a pulse signal having a number of pulses associated with the signal width of the low level (L) of the recording signal Sig 0, while the output signal Sig 6 of the AND gate 40 is a pulse signal having a number of pulses associated with the pulse width of the high level (H) of the recording signal Sig 0. Hence, the control signal generating circuit 20 outputs the aforementioned control signals Sig 1 to Sig 6 from the aforementioned recording signals Sig 0 and clock pulse CK. Figure 10 shows a magnetic head drive circuit according to a second embodiment of the present invention. In this figure, the one end or point a of the head coil 1 is connected to a positive power source via diode 51. The other end or point b of the head coil 1 is connected via diode 52 to the positive source. The drive circuit of the present embodiment is otherwise the same as that of the preceding embodiment and hence the same numerals are affixed in fig 10 to the same circuit components as those used in fig 6 and the corresponding description is omitted. To the switching elements 2, 8, 5, 10, 4 and 9 of the present magnetic head drive circuit, there are supplied control signals Sig 1 to Sig 6 shown at C to H in fig 11 from the control signal generating circuit 20′. The control signal Sig 1 is in the form of a pulse train occurring during the high (H) level period of the control signal Sig 1 shown at C in fig 7. The control signal Sig 2 is in the form of a pulse train occurring during the high (H) level period of the control signal Sig 2 shown at D in fig 7. The remaining control signals Sig 3 to Sig 6 are in the form of the same pulse trains as the control signals Sig 3 to Sig 6 shown at E to H in fig 7. The operation of the magnetic head drive circuit is the same as that of the preceding first embodiment except that the above control signals Sig 1 and Sig 2 are in the form of pulse trains and the switching elements 2 and 8 are turned on only during the turned-on periods of the switching elements 5, 10, 4 and 9. Hence the present magnetic head drive circuit is able to control the switching elements 2, 8, 5, 10, 4 and 9 in their entirety by pulse trains. It is to be noted that FET's or transistors may be employed as the switching elements 2, 8, 5, 10, 4 and 9 and that diode 7, 11, 51 and 52 may be omitted, their functions being provided by parasitic diode effects especially when the FET's are employed. Figure 12 shows a magnetic head drive circuit according to a third embodiment of the present invention. In this fig, the one end of a capacitor 70 is connected via switching element 5 to one end or point a of the head coil 1, while being connected via switching element 10 to the other end or point b of the head coil 1. The other end of the capacitor 70 is grounded. Thus the circuit configuration of fig 12 is the same as that of the preceding first embodiment except that the negative power source shown in fig 6 is replaced by the capacitor 70. Hence the same circuit components are indicated by the same reference numerals as those used in fig 6 and the corresponding description is omitted for simplicity. Switching elements 2, 8, 5, 10, 4 and 9 of the magnetic head drive circuit are supplied with control signals Sig 1 to Sig 6, shown at C to H in fig 13, from the control signal generating circuit 20. These control signals Sig 1 to Sig 6 are each a replica of the aforementioned control signals Sig 1 to Sig 6 shown at C to H in fig 7. The potential Va at one end or point a of the head coil 1 is shown at I in fig 13. The potential Vb at the other end or point b of the head coil 1 is shown at J in fig 13. The potential Vc of the capacitor 70 is shown at K in fig 13 and also at I and J in fig 13 in broken lines. The current Iab in the head coil 1 is shown at L in fig 13. The potential Va at point a is decreased sharply at the falling edge of the recording signal Sig 0, that is, at the timing t₁ in fig 13, as in the magnetic head drive circuit of the preceding first embodiment, since the electrical charges are moved at this timing from the point a to the point b on account of the flyback of the inductance L of the head coil 1. Since the electrical charges of the capacitor 70 are shifted at this time via diode 7 to the head coil 1, the upper plate of capacitor 70 is at a considerably negative potential. When the switching element 5, to which the aforementioned control signal Sig 3 is supplied, is turned on at the timing of t₂, the capacitor 70 continues to be charged, until the capacitor 70 is connected to the positive power source 3 via head coil 1 and the switching elements 5 and 8 and the switching element 5 is turned off at the timing t₃. With the switching element 5 turned off, the potential prevailing at this time is maintained across the capacitor 70. The potential Vb at the point b is decreased sharply at the rising edge of the recording signal Sig 0, that is, at the timing shown at t₅ in 13, since the electrical charges are moved at this timing from the point b to the point a on account of the flyback of the inductance L of the head coil 1. Since the electrical charges of the capacitor 70 are shifted at this time via diode 11 to the head coil 1, the upper plate of capacitor 70 is again at a considerably negative potential. Thus the present magnetic head drive circuit may be driven by a single power source, since the capacitor 70 performs approximately the same operation as that of the negative power source 6 of the preceding first embodiment (it is noted that there are two power sources if the ground potential is thought of as a separate power source). It will be noted FET's or transistors may also be used as the switching elements 2, 8, 5, 10, 4 and 9 and the diodes 7 and 11 may be omitted by parasitic diode effects, especially when the FET's are employed as the aforementioned switching elements 5 and 10.

Claims: A magnetic head drive circuit comprising first and second power sources (3, 6; 3, C) presenting respective different potentials for supplying current to a coil (L) of a magnetic head adapted for carrying out opto-magnetic recording, first commutating means (2, 5) adapted for connecting each of said power sources (3, 6) to one end (a) of said coil (L), and second commutating means (8, 10) adapted for connecting each of said power sources to the other end (b) of said coil, the arrangement being such that each of said commutating means is actuatable on the basis of a recording signal such that said power sources presenting the respective different potentials are connected in a commutating fashion to the ends (a, b) of said coil (L) so that a potential difference is applied across said coil during the period of magnetic field inversion which is larger than the potential difference across the coil (L) during the following period of generation of stationary magnetic field; characterised by including first and second switching means (4, 9) each operable to connect the coil (L) to a third power source and actuatable on the basis of said recording signal to supply current from said third power source to said coil (L) between periods of inversion by actuation of said first and second commutating means to maintain the current flowing through the coil between said periods substantially at a constant level. A magnetic head drive circuit according to claim 1 comprising drive control means (20) for reciprocally actuating respective switching elements (2, 5; 8, 10; 4, 9) of the commutating means and of the switching means interposed between a power source of said three power sources (3, 6) affording a first potential and the coil (L) of the magnetic head by control signals having pulse widths associated with the recording signal, for actuating respective ones of the switching elements (2, 5; 8, 10; 4, 9) interposed between said coil (L) and one of the power sources affording a second potential for a predetermined period during magnetic field inversion, and for actuating the respective switching elements (2, 5; 8, 10; 4, 9) between said coil (L) and the source affording an intermediate potential by control signals composed of pulse trains having a number of pulses associated with the recording signal. A magnetic head drive circuit according to claim 2 wherein said drive control means (20) is adapted for reciprocally actuating respective ones of the switching elements (2, 5; 8, 10; 4, 9) interposed between the power source affording the highest potential and the coil (L) of the magnetic head by control signals having pulse widths associated with the recording signal, actuating respective ones of the switching elements (2, 5; 8, 10; 4, 9) interposed between the power source affording the lowest potential and said coil (L) for a predetermined period during magnetic field inversion and for actuating respective ones of switching elements (2, 5; 8, 10; 4, 9) interposed between the power source affording the intermediate potential and said coil (L) by control signals in the form of pulse trains each having a number of pulses associated with the recording signal. A magnetic head drive circuit according to claim 2 or 3 wherein a switching element (2; 8) and a reverse biased diode (51, 52) are connected in parallel between the coil (L) of the magnetic head and the power source affording the highest potential. A magnetic head drive circuit according to claim 1 comprising drive control means (20) for reciprocally actuating respective switching elements (2, 5; 8, 10; 4, 9) of the commutating means and of the switching means interposed between a power source of said three power sources (3, 6) affording a first potential and the coil (L) of the magnetic head by control signals in the form of pulse trains each having a number of pulses associated with the recording signal, for actuating respective ones of switching elements (2, 5; 8, 10; 4, 9) interposed between said coil and the source affording an intermediate potential by control signals in the form of pulse trains each having a number of pulses associated with the recording signal. A magnetic head drive circuit according to claim 5 wherein said drive control means (20) is adapted for actuating respective ones of said switching elements (2, 5; 8, 10; 4, 9) interposed between the power source affording the highest potential and the coil (L) of the magnetic head by control signals in the form of pulse trains each having a number of pulses associated with the recording signal, for actuating respective ones of the switching elements (2, 5; 8, 10; 4, 9) interposed between the power source affording the lowest potential and said coil (L) for a predetermined period during magnetic field inversion and for actuating respective ones of the switching elements (2, 5; 8, 10; 4, 9) between the power source affording an intermediate potential and said coil (L) by control signals in the form pulse trains each having a number of pulses associated with the recording signal. A magnetic head drive circuit according to claim 5 or 6 wherein a switching element (5; 10) and a reverse biased diode (7, 11) are connected in parallel between respective ends of the coil (L) and the power source (6) affording the lowest potential, and wherein a switching element (2; 8) and a diode (7; 11) are connected in parallel between said coil (L) and the power source affording the highest potential (3). A magnetic head drive circuit according to any one of claims 1 to 7 wherein a power source of a three said power sources presenting an intermediate potential affords a ground potential. A magnetic head drive circuit according to claim 8 wherein any one of three said power sources which affords the highest potential or the lowest potential is formed as a capacitor. A magnetic head drive circuit according to any one of the preceding claims wherein switching elements (2, 4, 5; 8, 9, 10) of the commutating means and switching means formed by a respective field effect transistor.

Inventors: FUJIIE, KAZUHIKO, OHMORI, TAKASHI
Applicants: SONY CORPORATION
Application year: 1988
Main classification: G11B20
IPC codes: G11B19, G11B11, G11B5