Forcing synchronisation on two pulse trains

Abstract: An apparatus and method for digital correction of oscillator drift provides for phase alignment between two clock signals (10, 12) running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths (40) of a variable delay path (20) formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator (14). The product of phase comparison controls a digital delay selector (18) to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signal. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal. A second digital phase comparator (22) compares the phase of the corrected clock signal with a predetermined reference phase of the clock signal from which it is derived. When the phases of the clocks are aligned, the second comparator produces a reset signal which resets the digital selection circuit to a predetermined point in the delay signal sequence, thereby operating the variable digital delay to correct the clock signal to a phase corresponding to the predetermined reference phase. The use of digital circuitry to correct for drift between the two clock signals permits the invention to be fully embodied in integrated digital circuits. The elimination of requirement for any analog circuitry to correct for oscillator drift permits phase alignment at various points along the line of clock distribution in an integrated digital system. By use of the invention, phase alignment can be performed on-chip between discreet functions on a single integrated circuit, between separate integrated circuits, and between independently-operating digital systems.

Description: The present invention relates to forcing synchronisation on two pulse trains such as, for example, phase alignment of clock signals of nearly equal frequencies in such a way that, if necessary, units of delay can be continuously added to the leading clock signal. A variety of means and procedures for compensation or correction of drift between oscillators operating at nearly the same frequency are known. For example in US-A-4,290,022 of Puckette, a phase shifter detects and corrects for phase difference between a pair of square wave of equal frequency. Phase correction is provided by selective imposition of a variable amount of delay on one of the signals, based upon the difference in phase between it and the other signal. No provision, however, is made for "closing the loop" between the corrected signal and the phase detection function in such manner as to support virtually continuously variable phase correction. Digital phase correction in the prior art finds its most varied expression in data synchronisation For example, US-A-3,505,478 of Kaneko and US-A-4,524,448 of Hullwegen, which has counterpart EP-A-0102 598 both teach synchronisation of a clock extracted from data received in a transmission channel to a local clock which is used by a data receiving unit to control local data receiving and decoding operations. In these references, one reference clock signal is extracted from transmitted data. In both patents, a variable delay unit is provided for inserting more or less delay into the received data signal before a reference clock signal is extracted from it. The Hullwegen patent shows closure of a loop in such a manner as to provide for continuous phase correction by a single loop which operates in response to the phase between the clock extracted from the data and the local clock. The Hullwegen circuit does not operate by directly correcting the phase of the clock; rather, it corrects the phase of the data signal from which the clock is extracted. Furthermore, no provision is made for resetting the correction loop when a predetermined amount of delay has been inserted, with the resetting done in such a manner as to make the amount of the delay apparently infinite. The present invention provides an apparatus for forcing synchronism on two nominally identical endlessly repetitive pulse trains on separate signal paths, comprising a limited length string of delay logic elements selectively insertable in a first one of the signal paths; first comparator means receiving as first input a signal derived from the output signal of the string of delay elements and as second input a signal derived from the pulse train of the other of the signal paths for comparing the phases thereof to detect any phase difference therebetween; control means responsive to the output of the first comparator means for adjusting the number of inserted delay logic elements in order to correct any phase difference detected thereby; the apparatus being characterised by second comparator means for comparing the phase difference between a signal derived from the output signal of the string of delay elements and one or more reference signals derived from the pulse train on the first signal path to test for a predetermined phase difference therebetween; and reset means responsive to the second comparator means for resetting the control means if the predetermined phase difference is found, to adjust the number of inserted delay logic elements directly to a predetermined number thereof, the operation of the control means being independent of any such resetting, whereby the control means operates as if the limited length string of delay logic elements were of unlimited length. The invention also provides various configuration incorporating the above together with its method of operation. A distinct advantage of this arrangement is that it can be achieved by means of a digital circuit which selects the amount of delay through a delay selection loop that operates continuously on the clock signal to be corrected through provision of a reset function. The inventors' critical realisation underpinning this invention is that the operation of a phase correction loop can be enhanced by provision of a reset function, operable when a predetermined amount of phase correction has been inserted into a compensated clock waveform. An embodiment of the present invention disclosed hereinafter is based upon a digital phase lock loop for phase aligning a first oscillator signal CLK₁ having a frequency f₁ and a second oscillator signal CLK₂, having a frequency f₂ nominally equal to f₁. A local digital phase comparator compares the phase of CLK₂ with the phase of a corrected oscillator signal CLK 1C , producing a delay control signal based upon the comparison. A digital selector is connected to the local digital phase comparator to generate delay signals in a delay signal sequence in response to a succession of delay control signals. A variable digital delay circuit receives CLK₁ and is connected to the digital selector for producing CLK 1C by delaying CLK₁ by an amount of time determined by the delay signal sequence. A reset digital phase comparator compares the phase of CLK 1C with a reference phase of CLK₁ and produces a reset signal when those phases are aligned. Finally, the digital selector responds to the reset digital phase comparator by generating the delay signal at a predetermined point in the delay signal sequence in response to the reset signal. The first oscillator signal CLK₁, having a frequency f₁, is phase aligned to the second oscillator signal CLK₂, having a frequency f₂ nominally equal to f₁. Next the phase of CLK₂ is compared with the phase of CLK 1C , a corrected oscillator signal having a frequency f₁, following which CLK₁ is delayed by an amount of time determined by the first comparison, then, CLK 1C is provided based upon the delaying step. The phase of CLK 1C is compared with a predetermined reference phase of CLK₁. Finally, the amount of time by which CLK₁ is delayed is adjusted to a predetermined amount when the phase of CLK 1C equals the reference phase of CLK₁. The basic apparatus and procedure thus expressed permit the achievement of phase lock between an external oscillator and a local oscillator running at nearly the same frequency as the external, thus supporting the synchronisation of different elements of a machine without the use of analog circuits. This is elaborated in the synchronisation of separate LSI chips of a machine by the use of local oscillators which run at approximately the same frequency, without the introduction of a single point of failure in the form of a single clock source. Provision of the invention in each of a pair of digital systems permits the synchronisation of the systems without the exposure to a single point of failure in the form of a single clock source for both systems. The present invention will be described further by way of example with reference to embodiments thereof as illustrated in the accompanying drawings, in which: Figure 1 is a signal diagram illustrating the concept of digital compensation according to the invention; Figure 2 is a waveform drawing illustrating the incrementation of delay in a corrected clock waveform according to a continuously cycling sequence; Figure 3 is a schematic diagram illustrating the fundamental structure of the apparatus of the invention; Figure 4 is a more detailed illustration of a pulse generator of Figure 3; Figure 5 is a more detailed schematic of a shift synchronising element of Figure 3; Figure 6 is a waveform diagram illustrating the operation of the pulse generator of Figure 4; Figure 7 is a waveform diagram illustrating the operation of the shift synchronising element of Figure 5; Figure 8 is a block diagram illustrating a specific implementation of the invention in synchronising the operations of master and slave logic circuits; Figure 9 is a block diagram illustrating the use of the invention in synchronising inter-chip functions between a pair of integrated circuits; Figure 10 is a block diagram illustrating the use of the invention in synchronising the operations of a pair of separate logic systems; and Figure 11 is a block diagrams of a nesting of phase locked loops. With reference now to Figure 1, the phase of a first conventional clock signal CLK₁ is compared with and adjusted to the phase of a second conventional clock signal CLK₂. It is asserted that CLK₁ has a frequency f₁ and that CLK₂ has a frequency f₂, and that f₁ is approximately equal to f₂. In the case of Figure 1, both signals are provided by independent oscillators, with the oscillator producing CLK₁ being slightly faster than the other. Further, it is postulated that CLK₁ is, by operation of the invention, tracking CLK₂. On an oscilloscope, CLK₁ will appear to shift leftward relative to CLK₂. Continual addition of a unit of delay (D) to CLK₁ will enable CLK₁ to stay in synchronisation with CLK₂. If f₁ differs slightly from f₂, eventually, CLK₁ will again lead CLK₂. When this occurs, a second unit of delay is added to the first. Units of delay are accumulated in a sequence of one unit increments; and CLK₁ is delayed by an amount of time equal to the accumulated total of unit delays. Assuming that the frequencies of the two oscillators producing CLK₁ and CLK₂ do not change, and assuming further that the process of adding a unit of delay D continues indefinitely in an incremental sequence, the eventual result will be to accumulate enough delay units to amount to at least one period of the CLK₁ waveform. At that time, an amount of delay equal to one period of CLK₁ can be removed from the accumulated delay without any evident effect upon the phase relationship of CLK₁ and CLK₂. Thus an apparent endless amount of delay can be added to the signal output by the faster oscillator. This concept is illustrated in Figure 2. In Figure 2, a corrected oscillator signal CLK 1C is produced by incrementing the amount of time by which CLK₁ is delayed by a predetermined amount. The time increments are equal, and each increment is referred to as a "delay event." The incremental process corresponds essentially to retarding the phase of CLK₁ in a series of discreet steps, with each incrementation resulting in the delay of the positive edge of CLK 1C by a predetermined amount. The incremental delays accumulate to the point where the next increment results in CLK₁ being delayed by more than one of its own fundamental periods. At this point, the sequence of adding delay events is ready to be reset to a predetermined point. Reset to the predetermined point is effected by removing a number of delay elements corresponding to a fundamental period of CLK₁. The apparatus of the invention which accomplishes this resettable delay incrementation sequence is illustrated in Figure 3. The apparatus, indicated by reference numeral 8, operates in conjunction with a first oscillator 10 producing CLK₁, and a second oscillator 12, producing CLK₂. CLK₂ is fed to a conventional digital divider 13 which divides CLK₂ by N to produce a reference signal REF₂ having a frequency f 2R =f₂/N , where N is understood to be a positive integer, greater than one. The apparatus 8 includes a local digital phase comparator 14 feeding a digital selector consisting of a left/right shift register 16 and gated selection logic 18. The digital selector is connected to a variable digital delay line 20. A reset digital comparator 22 provides a reset signal (RESET) to the left/right shift register 16. The phase comparator 14 indirectly compares the phases of a signal CLK 1C and CLK₂. The comparator performs the phase comparison on signals derived from CLK 1C and CLK₂. REF₂, described above, is one of those signals. The other, REF₁, is obtained, as explained hereinbelow, through dividing CLK 1C , the phase-shifted representation of CLK₁, by N. REF₁ thus comprises a signal having a frequency f R1 =f₁/N , which differs from the frequency of REF₂ in proportion to the difference between f₁ and f₂. Since REF₁ and REF₂ are derived directly from CLK 1C and CLK₂, respectively, it will be evident that any phase difference existing between the outputs of the oscillators 10 and 12 will be represented by an equivalent phase difference between REF₁ and REF₂. This phase difference is detected in the phase comparator 14. The phase comparator 14 can comprise a conventional digital comparator, such as a polarity hold latch, which compares negative transitions on REF₁ and REF₂. The measured phase difference measured by the local comparator 14 is indicated by a pair of outputs, one indicating a positive difference (+) when REF₁ leads REF₂ and a second output (-) when REF₁ lags REF₂. The difference signals are fed through respective pulse generators 24a and 24b, either of which produces a CONTROL pulse provided to a shift synchroniser 26. The shift synchroniser 26 operates to synchronise the provision of a respective CONTROL pulse to the left/right shift register 16 with the transitions of CLK₁. The synchronised CONTROL pulses are presented to the shift register 16 as left shift signals (CONTROL L ) or right shift (CONTROL R ) signals. The shift register 16 is a conventionally structured sequence of serially-connected storage elements d₀-d q , each shifting to an adjacent element in a direction determined by the CONTROL signal provided the shifting element. In addition, the storage element sequence is resettable by provision of a RESET signal to a predetermined configuration. Those skilled in the art will recognise that the shift register 16, thus described, conforms essentially to a shuttle counter which counts up or down by moving a single token signal to the left or to the right in the shift register 16. Further, upon the provision of the RESET signal, the shift register 16 is configured to place the token signal at a predetermined preset location anywhere in the serial sequence of storage elements. In Figure 3, the RESET signal causes the token to be set to the centre of the storage element sequence, represented by storage element d i . Over time, as a series of phase comparisons made by the comparator 14 results in the provision of a corresponding series of CONTROL signals, movement of the token signals in the shift register 16 will cause the register to output a corresponding sequence of DELAY signals. The DELAY signal sequence is denoted as DELAY₀-DELAY q . The DELAY signals are fed to the second element of the digital selector represented by the logic circuit 18. The logic circuit 18 includes a plurality of conventional, two-input AND gates 30, each connected to receive a respective one of the DELAY signals output by the register 16. The outputs of the AND signals are collected in a conventional OR circuit 32 having q+1 inputs. The variable digital delay circuit 20 consists of a serially-connected sequence of equivalent delay elements 40. Each of the lumped delay elements 40 comprises a conventional integrated circuit element. In the embodiment of Figure 3, each delay element consists of a series of two inverters. Every delay element will thus impose on a signal a determinable delay having a magnitude equal to the delay of any other delay element 40. Each delay element output represents a respective tap point of the delay circuit 20. Each tap represents a time or phase delay equivalent to the sum of element delays downstream in the delay circuit. The output of every delay element 40, save the last, is connected to the input of the next delay element and to the input of a respective one of the AND gates 30. The output of the last delay element is connected only to the input of the last AND gate of the logic 18. The sole other exception is the output of the centremost delay element, which is connected to the centremost AND gate 30 through a lumped delay element 42 and also, through a lumped delay element 43 to an AND gate 44. The output of the logic circuit 18 is provided through the output of the OR gate 32 and is connected to a conventional digital divider circuit 45, equivalent in all respects to the circuit 13. The divider circuit 45 divides the output of the OR circuit 32 by N. The output of the divider 45 is provided as a distribution clock (CLK₃) and also through a lumped delay element 46 to the other input of the AND gate 44. The output of the AND gate 44 is provided as one input to the reset phase comparator 22, with the other input of the comparator being taken from the output of the delay circuit 20. In operation, the circuit of Figure 3 receives CLK₁ at the input of the variable digital delay circuit 20 where through it is propagated. The output of one of the delay elements 40 is selected by activating one of the AND gates 30 through the provision of a DELAY signal. The activated AND gate therefore conducts CLK₁ delayed in phase (or in time) by an amount determined by the number of delay elements through which CLK₁ is conducted to the active AND gate. The delayed form of CLK₁ is provided as a corrected clock CLK 1C through the output of the OR circuit 32. The corrected clock CLK 1C is divided by the circuit 45 and conducted through the delay circuit 46 whence it is provided as the reference signal REF₁. The phase of REF₁ relative to the phase of REF₂ thus represents the phase of CLK₁ relative to the phase of CLK₂. The relative phase is measured and indicated by the phase comparator 14. The output of the comparator is provided in the form of a CONTROL pulse by one of the pulse generators 24a or 24b to the shift synchronisation circuit 26. The shift synchronisation circuit 26 conducts the CONTROL signal through a phase shift circuit corresponding with the circuit 20 so that the provision of shift control pulses to the storage elements of the shift register 16 is synchronised with the passage of CLK₁ through the delay circuit 20. Eventually, the CONTROL signal will be conducted to the storage element currently holding the delay token signal. When this occurs, the delay token signal will be shifted to an adjacent storage element. When the token is shifted, the DELAY signal provided by the storage element from which the token is shifted will inactivate, while the DELAY signal output by the element to which the token is shifted will activate. Thus, control will be shifted from the AND gate from which the DELAY signal is removed to the adjacent AND gate, whose DELAY control signal is activated. Since control is passed from one of the AND gates 30 to an adjacent one, it will be evident that one unit of delay will be either added to or deleted from CLK₁, thereby changing the phases of CLK 1C and REF₁. Such insertion or removal corresponds to a single delay event illustrated in Figure 2. Continuing with the description of operation of Figure 3, the reset phase comparator 22 compares the phase of CLK 1C with a reference phase of CLK₁ indicated in Figure 3 as CLK 1CNT . In this regard, the subscript "CNT" refers to the centremost delay element 40 in the variable digital delay circuit 20. The comparator thus compares the phase of the instantaneously-corrected clock signal CLK 1C with the phase of CLK 1CNT and provides the RESET signal when those phases are aligned. In practice, the total delay through the variable digital delay circuit 20 is selected to be equivalent to at least two periods of CLK₁. Thus, a lumped delay of at least one period of CLK₁ extends on either side of the centremost element 40 of the variable digital delay circuit 20. The phase comparator 22 detects when CLK 1C has been subjected to enough delay increments to shift it in phase to be equal to CLK 1CNT . When this occurs, the shift register 16 is reset to the centremost storage element, thereby selecting CLK 1CNT as the output of the OR circuit 32. This changes the source of CLK 1C , without changing its phase. The effect is to provide an apparently infinite amount of incremental delay by which to adjust CLK₁. Stated another way, the sequence of delay signals generated by the shift register 16 sequentially increments the delay in CLK₁ until a predetermined reference phase, equivalent to the phase of CLK 1CNT , is reached, whereupon the sequence is reinitialised by changing the phase of CLK 1C to that of CLK 1CNT . CLK 1CNT is provided through the AND gate 44 to the comparator 22 only when the gate is activated by the positive level of REF₁. This permits the gate 44 to sample CLK 1CNT only at intervals determined by REF₁. The delays 43 and 46 are inserted into the circuit paths of CLK 1CNT and REF₁ in order to equalise their arrival time at the AND gate 44. The delay 42 accounts for the throughput time to the output of the phase comparator 14. Figures 4 and 6 illustrate the structure and operation, respectively, of each of the pulse generators 24a and 24b. Each pulse generator consists of a pair of phased latches of the level sensitive scan design (LSSD) variety in which a data signal is presented to the data (d) input of the latch and shifted sequentially from a first latch stage (1) to a second latch stage (2) in response to respective clocks input to those stages. The latches of the Figure 4 generator are indicated by 50 and 52, with the respective stages of the latch 50 indicated by L1A and L2A and the stages of the latch 52 by L1B and L2B. Each of the latches 50 and 52 provides the positive sense of its output through a port O and the negative sense through a port O. The positive output of the latch 50 and the negative output of the latch 52 are collected in a conventional AND gate 58. The phased clock signals to the latches 50 and 52 are developed from CLK 1C though a circuit consisting of a conventional AND gate 54 and a conventional digital inverter 56. The purpose of the parallel circuit comprising the elements 54 and 56 is to present equal delays to the positive and negative sense of CLK 1C . The positive sense of CLK 1C is provided through the AND gate 54 to the first stages of the latches 50 and 52, while the inverted version of CLK 1C is provided through the inverter 56 to the second stages of the latches. The input to the first stage of the latch 50 is provided from one of the outputs of the comparator 14, while the data input to the latch 52 is taken from the positive output sense of the latch 50. The operation of the pulse generator of Figure 4 is shown in Figure 6. Assuming a phase difference signal is activated by the phase comparator 14, indicating a phase difference, the high level of CLK 1C causes the first stage of the latch 50 to follow the rising edge 59 of the DO SHIFT pulse. The negative edge 60 of CLK 1C , inverted by the inverter 56 to clock the second stage of the latch 50, moves the DO SHIFT level to the output O of the latch 50. At this time, the negative output of the latch 52 is positive, causing the control signal to be emitted by the AND gate 58. Thus, the control signal is generated following the negative edge 60 of CLK 1C . Since the positive output of the latch 50 is fed forward into the latch 52, the inverse output, O, of latch 52 will fall following the negative-going edge 62 of CLK 1C , deactivating the CONTROL signal. Figures 5 and 7 illustrate how the control pulse generated by one of the pulse generators 24a or 24b is synchronised with the provision of CLK₁ to the delay circuit 20 in such manner that the state of the shift register 16 does not change while CLK 1C is active. In Figure 5, the shift synchronisation circuit 26 is a sequence of serially-connected delay elements 69 equivalent to the delay elements 40 which make up the variable digital delay circuit 20. A portion of the shift register 16 for shifting a delay token to the right when CLK₁ leaves CLK₂ is illustrated as including LSSD latch pairs 70, 72, and 74. Assume that latch 72 holds the delay token signal, AND gate 30 (representing TAP n of the delay circuit 20) is active and that OR gate 32 is providing CLK₁, obtained from TAP n of the delay circuit 20, as CLK 1C . Next, assume that the control signal generation scenario of Figure 6 has occurred, with CLK₁ being provided through AND gate 30, denoted as CLK 1n in Figure 7. Finally, assume that the clock for the L2 stages of the latches, although not shown, would be controlled to be active at a time that the CONTROL pulse was not propagating through the shift synchronising circuit 26. The negative transition 60 of CLK₁ arrives at TAP n of the delay circuit 20 shortly before the control pulse arrives at TAP n of the shift synchronisation circuit, where it is provided to the latch 72 as CONTROL n . Since CLK₁ and the CONTROL pulse move through essentially identical delay circuits, the edge 60 of CLK 1n and the edge 64 of the CONTROL pulse will have the same phase relationship as in Figure 6, thereby enabling the CONTROL pulse edge 64 to shift the delay token signal from the latch 72 to the latch 74 as shown in the edge transitions 66 and 68. When the DELAY n signal provided by the latch 72 deactivates, the AND gate n is inactivated, while the next AND gate to the right of it (AND n+1 , not shown) is activated (DELAY n+1 ). The outputs of the AND gates are combined by the OR gate 32 to provide a continuous CLK 1C signal with an element of delay added as shown. Thus, the provision of the control function through the shift synchronisation circuit 26 synchronises it with the transition in CLK₁ which generated it. The CONTROL bit is propagated such that it acts to change the state of the shift register 16 only when the CLK₁ signal is inactive at the TAP of the variable digital delay circuit to be moved. It will be evident to those skilled in the art that the propagation of the CONTROL pulse will operate to synchronise both a reset of the register 16 and a one position shift in TAP selection. Although Figure 5 illustrates essentially a lead shift synchronisation, the data path controls for causing a lag (shift left) to remove delay, as well as the data path controls for establishing a reset condition work in the shift register 16 in a manner similar to that illustrated and described in connection with Figure 5, and are common knowledge to logic designers. Returning to Figure 3, it should be evident that the phase correcting feature of this circuit provides the ability to synchronise the oscillator 10 to the oscillator 12 without affecting the oscillator 12. This implies that if the oscillator 12 operates as "master" oscillator, the act of synchronising the oscillator 10 to it would not affect the operation of the master. Further, it also implies that any number of "slaves" could be synchronised to the one "master." Thus, the phase compensation function performed by the circuit of Figure 3, which is usually associated with communication or data handling tasks, now is moved to the logic control task. Since the circuit of Figure 3 is formed from digital components, it can be fully integrated on the same circuit chips with the rest of the logic which it controls. It is reasonable to assume independent crystal oscillators such as the oscillators 10 and 12 for the slave and master units. Further, it should be assumed that the variability or difference in frequency between the oscillators 10 and 12 is small. Those skilled in the art will realise that crystal controlled oscillators can be shifted in frequencies by small amounts through variable capacitance tuning employing varactor diodes and other, similar elements. However, in such cases, the all-digital objective of the invention would not be met. Instead, in the invention the oscillator 10 (the "slave" oscillator) is allowed to drift relative to the "master" oscillator (the oscillator 12) while the phase-lock signal REF₂ is delivered to the slave logic. In most cases, it will be desirable for the frequencies of the reference signals REF₁ and REF₂ to be equal to some integer division (such as 1/16) of their respective oscillator frequencies, in order to reduce the difficulty of propagating the signals. Figure 3 essentially illustrates the synchronisation of the slave oscillator 10 with a master oscillator 12. Another variation of the master/slave arrangement is illustrated in Figure 8. In Figure 8, the elements 10, 12, 13, 14, 16, 18, 20, and 45 are functionally equivalent to the identically-referenced elements in Figure 3. However, in Figure 8 the delay circuit 20 has only half the number of delay elements and provides a total delay of slightly more than one period of CLK₁. The shift register 16 can still shift left or right according to the CONTROL signal generated by the comparator 14, however, the register 16 has half as many storage elements as the register 16 in Figure 3, and further can be reset to the extreme lefthand (RL) or extreme righthand (RR) element. In addition, the circuit of Figure 8 includes two phase comparators 82 and 84, each comparing the corrected clock signal CLK 1C with a respective reference phase of CLK₁. The phase comparator 82 compares the currently-selected phase of CLK 1C with CLK₁ unshifted, and thus compares the corrected version of the clock against its zero-phase representation. Thus, as delay is added to CLK₁ by shifting the delay token to the right in the register 16, the register will be reset to the extreme left-hand position, inserting the minimum phase delay in CLK₁, as CLK 1C comes into phase with CLK₁. Similarly, the phase comparator 84 compares the currently-delayed waveform with the maximally-delayed waveform, and resets the shift register 16 to the extreme righthand storage element when the phase of the corrected waveform equals that of the maximally-delayed waveform. Thus, when CLK₁ lags the master clock generated by the oscillator 12, delay is incrementally removed from CLK 1C by moving the shift token in the register 16 to the left, with the procedure being reinitiated by a reset to the right in the register 16 when CLK 1C equals the maximally-shifted clock waveform in phase. Figure 9 illustrates the use of a phase correction circuit consisting of elements 14, 16, 18, and 20 corresponding to their identically-numbered counterparts in Figure 3, with the exception that the comparator 14 measures phase difference in only a single direction and the shift register phase splitter 16 shifts in that single direction. The corrected waveform CLK 1C is output on signal line 90 and provided to a shift register counter 92, which essentially performs the 1/N division necessary to obtain the reference signal of the local phase comparator 14. In Figure 9, it is assumed that a single clock is distributed from a master integrated circuit 91 to the slave integrated circuit 89 for synchronisation of digital functions performed by the slave circuit. In this context, no independent oscillator signal is provided to the slave circuit 89. Instead, CLK₁ is provided as a distributed clock whose genesis is the oscillator 94 providing CLK O ¹ 1 which is received by the master circuit 91 and divided by the 1/N dividing circuit 95. The divided clock is passed through a driver 97 to provide the reference REF₀ which is fed through the receiver 101 to be compared against REF₁ by the phase comparator 14. The undivided clock is distributed through the driver 98 and is received by the slave circuit 89 through a receiver 100. The clock out of the receiver 100 is re-labled as CLK₁, which serves as the source clock waveform for all functions on the slave circuit 89. The phase-corrected version of CLK₁, that is CLK 1C , is divided by N through the shift register counter 92 and distributed to other logical functions on the slave circuit 89 through a conventional clock distribution power tree 103. One of the clocks distributed through the power tree 103 is fed back to the phase comparator 14 as REF₁. Phase comparator 14 compares the difference between REF₁ generated on chip with REF₀ received from the master chip and decides when and if to shift the control bit in the shift register to add delay to REF₁. Each time this occurs phase comparator 105, compares the incoming oscillator signal with the delayed oscillator signal 104. When the two are in phase the shift register can be reset without disturbing the delayed oscillator signal and an arbitrary amount of delay can be added. The arrangement illustrated in Figure 9 is effective to compensate for skew imposed on a master clock distributed to a plurality of slave integrated circuits such as 89. For example, a logic assembly that is made up of a number of LSI circuit chips that must work in synchronism at a speed that approaches the switching speed of the logic on the chips is affected by the distribution of CLK₀ to the slave chips. Circuit chips that contain 20,000 to 40,000 cells will require 4 to 6 levels of clock signal repowering in order to provide enough drive capability for all of the circuit loads involved. Each level imposes a certain amount of delay in the propagated clock signal. The intercircuit drivers and receivers also contribute to this delay. The normal procedure based upon generating a clock signal in one location (the master circuit 93) and distributing it as needed to and through slave circuits, produces in a clock signal skew between circuits resulting from the total delay through the circuit path and the tracking precision of the technology between the chips. Interchip skew can be as bad as one-half the worst case propagation delay or more. In Figure 9, a single reference oscillator 94 provides the frequency precision required for logic circuit operation in the form of CLK₀. The lower frequency reference signal REF₀ is generated on the master chip 93 and distributed to all slave chips, together with CLK₀. Each of the slave circuits, such as the circuit 89, provides the adjustable delay described above to align the circuit clock (CLK₁) with the distributed clock (CLK₀). Initially, the ring counter 92 will be inactivated and the shift register 16 set to minimum delay. The counter 92 will be activated with the arrival of the reference signal REF₀, allowed to run freely thereafter, and then stepped by the repowered clock signal CLK 1C . By starting the ring counter 92 away from the end of a cycle, it will be possible to ensure that the local phase, indicated by REF₁, always initially leads the reference phase REF₀. While comparing the trailing edges of the reference and local phases, delay can be added one element at a time until a match is made. Once this alignment is accomplished, no further action is necessary unless the frequency of the distributed clock (CLK₀) is affected by changes in operating conditions such as temperature or power supply. The benefits derived from the configuration of Figure 9 are manifold. Since there is no need for active phase compensation while the logic on the chip is in operation, the shift register 16 can comprise a simple binary counter, without the requirement for the shift synchronisation of Figure 3. Since phase correction action is always accomplished from one direction over a limited range of phase error, the phase comparator 101 can be as simple a circuit as a polarity hold latch. Multiple slave chips can be synchronised to the reference REF₀, permitting an arbitrary number of chips to work together in relative synchronisation. Further, failure of any one slave chip's phase compensation circuit will not cause disturbance to any other slave chip. Finally, continuous monitoring of the state of phase equilibrium on each chip permits fault isolation at the failing chip and enhances the visibility of errors. To recap, in Fig 9, a single oscillator 94 provides the frequency precision required for logic circuit operation in the form of CLK₀1. The lower frequency reference signal REF₀ is generated on the master chip 93. Each of the slave chips, such as 89, provides the adjustable delay described above to align a corresponding low frequency reference generated on chip, 1/N 106, with the master reference. Phase comparator 14 compares the difference between REF₁ generated on chip with REF₀ received from the master chip and decides when and if to shift the control bit in the shift register to add delay to REF₁. Each time this occurs phase comparator 105, compares the incoming oscillator signal with the delayed oscillator signal 104. When the two are in phase as detected by comparator 105 the shift register can be reset without disturbing the delayed oscillator signal and an arbitrary amount of delay can thus be added. Since the circuits of slave chip 89 form all the function needed for a phase locked loop, and since phase locked loops can be nested in several ways, it is possible to have a slave 89 perform frequency locking as well as delay compensation at the same time. Figure 11 displays such a nesting such that the reference from Master0 is distributed to each of its slaves (slave 00, 01, 02, etc). When Master0 is performing frequency lock with Master1, it is necessary for slave 00, 01, 02, etc to frequency lock with Master1 in order to keep in phase with Master0. The benefit of doing things in this manner is that the act of keeping in frequency lock will provide additional opportunities to remove any delay changes caused by temperature changes in the hardware without requiring the complexity of Figure 8 in which the Phase lock loop hardware must be able to reset Right or Left or in function add or remove delay. The function of the Figure 9 circuits only allow it to add delay. The Figure 10 illustrates how a duplex arrangement after the style of Figure 3 can be used to synchronise a pair of autonomous digital systems 110 and 120 whose respective operations are controlled and synchronised by clocks derived from oscillators 111 and 121. Based on trends in industry, there is an increasing need to synchronise the two independent clocking sources to support the use of dual system configurations. Such configurations are favoured, as they provide built-in redundancies, and thereby achieve higher levels of availability and reliability. Further, when there exists a requirement for communication between two such systems, it is advantageous to employ synchronised clocking to maximise the performance and reduce hardware complexity and costs. In the past, synchronisation of such systems has been accomplished by distribution of a single clock to both systems. This achieves synchronisation, but is a troublesome solution in that introduces a single point of failure to the configuration. Providing an independent oscillator to each system, and employing the method of the invention to synchronise the oscillators, achieves the goals of maximum performance, availability, and reliability. Further, use of arrangements permits synchronisation to be implemented in digital, rather than analog, circuitry, which provides the benefits of less costly test procedures. As is known, analog designs typically require manually generated test patterns in the use of unique test equipment. These factors translate into added test time and increased production cost. Digital implementations, however, can employ structure design techniques which allow a higher degree of test coverage and facilitate the use of automated test pattern generation. In addition, testing digital components can be performed using the same logic test equipment that is used to test the associated functions of the overall systems. The embodiment of Figure 10 therefore assumes the two autonomous digital systems 110 and 120, each incorporating a digital phase compensation circuit according to the above teachings. In system 110 of Figure 10, a delay select logic circuit includes the shift register 16 and select logic 18 described above, the variable digital delay circuit 20, also described above, as well as the local phase comparator 14 and reset phase comparator 22, both also corresponding to identically-numbered elements of Figure 3. The elements 14, 16, 18, 20, and 22 are interconnected as described above, with the exception that the comparators 14 and 22 compare the phases of undivided clock signals. A corresponding complement of the circuitry is provided in the system 120, with the components being indicated by apostrophed reference numerals simply to distinguish their locations from the locations of the identically-referenced elements in the system 110. Each of the systems 110 and 120 performs the phase compensation in response to measurement performed directly upon uncompensated and compensated clock waveforms. In addition, the compensated clock waveforms are exchanged by the systems to provide references (REF₁ and REF₂) against which to compare the local compensated clock waveform. Thus, for example, in the system 110 the local phase comparator 14 compares the local corrected clock CLK 1C with the corrected clock CLK 2C of the system 120. Thus, phase compensation in each of the systems is performed in response to phase difference detected by the phase comparators 14 and 14′ between the two compensated clock waveforms. In each case, the shift register in the delay select logic is reset when the locally-generated clock waveform in the local corrected clock waveform are in phase. As with the circuit of Figure 3, the delay select logics 16, 18, and 16′, 18′, introduce variable delays in the paths of the oscillators 101 and 111, respectively. The gating of the variable digital delay circuits 20 and 20′ is controlled by the shift registers in the delay select logics. Each one-bit shift of the delay token in a respective register introduces one additional delay element into the oscillator path. The sole limitation on operation of the compensation circuitry is that the shifting through a shift register is limited to the right-hand direction, thereby limiting each circuit to lead correction. This removes the instability which would occur if, for example, the system 110 perceived that its locally compensated clock waveform CLK 1C was leading the compensated waveform produced by 120, while the system 120 perceived the opposite. In this case, both systems would attempt to independently compensate for same phase misalignment, thereby introducing the possibility of oscillation. Limiting each system to correct only in one pre-ordained direction eliminates the instability. For example, when CLK 1C leads CLK 2C , the compensation circuit of the system 110 will add delay to CLK 1C to bring the two waveforms into phase alignment, while the system 120 will take no action. With the addition of delay, the two clock waveforms will come into alignment. As illustrated in Figure 10, it is the corrected clocks, CLK 1C and CLK 2C , which are distributed within their respective systems for functional clocking.

Claims: An apparatus for forcing synchronism on two nominally identical endlessly repetitive pulse trains (CLK1, CLK2) on separate signal paths, comprising a limited length string (20) of delay logic elements (40) selectively insertable in a first one of the signal paths; first comparator means (14) receiving as first input a signal derived from the output signal of the string of delay elements and as second input a signal (REF2; REF0) derived from the pulse train of the other of the signal paths for comparing the phases thereof to detect any phase difference therebetween; control means (16, 18, 24a, 24b, 26; 92) responsive to the output of the first comparator means for adjusting the number of inserted delay logic elements in order to correct any phase difference detected thereby; the apparatus being characterised by second comparator means (22; 82, 84; 105) for comparing the phase difference between a signal (REF1) derived from the output signal of the string of delay elements and one or more reference signals (CLK1CNT) derived from the pulse train on the first signal path to test for a predetermined phase difference therebetween; and reset means responsive to the second comparator means (22; 82, 84; 105) for resetting the control means (16, 18, 24a, 24b, 26; 92) if the predetermined phase difference is found, to adjust the number of inserted delay logic elements directly to a predetermined number thereof, the operation of the control means (16, 18, 24a, 24b, 26; 92) being independent of any such resetting, whereby the control means (16, 18, 24a, 24b, 26; 92) operates as if the limited length string of delay logic elements were of unlimited length. Apparatus as claimed in claim 1, wherein the, or each, reference signal is the pulse train on the first signal path delayed by a predetermined amount equivalent to from none through one half to all of the available delay elements. Apparatus as claimed in claim 2, wherein the control means (16, 18) includes means (24) for detecting the sense in which the phases differ and can increase or decrease appropriately the number of inserted delay elements, wherein the reference signal is the pulse train on the first signal path delayed by an amount equal to one half of the available delay elements, the reset means being arranged to reset the number of inserted delay elements to one half of those available. Apparatus as claimed in claim 2, wherein the second comparator means (82, 84) is arranged to compare with reference signals which are the pulse train on the first signal path delayed by an amount equivalent to a null delay and a full delay equal to all the available delay elements and the reset means is arranged to reset to no or all available delay elements inserted appropriately. A slave unit comprising apparatus as claimed in any preceding claim adapted to be clocked by a master unit, wherein, in operation, one pulse train is the clock-in signal from the master unit to the slave unit and the other pulse train is the effective clock signal used by the slave unit. A digital system comprising a plurality of slave units adapted to be clocked by a master unit, each slave unit comprising apparatus as claimed in any of claims 1 to 4 incorporated therein, wherein, in operation, in each slave unit one pulse train is the clock-in signal from the master unit to the slave unit and the other pulse train is the effective clock signal used by the slave unit, whereby synchronism with master unit and each other is forced on each slave unit. Digital system comprising a pair of independently clockable units each comprising apparatus as claimed in any of claims 1 to 4 incorporated therein, the arrangement being such that for each unit one or said pulse trains is derived from the clock of the other unit. A digital phase lock loop for phase-aligning a first oscillator signal (CLK₁) having a frequency f₁ - one pulse train - and a second oscillator signal (CLK₂) having a frequency f₂ nominally equal to f₁ - the other pulse train - , comprising the apparatus of any of claims 1 to 4, wherein the first comparator (14) is a local digital phase comparator for comparing the phase of a signal derived from the second oscillator signal (CLK₂) with the phase of a signal derived from the corrected oscillator signal (CLK 1C ), and for producing a delay control signal based upon the comparison; the control means (16, 18) comprises digital selection logic connected to the local digital phase comparator (14) for generating delay signals in a delay signal sequence (DELAY₀ ... DELAY q ) in response to a succession of delay control signals; the delay elements (40) form part of a variable digital delay circuit (20) for receiving the first oscillator signal (CLK₁) by adjusting the phase of the first oscillator signal (CLK₁) by delaying the first oscillator signal (CLK₁) an amount of time which changes with the delay signal sequence; and the second comparator (22) is a reset digital phase comparator for comparing the phase of the corrected oscillator signal (CLK 1C ) with one or more reference phase signals (CLK1CNT) produced by the variable digital delay circuit and for producing a reset signal when the phases of the corrected oscillator signal (CLK 1C ) are of the reference phase signals (CLK1CNT) are substantially equal; the reset means being operative on the digital selection logic to generate a delay signal corresponding to a predetermined point in the delay signal sequence in response to the reset signal. A digital phase lock loop as claimed in claim 8, wherein the digital variable delay means includes: a series of digital delay elements (40); a plurality of AND elements (30), each having a first input connected to receive the first oscillator signal (CLK₁) through a respective digital delay element, a second input connected to receive one delay signal in the sequence of delay signals, and an output; and an OR element (32) for receiving the outputs of the AND elements and for generating the corrected oscillator signal (CLK 1C ) in response to the AND element outputs. A digital phase lock loop as claimed in claim 8 or claim 9, wherein the digital selection means includes a multi-stage shift element (16) which moves a delay token signal between adjacent shift stages in response to the control signal, each of the shift stages producing a respective delay signal in the delay signal sequence in response to the delay token signal. A method of phase-aligning a first oscillator signal (CLK₁), having a frequency f₁, with a second oscillator signal (CLK₂) having a frequency f₂ nominally equal to f₁, comprising the steps of: during a succession of cycles of the second oscillator signal (CLK₂), comparing the phase of the second oscillator signal (CLK₂) with the phase of a corrected oscillating signal (CLK 1C ) having a frequency f 1C =f₁ , to produce a sequence of delay control signals; delaying the first oscillator signal (CLK 1C ) by an amount of time which is successively changed in uniform time units in response to the delay signal sequence; providing the corrected oscillating signal (CLK 1C ) based upon the delaying step; comparing the phase of the corrected oscillating signal (CLK 1C ) with a predetermined reference phase of the first oscillator signal (CLK₁); and adjusting the amount of time by which the first oscillator (CLK₁) is delayed to a predetermined amount corresponding to the reference phase when the phase of the corrected oscillator signal (CLK 1C ) equals the phase of the first oscillator signal (CLK₁).

Inventors: AZEVEDO MICHAEL JOSEPH, CORCHERO CHARLES ANTHONY, LANG DONALD JOHN, WOODMAN GILBERT ROUSE JR, AZEVEDO, MICHAEL JOSEPH, CORCHERO, CHARLES ANTHONY, LANG, DONALD JOHN, WOODMAN, GILBERT ROUSE, JR.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H03L7
IPC codes: H04L7, G06F1, H03L7