A METHOD OF CONTROLLING AN OPTICAL PNPN THYRISTOR

Abstract: The method comprises the step of applying a train of pulses (313) across the anode (33) and cathode (36) of the thyristor to maintain a low impedance state of an optical pnpn thyristor which is shifted beforehand to be in a low impedance state by a positive set pulse (311). Each of the train of pulses (313) is less than in its level than the positive set pulse (311). When light emission is required for the reading of information, another positive set pulse (312) is applied to the optical pnpn thyristor. As a result, electric power consumption is reduced during a time storing the information. The train of pulses (313) may be superimposed on a low bias voltage (Vb1).

Description: The invention relates to a method for controlling an optical pnpn thyristor and more particularly to a method in which the optical pnpn thyristor is turned on to be held with reduced power consumption. An optical semiconductor memory in which light emission is performed with a small amount of trigger light to be continued even after the extinction of the trigger light is a basic device indispensable with an optical apparatus such as an optical switching, an information parallel processing system etc. Such an optical semiconductor memory is described as an optical pnpn thyristor on pages 596 to 600 of "Journal of Applied Physics, 59(2), 15 January 1986". The conventional optical pnpn thyristor comprises an anode layer of p-AlGaAs, a cathode layer of n-AlGaAs, and a gate layer sandwiched between the anode and cathode layers wherein the gate layer is of a forbidden band narrower than those of the anode and cathode layers and includes an n-gate layer of n-GaAs and a p-gate layer of p-GaAs. In operation, the pnpn thyristor is turned on to be shifted from a high impedance state to a low impedance state wherein carriers are mainly injected into the n-gate layer to be confined therein thereby emitting light with a high light emission efficiency. If a predetermined bias voltage less than a turning-on voltage is applied across the anode and cathode layers, light emission is continued even after the extinction of a trigger light so that the pnpn thyristor can be used for an optical memory. In the conventional optical pnpn thyristor, however, there is a disadvantage that a considerable amount of electric power is consumed in maintaining the ON state by applying the predetermined voltage thereto under the extinction of the trigger light. According to the report of the aforementioned "Journal of Applied Physics", output light of 30uW is obtained with an injected current of 100mA when voltage of approximately 1.5V is applied across the anode and cathode layers. Therefore, a power consumption of 150mW is resulted from one element of the pnpn thyristor. As compared to an electronic semiconductor memory such as S-RAM, D-RAM etc. the value of 150mW is much higher so that it is difficult to put the pnpn thyristor into a practical use due to a construction that pnpn thyristors of the number as much as required must be arranged on a wafer. Accordingly, it is an object of the invention to provide a method of controlling an optical pnpn thyristor wherein the ON state is held to store optical information which is written thereinto and read therefrom with a low electric power consumption. The method according to the invention is set forth in claim 1 below. The invention will be explained in more detail in conjunction with appended drawings wherein, Figs. 1A and 1B are cross sectional and top views showing a conventional optical pnpn thyristor, Fig. 2 is a graph showing a relation between voltage and current when the conventional optical pnpn thyristor is driven, Figs. 3A to 3C are timing charts showing a relation among voltage, trigger light and light output when the conventional optical pnpn thyristor is driven, Fig. 4 is a cross sectional view showing an optical pnpn thyristor used for conducting a process for controlling an optical pnpn thyristor to be driven according to the invention, Fig.5 is a graph showing a relation between voltage and current in a process for controlling an optical pnpn thyristor to be driven in a first embodiment according to the invention, Figs. 6A to 6D are timing charts showing a relation among voltage, trigger light, current and output light in the first embodiment, Figs. 7A to 7C are energy band diagrams of an optical pnpn thyristor, Fig. 8 is a graph showing a relation between ON state holding time and a bias voltage in a process for controlling an optical pnpn thyristor to be driven in a second embodiment according to the invention, Figs. 9A to 9D are timing charts showing a relation among voltage, trigger output, current, and output light in the second embodiment, and Fig. 10 is a circuit diagram showing a process for controlling an optical pnpn thyristor to be driven in the first embodiment. DESCRIPTION OF PREFERRED EMBODIMENTS Before describing a process for controlling an optical pnpn thyristor to be driven in an embodiment according to the invention, the aforementioned pnpn thyristor which is described in the "Journal of Applied Physics" will be explained. Figs. 1A and 1B show the pnpn thyristor which comprises a contact layer 31 of P⁺-GaAs, a buffer layer 32 of P⁺-GaAs having a thickness of 0.3µm, an anode layer 33 of P⁺-AlGaAs having a thickness of 0.5µm, an n-gate layer 34 of n-GaAs having a thickness of 1µm, a P⁺-gate layer 35 of P⁺-GaAs having a thickness of 3nm (30Å), a cathode layer 36 of n-AlGaAs having a thickness of 40nm (400Å), a contact layer 37 of n⁺-GaAs having a thickness of 0.5µm, an anode electrode 30 formed on the back surface of the contact layer 31, and a cathode electrode 38 having an aperture 38A for trigger and output lights formed on the top surface of the contact layer 37. In the pnpn thyristor, the n and P⁺- gate layers 34 and 35 are sandwiched between the anode and cathode layers 33 and 36, and forbidden band width of the formers are narrower than those of the latters. In operation, when the pnpn thyristor is turned on, a state thereof is shifted from a high impedance to a low impedance, and carriers are mainly injected into the n-gate layer 34 and confined therein to result in light emission therefrom. As described before, a high light emission efficiency is obtained because the gate layer including the n and P⁺-gate layers 34 and 35 is sandwiched between the anode and cathode layers 33 and 36 having wider forbidden bands than that of the gate layer. Figs. 2 and 3 show a conventional process for controlling such an optical pnpn thyristor to be driven wherein voltage V b less than a switching voltage V s by which a high impedance state is shifted to a low impedance state is applied to an optical pnpn thyristor. In the circumstance, the pnpn thyristor is turned on to emit light when trigger light is supplied thereto. As long as the voltage V b is not less than voltage V h as shown in Fig. 2 even if the voltage V b is decreased down to the voltage V h after the turning-on of the pnpn thyristor, the low impedance state is maintained therein. Thus, the voltage V h is defined as a holding voltage. In such a low impedance state, light output of 30µW is obtained with current of 100mA when the voltage V b of 1.5V which is more than the holding voltage V h is applied across anode and cathode layers thereof as described before. Therefore, there is the aforementioned disadvantage in the conventional process for controlling an optical pnpn thyristor to be driven. Fig. 4 shows an optical pnpn thyristor used in an experiment in which a process for controlling an optical pnpn thyristor to be driven according to the invention is embodied as described later. The optical pnpn thyristor comprises a buffer layer 42 of n-GaAs having a thickness of 0.5µm and a carrier density of 2x10¹⁸cm⁻³ on a substrate 41 of n-GaAs, a cathode layer 43 of n-Al 0.4 Ga 0.6 As having a thickness of 1µm and a carrier density of 5x10¹⁷cm⁻³, a p-gate layer 44 of p-GaAs having a thickness of 50Å and a carrier density of 1x10¹⁹cm⁻³, an n-gate layer 45 of n-GaAs having a thickness of 1µm and a carrier density of 1x10¹⁷cm⁻³, an anode layer 46 of p-Al 0.4 Ga 0.6 As having a thickness of 0.5µm and a carrier density of 5x10¹⁸cm⁻³, and a contact layer 47 of p-GaAs, respectively grown by using molecular beam epitaxy (MBE). The optical pnpn thyristor further comprises a cathode electrode 49 provided on the back surface of the substrate 41, an anode electrode 50 provided on the top surface of the contact layer 47, an n-gate electrode 51 provided on the n-gate layer 45, and a p-gate electrode 52 provided on a diffusion region 48 diffused through the n-gate layer 45 and the p-gate layer 44 into the cathode layer 43 with Zn. In the pnpn thyristor, a cathode region is composed of the cathode layer 43, the buffer layer 42 and the substrate 41, and an anode region is composed of the contact layer 47 and the anode layer 46. The size of the pnpn thyristor described above is 100µm x 100µm, and a switching voltage V s and a holding voltage V h are 6.2V and 1.5V, respectively as shown in Fig. 5. The holding voltage V h is detected visually on a display of a curve tracer in accordance with a measured curve of current and voltage. Although a feature of the invention will be described later, the invention is based on a finding that ON state is stored in an optical pnpn thyristor for a minute time even if a bias voltage V b is decreased less than a holding voltage V h under ON state of the pnpn thyristor. According to the pnpn thyristor as shown in Fig. 4, light output is improved to be 200µW with current of 100mA in a low impedance state thereof as compared to the conventional pnpn thyristor because a layer structure thereof is improved. In operation, a set pulse 311 of voltage V b (= 2.3V) is applied across the anode and cathode electrodes 46 and 43 (FIG. 6A), and trigger light as shown in Fig. 4 by an arrow is supplied to the pnpn thyristor simultaneously (FIG. 6B) so that a state shift is performed therein from a high impedance to a low impedance thereby resulting in current flowing response (FIG. 6C) and light emission (FIG. 6D). Thereafter, the set pulse 311 is turned off, and intermittent pulses 313 each having a pulse width of 500 ns, a pulse interval of 7µs and voltage of V I (=1.7V) are intermittently applied to the anode and cathode electrodes 46 and 43. As a matter of course, the pulse interval is less than a period during which ON state is stored in the pnpn thyristor even if a bias voltage V b is decreased less than a holding voltage V h . In the circumstance, no current flowing response is observed in a range of illustration in Fig. 6C because the pnpn thyristor operates in a region where a differential resistance for a current and voltage characteristic is very large. In order to maintain ON state of the pnpn thyristor, a small amount of excess carriers must be only held in an exterior of the pnpn thyristor. Therefore, an amount of carriers injected by one of the intermittent pulses 313, that is, current value induced therein is inevitably small. As a result, an electric power consumption of 13µW which is a holding electric power is resulted from the application of the intermittent pulse 313. In the embodiment, although the pulse width is 500 ns, it may be shorter than that period during which ON state is held. A holding current is measured to be several µA in accordance with a current and voltage characteristic of a curve tracer when a holding voltage V h is 1.5V. Accordingly, it is considered that a holding electric power can be decreased down to several µW (several µA x 1.5V) per one element of the pnpn thyristor. As a matter of course, if the size thereof is decreased less than the aforementioned size of 100 µm x100µm, the electric power will be proportionally low. In the above described situation in which ON state is held in the pnpn thyristor by the intermittent pulses 313, a set pulse 312 is applied to the anode and cathode electrodes 46 and 43 thereof without supplying trigger light to the pnpn thyristor (FIGS, 6A and 6B) so that light emission and current flowing response are obtained (FIGS. 6C and 6D). In this case, a current flowing response time is less than 1 ns, while a time during which light output is increased from zero to a normal value is approximately 20 ns. This is a reason why a response time of light output depends on a light emission recombination life of injected carriers. Here, a feature of the invention will be summarized as follows. Although an optical pnpn thyristor is turned on to provide light emission by a positive bias voltage applied across an anode and cathode electrodes thereof and trigger light supplied thereto, the light emission is ceased and an information of a fact that light is supplied thereto is erased when the bias voltage is turned off. For this reason, the positive bias voltage is kept to be applied across the anode and cathode electrodes thereof so that the information is stored therein. On the other hand, the inventors found in their experiment that ON state is held in a pnpn thyristor for a minute time even if a bias voltage is turned off. In such a pnpn thyristor, it is necessary to expel excess carriers from three forward biased pn junctions thereby restoring a high impedance state from a low impedance state as shown in Figs. 7A to 7C. Even if a bias voltage is dropped down to zero before completing the restoration of a high impedance state, the low impedance state is held. In the experiment, it is confirmed that a time during which the low impedance state is held under no bias voltage is several hundreds ns to several tens µs. It is further confirmed that if a train of positive intermittent pulses having a pulse interval less than the aforementioned period are applied across the anode and cathode electrodes to intermittently inject a small amount of carriers which are necessary to maintain the low impedance state, the low impedance state is held. As a result, the process for controlling the pnpn thyristor to be driven as described above provides an extremely less electric power consumption as compared to a conventional one. Next, a process for controlling an optical pnpn thyristor to be driven in a second embodiment according to the invention will be explained wherein the same pnpn thyristor as shown in Fig. 4 is used. Before describing the second embodiment, it is explained as shown in Fig. 8 that ON state holding time on the horizontal axis is linearly proportional to a bias voltage on the vertical axis which is less than a holding voltage V h . Accordingly, a bias voltage V b1 less than a peak value of intermittent pulses 313 is constantly applied, as shown in Fig. 9A, across an anode and cathode electrodes of an optical pnpn thyristor which is turned on to be in a low impedance state by a set pulse 311, which is kept to remain in the low impedance state by the intermittent pulses 313, and which is again turned on to emit light for the reading of information stored therein by a set pulse 312. The ON holding time can be as long as 25µs in a case where a bias voltage V b1 (=1.2V) is applied so that a repetition frequency of the intermittent pulses 313 can be lowered as clearly understood from the comparison between Figs. 6A and 9A. Finally, a high speed turning off (erasing) process of an optical pnpn thyristor will be explained in Fig. 10. For the purpose, it is known that a negative reset pulse is applied across the anode and cathode electrodes of the pnpn thyristor. In Figs.4 and 10, the n and p-gate electrodes are provided wherein a resistance 60 of 10kΩ is connected between the n-gate electrode 51 and the ground, and a Shottky diode 61 (for instance, 15512M of NEC Corporation) is connected between the anode electrode 50 and the p-gate electrode 52, provided that a resistance 62 connected between the cathode electrode 49 and the ground is a series resistance for adjusting a value of current which flows during ON state of the pnpn thyristor. In the provision of the resistance 60, a switching voltage V s is decreased from 6.2V to 2.4V for the reason why electrons are injected through the resistance 60 into the n-gate layer. A high speed erasing of ON state can be realized in the presence of a bypass for pulling out excess carriers at a time of resetting the pnpn thyristor. As described above, the invention relates to a process for controlling an optical pnpn thyristor which is applicable to an image processing, an optical logic calculation etc. wherein ON state of the pnpn thyristor is held by applying intermittent pulses with a predetermined pulse interval after an optical information is written into the pnpn thyristor. In the circumstance, a set pulse is applied to the pnpn thyristor only when light emission is required to read the optical information therefrom. As a result, electric power is prevented from being consumed more than necessary in a time storing the optical information so that an optical memory with less electric power consumption can be realized for the first time. In a case where the invention is applied to an optical pnpn thyristor matrix and a process for controlling the pnpn thyristor matrix to be driven, a processing of a stored image data, a pattern discrimination etc. in which an enormous processing time is consumed in a presently used digital computer can be performed with a short processing time.

Claims: A method of controlling an optical pnpn thyristor, the thyristor including an anode region (33) of p-semiconductor, a cathode region (36) of n-semiconductor, and a plurality of semiconductor layers (34,35) sandwiched between the anode and cathode regions, characterised by the steps of shifting the thyristor from a high impedance state to a low impedance state to provide light emission by applying a first positive set pulse of voltage (311) across its anode and cathode, applying a train of intermittent voltage pulses (313) across the anode and cathode, each of these pulses being less in its level than the first positive set pulse of voltage so that the low impedance state of the optical pnpn thyristor is held without light emission, and applying a second positive set pulse of voltage (312) across the anode and cathode of the optical pnpn thyristor, which is held in the low impedance state to provide light emission. A method according to claim 1, further characterised by the step of applying a positive bias voltage (Vb1) less in its level than the said train of voltage pulses (313) across the anode and cathode of the optical pnpn thyristor, the thyristor being shifted to be in the low impedance state by the first positive set pulse of voltage (311).

Inventors: KASAHARA, KENICHI C/O NEC CORPORATION, TASHIRO, YOSHIHARU C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1988
Main classification: H01L33
IPC codes: H03K19, G02F3, H01L29, G11C7, G11C11, H01L33, G02F1, H01L31, H03K17