SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED CELL ARRANGEMENT

Abstract: A semiconductor memory device provided with the improved cell arrangement is disclosed. The memory device includes at least one memory cell array having a plurality of 1 transistor - 1 capacitor type memory cells arranged in rows and columns (Y₁-Y n ) and is featured in that the capacitors of the memory cells in the two outer columns (Y₁, Y n ) have a large capacitance as compared to the capacitors of the memory cells in the inner columns (Y₂-Y n-1 ) other than the two outer columns (Y₁, Y n ).

Description: BACKGROUND OF THE INVENTION: The present invention relates to a semiconductor memory device fabricated on a semiconductor substrate and more particularly to a dynamic type semiconductor memory device employing one transistor-one capacitor type memory cells. A dynamic semiconductor memory device is structured such that at least one memory cell array is provided near a central zone of a semiconductor chip and peripheral circuits such as an address buffer/decoder and a data input/output circuit are arranged in a peripheral zone of the central zone of the semiconductor chip. The dynamic type semiconductor memory device thus arranged is responsive to address signals and control signals to write or read data informations into or from the memory cell array. In write or read operation, the peripheral circuits are enabled, so that electric charges from the peripheral circuits flow into the memory cell array area of the semiconductor chip. The information are stored in the form of electric charges in storage capacitors of the memory cells. Thus, the data information is liable to be affected by the electric charges come from the peripheral circuits. Moreover, in view of formation of the memory cell array, particularly, the uniformity of the memory cell array, for example that of insulating layer in the memory cell array is generally decreased near the peripheral portion of the memory cell array. For example, the deviation in thickness of the insulating layer from a desired value is relatively small in the central portion of the memory cell array while the deviation in thickness of the insulating layer from the desired value is relatively large in the peripheral portion of the memory cell array. Thus, there is tendency that electrical characteristics of elements in the side portions of the memory cell array cannot satisfy the required provisions. Thus, in the worst case, data information stored in the memory cells in the peripheral or outer portion of the memory cell array is destroyed or inverted in logic levels. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a dynamic type semiconductor memory device having an improved memory cell array whose outer region cells are free from data destruction. The semiconductor memory device according to the present invention is specified in claim 1. It comprises at least one memory cell array having a plurality of memory cells arranged in rows and columns, and a peripheral circuit arranged outside the memory cell array for achieving a read or write operation with respect to a selected memory cell, and is featured in that each of the storage capacitors of the memory cells in the two outer columns has a larger dimension or capacitance than the storage capacitors of the memory cells in the inner columns other than the two outer columns. According to the present invention, the storage capacitors of the memory cells in the outer columns have the increased value of capacitances and therefore they are hardly affected by electric charges or noises from the outside of the memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a plan view showing a general layout of a semiconductor memory device; Fig. 2 is a schematic block diagram of a cell array with peripheral circuits; Fig. 3 is a schematic circuit diagram of a dynamic memory cell; Fig. 4 is a plan view showing patterns of memory cells according to a prior art; Fig. 5 is a plan view showing patterns of memory cells according to a first embodiment of the present invention; Fig. 6 is a sectional view along the axis A-A′ of Fig. 5; Fig. 7 is a plan view showing patterns of memory cells according to a second embodiment of the present invention; and Fig. 8 is a drawing explaining the effect of the invention. DETAILED DESCRIPTION OF THE INVENTION: First, referring to Figs. 1 to 4, a memory device according to a prior art will be explained. A general arrangement of memory cells in a dynamic memory device is show in Fig. 1. A large number of memory cells are grouped into, in this case, 8 memory arrays 10-1 to 10-8 formed on a semiconductor chip 1. For example, in the case where the total memory capacity of the memory device is 256 k-bits, each of the memory array 10-1 to 10-8 includes 32 k-bits of memory cells. Although, not indicated in Fig. 1, the peripheral circuits such as row (X) decoders, column decoders are arranged outsides of the respective memory arrays. The number of the memory arrays is optional and determined according to design choice. The general structure of each memory array 10-i and its peripheral circuits are shown in Fig. 2. The memory array 10-i (1 ≦ i ≦ 8) includes a plurality of word lines WL arranged in rows, a plurality of pairs of bit lines DL, DL arranged in columns and a plurality of memory cells MC coupled to the word lines WL and the bit lines in a known way. A plurality of sense amplifiers 4 are provided for the respective columns and connected to the pair of bit lines of that column. A row (X) decoder 2 is coupled to the word lines WL. A pair of bus lines I/O and I/O are coupled to the respective pairs of bit lines DL, DL via a plurality of pairs of transfer gates TF, TF which are selected by outputs Y o - Y n of a column (Y) decoder 3 in a known way. A circuit structure of the memory cells MC is shown in Fig. 3. Each of the memory cells MC includes a memory cell transistor Q M and a storage capacitor C M connected in series between the bit line DL and a fixed potential such as a ground potential. A pattern of a part of the memory array 10-i according to a prior art is shown in Fig. 4. The bit line DL of the outer, side column, e.g. that selected by the column selection output Y₁ (column of Y₁) and the bit line DL of the inner side column e.g. that selected by Y₁ (column of Y₁) are representatively shown in Fig. 4. The bit lines DL, DL are made of aluminum strips extending in column direction and the word lines are made of polycrystalline silicon extending in row direction. N-type regions 11 formed in a P-type substrate 9 serve as one electrodes of the capacitors C M . N-type regions 8 are connected to the bit lines DL, DL via contact holes 7. Between the N-type regions 11 and 8, charge transfer regions are defined. A polycrystalline silicon layer 6 is covered the substrate via an insulating layer (not shown) at least above the N-type regions 11 except for the contacts and the charge transfer regions. The polycrystalline silicon layer 6 serves as the other, opposite electrodes of the cell capacitors C M . As is seen from Fig. 4, all the capacitors C M in the respective memory arrays 10-i have the same configuration and the same size. In particular, the configuration and the size of the respective N-type regions 11 are the same throughout the each memory array 10-i. Since the peripheral circuits such as decoders, and sense amplifiers operatively discharge a relatively large amount of electric charges and some part of the discharged charges leak to the memory cell capacitor C M to reduce electric charges stored therein. Moreover, the capacitors C M in the periphery side column have deviations in the electric characteristics due to the deviations in forming the N-type regions 11 and the insulating layer thereof and therefore such capacitors in the periphery side column have less ideal characteristics, e.g. smaller capacitance values. Accordingly, in the conventional semiconductor memory device, the states of the memory cell capacitors C M in the outer, side columns, i.e. the columns of Y₁ and Y n are liable to be affected by the peripheral circuits and is less reliable. With reference to Figs. 5 and 6, a part of the memory array according to one embodiment of the present invention will be explained. In Figs. 5 and 6, the portions corresponding to those of Fig. 4 are denoted by the same or similar reference numerals. The present embodiment is obtained by enlarging the area of the N-type regions 11 of only the periphery side columns of Y₁ and Y n in Fig. 4 to form enlarged N-type regions 11′ as the one electrodes of the memory cell capacitors, as illustrated in Fig. 5. While the N-type regions 11 of the columns Y₂ - Y n-1 which are inner columns, have the same size as those 11 in Fig. 4. In particular, the width W B of the N-type regions 11′ is made larger than the width W A of the N-type regions 11 while the length L B of the N-type regions 11′ are made equal to the length L A of the N-type regions 11. This is because the number of the memory cells arranged in the respective columns of Y₁ - Y n must be the same and the memory cells must be arranged in accordance with the arrangement of the word lines in the respective columns, while it is allowed to enlarge the width W B of the N-type regions 11′ of the periphery side columns of Y₁ and Y₂ without disturbing the whole memory cell arrangement in the respective arrays. Assuming that the respective area or capacitance of the capacitors C M of the side columns Y₁ and Y n is C B and the area or capacitance of the capacitors C M of the inner columns of Y₂ - Y n-1 is C A , the area ratio C B /C A is favorably set at 1.2 to 2. Namely, normalized soft error rate of the memory cells in the side column with respect to the ratio of C B /C A in Fig. 8. In Fig. 8, EN indicates the error rate of the memory cells of the inner columns. As is shown in Fig. 8, the error rate is not significantly improved between 1 to 1.2 of C B /C A . But the error rate is improved from 1.2 of C B /C A and becomes the same error rate as EN around 1.5 of C B /C A . Then, the error rate is gradually improved after 1.5 of C B /C A . In the case of C B /C A of less than 1.2, the effect against the charges is not sufficient. While in the case of C B /C A of more than 2, it is not practical to arrange a large number of memory cells in the respective memory arrays with high-density structure. In particular, the above ratio C B /C A is achieved favorably by setting the ratio of W B /W A at 1.2 to 2 in the case of the same value of L A and L B with case. According to the present invention, the capacitance of the memory cell capacitors C M of the side columns of Y₁ and Y n is made increased, and therefore electric charges stored in the capacitors in the periphery columns Y₁ and Y n are also increased. Therefore, even when the electric charges flow into the capacitors in the periphery columns of Y₁ and Y n , the states of the capacitors in the periphery columns of Y₁ and Y n are hard to be affected. Referring to Fig. 7, the side part of the memory array according to a second embodiment will be explained. This embodiment is featured in that the enlarged N-type regions 11″ have a symmetrical pattern with respect to the respective bit lines DL and DL of the periphery columns of Y₁ and Y n . Namely, the pitch of the pair of bit lines DL and DL of the periphery columns (Y₁, Y n ) is set the same as that of the pair of bit lines DL and DL in the inner columns Y₂ - Y n-1 , and only one half width W C of the regions 11″, which are outside the pair of bit lines DL and DL in the periphery columns of Y₁ and Y n is enlarged. This embodiment is advantageous in keeping the pitch of the pair of bit lines DL and DL throughout the memory array. As has been explained, the present invention effectively reduces the affect of electric charges or noise to the memory array and can provide the improved semiconductor memory device operable stably.

Claims: A semiconductor memory device comprising at least one memory array (10-i) having a plurality of memory cells (MC) arranged in rows and columns, each of said memory cells (MC) including a storage capacitor (CM) and a field effect transistor (QM), characterized in that the storage capacitors of the memory cells in the inner columns (Y2,...,Yn-1) other than two outer columns (Y1, Yn) along the both peripheries of said array in columns have a first capacitance and the storage capacitors of the memory cells in said two outer columns (Y1, Yn) have a second capacitance larger than said first capacitance. The semiconductor memory device according to claim 1, characterized in that a ratio of said second capacitance to said first capacitance is within a range of 1.2 to 2. The semiconductor memory device according to claim 1, characterized in that a plurality of word lines (WL) are arranged in said rows and a plurality of bit lines (DL, DL ) are arranged in said columns in said memory array. The semiconductor memory device according to claim 1, characterized in that said second capacitors have width (WB) larger than that (WA) of said first capacitors in direction of said rows.

Inventors: KAWATA, KOUJI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1988
Main classification: G11C11
IPC codes: H01L27, G11C11, H01L21