Stacked metal-insulator semiconductor device

Abstract: A stacked MIS device is comprised of a semiconductor substrate of one conductivity type, a first pair of source and drain regions of the other conductivity type formed in the semiconductor substrate in spaced relation from each other to define therebetween a first channel region, a gate electrode disposed on the first channel region through a gate insulating film so as to extend transversely of the first channel region, a semiconductor film of the conductivity type disposed along the gate electrode through another gate insulating film, and a second pair of source and drain regions of the one conductivity type formed in the semiconductor film in spaced relation from each other to define therebetween a second channel region, the length of second channel region being arranged to intersect with that of the first channel region.

Description: The present invention relates to semiconductor devices composed of field effect transistors (hereinafter referred to as FET) of metal-insulator semiconductors (hereinafter referred to as MIS) stacked on one another, and in the preferred embodiment relates to stacked MIS devices composed of a pair of N-type MIS-FET and P-type MIS-FET stacked to each other with a common gate electrode. This type of stacked MIS device has been used in memory cells such as static random access memory (hereinafter referred to as SRAM), which need high integration density. Figs. 2(a), 2(b) and 2(c) illustrate one example of a conventional stacked MIS device in which the device is formed as an inverter circuit. Fig. 2(a) is a circuit diagram of an inverter using P- and N-type MIS-FET's, Fig. 2(b) is a schematic plan view of a conventional stacked MIS device, and Fig. 2(c) is a schematic sectional view taken along line D-D of Fig. 2(b). In Fig. 2(a), numeral 1 refers to a power terminal held at a potential level of a power supply and numeral 2 refers a grounding terminal held at a grounding potential. A P-type MIS-FET 5 and an N-type MIS-FET 6 are serially connected between the power terminal 1 and the grounding terminal 2. The gate electrodes of those MIS-FET'S 5 and 6 are commonly connected to an input terminal 4. Similarly, their drain electrodes are commonly connected to an output terminal 3. An input signal applied to the input terminal 3 is inverted by the FET'S 5 and 6 to be derived at the output terminal 4. For such inverting operation, the gate electrodes of both FET'S 5 and 6 are supplied with the same input signal through the input terminal 3. Therefore, it is better to form the gate electrodes of both FET'S 5 and 6 with a single conductive layer having a single region which operates as both gate electrodes. For realizing such gate structure, a stacked MIS device has been devised. Fig. 2(b) is a schematic plan view of this conventional stacked MIS device, and Fig. 2(c) is a schematic sectional view of the same taken along line D-D of Fig. 2(b). In these figures, an N-type source region 32 and an N-type drain region 33 of the N-type, MIS-FET 6 are formed in a P-type semiconductor substrate 31 such as Si. A gate insulating film 34 is formed on the semiconductor substrate 31 between the source and drain regions 32 and 33 and a gate electrode 35 is formed on the gate insulating film 34 to thereby constitute the N-type MIS-FET 6. Further, another gate insulating film 36 is formed on the gate electrode 35 and an N-type semiconductor film 39 such as polycrystalline Si is formed on the gate insulating film 36. Thereafter, a P-type source region 37 and a P-type drain region 38 are formed in the semiconductor film 39 to thereby constitute a P-type MIS-FET 5 together with the aforementioned gate electrode 35. However, in the above described stacked MIS device of the conventional type, the source and drain regions 32 and 33 of N-type MIS-FET 6 are aligned along the common gate electrode 35 in the same direction as those of source and drain regions 37 and 38 of P-type MIS-FET 5. Therefore, when the channel length of the N-type MIS-FET 6 is to be reduced, the channel length of the P-type MIS-FET 5 is correspondingly needed to be reduced. However, when reducing the dimensions of MIS-FETS in order to increase the integration density of the device, the lower MIS-FET 6 may have different limit in reducing its dimension than that of the upper MIS-FET 5. In such case, the possible reduction of dimension is determined by the critical limit of one MIS-FET which is greater than the dimensional limit of the other MIS-FET. Namely, in such case that the upper P-type MIS-FET 5 is. composed of a semiconductor film made of a poly-crystalline silicon or made by re-crystalization of the poly-crystalline silicon, which has a considerable limit in reducing the dimension thereof, the channel length of the lower N-type MIS-FET 6 must be reduced in registration with that of the upper MIS-FET 5. In order to improve the performance of inverter circuit as shown, for example, in Fig. 2(a), it is desirable to reduce the channel length of N-type MIS-FET 6. However, as described above, the possible minimum channel length of N-type MIS-FET 6 is controlled by greater minimum channel length of P-type MIS-FET 5, thereby failing to improve the total performance of the device. Japanese specification A-58.087.859 (Patent Abstracts of Japan, Vol. 7, No. 182) discloses a stacked device wherein the upper and lower transistors are arranged orthogonally. According to the present invention, there is provided a semiconductor device as defined in claim 1. A preferred embodiment of the invention will be described by way of example with reference to Fig. 1 of the accompanying drawings, wherein Fig. 1(a) is a schematic plan view of a stacked MIS device according to a preferred embodiment of the present invention, and Fig. 1(b) is a schematic sectional view taken along line C-C of Fig. 1(a). A source region 22 and drain region 23 of an N-type MIS-FET are formed in a P-type silicon semiconductor substrate 21 to define a channel section therebetween. A first gate insulating film 24 is formed over the source and drain regions 22, 23. A gate electrode 25 is disposed over the channel between the source region 22 and drain region 23 upon the insulating film 24, and extends transversely of the channel. The channel is oriented with its length along a first direction joining the source and drain 22,23 and with its width orthogonal thereto. A semiconductor film 29 is formed along the gate electrode 25 on another gate insulating film 26 which covers the gate electrode 25. Another pair of source and drain regions 27 and 28 of a P-type MIS-FET transistor are formed in the semiconductor film 29 in spaced relation from each other in a second direction transverse to the length of the channel between the source and drain regions 22 and 23. In addition, the semiconductor film 29 is formed into an "I"-shape so as to avoid the source and drain regions 27 and 28 of the P-type MIS-FET transistor from overlapping the source and drain regions 22 and 23 of the N-type MIS-FET transistor. Thus, the source and drain regions 27 and 28 are formed in the opposite end portions of "I"-shape semiconductor film 29. A channel is thus formed between the source and drain regions 27 and 28 with its length disposed orthogonally to the length of the channel between the source and drain 22,23. As can be seen from Figure 1(b) the width of the channel of the P-type transistor is less than the length of the channel of the N-type transistor. Further, the width of the channel of the P-type transistor is less than its length. As described above, the length of channel between the source and drain regions of one conductive type MIS-FET formed on a semiconductor substrate is arranged orthogonally to the length of channel between the source and drain regions of the opposite conductive type MIS-FET transistor formed in a semiconductor film disposed on the one conductive type MIS-FET. Therefore, the respective channel lengths of the one conductive type MIS-FET and the opposite conductive type MIS-FET may be set relatively independently of each other compared to the device of Figure 2. Thus, the channel length of the upper P-type MIS-FET can be set without regard to the channel length of the lower N-type MIS-FET. Further, since the channel width of the upper P-type MIS-FET is less than the channel length of the lower N-type MIS-FET, the reduction of the N-type MIS-FET channel length may affect the characteristics of the P-type MIS-FET such as its withstand voltage. However, the leak current of the P-type MIS-FET can be reduced. Consequently, when this type of stacked MIS-FET is applied to a SRAM circuit, the reduction of leak current, which is a more significant factor than degradation of the P-type MIS-FET performance, can be achieved to benefit the design of this type of circuit. Although, the channel length of the lower N-type MIS-FET transistor may not be reduced to a minimum, the source and drain regions of the upper P-type MIS-FET do not overlap with the source and drain regions of the lower N-type MIS-FET transistor, respectively. The electrostatic capacitance is thereby eliminated between the upper source and drain regions 27 and 28 and the lower source and drain regions 22 and 23.

Claims: A semiconductor device comprising a semiconductor substrate (21); a first field effect transistor having first source and drain regions (22,23) formed in said semiconductor substrate and aligned in a first direction to define a first channel region therebetween in said semiconductor substrate, the first channel region having a predetermined length in said first direction and a predetermined width in a second direction orthogonal to said first direction, said width being greater than said length, and a gate electrode (25) formed between said first source and drain regions (22,23) and located over said first channel region and spaced from said first channel region by a first gate insulating film (24), a semiconductor layer (29) formed over said gate electrode on a second gate insulating film (26) which covers said gate electrode (25), a second field effect transistor having second source and drain regions (27,28) formed in said semiconductor layer (29) on both sides of said gate electrode so as to align in said second direction to define a second channel region therebetween, said gate electrode being common to said first and second field effect transistors, characterised in that the width of the second channel region in said first direction is less than the length of the first channel region in said first direction, and in that said semiconductor layer is formed in an I-shape, said second source and drain regions (27,28) being formed in respective end portions of the I-shape so as to prevent the second source and drain regions from overlapping with the first source and drain regions (22,23).

Inventors: OKAZAWA TAKESHI, OKAZAWA, TAKESHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21