Interface circuit between "or-tied" connection of a PLA device and a TTL output buffer

Abstract: An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circuit (42), and a sensing circuit (26). The first bandgap generator (40) generates a first reference voltage (VB1) which has a positive temperature coefficient. The second bandgap generator (42) generates a second reference voltage (VB2) which has a negative temperature coefficient. A resultant base drive current (I x ) is supplied to the base of a phase splitter transistor (Q2) in the output buffer (36). The resultant current (I x ) is controlled by the first and second bandgap generators (40, 42), the current being higher at low temperatures and being smaller at high temperatures.

Description: This invention relates generally to programmable logic array (PLA) devices and more particularly, it relates to an interface circuit for interfacing between the "OR-Tied" connection of a PLA device and the phase splitter transistor of a TTL output buffer so as to provide a high speed of operation over a wide range of temperature variations. As is generally known, arrays for performing logic functions are typically referred to as logic arrays or programmable logic arrays (PLAs) and have been used in recent years to replace random logic in many digital circuits. Such programmable logic arrays are especially useful in the control section of digital systems and are frequently thought of as read-only storage, read-only memories, or the like. The programmable logic array is a well known conventional way of using arrays of identical circuit elements to implement arbitrary logic function in integrated circuits. A simplified schematic circuit diagram of a TTL programmable logic array device 10 with a Schottky diode array structure 12 of the prior art is shown in Figure 1 and has been labeled "Prior Art." One of the major problems experienced in this prior art PLA device 10 is that extra propagation delays are encountered due to the double inversion in the buffer 34 having the two inverter stages. This buffer stage is required to properly interface the "OR-tied" to the output buffer and provide necessary level and drive to the output stage 36 over operating temperature range. The interface circuit 110 of Figure 2 for use between the "OR-tied" connection of a PLA device and the phase splitter transistor of a TTL output buffer is an improvement over the one of Figure 1 and exhibits a high speed of operation over a wide range of temperature variations. This is achieved by the elimination of the buffer 34 having the two inverter stages so that the output of the sensing circuit 26 is connected directly to the phase splitter transistor Q2 of the output buffer 36. Since the beta (current gain) of the phase splitter transistor Q2 will increase with temperature, a smaller current drive is required at the higher temperatures. Two independent bandgap generators with opposite temperature coefficients are provided so as to generate a resultant base drive current to the phase splitter transistor Q2 which is greater at the lower temperature of -55°C and is less at the high temperature of +155°C, thereby maintaining a high switching speed over the temperature range. Accordingly, there is described an improved interface circuit which overcomes the disadvantages of the prior art, and which has a high speed of operation over wide range of temperature variations. There is also described an interface circuit for interfacing between the "OR-TIED" connection of a PLA device and the phase splitter transistor of a TTL output buffer which eliminates the need of a buffer having two inverter stages so as to reduce propagation delays. The interface circuit includes two independent bandgap generators with opposite temperature coefficients so as to generate a resultant base drive current to a phase splitter transistor that is greater at low temperatures and is less at higher temperatures. More particularly, there is provided an interface circuit for interfacing between an "OR-tied" connection of a programmable logic array and a TTL output buffer, the output buffer having a phase splitter transistor responsive to the voltage at the connection such that the transistor receives base drive current only when the array is in a first logic state and the voltage at the connection is above a predetermined threshold value, the interface circuit comprising: first means for supplying a first current to the logic array to determine the voltage at the connection when the array is in its first logic state; and second means providing a second current to determine the threshold voltage at which the base drive current to the transistor is cut off when the array switches from its first logic state to a second logic state, the magnitude of the base drive current with the array in its first logic state being dependent on the magnitude of the second current and the voltage at the connection, characterised in that the first and second currents are dependent on respective first and second reference voltages having opposite polarity temperature coefficients whereby the base drive current to the phase splitter transistor decreases with increasing temperature to maintain the switching speed of the output buffer substantially constant over a predetermined range of temperature. In the accompanying drawings, by way of example only: Figure 1 is a simplified schematic circuit diagram of a TTL programmable logic array device with a Schottky diode array structure of the prior art; Figure 2 is a schematic circuit diagram of an interface circuit of the present invention; Figure 3 is a schematic circuit diagram of an output section of the conventional input buffers of Figure 2; Figure 4 is a schematic circuit diagram of a conventional high level clamp circuit of Figure 2; Figure 5 is a schematic circuit diagram illustrating an implementation of the bandgap generators; Figure 6 are plots showing the operating characteristics of the reference voltages VB1 and VB2 of the bandgap generators over the temperature range; and Figure 7 are plots of the high level voltage V H , low level voltage V L and the threshold level voltage V TH showing its operating characteristics over the temperature range. Referring now to the drawings, there is shown in Figure 1 a simplified schematic circuit diagram of a TTL programmable logic array device 10 with a Schottky diode array structure 12 of the prior art. The prior art PLA device 10 includes a plurality of input buffers 14a...14n. Input logic signals 16a...16n on respective input terminals 18a...18n are connected to the corresponding inputs of the plurality of input buffers 14a...14n. The input buffers are standard circuits which buffer the input logic signals as well as to provide inverted output signals on lines 20a...20n. The output of the input buffer 14a on the line 20a is connected to the cathodes of Schottky diodes SDA1 ... SDAn . The respective anodes of the Schottky diodes SDA1 ... SDAn are connected to one end of corresponding blowable fuses F1 ... Fn . The other end of the fuses F1 ... Fn are connected to corresponding common nodes A1...An. Similarly, the output of the input buffer 14n on the line 20n is connected to the cathodes of Schottky diodes SDA1 ... SDAn . The anodes of the Schottky diodes SDA1 ... SDAn are connected to one end of corresponding blowable fuses F1 ... Fn . The other ends of the fuses F1 ... Fn are connected to the respective common nodes A1...An. The PLA device 10 further includes a plurality of input buffers 22a...22n for generating non-inverted output signals on lines 24a...24n. The input buffer 22a has its input connected to the output of the input buffer 14a and its output on the line 24a connected to the cathodes of the Schottky diodes SDA1...SDAn. The respective anodes of the Schottky diodes SDA1...SDAn are connected to one end of corresponding blowable fuses F1...Fn. The other ends of the respective fuses F1...Fn are connected to the corresponding common nodes A1...An. Similarly, the input buffer 22n has its input connected to the output of the input buffer 14n and its output on the line 24n connected to the cathodes of Schottky diodes SDA1...SDAn. The respective anodes of the Schottky diodes SDA1...SDAn are connected to one end of corresponding blowable fuses F1...Fn. The other ends of the respective fuses F1...Fn are connected to the corresponding common nodes A1...An. Each of the common nodes A1...An are coupled via Schottky diodes SDA1 to the bases of the respective transistors Q1a...Q1n and also to the programming circuit (not shown) which provides the capability to blow fuses. The collectors of the transistors Q1a...Q1n are connected to a supply voltage or potential VCC, which is typically at +5.0 volts. The emitters of the transistors Q1a...Q1n are all connected together to a common node or point P which is commonly referred to as an "OR-tied" connection. The node or point P is also fed to an input of the sensing circuit 26. The current I₂ in the sensing circuit 26 is controlled by a voltage VB1 having a positive temperature coefficient from a bandgap generator 28. The voltage VB1 is also used to control the current I₁ in a high level clamp circuit 30. The output of the sensing circuit 26 on line 32 is fed to a buffer 34 having two inverter stages to properly interface and provide current driving capability to a TTL output buffer 36. Figure 2 is a schematic circuit diagram of an interface circuit 110 of the present invention for interfacing between the "OR-tied" connection of the PLA device 10 and the phase splitter transistor Q2 of the TTL output buffer 36. The circuit of Figure 2 represents an improvement over the circuit of Figure 1 and has a high speed of operation wide a wide range of temperature variations. As can be seen from comparing Figures 1 and 2, the interface circuit 110 interconnected between the device 10 and the output buffer 36 does not include the buffer 34 (Figure 1) with its two inverter stages. As a result, the output of the sensing circuit 26 on the line 32 is connected directly to the base of the phase splitter transistor Q2 of the output buffer 36. Further, the interface circuit 110 includes a first bandgap generator 40 which has a positive temperature coefficient and is similar to the bandgap generator 28 of Figure 1 and a second bandgap generator 42 which has a negative temperature coefficient. Consequently, a resultant drive current I x is created at the base of the phase splitter transistor Q2 which is higher at low temperatures and is lower at high temperatures, thereby maintaining a substantially constant switching speed over the temperature range of -55°C and +155°C. The bandgap generator 40 has an output on line 44 which provides a first reference voltage VB1 and is fed to the input of the high level clamp circuit 30. The first reference voltage VB1 having a positive temperature coefficient is plotted at its curve A in Figure 6 as a function of temperature. The bandgap generator 42 has an output on line 46 which provides a second reference voltage VB2 and is fed to the input of the sensing circuit 26. The second reference voltage VB2 having a negative temperature coefficient is plotted as curve B in Figure 6 as a function of temperature. A conventional schematic circuit diagram of the bandgap generator 40(42) is illustrated in Figure 5. The bandgap generator 40(42) is formed of transistors Q11-Q18 and resistors R11-R17. It should be apparent to those skilled in the art that the physical sizes of the various transistors Q11-Q18 and the particular resistance values of the various resistors R11-R17 can be properly designed so as to generate either the first reference voltage VB1 having the positive temperature coefficient or the second reference voltage VB2 having the negative temperature coefficient. The first reference voltage VB1 on the line 42 is used to control a current I₁ which flows in the high level clamp circuit 30 and thus sets the high level clamp voltage V HLC at its output on line 48. A conventional schematic circuit diagram of the high level clamp circuit 30 is depicted in Figure 4. The high level clamp circuit 30 is formed of transistors Q19-Q22, QH1, QH2 and resistors R1, R3-R6. Since the first reference voltage VB1 has a positive temperature coefficient, the current I₁ flowing through the transistor Q19 will therefore decrease with increasing temperatures. Due to the current mirror arrangement, this same current I₁ is reflected and flows through the transistor Q20. Thus, the high level clamp voltage V HLC can be expressed mathematically as follows: V HLC = I₁ (R1) + V BE(QH1) + V BE(QH2) where: I₁ = current flowing through resistor R1 V BE(QH1) = base-emitter voltage across transistor QH1 V BE(QH2) = base-emitter voltage across transistor QH2 Accordingly equation (1) can be simplified to: V HLC = I₁R1 + 2V BE The second reference voltage VB2 on the line 46 is used to control I₂ which flows in the sensing circuit 26. Since the second reference voltage VB2 has a negative temperature coefficient, the current I₂ flowing through the transistor Q23 will therefore increase with increasing temperatures. Due to the current mirror arrangement, this same current I₂ is reflected and flows through the transistor Q24. Each of the standard input buffers 14a...14n and 22a...22n includes a conventional output section 50 which is illustrated in a schematic circuit diagram form in Figure 3. As can be seen, the output section 50 includes a Schottky transistor QI1, a bipolar transistor QI2 and a Schottky diode DSI1. The cathode of the diode DSI1 defines either the output of the respective input buffer 14a...14n to provide the inverted signals on the lines 20a...20n or the output of the respective input buffers 22a...22n to provide the non-inverted signals on the lines 24a...24n. Now, the operation of the interface circuit 110 of this invention constructed as described above will be explained with reference to the voltage swing occurring at the common node or point P, which is the "OR-tied" connection. The low level voltage V L at the point P is determined by the output section 50 of the input buffer shown in Figure 3 and is expressed as follows: V L = -V BE(Q1) + V SD1 + V SDA + (-V DSI1 +V BE(QI2) + V BE(QI1) ) where: V BE(Q1) = base-emitter voltage across transistor Q1 V SD1 = voltage drop across Schottky diode SD1 V SDA = voltage drop across array Schottky diode SDA V DSI1 = voltage drop across Schottky diode DSI V BE(QI2) = base-emitter voltage across transistor QI2 V BE(QI1) = base-emitter voltage across transistor QI1 By designing the Schottky diode DSI in the output section 50 of the input buffer to be of the same type as the array Schottky SDA or SDA , equation (3) can be simplified to: V L ≃ V BE + V SD The high level voltage V H is a function of the current I₁ at the point P and is determined by the high level clamp circuit 30 shown in Figure 4 and is given by: V H = V HLC + V SD2 - V BE(Q1) where: V SD2 = voltage drop across diode SD2 V BE(Q1) = base-emitter voltage across transistor Q1 By substituting for V HLC from equation (1) into the above equation, there is given: V H = (I₁R1 + V BE(QH1) + V BE(QH2) ) + V SD2 - V BE(Q1) This can be simplified to: V H = V BE + V SD + I₁R1 The voltage swing V SW between the high level voltage V H and the low level voltage V L is obtained by subtracting equation (4) from equation (7), or: V SW = V H - V L = I₁R1 When the point P is at the high level voltage V H , the amount of resultant current I x on the line 32 flowing into the base of the phase splitter transistor Q2 in the output buffer 36 can be expressed approximately as follows: I x = I T - I₂ where: I T = total current which flows through resistor R2 I₂ = current flowing through transistor Q24 Further, the total current I T is determined by the voltage across the resistor R2 divided by the resistance value of the resistor R2 and can be stated to be: I T = V H - V BE(Q2) - V BE(Q3) R2 = V H - 2V BE R2 where: V BE(Q2) = base-emitter voltage across transistor Q2 V BE(Q3) = base-emitter voltage across transistor Q3 By substituting V H from equation (7) into equation (10), there is given: I T = (V BE + V SD + I₁RI) - 2V BE R2 = V SD - V BE + I₁R1 R2 By inserting equation (11) for the total current I T into equation (9), the resultant current I x is determined to be: I x = V SD - V BE + I₁R1 R2 - I₂ This resultant current I x is very critical in determining the switching speed of the phase splitter transistor Q2 and thus the switching speed of the pulldown output transistor Q3. As is known, the beta (current gain) of the transistors will be lower at cold temperatures (i.e., -55°C) and will be higher at hot temperatures (i.e., +155°C). Since the current gain of the phase splitter transistor Q2 will be lower at the cold temperatures, a larger current drive is required in order to quickly turn on the transistor Q2. However, a smaller current drive is necessary at the higher temperatures due to the increasing beta with respect to temperature so as to prevent excessive base drive which causes the transistor Q2 to saturate, thereby increasing its turn-off time. As can be seen from the above equation (12), the resultant base drive current I x has been shown to be functions of the current I₁ controlled by the first bandgap generator 40 and of the current I₂ controlled by the second bandgap generator 42. As will be recalled, the first bandgap generator 40 is designed to provide the first reference voltage VB1 having the positive temperature coefficient and thus the current I₁ will be decreasing with rising temperatures. The second bandgap generator 42 is designed to provide the second reference voltage VB2 having the negative temperature coefficient and thus the current I₂ will be increasing with rising temperatures. Accordingly, at the cold temperature of -55°C the current I₁ will be higher and the current I₂ will be lower. On the other hand, at the hot temperature of +155°C the current I₁ will be lower and the current I₂ will be higher. Therefore, the resultant base drive current I x will be increased at the cold temperatures and will be decreased at the hot temperatures so as to optimize the switching speed of the phase splitter transistor Q2. The threshold voltage V TH at which the switching occurs is determined when the total current I T is equal to the current I₂ or I x =0. From equation (12), the threshold voltage V TH is defined by setting the resultant current I x =0 and solving for V H which is the voltage at the point P. Thus, V TH = V H = 2V BE + I₂R2 Therefore, the difference between the threshold voltage V TH and the low level voltage V L is obtained by subtracting equation (4) from equation (13) and is given by: V TH - V L = 2V BE + I₂R2 - (V BE + V SD ) By simplifying, there is given: ΔV TH = (V BE - V SD ) + I₂R2 From the above equation (15) it can be seen that the first term (V BE - V SD ) will decrease with rising temperatures since it is known that both the base-emitter voltage drop of a transistor and the junction drop across the Schottky diode have negative temperature coefficients. Further, the second term (I₂R2) will increase with rising temperatures since both the current I₂ and the resistance R2 will be increasing over temperature and thus compensating for the effect of the first term. As a net result, the ΔV TH is designed to be maintained substantially constant over the operating temperature range of -55°C to +155°C. The low level voltage V L from equation (4) is plotted as curve A in Figure 7 as a function of temperature. The high level voltage V H from equation (7) is plotted as curve B in Figure 7 as a function of temperature. The threshold voltage V TH from equation (13) is plotted as curve C in Figure 7 as a function of temperature. Consequently, by making a substantially constant ΔV TH over temperature, the switching speed of the phase splitter transistor Q2 is not reduced at the higher temperatures, thereby effecting a high speed of operation over the entire temperature range. From the foregoing detailed description, it can thus be seen that the interface circuit of the present invention has eliminated extra propagation delays due to the elimination of a buffer 34 having two inverter stages. Further, the high switching speed of the phase splitter transistor Q2 in the output buffer 36 is maintained over a wide temperature range by the provision of two independent bandgap generators which have opposite temperature coefficients. While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention. Therefore, it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims: An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array (10) and a TTL output buffer (36), the output buffer (36) having a phase splitter transistor (Q2) responsive to the voltage at the connection (P) such that the transistor (Q2) receives base drive current (Ix) only when the array (10) is in a first logic state and the voltage at the connection (P) is above a predetermined threshold value (V TH ), the interface circuit (110) comprising: first means (30) for supplying a first current (I₁) to the logic array (10) to determine the voltage at the connection (P) when the array is in its first logic state; and second means (26) providing a second current (I₂) to determine said predetermined threshold voltage (V TH ) at which the base drive current (Ix) to the transistor (Q2) is cut off when the array switches from its first logic state to a second logic state, the magnitude of the base drive current (Ix) with the array (10) in its first logic state being dependent on the magnitude of the second current (I₂) and the voltage (V H ) at the connection (P), characterised in that the first and second currents (I₁, I₂) are dependent on respective first and second reference voltages (VB1, VB2) having opposite polarity temperature coefficients whereby the base drive current (Ix) to the phase splitter transistor (Q2) decreases with increasing temperature to maintain the switching speed of the output buffer (36) substantially constant over a predetermined range of temperature. An interface circuit as claimed in Claim 1, wherein said first reference voltage (VB1) is generated by a first bandgap generator (40). An interface circuit as claimed in Claim 1 or Claim 2, wherein said second reference voltage (VB2) is generated by a second bandgap generator (42). An interface circuit as claimed in any one of the Claims 1 - 3, wherein said first current (I₁) clamps the output voltage (V H ) at a predetermined level. An interface circuit as claimed in any one of the Claims 1 - 4, wherein said phase splitter transistor (Q2) is of the NPN-type conductivity. An interface circuit as claimed in Claim 5, wherein said phase splitter transistor (Q2) is a Schottky transistor. An interface circuit as claimed in any one of the Claims 1 - 6, wherein said temperature range is between -55°C and +155°C. The use of an interface circuit according to any one of the preceding claims in a programmable logic array device (10), the device (10) comprising: a plurality of input buffers (14a...14n), each of said plurality of input buffers having an input for receiving an input logic signal and an output; and a plurality of output transistors (Q1a...Q1n), each of said plurality of transistors having its base coupled to the respective outputs of said input buffers ( (14a...14n), its collector connected to a supply potential, and its emitter connected to a common node defining the said "OR-tied" connection (P).

Inventors: VASSEGHI NADER, VASSEGHI, NADER
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1988
Main classification: H03K19
IPC codes: G06F7, H03K5, G05F3, H03K19