COMPOUND SEMICONDUCTOR DEVICE HAVING NONALLOYED OHMIC CONTACTS

Abstract: An ohmic contact layer (15) is provided between an n-GaAs/n-AlGaAs/undoped GaAs double-heterojunction structure (14, 13, 12) and source/drain electrodes (19S, 19D) in a high electron mobility transistor. The ohmic contact layer (15) is made of In x Ga 1-x As or Ge. The ohmic contact layer (15) has a function of considerably reducing a specific contact resistance of a barrier (40) formed at an interface between the ohmic contact layer and the source and drain electrodes. Thereby, a nonalloyed ohmic contact is formed between the source and drain electrodes and source and drain regions formed in the undoped GaAs layer.

Description: The present invention generally relates to compound semiconductor devices, and in particular to compound semiconductor devices such as a high electron mobility transistor. At present, the practical use of integrated circuit devices utilizing compound semiconductor devices is advanced. Such integrated circuit devices have a good potential for use in future because of their excellent physical properties. Further improvements of integration level, speeding-up and lower consumed power are desired. Currently, electronic circuits fabricated as a compound semiconductor integrated circuit device are logic circuits. In general, a unit cell or circuit of a logic circuit is an inverter which consists of a driving-side-transistor and a load-side-transistor. In many cases, each transistor employed in the compound semiconductor integrated circuit device is a high electron mobility transistor (hereafter simply referred to as HEMT) or a metal semiconductor field effect transistor (hereafter simply referred to as MESFET). As is well known, both alloyed ohmic contacts and Schottky contacts are widely employed for aluminum gallium arsenide/gallium arsenide (AlGaAs/GaAs) HEMTs, GaAs MESFETs and the like. Ohmic contacts are used for source and drain electrodes, and Schottky contacts are used for gate electrodes. The source and drain electrodes are generally made of AuGe, which is subjected to an alloying process to make the ohmic contacts with source and drain regions. Schottky gate electrodes are generally made of Al or other metals having high melting points, and make Schottky contact with channels. It is noted that alloyed source and drain electrodes differ from Schottky gate electrodes in materials used. An example of a conventional HEMT having the above configuration is disclosed in U.S. Patent No. 4 424 525, for example. The above fact that the alloyed source and drain electrodes and Schottky gate electrodes are made of mutually different materials is disadvantageous for realising compound semiconductor integrated circuits of a higher integration level. This is because contact regions are necessary to connect the source or drain electrodes to the Schottky gate electrodes to configure a desired logic circuit. The presence of the contact regions prevents improvements in the integration level. That is, an increased area of the contact regions on a semiconductor chip is needed as the integration level increases. Hence, the possible integration level of the compound semiconductor integrated circuit is unsatisfactory at present. Further, it is noted that an alloying process for forming ohmic contacts is complex and cumbersome. It is therefore desirable to provide a novel and useful compound semiconductor device having nonalloyed ohmic contacts in which the above disadvantages have been eliminated. US-A-4 325 181 discloses a MESFET structure having reduced gate and source contact resistances. The structure consists of a GaAs substrate, an n-GaAs layer, an n⁺-GaAs layer, an n⁺⁺-Ge layer, a refractory metal layer and a gold layer successively formed on the substrate. The purpose of the n⁺⁺-Ge layer is to reduce the contact resistance. An article by T. Ishibashi in "Electronics Letters", 19th March 1981, Vol. 17, No. 6, pages 215-216, discloses an InP MESFET with InGaAs/InP heterostructure contacts. The source and drain contacts are constituted by an Au/Ni/In 0.53 Ga 0.47 As/InP layered structure without a metal alloying process. According to the present invention there is provided a compound semiconductor device comprising:- a compound semiconductor substrate; an active layer comprising a first semiconductor formed on the compound semiconductor substrate, the active layer having a channel region, a source region and a drain region; an electron supply layer comprising a second semiconductor formed on the active layer, an electron affinity of the second semiconductor being smaller than that of the first semiconductor; an intermediate layer formed on the electron supply layer and over the source and drain regions, comprising a third semiconductor having a band gap smaller than that of said electron supply layer; a Schottky gate electrode formed on the electron supply layer and comprising a material making a Schottky contact with the electron supply layer, and source and drain electrodes formed over the source and drain regions; further comprising:- an ohmic contact layer formed on the intermediate layer, comprising a fourth semiconductor and having a composition enabling formation of a nonalloyed ohmic contact between the intermediate layer and said source and drain electrodes, wherein the active layer, electron supply layer and intermediate layer form a structure having heterojunction barriers at the interfaces between the active layer and electron supply layer, and between the electron supply layer and the intermediate layer, said structure being constituted such that said heterojunction barriers allow most electrons to tunnel therethrough; and wherein the source, drain and gate electrodes are made of the same metallic substance. An embodiment of the present invention provides a compound semiconductor device having nonalloyed ohmic contacts in which source and drain electrodes are coupled with source and drain regions by nonalloyed ohmic contacts. An embodiment of the present invention also provides a compound semiconductor device having nonalloyed ohmic contacts in which source, drain and gate electrodes can be formed by the same metallic material, and/or in which a source or drain electrode can be integrally formed with a gate electrode. By means of the present invention there may be provided an integrated circuit of a higher integration level, which can be manufactured at a higher yield rate and with a higher reliability. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 is an elevational cross-sectional view for explaining a first step out of successive steps for producing a preferred embodiment of a HEMT which is an example of a compound semiconductor device according to the present invention; Fig. 2 is an elevational cross-sectional view for explaining a step following the step shown in Fig. 1; Fig. 3 is an elevational cross-sectional view for explaining a step following the step shown in Fig. 2; Fig. 4 is an elevational cross-sectional view for explaining a step following the step shown in Fig. 3; Fig. 5 is an elevational cross-sectional view of the embodiment of the HEMT produced by the above successive steps; Fig. 6A and 6B are energy band diagrams of the HEMT shown in Fig. 5; Fig. 7 is a graph showing a specific contact resistance vs. mole fraction x in In x Ga 1-x As; Figs. 8 to 11 illustrate steps for producing a MESFET, which is not in accordance with the present invention but helpful for understanding the same; Fig. 12 is a circuit diagram of a logic circuit which is configured by compound semiconductor devices; and Fig. 13 is a view showing a layout of a part of the logic circuit shown in Fig. 12, in which transistors are employed according to the present invention. A description will be given of a preferred embodiment of a compound semiconductor device according to the present invention, by referring to Figs. 1 to 7. The embodiment depicted in these Figures is an improvement of the HEMT which is a typical example of compound semiconductor devices produced by use of selective doping. Referring to FIG.1, an undoped gallium arsenide (i-GaAs) active layer 12 is grown on a semi-insulating GaAs substrate 11. In the undoped GaAs active layer 12, there are formed two-dimensional electron gas channels (hereafter simply referred to as 2DEG) 16 and source and drain regions. A pair of source and drain regions are located on both sides of one 2DEG channel. An n-type aluminum gallium arsenide (AlGaAs) electron supply layer 13 is grown on the undoped GaAs active layer 12. A GaAs intermediate layer 14 is grown on the n-AlGaAs electron supply layer 13. An n⁺-type indium gallium arsenide (In x Ga 1-x As: 0 ≦ x ≦ 1) ohmic contact layer 15 is grown on the n-GaAs intermediate layer 14. The above layer structure may be grown by any one of molecular beam epitaxy (hereafter simply referred to as MBE), metalorganic chemical vapor deposition (hereafter simply referred to as MOCVD), and vapor phase epitaxy (hereafter simply referred to as VPE). An electron affinity of the n-AlGaAs electron supply layer 13 is smaller than that of the i-GaAs active layer 12. The 2DEG channels 16 are formed in the vicinity of a hetero-interface. The n⁺-In x Ga 1-x As ohmic contact layer 15 is formed by firstly forming a graded layer portion in a range of x=0 to x=0.5 and secondly forming a layer portion with the constant mole fraction x of 0.5 on the graded layer part. The following parameters may apply for the layers of the HEMT shown in FIG.1, where d represents an impurity or doping concentration and t is a layer thickness: A. undoped GaAs active layer 12 t: 600 (nm) B. n-AlGaAs electron supply layer 13 t: 40 (nm) d: 1.4 x 10¹⁸ (cm⁻³) C. n-GaAs intermediate layer 14 t: 70 (nm) d: 2 x 10¹⁸ (cm⁻³) D. graded portion of n⁺-In x Ga 1-x As ohmic contact layer 15 x value: 0.0 → 0.5 t: 150 (nm) d: 1 x 10¹⁹ (cm⁻³) E. the other portion of n⁺-In x Ga 1-x As ohmic contact layer 15 x value: 0.5 t: 50 (nm) d: 1 x 10¹⁹ (cm⁻³) By a next step shown in FIG.2, grooves 11A for separating elements are formed by using a resist process, wet etching, dry etching and so on which are carried out in the conventional photolithography technology. Instead of an etching process, Ion Implantation (for example, H⁺, O⁺) can be used to form isolation areas. Subsequently, as shown in FIG.3, a photoresist film 17 is formed by using the resist process in the conventional photolithography technology. The photoresist film 17 has openings at its portions at which gate electrodes are to be formed. In FIG.3, only one of openings formed in the photoresist film 17 is shown. Then, the n⁺-In x Ga 1-x As ohmic contact layer 15 is selectively etched in which etchant containing HF or H₃PO₄ as its main component is used. This etching process forms openings 15A in the n⁺-In x Ga 1-x As ohmic contact layer 15. The etching process can be reliably stopped at the surface of the GaAs intermediate layer 14. Then, as shown in FIG.4, a photoresist film 18 is deposited by the resist process in the conventional photolithography technology. The photoresist film 18 includes openings at its portions at which gate, source and drain electrodes are desired to be formed. Subsequently, the n-GaAs intermediate layer 14 is subjected to selective etching in which etching gas of CCl₂F₂ + He is used. According to this etching process, a selective ratio of GaAs/AlGaAs of approximately 250 can be obtained. In addition, a smooth and uniform Schottky interface can be obtained. The selective etching using CCl₂F₂ + He gas is effective not only for GaAs/AlGaAs but also for GaAs/InGaAs which is employed in another embodiment described later. That is, an etching rate for InGaAs is approximately 2 (nm/min). This rate is nearly equal to that for AlGaAs. For this reason, the openings formed in the photoresist film 18 at which the source and drain electrodes are to be formed may remain open during the selective etching for the exposed part of the GaAs intermediate layer 14 at which the gate electrode is to be formed. After that, an aluminum (Al) film 19 of a thickness of approximately 400 (nm) is formed in accordance with a conventional vapor evaporation process. A titanium (Ti) film, a platinum (Pt) film, a tungsten silicide (WSi) film and the like may be used instead of the Al film 19. Thereafter, the configuration thus formed is placed into ace tone so as to dissolve and remove the photoresist film 18. Thereby, the Al film 19 is patterned by so-called lift-off, and gate electrode 19G, source electrode 19S and drain electrode 19D are formed. The source and drain electrodes 19S and 19D thus formed are coupled with the n⁺-InGaAs ohmic contact layer 15 by nonalloyed ohmic contacts, and the gate electrode 19G is coupled with the n-AlGaAs electron supply layer 13 by the Schottky contact. A description will be given of the effects such that the source and drain electrodes can be coupled with the source and drain regions formed in the active layer by ohmic contacts of low resistance, by referring to FIGS.6A, 6B and 7. FIGS.6A and 6B are energy band diagrams of the HEMT produced in accordance with the above successive steps. A horizontal axis of FIG.6A denotes a depth from the Schottky gate electrode 19G, and a vertical axis thereof denotes energy. A horizontal axis of FIG.6B denotes a depth from the source electrode 19S or the drain electrode 19D, and a vertical axis thereof denotes energy. In FIGS.6A and 6B, a symbol E V denotes a top energy level of a valence band, a symbol E F denotes a Fermi level, and a symbol E C denotes a bottom energy level of a conduction band. As well known, the n-GaAs/n-AlGaAs/undoped GaAs double-heterojunction forms a barrier against electrons which run from the source or drain electrode to the 2DEG channel or vice versa. In addition, a metal-semiconductor barrier against electrons is formed at an interface between the source and drain electrodes made of metallic substance and the semiconductor layer on which these electrodes are provided. The alloying process is aimed at destroying these barriers and thereby making alloyed ohmic contacts with the source and drain regions. On the other hand, a HEMT provided by the present invention does not employ any alloyed ohmic contacts. From this viewpoint, it would be expected that as shown in FIG.6B, there exists a metal-semiconductor barrier 40 as well as a n-GaAs/n-AlGaAs/undoped GaAs double-heterojunction barrier 50. In order to achieve a HEMT with nonalloyed ohmic contacts, specific contact resistances ρ c1 and ρ c2 of the barriers 40 and 50 respectively, must be kept as small as possible. That is, it is essential that a height and width of the barrier 40 and a height of the barrier 50 be small. In this case, it is particularly important that the height and width of the barrier 40 is reduced, i.e. its specific contact resistance ρ c1 is made as small as possible. This is because the specific contact resistance ρ c1 of the metal-semiconductor barrier 40 is generally greater than the specific contact resistance ρ c2 of the double-heterojunction barrier 50. As will be described later, the resistance ρ c2 of the barrier 50 can be easily made sufficiently small, in the order of 1 x 10⁻⁶ (Ω·cm²) or less by suitably selecting the mole fraction x in the n-Al x Ga 1-x As electron supply layer 13. In order to reduce the contact resistance ρ c1 of the barrier 40, the n⁺-InGaAs ohmic contact layer 15 is employed in the HEMT which is one example of the compound semiconductor devices according to the present invention. FIG.7 is a graph showing a specific contact resistance as a function of the mole fraction x of In x Ga 1-x As. A horizontal axis of the graph denotes the mole fraction x of In x Ga 1-x As, and a vertical axis thereof denotes the specific contact resistance (Ω·cm²). The illustrated graph reveals that when the x value is equal to 0.5 and the doping concentration N D is equal to 1 x 10¹⁹ (cm⁻³) or more, the specific contact resistance ρ c1 between the metal and the semiconductor In x Ga 1-x As becomes equal to 1 x 10⁻⁷ (Ω·cm²) or less at 300 K (room temperature). Therefore the height and width of the barrier 40 is sufficiently reduced, and thereby electrons can pass through the barrier 40 by tunneling. It is noted that a specific contact resistance of the alloyed ohmic contacts of the conventional HEMT is approximately 1 x 10⁻⁶ (Ω·cm²). Therefore, it can be seen that the nonalloyed ohmic contacts are effective for the HEMT. The specific contact resistance ρ c1 is preferably equal to 1 x 10⁻⁶ (Ω·cm²) or less, because the nonalloyed ohmic contacts have the barrier 50 of the specific contact resistance ρ c2 in addition to the barrier 40. Combinations of the mole fraction x and the doping concentration N D can be arbitrarily selected so as to satisfy the above condition of the specific contact resistance ρ c1 . Since InGaAs can be deeply doped up to approximately 5 x 10¹⁹ (cm⁻³), it is possible to easily obtain the specific contact resistance ρ c1 in the order of 1 x 10⁻⁶ or less (Ω·cm²). It is seen from the graph that the doping concentration N D of at least 5 x 10¹⁸ (cm⁻³) is necessary to obtain the specific contact resistance ρ c1 of 1 x 10⁻⁶ (Ω·cm²). In order to investigate the possibility of reducing the barrier 50, the specific contact resistance ρ c2 of n-GaAs/n-Al x Ga 1-x As/undoped GaAs double-heterojunction barrier was calculated in which the mole fraction x was used as a parameter for the calculation. This calculation is based on the fact that the height of the above double-heterojunction barrier depends on the value of x in Al x Ga 1-x As. In this calculation, thermionic emission, thermionic field emission and field emission were considered. Further, the following parameters were used in the calculation: the doping concentration of n-GaAs was 1.8 x 10¹⁸ (cm ⁻³) and that of n-Al 0.2 Ga 0.8 As was 1.4 x 10¹⁸ (cm⁻³); and the conduction-band-edge offset of AlGaAs-GaAs was ΔEc = 0.60 ΔEg. By the calculation of the specific contact resistance ρ c2 , values of 1.5 x 10⁻⁷ (Ω·cm²) at 300K and 3.3 x 10⁻⁷ (Ω·cm²) at 77K were obtained where the x value was 0.2. This means that most electrons can pass through the double-heterojunction barrier 50 by tunneling. The above values for the specific contact resistance ρ c2 of the barrier 50 are satisfactory, compared with the specific contact resistance of the alloyed ohmic contact of approximately 1 x 10⁻⁶ (Ω·cm²). As a result, the specific contact resistance ρ c2 of the barrier 50 can be kept at 1 x 10 ⁻⁶ (Ω·cm²) or less by suitably selecting the mole fraction x in the Al x Ga 1-x As electron supply layer 13. The total value of the specific contact resistance of the nonalloyed ohmic contact is approximately 1 x 10⁻⁶ (Ω·cm²) or less. This value for the specific contact resistance of the nonalloyed ohmic contact is suitable for the ohmic contacts in a HEMT. The value of the specific contact resistance can be further improved to the order of 5 x 10⁻⁷ (Ω·cm²) or less by heat treatment at 350°C for 3 minutes, for example. On the other hand, as shown in FIG.6A, the gate electrode 19G forms a Schottky contact with respect to the n-AlGaAs electron supply layer 13. Therefore, the height of the Schottky contact is considerably larger than that of the barrier 50. In other words, the surface Fermi level pinning of the n-AlGaAs electron supply layer 13 beneath the gate electrode 19G contributes to the formation of a Schottky contact. As seen from the above description, a HEMT with nonalloyed ohmic contacts can be realized. The above explanation can be summarized as follows. Directly under the gate electrode 19G, as shown in FIG.6A, the electron supply layer 13 exhibits high barrier properties due to the Schottky contact of the gate electrode 19G. On the other hand, directly under the source and drain electrodes 19S and 19D, as shown in FIG.6B, the low barriers 50 due to the heterojunctions are only formed at both the end surfaces of the electron supply layer 13. Therefore, nonalloyed ohmic contacts of low resistance can be formed by firstly reducing the contact resistance ρ c1 between the contact layer 15 and the source and drain electrodes 19S and 19D and secondly by reducing the contact resistance ρ c2 by suitably selecting the mole fraction in the electron supply layer 13. That is, it is considered that the electrons pass, by tunneling, through the junctions between the contact layer 15 and the source and drain electrodes 19S and 19D, and the heterojunctions between both the end surfaces of the electron supply layer 13. The nonalloyed ohmic contacts of the source and drain electrodes 19S and 19D result in an advantage such that the gate electrode 19G and source and drain electrodes 19S and 19D can be formed of the same material. Therefore, it becomes possible to connect the gate electrode 19G to the source or drain electrode 19S or 19D by a metallic layer used as a connecting line made of material identical to that of the electrodes, without using contact regions. In other words, the connecting line can be integrally formed with the electrodes by using the same material. In the above embodiment, the n⁺-InGaAs ohmic contact layer 15 includes graded n⁺-InGaAs portions. The graded portion is used to avoid a possible discontinuity between n⁺-InGaAs of the ohmic contact layer 15 and n-GaAs of the intermediate layer 14, because the energy band gap between the energy levels E C and E V of n⁺-InGaAs is smaller than that for n-GaAs. However, a graded n⁺-InGaAs portion is not necessarily provided in a HEMT with nonalloyed ohmic contacts according to the present invention. This is because InGaAs can be doped deeply in the order of 1 x 10¹⁹ (cm⁻³). Hence, even when an n⁺-InGaAs layer of constant x value is grown directly on the GaAs intermediate layer 14, a barrier which would be formed at an interface therebetween can be kept small, so that electrons can pass through the barrier by tunneling. In addition to InGaAs-AlGaAs HEMT described above, nonalloyed ohmic contacts can be made in an InGaAs-InAlAs HEMT, an InGaAs-InGaP HEMT, a Ge-InAlAs HEMT, a Ge-InGaP HEMT and a Ge-AlGaAs HEMT. And also, it is quite obvious that nonalloyed ohmic contacts can be made in various pseudomorphic channel HEMTs. A layer structure for each HEMT is listed below: A. InGaAs-InAlAs HEMT substrate: InP active layer: i-InGaAs electron supply layer: n-InAlAs intermediate layer: n-InGaAs ohmic contact layer: n⁺-InGaAs B. InGaAs-InGaP HEMT substrate: GaAs active layer: i-GaAs electron supply layer: n-InGaP intermediate layer: n-GaAs ohmic contact layer: n⁺-InGaAs C. Ge-InAlAs HEMT substrate: InP active layer: i-InGaAs electron supply layer: n-InAlAs intermediate layer: n-InGaAs ohmic contact layer: n⁺-Ge D. Ge-InGaP HEMT substrate: GaAs active layer: i-GaAs electron supply layer: n-InGaP intermediate layer: n-GaAs ohmic contact layer: n⁺-Ge E. Ge-AlGaAs HEMT substrate: GaAs active layer: i-GaAs electron supply layer: n-AlGaAs intermediate layer: n-GaAs ohmic contact layer: n⁺-Ge A description will now be given of a MESFET which is useful for understanding the present invention, with reference to Figs. 8 through 11. Referring to FIG.8, an n-GaAs active layer 22 is grown on a semi-insulating GaAs substrate 21 by any one of MBE, LPE and VPE. Essential parameters of the n-GaAs active layer 22 are as follows: t: 1000 Å d: 2 x 10¹⁷ (cm⁻³) As a next step, isolation by using conventional photolithography technology is carried out, but it is not shown in the following illustrations. Next, an insulating film 23 made of silicon nitrogen oxide (SiON) or silicon dioxide (SiO₂) is deposited and patterned so that portions of the film 23 are formed at which the source and drain are to be formed, as shown in FIG.8. Deposition of the insulating film 23 may be performed by plasma chemical vapor deposition (called plasma CVD). The insulating film 23 is 300 (nm) in thickness, for example. Patterning can be carried out by the conventional photolithography technology. Then, an n⁺-In x Ga 1-x As ohmic contact layer 24 is grown by MBE or MOCVD, as shown in FIG.8. As in the case of the n⁺-In x Ga 1-x As ohmic contact layer 15 of the InGaAs-AlGaAs HEMT described before, the ohmic contact layer 24 includes a graded portion in which the mole fraction x in n⁺-In x Ga 1-x As is gradually changed from 0.0 to 0.5. The other portion of the n⁺-In x Ga 1-x As ohmic contact layer 24 which is grown on the graded portion has a constant value x of 0.5. Essential parameters of the ohmic contact layer 24 are as follows: A. graded portion of the n⁺-In x Ga 1-x As ohmic contact layer 24 x value: 0.0 → 0.5 t: 150 (nm) d: 1 x 10¹⁹ (cm⁻³) B. the other portion of the n⁺-In x Ga 1-x As ohmic contact layer 24 x value: 0.5 t: 50 (nm) d: 1 x 10¹⁹ (cm⁻³) In the above structure, portions of the ohmic contact layer 24 on the n-GaAs active layer 22 which are partially exposed through openings formed in the insulating film 23 are singlecrystal, whereas portions of the ohmic contact layer 24 on the insulating film 23 are polycrystal. A subsequent step is to form a thick photoresist film (not shown) over the entire surface of the structure shown in FIG.8 and to flatten the surface by use of the spin coat process, for example. Thereafter, as shown in FIG.9, the entire surface of the photoresist film is uniformly etched by ion milling with argon gas in order to expose the surface of the insulating film 23. Thereby, only the singlecrystal n-In x Ga 1-x As portions of the layer 24 which are formed in the openings of the insulating film 23 remain. Thereafter, a photoresist film 25 (Fig. 10) having openings at which the gate, drain and source are to be formed is deposited on the surface of the structure shown in FIG.10 by the resist process employed in the conventional photolithography technology. Then, selective etching is performed by HF wet etching, in which the photoresist film 25 is used as a mask in order to form openings at the regions which are to form the respective gate electrodes. Subsequently, the portions of the n-GaAs active layer 22 exposed through the openings are recessed by the HF wet etching process. In this case, the openings formed in the photoresist film 25 may remain open. After that, an Al film 26 of a thickness of 400 (nm), for example, is deposited on the photoresist film 25 by the vapor evaporation process. Finally, the structure thus configured is placed into ace tone so as to dissolve and remove the photoresist film 25. Thereby, as shown in FIG.11, the Al film 26 is patterned by lift-off, and gate electrode 26G, source electrode 26S and drain electrode 26D are formed. The source and drain electrodes 26S and 26D thus formed are coupled with the n-InGaAs ohmic contact layer 25 by ohmic contacts, and the gate electrode 26G is coupled with the n-GaAs active layer 22 by a Schottky contact . It is noted that the MESFET thus configured has nonalloyed ohmic contacts. In this MESFET, the graded portion of the ohmic contact layer 24 is not necessarily required. FIG.12 is a circuit diagram of a logic circuit which may be configured using compound semiconductor devices. The illustrated logic circuit consists of two inverters. One of the inverters consists of a driving-side-transistor Q D1 and a load-side-transistor Q L1 , and the other consists of a driving-side-transistor Q D2 and a load-side-transistor Q L2 . An input signal IN1 is applied to a gate terminal of the transistor Q D1 . A drain terminal of the transistor Q D1 and a source terminal of the transistor Q L1 are connected to each other. Further, a gate terminal of the transistor Q L1 is connected to its source terminal. An output signal OT1 of the inverter at the initial stage is supplied to a gate terminal of the transistor Q D2 . A drain terminal of the transistor Q D2 is connected to source and gate terminals of the transistor Q L2 . An output signal OT2 of the inverter formed by the transistors Q D2 and Q L2 is supplied to a next stage (not shown). Symbols V DD and V SS denote a positive power supply potential and a ground power supply potential, respectively. As described before, contact regions such as CT1 and CT2 are necessary to form the depicted circuit structure by conventional HEMTs or MESFETs with alloyed ohmic contacts, because the material of the gate electrode is different from that of the source and drain electrodes. The presence of the contact regions prevents improvements in integration level, as mentioned before. In general, a unit cell in a memory circuit consists of six transistors. In this case, an area of the unit cell on the chip is calculated to be approximately 550 (µm²) where the integration level is of the order of 16K static random access memory (SRAM). Alternatively, an area of a unit cell composed of four transistors and two resistors (loads) is estimated to be 350 (µm²). On the other hand, with compound semiconductor devices embodying the present invention, the electrodes of transistors and connection lines between transistors can be integrally formed by the same substance. Hence, the circuit shown in FIG.12 can be formed without using contact regions such as CT1 and CT2. As a result, an area of the unit cell composed of four transistors and two resistors provided by the present invention is calculated to be approximately 150 to 200 (µm²). This value is approximately one-third of the area taken by the conventional transistors. In the calculation, the following parameters are used: a region for separating adjacent elements: 3 (µm); line and space in a connection line: 1.5/2 (µm); a gate width of a driver: 5 (µm); a width of a transfer gate: 2 (µm); and a gate length: 0.5 to 1 (µm). FIG.13 shows a layout of the circuit shown in Fig. 12, wherein transistors embodying the present invention are employed. A V DD power supply line 63 is connected to the source terminals of the transistors Q L1 and Q L2 at contact regions 61₁ and 61₂, respectively. A V SS power supply line 64 is connected to the source terminals of the transistors Q D1 and Q D2 at contact regions 62₁ and 62₂, respectively. The source terminal of the transistor Q L1 and the drain terminal of the transistor Q D1 , the gate terminal of the transistor Q L1 and the gate terminal of the transistor Q D2 are mutually connected by an integrally formed metallic layer (a connecting line) 65 without using contact regions. A compound semiconductor device embodying the present invention can enable the manufacture of integrated circuits of a higher speed, a higher productivity and a higher reliability, because it does not use contact regions for connecting terminals of transistors made of different materials to each other.

Claims: A compound semiconductor device comprising:- a compound semiconductor substrate (11); an active layer (12) comprising a first semiconductor formed on the compound semiconductor substrate, the active layer (12) having a channel region, a source region and a drain region; an electron supply layer (13) comprising a second semiconductor formed on the active layer (12), an electron affinity of the second semiconductor being smaller than that of the first semiconductor; an intermediate layer (14) formed on the electron supply layer (13) and over the source and drain regions, comprising a third semiconductor having a band gap smaller than that of said electron supply layer; a Schottky gate electrode (19G) formed on the electron supply layer (13) and comprising a material making a Schottky contact with the electron supply layer, and source and drain electrodes (19S, 19D) formed over the source and drain regions; further comprising:- an ohmic contact layer (15) formed on the intermediate layer (14), comprising a fourth semiconductor and having a composition enabling formation of a nonalloyed ohmic contact between the intermediate layer (14) and said source and drain electrodes (19S, 19D), wherein the active layer (12), electron supply layer, (13) and intermediate layer (14) form a structure having heterojunction barriers at the interfaces between the active layer (12) and electron supply layer (13), and between the electron supply layer (13) and the intermediate layer (14), said structure being constituted such that said heterojunction barriers allow most electrons to tunnel therethrough; and wherein the source, drain and gate electrodes (19S, 19D, 19G) are made of the same metallic substance. A device as claimed in claim 1, wherein the fourth semiconductor is selected from the group consisting of indium gallium arsenide (In x Ga 1-x As; 0 ≦ x ≦ 1) band germanium (Ge). A device as claimed in claim 2, wherein the fourth semiconductor has a doping concentration of In x Ga 1-x As of 5 x 10¹⁸ (cm⁻³) or over. A device as claimed in claim 2, wherein the ohmic contact layer (15) includes a graded layer portion in which a mole fraction x in In x Ga 1-x As increases from an interface with the intermediate layer (14). A device as claimed in any preceding claim, wherein the resistance of the structure comprising the active layer (12), the electron supply layer (13) and the intermediate layer (14) below the source and drain electrodes (19S, 19D) is based on a mole fraction of the second semiconductor and is 1 x 10⁻⁶ (Ω·cm²) or less. A device as claimed in any preceding claim, wherein the contact resistance of a barrier formed at an interface between the source or drain electrode (19S, 19D) and the ohmic contact layer (15) is 1 x 10⁻⁶ (Ω·cm²) or less. A device as claimed in any preceding claim, wherein the resistance of the structure comprising the active layer (12), the electron supply layer (13) and the intermediate layer (14) below the source and drain electrodes (19S, 19D) is less than that of a Schottky barrier formed below the gate electrode (19G). A device as claimed in any preceding claim, wherein the second semiconductor is selected from the group consisting of aluminum gallium arsenide (AlGaAs), indium aluminium arsenide (InAlAs) and indium gallium phosphorus (InGaP). A device as claimed in any preceding claim, further comprising a metallic layer for connecting the gate electrode to at least one of the source and drain electrodes to form a logic circuit.

Inventors: KURODA, SHIGERU, MIMURA, TAKASHI, NOTOMI, SEISHI
Applicants: FUJITSU LIMITED
Application year: 1988
Main classification: H01L29
IPC codes: H01L29