COMPLEMENTARY SIGNAL OUTPUT CIRCUIT

Abstract: A complementary signal output circuit for supplying a in-­ phase output signal and an anti-phase output signal with respect to an input signal comprises first inverter circuit (I7) for outputting the in-phase output signal and a second inverter circuit (I6) for outputting the anti-phase output signal, in responsive to the input signal. The first inverter circuit is provided with a transistor (Q1) at the output terminal thereof. The transistor changes the output signal of the first inverter circuit from a low level state to a high level state substantially simultaneously with the change of the anti-phase output signal from the high level state to the low level state.

Description: This invention concerns a complementary signal output circuit which supplies complementary signals which are in-phase with and anti-phase to an input signal. FIG.1 is a block diagram of a conventional complementary signal output circuit for obtaining mutually anti-phase complementary signals which are used as, e.g., clock signals for logic circuits. The complementary signal output circuit of FIG.1 is constructed from inverter circuits I1 - I4 composed of, for instance, CMOS circuits. An input signal IN is received by the inverter circuit I1, and inverted thereby. The output signal of the inverter circuit I1 is inverted by the inverter circuit I2. Then, the output signal of the inverter circuit I2 is inverted by the inverter circuit I3, and the output of the inverter circuit I3 is obtained as an anti-phase signal  which is anti-phase to the input signal IN. At the same time, the output signal of the inverter circuit I1 is inverted by the inverter circuit I4, and the output signal of the inverter circuit I4 is obtained as an in-phase signal  which is in-phase with the input signal. Therefore, in this circuit, whereas the anti-phase signal  is obtained by an odd number of inverter circuits I1, I2 and I3 which are cascade-connected to the input signal IN, the in-phase signal  is obtained by an even number of inverter circuits I1 and I4 which are cascade-connected to the input signal IN. That is to say, while the in-phase signal  is outputted with a delay time of 2 stages of inverter circuits with respect to the input signal IN, the anti-phase signal  is outputted with a delay time of 3 stages of inverter circuits with respect to the input signal IN. Thus, as shown by the operating wave-form diagram in FIG. 2, the anti-phase signal  is delayed by one more stage of inverter circuit when compared with the in-phase signal . Thus, there is a problem of different switching times between the in-phase signal  and the anti-phase signal  in the prior art, which sometimes causes a misoperation of the circuit being supplied with the signals. U.S. Patent 4,617,477 describes a circuit which generates complementary output signals essentially simultaneously with each other. Therefore, an object of this invention is to provide a complementary signal output circuit which can make the switching times of the in-phase signal and the anti-phase signal approximately equal, using a simple construction. According to the present invention, there is provided a complementary signal output circuit for supplying two output signals in response to an input signal alternating between high level state and a low level state in a predetermined phase, and a power source voltage, comprising: first inverter means for outputting one of the two output signals having the predetermined phase in response to the input signal and comprising a CMOS inverter circuit having two components, one connected between a power source voltage terminal and the output terminal of the circuit and the other connected between the said output terminal and a reference voltage terminal; second inverter means for outputting the other output signal having an opposite phase to the predetermined phase in response to the input signal; transistor means for changing the output signal of the first inverter means from a low level state to a high level state substantially simultaneously with the change of the other output signal from the high level state to the lower level state, characterised in that a MOS transistor is serially connected with the said other component of the CMOS inverter circuit between the said output and reference voltage terminals and being non-conductive at the time that the said transistor means is rendered conductive. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and, together with the description, serve to explain the principles of the invention. Referring now to the drawings, like reference characters designates like or corresponding parts throughout the several views. In the drawings: Fig. 1 is a block diagram of a conventional complementary signal output circuit; Fig. 2 is a wave-form diagram of the complementary signal output circuit shown in Fig. 1; Fig. 3 is a block diagram of a complementary signal output circuit; Figs. 4 and 5 are circuit diagrams showing practical constructions for the complementary signal output circuit shown in Fig. 3, the circuit of figure 5 being an embodiment of the present invention; Figs. 6, 7 and 9 are circuit diagrams of other arrangements; Fig. 8 is a wave-form diagram of the complementary signal output circuit shown in Fig. 7, and Fig. 10 is a circuit diagram of another embodiment of the present invention. The present preferred embodiments of this invention are explained with reference to the drawings. FIG.3 is a block diagram of a complementary signal output circuit. The complementary signal output circuit shown in FIG.3 comprises inverter circuits I5, I6 and I7, which are cascade-connected, and an NPN type bipolar transistor Q1. This circuit is a construction for the case when the load (not shown) to be supplied with the complementary signals  and  is relatively light. The inverter circuit I5 receives an input signal IN to be inverted, and applies its output signal to the inverter circuit I6. The inverter circuit I6 receives the output signal of the inverter circuit I5 to be inverted, and supplies an in-phase signal  which is in-phase with the input signal. The inverter circuit I7 receives the in-phase signal  which is the output signal of the inverter circuit I6 to be inverted, and supplies an anti-phase signal  which is anti-phase to the input signal IN. The base electrode of the bipolar transistor Q1 is connected to the output terminal of the inverter circuit I5 via a current-limiting resistor R. The collector electrode of the transistor Q1 is connected to the power source, e.g. 5 V, and the emitter electrode thereof is connected to the output terminal of the inverter circuit I7. In this circuit, when the input signal IN falls from a high level to a low level, the output signal of the inverter circuit I5 rises from a low level to a high level. When the output signal of the inverter circuit I5 shifts from a low level to a high level, the output signal of the inverter circuit I6 falls from a high level to a low level, and the in-phase signal  is obtained. At the same time, when the output signal of the inverter circuit I5 rises from a low level to a high level, the bipolar transistor Q1 changes from the non-conductive state to the conductive state. Therefore, the anti-phase signal  starts to rise from a low level to a high level. When the output signal of the inverter circuit I6, namely the in-phase signal , falls from a high level to a low level, the in-phase signal  is inverted by the inverter circuit I7, and the rising of the anti-phase signal  from a low level to a high level is also carried out by the inverter circuit I7. In other words, the falling of the in-phase signal  and the rising of the anti-phase signal  are both controlled by the output signal of the inverter circuit I5. Consequently, the time difference (skew) between the rising edge of the anti-phase signal  and the falling edge of in-phase signal  becomes smaller. Thus, it is possible to make the skew of the complementary signals  and  much smaller than has been obtained by the conventional complementary signal output circuit shown in FIG.1. Moreover, the delay time of the anti-phase signal  with regard to the input signal IN is approximately the delay time of 2 stages of inverter circuits. Thus,the inversion of the anti-phase signal  can be accomplished obtained faster than in the conventional circuit shown in FIG.1. FIG.4 is a circuit diagram of a concrete circuit of the complementary signal output circuit shown in FIG.3. In this circuit, CMOS circuits are used for the inverter circuits I5, I6 and I7. In FIG.4, the inverter circuit I5 is constructed from a PMOS P1 and an NMOS N1, the inverter circuit I6 is constructed from a PMOS P2 and an NMOS N2, and the inverter circuit I7 is constructed from a PMOS P3 and an NMOS N3. By constructing the inverter circuits from CMOS circuits, the same effect which can be obtained with the circuit shown in FIG.3 is obtained with a lower power consumption. FIG.5 is a circuit diagram of another concrete circuit of the complementary signal output circuit shown in FIG.3. In this circuit, each inverter circuit I5, I6 and I7 is constructed from CMOS circuit, in the same way as the complementary signal output circuit shown in FIG.4. The difference between this circuit and the circuit of FIG.4 is an addition of an NMOS N4. The NMOS N4 is connected between the NMOS N3, which composes the inverter circuit I7, and ground. The remainder of the construction is the same as in FIG.4, and has been given the same symbols. In the complementary signal output circuit shown in FIG.4, after the output signal of the inverter circuit I5 has changed from a low level to a high level, there is a period when the bipolar transistor Q1 and the NMOS N3 are both in the conductive state, during the shift of the NMOS N3 from the conductive state to the non-conductive state. The characteristic of the complementary signal output circuit of FIG.5 is that the circuit is designed to prevent a through current flowing from the power source to the ground via the bipolar transistor Q1 and the NMOS N3 during the above described period by causing the NMOS N4 to change from the conductive state into the non-conductive state when the input signal has shifted from the high level to the low level. The circuit of figure 5 forms an embodiment of the present invention. In this circuit, it is of course possible to make the skew between the rising edge of the anti-phase signal  and the falling edge of the in-phase signal  smaller in respect of the fall of the input signal IN. FIG.6 is a circuit diagram of another circuit arrangement. In this circuit, an MOS circuit in stead of a bipolar transistor is used to make the skew between the anti-phase signal  and the in-phase signal  small. In this circuit, an inverter circuit I9 is connected to the output of an inverter circuit I8, which receives and inverts the input signal IN. The inverter circuit I9 is composed of a PMOS P5 and an NMOS N5, and outputs an in-phase signal  from the interconnected drain electrodes of those devices. The gate electrode of the PMOS P5 is connected to the output of the inverter circuit I8, and the source electrode thereof is connected to the power source. The gate electrode of the NMOS N5 is connected to the output of the inverter circuit I8, and the source electrode thereof is connected to the ground. The source electrodes of an NMOS N6 and a PMOS P6 are connected to the output of the inverter circuit I9. The gate electrodes of the NMOS N6 and PMOS P6 are supplied with the input signal IN, and the drain electrodes thereof are connected to the power source and the ground, respectively. An inverter circuit I10 is connected to the input of the inverter circuit I8, and outputs an in-phase signal . The inverter circuit I10 is composed of a PMOS P7 and an NMOS N7, which both receive the input signal at their respective gate electrodes, and whose respective drain electrodes are interconnected. The source electrodes of an NMOS N8 and a PMOS P8 are connected to the output of the inverter circuit I10. The gate electrodes of the NMOS N8 and the PMOS P8 are connected to the output of the inverter circuit I8, and the drain electrodes of the NMOS N8 and the PMOS P8 are connected to the power source and the ground, respectively. In this circuit, when the input signal IN starts to rise from a low level to a high level, the NMOS N6 and N7 change into their conductive states. Thus, the in-phase signal  starts to rise from a low level to a high level, and at the same time, the anti-phase signal  starts to fall from a high level to a low level. Then, when the output signal of the inverter circuit I8 shifts from a high level to a low level, the PMOS P5 and P8 both change into the conductive state. When the input signal IN starts to fall from a high level to a low level, the PMOS P6 and P7 change into the conductive state. Thus, the in-phase signal  starts to fall from a high level to a low level and, at the same time, the anti-phase signal  starts to rise from a low level to a high level. Then, when the output signal of the inverter circuit I8 shifts from a low level to a high level, the NMOS N5 and N8 both change into the conductive state. As explained above, the start of the rising and the falling of the complementary signals  and  is controlled by changing the NMOS N6, N7 and the PMOS P6, P7 with the input signal IN, and the start points of the rising and the falling of the complementary signals  and  are approximately the same. Thus, it is possible to make the switching times of the respective complementary signals  and  almost equal. Moreover, the in-phase signal  is raised to the power source potential by the PMOS P5. Furthermore, as the inverter circuit I9 and I10 are added to the MOS circuits N6, P6 and N8, P8 of the same construction, a balance of the output signal  and  is maintained. FIG.7 is a circuit diagram of another circuit arrangement. The complementary signal output circuit shown in FIG.7 is constructed from inverter circuits I8, I9 and I10 and NPN type bipolar transistors (hereafter "BT") Q2 and Q3. In this circuit, the input signal IN is applied to the base electrode of the BT Q2. The collector electrode of the BT Q2 is connected to the power source, and the emitter electrode thereof is connected to the output of the inverter circuit I9. The conductivity of the BT Q2 is controlled by the input signal IN. The base electrode of the BT Q3 is connected to the output terminal of the inverter circuit I8. The collector electrode of the BT Q3 is connected to the power source, and the emitter electrode thereof is connected to the output terminal of the inverter circuit I10. The conductivity of the BT Q3 is controlled by the output signal of the inverter circuit I8. In this circuit, when the input signal starts to rise from a low level to a high level, the BT Q2 and NMOS N7 change into the conductive state, and the in-phase signal  starts to rise and the anti-phase signal  starts to fall. Then, when the output signal of the inverter circuit I8 falls from a high level to a low level, the PMOS P5 changes into the conductive state and carries out the raising of the in-phase signal . In this way, as the rise of the in-phase signal  starts when the BT Q2 changes into the conducting state by being supplied with the input signal IN, the delay due to the existence of the inverter circuit I8 is compensated. Next, when the input signal IN starts to fall from a high level to a low level, the PMOS P7 changes into the conductive state and the anti-phase signal  starts to rise. Then, when the output signal of the inverter circuit I8 rises from a low level to a high level, the NMOS N5 changes into the conductive state and the in-phase signal  starts to fall. Moreover, at the same time, the BT Q3 changes into the conductive state and carries out the raising of the anti-phase signal  . FIG.8 is a diagram showing the simulated result of the complementary signals  and  , in respect of the input signal IN in the circuit shown in FIG.7. As shown in FIG.8, in the circuit construction shown in FIG.7, it is possible to make the potentials of the intersections of the respective rises and falls of the complementary signals  and  almost agree, and the switching times can be made almost equal. Furthermore, the bipolar transistors Q2 and Q3, which carry out the raising of the complementary signals  and  , are provided at the output terminals of the inverter circuit I9 and I10. Thus, using the high current drivability of these bipolar transistors, it is possible to make the rising waveforms of the complementary signals  and  sharper, even for heavy loads. FIG.9 is a circuit diagram of yet another circuit arrangement. The complementary signal output circuit shown in FIG.9 has the characteristics that, at the output terminals of inverter circuits I9 and I10 of the complementary signal output circuit shown in FIG.7, NPN type BT Q4 and BT Q5 are provided to speed up the falling speed of the complementary signals  and  . Moreover, this complementary signal output circuit is designed so that, by applying an input signal IN to the input of the inverter circuit I8 via an input circuit 11, the anti-phase signal  is obtained from the output of inverter circuit I9, and the in-phase signal  is obtained from the output terminal of the inverter circuit I10. The inverter circuit I8 is composed of a PMOS P10 and an NMOS N10, and the input circuit 11 is composed of PMOS P11 and P12, NMOS N11 and N12 and BT Q6. When the input signal shifts from a high level to a low level, the PMOS P11 and P12 and BT Q6 in the input circuit 11 all change into the conductive state and a high level signal is applied to the inverter circuit I8. When the input signal shifts from a low level to a high level, the NMOS N11 and N12 change into the conductive state and a low level signal is applied to the inverter circuit I8. That is to say, the input circuit 11 applies a signal which is an inversion of the input signal IN to the inverter circuit I8. The BT Q4 is connected between the output terminal of the inverter circuit I9 and ground, and its base electrode is connected to the node between the NMOS N13 and N14, which are connected in series between the output terminal of the inverter circuit I9 and the ground. The conductivity of the NMOS N13 is controlled by the output signal of the inverter circuit I8, and the conductivity of the NMOS N14 is controlled by the output signal of input circuit 11. The BT Q5 is connected between the output terminal of the inverter circuit I10 and the ground, and its base electrode is connected to the node between the NMOS N15 and N16, which are connected in series between the inverter circuit I10 and the ground. The conductivity of the NMOS N15 is controlled by the output signal of the input circuit 11, and the conductivity of the NMOS N16 is controlled by the output signal of the inverter circuit I8. In this circuit, the basic operation is the same as that of the circuit shown in FIG.7. During the falling time of the complementary signals  and  , the falling speed of the complementary signals  and  is speeded-up by the operation of the BT Q4 and BT Q5. That is to say, when the input signal to the inverter circuit I9 rises from a low level to a high level, the NMOS N5 changes into the conductive state and the anti-phase signal  starts to fall. At the same time, the NMOS N13 changes into the conductive state and the NMOS N14 changes into the non-conductive state. Thus, a current flows from the load (not shown) via the NMOS N13 to the base electrode of the BT Q4 to make the Q4 conductive state. Therefore, the current driving drivability is increased due to the BT Q4 compared with the case where the NMOS N5 alone. Thus, the falling of the anti-phase signal  is speeded-up. When the input signal IN falls from a high level to a low level, the NMOS N7 changes into the conductive state, and the in-phase signal  starts to fall. At the same time, the NMOS N15 changes into the conductive state, and the NMOS N16 changes into the non-conductive state. In this way, in the same way as described above, the BT Q5 changes into the conductive state and the falling speed of the in-phase signal  is speeded-up. Consequently, the rising and falling wave-forms of the complementary signals  and  can be made sharper, even for heavy loads. FIG.10 is a circuit diagram of a second embodiment of this invention. The characteristic of this circuit is that, in order to prevent a through current attempting to flow from the power source to the ground via the BT Q2 and the NMOS N5 in the complementary signal output circuit shown in FIG.9, an NMOS N17 is inserted between the NMOS N5 and the ground. The conductivity of the NMOS N17 is controlled by the input signal IN. When the input signal IN falls from a high level to a low level, whereas the BT Q2 changes into the conductive state in respective to the high level output signal of the input circuit 11, the NMOS N5 changes into the non-conductive state after a delay time due to the 1-stage component of the inverter circuit I8. Because of this, the BT Q2 and NMOS N5 become temporarily in the conductive state at the same time. Therefore, by changing the conductivity of the NMOS N17 into the non-conductive state before the BT Q2 changes into the conductive state, by applying the input signal IN to the NMOS N17, a through current is prevented. When using this invention as described above, either or both of the switching operations of the complementary signals may be compensated by either or both of a transistor connected between the output of an even-numbered inverter circuit and the power source and a transistor connected between the output of an odd-numbered inverter circuit and the power source. Thus, it becomes possible, using a simple construction, to make the switching times of each complementary signal in respect of the input signal almost equal. The present invention has been described with respect to specific embodiments. However, other embodiments based on the principles of the present invention should be obvious to those of ordinary skill in the art.

Claims: A complementary signal output circuit for supplying two output signals in response to an input signal alternating between a high level state and a low level state in a predetermined phase, and a power source voltage, comprising: first inverter means (I7; I8; I9) for outputting one of the two output signals having the predetermined phase in response to the input signal and comprising a CMOS inverter circuit having two components, one (P3; P5) connected between a power source voltage terminal and the output terminal of the circuit and the other (N3; N5) connected between the said output terminal and a reference voltage terminal; second inverter means (I6; I10) for outputting the other output signal having an opposite phase to the predetermined phase in response to the input signal; transistor means (Q1; Q2) for changing the output signal of the first inverter means from a low level state to a high level state substantially simultaneously with the change of the other output signal from the high level state to the lower level state, characterised in that a MOS transistor (N4; N17) is serially connected with the said other component (N3; N5) of the CMOS inverter circuit between the said output and reference voltage terminals and being non-conductive at the time that the said transistor means (Q1, Q2) is rendered conductive. The complementary signal output circuit of claim 1, wherein the first (I7) and the second (I6) inverter means are cascade-connected to the input signal. The complementary signal output circuit of claim 1, wherein the second inverter means (I6) comprises a first terminal supplied with the power source voltage and a second terminal, and a CMOS inverter circuit connected between the first and the second terminals. The complementary signal output circuit of claim 1, wherein the first (I8, I9) and the second inverter means (I10) are connected in parallel to the input signal. The complementary signal output circuit of claim 4, wherein the first inverter means comprises a first (I8) and a second (I9) inverter circuit being cascade-connected to the input signal. The complementary signal output circuit of claim 1 or claim 4, wherein the transistor means comprises a bipolar transistor (Q2) having a base electrode being supplied with the input signal.

Inventors: HARA, HIROYUKI C/O PATENT DIVISION, UENO, MASAJI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: H03K5
IPC codes: H03K5, H03K19