SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED SENSE AMPLIFIER ARRANGEMENT

Abstract: A semiconductor memory device having an improved arrangement of bit lines which can operates stably, is disclosed. The memory device comprises a plurality of first bit line pairs, a plurality of second bit line pairs, and a plurality of sense amplifiers, a control circuit for connecting either of the first bit line pairs and the second bit line pairs to the sense amplifiers, and is featured in that the first and second bit line pairs are alternately arranged in parallel one by one.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a semiconductor memory device, and more particularly to a dynamic type semiconductor memory device employing so-called shared sense amplifier scheme. Semiconductor memory devices have come to have large memory capacities such as 256 K bits, 1 Mega bits, and the internal signals read-out from memory cells are reduced to a minute level. In such memory devices, those employing one-transistor type memory cells having one transistor and one capacitor are generally utilized. Accompanied by the increase in the memory capacity, the number of memory cells coupled to the respective bit line has become large and effective capacitance of the respective bit line has also become large. This increase in the bit line capacitance lowers a potential change at the bit line by the read-out signal from a memory cell. Under such circumstance, the so-called shared sense amplifier scheme has been proposed. According to the shared sense amplifier scheme, the respective pair of bit lines are splitted into two pairs of first and second bit line segments and one pair of the bit line segments are electrically connected to a sense amplifier. The details of the shared sense amplifier scheme is disclosed in the United States Patent Specification 4,366,559 issued to Misaizu et al. In the shared sense amplifier scheme, it has been practised to arrange a plurality of pairs of first bit line segments in parallel at one side of sense amplifiers arranged in line and a plurality of pairs of second bit line segments in parallel at the other side of the sense amplifiers. Accordingly, in the shared sense amplifier, the capacitance of the respective bit line segment is reduced to half as compared to the conventional scheme, and it is possible to perform more stable and reliable sensing operation. The conventional semiconductor memory device suffers, however, from the problem concerning the noise generated by coupling capacitance (C BB ) between the bit lines arranged in parallel. Considering this problem in regard to the so-called folded bit line arrangement, a pair of bit lines which are connected to the same sense amplifier are always in anti-phase relation to each other when activated and therefore act so as to reduce the differential potential between the true and complementary bit lines constituting the bit line pair. When bit line pairs which are adjacent to the certain bit line pair concerned act in anti-phase relation to the certain bit line pair also, the coupling capacitance C BB between the certain bit line pair and the adjacent bit line pairs acts so as to reduce the differential potential between the bit lines of the certain bit line pair. In other words, the coupling capacitance C BB between the bit lines substantially causes lowering in the sensitivity of the sense amplifier. As the integration density and the memory capacity are increased and the spacing between the wirings is consequently reduced, that is, as the spacing between the bit lines is reduced, the coupling capacitance C BB increases and becomes a critical problem. Thus, the memory device employing the folded bit line scheme is readily affected by the noise generated by the coupling capacitance between the bit lines. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which has improved sensitivity and stability in sensing stored information. It is another object of the present invention to provide a semiconductor memory device having the improved shared sense amplifier scheme. The invention is defined by claims 1 and 4. The semiconductor memory device according to the present invention comprises a plurality of first bit line pairs, a plurality of second bit line pairs, a plurality of sense amplifiers, a control circuit for electrically connecting either of the first bit line pairs and the second bit line pairs to the sense amplifiers during a sense period, and is featured in that the plurality of first bit line pairs and the second bit line pairs are alternately arranged in parallel. Accordingly, the non-selected, or non-activated bit line pair is necessarily interposed between every two activated bit line pairs, and the effective capacitance between the every two activated bit line pairs. Thus, noise between the activated bit line pairs can be remarkably reduced. For example, when the first bit line pairs are selected and connected to the sense amplifiers, the second bit line pairs are not connected to the sense amplifiers for amplification. Therefore, the potential change in one of the first bit line pairs caused by the sense amplifier is not directly transmitted to other first bit line pairs near the above one bit line pair via the coupling capacitance C BB because the second bit line pair which is not subjected to the potential, is interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic block diagram showing major part of the conventional shared sense amplifier scheme; Fig. 2 is a schematic block diagram showing major part of the memory device according to one embodiment of the present invention; and Fig. 3 is a timing diagram of the device of Fig. 2. DETAILED DESCRIPTION OF THE INVENTION Referring to Fig. 1, the conventional memory device employing the share sense amplifier scheme is explained. By way of explanation, two columns of arrangement are representatively illustrated in Fig. 1. Sense amplifiers SA₁, SA₂ ... are arranged in row in line. Each of sense amplifiers includes a pair flip-flop transistors Q A1 and Q A2 , a pair of sense nodes N₁, N₂ and a sense enable node N₃. The sense enable nodes N₃ of all the sense amplifiers are supplied with a sense enable signal SE in common. On the left side of the arrangement of the sense amplifiers, a plurality of memory cells MC are arranged in a matrix form in rows and columns and a plurality of word lines WL1A - WLnA and a plurality of pairs of bit lines BL1A, BL1A , BL2A, BL2A ... are also arranged in rows and columns, respectively. Similarly, on the right side of the sense amplifiers a plurality of memory cells are arranged with word lines WL1B - WLnB and a plurality of pairs of bit lines. The pair of bit lines BL1A, BL1A and the pair of bit lines BL1B, BL1B belong to the same column and correspond to the pair of first bit line segments and the pair of second bit line segments, in the sense of the foregoing explanation. However, for simplicity of explanations, those are simply referred to as bit lines. The pairs of bit lines BL1, BL1A ... on the left side are connected to the sense amplifiers via a plurality of pairs of transfer gate field effect transistors Q₁₁, Q₁₂, Q₃₁, Q₃₂ ... , respectively. Similarly, the pairs of bit lines BL1B, BL1B , BL2B, BL2B ... on the right side are connected to the sense amplifiers via a plurality of pairs of transfer gates Q₂₁, Q₂₂, Q₄₁, Q₄₄ ... respectively. Precharge transistors Qp are connected between the bit lines and a precharge potential Vp. As is seen from Fig. 1, the coupling capacitance C BB is present between every adjacent bit lines arranged in parallel. The operation of the memory of Fig. 1 is as follows: First, a precharge control signal Φ p is raised to a power voltage V DD or more to make the precharge transistors Q p on so that the bit lines are precharged to V p . In this instance, control signals Φ T1 and Φ T2 are both raised to a high level with the sense enable signal SE of the precharge potential V p so that the sense nodes N₁ and N₂ of the respective sense amplifiers are also precharged. Then, a sense period is introduced and one of word lines is selected according to address information and one of the control signals Φ T1 and Φ T2 is selected. For example, the word lines on the left side e.g. WL1A, is selected, the control signal Φ T1 remains active while the control signal Φ T2 is rendered inactive. Thus, the bit lines on the left side are connected to the sense amplifiers and the bit lines on the right side are electrically isolated from the sense amplifiers. The memory cells coupled to the selected word line provide small potential difference in the respective pairs of bit lines in the left side. The the sense enable signal SE is gradually changed to a low level from the precharge level so that the potential differences in the respective bit line pairs on the left side are amplified by the sense amplifiers enabled by SE . Through the amplification by the sense amplifiers, one bit line e.g. BL1A having a lower potential is discharged to the ground potential while the other bit line e.g. BL1A of a higher potential remains at a high level or is made further high, in each bit line pairs. In this instance, assuming that the adjacent bit line, e.g. BL2A in the adjacent bit line pair is changed to the low level, the bit line ( BL1A ) of the high level is inevitably affected by the two adjacent bit lines (BL2A, BL1A) of the low level via the coupling capacitances C BB . Thus, the level of the bit line BL1A is undesirably lowered. Throughout the amplification of the bit line pairs on the left side, the bit line pairs on the right side are left in the high impedance, precharged state. Thus, the conventional memory device of Fig. 1 suffers from the noise generated by the coupling capacitance C BB between the every adjacent bit lines. Referring to Fig. 2, the memory device according to one preferred embodiment of the present invention will be explained. In Fig. 2, the elements or portions corresponding to those in Fig. 1 are denoted by the same or similar references, and the detailed feature with respect to the sense amplifiers SA₃, SA₄ and their relevant cell arrangements is not illustrated because they are repetition of those with respect to the sense amplifiers SA₁ and SA₂. The present embodiment is featured in that a plurality of transfer gate pairs (Q₁₁, Q₁₂; Q₃₁, Q₃₂; Q₅₁, Q₅₂ ...) for connecting the bit lines pairs on the left side are alternately controlled by the control signals Φ T1 and Φ T2 . Similarly, a plurality of transfer gate pairs (Q₂₁, Q₂₂; Q₄₁, Q₄₂; Q₆₁, Q₆₂; ...) for connecting the bit line pairs in the right side to the sense amplifiers SA₁, SA₂ SA₃ ... are alternately controlled by the control signals Φ T2 and Φ T1 , as illustrated. Thus, in each side, only one bit line pair in every two adjacent bit line pairs is coupled to the sense amplifier while the other bit line pair in the every two adjacent bit line pairs is not coupled to the sense amplifier but left in the floating, high impedance state. In this embodiment, a pair bus lines I/O and I/O are provided along the sense amplifiers and coupled to the sense nodes N₁ and N₂ of the respective sense amplifiers via a plurality of transfer gate pairs (Q 1A , Q 1B ; Q 2A , Q 2B ...) controlled by column selection signals Y₁, Y₂ ..., respectively. Each of memory cells MC includes an additional transfer gate transistor Q 2A which is controlled by the relevant one of the control signals Φ T1 and Φ T2 , in addition to the conventional cell transistor Q M and the cell capacitor C M . Each of dummy cells DMC includes also an additional transistor Q 3A controlled by the relevant control signal Φ T1 or Φ T2 , in addition to a dummy cell transistor Q R2 , a reset transistor Q R1 and a capacitor C R . The gates of the transistors Q R2 and Q R1 are connected to a dummy word line Φ DX and a reset control line Φ RS . The operation of the device of Fig. 2 is as follows: After the precharge operation for the bit lines by the precharge transistors Q p , one of the word lines WL1A ... on the left side and one of the word lines WL1B ... on the right side are simultaneously selected. Also, according to a part of address information, one of the control signals Φ T1 and Φ T2 is activated. Assuming that the control signal Φ T1 is activated and WL1A and WL1B are selected, the memory cells MC₁₁, MC₂₂ are activated while the memory cells MC₁₂, MC₂₁ are not activated and the bit line pairs (BL1A, BL1A ; BL2B, BL2B ) connected to the activated memory cells are electrically connected to the sense amplifiers SA₁, SA₂, respectively and subjected to amplification thereby. While the bit line pairs (BL1B, BL1B ; BL2A, BL2A ) connected to non-activated memory cells are electrically isolated from the sense amplifiers SA₁, SA₂ ... . Therefore, the selected bit line pair, e.g. BL1A, BL1A is not affected by the potential change in the adjacent bit line pairs, e.g. BL2A, BL2A . Waveforms of the major portions in Fig. 2 is illustrated in Fig. 3. With the above-described circuit configuration, it is possible to reduce considerably the interference between the adjacent bit line pairs. This is because a bit line pair which is in a floating state is infallibly provided between the activated bit line pairs to reduce the coupling capacitance between the activated bit line pairs.

Claims: A semiconductor memory device comprising a plurality of memory units arranged in parallel, said memory units being classified into odd number of memory units and even number of memory units according to their locations, each of said odd number of memory units including a first sense amplifier (SA₁, SA₃), a first bit line pair (BL1A, BL1A ; BL3A, BL3A ) arranged on one side of said first sense amplifier, a second bit line pair (BL1B, BL1B ; BL3B, BL3B ) arranged on the other side of said first sense amplifier, first means (Q 11 , Q 12 , Q 51 , Q 52 ) for operatively connecting said first bit line pair to said first sense amplifier, and second means (Q 21 , Q 22 , Q 61 , Q 62 ) for operatively connecting said second bit line pair to said first sense amplifier, each of said even number of memory units including a second sense amplifier (SA₂, SA₄), a third bit line pair (BL2A, BL2A ; BL4A, BL4A ) arranged on one side of said second sense amplifier, a fourth bit line pair (BL2B, BL2B ; BL4B, BL4B ) arranged on the other side of said second sense amplifier, third means (Q 31 , Q 32 ) for operatively connecting said third bit line pair to said second sense amplifier, and fourth means (Q 41 , Q 42 ) for operatively connecting said fourth bit line pair to said second sense amplifier, each said first bit line pairs being positioned adjacently to each of said third bit line pairs in parallel, each of said second bit line pairs being positioned adjacently to each of said fourth bit line pairs; characterised by control means (Φ T1 , Φ T2 ) for controlling said first to fourth means in a first state in which said first and fourth means are enabled and said second and third means are disabled during a sensing period and a second state in which said second and third means are enabled and said first and fourth means are disabled during said sensing period. The memory device according to claim 1, in which each of said first to fourth means includes a transfer gate pair for connecting the associated said bit line pair to the associated sense amplifier. The memory device according to claim 1, in which each of said memory units includes a plurality of memory cells (MC), each of said memory cells having a capacitor (C M ) and a series circuit of first (Q M ) and second (Q 2A ) transistors coupled between one end of said capacitor and one of bit lines in each bit line pair, a gate of one of said first and second transistors being connected to one of word lines (WL), a gate of the other of said first and second transistors being connected to said control circuit (Φ T1 , Φ T2 ). A semiconductor memory device comprising a plurality of first sense amplifiers (SA₁, SA₃) and a plurality of second sense amplifiers (SA₂, SA₄), a plurality of first bit line pairs (BL1A, BL1A ; BL3A, BL3A ), a plurality of second bit line pairs (BL2A, BL2A ; BL4A, BL4A ), said first bit line pairs and said second bit line pairs being arranged in parallel such that each first bit line pair is positioned adjacently to each second bit line pair, first means (Q 11 , Q 12 , Q 51 , Q 52 ) for operatively connecting each one of said first bit line pairs to a corresponding one of said first sense amplifiers, second means (Q 31 , Q 32 ) for operatively connecting each one of said second bit line pairs to a corresponding one of said second sense amplifiers, characterised by control means (Φ T1 , Φ T2 ) for operatively enabling one of said first and second means and disabling the other of said first and second means during a sense period when said sense amplifiers amplify potential differences in the bit line pairs connected thereto, whereby all of said first or all of said second bit line pairs are electrically isolated from said sense amplifiers and the others of said first and second bit line pairs are electrically connected to their corresponding sense amplifiers during said sense period. The memory device according to claim 4, further comprising precharging means (Q p , Φ 1 ) for operatively precharging said first bit line pairs and said second bit line pairs to a precharge potential (V cc ). The memory device according to claim 4, in which said first means includes a plurality of first transfer gate pairs each coupled between one of said first bit lines and one of said first sense amplifiers, and said second means includes a plurality of second transfer gate pairs each coupled between one of said second bit line pairs and one of said second sense amplifiers.

Inventors: HANNAI, SEIICHI
Applicants: NEC CORPORATION
Application year: 1988
Main classification: G11C7
IPC codes: G11C11, G11C7