Frame synchronising method and system

Abstract: In this invention, a structure in which a data stream encoded into the M² code is cut at the boundary of its arbitrary bit cells and a unique sync pattern is inserted between the bit cells is adopted. As a result, the erroneous detection of data of the data stream modulated with the M² code as a sync pattern can be prevented to avoid the synchronization shift, the occurrence of the synchronization error. Further, the correct and stable synchronization can be established so as to enable reproduction of an original digital data with high fidelity. Also, by eliminating the sync pattern and connecting its data blocks before and after as they are, a data stream satisfying the rule of the code and inserting the pattern into a data stream modulated with the M² code.

Description: This invention relates to a frame synchronizing method and system for a data stream modulated based on M² code. Various kinds of proposals have been made conventionally with respect to a digital data modulation system. One of them is the M² code disclosed in U.S. Patent No. 4,027,335. The M² code is based on the miller code and is the so-called DC-free code in which a direct current component after modulation can be eliminated. The M² code is a self-clocking enable code of the minimum inversion interval Tmin = T, detection window width Tw = 1/2T, the maximum inversion interval T MAX = 3T (T MAX /Tmin = 3) if it is assumed that the length of bit cells is T and a suitable code of the range in which the data rate does not become so much high. As a result, the recording of video data modulated with the M² code into a tape has generally been performed at a part of digital VTR. The modulation rule of the Miller code is basically applied to that of the M² code in which an improvement for eliminating a DC component of data is made to solve a disadvantage in the Miller code. Basically, "0" of original data is represented by a first level transition of a bit cell, while "1" of the original data is represented by an intermediate level transition of the bit cell. Further, with respect to "0" subsequent to "1" of the original data, the level transition of the bit cell is suppressed. This is the modulation rule of the Miller code. In addition, in the modulation rule of the M² code, the level transition of the last "1" is suppressed to eliminate a DC component of post-modulation data if an even number of "1's" continue after "0" of the original data, for example. As a result of the modulation based on such modulation rule, the above-mentioned various conditions are satisfied. Now, the correct frame synchronization must be established at the time of digital data reproduction. Therefore, a sync pattern which is clearly distinguished from data must be inserted into a data stream. For instance, in an 8 - 10 modulation system used in RDAT, it is possible to form a unique sync pattern (which does not occur in a data stream). However, in the above-stated M² code, a unique sync pattern is not defined in the encoded data stream. For this reason, a method for inserting a particular (sixteen-bit, for example) sync pattern for frame synchronization between data blocks before encoding has been adopted generally. As has been mentioned before, since a particular sync pattern is inserted into a data stream, this sync pattern cannot be unique thereby to raise a problem that the identical pattern occurs at a certain probability. As a result, there is a probability that the above-mentioned data may be detected erroneously as a sync pattern. Therefore, there is a problem that the synchronization shift and the synchronization error take place so as to make difficult the establishment of correct synchronization and, as a result, the correct reproduction of digital data. Also, in a conventional method there is a problem that the sync pattern can be detected only after decoding. Therefore, an improvement on this problem has been desired. GB-A-2056206, on which the precharacterising portion of appended claim 1 is based, proposes a method of providing a block marker having a pulse length which does not appear in an M² coded data stream, namely of four data bits. This pulse may be generated by coding a binary bit sequence "10001" and suppressing the expected resulting transitions between the "0"s. Furthermore, to avoid a DC component, it is proposed to code "100010001". However, this prior system is disadvantageous in that it requires not only the insertion of a special bit sequence in the data to be coded but also appropriately timed suppression of transitions between "0"s. An object of the present invention is, therefore, to provide a frame synchronizing method and system for a data stream encoded with the M² code to avoid the above-mentioned disadvantages in the prior art. Another object of this invention is to provide a frame synchronizing method and system capable of preventing a false detection of a frame synchronizing pattern on the decoding or reproducing side. Still another object of the invention is to provide a frame synchronizing method and system capable of detecting a frame synchronizing pattern before decoding on the decoding or reproducing side. Further object of the invention is to provide a frame synchronizing method and system for enabling a frame synchronization to be established with high accuracy and stability on the decoding or reproducing side. According to an aspect of the present invention, there is provided a frame synchronizing method for generating encoded data with a frame synchronizing signal, the encoded data being based on original data and having a first logical bit state and a second logical bit state, said method comprising steps of: encoding said original data into an M² coded data stream; and providing a frame synchronizing signal having a unique pattern which does not appear in said M² coded data stream other than a period of time of said frame synchronizing signal, the total period of time when a level of said unique pattern is an "L" level being equal to the total period of time when the level of said unique pattern is an "H" level and being one half of the total period of time of said unique pattern, and an initial period of time of said unique pattern is 0.5T followed directly by a transition where T is the period of each bit cell of the original data; characterised by providing at least two unique patterns each having a different initial level, the number of level transitions in each said unique pattern being even, a last period of time of each said unique pattern being at least 1T and the level of the last period of time being equal to that of said initial period of time; inserting into said M² coded data stream one of said unique patterns having the level of said initial period of time which is equal to that of the M² coded data preceding said unique pattern. According to another aspect of the present invention, there is provided a frame synchronizing system for generating encoded data with a frame synchronizing signal, the encoded data being based on original data and having a first logical bit state and a second logical bit state, said system comprising: means (2) for encoding said original data into an M² coded data stream; and means (4) for providing a frame synchronizing signal having a unique pattern which does not appear in said M² coded data stream other than a period of time of said frame synchronizing signal, the total period of time when the level of said unique pattern being an "L" level is equal to the total period of time duration when the level of said unique pattern is an "H" level and being one half of the total period of time of said unique pattern, and an initial period of time of said unique pattern being 0.5T followed directly by a transition, where T is the period of each bit cell of the original data, characterised by means for providing two unique patterns, each having a different initial level, the number of level transitions in each said unique pattern being even, a last period of time of each said unique pattern being at least 1T and the level of the last period of time being equal to that of said initial period of time; means (4) for inserting into said M² coded data stream one of said unique patterns having the level of said initial period of time equal to that of the M² coded data preceding said unique pattern. As a result, the frame synchronizing signal can be detected without error other than when the error occurs in the M² coded data stream, and the frame synchronizing signal can be detected prior to the decoding of the M² coded data stream. The present invention will be described in more detail with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a first embodiment of the invention; Fig. 2 is a block diagram of a decoder for decoding encoded data in the first embodiment; Figs. 3 and 4 are time charts for describing the operation of the embodiment; Fig. 5 is a diagram of a state transition of M² code; Fig. 6 is a block diagram of a second embodiment of the present invention; Fig. 7 and 8 are time charts for describing the embodiment of Fig. 6; Fig. 9 is a block diagram of a decoder for decoding data encoded in the second embodiment; Figs. 10 and 11 are block diagrams for showing detailed examples of a sync detection circuit; Fig. 12 is a diagram for showing a data pattern; and Fig. 13 is a time chart for describing the operation of the second embodiment. One embodiment of this invention will be described hereunder referring to the drawings. The embodiment is the one to which the invention is applied to a sync pattern of 8-bit cells [8T]. In the embodiment, an encoded data stream of the M² code is severed at the boundary of arbitrary bit cells and a predetermined sync pattern is inserted between those cells. Figs. 1 and 2 show a structure of a system to which this invention is embodied. An explanation will be given in the order as follows: Encoding side Fig. 1 shows a structure of an encoding side of a frame synchronizing system. Original digital data Dori produced from a data generator 1 is supplied to an M² encoder 2. At the M² encoder 2, the original digital data Dori is M²-modulated based on the M² code rule, and data D is given to one terminal 3a of a switch 3 and a sync pattern generator 4, respectively. The sync pattern generator 4 detects whether the last bit cell of the data D supplied from the M² encoder 2 is eigher an "H" level or "L" level to generate its corresponding sync pattern P SY . The pattern P SY is given to the other terminal 3b of the switch 3. All of the above-mentioned data generator 1 and M² encoder 2 and the sync pattern generator 4 operate in response to the outputs of AND gates 5 and 6 to which a clock signal S 2CK and a sync signal S SY are inputted. The signal S SY becomes "H" in a period of 8T during which a sync pattern is inserted. Now, T is a length of bit cells of a signal before encoding and an inverse number of the data rate. It is to be noted that the clock signal S 2CK is the one obtained by frequency doubling a clock signal of the bit cell frequency. In the above-stated structure of Fig. 1, when the sync signal S SY takes an "H" level, the sync signal S SY given to the AND gate 5 is inverted to take an "L" level. As a result, the clock signal S 2CK is not output from the AND gate 5 so that the data generator 1, M² encoder 2 do not operate. At this time, since the sync signal S SY inputted to the AND gate 6 assumes an "H" level, the clock signal S 2CK is produced from the AND gate 6 so as to operate the sync pattern generator 4. The sync pattern P SY generated at this time corresponds to the "H" level or "L" level of the last one of the data supplied by the M² encoder 2. The sync pattern P SY produced by the sync pattern generator 4 is given to the terminal 3b. At the switch 3, when the sync signal S SY takes an "H" level, the terminals 3b and 3c are connected. For this reason, the sync pattern P SY produced from the sync pattern generator 4 is taken out to an output terminal 7 through the terminals 3b and 3c. Next, with the "L" level of the above-described sync signal S SY , the sync signal S SY given to the AND gate 5 is inverted to have an "H" level. As a result, the clock signal S 2CK is output from the AND gate 5 to operate the data generator 1 and the M² encoder 2. At this time, since the sync signal S SY inputted to the AND gate 6 takes an "L" level, the clock signal S 2CK is not produced from the AND gate 6 so as not to operate the sync pattern generator 4. The data D produced from the M² encoder 2 and modulated with the M² code is taken out from the terminal 3a. At the switch 3, the terminals 3a and 3c are connected when the sync signal S SY assumes an "L" level. As a result, the data D given from the M² encoder 2 is taken out of the output terminal 7 through the terminals 3a and 3c. One byte of the above-mentioned sync signal S SY is output for every 35 bytes of the data D, for example. The 35-byte data and one-byte sync pattern P SY form one frame data. Decoding side Fig. 2 shows a structure of the decoding side of the frame synchronizing system. Reception data having each frame structure (frame data composed of the sync pattern P SY and data D) supplied from an input terminal 10 is given to a 16-bit shift register 11 and a PLL circuit 12. The PLL circuit 12 performs an extraction of a bit clock and supplies the two-multiplied clock signal S 2CK to the above-mentioned shift register 11 and an AND gate 13. The shift register 11 is composed of a 16-bit shift register for taking in the above-stated reception data on the basis of the clock signal S 2CK supplied from the PLL circuit 12. When the reception data is being transferred in the shift register 11 according to the clock signal S 2CK , the reception data is supplied to a coincidence detection circuit 14 for every bit of the data. The reception data from the shift register 11 is given to an M² decoder 15 and demodulated into the original digital data Dori on the basis of the rule of the M² code. At the coincidence detection circuit 14, the reception data taken into the shift register 11 is compared with a predetermined sync pattern P SY . If the sync pattern P SY is detected in the reception data, a control signal Scon of "H" level is given to the AND gate 13 and an output terminal 16. The control signal Scon inputted to the AND gate 13 is inverted to take an "L" level. As a result, the clock signal S 2CK is not produced from the AND gate 13 so as not to operate the M² decoder 15. Since this state is continued until the last bit of the sync pattern P SY [8T] has passed the shift register 11, the sync pattern P SY is not accepted at the M² decoder 15 so that the pattern is discarded. After the last bit of the sync pattern P SY has passed the shift register 11, the control signal Scon output from the coincidence detection circuit 14 takes an "L" level and is supplied to the AND gate 13 and the output terminal 16. At this time, because the control signal Scon given to the AND gate 13 is inverted to have an "H" level, the clock signal S 2CK given from the PLL circuit 12 is supplied to the M² decoder 15 through the AND gate 13 to operate the M² decoder 15. In this way, by eliminating the sync pattern P SY and connecting data blocks, which lie before and after, as they are, a data stream satisfying the M² code rule is obtained. Only data D of the reception data is decoded at the M² encoder 15 and is decoded into the original digital data Dori in a synchronized state. Fig. 3 and Fig. 4 show a state where a unique sync pattern P SY is inserted in the data stream in the M² code. Also, Fig. 5 shows a diagram of a state transition of the M² code. 0:00 in this transition diagram of Fig. 5 show the bit state of the original digital data and that of the M² code, respectively, and numerals marked on each arrow indicate the occurrence rate. In this embodiment, the unique sync pattern P SY in the M² code means a pattern, which is never formed by the modulation rule of the M² code. For example, as evident from the state transition diagram of Fig. 5, any of the transition interval 2T, 2.5T or 3T is not continued next to 2.5T in the M² code and there exists no pattern having a transition interval equal to or larger than 3T [for example, 3.5T]. In sum, if any of 2T, 2.5T or 3T (further 3.5T) or plural ones after 2.5T is selected and their continuity is kept to form a sync pattern P SY , this pattern never coincides with the data D modulated with the M² code except the case where an error has occurred so as to become a unique sync pattern P SY . Namely, "a data pattern which does not exist in a data stream encoded into the M² code in the period of a unique sync pattern" means "a pattern in which a signal transition interval of any of 2T, 2.5T, 3T is continued next to 2.5T or a pattern having a signal transition interval equal to or larger than 3.5T". Hereunder, one example of the sync pattern P SY will be described referring to Figs. 3 and 4. Fig. 3A and Fig. 4 show six kinds of changes of DSV (digital sum variation) of two kinds of sync patterns P SY1 and P SY2 , Fig. 3B shows waveforms of these sync patterns P SY1 and P SY2 . The sync pattern P SY in this embodiment is formed by the succession of transition intervals 2.5T, which is never formed from the modulation rule of the M² code basically, and it has eight-bit cells (8T) as a whole. The DSV of the M² code lies between ±1.5. Also, at the bit cell boundary the value of the DSV is any one of 0, ±1. To cut the data stream at the boundary of arbitrary bit cells, insert a sync pattern P SY and put the DSV at the places other than the sync pattern P SY between ±1.5, the sync pattern P SY must have the same value and the same inclination in a change as the above-mentioned DSV in its first period L1 and its last period L2 ("L" level or "H" level period). For this reason, the period L1 of the beginning of the unique sync pattern P SY1 shown at the solid line in Fig. 3B is 0.5T, and its level is brought to an "L" level equal to the data level immediately before the unique sync pattern. In addition, the period L2 of the last of the unique sync pattern P SY1 is 1T, and its level is brought to the "L" level equal to the data level immediately before the sync pattern P SY1 . The change of DSV corresponding to this is shown at DSV1 indicated by a solid line of Fig.3A. In the sync pattern P SY2 indicated by a broken line of Fig.3B, its first period is 0.5T and its data level has an "H" level equal to the data level immediately before the unique sync pattern. Meanwhile, the last period of the pattern P SY2 is 1T and its data level is brought to the "H" level (P SY2 = P SY1 is established). The variations of DSV corresponding to this are shown by DSV2 and DSV3 indicated by broken lines of Fig. 3A. These DSV2 and DSV3 correspond to when the value of DSV at the beginning of a sync pattern is +1 or 0, respectively. Fig. 4 also shows variations of DSV when the sync patterns P SY1 and P SY2 are inserted. DSV4 and DSV5 correspond to the changes of DSV when the sync pattern P SY1 is inserted. DSV4 corresponds to when DSV immediately before the sync pattern P SY1 is -1 and DSV5 corresponds to when DSV immediately before the sync pattern P SY2 is 0. DSV6 represents a change of DSV when the sync pattern P SY2 is inserted and corresponds to when DSV immediately prior to the sync pattern P SY2 is -1. By this, even if the data stream is cut at the boundary of its arbitrary bit cells and the sync pattern P SY is inserted, it is possible to secure the shortest inversion interval 1T and reduce the longest inversion interval as much as possible (3.5T in this example). Meantime, in order to cut the data stream at its arbitrary bit cells and insert the sync pattern P SY or eliminate the sync pattern P SY and connect the data blocks lying before and after as they are so that the original data stream may be developed, the integration value of the DSV of the sync pattern P SY must be zero and the continuity of the high and low levels of each period of the above-mentioned beginning and last must be kept. As has been described, in order to bring the integration value of the sync pattern P SY to zero, the total length of the level "L" periods and that of the level "H" periods, which lie within the period [8T] of the unique sync pattern P SY must be one half of the entire length of said unique sync pattern and must be equal to each other. Consequently, the period of each level of "L" and "H" is 4T in Figs. 3 and 4, respectively. To keep the continuity of the high and low levels in each of the periods L1 and L2 of the beginning and the last, the number of signal transitions in the period [8T] of the unique sync pattern P SY must be even. As a result, the number of the signal transitions is made even (four times) in both Fig. 3 and Fig. 4. It is to be noted that the value of DSV may exceed ±1.5 in the period of the sync pattern P SY is unique. Meantime, the value of the DSV at the boundary of the bit cells is any of 0, ±1 as mentioned before. As a result, it is considered that the value and inclination of data immediately before the sync pattern P SY at the above-mentioned three points (DSV of 0, ±1) have two ways of an increase tendency and a decrease tendency in terms of the time-axis direction (3 x 2 = 6 ways as a whole). For this reason, in Fig. 3A, the state in which both of the increase and decrease directions (DSV2, DSV1) at the point of DSV = +1 and the increase direction (DSV3) at the point of DSV = 0 are indicated (three ways as mentioned above); in Fig. 4, the state in which both of the increase and decrease directions (DSV6, DSV4) at the point of DSV = -1 and the decrease direction (DSV5) at the point of DSV = 0 are indicated (three ways as described above). Namely, the DSV changes DSV1 to DSV3 shown in Fig. 3A and the DSV changes DSV4 to DSV6 shown in Fig. 4 are symmetrical with respect to the boundaries defined by the lines of DSV = 0. Next, the significance of the unique sync pattern P SY will be described. For an example, the sync patterns P SY indicated in Figs. 3 and 4 are compared with a 16-bit sync pattern, which is not unique. First, the probability that a 16-bit sync pattern which is not unique appears in a data stream is 2⁻¹⁶ ≅ 1.5 x 10⁻⁵ on the assumption that there is no error. Meanwhile, in the case of an 8-bit unique sync pattern, the probability that it appears in the data stream is zero if it is assumed that no error exits. Therefore, an error must be considered. Now, it is assumed that the bit error rate after the decoding of the M² code is 10⁻³ (this corresponds to the byte error rate 8 x 10⁻³ and is an awful error rate, which is usually unthinkable), the probability that the erroneous detection of data as a sync pattern P SY becomes ≅ 8 x 10⁻⁶. Assuming that the bit error rate is 10⁻⁴, this probability becomes ≅ 8 x 10⁻⁷. In this way, the 8-bit unique sync pattern P SY has the capability equal to or greater than that of the 16-bit sync pattern which is not unique. Also, the longest inversion interval is 3.5T as compared with 3T of the usual M² code (DSV may be ±3 at a maximum in the period of the sync pattern). According to this embodiment, there is an advantage that erroneous detection as a sync pattern of data in the data stream modulated with the M² code can be prevented to avoid the synchronization shift and the occurrence of erroneous synchronization. As a result, the frame synchronization can be established correctly and stably to perform digital data reproduction. Further, by eliminating the sync pattern and connecting the data blocks lying after and before as they are, a data stream satisfying the M² code rule can be obtained. Also, according to this invention, even if the data stream is cut at the boundary of its arbitrary bit cells and a sync pattern is inserted, the shortest inversion interval 1T can be secured and simultaneously the longest inversion interval can be shortened as much as possible (3.5T in the embodiment). Further, with respect to the probability that data is erroneously detected as a sync pattern, an 8-bit unique sync pattern is far lower than a 16-bit sync pattern which is not unique. For this reason, the 8-bit unique sync pattern can expect the capability equal to or greater than the 16-bit sync pattern which is not unique. As a consequence, the prevention of an increased redundancy for frame synchronization can be achieved. Next, a second embodiment of the invention will be described referring to the drawings. As shown in Figs. 6 to 13, in the second embodiment, the invention is applied to a sync pattern of eight-bit cells (8T) similarly to the first embodiment. In the second embodiment, a predetermined sync is inserted in original data and converted into the M² code. Figs. 6 to 11 show a system structure in which the invention is embodied. Description on the system structure will be given below. Encoding side Figs. 6 to 8 show a construction on the encoding side of a frame synchronizing system. Referring to Fig. 6, a sync pattern P SY of 8T given from a terminal 101 or original digital data Dori as a digital signal is supplied to an inversion control signal generator 102 for M² (hereunder called "control signal generator") and an inversion inhibiting control circuit 103. The circuits 102 and 103 operate in synchronism with a clock signal S CK , which has the bit cell frequency and is inputted from a terminal 104. At the control signal generator 102, an inversion control signal S INC is developed by the sync pattern P SY or the original digital data Dori supplied on the basis of the M² code modulation rule. The signal S INC is supplied to an AND gate 105. The inversion inhibiting control circuit 103 produces an inversion inhibiting signal S IOF with an "H" level supplied to the AND gate 105 when predetermined inversion inhibiting portions of the sync pattern P SY supplied sequentially by the clock signal S CK are detected while a sync period signal S SYT indicative of a sync insertion period is given from a terminal 107. The inversion inhibiting signal S IOF is output to have an "L" level in other period than the predetermined inversion inhibiting portions of said sync insertion period. In the AND gate 105, the inversion inhibiting signal S IOF input is inverted by an inverter when the signal S IOF has an "L" level. As a result, an inversion control signal S INC produced by the inversion control signal generator 102 is given to both of J and K terminals of a J-K flip-flop 106 (called "J-K FF" hereunder). RF data is produced from a Q terminal in response to the trailing edge of a clock signal S 2CK from a terminal 108 depending on the input state of both of the J and K terminals. The clock signal S 2CK is the one obtained by frequency doubling the clock signal S CK with the bit cell frequency. Also, in the case where the above-stated inversion inhibiting signal S IOF assumes an "H" level, it is inverted on the input side of the AND gate 105 to have an "L" level. As a result, the output of the AND gate 105 is brought to the "L" level to be given to the J and K terminals. The J-K FF 106 consequently holds the previous RF data and outputs it. Referring to Figs. 6 to 8, the circuit operation on the encoding side will be described. While the original data Dori is given to the terminal 101, the output with the "L" level is supplied to the AND gate 105 from the inversion inhibiting control circuit 103 as mentioned before. Since this output is inverted to have an "H" level, the inversion control signal S INC from the control signal generator 102 is directly supplied to the J and K terminals of the J-K FF 106. In response to the input state of the J and K terminals, the RF data is sequentially output in synchronism with the trailing edge of the clock signal S 2CK . In a sync insertion period in which a sync pattern P SY is inserted, sync patterns P SY1 ("00000101") and P SY2 ("01000101") represented by NRZ (non-return-to-zero) are supplied to the control signal generator 102. The generator 102 selects either of the two patterns depending on a state of the original digital data Dori. Further, the sync period signal S SYT is given to the inversion inhibiting control circuit 103. As shown in Fig. 7A, assuming that the sync pattern P SY1 "00000101" indicated by NRZ is selected, the inversion control signal S INC is developed by the control signal generator 102. As shown in Fig. 7C, the inversion control signal S INC rises by 1/2 T in the latter part of the bit cell in synchronism with the clock signal S CK when data is "0", while it rises by 1/2 T in the early part of the bit cell when data is "1". Here, T is a bit cell length of a signal prior to encoding and is an inverse number of the data rate. In the case of this sync pattern P SY1 , only the interval between fourth and fifth bit cells is regarded as an inversion inhibiting portion as mentioned later. Accordingly, no inversion inhibiting portions exist in the intervals between bit cells other than said fourth and fifth bit cells as indicated in Figs. 7C and 7E, and the inversion control signal S INC is directly supplied to the J-K FF 106. When a bit cell having an inversion inhibiting portion, i.e., the fourth bit cell BC4 of the sync pattern P SY1 is detected at the inversion inhibiting control circuit 103, the inversion inhibiting signal S IOF with an "H" level is produced from the inversion inhibiting control circuit 103 to the AND gate 105 as shown in Fig. 7D. An output having an "L" level from the AND gate 105 is consequently given to the J-K FF 106 during a period of the bit cell BC4 as indicated in Fig. 7E. The M² encoding process of the above-mentioned sync pattern P SY1 represented by NRZ will be described hereunder. (1) In a first bit cell BC1 ("0") of the sync pattern ("00000101"), assuming that an original Q output is zero, the Q output of the J-K FF 106 becomes "00" as shown in Fig. 7G since the conditions for varying the Q output are not met. In a 1/2 T period of the latter part of the bit cell BC1, the inversion control signal S INC assumes an "H" level as shown in Fig. 7C so that the signal S INC is directly output to both of the J and K terminals of the J-K FF 106. (2) As shown in Figs. 7C and 7E in a second bit cell BC2 ("0"), the J and K terminals of the J-K FF 106 have an "H" level. For this reason, the Q output of the J-K FF 106 is inverted with the trailing edge of the clock signal S 2CK to provide "11". (3) In a third bit cell BC3 ("0"), the Q output of the J-K FF 106 is inverted at the rising edge to provide "00" in a manner similar to the above (2). (4) As shown in Figs. 7D and 7E,in the fourth bit cell BC4 ("0"), the inversion inhibiting signal S IOF rises but the J-K terminals of the J-K FF 106 still have an "H" level. As a result, the Q output of the J-K FF 106 is inverted to provide "11" with the falling of the clock signal S 2CK . (5) In the fifth bit cell BC5 ("0"), an "L" level is given to the J-K FF 106 by the inversion inhibiting signal S IOF with the "H" level. The Q output consequently has the output of the above (4) to provide "11". (6) In a sixth bit cell BC6 ("1"), the signal S INC has an "H" level in a 1/2T period in the early part of the bit cell BC6. The "H" level is given to the J-K FF 106. In this case, the input of the J-K FF 106 has an "H" level, and the position where the clock signal S 2CK falls lies in the middle of the bit cell BC6. As a result, the Q output of the J-K FF 106 is inverted in the middle of the bit cell BC6. In other words, in the early part of the bit cell BC6, the previous output "1" is held, while "0" is produced in the latter part of the same cell. As a result, the Q output becomes "10". (7) As shown in Fig. 7C, in a seventh bit cell BC7 ("0"), because the inversion control signal S INC remains in the "L" level, the input of the J-K FF 106 assumes an "L" level, so that the Q output is brought to "00" to keep the state of the above (6). (8) In an eighth bit cell BC8 ("1"), the Q output is inverted in the middle of the bit cell BC8 in a similar manner to the above (6). Specifically, "0" of the output of the above (7) is retained in the early part, while in the latter part, "1" is produced after the inversion. The sync pattern P SY1 "00000101" represented by NRZ becomes "0011001111100001" through the process of the above (1) to (8), and a sync pattern P SY11 , which has been M²-coded with 16 bits, is developed depending on the rate of the clock signal S 2CK . A Q output shown in Fig. 7F is a pattern when the original Q output of the J-K FF 106 is "1", and is a sync pattern P SY12 with "0" and "1" inverted for the above-mentioned sync pattern P SY11 . Also, Fig. 8 shows a time chart similar to Fig. 7 when "01000101" represented by NRZ is adopted as a sync pattern P SY through detailed description is not given. With this, sync patterns P SY21 and P SY22 M²-coded with 16 bits at the rate of the clock signal S 2CK are developed in a manner similar to the above-mentioned sync patterns P SY11 and P SY12 . The sync pattern P SY21 in this case is ("1110001111100001"). In addition, the sync pattern P SY22 is ("0001110000011110"). Decoding side Figs. 9 to 11 show a structure on the decoding side of a frame synchronizing system. RF data having each frame structure (frame data composed of a sync pattern P SY and a data block D BL ) supplied from a terminal 110 is given to an M² decoder 111, a sync detection circuit 112 and a PLL circuit 113, respectively. The PLL circuit 113 extract a bit clock from the RF data and supplies a frequency doubled clock signal S 2CK to the M² decoder 111 and the sync detection circuit 112. The M² decoder 11 decodes the RF data supplied from the terminal 110 into original digital data Dori on the basis of the rule of M² code and produces the decoded data to an AND gate 114. In the sync detection circuit 112, the RF data given from the terminal 110 and a predetermined sync pattern P SY are compared. If the sync pattern P SY is detected in the RF data, a control signal Scon taking a "H" level is supplied to the AND gate 114 and an output terminal 115. The control signal Scon inputted to the AND gate 114 assumes an "L" level after being inverted. As a result, the original digital data Dori is not output from the AND gate 114. This state is continued during a sync period of 8T. After the last bit of the sync pattern P SY has passed the sync detection circuit 112, the control signal produced from the circuit 112 takes an "L" level and is fed to the AND gate 114 and the output terminal 115. At this time, the control signal Scon given to the AND gate 114 is inverted to have an "H" level. The original digital data Dori decoded at the M² decoder 111 is supplied to the output terminal 116 and taken out therefrom. The M² decoder 111 and the sync detection circuit 112 operate in synchronism with the clock signal S 2CK given from the PLL circuit 113. In this way, the sync pattern P SY is detected in the sync period (8T), and in periods other than the sync period, only the data block D BL of the RF data is decoded at the M² decoder 111 and reproduced into the original digital data Dori. Figs. 10 and 11 show examples of the sync detection circuit 112. A sync detection circuit 120 of Fig. 10 is the so-called shift register. The shift register 120 composed of 16 bits takes into the RF data in response to the clock signal S 2CK fed from the PLL circuit 113 (each signal of the 16 bits is represented by each code of A to P). When the RF data is moving in the shift register 120 depending on the clock signal S 2CK , the RF data is compared with a sixteen-bit sync pattern P SY predetermined for each of the 16 bits. The control signal Scon of "H" level is output from the sync detection circuit 120. C and D of A to P codes corresponding to 16 bits are control bits. In a sync detection circuit 125 of Fig. 11, the AND operation in AND gates 126 and 127 is performed with respect to two common ones of the above-mentioned four sync patterns P SY11 , P SY12 , P SY21 and P SY22 having 12 bits except for A to D bits (that is, with respect to the P SY11 and P SY21 ; the P SY12 and P SY22 ). The outputs of the AND gates 126 and 127 are given to an OR gate 128 to detect a sync pattern P SY . Now, all the four kinds of sync patterns P SY11 to P SY22 may be combined at the OR gate 128 though not shown. Namely, Referring to Figs. 12 to 13, an example of a unique sync pattern (sync data pattern) will be described. Fig. 12 shows an entire structure of the sync pattern. Figs. 13A and 13D indicate changes of DSV (digital sum variation) of the sync patterns P SY11 to P SY22 and B and C of Fig. 13 show waveforms of the sync patterns P SY11 and P SY22 , respectively. The sync pattern P SY shown in Fig. 12 is composed of an auxiliary data portion 30, "0" data 31 of one bit with "0" inserted, a control bit 32 with "0" or "1" inserted and a five-bit sync data pattern 33, and has an eight-bit cell length (8T) except for the data portion 30. The sync data pattern 33 is made up of fixed patterns 34, 35 and a unique data pattern 36 disposed between the fixed patterns 34 and 35. The "0" data 31 and the control bit 32 function to complete the starting point of the sync pattern with any one of the following three patterns based on the M² code: The "0" data 31 and the control bit 32 are also used to bring DSV at the starting point of the sync pattern to zero. This is to generate the shortest sync pattern P SY (sync pattern 33) among the sync patterns P SY 's having the same unique pattern. Namely, it is known that DSV of the M² code lies between ±1.5 and the value of DSV is either 0 or ±1 at the boundaries of the bit cells. Therefore, in a last point 37 of the data block D BL indicated in Figs. 13A and 13D, DSV takes either ±1 or 0 to provide six kinds of variations at this stage, because each of the three values has two directions of decrease and increase. Consequently, by providing the "0" data 31 subsequent to the data block D BL , the lines of DSV at both points of ±1 on the side of the starting point of the bit cell BC1 of the "0" data 31, i.e., the last point 37 of the data block D BL are reversed. For this reason, there are four kinds of variations of DSV at the bit cell BC1 of the "0" data 31. Namely, DSV = 1 indicates only the decrease direction (P SY22 ), DSV = 0 indicates both directions of increase and decrease (P SY11 , P SY21 ), and DSV = -1 indicates only the increase direction (P SY21 ). The value of DSV at the last point 38 of the "0" data bit cell BC1 takes any one of ±1, 0. Variations of DSV at the last point 38 of the cell BC1 are consequently completed to have any one of the above-mentioned three patterns. In the bit cell BC2 of the control bit, because "1" or "0" data whose polarity is inversion-controlled depending on DSV at the last point 38 of the bit cell BC1 of the "0" data is inserted, DSV at a last point 39 of the bit cell BC2 becomes 0 (that is, "0" for DSV = ±1, "1" for DSV = 0). As a result, the shortest sync pattern P SY can be generated among the sync patterns P SY 's having the same unique pattern, and DSV of the entire sync patterns P SY 's can be put within the range of ±1.5. The sync data pattern 33 is provided next to the control bit 32, and the unique data pattern 36 is disposed between the fixed patterns 34 and 35. It is to be noted that the unique data pattern 36 is a pattern having a signal transition interval, which is never developed from the M² code modulation rule. For example, as is evident from the state transition of Fig. 5, the signal transition interval of 2T, 2.5T or 3T or their combination does not continue after 2.5T. Further, no pattern with a transition interval exceeding 3T (for instance, 3.5T) exists. In sum, if the data pattern 36 is formed by selecting and continuing any one of 2T, 2.5T or 3T or plural ones of them, for instance, after 2T, the pattern 36 does not coincide with data modulated with the M² code except the case where an error has occurred. For this reason, the data pattern 36 becomes unique. Therefore, the pattern such as the data pattern 36 in which the continued occurrence of the signal transition intervals 2.5T and 2T takes place is a unique pattern. As a result, since the data pattern 36 is a unique pattern, which is never developed from the M² code modulation rule, the detection of the sync pattern P SY becomes easy and its erroneous detection can be prevented. The fixed pattern 34 with "0" inserted is to put DSV of the sync data pattern 33 within ±1.5. Also, the sync pattern 35 brings the DSV of the sync pattern 33 to zero and is to put DSV of a subsequent data block D BL within ±1.5. That is, since at the last end 39 of the bit cell BC2, DSV = 0 is established, there is a possibility that DSV may exceed the range of ±1.5 in the case where the signal transition interval in the data pattern 36 is 2.5T and where there is no fixed pattern with zero inserted. Also, if DSV of the data block D BL is started from zero, there is a case where DSV of the data block D BL is not put within the range of ±1.5 and where the condition for making DC free is not satisfied. It is to be noted that the data pattern 36 may be equal to or greater than 3.5T. DSV of the sync data pattern 33 in this case may exceed ±1.5. To keep a signal transition period of 2.5T, an inversion inhibiting point P IOF is set in the data pattern 36 as shown in Figs. 13A and 13C. This is achieved by keeping the Q output with an "L" level given to both of the J and K terminals of the J-K FF 106 as mentioned in detail above. As indicated in Figs. 13A and 13D, "00" are inserted in both bit cells adjacent to the inversion inhibiting point P IOF , i.e., the bit cells BC4 and BC5. In the usual M² code, the tendency of DSV reverses at said point P IOF . More specifically, what has an increase or decrease tendency at the bit cell BC4 becomes the one having a decrease or increase tendency at the next bit cell BC5. However, by the setting of the inversion inhibiting point P IOF , the tendency of DSV becomes continuous at the bit cells BC4 and BC5 to assure the signal transition interval of 2.5T or over a longer period. The above-mentioned control bit 32, the number of zeros of the digital signal and the presence or absence of inversion inhibition are shown at a table given below. The position of the inversion inhibiting point varies depending on a preset sync pattern P SY . As has been described above, if data to be inserted into such data as the "0" data 31, the control bit 32 ("0" or "1"), the fixed pattern 34 ("0"), the data pattern 36 (2.5T + 2T) and the fixed pattern 36 or various conditions giving limitations are represented by the NRZ format, the following two patterns become the sync pattern: "00000101" (sync pattern P SY1 ) "01000101" (sync pattern P SY2 ) By representing these sync patterns P SY1 and P SY2 with the clock rate of the clock signal S 2CK , the following four patterns become the sync patterns P SY11 to P SY22 as mentioned before: There four sync patterns P SY11 to P SY22 are all 16-bit represented. The sync patterns P SY11 and P SY12 correspond to the above-mentioned sync pattern P SY1 , and the sync patterns P SY21 and P SY22 correspond to the above-mentioned sync pattern P SY2 . With the correspondence of the value of each bit and the DSV variations, the sync patterns P SY11 , P SY12 , P SY21 and P SY22 are respectively indicated in Figs. 13A to 13D. As is clear in Figs. 13A to 13C, DSV = 0 is established at the last point 39 of the control bit 32 in any one of the sync patterns P SY11 , P SY12 , P SY21 and P SY22 . The fixed pattern 34 brought to zero can prevent the sync pattern 33 from being outside of the range of ±1.5. The provision of the inversion inhibiting point P IOF in the data pattern 36 enables maintaining the transition interval of the data pattern 36 at 2.5T. Further, DSV of at a last point 40 of the sync pattern P SY is brought to zero by the fixed pattern 35. It is to be noted although all of the "0" data 31, the control bit 32, the fixed pattern 34, etc. have a length of one bit in the second embodiment, they may have an arbitrary bit length depending on the bit length of a corresponding sync pattern. According to the second embodiment, the erroneous detection of M²-code modulated data in the data stream as a sync pattern can be prevented. As a result, a synchronization shift and a synchronization error can be prevented to establish a correct and stable synchronization so that a reproduction of a digital signal can be made with high fidelity. Among the sync patterns having a unique pattern, the shortest sync pattern can be formed without enhancing the redundancy for the frame synchronization. Additionally, DSV at the last point of a sync pattern is brought to zero by a fixed pattern subsequent to the sync pattern, data subsequent to the sync pattern starts at DSV = 0. As a result, DSV of a digital signal following the sync pattern can be placed within ±1.5 to assure a DC-free state and to simplify a decoding circuit. Further, in the second embodiment, since the fixed pattern is disposed before a data pattern, DSV of the entire sync pattern can be put within ±1.5 so as to maintain the entire sync pattern in the DC-free state.

Claims: A frame synchronizing method for generating encoded data with a frame synchronizing signal, the encoded data being based on original data and having a first logical bit state and a second logical bit state, said method comprising steps of: encoding said original data into an M² coded data stream; and providing a frame synchronizing signal having a unique pattern which does not appear in said M² coded data stream other than a period of time of said frame synchronizing signal, the total period of time when a level of said unique pattern is an "L" level being equal to the total period of time when the level of said unique pattern is an "H" level and being one half of the total period of time of said unique pattern and an initial period of time of said unique pattern is 0.5T followed directly by a transition, where T is the period of each bit cell of the original data; characterised by providing at least two unique patterns each having a different initial level, the number of level transitions in each said unique pattern being even, a last period of time of each said unique pattern being at least 1T and the level of the last period of time being equal to that of said initial period of time; inserting into said M² coded data stream one of said unique patterns having the level of said initial period of time which is equal to that of the M² coded data preceding said unique pattern. A frame synchronizing method as claimed in claim 1, wherein said unique pattern includes a period of time of 2.5T between two sequential level transitions followed by a period of time of 2T, 2.5T or 3T between two sequential level transitions. A frame synchronizing method as claimed in claim 1, wherein said unique pattern includes a period of time longer than 3T between two sequential level transitions. A frame synchronizing method as claimed in claim 1, 2 or 3, wherein said inserting step includes steps of generating a synchronizing pattern, forming said frame synchronizing signal, encoding said synchronizing pattern into encoded data including said unique pattern, and inserting said encoded data into said M² coded data stream. A frame synchronizing method as claimed in claim 4, wherein said synchronizing pattern includes a synchronizing data pattern with a predetermined bit number, "0" data preceding said synchronizing data pattern, and a control bit arranged between said "0" data and said synchronizing data pattern and having a level depending on DSV (digital sum variation) at a starting point of said synchronizing data pattern. A frame synchronizing system for generating encoded data with a frame synchronizing signal, the encoded data being based on original data and having a first logical bit state and a second logical bit state, said system comprising: means (2) for encoding said original data into an M² coded data stream; and means (4) for providing a frame synchronizing signal having a unique pattern which does not appear in said M² coded data stream other than a period of time of said frame synchronizing signal, the total period of time when the level of said unique pattern being an "L" level is equal to the total period of time duration when the level of said unique pattern is an "H" level and being one half of the total period of time of said unique pattern, and an initial period of time of said unique pattern being 0.5T followed directly by a transition, where T is the period of each bit cell of the original data, characterised by means for providing two unique patterns, each having a different initial level, the number of level transitions in each said unique pattern being even, a last period of time of each said unique pattern being at least 1T and the level of the last period of time being equal to that of said initial period of time; means (4) for inserting into said M² coded data stream one of said unique patterns having the level of said initial period of time equal to that of the M² coded data preceding said unique pattern. A frame synchronizing system as claimed in claim 6, wherein said unique pattern includes a period of time of 2.5T between two sequential level transitions followed by a period of time of 2T, 2.5T or 3T between two sequential level transitions. A frame synchronizing system as claimed in claim 6, wherein said unique pattern includes a period of longer than 3T between two sequential level transitions. A frame synchronizing system as claimed in claim 6, 7 or 8, wherein said means (4) for inserting includes means (4) for generating a synchronizing pattern forming said frame synchronizing signal, means (4) for encoding said synchronizing pattern into an encoded data including said unique pattern, and means (3) for inserting said encoded data into said M² coded data stream. A frame synchronizing system as claimed in claim 9, wherein said synchronizing pattern includes a synchronizing data pattern with a predetermined bit number, "0" data preceding said synchronizing data pattern, and a control bit arranged between said "0" data and said synchronizing data pattern and having a level depending on DSV (digital sum variation) at a starting point of said synchronizing data pattern.

Inventors: MASUZAKI KENSHIRO SONY CORPORA, SUZUKI HIDETO SONY CORPORATION, TACHI KATSUICHI SONY CORPORATI, TAKAYAMA JUN SONY CORPORATION, MASUZAKI, KENSHIRO SONY CORPORATION, SUZUKI, HIDETO SONY CORPORATION, TACHI, KATSUICHI SONY CORPORATION, TAKAYAMA, JUN SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: G11B20
IPC codes: G11B20, G11B27, H04L7, H04L25