Heterojunction bipolar transistor

Abstract: A semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer (13) and the surface of an emitter-base junction between an emitter layer (14,15) and the base layer (13) are covered with a high-resistivity layer (17) of compound semiconductor containing at least one constituent element common to the emitter layer (14,15) and the base layer (13). The transistor is formed by the emitter (14,15) and base layer (13) together with a collector layer (12) on a semiconductor substrate (11). The base layer (13) extends to a base contact layer (113) with an electrode (111). In this way, it is possible to overcome to a significant extent the lowering of a D.C. current gain (the emitter size effect) attributed to the reduction of an emitter size attendant upon the microfabrication of a device.

Description: The present invention relates to a bipolar transistor employing a heterojunction, and a method of manufacturing such a transistor. A bipolar transistor having a heterojunction, e.g. one of GaAs/AlGaAs, permits the impurity concentration of the base layer to be increased without causing degradation of the current gain. As a result, a lower base resistance can be achieved with the base layer thinner than in conventional transistors, and a high-speed operation becomes possible. Fig. 3 shows a schematic sectional view of a knwon mesa type heterojunction bipolar transistor. Usually, such a device is fabricated in the following way. An n⁺-type GaAs collector contact layer 32, an n-type GaAs collector layer 33, a p⁺-type GaAs base layer 34, an n-type AlGaAs emitter layer 35 and an n⁺-type GaAs emitter contact layer 36 are successively stacked and grown on a semi-insulating GaAs substrate 31 by MBE (molecular-beam epitaxy) or the like. Then, the surfaces of the base layer 34 and the collector contact layer 32 are exposed by mesa etching, and electrodes 37,38 and 39 respectively corresponding to an emitter, a base and a collector are formed. The device is then completed. To achieve high speed operation in the heterojunction bipolar transistor, it is very important to lower further the external base resistance and to reduce the base-collector capacitance. To achieve this, it is possible to microfabricate the device and to shorten its interelectrode distances. The microfabrication of the device, however, brings about the problem that the D.C. current gain of the device is reduced with reduction in the emitter size thereof (the emitter size effect), as discussed in, for example, Japanese Journal of Applied Physics, Vol 24, No 8 (1985), pp L596-L598. When an SiN film formed by sputtering is employed as a protective film, the emitter size effect mitigates as compared with those in the cases of other protective films (SiO₂ films produced by sputtering and CVD (chemical vapor deposition)). In practical use, however, the emitter size effect needs to be overcome to a greater extent. The prior art stated above has had the problem that the lowering of the current gain attendant upon the microfabrication of the device (the emitter size effect) cannot be overcome sufficiently. Therefore the present invention seeks to overcome the emitter size effect to a greater extent. EP-A-0101739 and EP-A-0184016 each disclose a semiconductor bipolar transistor in which a heterojunction is formed between a base layer and a emitter layer of different semiconductor materials. In EP-A-0101739, the emitter layer is formed by suitable doping of a polychrystalline or amorphous silicon layer. In EP-A-0184016, the base has a lead out portion formed by ion-implantation or selective epitaxial growth. According to a first aspect of the present invention there is provided a method of manufacturing a heterojunction bipolar transistor, comprising the steps of: forming a collector layer, base layer and emitter layer in that order on a semiconductor substrate, the base layer and the emitter layer being of different semiconductor materials so as to provide a heterojunction therebetween; forming an insulating film on a designated emitter region of said emitter layer; forming said emitter region by etching, using said insulating film as a mask, so as to expose an outer base region of the base layer; forming a high resistivity undoped compound-semiconductor layer on said outer base region so as to bury the emitter region, the high resistivity undoped compound-semiconductor layer contacting said emitter region, wherein the high resistivity undoped compound-semiconductor layer contains at least one element contained in both said emitter layer and said base layer as a constituent element thereof; forming a side-wall insulator film on the side-wall of said insulating film; forming a base contact layer by ion-implantation of an impurity exhibiting a same conductivity type as that of said base layer into said high resistivity undoped compound-semiconductor layer using said insulating film and said side-wall insulator film as a mask; and forming an emitter electrode, a base electrode and a collector electrode on said emitter region, said base region and said semiconductor substrate, respectively. Accordingly to a second aspect of the present invention there is provided a method of manufacturing a heterojunction bipolar transistor, comprising the steps of: forming a collector contact layer, a collector layer, a base layer and an emitter layer in that order on a semi-insulating semiconductor substrate the base layer and the emitter layer being of different semiconductor materials so as to form a heterojunction therebetween; forming an insulating film on a designated emitter region of said emitter layer; forming said emitter region by etching, using said insulating film as a mask, so as to expose an outer base region of the base layer; forming a high resistivity undoped compound-semiconductor layer on said outer bae region so as to bury said emitter region, the high resistivity undoped compound-semiconductor layer contacting said emitter region, wherein the high resistivity undoped compound-semiconductor layer contains at least one element contained in both said emitter layer and said base layer as a constituent element thereof; forming a side-wall insulator film on the side-wall of said insulating film; forming a base contact layer by ion-implantation of an impurity exhibiting a same conductivity type as that of said base layer into said high resistivity undoped compound-semiconductor layer using said insulating film and said side-wall insulator film as a mask; removing a desired region of said high resistivity undoped compound-semiconductor layer and said outer base layer to form a collector lead-out portion; forming said collector lead-out portion by ion-implantation of an impurity exhibiting a same conductivity type as that of said collector layer into said collector layer; and forming an emitter electrode, a base electrode and a collector electrode on said emitter region, said base region and said collector lead-out portion respectively. Thus, for example, consider a compound-semiconductor bipolar transistor having a structure in which a collector layer, a base layer and an emitter layer are successively stacked on a semiconductor substrate. According to the present invention it is proposed that the base layer includes an inner base region on which the emitter layer is placed in a substantially identical plan shape, and an outer base region which is other than the inner base region, that the periphery of a p-n junction region defined between the inner base region and the emitter layer, and a part of a front surface of the outer base region as surrounds the p-n junction are covered with a compound-semiconductor high-resistivity layer which contains at least one element contained in both the emitter layer and said base layer as a constituent element thereof. A base contact layer which is made of a compound semiconductor having the same conductivity type as that of said base layer may then be formed on a part of the outer base region not overlaid with the compound-semiconductor high-resistivity layer, and a base electrode is then formed on the base contact layer. It has been revealed that if the surface of the base and the surface of the emitter-base junction are covered with the compound-semiconductor high-resistivity layer, the D.C. current gain (h FE ) of the transistor becomes greater than if SiN protective film is used, so the emitter size effect can be further overcome. The reason for this is thought to be as follows. Since the compound-semiconductor high-resistivity layer contains a constituent element common to both the base layer and the emitter layer as described above, the lattice constant thereof is substantially equal to those of the base layer and emitter layer. Therefore, the surface state density of the high-resistivity layer at the interfaces thereof with the base layer and emitter layer become much lower than in the case of the SiN film, which has previously been used. As a result, recombination currents in the base surface and the emitter-base junction surface decrease significantly. In addition, by providing the base electrode through the compound-semiconductor high-resistivity layer made of, for example, the high-resistivity epitaxial layer, the parasitic capacitances between the emitter and the base and between the collector and the emitter may be decreased. Thus, a high-speed operation may be achieved. Moreover, in a semiconductor device of the present invention, the base contact layer and the compound-semiconductor high-resistivity layer may be formed so as to be substantially even with the emitter layer (or an emitter contact layer if formed), and a planar structure implemented with an Si device can be obtained so as to facilitate integration. Also, the formation of the base contact layer may lower not only the contact resistance of the base region relative to the base electrode, but also the D.C. resistance between the base electrode and the base region, so that the resistance of the base can be lowered. Embodiments of the invention will now be described in details, by way of example, with reference to the accompanying drawings, in which: Figs. 1(a) - 1(g) are processing sectional views of a semiconductor device in Embodiment 1 of the present invention; Fig. 2 is a sectional view of a semiconductor device in Embodiment 2 of the present invention; and Fig. 3 is a sectional view of a prior art semiconductor device. Embodiment 1: This embodiment will be described with reference to processing sectional views shown in Figs. 1(a) - 1(g). On an n⁺-type GaAs substrate 11, and using MBE or the like, there are successively stacked and grown an n-type GaAs collector layer 12 having a thickness of about 400 - 500 x 10⁻⁹m (4000 - 5000 Å), a p⁺-type GaAs base layer 13 having a thickness of about 50 - 100 x 10⁻⁹m (500 - 1000 Å), an n-type AlGaAs emitter layer 14 having a thickness of about 100 x 10⁻⁹m (1000 Å), and an n⁺-type GaAs emitter contact layer 15 having a thickness of about 100 x 10⁻⁹m (1000 Å). Thereafter, using conventional CVD and lithographic techniques, an SiN film mask 16 which corresponds to the shape of an emitter pattern is formed on the emitter contact layer 15 (Fig. 1(a)). Subsequently, an emitter region which is made up of the n⁺-type GaAs emitter contact layer 15 and the n-type AlGaAs layer 14 is formed using the SiN film mask 16 and by dry etching with CF₄ or the like (Fig. 1(b)). At the next step, any of proton, boron and oxygen is ion-implanted using the SiN film mask 16, whereby the part 112 of the collector layer 12 underlying the outer base region of the base layer 13 is rendered insulating (Fig. 1(c)). Next, an undoped GaAs layer 17 is grown on the external base layer 13 by MOCVD (organometallic CVD) or the like, thereby to bury the emitter layer 14 and the emitter contact layer 15 (Fig. 1(d)). Here, even the emitter contact layer 15 is buried for flattening the front surface of the device. To the accomplishment of that relief of the emitter size effect which is the original object of the present invention, it suffices to bury only the emitter layer 14. In addition, when the side walls of the emitter layer 14 and emitter contact layer 15 are made vertical or inverted-mesa-like by the etching illustrated in Fig. 1(b), the front surface of the device is perfectly flattened by the burying growth based on the aforementioned MOCVD. Subsequently, the SiN film mask 16 is formed with a side-wall insulator film 18 of SiO₂ (Fig. 1(e)), and using them as a mask, an acceptor impurity such as beryllium (Be) is implanted, whereupon it is activated by predetermined annealing so as to form a base contact layer 113 (Fig. 1(f)). Next, ohmic electrodes 19 and 110 made of AuGe/Au are respectively formed on the emitter contact layer 15 and the n⁺-type GaAs substrate 11 to serve as a collector contact layer, and an ohmic electrode 111 made of Au/Zn/Au is formed on the base layer 13, by evaporation and a lift-off method. Then, the heterojunction bipolar transistor of the present invention is finished up (Fig. 1(g)). When the D.C. current gain of this transistor was measured, a value nearly equal to that in the case of a large area was obtained even in case of a small emitter size. It has accordingly been found that the emitter size effect is sufficiently relieved. Besides, the heterojunction bipolar transistor of this embodiment has its feature in that, as shown in Fig. 1(g), the front surface of the base and the surface of the emitter-base junction are covered with the high-resistivity epitaxial layer 17 made of the same compound semiconductor as that of the base. Embodiment 2: In Embodiment 1, the collector is led out from the rear surface of the n⁺-type GaAs substrate, whereas in Embodiment 2, a collector is led out from the same plane as that of an emitter or a base. Now, this embodiment will be described with reference to Fig. 2. On a semi-insulating GaAs substrate 21 and in the same manner as in Embodiment 1, there are successively grown an n⁺-type GaAs collector contact layer 22, an n-type GaAs collector layer 23, a p⁺-type GaAs base layer 24, an n-type AlGaAs emitter layer 25 and an n⁺-type GaAs emitter contact layer 26 which are the constituent portions of a transistor. Thereafter, an emitter electrode 211 and a base electrode 212 are formed via the steps of Figs. 1(a) - 1(g) illustrated in Embodiment 1. Here, a collector electrode 214 is formed after an n⁺-type collector lead-out portion 213 has been formed by etching a high-resistivity epitaxial layer 27 as well as the base layer 24 and ion-implanting a donor impurity such as Si. Numeral 29 in Fig. 2 indicates the part of the collector layer rendered insulating, and numeral 210 a base contact layer. With this transistor, the same effect as in Embodiment 1 is attained. Moreover, in this embodiment, the emitter electrode 211, base electrode 212 and collector electrode 214 are formed on the front surface of the device, so that the versatility of circuit designs is high. In a case where the isolation of the high-resistivity epitaxial layer 17 or 27 in Embodiment 1 or 2 stated above is insufficient, the SiO₂ film 18 or an SiO₂ film 28 is removed after the formation of the emitter and base electrodes (Fig. 1(g) or Fig. 2), and the ion implantation of proton, boron, oxygen or the like is carried out using the electrodes 19, 111 or 211, 212 as a mask, whereby the effect of the isolation of the high-resistivity epitaxial layer 17 or 27 can be more enhanced. Besides, although the epitaxial layer (a single crystal) has been employed as the high-resistivity semiconductor layer in Embodiments 1 and 2 stated above, it may well be replaced with an amorphous layer or a polycrystalline layer. In this case, the insulation between the emitter and the base is enhanced. According to the present invention, recombinations in the surface of a base-emitter junction can be remarkably reduced, so that the emitter size effect can be removed. In addition, an emitter-base parasitic capacitance can be lowered, and the implementation of a planar structure is possible. Accordingly, a heterojunction bipolar transistor capable of higher-speed operation can be realized owing to the microfabrication of the device. Besides, since an emitter-base distance is shortened by utilizing a side-wall insulator film, the resistance of a base can be lowered with a favorable controllability. Further, since an acceptor impurity is implanted into an undoped GaAs layer, a base lead-out portion which is stable and which is of lower resistance can be formed. Owing to such lowering in the base resistance, a heterojunction bipolar transistor having an excellent high-frequency response has been realized.

Claims: A method of manufacturing a heterojunction bipolar transistor, comprising the steps of: forming a collector layer (12), base layer (13) and emitter layer (14) in that order on a semiconductor substrate (11), the base layer (13) and the emitter layer (14) being of different semiconductor materials so as to provide a heterojunction therebetween; forming an insulating film (16) on a designated emitter region of said emitter layer (14); forming said emitter region by etching, using said insulating film (16) as a mask, so as to expose an outer base region of the base layer (13); forming a high resistivity undoped compound-semiconductor layer (17) on said outer base region so as to bury the emitter region, the high resistivity undoped compound-semiconductor layer (17) contacting said emitter region, wherein the high resistivity undoped compound-semiconductor layer (17) contains at least one element contained in both said emitter layer (14) and said base layer (14) as a constituent element thereof; forming a side-wall insulator film (18) on the side-wall of said insulating film (16); forming a base contact layer (13) by ion-implantation of an impurity exhibiting a same conductivity type as that of said base layer (13) into said high resistivity undoped compound-semiconductor layer (17) using said insulating film (16) and said side-wall insulator film (18) as a mask; and forming an emitter electrode (19), a base electrode (111) and a collector electrode (110) on said emitter region, said base region and said semiconductor substrate, respectively. A method of manufacturing a heterojunction bipolar transistor according to claim 1, including a further step of forming an emitter contact layer (15) on said emitter layer (14) before forming said insulating film (16) said insulating film (16) being formed on the emitter contact layer (15) and wherein the emitter contact layer (15) is etched, using said insulating film (16) as a mask so as to form an emitter contact region on the emitter region. A method of manufacturing a heterojunction bipolar transistor according to claim 2, including a further step of rendering a part (112) of said collector layer (12) underlying said outer base region, insulating by ion-implantation using said insulating film (16) as a mask, before said step of forming said high resistivity undoped compound-semiconductor layer (17). A method of manufacturing a heterojunction bipolar transistor according to claim 3, wherein ions implanted in said ion-implantation are at least one selected from a group consisting of proton, boron and oxygen. A method of manufacturing a heterojunction bipolar transistor according to claim 3, wherein said semiconductor substrate (11) consists of n⁺type Gabs, said collector layer (12) consists of n-type Gabs, said base layer (13) consists of p+type Gabs, said emitter layer (14) consists of n-type AlGaAs, said emitter contact layer (15) consists of N⁺-type Gabs and said high resistivity undoped semiconductor layer (17) consists of undoped Gabs. A method of manufacturing a heterojunction bipolar transistor according to claim 2, wherein the high resistivity undoped compound-semiconductor layer (17) is formed so as to bury both the emitter region and emitter contact region. A method of manufacturing a heterojunction bipolar transistor according to claim 6, wherein the high resistivity undoped compound-semiconductor layer (17) has a top surface, and is formed such that the top surface thereof is in a same plane as a top surface of the emitter contact region. A method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein the high resistivity undoped compound-semiconductor layer (17) has a top surface, and is formed such that the top surface thereof is in a same plane as a top surface of the emitter region. A method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein the same compound-semiconductor material is used for the base layer (23) and for the high resistivity undoped compound-semiconductor layer (17). A method of manufacturing a heterojunction bipolar transistor according to any one of the preceding claims, wherein the different semiconductor materials are different compound-semiconductor materials. A method of manufacturing a heterojunction bipolar transistor according to claim 1, including further steps of: removing said side-wall insulator film (18) after the formation of said emitter and base electrodes; and carrying out ion-implantation into said high resistivity undoped compound-semiconductor layer (17) using said emitter and base electrodes as a mask to enhance the effect of the isolation of said high resistivity undoped compound-semiconductor layer, after said removal of said side-wall insulator layer (18). A method of manufacturing a heterojunction bipolar transistor according to claim 11, wherein an ion implanted in said ion-implantation is at least one selected from a group consisting of proton, boron and oxygen. A method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein said high resistivity undoped compound-semiconductor layer (17) is selected from a group consisting of single crystal, polycrystalline and amorphous. A method of manufacturing a heterojunction bipolar transistor, comprising the steps of: forming a collector contact layer (22), a collector layer (23), a base layer (24) and an emitter layer (25) in that order on a semi-insulating semiconductor substrate (21), the base layer (24) and the emitter layer (25) being of different semiconductor materials so as to form a heterojunction therebetween; forming an insulating film on a designated emitter region of said emitter layer (25); forming said emitter region by etching, using said insulating film as a mask, so as to expose an outer base region of the base layer (24); forming a high resistivity undoped compound-semiconductor layer (27) on said outer base region so as to bury said emitter region, the high resistivity undoped compound-semiconductor layer (27) contacting said emitter region, wherein the high resistivity undoped compound-semiconductor layer (27) contains at least one element contained in both said emitter layer (25) and said base layer (24) as a constituent element thereof; forming a side-wall insulator film (28) on the side-wall of said insulating film; forming a base contact layer (210) by ion-implantation of an impurity exhibiting a same conductivity type as that of said base layer into said high resistivity undoped compound-semiconductor layer (27) using said insulating film and said side-wall insulator film (28) as a mask; removing a desired region of said high resistivity undoped compound-semiconductor layer (27) and said outer base layer (24) to form a collector lead-out portion (213); forming said collector lead-out portion by ion-implantation of an impurity exhibiting a same conductivity type as that of said collector layer into said collector layer (23); and forming an emitter electrode (211), a base electrode (212) and a collector electrode (214) on said emitter region, said base region and said collector lead-out portion (213) respectively. A method of manufacturing heterojunction bipolar transistor according to claim 14, including a further step of forming an emitter contact layer (26) on said emitter layer (25) before forming said insulating film, said insulating film being formed on the emitter contact layer (26), and wherein the emitter contact layer (26) is etched, using said insulating film as a mask so as to form an emitter contact region on the emitter region. A method of manufacturing a heterojunction bipolar transistor according to claim 15, including a further step of rendering a part (29) of said collector layer, underlying said out base region, insulating, by ion-implantation using said insulating film as a mask, before said step of forming said high resistivity undoped compound-semiconductor layer (27). A method of manufacturing a heterojunction bipolar transistor according to claim 16, wherein ions implanted in said ion-implantation are at least one selected from a group consisting or proton, boron and oxygen. A method of manufacturing a heterojunction bipolar transistor according to claim 15, wherein the high resistivity undoped compound-semiconductor layer (27) is formed so as to bury both the emitter region and emitter contact region. A method of manufacturing a heterojunction bipolar transistor according to claim 18, wherein the high resistivity undoped compound-semiconductor layer (27) has a top surface, and is formed such that the top surface thereof is in a same plane as a top surface of the emitter contact region. A method of manufacturing a heterojunction bipolar transistor according to claim 15, wherein the high resistivity undoped compound-semiconductor layer (27) has a top surface, and is formed such that the top surface thereof is in a same plane as a top surface of the emitter region. A method of manufacturing a heterojunction bipolar transistor according to claim 16, wherein said semi-insulating semiconductor substrate (21) consists of semi-insulating Gabs, said collector lead-out portion consists of N⁺-type Gabs, said collector layer (23) consists of n-type Gabs, said base layer (24) consists of p⁺-type Gabs, said emitter layer (25) consists of n-type AlGaAs, said emitter contact layer (26) consists of N⁺-type Gabs and said high resistivity undoped compound-semiconductor layer (27) consists of undoped Gabs. A method of manufacturing a heterojunction bipolar transistor according to claim 14, including further steps of: removing said side-wall insulator film (28) after the formation of said emitter and base electrodes (211, 212); and carrying out ion-implantation into said high resistivity undoped compound-semiconductor layer (27) using, said emitter and base electrodes as a mask, to enhance the effect of the isolation of said high resistivity undoped compound-semiconductor layer (27), after said removal of said side-wall insulator layer (28). A method of manufacturing a heterojunction bipolar transistor according to claim 22, wherein an ion implanted in said ion-implantation is at least one selected from a group consisting of proton, boron and oxygen. A method of manufacturing a heterojunction bipolar transistor according to claim 14, wherein said high resistivity undoped compound-semiconductor layer (27) is selected from a group consisting of single crystal, polycrystalline and amorphous.

Inventors: KOBAYASHI MASAYOSHI, KUSANO CHUSHIRO, MITANI KATSUHIKO, TAKAHASHI SUSUMU, TANOUE TOMONORI, KOBAYASHI, MASAYOSHI, KUSANO, CHUSHIRO, MITANI, KATSUHIKO, TAKAHASHI, SUSUMU, TANOUE, TOMONORI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1988
Main classification: H01L29
IPC codes: H01L29, H01L21