DIGITAL DATA DISPLAY APPARATUS

Abstract: A digital data rester display apparatus in which character codes, character attributes and field attributes are used. Means are provided to specify the mode of operation and to select the control mode. Depending on the specified mode the storage pattern in the re-fresh memory is varied. A first control mode stores field attributes only and the second control mode stores character attributes. A third mode mixes both field and character attributes. In the first mode the re-fresh memory stores either field attributes or character codes in such of a plurality of sequentially addressable locations. In the second mode character codes and character attributes are stored at alternate address.

Description: The present invention generally relates to a raster scanning type digital data display apparatus, and more particularly, to a display apparatus having an attribute controlling function. Techniques using control codes called attributes to control display modes of characters are well known and there exist two such typical techniques. The first uses character attributes each of which determines the display mode of each character. Display apparatuses according to this technique include those of the type which stores character codes and character attributes alternately at successive storing locations of a memory and those of the type which stores both of them in separate memories or memory areas. The second uses field attributes each of which determines the display mode of each group of characters. In this technique, each field attribute is stored for any desired number of characters in successive storing locations of a memory. Generally, a display apparatus according to either said first or second technique is constructed so as to enable only the use of either field attributes or character attributes but not the use of both of them. In consideration of such circumstances, there have been proposed thereafter a third technique which enables the use of these two kinds of attributes. Namely, a technique disclosed in Japanese Published Unexamined Patent Application No. 55-78336 has enabled the use of these two kinds of attributes based on the use of the codes having the special format illustrated in Fig. 9. More specifically, the higher three bits B8-B10 of a code consisting of eleven bits B0-B10 are allocated as a character attribute, and the bit B7 is set to 0 or 1 to indicate whether the lower seven bits B0-B6 constitute a character code or a field attribute. While said third technique is desirable to attain a versatile attribute control, the technique disclosed in the above Japanese Published Unexamined Patent Application No. 55-78336 has a problem that storing spaces of a memory cannot be effectively used. Namely, since each of the codes stored in successive storing locations includes a portion allocated as a character attribute, it is apparent that such character attribute portions in all the codes in the memory would be of no use and the spaces storing them would be wasted in such a situation that only field attributes are used without using any character attribute. Although only three bits are included in each of the character attribute portions in the above prior technique, it would generally be necessary in these days to allocate many more bits as a character attribute for determining various display modes, such as a reverse display, a high intensity display, blinking, a display with underlining, etc., which would aggravate said uselessness. Further, the above prior technique using the special code format cannot be adapted for use in the ordinary information processing in bytes (8 bits) and requires a special bus for transmitting the information. The display apparatus according to the present invention uses three kinds of codes, i.e., character codes (CC's), character attributes (CA's), and field attributes (FA's), without using such codes of a special format including character attributes as used in the above stated prior technique. There is provided a mode specifying means which can be set so as to specify selectively at least two control modes for the control of the attributes. Depending on the modes specified by said means, the storing mode of a refresh memory and the operation rate of an address generating means associated therewith are varied. A first control mode is a mode using FA's only and a second control mode is a mode using at least CA's. In the first control mode, the refresh memory stores either an FA or a CC in each of a plurality of sequentially addressable storing locations, and in the second control mode, basically stores CC's and CA's alternately in a plurality of sequentially addressable storing locations. The address generating means for reading out display data in the refresh memory to be displayed by the display means operates so as to generate successive address signals at a predetermined operation rate in the first control mode, and at an operation rate which is double the predetermined operation rate in the second control mode. In an embodiment of the present invention which will be explained below, the first control mode is an FA only mode and the second control mode is a CA only mode or an FA/CA mixed mode. In the CA only mode, only CA's are used. In the FA/CA mixed mode, both of FA's and CA's are employed and FA's are stored instead of some of the CA's. According to the invention there is provided a digital data display apparatus of the type which controls display modes of characters with attributes in displaying them by a raster scanning type display means, characterised by comprising: a mode specifying means settable so as to specify selectively either a first control mode using field attributes only or a second control mode using at least character attributes; a refresh memory having a plurality of sequentially addressable storing locations for storing either a field attribute or a character code in each of said plurality of storing locations when said mode specifying means specifies said first control mode and for storing character codes and character attributes alternately in said plurality of storing locations when said mode specifying means specifies said second control mode; and an address generating means associated with said mode specifying means and said refresh memory for generating address signals to read out character codes or attributes in said refresh memory, which means generates successive address signals at a predetermined operation rate when said mode specifying means specifies said first control mode and generates successive address signals at an operation rate which is double the predetermined operation rate when said mode specifying means specifies said second control mode. In order that the invention may be fully understood a preferred embodiment thereof will now be described with reference to the accompanying drawings in which, Fig. 1 illustrates an embodiment of the display apparatus according to the present invention. Fig. 2 illustrates a structure of the timing signal generator. Fig. 3 illustrates the contents of the mode register. Fig. 4 illustrates the storing modes of the display data in the three control modes. Fig. 5 illustrates the formats of CC's, CA's, and FA's used in the three control modes. Figs. 6 through 8 illustrate the timing of the operations of the display apparatus in Fig. 1 in the three control modes. Fig. 9 illustrates a format of display data used in the prior art. Fig. 1 illustrates a preferred embodiment of the display apparatus according to the present invention. A refresh memory 14 has stored therein display data selectively including CC's, CA's, and FA's under the control of a microprocessing unit (MPU) 10. The display data are read out according to address signals generated from an address generator 15 and transmitted to an attribute register circuit 20 or a CC register 27 through a buffer register 18 for controlling timing and a code/attribute register 19. The CC register 27 temporarily retains CC's and supplies them as addresses of a character generator 28. The character generator 28 supplies bit patterns according to the CC's and the line counts generated from a timing signal generator 13 in an operation controller 11, to a video and attribute control circuit 29. The control circuit 29 receives also attribute signals generated from the attribute register circuit 20 and causes the bit patterns to be displayed accordingly on a CRT 30. The attribute register circuit 20 includes a CA register 21 for retaining CA's and an FA register 22 for retaining FA's. This will be described later more in detail. An example of a specific structure of the timing signal generator 13 provided in the operation controller 11 is illustrated in Fig. 2. An oscillator 41, a dot counter 42, a column (or character) counter 43, a line counter 44, and a row counter 45 are respectively of any known structure and closely related to the display modes on the screen of the CRT 30 (Fig. 1). As an example, now assume that a display consisting of 25 rows × 80 columns (characters) is generated on the screen with each row consisting of 15 lines (scanning lines) and each column having a lateral width of 9 dots. In this case, the dot counter 42 counts 0 through 8 repeatedly and generates C-clocks, each being one ninth of a dot clock. The column counter 43 counts 0 through 99 repeatedly according to the clocks and generates column counts indicating columns (character times) being scanned onto an output line 43a and also provides the line counter 44 with a pulse each time the counting is repeated. The line counter 44 counts 0 through 14 repeatedly and generates line counts indicating lines being scanned onto an output line 44a and also provides the line counter 45 with a pulse each time the counting is repeated. The row counter 45 counts 0 through 27 repeatedly and generates row counts indicating rows on the screen onto an output line 45a. In this example, the column counts 3 through 82 of the column counts 0 through 99 correspond to display times and the remaining column counts correspond to horizontal blanking times. Further, the row counts 0 through 24 of the row counts 0 through 27 correspond to the display times and the remaining row counts correspond to perpendicular blanking times. The timing signal generating circuit 13 in Fig. 2 further includes two logic circuits 46 and 47. The logic circuit 46 generates increment enable signals and address load signals on lines 32 and 33 according to the column counts. The address load signals are generated according to the appropriate column counts during the horizontal blanking times, and the increment enable signals are generated while the column counts are 0 through 79. These signals are used in association with the address generator 15, as to be explained later. The logic circuit 47 generates buffer clock signals, having a frequency which is double the frequency of C-clocks, according to the C-clocks onto a line 36. The signals determine the timing in the operations of the above stated registers 18 and 19. Referring again to Fig. 1, the operation controller 11 is further provided with a mode register 12. For example, as illustrated in Fig. 3, the mode register 12 stores eight bits B0-B7 for controlling the various operation modes for the display apparatus. In this example, the bits B5 and B4 are used to specify the attribute control modes, and as illustrated, the FA only, CA only, and FA/CA mixed modes are specified respectively with 10, 01, and 00. The meanings of the three control modes and the storing modes of the display data in the refresh memory 14 are as follows. (a) FA Only Mode: Only FA's are used. The storing mode of FA's and CC's in the refresh memory in this case is illustrated by (A) in Fig. 4. In the storing location specified with the address P, a field attribute FA1 has been stored and is used to control the display mode of the succeeding character codes CC1-CC3. In the location of the address P + 4, the next field attribute FA2 has been stored and is used to control the display mode of the succeeding character codes CC4-CC8. (b) CA Only Mode: Only CA's are used. In this case, as illustrated by (B) in Fig. 4, the character codes CC1-CC5 and the character attributes CA1-CA5 associated therewith are stored alternately in the successive storing locations. In this embodiment, CC's are stored in the even-numbered address locations and CA's are stored in the odd-numbered address locations. (c) FA/CA Mixed Mode: Both of FA's and CA's are used. As illustrated by (C) in Fig. 4, the display data storing mode in this case may be referred to as a mode little modified from the CA only mode storing CC's and CA's alternately. Namely, in this mode, one or more FA's are stored selectively in one or more of the odd-numbered address locations for storing one or more CA's, and an FA flag code (FAF) is stored instead of a CC in the even-numbered address location immediately prior thereto. The FAF is a code indicating that an FA (FA1 in this case) exists in the next address location. The mode specifying bits B4 and B6 of the mode register 12 are set either by the MPU 10 according to the instruction of the user or by the operation controller 11 using line attributes. To explain further the latter case, since a plurality of line attributes including control information for a plurality of rows on the screen are generally used for the control of display, a method of introducing mode specifying information into each of the line attributes and setting the mode register 12 for each row according to the mode specifying information in the line attributes may be adopted. As well known in the art, the plurality of line attributes are stored in the refresh memory 14 or any other appropriate storing means as a table and sequentially read out in synchronisation with the scanning of the screen to be used by the operation controller 11. According to this method, the attribute control mode can be easily changed for each row, so that it is possible, for example, to divide the screen into a plurality of segments for a plurality of applications and use a different attribute control mode for each of the segments. Fig. 5 illustrates the formats of the display data used in the respective control modes. In any case, codes are used in bytes (bits B0-B7). First, in case of the FA only mode, as illustrated by (A) in Fig. 5, each code is discriminated to be an FA or a CC by binary 1 or 0 of the bit B7. In case of the CA only mode, as illustrated by (B) in Fig. 5, all of the eight bits are used as a CC or a CA. It is not needed in this mode to use one bit to discriminate between a CC and a CA because it has already been known that those in the even-numbered address locations are CC's and those in the odd-numbered address locations are CA's. In case of the FA/CA mixed mode, the format illustrated by (C) in Fig. 5 is used. As stated before, an FAF has only the function of indicating that an FA follows immediately thereafter and the bit B7 has been set to be 1. A plurality of bits in an FA are all used as attribute information. A CA has the bit B7 set to be 0. All the bits in a CC can be used to indicate a character. In any mode, a CA and an FA have respectively a plurality of bits allocated to control, for example, a reverse display, blinking, a high intensity display, a display with underlining, a blank, and so on. Next, the operation of the address generator 15 in Fig. 1 will be explained more in detail. The address generator 15 is a loadable counter and the operation controller 11 has a function of loading start addresses to the address generator 15 via a line 34 at the timing of the address load signals stated before. A start address specifies the first of a series of storing locations in the refresh memory 14 storing the display data to be displayed in one row on the screen. The technique employing start addresses itself is well known in the art and, generally, a plurality of ad- dresses for a plurality of rows are retained as a table in an appropriate storing means to be used as required. The operation controller 11 is either of the structure incorporating therein such a table storing means or of the structure allocating specified segments in the refresh memory 14 as a table storing means and accessing them. The address generator 15 performs counting according to the clocks provided from a multiplexer 16 while increment enable signals are supplied through the line 32 after a start address is loaded. The multiplexer 16 receives C-clocks and modified C-clocks generated from a divider 17 having the function of dividing the frequency of C-clocks into a half and gates either of them as clocks for the address generator 15 according to select signals on a line 35. More specifically, the operation controller 11 has a function of providing the multiplexer 16 with select signals which cause modified C-clocks of the outputs of the divider 17 to be gated in the FA only mode and cause C-clocks to be gated in the FA/CA mixed mode. In this embodiment, the operation controller 11 operates so as to load the address generator 15 with the same start address repeatedly for each count of the line counter 44 while the row counter 45 is indicating one row count. If a row buffer is provided at the output end of the refresh memory 14 to retain the display data for one row to be displayed, the loading of the start address would be needed to be performed only once for each row to be displayed. In that case, a series of corresponding display data are read out into the row buffer only once for each row to be displayed to be used repeatedly for each of a plurality of lines in each row to be displayed. Now, referring to Fig. 1 and Figs. 6 through 8, the operation sequence of the display apparatus for handling the display data illustrated in Fig. 4 will be explained in detail. Fig. 6 illustrates the timing in the operation of handling the display data illustrated by (A) in Fig. 4 in the FA only mode. First, the address generator 15 is loaded with P as a start address. In the FA only mode, since it is required to read out the display data one by one from sequential storing locations in the refresh memory in synchronisation with column counts indicating sequential character display times, the address generator 15 increments the address (illustrated in Fig. 6 as RM address) according to successive transitions of modified C-clocks, having half the frequency of C-clocks. According to the successive addresses, data (RM data) are read out from a series of storing locations. These data are sequentially transferred to the buffer register 18 and the code/attribute register 19 according to buffer clock signals. The registers 18 and 19 are respectively constructed with eight D-type flip-flops (D-FF's). Next, prior to continuing further the explanation of the operation, the structure of the attribute register circuit 20 provided at the output end of the register 19 will be explained. The CA register 21 and the FA register 22 are the registers for retaining CA's and FA's, respectively, and are respectively constructed with eight D-type latches. The CA register 21 latches input data according to positive transitions of C-clocks. The FA register 22 latches input data according to positive transitions of C-clocks passing through an AND circuit 24 only when an FA detector 23 is generating outputs. The FA detector 23 has the function of detecting the bit B7 = 1 of the above stated FA and FAF and generating outputs. The outputs of the FA register 22 are directly transferred to an OR circuit 26, while the outputs of the CA register 21 are supplied to the OR circuit 26 through an AND circuit 25 only when CA enable signals are generated. The CA enable signals are generated from the operation controller 21 only in the FA only mode and the FA/CA mixed mode. Accordingly, in the FA/CA mixed mode, an OR output between an FA and a CA is used as an attribute signal. For example, when an FA specifies a reverse display and a CA specifies blinking, both of the reverse and blinking displays are performed as to a character associated with the CA. Now, returning back to the explanation of the timing of the operation illustrated in Fig. 6, the data read out first which is the field attribute FA1 is received by the FA register 22 and transferred to the controller 29 to be used to control the display modes. In this embodiment, although the FA1 is also set in the code register 27 and some pattern is generated accordingly from the character generator 28, it causes no problem since the controller 29 functions so as to suppress the display in the first cycle in receiving the FA from the FA register 22. The register 22 is constructed with eight D-FF's. The CC1, CC2, and CC3 following the FA1 are used as addresses for the character generator 28 via the code register 27 and the patterns of the characters C1, C2, and C3 corresponding thereto are displayed on the CRT 30. At that time, the controller 29 controls the display mode according to the FA1. Fig. 7 illustrates the timing of the operation in handling the display data illustrated by (B) in Fig. 4 in the CA only mode. In this mode, since it is required to read out a CC and a CA from two storing locations for each column count corresponding to each character display time, C-clocks are supplied to the address generator 15 and the address generator 15 increments the address according to the successive transitions of the C-clocks. Thus, the characters C1, C2, etc., corresponding to the CC1, CC2, etc., are displayed under the control of CA1, CA2, etc. Fig. 8 illustrates the timing of the operation in handling the display data illustrated by (C) in Fig. 4 in the FA/CA mixed mode. This timing of the operation is basically the same as that of the CA only mode. As illustrated, the characters C2, C3, C4, etc., are displayed under the control of FA1 + CA2, FA1 + CA3, FA1 + CA4, etc. The present invention provides a versatile attribute control while effectively using memory spaces, and the ability to use one display apparatus for various applications and to use different attribute control modes in a plurality of segments on the screen divided for a plurality of applications.

Claims: A digital data display apparatus of the type which controls display modes of characters with attributes in displaying them by a raster scanning type display means, said digital data display apparatus comprising: a mode specifying means settable so as to specify selectively either a first control mode using field attributes only or a second control mode using at least character attributes; a refresh memory having a plurality of sequentially addressable storing locations for storing either a field attribute or a character code in each of said plurality of storing locations when said mode specifying means specifies said first control mode and for storing character codes and character attributes alternately in said plurality of storing locations when said mode specifying means specifies said second control mode; and an address generating means associated with said mode specifying means and said refresh memory for generating address signals to read out character codes or attributes in said refresh memory, which means generates successive address signals at a predetermined operation rate when said mode specifying means specifies said first control mode and generates successive address signals at an operation rate which is double the predetermined operation rate when said mode specifying means specifies said second control mode. Display apparatus as claimed in Claim 1, wherein: said predetermined operation rate of said address generating means is a rate of incrementing one address for each character display time of said display means. A display apparatus as claimed in Claim 1 or in claim 2, wherein: said address generating means is a counter which performs counting according to clock signals and is provided with a means for changing the frequency of said clock signals depending on the specification of said control modes by said mode specifying means. Display apparatus as claimed in anyone of claims 1, 2 or 3, wherein: said mode specifying means indicates selectively, as said second control mode, either a CA only mode using character attributes only or an FA/CA mixed mode using both of field attributes and character attributes, and in said FA/CA mixed mode, one or more field attributes are stored instead of one or more character attributes at one or more storing locations selected in said refresh memory. Display apparatus as described in Claim (4), wherein: a first, a second, and a third means for retaining separately said character codes, character attributes, and field attributes, respectively, are connected to the output bus of said refresh memory, and a logic means for combining each of said one or more character attributes and each of said one or more field attributes into one attribute when said mode specifying means specifies said third control mode is provided on the output side of said second and third retaining means.

Inventors: AOKI, TAKAAKI, NOJIMA, KATSUYUKI, SEKI, YOHJI
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: G09G1
IPC codes: G09G1, G09G5