Apparatus and method for alterable resource partitioning enforcement in a data processing system having central processing units using different operating systems

Abstract: In a data processing system having a plurality of non-homogeneous central processing units, apparatus is disclosed that permits a central processing unit not having mechanisms for protection of the allocation of resources to be coupled to the data processing system while preserving a peer relationship among the central processing units. The protection apparatus is interposed between the coupled central processing unit and the system bus and reviews each access to data processing system resources to insure that the accessed system resource is available to the associated data processing system. In addition, the apparatus permits initialization procedures without interprocessor conflict, provides status information from the coupled central processing unit to a requesting central processing unit and permits selected control signals to be applied to the coupled central processing unit.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to data processing systems and more particularly to data processing systems having a plurality of central processing units. 2. Description of the Related Art In order to increase the processing capability of data processing systems, one technique has been to couple additional central processing units to the system. The ability to select the number of central processing units in a data processing system permits an efficient matching of the capabilities of the system to the data processing requirements. Data processing units having a plurality of central processing units typically have one of two configurations. Referring now to Fig. 1A, a data processing system having a plurality of central processing units, according to a first implementation found in the prior art, is shown. The data processing system includes a plurality of central processing units 11-12 coupled to a system bus 19. The central processing units 11-12 perform the actual manipulation of data groups under control of operating and user software programs. The main memory unit 16, also coupled to the system bus 19, stores the data and program signal groups which are currently being used by the central processing units. The input/output units 14-15, coupled to the system bus 19, include devices for storage of large quantities of data and program signal groups, e.g., disk storage devices, terminals for the entry of data by system users, and communication devices for exchange of data and program groups with remote locations. The system bus 19 provides the principal path for the exchange of data and program groups between the components of the data processing system. Referring next to Fig. 1B, a second implementation of a multiprocessor system, according to the related art, is shown. Generally, the same components are available to perform the processing functions as in Fig. 1A except that the components are coupled by a memory control unit 14 instead of by the system bus 19. The memory control unit 14 is typically an electronic switch providing the coupling of the data processing unit component in response to control signals. The memory control unit 14 can also provide functionality, such as conflict resolution, that would typically be distributed in the bus oriented data processing system. The data processing systems of Fig. 1A and Fig. 1B are typically implemented in the related art such that the central processing units are homogeneous. In a homogeneous data processing system, the operating systems are the same or similar, the implementing apparatus is the same or similar and the operations performed on apparatus external to the data processing system is the same or similar. Even though the central processing units are homogeneous, substantial efforts are employed to prevent conflicts between the central processing units, thereby preventing conflicts between different activities for the data processing system resources. For example, one of the central processing systems can be selected to allocate resources and tasks among the plurality of central processing units. The resources of the system are the storage devices, terminals, main memory locations and other data processing facilities to which a central processing unit has access for the purpose of performing the data processing functions. This relationship is generally referred to as the master/slave relationship because of the control asserted by the selected processor. However, some data processing systems can be designed wherein the central processing units, operating under control of the same operating system, can operate under as equal members (as contrasted with the master/slave relationship) of the data processing system. The following references provide examples of the way in which a plurality of central processing units can be incorporated in a data processing system without a master/slave relationship while avoiding system resource access conflicts. In U.S. Patent 3,631,405, issued December 28, 1971, entitled SHARING OF MICROPROGRAMS BETWEEN PROCESSORS and invented by G. S. Hoff and R. P. Kelly, two microprogrammed processing units share control elements that permit sharing of microprogram repertoires. By appropriate invocation of the operating system, the control signals from a first microprogrammed processing unit are transferred to the second microprogrammed processing unit. In fact, this configuration can best be described as a single processing unit with resources allocated by a supervisor controlled operating system. The use of a supervisor program as well as the coupling between the two processing units distinguishes this configuration from the peer processing unit relationship described in the present invention. In U.S. Patent 4,131,941, issued December 26, 1978, entitled LINKED MICROPROGRAMMED PLURAL PROCESSOR UNIT and invented by H. L. Siegel, G. F. Muething, Jr., and E. J. Radkowski, a configuration of a plurality of processors is described that permits the processors to act independently or to be reconfigured so that a master/slave relationship can be invoked. The plurality of processors are linked together and, even when operating in a mode described as being independent, are not independent but subject to a supervisory control structure for configuration determination and for allocation of activity. Of course, the control of the allocation of activities implies the control of the allocation of resources. In addition, the data processing system described by this U.S. Patent, either has one operating system or a plurality of identical operating systems. The invention of the U.S. Patent appears to be best described as a single data processing system with a controllable configuration. The present invention is directed to central processing units having different operating systems that can function independently. In U.S. Patent 4,200,930, issued on April 29, 1980, entitled ADAPTER CLUSTER MODULE FOR DATA COMMUNICATIONS SUBSYSTEM invented by R. L. Rawlings and R. D. Mathews, a host processing unit can have a plurality data communications subsystems coupled thereto for performing routine communications functions with incoming and outgoing signals. Although the data communications subsystems are capable, in case of a failure of the host processing unit, of continuing communications, the role of the host processing unit to the data communications subsystems is clearly that of a master/slave relationship. The peer processor relationship is not applicable because the data communications subsystems do not have access to all the resources available to the host processing unit. In U.S. Patent Specification No.4,703,417, entitled MULTIPROCESSOR SYSTEM ARCHITECTURE, the communication of two processors is described. In this application, the sharing of memory without interference is accomplished by controlling buses associated with each processor system. The buses are coupled to particular areas of memory and, for one processor to access the memory dedicated to the second processor, the bus of the first processor is coupled to the bus of the second processor. Apparatus associated with each bus controls the ability of the other processor to access the system bus, thereby effectively limiting access of each processor to the system resources. The European patent application EP-A-0192944 discloses a data processing system with a main processor and a co-processor sharing the same resources. A control technique is employed in a co-processing environment in which I/O facilities are shared between a master processor running a known set of support code and a co-processor running code of unknown origin relative to the master processor. The actual management of the shared I/O resources is made transparent to the software running in the co-processor because of additional con trol logic associated with the co-processor. This is accomplished by providing trapping logic incorporating a RAM loadable by the master processor which contains data related to the current usability by the co-processor of a shared I/O device. The trapping logic is dynamically controllable by the main processor depending on the main processor's current needs for utilization of the various shared I/O devices. The trap causes the co-processor to generate an interrupt to the main processor via an interrupt request signal which notifies the main processor of its need for service. This arrangement is illustrative of a master/slave mode of operation. More recently, interest has been demonstrated in data processing systems having a plurality of central processing units functioning with non-homogeneous (generally incompatible) characteristics. The availability of non-homogeneous central processing units can be particularly advantageous to a system user providing the availability of a plurality of program repertoires. Ideally, all of the central processing units should have a peer relationship, i.e., should be capable of accessing all resources without the benefit of auxiliary protection mechanisms described in relation to the related art and without having a master/slave relationship in which one central processing unit controls all the activity and allocation of resources. Many central processing systems do not have the necessary hardware and/or software functionality to enforce allocation of resources. Non-the-less, the peer relationship between central processing units is a desirable multiprocessor relationship, allowing easy expandability of the processing system. A need has been felt for technique that permits any central processing unit to be coupled to a data processing system even though necessary the mechanisms for enforcement of resource allocation are not present. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved data processing system that overcomes the problems of the prior art. It is a feature of the present invention to provide an improved data processing system having a plurality of central processing units. It is another feature of the present invention to provide an improved data processing system having a plurality of central processing units utilizing different operating systems. It is a further feature of the present invention to provide an improved data processing system in which a plurality of central processing units executing instructions under different operating systems can have a peer relationship. It is more particular feature of the present invention to provide apparatus permitting two central processing units of a data processing system to operate in a non-hierarchical relationship while controlling the interaction between the central processing units. It is still another feature of the present invention to permit a central processing unit to be coupled to a data processing system, in which all the central processing units have a non-hierarchical relationship, even though the central processing unit being coupled to the data processing system does not have the requisite resource allocation enforcement mechanisms. The aforementioned and other features are accomplished, according to the present invention as set out in claims 1 and 19, respectively. Thereby, a central processing unit, typically not compatible with a central processing unit(s) already coupled to a data processing system, is coupled to the data processing system. The non-compatible central processing unit is coupled to the data processing system through a central processing unit interface device. The central processing unit interface device includes resource allocation mechanisms by which a data processing system which can permit the coupled central processing unit(s) to have access to all of the resources of data processing system. The central processing unit interface device dynamically controls the resources to which the coupled central processing unit can have access. The central processing unit interface device also eliminates potential conflicts during initialization procedures, provides status signals relating to the operation of the non-homogeneous central processing unit and applies selected control signals to the non-compatible central processing unit. These and other features of the invention will be understood upon reading of the following description along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a block diagram of a bus oriented data processing system having a plurality of central processing units according to the related art, while Fig. 1B is a block diagram of a memory controller oriented data processing system having a plurality of central processing units according to the prior art. Figure 2A illustrates the apparatus for implementing a peer processor relationship in a multiprocessor data processing system, while Fig. 2B illustrates the partitioning of main memory storage in a peer processor relationship. Figure 3 is a block diagram of the principal components of the protection enforcement mechanism for the partitioning of resources according to the present invention. Figure 4 is a block diagram of the central processing unit according to one implementation of the preferred embodiment. Figure 5 is a block diagram of the status and control logic unit 32 of the protection enforcement mechanism. Figure 6 is a block diagram illustrating the components of the dedicated memory unit 34 shown in Fig. 3. Figure 7 is a block diagram of the components of the main memory unit protection device and the input output protection device. DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures Referring to Fig. 2A, the principal components that permit the central processing units of a data processing system of multiprocessor data processing system to assume a peer relationship are illustrated. Each central processing unit 11 (through 12) has associated therewith apparatus, software procedures or a combination of apparatus and software programs that prevent the generation of addresses or attempts to access input/output devices are nominally unavailable to the central processing unit 11 (through 12 respectively). This apparatus is illustrated as address generation apparatus 111 as part of central processing unit 11 and address generation security apparatus 121 as part of central processing unit 12. The main memory unit 15 is divided into a plurality of regions. Region 151 is a region reserved for the operating system controlling the operation of central processing unit 11, while region 152 is a portion of the main memory unit reserved for the operating system controlling operation of the central processing unit 12. The portion of the main memory unit denoted by region 153 is reserved for the files, tables, software procedures, etc., used by the central processing unit 11, while the region 154 is reserved for the files, tables, software programs used by central processing unit 12. Region 155 is a common region and accessible to both central processing unit 11 and central processing unit 12. Referring to Fig. 2B, more detail in the allocation of the storage of the main memory unit 15 is shown symbolically. The regions 151 and 152 reserved for operating systems of the associated central processing unit each have two subregions (151A and 151B, and 152A and 152B,respectively) that are important for operation of a peer relationship. The subregions 151A and 152A provide a list of the resources, i.e., input/output devices and reserved main memory unit regions, reserved for the associated central processing unit. Subregions 151B and 152B provide the procedure by which the two central processing systems can communicate. In the preferred embodiment, this communication is performed through subregion 155A of the portion of main memory reserved for usage by both the central processing units 11 and 12 using a technique typically referred to as a data processing system mail box. In this technique, a message is left in the mail box 155A by a first central processing unit and a second central processing unit either reads the contents of the mail box periodically or is alerted by the first central processing unit that a message is available. Upon reading of the contents of the mail box 155A, the second central processing unit can make an appropriate response. Referring now to Fig. 3, the principal components of the central processing unit interface device 30 are shown. The system bus 19 is coupled to system bus interface unit 17. The bus interface unit 17 has appropriate apparatus for identifying communications directed to the apparatus associated with the system bus interface unit 17 and for applying messages to the system bus 19 according to the protocol established for the system bus. The system bus interface unit 17 also includes ACK-NACK (acknowledge-acknowledge_not) decision unit 17A. Communications from the system bus 19 are applied, through the system bus interface unit 17, to the input buffer registers 31, the status and control logic unit 32, to the reserved memory unit 34, to the main memory protection unit 35 and to the input/output protection unit 36. Signals from the status and control logic unit 32 are applied to the central processing unit 12 and to the system bus interface unit 17. The reserve memory unit 34 receives signals from the central processing unit 12 and applies (data) signals to the central processing unit 12. The main memory protection unit 35 and the input/output protection unit 36 receive signals from the central processing unit 12 and apply signals to the system bus request unit 37. The system bus request unit 37, which includes the system bus output registers 37A, receives signals from the central processing unit 12 and applies signals to the central processing unit 12. Referring next to Fig. 4, a block diagram of the components of a central processing unit 12 used in the preferred embodiment is shown. The principal processing function is performed by processor unit 41, an Intel 80386 component. The complex processing functions, such as floating point operations, are provided by coprocessor unit 43, implemented by an Intel 80387 component. The cache memory unit 44 provides access to the data required for processing by the central processing unit 12. Referring next to Fig. 5, a block diagram of the components of the status and control logic unit 32 are shown. The device identification register 51 contains identification information for the central processing unit 12 coupled to the central processing unit interface device 30. The controller revision number register 52 identifies the functionality of the protection enforcement apparatus 30. The syndrome signal register 53 receives signals from the associated central processing unit that indicate an operational event having significance for the operation of the data processing system. The contents of the device identification register 51, the controller revision number register 52 and the syndrome signal register 53, in response to appropriate commands from the system bus interface unit 17, applies the register contents to the system bus interface unit 17. The software error register 54 is a status register for the software procedures. The interrupt control register 55 includes interrupt status information such as the interrupt level of the currently executing program. Interrupt register 56 has information relating to a pending externally applied interrupt procedure stored therein. The software error register 54, the interrupt control register 55 and the interrupt register 56 can have data stored therein from signals in the system bus interface unit 17 and can apply the contents of the registers to the system bus interface unit 17. In addition, the interrupt register 56 applies a signal to the associated central processing unit indicating that an interrupt is pending. The privileged control register 57 and the unprivileged control register 58 contain control signals that are applied to and effect the operation of the associated central processing unit 12. Registers 57 and 58 receive signals from the system bus interface unit 17. In the preferred embodiment, the unprivileged control register 58 is used for control of cache memory unit 44, while the privileged control register 57 applies signals to the associated processor 41 that impacts the operation. Referring next to Fig. 6, the address buffer register 61 and the data buffer register 62 receive signals from the system bus interface unit 17 and apply the signals stored therein to dedicated RAM (Random Access Memory) unit 63. Dedicated RAM memory unit 63 receives address signals from the associated central processing unit 12 and transfers data signals to the associated central processing unit 12. The dedicated memory unit 34 is used during the initialization procedure and is described below. Referring next to Figure 7, a block diagram of the main memory unit protection device 35 and the input/output unit protection device 36 are shown. The input/output unit protection device address buffer register 77 and the input/output protection device data buffer register 78 receive signals from the system bus interface unit 17 and apply signals to the address input terminals and data input terminals respectively of input/output availability array 79. The central processing unit address buffer unit 69 receives signals from the central processing unit 12 and applies signals to the address terminals of input/output unit availability array 79. The availability array 79 applies signals to the I/O array decode unit 70. The signals from I/O array decode unit 70 are applied to system bus request unit 37. The main memory unit protection device address buffer register 75 and the main memory protection device data buffer register 76 receive signals from the system bus interface unit 17 and apply signals to the address input terminals and the data input terminals respectively of the main memory unit availability array 72. The address input terminals of array 72 also receive signals from the central processing unit by means of the central processing unit address buffer register 71. The I/O-main memory transfer logic unit 74 receives signals from the central processing unit 12 and applies signals to the address signal input terminals of main memory unit availability array 72. The output signals from availability array 72 are applied to main memory array decode unit 73, the decode unit 73 applies signals to the system bus request unit 37. 2. Operation of the Preferred Embodiment In a ideal multiprocessor configuration, all of the central processing units would have access to all the resources of the data processing system without the requirement for protection mechanisms insuring the partitioning of resources among the central processing units. However, many operating systems do not have the procedures that prevent the attempts to access a resource assigned to another processor and/or are incompatible (non-homogeneous) the existing central processing unit(s) of the data processing system. The present invention provides the apparatus to permit an additional, non-homogeneous central processing unit to be treated by the other central processing unit(s) of a data processing system in a peer relationship, i.e., as if these protection mechanisms were present, by locating a central processing unit interface device 30 between the central processing unit 12 and the remainder of the data processing system, typically the system bus 19, that provides the appropriate protection. Thus, if an updated version (release) of an operating system includes the protection mechanisms, then the (intermediate) central processing unit interface device 30 will not be necessary. In the preferred embodiment, the host central processing unit 11 is a Honeywell Bull DPS6PLUS data processing system operating under control of the HVS1 operating system. The HVS1 operating system includes procedures that provide for the trustworthiness of the system. In order to provide the data processing system with the capability of executing the wide repertoire of user programs using the UNIX operating system, the central processing unit 12, described in Fig. 4, was selected. The Honeywell Bull UCOSV operating system, based on the UNIX operating system, has been provided for executing the user programs was believed to lack, at present, the appropriate mechanisms for secure partitioning of resources in the multiprocessor environment. The central processing unit interface device 30, illustrated in block diagram form in Fig. 3 is used to provide the protection mechanisms for the partitioning of resources. Referring to the status and control logic unit of Fig. 5, a host processing unit can control the operation of the data processing unit coupled to central processing interface unit 30 by entering data groups in appropriate registers and can obtain information concerning the coupled central processing unit by reading data groups in the registers. The ACK-NACK decision unit 17A controls the access to the status and control logic unit 32 from the system bus 19. For example, when an attempt is made to enter an interrupt command in the interrupt register 56, the ACK-NACK decision unit 17A compares the interrupt level of the interrupt command with the current level of operation of the central processing unit 12 stored in interrupt control register 55. When the current operation level exceeds the interrupt level, then the ACK-NACK decision unit 17A applies an NACK (ACKNOWLEDGE-NOT) signal to the system bus indicating that the interrupt command signal group has not been stored in the interrupt register 56. Similarly, the ACK-NACK decision unit will prevent the occurrence of possible conflicts by refusing to accept selected signal groups. In the preferred embodiment, access to the registers is typically through the system bus (by means of an I/O command). For example, the interrupt register 56 can signal to the coupled central processing unit 12 the presence of an interrupt command stored therein, for the coupled central processing unit 12 to read the contents of the interrupt register 56, a I/O procedure is used. The dedicated memory unit of Fig. 6 is used during the initialization procedure. Central processing unit 12, as illustrated in the embodiment of Fig. 4 has an initialization procedure that addresses a portion of the main memory which the DPS6PLUS central processing system uses for its initialization procedure. In addition, the 80386 processor addresses main memory locations that are not (currently) implemented in the main memory unit 15. Therefore, during the initialization procedures for the data processing system, the initialization procedures needed to initialize (boot) the 80386 central processing unit is transferred to the dedicated RAM unit via the system bus 19. Thereafter, as the 80386 central processing unit begins its internal initialization procedures, although the addresses supplied from the central processing unit are main memory unit addresses, the addressed data is supplied from the reserved memory unit 34. Referring to Fig. 7, the mechanism by which the access to the associated central processing unit 12 to data processing system resources is illustrated. The input/output address buffer registers 77 and the input/output data buffer register 78 receive signals from data processing system that associate an input/output device address (i.e., channel number) with the availability of that input/output device (encoded as data) to the associated central processing unit 12. The encoded availability data is stored at the appropriate address in the availability register 79. When the associated central processing unit 12 attempts to access an input/output device, the address signals are applied to the availability memory 79. The encoded data associated with that address is applied to the decode unit 70 and the decode unit 70 applies a signal to the system bus request unit that permits or prohibits the continuation of the access of the input/output unit. Similarly, the main memory unit protection device 35, by means of the address buffer register 75 and the data buffer register 76 receive signals from the (system bus 19 of the) data processing system and store data signals encoded with information relating to the availability of the main memory unit 15 to the associated central processing unit 12. This information is stored at an address associated with a main memory address in the availability memory 72. When the associated central processing unit 12 attempts to access the main memory unit 15, the address signals are applied, through address buffer register 71 to the availability memory 72. The encoded data signals associated with that main memory unit address are then applied to decode unit 73. The decode unit 73 determines the availability of the addressed main memory location and applies appropriate signals to the system bus request unit 37. The address signals from the central processing unit 12 are stored in the system bus request unit I7 until the result of the decoding by decode unit 73 is completed. The output signals from decode unit 73 determines whether the access of the main memory unit 15 can continue or is terminated in the system bus request unit 37. Input/output-main memory transfer logic unit 74 receives data signals from the associated central processing unit 12. In the event that an operation from the associated central processing unit involves a transfer of data between an input/output unit (e.g., 16)and the main memory unit 15, the availability of the input/output device 16 can be determined by address signals. However, the main memory location is encoded in the data signals. Transfer logic unit 74 determines the address in the main memory unit 15 to be accessed and applies this address to availability memory 72, thus controlling access to the main memory locations. As will be clear, this technique has the advantage that the availability of the main memory and the input/output units can be controlled, not only during an initiation procedure, but dynamically during the operation of the data processing system. It will be clear to those skilled in the art that the peer processing configuration of the present invention relates to data processing system generally referred to as being "tightly-coupled". In this type of data processing system, the components of the data processing system are generally coupled without the intervention of a communication system or similar format translation system. It will be clear that the presence of the central processing unit interface device 30 provides the mechanism for secure partitioning of data processing system resources which permits the associated data processing unit to have a peer relationship with the other central processing units of the data processing system. The difference in the peer relationship of the present invention is that, even though the central processing unit which enters the data to be stored in the central processing unit interface device does not control the central processing unit associated with the central processing unit interface device the sense of a master/slave relationship, the entering data processing unit is required because its partitioning mechanism is secure (trustworthy). The central processing unit interface device, in response to the signals from the entering central processing unit, provides the secure (trustworthy) partitioning mechanism that is not present in the associated central processing unit. The foregoing description is included to illustrate the operation of the preferred embodiment.

Claims: Multi-processor data processing system having a first CPU (11) and at least a second CPU (12) which operates under control of an operating system that is incompatible with said first CPU's and said data processing system's operating system; and having a system bus (19) coupled via system bus interface means (17) to said CPUs for distributing signals applied to said system bus throughout said data processing system; said data processing system further having a plurality of DP system resources such as a main memory (15) and I/O resources (16, 17) coupled to said system bus (19) for applying signals thereto and for receiving signals therefrom, characterized in that said CPUs cooperate in a peer relationship; said main memory (15) comprises first regions (151, 152) provided for the operating systems of the associated CPUs, and second regions (153, 154) for the data and programs of the associated CPUs; said first regions (151, 152) having first subregions (151A, 152A) which provide resource lists for each associated CPU, and second subregions (151B, 152B) which provide the communication procedure by which the CPUs (11, 12) can communicate with each other thereby allowing dynamically reassigning said resources (15, 16, 17) in response to signal groups from a CPU which requires non-assigned resource as well as assigning resources to each CPU; said main memory further comprising a mail box (155A) in a common region (155) for using by said CPUs (11, 12) in such a way that -when a message is stored in said mail box for a CPU- this CPU is alerted to read said message so that this CPU can take appropriate action; and a CPU interface means (30) is provided for coupling the at least second CPU (12) to said system bus interface means (17) comprising protection devices (35, 36) for said DP system resources (15, 16, 17) for permitting access to a group of assigned resources and preventing access to resources not assigned to said CPU; and for converting signal groups generated by said second CPU (12) to a format compatible with the system transfer signal groups. The system of claim 1, wherein a first group of resources is assigned to a first CPU for use by said first CPU and a second group of resources is assigned to a second CPU for use by said second CPU, characterized in that the interface means (30) includes access control means (35,36) for determining said group of resources to which said second CPU (12) is permitted access, and, in response to signals from said first CPU (11), for dynamically changing said second group of resources to which said second CPU is permitted access. The system of claim 2, characterized in that said interface means (30) includes memory means (34) for storing initiation procedures for said second CPU. The data processing system of claim 1, characterized in that said interface means (30) includes register means (31, 33) for storing control signals from said first CPU and for transferring said control signals to said second CPU. The system of claim 4, characterized in that said control signals include an interrupt signal and identification signals identifying an interrupt procedure. The system of claim 5, characterized in that said register means (31, 33) receive and store status signals from said second CPU, and that -in response to request signals from said first CPU- said status signals are transmitted to said first CPU. The system of claim 6, characterized in that said interface means (30) provides signal groups to and receives signal groups from said CPUs which are compatible with the signal groups transferred over said system bus (19). The system of claim 1, wherein said CPU interface means (30) is used to enforce the assigned use of resources where the software to preventing access may not be sufficient to prevent access to a particular resource, characterized in that said interface means (30) comprises protection means (35, 36) responsive to commands received from the first CPU (11) identifying a resource to which access by said first CPU is required; said protection means (35, 36) determining when an identified resource identified by said commands is allocated to said first CPU, said commands being transferred to said identified resource when said resource is allocated to said first CPU. The system of claim 8, characterized in that said protection means consist of a main memory protection means (35) and an I/O protection means (36) which are responsive to main memory reference signals and to I/0 commands, respectively, that said main memory reference signals are transferred to said identified main memory resource when said main memory resource is allocated to said first CPU, and that said I/O command is transferred to said identified I/O resource when said identified I/O resource is allocated to said first CPU. The system of claim 9, characterized in that said main memory protection means (35) and/or said I/O protection means (36) is responsive to and stores control data signal groups supplied by said system bus (19) which signal groups determine when a main memory resource and/or an I/O resource is allocated to said first CPU. The system of claim 10, characterized in that said main memory protection means (35) and/or said I/O protection means (36) are responsive to and store control data signals from the second CPU, said control data signals being selected from the group consisting of resource allocation control signals and interrupt control data signals. The system of claim 10, characterized in that said interface means (30) further comprise reserved memory means (34) for storing initialization procedures for the CPU, wherein main memory reference signals from said CPU are applied to said reserved memory means (34) during said initialization procedures. The system of claim 12, characterized in that said interface means (30) further comprise status and control means (32) for storing status signals from said first CPU, wherein said first CPU status signals are applied for effecting an interrupt operation of the second CPU, and for storing control signals from said second CPU, wherein said second CPU control signals are provided for controlling the operation of said first CPU. The system of claim 13, characterized in that said status and control means (32) includes an interrupt register (56) for storing a pending interrupt data signal group. The system of claim 13, characterized in that said status and control means (32) includes an interrupt control register (55) for storing logic signals related to a current level of priority of operation of said first CPU. The system of claim 14, characterized in that said status and control means (32) stores logic signals from and transfers logic signals to said first CPU in response to commands from said second CPU. The system of claim 8, characterized in that said protection means (35, 36) comprise: a protection device address buffer register (75, 77) receiving signals from said system bus interface means (17); a protection device data buffer register (76, 78) receiving data from said system bus interface means (17); a resource availability array (72, 79) receiving address signals and/or data from the said protection device address buffer register (75, 77), said protection device data buffer register (76, 78), and from the CPU address buffer (69, 71), and supplying signals to a resource decode unit (70, 73) which determines the availability of the addressed resource by permitting or prohibiting the continuation of the access of the respective resources by applying respective control signals to a system bus request unit (37) being part of the CPU interface means (30) which is coupled via the system bus interface unit (17) to said system bus (19). The system of claim 1 or any other preceding claim, characterized in that, if an operation of an associated CPU (e.g. 12) involves a data transfer between an I/O unit (e.g. 16) and the main memory (15), the address signals determine the I/O channel and thus the availability of the I/O device whereas the main memory location is encoded in the data signals, and I/O memory transfer logic means (74) determine the address in the main memory (15) to be accessed and apply this address to a memory availability means (72) thereby controlling access to the main memory locations. A method of operating a data processing system having at least a first CPU (11) and at least a second CPU (12) said second CPU operating under Control of an operating system which is incompatible with said first CPU's and said data processing system's operating system, said DP system further having a system bus (19) coupled to said CPUs (11, 12) via system bus interface means (17) for distributing signals applied to said system bus (19) throughout said data processing system, and DP system resources, such as main memory (15) and I/O units (16, 17), wherein signals are exchanged among said resources (15, 16, 17) and said CPUs (11, 12), and wherein an interface unit (30) is coupled between each peer-related CPU and said system bus, the method being characterized by the steps of : providing a peer relationship between the at least two CPUs by having a) said main memory (15) comprising first regions (151, 152) provided for the operating systems of the associated CPUs, and second regions (153, 154) for the data and programs of the associated CPUs; said first regions (151, 152) having first subregions (151A, 152A) which provide resource lists for each associated CPU, and second subregions (151B, 152B) which provide the communication procedure by which the CPUs (11, 12) can communicate with each other; said main memory further comprising a mail box (155A) in a common region (155) for using by said CPUs (11, 12) in such a way that -when a message is stored in said mail box for a CPU- this CPU is alerted to read said message so that this CPU can take appropriate action; and b) a CPU interface means (30) coupled between the at least second CPU (12) and the system bus interface means; assigning a group of resources to the second CPU (12) and storing an identification of said group of resources in said interface means (30), wherein a requested resource can be assigned to said group of resources in response to communications between said CPUs (11, 12), via said mail box; when said second CPU (12) generates signal groups which would result in interaction with a destination resource, applying said signal groups to said interface means (30); determining in said interface means (30) whether said destination resource is included in said group of resources; when said destination resource is included in said group of resources, converting said signal groups to a format compatible with the system transfer signal groups and transmitting said converted signal groups to said system bus (19); when said destination resource is not in said group of resources, prohibiting said signal groups from being applied to said system bus (19). The method of claim 19, characterized in that the assigning step is responsive to requests for DP system resources from said second CPU (12). The method of claim 19, characterized by a step of providing a communication channel between said CPUs (11, 12), wherein these CPUs can dynamically reallocate assigned system resources. The method of claim 21, characterized by a step of initializing said second CPU (12) by means of second CPU initialization signal groups stored in said interface means (30). The method of claim 20, further characterized by the steps of: transmitting control signals for controlling the operation of said second CPU (12) from said first CPU (11); storing said control signals in said interface means (30); transferring said stored control signals to said second CPU (12); transferring from said second CPU (12) status signals indicating the status of said second CPU to said interface means (30); storing said status signals in said interface means (30), and applying said status signals to said system bus (19). The method of claim 19 or any other preceding method claim, characterized in that, if an operation of an associated CPU involves a data transfer between an I/0 unit and the main memory, address signals are provided which determine the I/O channel and thus the availability of the I/O device; data signals are provided which determine the main memory locations; the addresses to be accessed in the main memory are determined in an I/O memory transfer logic means (74), whereupon said addresses are applied to a memory availability means (72) thereby controlling access to the main memory locations.

Inventors: BOOTH ANTHONY J, MCNALLY LANCE, MORLEY PETER, BOOTH, ANTHONY J., MCNALLY, LANCE, MORLEY, PETER
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS INC.
Application year: 1988
Main classification: G06F15
IPC codes: G06F15, G06F9