Data transferring buffer circuits for data exchange

Abstract: Data transferring buffer circuits for data exchange include a plurality of buffers corresponding to a plurality of data sources for receiving and storing independently data sent from the plurality of data sources, and a buffer limit signal generating circuit for delivering a buffer limit signal when the amount of data stored in the buffer reaches a predetermined limit. The buffer circuits also include a data read signal generating circuit for selecting one of the buffers and generating a data reading signal for the selected buffer based on the remaining amount of data and information concerning a vacancy at a buffer to which data is to be supplied, and a selected data delivery circuit for adopting data selected by the data read signal generating circuit and delivering the adopted data.

Description: The present invention relates to data transferring buffer circuits for data exchange and a system of data transmission between processors using the data transferring buffer circuits. The data transferring buffer circuits according to the present invention can be used in a system of a simulation processor (SP). In data processing by a great number of processors with a transmission network for interconnecting the processors to allot divisions of processing and carry out the divisions of the processing in parallel, it is necessary to transfer data between the processors as quickly as possible. In general, in order to transfer data from a plurality of data sources to a plurality of data destinations, the data sources and the data destinations are directly connected through a switching unit. In this case, when a plurality of calls occur simultaneously for the same data destination, all except one are placed in a waiting state. Under such a situation, it is necessary to control the timing of data delivery from the data source in question according to the data transfer requests from other data sources. In order to simplify this control of data delivery timing, it is possible to provide input buffers and output buffers having sufficient storage capacity to store the data to be transferred where simultaneous plural calls for the same data destination occur. However, in such a case, there is a disadvantage that a great number of buffers are needed. The disadvantage is greater when the buffers are used for multi-stage data exchanging circuits. US-A-A 325 120 discloses a data processor architecture having features corresponding to those of the preamble of accompanying claim 1. According to the present invention there is provided a multiprocessor system in which data processing is carried out by exchanging data among a plurality of processors interconnected via a plurality of data exchange means; said data exchange means being arranged to receive data from said processors, to deliver the received data selectively to other said processors, and to hold the received data until delivery thereof is enabled in the event of multiple data exchange requests among said processors; characterised in that:- said system has a hierarchical structure in which the processors are arranged in groups and the data exchange means are arranged as lower and upper data exchange means, wherein:- a lower level of said hierarchical structure is constituted by the processors in said groups; a lower data exchange means is part of each respective group of processors and connected to all the processors in said group; a higher level is constituted by sets of several groups of the same level; an upper data exchange means is provided for the or each set of groups and connected to all the lower data exchange means in said set; and in that each data exchange means comprises : a data receipt portion for receiving data from any processor of its respective group or from data exchange means of any lower group, and, if an upper group exists, from exchange means of the upper group; a data holding portion for holding the received data; and a selective data delivery portion for selectively delivering the received data to any processor of its respective group or to data exchange means of any lower group, and, if an upper group exists, to exchange means of the upper group. An embodiment of the present invention may provide an improved system of data transfer between a great number of processors using data transferring buffer circuits for data exchange suitable for data transfer between processors by a relatively small number of buffers with relatively simple control processes. Such a system may also employ a plurality of event transmission buffers. The construction of the system is relatively easy, since the system can be constructed by simply connecting event transmission buffers having relatively simple structures. An embodiment of the present invention may also provide improved data transferring buffer circuits for use in such a data transfer system, enabling data transfer between a great number of processors by a relatively small number of buffers with relatively simple control processes. In the drawings, Figs. 1A and 1B show prior art data transfer between data sources and data destinations through a switching unit; Fig. 2 shows a system using a simulation processor to which the data transferring buffer circuits for data exchange according to the present invention can be applied; Fig. 3 shows an example of the event transmission network which can be used in the system of Fig. 2; Fig. 4 shows another example of the event transmission network; Fig. 5 shows the structure of the gate processor used in the simulation processor shown in Fig. 2; Fig. 6 shows an event transmission buffer used in an embodiment of the present invention; Fig. 7 shows the structure of the buffer in the event transmission buffer shown in Fig. 6; Fig. 8 shows the structure of the data read signal generating circuit in the event transmission buffer shown in Fig. 6; Fig. 9 shows an example of the structure of a simulation processor in which the data transferring buffer circuits for data exchange according to the present invention can be used; Fig. 10 shows a system of data transfer between a plurality of processors according to another embodiment of the present invention; Fig. 11 shows the structure of an event transmission unit used in the system of data transfer shown in Fig. 10; Fig. 12 shows an example of prior art multi-stage switching networks; and Fig. 13 shows a table representing the reduction of the number of switching modules in the device of Fig. 10. Before describing the preferred embodiments of the present invention, prior art data transfers between data sources and data destinations through a switching unit, and systems to which the present invention is to be applied, are described with reference to Figs. 1A, 1B, 2, 3, 4, and 5. The prior art data transfer system shown in Fig. 1A is constituted by a plurality of data sources 911, 912, ... 91n, a plurality of data destinations 951, 952, ... 95n, and a switching unit 93. In the system of Fig. 1A, when a plurality of calls occur from the data source side for the same data destination, all except one are placed in a waiting state. Under such a situation, it is necessary to control the timing of data delivery from the data source in question according to the data transfer requests from other data sources. Another prior art data transfer system shown in Fig. 1B is constituted by a plurality of data sources 911, 912, ... 91n, a plurality of input buffers 921, 922, ... 92n, a switching unit 93, a plurality of output buffers 941, 942, ... 94n, and a plurality of data destinations 951, 952, ... 95n. Each of the input and output buffers has sufficient storage capacity to store the data to be transferred where simultaneous, plural calls occur for the same data destination. A simulation processor system used for logic verification of very large scale integrated circuits (VLSI's) before production is shown in Fig. 2. The system of Fig. 2 is constituted by a computer 82, a simulation processor 81, and an engineering work station (display and keyboard) 83. The simulation processor 81 is constituted by a control processor 7, an event transmission network 2, gate processors (GP) 500, 501, ... 563, an input processor 61, and an output processor 62. For example, the multiple gate processors 501 to 563 simulate partitioned subcircuits with a maximum capacity of 64K primitives and a 512Kbyte memory at a maximum speed of 12.8M active primitive evaluations per second. The input processor 61 sends external input patterns to the circuit during simulation. The output processor 62 receives the events from the monitored nets, storing up to 4M events. The event transmission network 2 handles the interprocessor communication. An example of the event transmission network (ET) used for the system of Fig. 2 is shown in Fig. 3. The event transmission network of Fig. 3 is for 16 gate processors (GP) 500 to 515, and is divided into event network units (ETU) which exchange events among four gate processors, or four event transmission network units one level lower in the hierarchy, and one event transmission network unit, or a pair of an input processor and an output processor, one level higher in the hierarchy. Event transmission network units are designed such that each gate processor can send and receive one event independently in each clock cycle. The detailed structure of the event transmission network is shown in Fig. 4. Each of the event transmission buffers 1 independently receives four events every clock cycle and sends one event taken from the buffer that is closest to the storage limit. An event transmission network unit includes five event transmission buffers. In the device of Fig. 3, there are three types of event transmission paths: from GP0 (500), via an event transmission network unit, to GP1 (501); from GP1 (501), via an event transmission network unit, the upper event transmission network unit, and another event transmission network unit, to GP12 (512); and from GP12 (512), via an event transmission network unit and the upper event transmission network unit to output processor 63. In every clock cycle, events are transmitted in all paths in the form of pipeline processing. The structure of a gate processor with an event transmission network used in the system of Fig. 2 is shown in Fig. 5. The device of Fig. 5 is constituted by an event transmission network 2, OR gates 500a and 500b, new event memory 500c, fanout device 500d, evaluation device 500e, net status memory 500f, and evaluation gate memory portion 500g including evaluation gate memories 500g₁ and 500g₂. In the device of Fig. 5, first, the input processor sends external events through an event transmission network 2 to a gate processor. When the gate processor receives an event from the event transmission network 2, the gate processor stores the received event in the new event memory 500c and begins to send fanouts through the fanout pipeline. If not yet registered, the fanout primitive is stored in one of the evaluation gate memories 500g₁ and 500g₂. When the input processor and the event transmission network finish sending events, the input processor and the event transmission network notify the control processor with an end signal. The control processor increments the unit time by 1 and a start command is issued for a simulation for unit time 1. In response to the start command, the gate processor begins to update the net status memory 500f using the new event memory 500c. If the gate has a user-defined probing flag, the event is also sent to the output processor. When the updating and fanout fetching are completed, the connections of the evaluation gate memories 500g₁ and 500g₂ to the fanout device 500d and the evaluation device 500f are switched. The evaluation device first extracts the boundary primitives from the evaluation gate memory 500g₂. Events in boundary nets trigger interprocessor transmission, and then an evaluation for internal primitives is started. The transmission and evaluation are carried out in parallel so that the transmission overhead is minimized. When the evaluation device 500e detects a next event, the evaluation device 500e registers the same in the new event memory 500c, supplies the same to the fanout device 500d, and sends the same to the event transmission network 2, if necessary. Then, the fanout device 500d begins to fetch fanout primitives for unit time 2, which are stored in the evaluation gate memory 500g₁. During an evaluation, a gate processor can receive an event from the event transmission network only when the evaluation device 500e does not access the new event memory 500c. When all gate processors complete evaluation and the event transmission network completes event transmission, the gate processors notify the control processor by an end signal to start the unit time 2 simulation. An event transmission buffer according to an embodiment of the present invention is shown in Fig. 6. The device of Fig. 6 is constituted by buffers 101, 102, 103, and 104, registers 111, 112, 113, and 114, a buffer limit signal delivery circuit 12, a data read signal generating circuit 13, a selected data delivery circuit 14, and a register 15. Each of the buffers 101 to 104 receives data of 32 bits and a data effective signal of 1 bit from a source of data, a read signal from the data read signal generating circuit 13, and delivers data to a register, a buffer limit signal to the buffer limit signal delivery circuit 12, and a data remainder amount signal to the data read signal generating circuit 13. The selected data delivery circuit 14, in the form of multiplexer, receives data from the registers 111, 112, 113, and 114 and delivers selected data in accordance with a selection signal from the data read signal generating circuit 13. The buffer limit signal delivery circuit 12 receives buffer limit signals from the buffers 101 to 104 and delivers buffer limit signals to the data source. The data read signal generating circuit 13, as a selection determination portion, receives data from the registers 111 to 114, a data effective signal from the register 15, data remainder amount signals from the buffers 101 to 104, and buffer limit signals from a destination of data and delivers read signals to the buffers 101 to 104 and a selection signal to the selected data delivery circuit 14. Each of the buffers 101 to 104 is provided in correspondence to a data source. Each of the buffers 101 to 104 is constituted by a first-in-first-out (FIFO) memory. When the amount of data stored in a buffer reaches a predetermined limit value, a buffer limit signal is delivered through the buffer limit signal delivery circuit 12. The data read signal generating circuit 13, as a selection determination portion, selects one of the buffers 101 to 104 based on the data remainder amount signals from the buffers 101 to 104 and the buffer limit signals from the data destination, delivers read signals to the buffers 101 to 104, and delivers a selection signal to be selected data delivery circuit 14. The data selected in the selected data delivery circuit 14 based on the selection signal from the data read signal generating circuit 13 is delivered as output data through the register 15. A data effective signal is attached to this output data for designating the data destination. The structure of the buffer in the event transmission buffer is shown in Fig. 7. The buffer 101 of Fig. 7 is constituted by a memory cell array 101a, AND gates 101b and 101c, a write address register 101d, a read address register 101e, and a subtraction portion 101f. Data is written into an address of the memory cell array 101a designated by the write address register 101d. The count of the write address register 101d is counted up by the write signal generated based on the data effective signal. Data is read from an address of the memory cell array 101a designated by the read address register 101e. The count of the read address register 101e is counted up by the read signal generated by the data read signal generating circuit 13 (Fig. 6). The subtraction portion 101f calculates the difference Ni = X(W) - X(R) of the count X(W) of the write address register 101d and the read address register 101e. The difference Ni is transmitted to the data read signal generating circuit 13 as a data remainder amount signal. The data remainder amount signal (Ni) may be a signal actually indicating the number of the remaining data. However, it is possible, for example, to use the upper j bits of an address for calculation, calculate the data amount based on a sampling with respect to 2 to the j-th power as a compression of data, add one line as an indication of vacancy, and accordingly, reduce the number of signal lines. For example, assuming the depth of a buffer is 2K words, 11 bits are necessary to represent the remainder number. However, where j = 2, 0 to 0.5K words is represented by "00", 0.5 ∼ 1K words is represented by "01", 1 ∼ 1.5K words is represented by "10", 1.5 ∼ 2K words is represented by "11", another one line is added for representing vacancy, and, if necessary, a further one line is added for representing buffer-limit. By this arrangement, the signal transmission path can be constituted by four lines per one buffer. Also, it is possible to produce a buffer-limit signal from the subtraction portion 101f. The structure of the data read signal generating circuit 13 in the device of Fig. 6 is shown in Fig. 8. The data read signal generating circuit 13 is constituted by a buffer selection determination circuit 131 and an address decoder 132. The address decoder 132 decodes a data destination address on the registers 111 to 114 and delivers a signal indicating the data destination. The buffer selection determination circuit 131 receives a buffer limit signal of the data destination, detects the buffers which hold data to be sent to data destinations not in the buffer limit state based on the output of the address decoder 132, discriminates the buffer which has the greatest data remainder amount from the above-detected buffers based on the data remainder amount signals from the buffers, and accordingly, determines to which buffer the data is to be transferred. Also, a selection signal is sent instructing the selection of the above-selected buffer. The selected data delivery circuit 14 in the device of Fig. 6 receives the selection signal from the data read signal generating circuit 13, and selects one of the signals from the registers. The register 15 latches the output of the selected data delivery circuit 14. The data of the register 15 and the data effective signal of 4 lines is delivered as the output from the event transmission buffer 1. This data effective signal designates the buffer which is to receive the data in question from the four buffers. This state of selection is locked until the data read signal generating circuit detects data partition information from the data being transferred, i.e., the data from the selected register. When such a lock is released, data including information of the data destination which is the top word of the data is latched in the registers 111 to 114 so that the device returns to the initial state. The circuit for detecting the data partition information can be obtained by combining simple logic circuits. In the data read signal generating circuit 13, information of positions in the transmission network of the event transmission buffer 1 including the data read signal generating circuit 13 is preliminarily set therein. Hence, the data read signal generating circuit 13 receives the address of the data destination from the registers and determines to which four buffers of data destination the data in question is to be transmitted, based on the operation of the address decoder 132. The manner of expression of the data destination address may be unique or not-unique. For example, when there are 64 processors and the data destination is expressed in 6 bits, the data destination is unique and only one line of the data effective signal lines is effective. For example, when the data destination is expressed in 12 bits, a plurality of the destinations are expressed at once in a two-bit representation such as: "00" = 0, "01" = 1, "10" = 1 or 0, "11" = 1 or 0, with respect to each bit of a 6 bit address, a plurality of lines from the four data effective signal lines are simultaneously effective, and accordingly simultaneous transmissions to a plurality of buffers are possible. For example, a data destination "000000001001" corresponds to 6 bit addresses "000001" and "000011", and the data effective signal for these two data destination becomes effective. Also, various modifications of such address representation are possible. An example of a multiprocessor system using an event transmission buffer of Fig. 6 is shown in Fig. 9. The system of Fig. 9 is constituted by processors 5(0), 5(1), ... 5(15), event transmission buffers 1(0), 1(1), ... 1(24), an input processor 61, and an output processor 62. The 16 processors are grouped into processor groups of 4 processors, and connected via event transmission buffers in a hierarchical manner. The processors 5(0) to 5(3), 5(4) to 5(7), 5(8) to 5(11), and 5(12) to 5(15) constitute the processor groups of the first hierarchy. The entirety of the processors 5(0) to 5(15) constitutes the processor group of the second hierarchy. The input processor 61 and the output processor 62 are connected to the upper device or other external device. In the case where data is transmitted from the processor 5(0) to the processor 5(3), the processor 5(0) causes only the data effective signal corresponding to the event transmission buffer 1(3) among the four data effective signal lines to be effective and carries out transmission of data accordingly. Assuming that the input signal from the processor 5(0) is designated to the input terminal of the buffer 101 of the device of Fig. 6, the data is received by the buffer 101. The received data is transmitted through the selection portion of the device of Fig. 6 to the processor 5(3). In the case where data is transmitted from the processor 5(4) to the processor 5(11), the data is transmitted through the event transmission buffer 1(21), the event transmission buffer 1(18), and the event transmission buffer 1(11). A system of data transfer between a plurality of processors according to another embodiment of the present invention is shown in Fig. 10. The structure of an event transmission unit used therein is shown in Fig. 11. The system of Fig. 10 includes a plurality of event transmission units 2(0), 2(1), 2(2) and 2(3) as a plurality of switching modules, a plurality of gate processors 500 to 515, and an upper event transmission unit 3. Each of the event transmission unit and the upper event transmission unit is constituted by a data receipt portion 31, a data hold portion 32, and a data selection delivery portion 33. The system of Fig. 10 is arranged in the hierarchical manner. The first event transmission unit 2(0) and the gate processors 500 to 503 constitute GROUP-0, the second event transmission unit 2(1) and the gate processors 504 to 507 constitute GROUP-1, the third event transmission unit 2(2) and the gate processors 508 to 511 constitute GROUP-2, and the fourth event transmission unit 2(3) and the gate processors 512 to 515 constitute GROUP-3. Each of the GROUP-0, GROUP-1, GROUP-2, and GROUP-3 belongs to the first hierarchy. The group constituted by the GROUP-0, GROUP-1, GROUP-2, and GROUP-3 belongs to the second hierarchy. It is possible to form a group of a higher level by assembling four groups of the same level, and it is possible that a processor will belong not to the lowest level group, i.e., the group of the first hierarchy, but to only the upper group. The data receipt portion 31 receives the data from the processors in the same group or the lower event transmission unit 2, and, if an upper group exists, the data from the upper group. The data hold portion 32 receives data from the data receipt portion 31 and holds the same until the data is delivered in succession to the data destination. The data selection delivery portion 33 selects and delivers the data held in the data hold portion 32 to the processors or the lower event transmission units 2, and, if an upper group exists, to the upper group. The processors 500 to 515, and the event transmission units are connected through signal lines. Where data is to be transmitted from the processor 500 to the processor 503, the processor 500 supplies the data to the event transmission unit 2(0), which transmits the data through a signal line to the processor 503. Where data is to be transmitted from the processor 504 to the processor 511, the processor supplies the data to the event transmission unit 2(1), which transmits the data via a signal line to the upper event transmission unit 3 - which transmits the data via a signal line to the event transmission unit 2(2) - which transmits the data to the processor 511. In each of the event transmission units, data from a data source is received by the data receipt portion and the received data is held in the data hold portion. A processor or an event transmission unit which instructs a data exchange can supply the data to be exchanged to an event transmission in question without being forced to switch to a waiting state, regardless of a data exchange by another processor or the like. When a plurality of data exchange instructions simultaneously exist for an event transmission unit, to cause competition for a data destination, the data selection delivery portion transmits the data held in the data hold portion in succession, in correspondence with a data destination and in accordance with the selection in the data selection delivery portion. Therefore, it is not necessary to provide an exclusive control process or the like. The structure of an event transmission unit 2 used in the data transfer system of Fig. 10 is shown in Fig. 11. The event transmission unit 2 is constituted by a plurality of event transmission buffers 1(0), 1(1), 1(2), 1(3), and 1(X), and signal lines interconnecting the same. The data from the lower elements in the same group is supplied through lines INPUT-0, INPUT-1, INPUT-2, and INPUT-3. The data from the upper device is supplied through a line INPUT-X. The data to the lower elements in the same group is delivered through lines OUTPUT-0, OUTPUT-1, OUTPUT-2, and OUTPUT-3. The data to the upper device is delivered through line OUTPUT-X. The data on one line includes, for example, n lines for data and 4 lines for data effective signals. The lines for data may include a parity bit. Data input through input lines INPUT-0 to INPUT-3 and INPUT-X is received by the corresponding event transmission buffers 1(0) to 1(3), and 1(X), if one of the data effective signals is "1". A comparison of the number of switching modules in the device of Fig. 10 as an embodiment of the present invention and that of a prior art multi-stage switching network shown in Fig. 12 is shown in Fig. 13. The number of the processors is N which is equal to the n-th power of 4. The number A of the switching modules required for the device of Fig. 10 is expressed as A = 1 3 (N-1) , and the number B of the switching modules required for the device of Fig. 12 is expressed as B = 1 4 ·N·log₄N . As can be seen in Fig. 13, the ratio A/B is greatly reduced as the number N of the processors is increased. This shows the device of Fig. 10 can contribute to a reduction of the number of switching modules, and accordingly, to a simplification of the structure of the network.

Claims: A multiprocessor system in which data processing is carried out by exchanging data among a plurality of processors (500, 501, ...; 5(0), 5(1), ...) interconnected via a plurality of data exchange means (2, 3, 1); said data exchange means being arranged to receive data from said processors, to deliver the received data selectively to other said processors, and to hold the received data until delivery thereof is enabled in the event of multiple data exchange requests among said processors; characterised in that:- said system has a hierarchical structure in which the processors are arranged in groups and the data exchange means are arranged as lower and upper data exchange means, wherein:- a lower level of said hierarchical structure is constituted by the processors in said groups (500, 501, 502, 503; 504, 505, 506, 507; ... or 5(0), 5(1), 5(2), 5(3); 5(4), 5(5), 5(6), 5(7); ... ); a lower data exchange means (2) is part of each respective group of processors and connected to all the processors in said group; a higher level is constituted by sets of several groups of the same level; an upper data exchange means (3) is provided for the or each set of groups and connected to all the lower data exchange means in said set; and in that each data exchange means (2, 3, 1) comprises : a data receipt portion (31) for receiving data from any processor of its respective group or from data exchange means of any lower group, and, if an upper group exists, from exchange means of the upper group; a data holding portion (32) for holding the received data; and a selective data delivery portion (33) for selectively delivering the received data to any processor of its respective group or to data exchange means of any lower group, and, if an upper group exists, to exchange means of the upper group. A system according to claim 1, further comprising an input processor (61) and an output processor (62, 63), both arranged at said higher level of the hierarchy, for supplying data to and receiving data from said upper data exchange means (3, 1), respectively. A system according to claim 1 or 2, wherein each of said data exchange means (2, 3, 1) comprises:- a plurality of buffers (101, 102, 103, ...) corresponding to said group of processors or set of lower data exchange means, for independently receiving and storing data therefrom; a buffer limit signal generating circuit (12) for delivering a buffer limit signal when an amount of data stored in any of said buffers reaches a predetermined limit; a data read signal generating circuit (13) for selecting one of said buffers (101, 102, 103, ...) and generating a data reading signal for said selected buffer based on a remaining amount of data and information concerning a vacancy in a buffer to which data is to be supplied; and a selected data delivery circuit (14) for receiving data selected by said data read signal generating circuit (13) and delivering said received data. A system according to claim 3, wherein each buffer (e.g. 101) comprises:- a memory cell array (101a) for storing data; a write address register (101d) for receiving data and transferring the data to said memory cell array; a read address register (101e) for designating an address of said memory cell array and transferring data from said memory cell array; and a subtraction portion (101f) connected to the write address and read address register, for signalling to said buffer limit signal generating circuit (12) when the amount of data stored in said memory cell array reaches said predetermined limit. A system according to any preceding claim, wherein each said data exchange means is constituted by an event transmission network unit (2, 3) having a plurality of event transmission buffers (1). A system according to any of claims 1 to 4, wherein each said data exchange means is constituted by a plurality of event transmission buffers (1(0), 1(1), ... 1(24)). A system according to any preceding claim, wherein the system is a simulation processor system (81), the processors are gate processors (GP0, GP1,...), and a control processor (7) is arranged to provide a start signal to, and receive an end signal from, each of the gate processors for the purposes of carrying out a simulation.

Inventors: HIROSE FUMIYASU, HIROSE, FUMIYASU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G06F15
IPC codes: G06F15, G06F17