Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration compri­ sing a high-voltage bipolar power transistor and a low-­ voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epita­ xial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active struc­ ture. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ e­ mitter region of the same transistor; the second re­ ceives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

Description: This invention concerns an integrated high-voltage bipolar power transistor and low-voltage MOS power transistor structure in the emitter switching configuration and the relative manufacturing process. Document EP-A- 0 247 660 discloses a device comprising a p + region in an n emitter. Emitter switching is a circuit configuration in which a low-voltage power transistor (typically an MOS transistor) cuts off the emitter current of a high-voltage power transistor (typically a bipolar transistor) in order to switch it off. This configuration, which up till now was commonly obtained by means of discrete components, offers the following advantages: it increases the strength of bipolar transistor as far as the possibility of inverted secondary ruptures (ESB) occurring are concerned; it combines the current and voltage carrying capacity of piloted transistor and the high speed of low-voltage transistor; it enables the system to be piloted directly with linear logic circuits, through the MOS gate. In view of the advantages that an integrated circuit generally offers, as compared to an analog circuit obtained by means of discrete components, the purpose of this invention is to provide a high-voltage bipolar power transistor and a low-voltage MOS power transistor, connected together in the emitter switching configuration, and integrated in a single chip of semiconductor material. For this purpose the invention offers the solutions referred to in the claims set forth further on. A structure according to the present invention is defined in claim 1. A process of manufacturing a structure according to the present invention is defined in claim 2. The features of such solutions will be more clearly evident from the following description and accompanying drawings of non-restrictive embodiments in which: Fig. 1: shows the equivalent electrical circuit of the 4-terminals integrated structures, which the invention intends to realize; Figs. 2-7: show a structure according to the invention, in the vertical MOS power transistor version, during the various stages of the manufacturing process; Fig. 8: shows the structure obtained at the end of the process referred to in the previous Figs. 2-7; Fig. 9: shows a diagram of the concentrations of the various types of doping agent along a section of the structure of Fig. 7. Fig.1 shows the equivalent electrical circuit of the 4-terminal integrated structures that the invention intends to provide. This circuit consists of a high-voltage bipolar power transistor T connected by means of its emitter to the drain of a low-voltage MOS power transistor P. The various stages of the manufacturing process of the integrated structure, in the vertical MOS version, are described hereunder. A first high resistivity N- conductivity epitaxial layer 2 is grown on an N+ type substrate 1 ( Fig.2 ). A P+ type region 3 is then obtained, by deposition or implantation and subsequent diffusion, on said layer 2 ( Fig. 3 ). An N+ type region 4 is then obtained by means of the same process ( Fig.4 ). This is followed by the growth of a second N type epitaxial layer 5 ( Fig.5 ) and, by the known procedures of oxidation, photomasking, implantation and diffusion, the creation of the P+ type regions 8, which enable the region 3 constituting the base of the bipolar transistor to be connected on the surface ( Fig.6 ). A low-voltage vertical MOS power transistor and in particular the relative P conductivity body regions 6, N+ type source regions 7 ( Fig.7 ), the gate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmic contact with the regions 6, 7, 8 and the substrate 1 ( Fig.8 ) are then created in the area between the two regions 8, according to known procedures. Fig. 8 shows the final structure, as it appears after addition of the terminals C (collector), B (base), S (source) and G (gate) and the insulating layer 12 of the gate 9 (said gate being connected to the relative terminal by means of the insulated conductor 13). Regions 1, 2, 3 and 4 of the figure constitute, respectively, the collector, the base and the emitter of a bipolar transistor, while region 5 constitutes the drain of the MOS. Said drain is consequently connected directly to the emitter of the bipolar transistor thus forming a structure having as its equivalent circuit the circuit of Fig. 1. The emitter 4 represents a completely buried N+ type active region; by growing a second N type epitaxial layer 5 it is thus possible to connect the drain of the MOS to the emitter 4 of the bipolar transistor. The profile of the concentration (Co) of the various types of doping agent in the different regions of the structure, along section A-A of Fig. 7, is shown in Fig.9 , where axis x refers to the distance from the upper surface of the structure. The final structure obtained is provided with 4 terminals, 3 of said terminals being located on one face of the chip and the 4th on the other face. The described process can obviously be used to simultaneously obtain, on the same chip, several pairs of bipolar and MOS transistors having a collector terminal in common and their base contacts, sources and gates connected to three respective common terminals by means of a metal coating carried out on the front of the chip at the end of the process.

Claims: Integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration, comprising: an N+ type semiconductor substrate (1), an overlying semiconductor layer (2,5), a first P+ type region (3) buried in the aforesaid layer (2), a second P+ type region (8) connecting the first aforesaid region on the surface, said first and second region constituting the base region of the bipolar transistor, a third N+ type region (4) with its lower part adjoining the aforesaid first region and constituting the emitter region of the bipolar transistor, wherein: the semiconductor layer (2, 5) consists of a first N-type epitaxial layer (2) and a second N type epitaxial layer (5) grown on it; the first region is located in the first epitaxial layer, in the vicinity of the surface adjacent to the second epitaxial layer, the second region is located in the second eptaxial layer, the third region (4) consists of a completely buried layer located astride between the boundary of the first and the second epitaxial layer, the P type body regions (6) of the MOS are located in the second epitaxial layer, in the vicinity of its surface and above the third region, the N+ type source regions (7) of the MOS are located inside said P type body regions (6), the drain region of the MOS consists substantially of the region of said second epitaxial layer between the third region and the aforesaid body regions. Process of manufacturing an integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration, of the type in which: a first high resistivity N- type epitaxial layer (2), designed to form the collector of the bipolar transistor, is grown on a N+ type substrate (1), a P+ conductivity region (3), designed to serve as the base of the bipolar transistor, and then an N+ type region (4), designed to serve as the buried emitter zone of the same transistor, are subsequently created on said first layer, by deposition or implantation and subsequent diffusion, wherein: a second N conductivity epitaxial layer (5), designed to constitute the drain region of the MOS transistor and at the same time automatically form the connection between the drain of the MOS transistor and the emitter of the bipolar transistor, is grown on the first epitaxial layer, P type body regions (6) of the MOS transistor are then created in the second epitaxial layer, N+ type source regions (7) are created inside said P type body regions, and a gate (9) is created partially above said source regions, by means of known processes, above the aforesaid buried emitter zone of the bipolar transistor, a P+ type region (8), which enables the base region of the bipolar transistor to be electrically connected on the surface, is also created at the side of said MOS transistor, by means of known techniaues of oxidation, photomasking, implantation and diffusion.

Inventors: FERLA GIUSEPPE, FRISINA FERRUCCIO, FERLA, GIUSEPPE, FRISINA, FERRUCCIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21