Time division switching for multi-channel calls using two time switch memories acting as a frame aligner

Abstract: Signals on an incoming highway of a time division switching system are written into an alternate one of first and second time switch memories and are sequentially read out of the other alternate one of the memories into the time slots of an outgoing highway of the system in accordance with a phase difference between incoming and outgoing frames and a time slot interchanging relationship between signals on the incoming highway and corresponding signals on the outgoing highway, so that the beginning of the outgoing frame coincides with one of the time slots of the incoming frame which is displaced from the beginning of the incoming frame by an amount equal to the detected phase difference. Alternatively, if the time slot of at least one signal of a multi-channel call on the incoming highway is later than the time slot of a corresponding signal on the outgoing highway, all signals of that multi-channel call are sequentially read out of the memories into a given outgoing highway so that they correspond to those on an incoming frame which is one frame prior to the one being written at the beginning of the given outgoing frame. If the time slots of all signals of a multi-channel call on the incoming highway are earlier than those of respectively corresponding signals on the outgoing highway, all signals of that multi-channel call are sequentially read out of the memories into an outgoing frame so that they correspond to those on an incoming frame which is being written at the beginning of the outgoing frame.

Description: BACKGROUND OF THE INVENTION The present invention relates generally to a time division switching system for signals on multi-channel calls. When switching multi-channel calls at multiples of the basic bearer speed, or basic traffic unit of the ISDN (integrated services digital network), it is required that signals on an outgoing highway must appear in the same sequence as they appear on the incoming highway, a requirement known as "time slot sequence integrity". To meet this requirement, the phase of a frame on incoming highways is rendered coincident with the phase of a corresponding frame on outgoing highways using two time switch memories 304 and 305 as shown in Fig. 1. This prior art time division switching system comprises a write-in counter 310 which provides the timing of the whole system. This counter is reset in response to a signal from a frame detector 309 at the beginning of an incoming frame on incoming highway 301. To switch the time slots #2 and #3 of a multi-channel call (b,c) to time slots #1 and #4, the output of the write-in counter 310 is applied as an address signal to time switch memories 304 and 305 to store in signals on multi-channel calls ( b₁,c₁ ) and ( b₂,c₂ ) into the storage locations #2 and #3 of memories 304 and 305, respectively. Control circuit 320 stores in read address codes "2" and "3" into storage locations #1 and #4 of the control memory 321, respectively. To secure the time slot sequence integrity, control memory 321 must wait for the completion of write operation on a given frame before proceeding with the read operation of that given frame (see Fig. 2). However, the incoming and outgoing frames must be in phase alignment with each other in order to secure time slot sequence integrity. If multi-channel calls are handled by a switching system of a TxSxT (time-space-time switch) configuration in which the phase relationship between incoming and outgoing frames is predetermined, a memory such as first-in-first-out (FIFO) must be used as a frame aligner. This adds to hardware volume and complexity. There is described, both in the specification of European Patent No. 0053267, which was published on June 9 1983, and in the specification of corresponding English language United States Patent Specification number 4,467,471, which was published on August 21 1984, a time-division multiplex switching system for multi-channel connections in which the control operations of the time slot multiples are simplified by employing one full memory in a writing operation during a first write pulse frame and another full memory in a writing operation during a succeeding second write pulse frame. A feature of a particular arrangement to be described is division switching system for multi-channel calls which allows time division switching without the use of a frame aligner while maintaining time slot sequence integrity. In one particular arrangement, the time division switching system includes an incoming highway for supporting an incoming frame having time slots in which signals of the multi-channel calls are carried and an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of the multi-channels calls appear. First and second time switch memories are provided, each having memory locations corresponding to the time slots of each of the incoming and outgoing frames. Signals on the incoming highway are written into an alternate one of the first and second time switch memories and signals are sequentially read out of the other time switch memory into specified time slots of the outgoing highway in accordance with a phase difference between the incoming and outgoing frames and an interchanging relationship between signals on the incoming highway and corresponding signals on the outgoing highway, so that the beginning of the outgoing frame coincides with the one of the time slots of the incoming frame which is displaced from the beginning of the incoming frame by an amount equal to the phase difference. A further feature of the arrangement is that, if the time slot of at least one signal of a given multi-channel call on the incoming highway is later than the time slot of a corresponding signal on the outgoing highway, all signals of the given multi-channel call are sequentially read into the time slots of a given outgoing highway from one of the first and second time switch memories in accordance with the phase difference and a time slot interchanging relationship between the incoming and outgoing frames so that the signals on the given outgoing frame correspond to those on an incoming frame which is one frame prior to the one being written into the other time switch memory at the beginning of the given outgoing frame. If the time slots of all signals of the given multi-channel call are earlier than the time slots of respectively corresponding signals on the outgoing highway, all signals of that multi-channel call of an incoming frame are sequentially read into the time slots of a given outgoing highway from one of the first and second time switch memories in accordance with the phase difference and a time slot interchanging relationship so that the signals on the given outgoing frame correspond to those on an incoming frame which is being written at the beginning of the given outgoing frame. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a prior art time division switching system; Fig. 2 is a timing diagram associated with Fig. 1; Fig. 3 is a block diagram of a time division switching system according to a first embodiment of the present invention; Fig. 4a is a flowchart associated with the Fig. 3 embodiment, and Fig. 4b is a sketch associated with the flowchart of Fig. 4a; Fig. 5 is a timing diagram associated with the Fig. 3 embodiment; Fig. 6 is a block diagram of a time division switching system according to a second embodiment of the present invention; Fig. 7 is a flowchart associated with the Fig. 6 embodiment; Fig. 8 is a timing diagram associated with the Fig. 6 embodiment; Fig. 9 is a block diagram of a time division switching system according to a third embodiment of the present invention; Fig. 10a is a flowchart associated with the Fig. 9 embodiment and Fig. 10b is a sketch associated Fig. 10a; Figs. 11a and 11b are timing digrams associated with the Fig. 9 embodiment; Fig. 12 is a flow chart associated with the Fig. 9 embodiment; and Figs. 13a and 13b are timing digrams associated with the Fig. 9 embodiment. DETAILED DESCRIPTION In Fig. 3, there is shown a time division switching system according to an embodiment of the present invention. The switching system comprises an incoming highway 101, a demultiplexer 102 connected to the incoming highway 101, a first time switch memory 104 having a data input terminal DI₁ connected to a first output terminal of the demultiplexer 102, a second time switch memory 105 having a data input terminal DI₂ connected to a second output terminal of the demultiplexer 102, a multiplexer 106 having a first input terminal connected to an output terminal DO₁ of the first time switch memory 104 and a second input terminal connected to an output terminal DO₂ of the second time switch memory 105, and an outgoing highway connected to the output terminal of the multiplexer 106. A frame detector 109 is connected to the incoming highway 101 to produce an output at the beginning of each incoming frame. Write-in counter 110 increments its count at intervals corresponding to the time slot intervals of incoming frames FI and is reset once for every two outputs from frame detector 109. The least significant bit to the second most significant bit of the counter 110 output are applied as a write address WA(t) to both of the time switch memories 104 and 105, the most significant bit being supplied to the control input of demultiplexer 102 as a memory space switching signal for switching the write-in timing of a memory space defined by the time switch memories 104 and 105 at times between successive incoming frames and further applied through a NOT circuit 111 to the control input of multiplexer 106 for switching the read timing of the memory space during the interval of each outgoing frame in a manner as will be understood later. A readout counter 112 is provided, which increments its count at intervals corresponding to the time slot intervals of outgoing frames FO. The output of readout counter 112 is applied as a read address RA(c) to a control memory 121 as well as to a latch 113 where the read address is latched in response to an output from the frame detector 109. The latched data represents a phase difference between incoming and outgoing frames. A control circuit 120 derives a write address WA(c) for the control memory 121 and a read address RA(t) for the time switch memories 104 and 105 from the phase difference as well as from relationships between the individual time slots of an incoming frame and the time slots of a corresponding outgoing frame to which the signals on the incoming highway are to be switched. Read address RA(t) is stored into the control memory 121 In accordance with the write address WA(c) and read out of the control memory in accordance with the read address data RA(c) from readout counter 112 and supplied as a read address to time switch memories 104 and 105. Fig. 4a is an illustration of an algorithm of the control circuit 120. As shown in Fig. 4b, incoming signals on highway 101 are designated as Xj (where j represents time slot number ranging from 1 to M) and outgoing signals on highway 108 are designated as Yj. The interframe phase difference is indicated by D and the incoming frame extends between time slots T₁ and T n and the corresponding outgoing frame extends between time slots S₁ and S n . The operation of the algorithm starts with block 200 which directs the reading of signals Xj, Yj, and D. Exit then is to operations block 201 which directs the modulo subtraction of Yj - D and designating the result as Cj. Control proceeds to operations block 202 which directs the setting of the parameter j to one. Exit then is to operations block 203 which directs the finding of a minimum value of Cj among C₁ through C M and designating it as Ej. Control advances to operations block 204 to provide modulo summation of Ej and D, which is followed by operations block 205 which directs the switching of Xj to Ej. Exit is to operations block 206 which increments the parameter j by one, which is compared with M in decision block 207 to determine if j is equal to or smaller than M. If the parameter j is smaller than M, the answer in block 207 is affirmative and control returns to block 203 to repeat the above process, and otherwise, it ends the process. The operation of the embodiment of Fig. 4a will be described with reference to a timing diagram shown in Fig. 5. Assume that the switching system receives incoming frames FI₁ and FI₂ each carrying TDM signals b and c (each with a subscript identifying the frame in which they are carried) on the #2 and #3 time slots, respectively, on the incoming highway 101. It is further assumed that there is a phase difference of two time slots between the incoming and outgoing frames. This phase difference is detected by the latch 113 in response to an output of frame detector 109 at the beginning of the frame FI₁ and fed to the control circuit 120. Simultaneously, the write-in counter 110 is reset by the frame detector 109 output and supplied as a write address WA(t) to the time switch memories 104 and 105 so that TDM signals b₁ and c₁ are respectively stored into the #2 and #3 storage locations of time switch memory 104 and TDM signals b₂ and c₂ are respectively stored into the #2 and #3 storage locations of time switch memory 105. With a phase difference D being equal to 2, and X₁=2, X₂=3, Y₁=1 and Y₂=4, the execution of block 201 gives a result that C₁ and C₃ are respectively equal to "3" and "2". In block 203, E₁ becomes equal to C₂, i.e., C₂ is detected as a minimum of the signals and, X₁=2 is switched to E₁=2 + 2 = 4 in block 205. Likewise, E₂ is equal to C₁, and therefore X₂=3 is switched to E₂ which is a modulo sum of 3 + 2 = 1. On the other hand, control circuit 120 determines that #4 time slot of frame FO₁ and #1 time slot of frame FO₂ are the destination (sink) slots from the phase difference as well as from a switching control signal supplied from an external source and proceeds to relate the incoming time slot #2 to outgoing time slot #4 and incoming time slot #3 to outgoing time slot #1 by writing a code "2" into the #4 storage location of control memory 121 and a code "3" into the #1 storage location of that memory. Read operation is performed on one of the time switch memories 104 and 105 in accordance with the read address RA(t) from control memory 121 during the time write operation is being carried out on the other time switch memory. Memory space is switched in this way from one time switch memory to the other during the interval of an outgoing frame as marked by triangles in Fig. 5. More specifically, a TDM signal c₀ on an incoming frame that precedes frame FI₁ is read out of the storage location #3 of time switch memory 105 during the time slot #1 of outgoing frame FO₁ and TDM signal b₁ on incoming frame FI₁ is read out of the storage location #2 of time switch memory 104 during the time slot #4 of that outgoing frame. In this way, the incoming TDM signals b₁, c₁, b₂, c₂ can be switched to the #1 and #4 time slots of the outgoing highway 108, while retaining their order of occurrence. A modified embodiment of the present invention is shown in Fig. 6. This embodiment comprises an incoming highway 401, a demultiplexer 402 connected to the incoming highway 401, a first time switch memory 404 having a data input terminal DI₁ connected to a first output terminal of the demultiplexer 402, a second time switch memory 405 having a data input terminal DI₂ connected to a second output terminal of the demultiplexer 402, a multiplexer 406 having a first input terminal connected to an output terminal DO₁ of the first time switch memory 404 and a second input terminal connected to an output terminal DO₂ of the second time switch memory 405, and an outgoing highway 408 connected to the output terminal of the multiplexer 406. A frame detector 409 is connected to the incoming highway 401 to produce an output at the beginning of each incoming frame. Write-in counter 410 increments its count at intervals corresponding to the time slot intervals of incoming frames FI and is reset in response to each output from the frame detector 409. A readout counter 412 increments its count at intervals corresponding to the time slot intervals of outgoing frames FO. The second most significant bit to the least significant bit of the outputs of readout counter 412 are applied as a read address RA(c) to a control memory 421. The most significant bit of the output of readout counter 412 is applied to the demultiplexer 402 as a memory space switching signal for switching the write-in timing of a memory space defined by time switch memories 404 and 405 during the interval of each incoming frame and further applied through a NOT circuit 411 to the control input of multiplexer 406 for switching the read timing of the memory space at times between successive outgoing frames. This MSB output is also applied to a latch 413 to latch a write address WA(t) from the write-in counter 410 to produce an output representative of a phase difference between incoming and outgoing frames. A control circuit 420 derives a write address WA(c) for the control memory 421 and a read address RA(t) for the time switch memories 404 and 405 from the phase difference as well as from relationships between the individual time slots of an incoming frame and those time slots of an outgoing frame corresponding to that incoming frame. The read address RA(t) is stored into the control memory 421 in accordance with the write address WA(c) and read out of the control memory in accordance with the read address data RA(c) from readout counter 412 and supplied as a read address to time switch memories 404 and 405. The algorithm of the control circuit 420 is shown in Fig. 7 which is similar to that of Fig. 4a with the exception that the blocks 201 and 205 of Fig. 4a are replaced with blocks 210 and 211. In block 210, modulo subtraction of Xj - D is calculated and the modulo-subtraction is designated as Cj and in block 211 Yj is switched to Ej. With a phase difference D being equal to 2, and X₁=2, X₂=3, Y₁=1 and Y₂=4, the execution of block 210 gives a result that C₁ and C₂ are respectively equal to "4" and "1". In block 203, E₁ becomes equal to C₂, i.e., C₂ is detected as a minimum of the signals, X₁=2 is switched to E₁=2 + 2 = 4 in block 205. Likewise, E₁ is equal to C₁, and therefore X₂=3 is switched to E₂ which is a modulo sum of 3 + 2 = 1. In a manner similar to the previous embodiment, control circuit 420 relates incoming time slot #2 to outgoing time slot #4 and incoming time slot #3 to outgoing time slot #1 by writing a code "2" into the #4 storage location of control memory 421 and a code "3" into the #1 storage location of that memory. In this embodiment memory space switching between time switch memories 404 and 405 occurs during the interval of each incoming frame as marked by triangles in Fig. 8. Even if there is a phase difference between incoming and outgoing frames, TDM signals can be switched without altering their sequence by the use of memories having the total capacity of two frames. It is seen that the time switch memories not only serve as a time slot interchanger but also serve as a frame aligner. While mention has been made of a sequential-write-and-random-read mode of operation, a random-write-and-sequential-read mode of operation could equally be as well used in the present invention. With the previous embodiments, time slot sequence integrity will be lost if at least one signal of a multi-channel call on the incoming highway is later than a corresponding signal on the outgoing highway. A modified embodiment of the invention shown in Fig. 9 avoids this problem. Similar to the previous embodiments, the time division switching system of Fig. 9 comprises an incoming highway 501, a demultiplexer 502 connected to the incoming highway 501, a first time switch memory 504 having a data input terminal DI₁ connected to a first output terminal of the demultiplexer 502, a second time switch memory 505 having a data input terminal DI₂ connected to a second output terminal of the demultiplexer 502, a multiplexer 506 having a first input terminal connected to an output terminal DO₁ of the first time switch memory 504 and a second input terminal connected to an output terminal DO₂ of the second time switch memory 505, and an outgoing highway 508 connected to the output terminal of the multiplexer 506. A frame detector 509 is connected to the incoming highway 501 to produce an output at the beginning of each incoming frame. A write-in counter 510 increments its count at intervals corresponding to the time slot intervals of incoming frames FI and is reset once for every two outputs from frame defector 509. The least significant bit to the second most significant bit of the counter 510 output are applied as a write address WA(t) to both of the time switch memories 504 and 505, the most significant bit being supplied to the control input of demultiplexer 502 as a memory space switching signal for switching the write-in timing of a memory space defined by the time switch memories 504 and 505. A readout counter 512 increments its count at intervals corresponding to the time slot intervals of the time slot number of outgoing frames FO to produce a binary output, the second most significant bit to the least significant bit of the counter being applied as a read address RA(c) to a control memory 521 as well as to a latch 513. The most significant bit of the counter 512 output is applied to the latch 513 as well as to an exclusive-OR gate 511. A control circuit 520 derives a write address WA(c) for the control memory 521 and a read address RA(t) for the time switch memories 504, and 505 from a switching control signal applied thereto and writes the read address codes RA(t) identifying incoming time slots into the storage locations of the control memory 521 which in turn respectively correspond to outgoing time slots. All bits of the counter 512 output, which are stored in the latch 513, represent a phase difference between the incoming and outgoing frames. If the phase difference is less than a frame interval, the latched MSB is a binary 1 and if the phase difference is between a frame interval and a two-frame interval, the latched MSB is a binary 0. Control memory 521 has a plurality of control bit cells associated respectively to the individual storage locations of that memory to store a binary 1 or 0. Control circuit 520 operates according to an algorithm which is shown in the form of a flowchart in Fig. 10a. Similar to Fig. 4b, incoming signals on highway 501 are designated as Xj (where j represents time slot number ranging from 1 to M) and outgoing signals on highway 508 are designated as Yj as shown in Fig. 10b. The interframe phase difference is indicated by D and the incoming frame extends between time slots T₁ and T n and the corresponding outgoing frame extends between time slots S₁ and S n . Program execution starts with operations block 600 which directs the reading of input data including signals Xj, Yj, and D. Exit is to block 601 which directs the modulo summing of outgoing signal Yj and the phase difference D to give a modulo-sum Cj. Control proceeds to operations block 602 in which signal sequence number j is initialized to one to begin processing with a first signal of each multi-channel call. In decision block 603, control determines whether the time slot number of incoming signal Xj is greater than the phase difference D and at the same time if the modulo-sum Cj is smaller than the end time slot number T n . This means that if an incoming signal Xj is located between the beginning (S₁) of a first outgoing frame and the end (T n ) of a first incoming frame which at least partially overlaps with the first outgoing frame and if a corresponding (sink) outgoing signal Cj is located between the beginning ( =T n + D ) of a second, subsequent outgoing frame and the end (2T n + D) of a second, subsequent incoming frame, namely, Xj > D and 2T n + D > Cj > T n + D = Tn > Cj , then the decision is affirmative. If the answer is affirmative in block 603, exit is to decision block 604 to determine if the phase difference is smaller than one frame or greater than one frame but smaller than two frames. If the phase difference is smaller than one frame, the counter 512 MSB output is 1 and control proceeds to operations block 605 to generate binary 1 and otherwise, the MSB output is 0 and control proceeds to operations block 609 to generate a binary 0. If the decision in block 603 is negative, exit is to operations block 606 to increment j by one and control advances to decision block 607, which determines if j is equal to or smaller than M. If Xj is greater than D and Cj is smaller than T n , it cannot be read without delay and so all the signals of the multi-channel calls are read in a subsequent outgoing frame. Under such circumstances, the decision in block 603 will be affirmative and a binary 1 is generated if the counter 512 MSB is 1 or a binary 0 if the counter 512 MSB is 0. If the decision in block 603 is negative, a binary 0 is generated if the counter 512 MSB is 1 or a binary 1 if the counter 512 MSB is 0. The operation of the flowchart of Fig. 10a will be better understood with reference to Figs. 11a and 11b which respectively illustrate timing diagrams with a phase difference of three time slots and a phase difference of one-frame plus three time slots. In Fig. 11a, it is assumed that incoming frames FI₁ and FI₂ each carry signals A₁ and A₂ of a multi-channel call A on #5 and #7 time slots and signals B₁ and B₂ of a multi-channel call B on #3 and #8 time slots, and incoming time slots #5 and #7 are respectively switched to outgoing time slots #3 and #5 and incoming time slots #3 and #8 are respectively switched to outgoing two slots #2 and #4. Switching signals indicating the relationships between incoming and outgoing time slots and phase difference data are supplied to the control circuit 520 from an external source (block 600) to begin processing the multi-channel signals A₁ and A₂ in succession by executing blocks 601, 602 and 603. Thus, decisions for signal A₁ and A₂ are affirmative in block 603, resulting in the writing of a binary 1 into the control bit cells #3 and #5 of memory 521. In like manner, signals B₁ and B₂ are processed to give an affirmative decision in block 603 and a binary 1 is written into the control bit cells #2 and #4 of memory 521. Control bits of "1111" are therefore stored into the control bit cells of memory 521 which are associated respectively with the #2, #3, #4 and #5 storage locations of memory 521 in response to the write address WA(c) together with the corresponding read address data RA(t) and read out of this memory in response to the read address RA(c) from the readout counter 512. The control bits are supplied to one input of an exclusive-OR gate 511 to which the MSB output of readout counter 512 is also applied and the read address RA(t) is supplied to the time switch memories 504 and 505. The output of exclusive-OR gate 511 is applied as a memory space switching signal to the multiplexer 506. The purpose of the exclusive-OR gate 512 is to alternately reverse the binary state of the memory space switching signal during successive frames in step with changes in binary level of the MSB of readout counter 512. Since signal B₂₁ cannot be read during the outgoing frame FO₁, all signals A₁₁, A₂₁, B₁₁ and B₂₁ are read during the subsequent outgoing frame FO2 from the time switch memory 504 which now stores the signals of incoming frame FI₁. A sequence of "1111" bits is generated by exclusive-OR gate 511 during one outgoing frame and a sequence of "0000" bits is generated during a succeeding outgoing frame. If the phase difference is greater than one frame interval but smaller than two-frame interval, the latched MSB output of counter 512 is a binary 0 at the beginning of the first incoming frame and it changes to binary 1 during outgoing frame FO₁ and then to binary 0 during outgoing frame FO₂ as shown in Fig. 11b. Control circuit 520 generates a binary-0 control bit for all signals A₁, A₂, B₁, and B₂ to signify that signals of multi-channel calls A and B be read with one frame delay. Thus, binary 0 is generated for outgoing time slots #2, #3, #4 and #5. In this way, the sequence of bits generated by exclusive-OR gate 511 during each outgoing frame is the same as in the case of the smaller-than-one-frame phase difference. Fig. 12 is a flowchart of a modified form of the algorithm of Fig. 11a. The modified algorithm is similar to that of Fig. 11a with the exception that the decision block 603 of the previous embodiment is replaced with decision block 700 which determines whether Xj is greater than Cj. This algorithm will be understood with reference to Figs. 13a and 13b which correspond respectively to Figs 11a and 11b. In Fig. 13a, the decision in block 700 for signals A₁ and A₂ is negative, resulting in the generation of a binary 0 for counter 512 MSB-1 and a binary 1 or the MSB-0 and the decision in block 700 is negative for signal B₁ and affirmative for signal B₂. Control bits of "1010" are therefore stored into the control bit cells of memory 521 when the phase difference is smaller than one frame and control bits "0101" are stored into the control bit cells when the phase difference is greater than one frame but smaller than two frames (Fig. 13b). A sequence of "1010" bits is generated by exclusive-OR gate 511 during one outgoing frame and a sequence of "0101" bits is generated during a succeeding outgoing frame. Signals A₁₁ and A₂₁ are therefore read during the outgoing frame FO₁ from the time switch memory 504 which now stores the signals of incoming frame FI₁ and signals B₁₁ and B₂₁ are read during outgoing frame FO₂ from the same time switch memory. The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims: A time division switching system for multi-channel calls, comprising an incoming highway (101) for supporting an incoming frame having time slots in which signals of the multi-channel calls are carried, an outgoing highway (108) for supporting an outgoing frame having time slots in which corresponding signals of the multi-channels calls are carried, first and second time switch memories (104, 105), write address means (110) for supplying a write address (WA(t)) in synchronism with the time slots of each incoming frame to the time switch memories (104, 105), a demultiplexer (102) for supplying the incoming frames alternately to locations of the time switch memories (104, 105) specified by the write address (WA(t)), a multiplexer (106) connected between the time switch memories (104, 105) and the outgoing highway (108), a control memory (121) having memory locations corresponding to the time slots of each outgoing frame, control means (120) for generating read addresses (RA(t)) of the time switch memories (104, 105) according to a switching signal and writing the read addresses (RA(t)) into a location of the control memory (121) specified by a write address (WA(c)) and reading the read addresses (RA(t)) from the control memory (121) into the time switch memories (104, 105) according to a read address (RA(c)) so that signals stored in the time switch memories are supplied to the multiplexer (106), and readout means (112) for generating and supplying said read address (RA(c)) to the control memory (121) in synchronism with each time slot of the outgoing frame, characterized by a frame detector (109) connected to the incoming highway for detecting the beginning of each incoming frame to produce an output signal, and latch means (113) for latching the read address (RA(c)) from said readout means (112) as an indication of a phase difference between the incoming and outgoing highways in response to the output signal from the frame detector (109), and in that the control means (120) generates said read address (RA(t)) and said write address (WA(c)) according to the latched address (RA(c)). A time division switching system for multi-channel calls, comprising an incoming highway (401) for supporting an incoming frame having time slots in which signals of the multi-channel calls are carried, an outgoing highway (408) for supporting an outgoing frame having time slots in which corresponding signals of the multi-channels calls are carried, first and second time switch memories (404, 405), write means (410) for supplying a write address (WA(t)) in synchronism with the time slots of each incoming frame to the time switch memories (404, 405), a demultiplexer (402) for supplying the incoming frames alternately to locations of the time switch memories (404, 405) specified by the write address (WA(t)), a multiplexer (406) connected between the time switch memories (404, 405) and the outgoing highway (408), a control memory (421) having memory locations corresponding to the time slots of each outgoing frame, control means (420) for generating read addresses (RA(t)) of the time switch memories (404, 405) according to a switching signal and writing the read addresses (RA(t)) into a location of the control memory (421) specified by a write address (WA(c)) and reading the read addresses (RA(t)) from the control memory (421) into the time switch memories (404, 405) according to a read address (RA(c)) so that signals stored in the time switch memories are supplied to the multiplexer (406), and readout means (412) for generating and supplying said read address (RA(c)) to the control memory (421) in synchronism with each time slot of the outgoing frame, characterized by latch means (413) for latching the write address (WA(t)) from said write means (410) in response to the generation of a most significant bit of said read address (RA(c)) as an indication of a phase difference between the incoming and outgoing highways, and in that the control means (420) generates said read address (RA(t)) and said write address (WA(c)) according to the latched address (WA(t)). A time division switching system for multi-channel calls, comprising an incoming highway (501) for supporting an incoming frame having time slots in which signals of the multi-channel calls are carried, an outgoing highway (508) for supporting an outgoing frame having time slots in which corresponding signals of the multi-channels calls are carried, first and second time switch memories (504, 505), write address means (510) for supplying a write address (WA(t)) in synchronism with the time slots of each incoming frame to the time switch memories (504, 505), a demultiplexer (502) for supplying the incoming frames alternately to locations of the time switch memories (504, 505) specified by the write address (WA(t)), a multiplexer (506) connected between the time switch memories (504, 505) and the outgoing highway (508), a control memory (521) having memory locations corresponding to the time slots of each outgoing frame, control means (520) for generating read addresses (RA(t)) of the time switch memories (504, 505) according to a switching signal and writing the read addresses (RA(t)) into a location of the control memory (521) specified by a write address (WA(c)) and reading the read addresses (RA(t)) from the control memory (521) into the time switch memories (504, 505) according to a read address (RA(c)) so that signals stored in the time switch memories are supplied to the multiplexer (406), and readout means (512) for generating and supplying said read address (RA(c)) to the control memory (521) in synchronism with each time slot of the outgoing frame, characterized by a frame detector (509) connected to tile incoming highway for detecting the beginning of an incoming frame, and latch means (513) for latching the read address (RA(c)) as an indication of a phase difference between the incoming and outgoing highways in response to an output signal from the frame detector (509), and in that the control means (520, Figs. 9, 10a) includes means for making a first decision when an incoming signal of a given multi-channel call is located between the beginning of a first outgoing frame (FI₁) and the end of a first incoming frame (FO₁) which at least partially overlaps the first outgoing frame (FI₁) and a corresponding outgoing signal is located between the beginning of a second outgoing frame (FI₂) and the end of a second incoming frame (FI₂), making a second decision otherwise, sequentially reading, in response to the first decision, all signals of said given multi-channel call from one of said first and second time switch memories (504, 505) into time slots of said second outgoing frame (FO₂) which time slots are specified by the latched address (RA(c)) and sequentially reading, in response to the second decision, all signals of said given multi-channel call from one of said time switch memories into time slots of said first outgoing frame (FO₁) which time slots are specified by the latched address (RA(c)). A time division switching system for multi-channel calls, comprising an incoming highway (501) for supporting an incoming frame having time slots in which signals of the multi-channel calls are carried, an outgoing highway (508) for supporting an outgoing frame having time slots in which corresponding signals of the multi-channels calls are carried, first and second time switch memories (504, 505), write address means (510) for supplying a write address (WA(t)) in synchronism with the time slots of each incoming frame to the time switch memories (504, 505), a demultiplexer (502) for supplying the incoming frames alternately to locations of the time switch memories (504, 505) specified by the write address (WA(t)), a multiplexer (506) connected between the time switch memories (504, 505) and the outgoing highway (508), a control memory (521) having memory locations corresponding to the time slots of each outgoing frame, control means (520) for generating read addresses (RA(t)) of the time switch memories (504, 505) according to a switching signal and writing the read addresses (RA(t)) into a location of the control memory (521) specified by a write address (WA(c)) and reading the read addresses (RA(t)) from the control memory (521) into the time switch memories (504, 505) according to a read address (RA(c)) so that signals stored in the time switch memories are supplied to the multiplexer (406), and readout means (512) for generating and supplying said read address (RA(c)) to the control memory (521) in synchronism with each time slot of the outgoing frame, characterized by a frame detector (509) connected to the incoming highway for detecting the beginning of an incoming frame, and latch means (513) for latching the read address (RA(c)) as an indication of a phase difference between the incoming and outgoing highways in response to an output signal from the frame detector (509), and in that the control means (520, Figs. 9, 12) includes means for making a first decision when at least one signal of a given multi-channel call of a given incoming frame (FI₁) is later than a corresponding signal of a succeeding outgoing frame (FO i ) which immediately follows the given incoming frame (FI₁), or a second decision when all signals of said given multi-channel call are earlier than corresponding signals of said succeeding outgoing frame (FO i ), and reading, in response to said first decision, all signals of said given multi-channel call from one of the first and second time switch memories into time slots of an outgoing frame (FO i+1 ) subsequent to said succeeding outgoing frame (FO i ) which time slots are specified by the latched address (RA(c)), and reading, in response to said second decision, all signals of said given multi-channel call from one of the time switch memories into time slots of said succeeding outgoing frame (FO i ) which time slots are specified by the latched address (RA(c)). A time division switching system as claimed in claim 3 or 4, characterized in that said control memory (521) has additional memory locations corresponding respectively to the time slots of an outgoing frame, and in that said control means (520) writes a bit "1" into one of the additional memory locations specified by the write address (WA(c)) in response to said first decision, and writes a bit "0" into said one additional memory location in response to said second decision, and reads a bit from one of said additional memory locations specified by the read address (RA(c)), and in that exclusive-OR gate means (511) is arranged to receive the bit read from said additional memory locations and a most significant bit of the read address (RA(c)) from the readout means (512); and in that the multiplexer (506) is responsive to an output signal from the exclusive-OR gate means (511) for multiplexing signals from the first and second time switches (504, 505). A time division switching system as claimed in claim 5, characterized in that the value of said bit to be stored into said additional memory locations is reversed each time the phase difference is greater than one frame interval but smaller than two frame intervals.

Inventors: HAYANO SIN-ICHIRO, HAYANO, SIN-ICHIRO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H04Q11
IPC codes: H04Q11, H04J3