PROGRAMMABLE MULTIPLEXING/DEMULTIPLEXING SYSTEM

Abstract: A programmable multiplexing/demultiplexing system used in a digital communication network, suitable for an ISDN to be developed. The System includes a phase adjusting unit (100), a bit length varying unit (200), a start timing control unit (300), and a processor (20) which variably controls the three units. The phase adjusting unit (100) variably controls the phase of an internal clock in accordance with received data, and the thus-adjusted clock is used by the remaining two units. Whereby the bit length varying unit (200) variably controls the bit length of the received data, and the start timing control unit (300) variably controls the start timing of each transmission and reception processing carried out alternately by the processor (20).

Description: 1. Field of the Invention The present invention relates to a programmable multiplexing/demultiplexing system. A worldwide Integrated Service Digital Network (ISDN) is being developed, and a standardization thereof is being studied by CCITT. As well known, in the ISDN, voice, data, and image etc., signals output from many different types of terminal equipment are converted to digital signals, and various services are provided by processing these digital signals. When constructing an ISDN, i.e., forming a new communication network, a wide range of communication apparatuses, and at the same time, communication software, must be developed, and thus from the hardware viewpoint, many kinds of large scale integrated circuits (LSI's) also must be developed. Development of the ISDN is still in the initial stages, and therefore, no specific definitions of the kinds of functions and services to be provided by the ISDN have been formulated. Under these circumstances, it is obvious that facilities which can adaptively cope with future service needs must be developed. 2. Description of the Related Art In regard to the above, from the economical viewpoint, it is very risky to develop many new LSI's, especially since it would be difficult to cope with modifications of or additions to the functions of the ISDN by attempting to develop an exclusive LSI for each modification and addition, since, if an LSI has not been developed for a particular function, the costs of developing such an LSI, and the time and labor spent thereon would be unwarranted. Further, the design of a new LSI is time-consuming, and accordingly, a rapid development thereof is not possible, which means that a quick response to future service needs would be difficult to accomplish. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a programmable multiplexing/demultiplexing system which can be built by using a single exclusive LSI. This exclusive LSI can provide the various bit processing functions which would be realized in the prior art by employing a plurality of exclusive LSI's. To attain the above object, a programmable multiplexing/demultiplexing system according to the present invention is provided in which serial data received via a receiving line is converted into parallel data and latched by a latch circuit, the latched received data is read by a processor and stored in a memory to apply an internal processing to the received data and the processed data is output, as serial data, to a transmission line, characterized in that the system includes therein, at least: a phase adjusting means variably controlling a phase of a clock signal by said processor in accordance with the received data; a bit length varying means variably controlling a length of the received data by said processor when latched with said clock signal adjusted in phase by said phase adjusting means; and a start timing control means varying a start timing of a processing for the received data by said processor, when the processing is to be started after a processing of a transmitted data. The phase adjusting means is used for a variable control of the phase of a clock signal by the processor with respect to received data; the bit length varying means is used for a variable control of the length of the received data by the processor when latched with a clock signal having a phase which has been adjusted by the phase adjusting means; and the start timing control means is used for varying a start timing of the processing of data received by the processor, after the processor has processed data to be transmitted. BRIEF DESCRIPTION OF THE DRAWINGS The above object and features of the present invention will be more apparent from the following description of the preferred embodiments with reference to the accompanying drawings, wherein: Fig. 1 shows an example of a system to which the present invention is applied; Fig. 2 is a general and simplified view of the system according to the present invention; Fig. 3 shows an example of a phase adjusting means; Fig. 4 is a structural view showing the principle of the phase adjusting means of the present invention; Fig. 5 shows a specific example of a part of Fig. 4; Fig. 6 is a timing chart indicating the status at each major portion in Fig. 5; Fig. 7 shows a detailed example of a U/D counter; Fig. 8 shows an example of a phase adjusting unit; Fig. 9 is a flow chart of an operation of a processor; Fig. 10 shows an example of a prior art serial/parallel converter; Fig. 11 is a structural view showing a principle of a bit length varying means of the present invention; Fig. 12 shows a specific example of the bit length varying means of the present invention; Fig. 13 is a timing chart of an operation of the bit length varying means; Fig. 14 is a flow chart of an operation of the bit length varying means; Fig. 15 is a timing chart of a flow of the transmitted and received data; Fig. 16A and 16B are flow charts of a prior art procedure for processing the transmitted-received data; Fig. 17 is a schematic view of a construction showing a principle of the start timing control means; Fig. 18 shows an example of the start timing control means; Fig. 19 is a view of signal patterns at the normal time and at the test time; Fig. 20 is an enlarged timing chart of the test time of Fig. 19 in relation to the timer counter and the time resistor; Fig. 21 is a flow chart of an example of the transmission processing program; and Fig. 22 is a flow chart of an example of the reception processing program. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows an example of a system to which the present invention is applied. In the figure, the present invention is preferably applied to a terminating equipment ET for an exchange and/or a terminating equipment NT for a subscriber. The terminating equipment ET for an exchange is connected, via a transmission line L (corresponding, in this example, to a subscriber line), to the terminating equipment NT for a subscriber. NT and ET are ISDN symbols, and this equipment is usually called a digital service unit (DSU), and the terminating equipment ET is usually called an office channel unit (OCU). These units NT and ET are located between a center side exchange EX and terminal unit TE, such as a facsimile unit, a telephone, a personal computer, and the like. The programmable multiplexing-demultiplexing system (hereinafter, often referred to briefly as MUX/DMUX system) is formed in the terminating equipment NT and/or the terminating equipment ET, and the nucleus thereof, according to the present invention, is the above-mentioned exclusive LSI. Figure 2 is a general and simplified view of the system according to the present invention. The programmable multiplexing/demultiplexing system (MUX/DMUX system) 10 is mainly comprised of a phase adjusting means 100, a bit length varying means 200, a start timing control means 300, and a processor (MPU) 20. The phase adjusting means 100 includes a phase adjusting unit, a first register (REG1), and a frequency divider (FREQ DIV); the bit length varying means 200 includes a counter, a second register (REG2), a comparator, and a flag register (FR); the start timing control means 300 includes a third register (REG3) and a timer counter; and, the processor 20 processes data transmissions and receptions, together with a memory, via a bus. S/P indicates a serial/parallel converter and P/S a parallel/serial converter. Each serial/parallel converter (S/P) is formed as a latch circuit for momentarily storing the received data converted into parallel data. The operation of the MUX/DMUX system and details of the construction thereof will now be described. Note, the means 100, 200, and 300 will be described separately and independently, for a clear explanation of each means, and this description will include a description of the arts related to each means. Phase adjusting means 100 In a digital communication network, usually data, having a clock CK e , is sent via a transmission line and is received by a receiving apparatus having an internal clock Ck i . In this case, if the CK i does not follow the CK e , it is impossible to correctly process the data, and a mishit occurs. To prevent this, a clock phase synchronizing circuit is mounted in the receiving apparatus. In general, the clock phase synchronizing circuit is constructed as a DPLL. Figure 3 is a view showing an example of a phase adjusting means in an MUX/DMUX system which is part of a usual digital communication network. Data DT output from an exchange EX having a transmission line L is sent to a terminating equipment NT and finally to, for example, a facsimile unit, a telephone, or a personal computer, etc. The exchange EX includes a master clock source and outputs data DT, synchronized with an external clock CK e obtained by dividing the master clock MCK e , to the transmission line L. The terminating equipment NT receiving the data DT includes a master clock source. The master clock MCK i is divided by a frequency divider 112 to obtain an internal clock CK i by which a variety of circuits, such as a processor 20 and so on, are operated. In this case, the CK i should be synchronized with an external clock CK e extracted from the received serial data DT, and accordingly, a phase comparison unit 113 determines whether the internal clock CK i is lagging or leading in phase with respect to the external clock CK e . A phase adjusting unit 111 is informed of this lag or lead and effects a pulse insertion (in the case of a lag) or a pulse removal (in the case of a lead), both in pulse units, to or from a clock signal, i.e., the master clock CK i . The above-mentioned lag or lead phase (±ϑ) is detected in the clock (CK e or CK i ) unit, and the above pulse insertion or removal is carried out at every clock. Nevertheless, when such a phase adjustment is carried out at every clock, an unpreferable jitter appears in the internal clock CK i . Further, when the phase is promptly adjusted even when a noise appears only momentarily, this unpreferable jitter is emphasized. In the above circumstances, a protection stage number is employed whereby the pulse insertion or removal is not carried out at every clock. Namel, assuming that the protection stage number is set at , a pulse insertion is not carried out until the lag in phase has occurred 10 times continuously, or a pulse removal is not carried out until the lead in phase has occurred 10 times continuously; i.e., a hysteresis control is realized, and thus the internal clock CK i is stabilized. In the above example, the pulse insertion or removal is not carried out until the lag or lead in phase has occurred 10 times continuously. Accordingly, for example, even at a power-ON or when an input signal is not synchronized, the pulse insertion or pulse removal is carried out by using the number 10 as a standard. But this raises a problem in that a considerably long time must elapse before an acquisition of synchronism, when establishing a phase synchronization. Further, at a power-ON and when the input signal is not synchronized, a time allowed for an acquisition of synchronism is only several 10 µs, and thus another problem arises in that, even if a considerably long time has elapsed when establishing a phase synchronization, it is impossible for an operator to select a suitable protection stage number to be determined before and after an acquisition of synchronism, within such a very short time. The phase adjusting means 100 rapidly carries out a phase adjustment before an acquisition of synchronism, and realizes the phase adjustment with a satisfactory predetermined protection stage number after the acquisition of synchronism, and further, carries out the phase adjustment without the need for a manual operation. Figure 4 is a structural view showing the principle of the phase adjusting means of the present invention. In the figure, the phase adjusting means 100, the phase adjusting unit 111, the frequency divider 112, and the phase comparison unit 113 are identical to those shown in Fig. 3. According to the present invention, a counter 114 is provided between the phase comparison unit 113 and the phase adjusting unit 111, and the counter 114 cooperates with a protection stage number register 116 (see REG1 in Fig. 2) which is also connected, via a bus 118, to the processor 20. The carry output CR from the counter 114 is formed, via a differentiator 115, as a phase adjusting pulse P ad and is applied to the phase adjusting unit 111. The protection stage number can be varied by a combination of the counter 114 and the protection stage number register 116. Further, an initial value K to be set in the register 116, i.e., the protection stage number, is given in real time from the processor 20 via the bus 118. Before an acquisition of synchronism, the processor 20 specifies, for example, 3 , as the protection stage number, and thus a rapid phase synchronization is realized. After an acquisition of synchronism, the processor 20 specifies, for example, , as the protection stage number, and thus a stable phase synchronization, without jitter, is obtained. In both of the above cases, the number is specified by the processor 20, and accordingly, the specification is completed at a very high speed. Figure 5 shows a specific example of a part of Fig. 4. The phase comparison unit 113 is formed by a D flip-flop (FF1), and detects a lag or lead in phase of the internal clock CK i with respect to the external clock CK e . The lag or lead phase information ±ϑ is momentarily latched by a second flip-flop 117 (FF2) and then output to the phase adjusting unit 111. Also, the lag or lead phase information is sent to the Up/Down counter 114, and received at the U/D input thereof. In the counter 114, when the phase is lagging ("0"), the U p input is activated, and when the phase is leading ("1"), the Down input is activated. The initial value K to be preset in the U/D counter 114 is supplied, according to the present invention, from the protection stage register 116, where the value K is specified by the processor 20 via the bus 118. Note that the processor 20 comprises a RAM, ROM, ALU and so on (illustrated later), and carries out an overall control of the terminating equipment NT (Fig. 3) other than the aforesaid specification of the initial value K. If the U/D counter 114 overflows or underflows, the carry output CR is produced therefrom. Assuming that the protection stage number is set at , the carry output CR is sent when the phase lag has occurred 10 times continuously, or when the phase lead has occurred 10 times continuously. The carry output CR is passed through the differentiator 115 and shaped into a narrow pulse, which becomes the phase adjusting pulse P ad applied to the phase adjusting unit 111. Figure 6 is a timing chart indicating status at each major portion in Fig. 5, and specifically indicates the status in which the internal clock CK i is changed from a lag in phase to a lead in phase with respect to the external clock CK e . Assuming that it is a power-ON time or an input signal is out of synchronism, the processor 20 specifies, for example, 3 , as the protection stage number, to realize a rapid acquisition of synchronism, but after an acquisition of synchronism specifies, for example, , as the protection stage number. Accordingly, the carry output CR is produced every time the count value of the U/D counter 114 rises to 3 and the adjusting pulse P ad is output. When a lagging phase is made a leading phase, the carry output CR is produced every time the count value of the U/P counter 14 descends to 3 and the adjusting pulse P ad is output. The count value is reset (RST) by the pulse P ad . Figure 7 shows a detailed example of a U/D counter, and particularly, the output portion of the carry output CR is illustrated in detail. The count value of the U/D counter 114, consisting of, for example, 4 bits, is compared with the protection stage number, such as 3 or , stored in the protection stage number register 116. The comparison is obtained by the use of exclusive OR (EOR) gates 121 and 122. The EOR gate 121 is used to compare a limit value of the up side, and the EOR gate 122 is used to compare a limit value of the down side, for example, and , respectively. An inverter 123 is provided to create, according to the example, . If a coincidence is detected, i.e., according to the above-mentioned example, when the lag phase has continued 3 times or the lead phase has continued 3 times, "1" is output from an OR gate 24 and is momentarily latched, at a timing of the external clock CK e , at a flip-flop 119 (FF3) to produce the carry output CR. Figure 8 shows an example of a phase adjusting unit. In the unit, an inverted master clock MCK i is generated which is shifted in phase by π relative to the master clock MCK i , and AND gates 133 and 134 are provided to receive these clocks MCK i and MCK i at the inputs thereof. The AND gates 131 and 132 are selectively opened only when the adjusting pulse P ad exists. The gate to be opened is determined by whether the phase is leading ("1") or lagging ("0"). Where the phase is not leading (+ϑ = "0") and the P ad does not exist, the output from the AND gate 131 becomes "0", so that the AND gate 133 is opened, and thus the MCK i passes through an OR gate 135 and the frequency divider 112 to produce the CK i . Namely, in general, the master clock MCK i is always supplied from the OR gate 135. Where the phase is leading (+ϑ = "1") and the P ad exists (P ad = "1"), the output of the AND gate 131 becomes "1", and therefore, the AND gate 133 is closed only during the existence of the P ad , whereby one pulse of the MCK i is removed to obtain the CK i which is lagging in phase. To be specific, during the phase lead, the master clock is masked (cancelled) by the pulse P ad having a pulse width slightly wider than the pulse width of the MCK i . The wider pulse P ad is shown by a broken line in Fig. 6. Where the phase is lagging (-ϑ = "0") and the adjusting pulse exists (P ad = "1"), the output of the AND gate 32 becomes "1" and the AND gate 134 is opened. Accordingly, one pulse of the MCK i is inserted between two adjacent pulses of the MCK i , so that the CK i leading in phase is obtained. To be specific, during the phase lag, the master clock is supplied with a pulse between two adjacent master clock pulses. Figure 9 is a flow chart of an operation of a processor. The process shown by this flow chart starts, in the case of a power-ON or where an input signal is out of synchronism. In this example, the protection stage number is set to a small value, for example, 3 , (refer to step a). This process makes a rapid acquisition of synchronism possible, by executing a control loop N times under the thus set number 3 (refer to step 6). Note, N is usually determined from experience. After the N times execution, an acquisition of synchronism will be completed at a very high probability, and therefore, the protection stage number is changed to a usual protection stage number, for example, , (refer to step c), and thus a stabilized internal clock CK i , i.e., jitterless clock, can be obtained. At this step, establishment of the acquisition of synchronism is expected, and this is confirmed at step d. If the result is "NO", the prior steps are repeated from the beginning, and if the result is "YES", a usual data processing is commenced (refer to step e). Bit length varying means 200 When serial received data, input from the transmission line L is processed by a processor and output to another transmission line, the above serial/parallel (S/P) converter mus:t be employed. For example, an LSI performing a bit processing for a transmission, and an LSI performing a bit processing for a line termination and the like, are equivalent to the S/P converter, per se. But there is a demand that the functions of such LSI's be increased, to cope with future ISDN requirements. Figure 10 shows an example of a prior art serial/parallel converter, wherein 211 is a converting unit forming a major part of the serial/parallel (S/P) converter. The converting unit 211 cooperates with the processor 20 to convert a serial input received data SD in into a parallel output data (PD out ) in a unit of a predetermined number of n bits (n is a positive integer). Note that the term processor is a generic term for a program read only memory (ROM) PRG-ROM storing instructions, a sequencer SEQ for sequentially accessing the PRG-ROM, a decoder (DEC) for decoding the instruction from the PRG-ROM, an arithmetic logic unit (ALU) operated by the decoded instruction, a transfer bus 118 performing an input/output operation of the data PD out , and so on. The SD out is serial transmitted data from a parallel/serial (P/S) converting unit. The S/P converter 30 of the prior art is provided with a latch pulse generating unit 214, which specifies a timing for converting the serial received data SD in into the parallel transmitted data PD out in a unit of a predetermined number of n bits. LP in the figure denotes the latch pulse. A clock CK having the same speed as that of the serial received data the SD in is input to the generating unit 214, and forms a Digital Phase-Locked Loop (DPLL). In this case, an interrupt is applied to the processor 20 in parallel with the output of the latch pulse LP. This latch pulse LP allows the above-mentioned conversion from SD in to PD out to be carried out with the highest priority. With respect to the interrupt, an interrupt clear must be returned to the latch pulse generating unit 214, and to this end, the processor 20 issues an interrupt clear every time the fetching of the converted parallel output data PD out is completed. The serial/parallel converter 30 of the prior art shown in Fig. 10 has two problems; first, the converter lacks flexibility. In the above ISDN, the converters are used in a variety of terminal units refer to TE in Figs. 1 and 10) having speeds of 16 kbps, 32 kbps, 64 kbps, etc., and thus the hardware structure of the latch pulse generating unit 214 must be modified for each terminal unit having a different speed, which causes difficulties when matching the unit with the ISDN. Second, pairs of an interrupt and an interrupt clear must be executed frequently, and therefore, the job currently being processed by the processor 20 must be set aside every time an interrupt occurs, and thus the efficiency of the processor is greatly reduced. The bit length varying means of the present invention is constructed as a latch circuit forming a serial/parallel converter which does not employ an interrupt conversion but can cope with serial received data of any speed. Figure 11 is a structural view showing the principle of the bit length varying means of the present invention. Note, members identical to those previously mentioned are represented by the same reference numerals or symbols. The bit length varying means, i.e., the serial/parallel converter 200 of the present invention, comprises a clock counter 222 (see COUNTER in Fig. 2) counting the clock CK i having a same speed as that of the serial received data SD in , a time register 221 (see REG2 in Fig. 2) receiving, from the processor 20, a time value of the clock corresponding to a number of n bits and storing the same therein, a comparator 23 (see COMPARATOR in Fig. 2) detecting a coincidence between the clock count value CC from the clock counter 22 and the time value T, and producing a coincidence flag F, and a flag register 24 (see FR in Fig. 2) for storing the coincidence flag F. The processor 20 can freely set a time value T in the time register 221. Namely, all numbers of bits of the serial received data SD in received for conversion to parallel output data PD out are set therein, and thus it is possible to cope with serial received data SD in of any speed, such as 16 kbps, 32 kbps, etc., without the need for a hardware change. The processor 20 not using the interrupt always detects whether the coincidence flag F is generated in the flag register 224, and every time the flag is detected, the processor 20 issues a conversion instruction CI to perform the conversion, i.e., SD in → PD out , at every n bits. The coincidence flag F is output every time the clock count value CC of the clock counter 222 coincides with the time value T set in the time register 221. Note that the clock CK i counted by the clock counter 222 is obtained by a frequency division of an inside master clock(refer to Fig. 4), in which the required frequency dividing ratio, i.e., information about the serial received data SD in speed to be input next from the received line, is sent to the processor 20 via a separate path, i.e., by using a DIP switch, or via the transmission line L, or by installing another line and sending it in the form of a signal on that line. This makes it possible to cope with serial received data SD in of any speed, without the need for hardware modification, and further, the processor 20 need not be used for complicated operations, i.e., the above "interrupt-interrupt reset", and thus the utilization efficiency of the processor 20 can be increased. Figure 12 shows a specific example of the bit length varying means of the present invention, in particular, Fig. 12 shows the serial/parallel converting unit 211 in more detail. The converting unit 211 comprises a shift register (SR) 231 and a latch circuit 232. The shift register 231 stores the serial received data SD in bit by bit, in synchronism with the clock CK i , from the bottom to the top in the related figure. When, for example, 8 bits are stored therein (4 bits or 6 bits also possible), the bits are transferred to the latch circuit 232 all at once. The timing for this transfer is specified by the conversion instruction CI from the processor 20. In Fig. 12, the parallel serial converter (P/S) 212, connected to the transmitting line, is also specifically illustrated. Note, the construction thereof is an inversion of the serial/parallel converter 211. In this case, the latch circuit is driven by an output instruction OI. Figure 13 is a timing chart depicting an operation of the bit length varying means. First, a reset pulse RST for the clock counter 222 is output from the processor 20, and thus the clock count value CC of the clock counter 222 is made zero. Then the count value CC is incremented at the same pace as that of each data bit D₁ , D₂ , D₃ --- of the serial received data SD in . Namely, the count value CC is increased, for example, as 0, 1, 2, 3, 4 ---. Assuming that the 8 bits data is being processed, a time value T (= 7) is set in the time register 221 (Fig. 12). This time value is equivalent to 8 bits at the current data transmission speed, and thus, every time the clock count value CC reaches 7, 15, 23 ---, the comparator 223 (Fig. 12) produces the coincidence flag F to execute the conversion instruction CI. Note, the comparator 223 produces the flag F every time the time value T reaches 7 + 8 (M - 1) (8 denotes 8 bits, M denotes the number of received data), and thus the S/P conversion can be executed without using the above interrupt but merely by supervising the coincidence flag F. The parallel output data PD out (D₁ , D₂ --- D₈ of Fig. 13) fetched by the processor 20 is subjected to a predetermined data processing under a reception processing program. The thus-processed data is momentarily stored in the memory (Fig. 2), and thereafter, a transmission processing program is applied thereto and, by an execution of the output instruction OI, output as serial transmitted data SD out (D₁′, D₂′ --- D₈′ of Fig. 13) to the transmitting line of the transmission line L. Figure 14 is a flow chart of an operation of the bit length varying means. Note, Fig. 14 is only an example thereof. In the flow chart, the step at which T + 1 T indicates that, in Fig. 13, after execution of the conversion instruction at CC = 7 of the clock counter 222, the output instruction OI must be executed one clock (7 + 1) later. Further, the step at which T + 7 T indicates that a next conversion instruction CI should be executed 7 clocks (8 + 7) after the time at which CC = 8 of the clock counter 222. Start timing control means 300 In the above-mentioned digital communication network, a test must be carried out to maintain the quality, and is conducted by, for example, a supervisory unit (see SV in Fig. 1). The test is conducted in various ways, and in the present invention a loopback test is used. In the loopback test, test data is returned, as shown in Fig. 1 by a dotted line, at a loopback point LB in the figure; the correctness of the thus returned data is checked while varying the location of the point LB; and a fault position found. In this case, however, the transmitted data, i.e., downstream data d, and the received data, i.e., upstream data u, exist in parallel, and accordingly, the processing by the processor 20 at the terminating equipment ET (also at the terminating equipment NT) becomes very complicated. Note, in general, the test is conducted mainly by the terminating equipment ET. Figure 15 is a timing chart of a flow of the transmitted and received data, wherein row (a) represents a normal time and row (b) represents a test time. At the normal time, the transmitted data (downstream data d) D d1 , D d2 --- output from the processor 20 and the input data (upstream data u) received thereby, are clearly separated in terms of the generation timings thereof, and therefore, the processing in the processor 20 is relatively simple. At the test time, however, the timing of the transmitted data D d1 (downstream data d) for the test overlaps the timing of the received data D u1 (upstream data) returned at the loopback point LB. This is because the data is delayed, at most, by a time equivalent to about one stage of a latch at the loopback point LB, and accordingly, the processing by the processor becomes very complicated. Figures 16A and 16B are flow charts of a prior art procedure for processing the transmitted-received data. The flow chart of Fig. 16A ends at "A", continues onto the "A" of Fig. 16B, reaches the "B" thereof, and in next cycle, starts from the "B" of Fig. 16A. In the figure, the term frame pulse denotes a pulse which indicates a head of each cycle constituted by each pair of downstream data and upstream data. A counter, i.e., timer counter, is used to determine a time of each cycle, and operation of the processor 20 is started by using the thus-determined time as a clock source. In an LSI for a transmission operation, preferably the operation is in synchronism with a clock of a received data, and accordingly, the above-mentioned timer counter is used to count the clock of the received data. The term Fr pattern denotes a frame pattern of the transmitted data (downstream) D d1 , D d2 ---, and the term fr pattern denotes a frame pattern of the received data (upstream) D u1 , D u2 ---. The term "Normal/Test" indicates a discrimination between a normal time and a test time, wherein if "NO" stands, a normal time is indicated and the steps for timing adjustment are bypassed. According to the prior art data receiving-transmitting processing, both the program for the normal time and the program for the test time are prepared in advance, and one of these programs is selected. Namely, two programs must be prepared for normal time use and test time use, and accordingly, a problem occurs in that a large number of steps are needed. Further, another problem arises in that, since two discrimination steps, i.e., "Normal/Test", are required, the operation becomes complicated. Furthermore, yet another problem is involved in that, since the processings for both the downstream and upstream data are conducted by a single program, the program becomes complicated. The start timing control means 300 of the present invention provides an MUX/DMUX system in which the number of discrimination steps at the normal time and test time can be reduced, a data transmission program can be made shorter, and further, a program can be used which is simply set up with an easily understood step arrangement. Figure 17 is a schematic view of a construction showing the principle of the start timing control means. Reference numeral 300 represents the start timing control means cooperating with the processor 20. The processor 20 carries out a transmission processing of parallel data and outputs the related serial transmitted data SD out (D d1 , D d2 --- of Fig. 15) via the transmitting line 313 d , and receives, via the receiving line 313 u , the serial received data SD in (D u1 , D u2 --- of Fig. 15) and converts that data into parallel data to carry out the reception processing. The above transmission processing is represented by TP in the figure, and the reception processing by RP. The transmission processing TP and the reception processing RP are executed by a program P d for the downstream data and a program P u for the upstream data, respectively. Also, these processings are executed by a timer counter 314 (see TIMER COUNTER in Fig. 2) which is synchronous with the clock of the serial received data SD in . In the MUX/DMUX system of the present invention, the transmission processing program P d for the downstream data and the reception processing program P u for the upstream data are prepared independently and separately. Under the program P d , the transmission processing TP is executed commonly at both the normal time (NOR: Normal) and the test time (TST: Test). Under the program P u for the upstream data, however, the reception processing RP is executed commonly at both the normal time NOR and the test time TST. The reception processing program and the transmission processing program are activated alternately, and the reception processing program is started at a predetermined elapse of time (ΔT) after the execution of the transmission processing program. Note, the reception processing at the test time TST is started before the reception processing at the normal time NOR, by a predetermined time Δt. The timer counter 314 is used for the processing of the Δt stored in a time register 315 (i.e., register REG3 in Fig. 2). Further, the programs P d and P u are executed alternately, where the P u is executed in response to the start of the P d . Accordingly, the P d and P u run independently and alternately under the control of the timer counter 314 with the register 315, and consequently, compared with the prior art, the processor 20 can be operated by a simpler and more easily understood program than that of the prior art. Also, it is possible to use the transmission program alone in the program P d . The step of discrimination between the test time TST and the normal time NOR will be explained later with reference to the relevant flow chart. Figure 18 shows an example of the start timing control means, wherein the processor 20 is illustrated in detail. As mentioned above, the converting unit (S/P) 211 converts the serial data into parallel data and the converting unit (P/S) 212 reverses that conversion. The transmission processing and the reception processing, such as a multiplex operation, demultiplex operation, scramble operation and so on, are applied to the parallel data on the bus 118 under the control of the ALU and by utilizing a random access memory RAM. The instructions for specifying the transmission processing and the reception processing are stored in a program-read only memory PRG-ROM, and the instructions are then sequentially read to an instruction decoder DEC for execution. According to the present invention, both the transmission processing program P d for the downstream data, which deals mainly with the output processing, and the reception processing program P u for the upstream data, which deals mainly with the input processing, are stored in advance in the memory PRG-ROM and selected by sequencers SEQ d and SEQ u for a program read through a selector SEL. The sequencer SEQ d is used for the transmitting line and the SEQ u is used for the receiving line. The ALU indicates that it is currently a transmitting (downstream d) time or receiving (upstream u) time, by using a flag d and a flag u. A digital phase-locked loop circuit DPLL, constructed as the phase adjusting means 100, is provided and the clock CK i produced therefrom is synchronized with the serial received data (SD in ). Figure 19 shows signal patterns at the normal time and at the test time, and correspond to a more detailed Fig. 15. The character Fr represents a frame pattern of the transmitted data consisting of, for example, 8 bits, and fr represents a frame pattern of the received data consisting of, for example, 8 bits, each of which is followed by an information signal consisting of, for example, 10 bytes. Figure 20 is an enlarged timing chart of the test time of Fig. 19 in relation to the timer counter and the time register. The timer counter 314 is incremented by, for example, 0, 1, 2 --- 249 every time a frame pulse occurs. The transmitted (downstream) data SD out is output when the count value of the timer counter 314 reaches 7 , ---, and the received (upstream) data SD in is input when the count value reaches 9 , ---. Note that the figure shows an example wherein the time difference (Δt in the time register 315 of Fig. 18) between the transmission timing and the reception timing is 2 . The preset value (Δt) at the test time TST is shorter than the preset value (Δt′) at the normal time NOR (refer to Δt and Δt′ (Δt < Δt′) in Fig. 19) and the latter case, after completion of the transmission of the transmitted data, the reception processing is applied to the received data. Figure 21 is a flow chart of an example of the transmission processing program, and Fig. 22 is a flow chart of an example of the reception processing program. When compared with the prior art flow charts of Figs. 16A and 16B, it is apparent that the number of steps for discriminating the normal time and the test time is reduced by one, that only one output processing is carried out regardless of whether the time is the normal time or the test time, and that only one input processing is carried out regardless of whether the time is the normal time or the test time. Further, in the prior art, the programs are mixed together to form one program, as shown in Figs. 16A and 16B, and thus become complicated, but in the present invention, two separate programs, as shown in Figs. 21 and 22, are used and these two programs have no connection with each other, which makes the program simple. The only connection between the two programs is that one lies between the step "Set P u start flag" (Fig. 21) and the step ''Start flag" (Fig. 22). Namely, the only connection determined is that when the P d is to be started, in order to start the P u thereby. In Figs. 21 and 22, n denotes the count value of the timer counter 314, and the step wherein "counter = 249" denotes a time required for completing a pair of the transmission and the reception processings in one cycle. Further the step wherein "Set n = 7" denotes that, in Fig. 20, the time register 315 is preset with the term required for outputting the frame pattern Fr of the first transmitted (downstream) data SD out , and the step wherein "n = n + 8" denotes that n + 8 is set as the count value in the register 315, i.e., the first data (8 bits) of the SD out (Fig. 20) is output. Note, the counter 314 is operated as a down counter, and if 8 is preset in the register 315, the count value is decremented by, for example, 8, 7, 6 ---, and finally, a carry is output when reaching 1 to stop the related processing. In Fig. 22, the step "n = 9" at the test time denotes that the first input (fr pattern) of the received (upstream) data SD in continues up to the count value 9 , and thereafter, the value changes to, for example, 9, 17 ---. The step "n = 125" (normal time), however, denotes a duration time of the series of received (upstream) line data D u , and thereafter, "n + 8" is set n the register 315, to carry out the input operation in units of each byte, which forms, in total, an 11 times loop. During the processing of the transmission (downstream) (Fig. 21), a 10 times loop is formed, and the difference of 1 time therebetween is created because the input processing is counted as one under the reception processing program. In Fig. 22, the step "Frame synchronization" is required because the clock is extracted, via the phase adjusting means 100, from the serial received data, and therefore, a point identifying a time as zero must be defined. According to the above-mentioned technique, the transmission processing program P d for the downstream line and the reception processing program P u for the upstream line are executed alternately, and therefore, the processing must be executed at a speed which is twice that of the processing speed needed in the prior art, to realize an amount of processing equal to that of the prior art output processing and input processing. This means that the processor 20 must have a processing capability sufficient to cope with that requirement. As explained above in detail, according to the present invention, a programmable multiplexing/demultiplexing system is realized, which comprises a phase adjusting means, a bit length varying means, a start timing control means and a processor. Under the control of the processor, first the phase adjusting means can variably control the phase of the clock signal; second the bit length varying means can control the length of the received data by using the adjusted clock signal to freely cope with data of various speeds; and third, the start timing control means can variably determine the start timing of the transmission and reception processing programs by using the adjusted clock signal. Accordingly, the multiplexing/demultiplexing system is programmable, and therefore, is flexible when used with the ISDN.

Claims: A programmable multiplexing/demultiplexing system in which serial data received via a receiving line is converted into parallel data and latched by a latch circuit, the latched received data is read by a processor (20) and stored in a memory to apply an internal processing to the received data and the processed data is output, as serial data, to a transmission line, characterized in that the system includes therein, at least: a phase adjusting means (100) for variably controlling a phase of a clock signal by said processor in accordance with the received data; a bit length varying means (200) for variably controlling a length of the received data by said processor when latched with said clock signal adjusted in phase by said phase adjusting means; and a start timing control means (300) for varying a start timing of a processing for the received data by said processor, when the processing is to be started after a processing of a transmitted data. A system as set forth in claim 1, wherein said phase adjusting means comprises: a phase adjusting unit (111) carrying out a pulse insertion or a pulse removal, in pulse units, to or from a master clock; a frequency divider (112) which divides a frequency of the output from said phase adjusting unit (111) to produce an internal clock; a phase comparison unit (113) which receives said internal clock as a first input and an external clock as a second input with which the internal clock is synchronized and detects, in clock units, whether the internal clock is lagging or leading said external clock; a counter (114) to which an initial value K is preset for producing a carry output when either a phase lag or a phase lead occurs K times continuously; a protection stage number register (116) for storing said initial value K therein; and a differentiator (115) which converts said carry output into a pulse synchronized with said master clock, whereby said processor (20) outputs said initial value K to said protection stage number register (116) via a bus. A system as set forth in claim 2, wherein said counter is an up/down counter. A system as set forth in claim 2, wherein said phase adjusting unit (111) is adapted to first produce both said master clock and an inverted master clock shifted in phase by π relative to the master clock and then to selectively switch said two clocks to carry out a phase adjustment. A system as set forth in claim 2, wherein said processor (20) is adapted to set said protection stage number in said protection stage number register (116) such that the protection stage number is determined before an acquisition of synchronism, as a number smaller than a number determined after an acquisition of synchronism. A system as set forth in claim 1, wherein said latch circuit is formed as a serial/parallel converting unit (211) and said system contains, a clock counter (222) which counts a clock having a same speed as that of said serial input received data, a time register (221) which receives from said processor (20), a time value corresponding to n bits of said clock and stores said value therein, a comparator (223) which detects a coincidence between the count value of said clock counter (222) and said time value and produces a coincidence flag when a coincidence occurs, and a flag register (224) which stores said coincidence flag, whereby said processor (20) detects an occurrence of a generation of said coincidence flag and issues a conversion instruction to said serial/parallel converting unit (211). A system as set forth in claim 6, wherein a parallel/serial converting unit (211) is provided in the system and is adapted to latch said sending data momentarily and the parallel/serial converting unit (211) is adapted to be then activated by an output instruction, issued from said processor to transmit said sending data serially to said transmitting line therefrom. A system as set forth in claim 6, wherein said processor (20) is adapted to first issue said conversion instruction to be executed for said received data and then to issue said output instruction to be executed for said transmitted data. A system as set forth in claim 8, wherein said processor (20) issues said conversion instruction under a reception processing program and issues said output instruction under a transmission processing program. A system as set forth in claim 9, wherein said reception processing program and said transmission processing program are adapted to be activated alternately. A system as set forth in claim 9, wherein said reception processing program is adapted to be started after a predetermined elapse of time from an execution of said transmission processing program. A system as set forth in claim 6, wherein said system is adapted so that said parallel data is converted by said parallel/serial converting unit (211) into serial data and thereafter, said serial data is transmitted under said transmission processing program to said transmitting line (L) and after completion of a transmission of said transmitted data, said received data is received from said receiving line and converted into parallel data by said serial/parallel converting unit (211) and the reception processing program is applied thereto wherein both a timer counter (222) and a time register (221) are employed and both the timer counter and the time register are adapted to adjust a start timing of said reception processing program in accordance with said transmission processing-program, at a normal time, said parallel data is converted by said parallel/serial converting unit (211) into serial data and thereafter, said serial data is transmitted to the transmitting line (L) under said transmission processing program and after completion of the transmission of the transmitted data, the received data is received via said receiving line at said serial/parallel converting unit (211) and converted into parallel data and said reception processing program is applied thereto to perform a reception process, at a test time, said transmitting line (L) and said receiving line are connected through a loopback point and while test data is transmitted as serial data by said parallel/serial converting unit (211) to said transmitting line (L), said test data can be received via said receiving line by using said timer counter (222) and said time register (221) to which said processor (20) has set a preset value, said preset value being shorter than a preset value used at said normal time. A system as set forth in claim 12, wherein said timer counter (222) is adapted to be driven synchronously with said serial received data. A system as set forth in claim 12, wherein said reception processing program and said transmission processing program are adapted to be activated alternately. A system as set forth in claim 1, wherein said system is adapted so that said parallel data is converted into serial data and thereafter transmitted to said transmitting line (L) by said processor (20) and after completion of the transmission of said transmitted data, said received data is received from said receiving line and converted into parallel data and the reception processing program is applied thereto to perform a reception process by said processor (20) wherein both a timer counter (222) and a time register (221) are employed, both the timer counter (222) and the time register (221) being adapted to adjust a start timing of said reception processing program in accordance with said transmission processing program, at a normal time, said parallel data is converted into serial data and thereafter, said serial data is transmitted to the transmitting line (L) under said transmission processing program and after completion of the transmission of the transmitted data the received data is received via said receiving line and converted into parallel data and said reception processing program is applied thereto to perform the reception process, at a test time, said transmitting line (L) and said receiving line are connected through a loopback point and while transmitting test data as serial data to said transmitting line (L), said test data can be received via said receiving line by using said timer counter (221) and said time register (221) to which said processor (20) has set a preset value, said preset value being shorter than a preset value used at said normal time. A system as set forth in claim 15, wherein said transmission processing program and said reception processing program are adapted to be activated alternately.

Inventors: MURANO, KAZUO, SOEJIMA, TETSUO, WATANABE, TOSHIAKI
Applicants: FUJITSU LIMITED
Application year: 1988
Main classification: H04J3
IPC codes: H04J3, H04Q11, H04L7