DIGITAL DATA DETECTOR

Abstract: A digital modulation signal is sampled by an A/D converter (1) in a predetermined cycle. A phase interval P between a zero level crossing and the current sampling point using sampling data S i+1 at the current sampling point and sampling data S i at a sampling point which is located one point before the current sampling point. A phase P i+1 of the current sampling point is found using the phase interval P, a phase P i of the sampling point which is located one point before the current sampling point, a phase P i-1 of a sampling point which is located two points before the current sampling point and a phase P i-2 of a sampling point which is located three points before the current sampling point. A clock signal is detected using the phases P i+1 and P i . Digital data is detected using the phase interval P, the phase P i+1 and the sampling data S i at the sampling point which is located one point before the current sampling point.

Description: The present invention relates generally to digital data detectors, and more particularly, to digital data detectors for detecting digital data from a digital modulation signal in a digital data transmission system. Conventionally, various apparatuses for detecting digital data from a digital modulation signal have been proposed. As one example, a digital data detecting apparatus is disclosed in Japanese Patent Laying-Open Gazette No. 92410/1984 (EP-A-109 837). This apparatus detects digital data from a digital modulation signal in the following manner. The digital modulation signal is sampled at a frequency of m times (m > 1) a channel bit rate. It is assumed that the digital modulation signal is sampled at a frequency of two times a channel bit rate. Sampling data S i+1 at the current sampling point and sampling data S i at a sampling point which is located one point before the current sampling point are used to find a phase interval P between a point at which the digital modulation signal crosses a reference level and the current sampling point from the following equation. In this case phases of sampling points are represented by values of 0 to N-1 obtained by dividing a channel bit period into N equal divisions; where N/2 is a value of one-half of a channel bit interval. A predetermined value (N/2) is added to a phase P i of the sampling point which is located one point before the current sampling point, to obtain an estimated value of a phase of the current sampling point. In addition, the estimated value of the phase of the current sampling point is corrected from the following equation, so that a phase P i+1 of the current sampling point is calculated; P i+1 = {P - (P i + N/2)}· K + P i + N/2 (2) where K is a coefficient of 0 < K ≦ 1. On the other hand, when the digital modulation signal does not cross the reference level between the current sampling point and the sampling point which is located one point before the current sampling point, the phase P i+1 of the current sampling point is calculated from the following equation: P i+1 = P i + N/2 (3) A clock in synchronization with the digital modulation signal and digital data corresponding to the clock are detected in response to sampling data at each sampling point thus obtained and a phase of the sampling point. Meanwhile, the data detecting apparatus can cope with multichannel input by sampling channels at different timing and sequentially converting the channels into signals, to be inputted. According to the above described conventional data detecting apparatus, when the digital modulation signal does not cross the reference level, the phase of the current sampling point is evaluated from the equation (3), so that the phase interval between adjacent two sampling points always becomes a constant value N/2. Thus, if fluctuations in the frequency caused by wow, flutter or the like increase, a phase to be calculated cannot follow the fluctuations in the frequency, whereby data is erroneously detected. A digital data detector which operates in a similar manner to the above example is known from the present applicant's published European patent application EP-A-0,206,221. Meanwhile, Japanese Patent Laying-Open Gazette No. 222072/1986 (EP-A-196 034) filed by the assignee of the present application discloses a digital magnetic recording and reproducing apparatus in which clock extraction is determined by comparing phase information before and behind sampling data of a reproduced signal with each other and comparing magnitudes of the phase differences calculated from the sampling data with each other and the phase information is changed depending on the result of the determination. An object of the present invention is to provide a digital data detector in which data is little erroneously detected even if fluctuations in the frequency increase. In accordance with the invention, a digital data detector comprises: sampling data detecting means for sampling a digital modulation signal at a constant frequency, phase interval calculating means responsive to sampled data from said sampling data detecting means for calculating a phase interval (P) between a point at which said digital modulation signal crosses a reference level and the current sampling point, phase calculating means for calculating a phase (P i+1 ) of said current sampling point, clock detecting means responsive to the phases (P i+1 , P i ) of said current sampling point and a sampling point (the previous sampling point) located one point before said current sampling point, for detecting a clock signal in synchronization with said digital modulation signal, and data detecting means responsive to said phase interval, the phase of said current sampling point and said clock signal for detecting digital data from said digital modulation signal, characterised in that said phase calculating means determines said phase of the current sampling point: (i) in the case that said digital modulation signal crosses said reference level at a point between said current sampling point and said previous sampling point, according to the equation: P i+1 = {P - (P i + Pd)}·K + P i + Pd, (ii) in the case that said digital modulation signal does not cross said reference level at a point between said current sampling point and said previous sampling point, according to the equation: P i+1 = P i + Pd , where P i denotes a phase of the previous sampling point; Pd is a phase interval determined from the respective phases of sampling points located one point before and at least two points before said current sampling point; and K is a coefficient. In a preferred embodiment of the invention, the phase interval Pd is determined according to the equation: Pd = (P i - P i-2 )·L + N/2, where phases of sampling points are represented by values 0 to N-1 obtained by dividing a channel bit period into N equal divisions; P i-2 denotes a phase of a sampling point which is located three points before the current sampling point; and L is a coefficient. In the digital data detector according to the present invention, the phase of the current sampling point is calculated in response to the phase of a sampling point which is located one point before and the phase of a sampling point which is located at least two points before the current sampling point. Thus, even if the frequency of the digital modulation signal fluctuates greatly, for example, due to wow, flutter or the like, the digital data detector can cope with the fluctuations in the frequency, whereby data is little erroneously detected. The phase of the current sampling point is precisely calculated following the fluctuations in the frequency. Therefore, the clock signal in synchronization with the digital modulation signal is precisely detected. Consequently, the digital data is precisely detected from the digital modulation signal. The present invention will become more fully apparent from the following detailed description of preferred embodiments taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing a main portion of a digital data detector according to an embodiment of the present invention; Fig. 2 is a timing chart showing a signal of each portion according to the present embodiment; Figs. 3(a) to 3(g) are diagrams for explaining clock extraction determining conditions according to the present embodiment; Fig. 4 is a block diagram showing specific structure of clock and data detecting circuits; and Figs. 5A and 5B are diagrams for comparing a phase of a sampling point calculated according to the present embodiment with a phase of a sampling point calculated according to the conventional example, where Fig. 5A shows a case in which fluctuations in the frequency of a digital modulation signal are small and Fig. 5B shows a case in which fluctuations in the frequency of the digital modulation signal are large. Referring now to the drawings, an embodiment of the present invention will be described. As an example, description is made on a case in which digital data is detected from a digital modulation signal according to an NRZI type modulation scheme in the case of the minimum magnetization inversion interval (Tmin) = 0.8 T and the maximum magnetization inversion interval (Tmax) = 3.2 T. Fig. 1 is a block diagram showing a main portion of a digital data detector according to the present invention. In this portion, a digital modulation signal is sampled in a predetermined cycle, so that sampling data at the sampling point is detected and the position, i.e., a phase of the sampling point is calculated. In addition, Fig. 2 is a timing chart for explaining an operation of the digital data detector. In Fig. 1, a digital modulation signal S is inputted to an A/D converter 1. The A/D converter 1 samples the digital modulation signal S in synchronization with a clock signal f s , to convert the same into M-bit digital data. The frequency of the clock signal f s is m times a channel bit rate. It is assumed that the frequency of the clock signal f s is two times the channel bit rate. Furthermore, in this conversion, the polarities of plus (+) and minus (-) of the digital modulation signal are represented by an MSB (Most Significant Bit) of "0" and "1" using complement on, for example, two. An output of the A/D converter 1 is inputted to an M-bit parallel delay circuit 2, a zero data detecting circuit 4 and an absolute value circuit 5 as sampling data (referred to as the current data hereinafter) S i+1 at the current sampling point. An output of the M-bit parallel delay circuit 2 is inputted to an absolute value circuit 6 as sampling data (referred to as the preceding data hereinafter) S i at a sampling point which is located one point before the current sampling point. The zero data detecting circuit 4 outputs "1" when the current data S i+1 is "0" and the preceding data has negative polarity, i.e., the MSB is "1", which otherwise would output the MSB of the current data S i+1 . An output of the zero data detecting circuit 4 is applied to one input terminal of an exclusive OR gate (referred to as an Ex-OR gate hereinafter) 3. The MSB of the preceding data S i outputted from the M-bit parallel delay circuit 2 is applied to the other input terminal of the Ex-OR gate 3. The Ex-OR gate 3 outputs "1" when input signals applied to both the input terminals are different from each other while outputting "0" when the input signals are the same. Thus, when an output of the Ex-OR gate 3 is "1", the preceding data S i and the current data S i+1 are different in polarity, so that it is determined that the digital modulation signal S crosses a reference level (zero level) (referred to as zero-level crossing hereinafter). Contrary to this, when the output of the Ex-OR gate 3 is "0", the data S i and S i+1 are the same in polarity, so that it is determined that the digital modulation signal S does not cross the zero level. It is assumed that with the current data S i+1 being "0" (i.e., the sampling point being on the zero level), the current data S i+1 and the preceding data S i are the same in polarity when the preceding data S i has negative polarity while the current data S i+1 and the succeeding data are different in polarity when the succeeding data has positive polarity. In addition, it is assumed that with the current data S i+1 being "0", the current data S i+1 and the preceding data S i are the same in polarity when the preceding data S i has positive polarity while the current data S i+1 and the succeeding data are different in polarity when the succeeding data has negative polarity. On the other hand, the current data S i+1 and the preceding data S i are converted into absolute values |S i+1 | and |S i | by the absolute value circuits 5 and 6, respectively, to be inputted to an arithmetic circuit 7. The arithmetic circuit 7 calculates a phase interval P between a zero level crossing and the sampling point of the current data S i+1 from the following equation using the absolute value |S i+1 | of the current data and the absolute value |S i | of the preceding data: In this case phases of sampling points are represented by values of 0 to N-1 obtained from dividing a channel bit period into N equal divisions, where N/2 represents the position of the zero level crossing. A calculating method of the phase interval P using the equation (4) is employed in the digital magnetic recording and reproducing apparatus disclosed in the above described Japanese Patent Laying-Open Gazette No. 222072/1986. The calculated phase interval P is compared with an output (P i + Pd) of a phase loop (as described below) by a comparator 8, the result of comparison being outputted as {P - (P i + Pd)} . The output {P - (P i + Pd)} of the comparator 8 is corrected in numerical value by a coefficient K (0 < K ≦ 1) of a constant multiplier 9 corresponding to loop gain, to be outputted as (P - (P i + Pd)}·K. The output {P - (P i + Pd)}·K of the constant multiplier 9 is applied to one input terminal of a logical product gate (referred to as AND gate hereinafter) 10. The AND gate 10 has another input terminal receiving an output C of the above described Ex-OR gate 3. Consequently, only when the digital modulation signal S crosses the zero level so that the output C of the Ex-OR gate 3 becomes "1", the output {P - (P i + Pd)}·K of the constant multiplier 9 is outputted from the AND gate 10, to be applied to one input terminal of an adder 11. The adder 11 has another input terminal receiving an output (P i + Pd) of the phase loop. The result of addition by the adder 11 becomes a phase P i+1 of the current sampling point. When there is zero level crossing between the sampling point which is located one point before the current sampling point and the current sampling point, the phase P i+1 becomes as follows: P i+1 = {P - (P i + Pd)}·K + P i + Pd Contrary to this, when there is no zero level crossing, the phase P i+1 becomes as follows: P i+1 = P i + Pd The phase P i+1 is inputted to a J-bit parallel delay circuit 12. An output of the J-bit parallel delay circuit 12 is applied to one input terminal of an adder 14, one input terminal of an adder 18 and an I-bit parallel delay circuit 13 (generally I = J) as a phase P i of the sampling point which is located one point before the current sampling point. The number of delays of the I-bit parallel delay circuit 13 is two. An output of the I-bit parallel delay circuit 13 becomes a phase P i-2 of a sampling point which is located three points before the current sampling point. The output P i-2 of the I-bit parallel delay circuit 13 is inputted to the other input terminal of the comparator 14, to be compared with the output P i of the above described J-bit parallel delay circuit 12. An output of the comparator 14 becomes (P i -P i-2 ). The output (P i - P i-2 ) is inputted to a constant multiplier 15 having a coefficient L (0 < L ≦ 1) and corrected in numerical value, to be outputted as (P i - P i-2 )·L. The output (P i - P i-2 )·L of the constant multiplier 15 is applied to a data converter 16. The data converter 16 compares an input signal with a predetermined value Lim, to output a value A previously set when the following condition is satisfied while directly outputting the input signal when the following condition is not satisfied: (P i - P i-2 )·L ≧ Lim or (P i - P i-2 )·L ≦ -Lim The data converter 16 is provided for the following reasons. More specifically, when input data becomes invalid due to burst generation or the like, the phase calculated based on the input data also becomes invalid, so that the difference (P i - P i-2 ) between the two phases exceeds a range of a normal value. Since this affects the subsequent calculation of phases, the return to the normal value is delayed. When the value of (P i - P i-2 )·L is outside a predetermined range, the value is replaced with a value previously set. An output of the data detector 16 is applied to one input terminal of an adder 17. The adder 17 has another input terminal receiving a signal corresponding to N/2. The result Pd of addition by the adder 17 becomes as follows: Pd = (P i - P i-2 )·L + N/2 The output Pd of the adder 17 is applied to the other input terminal of the adder 18. Since the phase P i of the the sampling point which is located one point before the current sampling point is applied to one input terminal of the adder 18 as described above, (P i + Pd) is outputted from the adder 18. The output (P i + Pd) is applied to the other input terminal of the adder 11 as an output of the phase loop, i.e., an estimated value of the phase of the current sampling point. As described above, the output of the AND gate 10 is applied to one input terminal of the adder 11. Thus, when the output C of the Ex-OR gate 3 is "1'', the estimated value of the phase of the current sampling point is corrected based on the output of the AND gate 10. Consequently, the phase P i+1 of the current sampling point is outputted from the adder 11. Finally, the phase P i+1 of the current sampling point is given as follows: When there is zero level crossing, P i+1 = {P - (P i + Pd)}·K + P i + Pd (5) When there is no zero level crossing, P i+1 = P i + Pd (6) where Pd = (P i - P i-2 )·L + N/2 (7) P denotes a phase interval between a zero level crossing and the current sampling point, which is calculated from the equation (4). P i+1 denotes a phase of the current sampling point, P i denotes a phase of a sampling point which is located one point before the current sampling point, P i-2 denotes a phase of a sampling point which is located three points before the current sampling point, N/2 denotes a value showing half of the channel bit interval, and K and L denote coefficients. Description is now made on a method for detecting a clock in synchronization with the digital modulation signal S in response to the phase of each sampling point thus calculated. Fig. 3 is a diagram for explaining clock detection determining criteria according to the present embodiment. Figs. 3(a) to 3(d) show a case in which one π point (a point of N/2 from the zero point) of the digital modulation signal S exists between P i and P i+1 , and Figs. 3(e) to 3(g) show a case in which the above described π point does not exist between P i and P i+1 . In Fig. 3(a), the following condition is satisfied: P i > P i+1 , P i ≧ N/2, P i+1 ≧ N/2 In addition, in Fig. 3(b), the following condition is satisfied: P i > P i+1 , P i < N/2, P i+1 < N/2 Furthermore, in Figs. 3(c) and 3(d), the following condition is satisfied: P i < P i+1 , P i < N/2, P i+1 ≧ N/2 When the conditions are satisfied, it is determined that one π point exists between P i and P i+1 . Additionally, when sampling points continuously cross the zero level crossing, i.e., when the Ex-OR gate 3 continuously outputs "1", it is determined that the π point exists irrespective of comparison of P i with P i+1 . Under the above described clock detecting conditions, a clock in synchronization with the digital modulation signal is extracted by a circuit shown in Fig. 4 as described below. In addition, data corresponding to this clock is detected by the following condition. More specifically, it is assumed that the above described data has generally a sign of the sampling data S i while having a sign of the sampling data S i+1 when the output C of the Ex-OR gate 3 is "1" and the following condition is satisfied: P > P i+1 - N/2 Fig. 4 is a block diagram showing structure of circuits for detecting a clock and data based on the above described clock detecting criteria and the data determining condition. In Fig. 4, a phase P i of a sampling point which is located one point before the current sampling point, a phase P i+1 of the current sampling point and a phase interval P are applied to latch circuits 21, 22 and 23, respectively. The latch circuits 21, 22 and 23 hold P i , P i+1 and P at timing of a sampling frequency f s , to output the same. An output of the latch circuit 21 is applied to one input terminal of a comparator 24 and one input terminal of a comparator 25. An output of the latch circuit 22 is applied to the other input terminal of the comparator 25, one input terminal of a comparator 26 and one input terminal of a subtracter 27. In addition, a signal corresponding to N/2 is applied to the other input terminals of the comparator 24, the comparator 26 and the subtracter 27. The comparator 24 compares P i with N/2. The comparator 25 compares P i with P i+1 . The comparator 26 compares P i+1 with N/2. Outputs of the comparators 24, 25 and 26 and the output C of the Ex-OR gate 3 (see Fig. 1) are applied to a clock detecting circuit 28. The clock detecting circuit 28 outputs "1" when the above described clock detecting conditions are satisfied while outputting "0" when the clock detecting conditions are not satisfied. An output of the clock detecting circuit 28 is inputted to a data input terminal D of a flip-flop 29, to be acquired at timing of f s . An output of the flip-flop 29 is applied to one input terminal of an AND gate 30. The AND gate 30 has another input terminal receiving f s . When both the input signals are "1", the AND gate 30 outputs "1" at timing of f s , so that the output signal becomes a clock CK. On the other hand, an output corresponding to {P i+1 - (N/2)} is derived from the subtracter 27, the output being applied to one input terminal of a comparator 31. The comparator 31 has another input terminal receiving an output of the latch circuit 23. The comparator 31 outputs "1" when P > P i+1 - N/2, which otherwise would output "0". An output R of the comparator 31, a signal representing the sign of the preceding data S i , i.e., an MSB of S i and the output C of the Ex-OR gate 3 are inputted to a data detecting circuit 32. The data detecting circuit 32 samples data in response to the inputted signal based on the above described data determining condition. More specifically, the data detecting circuit 32 generally outputs the sign of the sampling data S i as reproduced data while outputting the sign of the sampling data S i+1 , i.e., a signal obtained by inverting S i as reproduced data when the output C of the Ex-OR gate 3 is "1" and the output R of the comparator 31 is "1" (when the relation P > P i+1 - N/2 is satisfied). An output of the data detecting circuit 32 is inputted to a data input terminal D of a flip-flop 33 and outputted from the flip-flop 33 at timing of the clock CK, so that reproduced data D₀ synchronized with the clock CK is detected. Figs. 5A and 5B are diagrams in which the phase calculated by the digital data detector according to the present embodiment is compared with the phase calculated by the conventional data detecting apparatus. Fig. 5A shows a case in which fluctuations in the frequency of the digital modulation signal are small, and Fig. 5B shows a case in which fluctuations in the frequency of the digital modulation signal are large. Assuming that K = 1/4, L = 1/2 and N/2 = 32, the phase of each sampling point is calculated. When the fluctuations in the frequency are small, the results of calculation of phases P₁ to P₇ of sampling points in the present invention are the same as those in the conventional example. However, when the fluctuations in the frequency become larger, the results of calculation of the phases P₁ to P₇ of the sampling points in the present invention are different from those in the conventional example. The phases of the sampling points take values 0 to N-1. Thus, when the phase and the phase interval become a value exceeding N-1 in the calculation process, N (= 64) is subtracted from the value. In Fig. 5B, a sampling point S4 is described by way of example. In this case, there is no point at which the digital modulation signal S and the reference level (zero level) crosses each other between sampling points S3 and S4. Thus, the equation (3) and the equations (6) and (7) are used in the conventional example and the present embodiment, respectively. In the conventional example, P₄ is found from the equation (3): P₄ = P₃ + N/2 Substitution of P₃ = 3 and N/2 = 32 gives P₄ = 35. In the present embodiment, P₄ is found from the equations (6) and (7): P₄ = P₃ + (P₃ - P₁)·L + N/2 Substitution of P₁ = 1, P₃ = 3, L = 1/2 and N/2 = 32 gives P₄ = 36. Then, a sampling point S7 is described by way of example. In this case, there is a point at which the digital modulation signal S and the zero level crosses each other between sampling points S6 and S7. Thus, P is found from the equation (4): Substitution of S₆ = 21 and S₇ = -28 gives P = 18. In the conventional example, P₇ is found from the equation (2): P₇ = {P - (P₆ + N/2)}·K + P₆ + N/2 Substitution of P = 18, P₆ = 35, N/2 = 32 and K = 1/4 gives P₇ = 6. However, P₆ + N/2 = 67, which exceeds N-1 (= 63). Thus, N (= 64) is subtracted from 67, so that 3 is obtained. P₇ is calculated assuming P₆ + N/2 = 3. In addition, the figures after the decimal point are neglected. In the present embodiment, Pd is first found from the equation (7): Pd = (P₆ - P₄)·L + N/2 Substitution of P₄ = 36, P₆ = 38, L = 1/2 and N/2 = 32 gives Pd = 33. Thus, P₇ is found from the equation (5): P₇ = {P - (P₆ + Pd)}·K + P₆ + Pd Substitution of P = 18, P₆ = 38, Pd = 33 and K = 1/4 gives P₇ = 9. However, P₆ + Pd = 71 , which exceeds 63. Thus, 64 is subtracted from 71, so that 7 is obtained. P₇ is calculated assuming P₆ + Pd = 7 . A reference point for obtaining the phase of each sampling point is a zero level crossing. Thus, the closer the phase P i+1 of the sampling point is to the phase interval P between the zero level crossing and the sampling point, the more satisfactorily data to be detected follows the fluctuations in the frequency of the digital modulation signal. The above described calculation results in P₇ = 6 in the conventional example while resulting in P₇ = 9 in the present embodiment. P₇ in the present embodiment is a value closer to the phase interval P = 18. Thus, the digital data is less erroneously detected. Although in the above described embodiment, description was made on the case of input of one channel, in the case of input of Y channels, the channels may be sampled at different timing and the number of delays of the parallel delay circuits 2 and 12 and the number of delays of the parallel delay circuit 13 may be made Y and 2Y, respectively. Although in the above described embodiment, description was made of the NRZI type modulation scheme in the case of Tmin = 0.8 T and Tmax = 3.2 T, it should be noted that the present invention is not limited to the same. For example, the present invention can be applied to the other modulation schemes such as NRZ type modulation scheme.

Claims: A digital data detector comprising: sampling data detecting means (1) for sampling a digital modulation signal (S) at a constant frequency (f s ), phase interval calculating means (2, 5, 6, 7) responsive to sampled data from said sampling data detecting means for calculating a phase interval P between a point at which said digital modulation signal crosses a reference level and the current sampling point, phase calculating means (3, 8 - 18) for calculating a phase P i+1 of said current sampling point, clock detecting means (21 - 26, 28 - 30; Figure 4) responsive to the phases P i+1 , P i of said current sampling point and a previous sampling point located one point before said current sampling point, for detecting a clock signal (CK) in synchronization with said digital modulation signal (S), and data detecting means (27, 31 - 33; Figure 4) responsive to said phase interval P, the phase P i+1 of said current sampling point and said clock signal (CK) for detecting digital data (D₀) from said digital modulation signal (S), characterised in that said phase calculating means determines said phase P i+1 of the current sampling point: (i) in the case that said digital modulation signal (S) crosses said reference level at a point between said current sampling point and said previous sampling point, according to the equation: P i+1 = {P - (P i + Pd)}·K + P i + Pd, (ii) in the case that said digital modulation signal (S) does not cross said reference level at a point between said current sampling point and said previous sampling point, according to the equation: P i+1 = P i + Pd, where P i denotes a phase of the previous sampling point; Pd is a phase interval determined from the respective phases (P i , P i-2 ) of sampling points located one point before and at least two points before said current sampling point; and K is a coefficient. A digital data detector according to claim 1, characterised in that the phase interval Pd is determined according to the equation: Pd = (P i - P i-2 )·L+ N/2 , where phases of sampling points are represented by values 0 to N-1 obtained by dividing a channel bit period into N equal divisions; P i-2 denotes a phase of a sampling point which is located three points before the current sampling point; and L is a coefficient. A digital data detector according to claim 1 or claim 2, wherein said phase interval calculating means calculates said phase interval P according to the equation: where S i+1 , denotes sampling data at said current sampling point and S i denotes sampling data at said previous sampling point. A digital data detector according to any one of claims 1 to 3, wherein said clock detecting means determines that one π point of said clock signal (CK) exists between the current sampling point and the previous sampling point when any of the following conditions is satisfied: (a) P i > P i+1 and P i ≧ N/2 and P i+1 ≧ N/2 (b) P i > P i+1 and P i ≦ N/2 and P i+1 < N/2 (c) P i < P i+1 and P i < N/2 and P i+1 ≧ N/2 A digital data detector according to any one of the preceding claims, wherein said data detecting means outputs a sign (C) of sampling data S i+1 at the current sampling point as reproduced data when the point at which said digital modulation signal crosses said reference level exists between the current sampling point and the previous sampling point and the relation P > P i+1 - N/2 is satisfied, but otherwise outputs a sign (C) of sampling data S i at the previous sampling point as reproduced data. A digital data detector according to claim 3, wherein said phase interval calculating means comprises: delay means (2) for finding said sampling data S i , absolute value means (6) for finding an absolute value |S i | of said sampling data S i , absolute value means (5) for finding an absolute value |S i+1 | of said sampling data S i+1 , and an arithmetic circuit (7) for finding said phase interval P using said absolute values |S i | and |S i+1 |. A digital data detector according to any one of the preceding claims, wherein said phase calculating means comprises: determining means (3) for determining whether or not the point at which said digital modulation signal crosses said reference level exists between the current sampling point and the previous sampling point, first delay mean (12) responsive to the phase P i+1 for outputting the phase P i , second delay means (13) responsive to the output of said first delay means (12) for outputting the phase P i-2 , first arithmetic means (14, 15, 17) responsive to the outputs of said first delay means (12) and said second delay means (13) for outputting said Pd, second arithmetic means (18) responsive to the outputs of said first delay means (12) and said first arithmetic means (17) for outputting (P i + Pd), third arithmetic means (8, 9) responsive to said phase interval P and the output of said second arithmetic means (18) for outputting {P - (Pi + Pd)}·K , logic means (10) responsive to the outputs of said determining means (3) and said third arithmetic means (9) for outputting said {P - (P i + Pd)}·K when said point at which the digital modulation signal crosses the reference level is detected, while outputting "0" when said point at which the digital modulation signal crosses the reference level is not detected, and adding means (11) responsive to the outputs of said logic means (10) and said second arithmetic means (18) for applying the result of addition thereof to said first delay means (12) as said phase P i+1 . A digital data detector according to claim 4, wherein said clock detecting means (Figure 4) comprises: first comparing means (24) for comparing said phase P i with said N/2, second comparing means (25) for comparing said phase P i with said phase P i+1 , third comparing means (26) for comparing said phase P i+1 with said N/2, clock determining means (28) responsive to the outputs of said first, second and third comparing means for outputting a first determination signal when any of said conditions (a), (b) and (c) is satisfied, but otherwise outputting a second determination signal, and clock outputting means (29, 30) responsive to a signal having said constant frequency (fs) for outputting the output (CK) of said clock determining means. A digital data detector according to claim 5, wherein said data detecting means (Figure 4) comprises: first comparing means (27) for comparing said phase P i+1 with said N/2, second comparing means (31) for comparing an output of said first comparing means (27) with said phase interval P, and detecting means (32) responsive to said sign C, the output (R) of said second comparing means (31) and said sampling data S i+1 of the current sampling point for outputting the reproduced data (D₀). A digital data detector according to claim 7, wherein said first arithmetic means comprises: fourth arithmetic means (15) for finding (Pi - Pi-2)·L using said phase P i from said first delay means (12), said phase P i-2 from said second delay means (13) and said coefficient L, fifth arithmetic means (16) for comparing said (P i - P i-2 )·L with a predetermined value Lim to output a previously set value when the condition (P i - P i-2 )·L ≧ Lim or (P i - P i-2 )·L ≦ -Lim is satisfied, while outputting said (P i - P i-2 )·L when said condition is not satisfied, and sixth arithmetic means (17) for adding an output of said fifth arithmetic means (16) to said N/2 to output the result of addition as said Pd. A digital data decoder according to any one of the preceding claims, wherein said sampling data detecting means comprises analog/digital converting means (1) for analog-digital converting said digital modulation signal (S) in synchronization with a clock having said constant frequency (f s ).

Inventors: SASADA, TAIZO, TAKEUCHI, HITOSHI
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1988
Main classification: G11B20
IPC codes: G11B20, H04L7