Circuit for controlling current switching in multiple inductive loads, with single current detector, particularly for windings of step motors

Abstract: The circuit controls current switching in multiple inductive loads (L1, L2, L3, L4) fed by means of respective switching switches (SW1, SW2, SW3, SW4) and by means of respective current adjustment switches (SWA, SWB), and comprises a single sense resistor (R) in series to said switching switches, and a single comparator circuit (C, FF) adapted to generate a logical signal (Q) when the voltage across the sense resistor exceeds a reference voltage (V ref ), which drives a plurality of AND gates (PA, PB) which control said adjustment switches and the second inputs whereof are driven by respective square-­ wave signals in opposite phase with a period equal to twice the switching period.

Description: The present invention relates to a circuit for controlling current switching in multiple inductive loads. particularly in windings of step motors. Circuits of this type are known from prior art references such as US-A-4 293 807 which use, besides a switching switch for each winding, also an adjustment switch for each winding or each group of windings, each adjustment switch being controlled by its own comparator circuit (PWM loop) driven by its own measurement or sense resistor for the current in that particular winding. In order to reduce the complexity of such switching control circuits, the use of a single adjustment switch, controlled by a single comparator circuit which is in turn driven by a single sense resistor, arranged in series to all the loads, is known from EP-A-187 224. This simplified circuit, though it avoids the duplication of the PWM control loop, has however the disadvantage that it does not allow the independent adjustment of the current in the two windings, since the overlap of the feed phases of two loads can give rise to mutual influences among the loads, with redistribution of the related currents. The aim of the present invention is therefore to provide a current switching control circuit in multiple inductive loads, particularly in windings of step motors, which uses a single sense resistor and a single comparator circuit, or PWM loop, though it maintains complete separation in the measurement of the currents in the loads. This aim, as well as other objects and advantages as will become apparent hereinafter, is achieved by the invention with a circuit for controlling current switching in multiple inductive loads as defined in the accompanying claims. A preferred embodiment of the invention is now described, given only by way of non-limitative example with reference to the accompanying drawings, wherein: figure 1 is a current switching control circuit for the windings of a unipolar step motor according to the prior art; figure 2 is a diagram illustrating switching signals used in the circuit of figure 1; figure 3 is a set of correlated waveform diagrams of various voltages present during the operation of the circuit of figure 1; figure 4 is a current switching control circuit for the windings of a unipolar step motor according to a preferred embodiment of the invention; and figure 5 is a set of correlated waveform diagrams of various signals present during the operation of the circuit of figure 4. In figure 1, L1 and L2 are the two parts of a first winding of a unipolar step motor or stepper (not shown), and L3 and L4 are the two parts of the second winding, SW1, SW2, SW3 and SW4 are switching switches arranged in series, having the purpose of activating the various steps of the motor in the sequence set by the mode of operation ("half step"/"full step"). The switches SW1, SW2, SW3, SW4 have respective freewheeling diodes D1, D2, D3 and D4 arranged in parallel, and have sense resistors RA and RB arranged in series and in pairs. The switches SW1, SW2, SW3 and SW4 are normally open, and are closed by means of "1" signals on respective control terminals M1, M2, M3 and M4 controlled by programmed circuits, not illustrated as they are beyond the scope of the invention. The windings L1, L2, L3 and L4 are fed in pairs by means of current adjustment switches SWA and SWB, also normally open, with freewheeling diodes D5 and D6 in parallel, leading to a supply voltage V s and activated by the outputs Q of control loops (PWM loops) to adjust the current in the windings. Said control loops comprise respective flip-flops FFA and FFB, synchronized with the set inputs by a clock signal CLK, and controlled on the reset inputs by the outputs of respective comparators CA and CB which compare the voltages across the resistors RA and RB with reference voltages V refA and V refB . Figure 2 illustrates, by way of example, the behaviours of the switching signals V1, V2, V3, V4 for the four switches SW1, SW2, SW3 and SW4 in the "full step" operating mode of the step motor. Considering, for the sake of simplicity, only the control of the current in the half-winding L1, and with reference to the diagrams of figure 3, suppose that the switch SW1 is closed and that the current in L1 is initially zero. A clock signal CLK forces the output Q of the flip-flop FFA to "1", and the switch SWA therefore also closes. Consequently the current in L1 starts to rise in a linear manner, with a slope V s /L, L being the inductance of half-winding L1. The voltage V sense across RA rises according to the same rule. When this voltage exceeds V refA , the comparator CA resets the flip-flop FFA, thus opening SWA. To ensure the continuity of the electromagnetic flux, the current then closes in the link constituted by SW1, L1, L2, D2, slowly decreasing, since (if the resistive drop on the switch SW1 is ignored) the current recirculates on the direct voltage of the diode D2. During this operation the voltage on the sense terminal is zero. The described cycle is repeated when a new clock signal occurs at the set input of the flip-flop. Both SWA and SW1 are switched off to bring the current to zero. This known control circuit allows to independently adjust the current in the two windings, but has the disadvantage of requiring two control loops each comprising a comparator and a flip-flop. An alternative circuital solution used in the prior art, which avoids the abovementioned circuit duplication, consists of using only one current adjustment switch and a single sense resistor in series to all the windings, with a single feedback loop to control the adjustment switch. On the other hand the disadvantage of this solution resides in that the single sense resistor, measuring all the currents simultaneously, does not allow to precisely separate the various steps, since there is a mutual influence, though small, among the various steps. With reference to figure 4, a preferred embodiment of a circuit for controlling the switching in the windings of a unipolar step motor is now described. The same reference numerals have been used in figure 4, where possible, for the parts identical to those of figure 1. The circuit according to the invention is similar to the known one described above regarding the switches SW1, SW2, SW3, SW4 with related diodes in parallel, and the switches SWA and SWB with related diodes. This circuit, however, comprises only one sense resistor R, and a single control loop, again comprising a flip-flop FF synchronized by a clock signal CLK and controlled by a comparator C which compares the voltage across the resistor R to a reference voltage V ref . The output signal Q of the flip-flop FF derives two AND gates, PA and PB, the outputs whereof control the switches SWA and SWB. To generate the second input signals at the gates PA and PB, the circuit comprises a first and a second flip-flop F1 and F2 of the toggle type, cascade connected. The flip-flop F1 is driven by the clock signal CLK, having twice the frequency with which the current in the motor is to be controlled, and with the reset input controlled by the output of the comparator C. The output Q1 of F1 controls the flip-flop F2, the outputs whereof Q2 and Q2 constitute the inputs for PA and PB. In general, the reference voltage V ref assumes two different values V ref1 and V ref2 during the operation of the circuit, in relation to the two windings L1, L2 and L3, L4 of the motor, with the same period as the signals Q2, Q2 for the control of the gates PA and PB. This can be provided, for example, by using two analogic gates connected to the input of the comparator and controlled by the same signals Q2, Q2 , not shown as they are obvious to the expert in the field. With this circuital arrangement, and with reference to the diagrams of figure 5, the first diagram illustrates the signal CLK with required timing. The signals Q2 and Q2 are then two square waves in opposite phase, with a period equal to twice that of CLK. The signal Q is constituted by pulses having a duration which depends on the switching threshold of the comparator C, but having the rising fronts occurring at the same frequency as CLK. If the reference voltages for the two loads are different, as illustrated in the last diagram, the voltage V sense across R, which starts every time from the same initial value with identical slope, causes the comparator C to trigger at different thresholds for the two loads, and this reflects in the different behaviour of the fluxes in the two windings. The gates PA and PB ensure that the two switches SWA and SWB never conduct simultaneously, and therefore the resistor R always measures only one of the currents. The currents in the two windings are thus defined in a fully independent manner. Naturally the control signals of the second inputs of the gates PA and PB may be provided in another manner, according to a given clock signal, while remaining within the scope of the inventive concept. Furthermore, though reference has always been made to the control of a step motor, this is only a preferred application of the invention, but the invention can be applied to different multiple inductive loads, e.g. to two bridge-connected or half-bridge connected inductors, the switching switches being also controlled, fully or partially, by said output signals of the AND gates. A preferred embodiment of the invention has been described, but is is understood that it is susceptible to equivalent modifications and variations on the part of the expert in the field, according to the given teachings. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included just for the sole purpose of increasing intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: Circuit for controlling current switching in multiple inductive loads (L1,L2,L3,L4) fed by means of respective switching switches (SW1,SW2,SW3,SW4) and by means of respective current adjustment switches (SWA,SWB), said circuit comprising a single sense resistor (R) in series to said switching switches (SW1,SW2,SW3,SW4) and a single comparator circuit (C, FF) adapted to generate a logical signal (Q) when the voltage across the sense resistor (R) exceeds a reference voltage (V ref ), characterized in that said circuit further comprises a plurality of AND gates (PA,PB) which control said current adjustment switches (SWA,SWB), said gates (PA,PB) having respective first inputs driven by said logical signal (Q) and respective second inputs driven by respective square-wave signals (Q2, Q2 ) in opposite phase with a period equal to twice the switching period. Control circuit according to one of claims 1-2, characterized in that it furthermore comprises means for changing said reference voltage (V ref ) in correlation with the transition of said square-wave signals (Q2, Q2 ). Control circuit according to claim 2. characterized in that it comprises further gate means driven by said square-wave signals (Q2, Q2 ), said further gate means controlling said means for changing said reference voltage (V ref ). Control circuit according to one or more of claims 1-3, characterized in that said square-wave signals (Q2, Q2 ) are generated by a circuit comprising two cascade coupled flip-flops (F1,F2), the first (F1) of the two flip-flops (F1,F2) being controlled by a clock signal (CLK) with a frequency equal to twice the control frequency of said current.

Inventors: PAPPALARDO SALVATORE, PIETROBON GIOVANNI, ROSSI DOMENICO, PAPPALARDO, SALVATORE, PIETROBON, GIOVANNI, ROSSI, DOMENICO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: H02P8
IPC codes: H02P8