A SO-CALLED SWITCHING VOLTAGE REGULATOR FOR AN INTERFACE CIRCUIT IN A TELEPHONE SUBSCRIBER LINE

Abstract: A so-called switching voltage regulator (1) for an interface circuit (16) in a telephone subscriber line, being of a type adapted to control the on/off states of an electronic switch (SW), connected to the interface circuit (16) and consisting of first (T1) and second (T2) transistors interconnected into a Darlington arrangement, comprises an ON-state sensor (14) connected input-wise to the collector (C1) of the first transistor (T1) and an OFF-state sensor (12) connected input-wise to the base (B1) of the first transistor (T1), and a pair of current extractor devices (11,10) respectively associated with the related bases (B1,B2) of the first (T1) and second (T2) transistors. Also provided are first (A1) and second (A2) current sources, each connected to a corresponding current amplifier (8,9) and a third hold current source (A3), the first (8) of such amplifiers powering both current extractor devices (11,10) and the second amplifier (9) and third current source (A3) being connected to the base (B2) of the second transistor (T2), as well as first (7) and second (5) dual input logic AND gates, the first gate (7) having an input (H) associated with the output of the OFF-state sensor (12) via a storage cell (6), and the second gate (5) having an input (Y) associated with the output of the ON-state sensor (14) via a further storage cell (4); each amplifier is respectively tied operatively with the outputs (U1,U2) of the first (7) and second (5) logic gates, each gate receiving on the other input (K,J) an appropriate enable signal from the regulator (1), whereas the hold current source (A3) is operatively tied directly with the enable signal of the second logic gate (5). Such a regulator (1) can minimize the current draw from the high tension power supply (-50 Volts) and make the on and off turning of the electronic switch (SW), including the pair of transistors (T1,T2) connected to the telephone subscriber line, faster.

Description: This invention relates to a switching voltage regulator for an interface circuit in a telephone subscriber line, which regulator is of a type controlling the on/off states of an electronic switch connected to said interface circuit and comprising first and second transistors, interconnected into a so-called Darlington arrangement. Voltage regulators of the above-noted type are employed in electronic interfacing circuits designed to drive voice transmissions over a telephone subscriber line. In particular, it is common practice for such regulators to voltage drive a telephone subscriber line interfacing and driving circuit, and to be connected both to a low (+/-5 V) level voltage supply and to a high level voltage supply (in the -50 V to -80 V range, depending on the subscriber line type to be driven). Such regulators require that the electric current drawn from said power supplies and particularly from the high voltage supply, be minimized, reducing as a result the amount of dissipated power. Conventional regulators of the type noted above usually comprise a circuit portion operative to regulate the high voltage supply to an interface circuit of a subscriber line by turning on and off an electronic switch connected to said interface circuit. For example, patent pubblication US-A-4,511,763 discloses a circuit for providing a controlled current to a subscriber loop. The circuit includes a DC-to-DC converter which switches periodically a DC source to cause a current to flow through the primary winding of a transformer and through a Darlington transistor pair until the converter is switched off. A rectifier in the secondary circuit supplies the subscriber loop circuit with a direct current which is dependent on the loop resistance. In order to reduce the power consumption a feedback circuit limits the maximum loop voltage by turning off the Darlington pair, thus immobilizing the DC-to-DC converter, when the loop resistance exceeds a predetermined value. As another example, a voltage regulator of the switching type and adapted to power an interface circuit referred to in the trade as a SLIC (Subscriber Line Interface Circuit) AMD, comprises a hysteresis comparator to the non-inverting input whereof a control signal is applied to turn on and off an electronic switch formed by a pair of npn transistors connected to each other into a so-called Darlington arrangement. This arrangement consists of interconnecting the collectors of the first and second transistors forming said pair, and of further connecting the emitter of the second transistor to the base of the first transistor. The base of the second transistor is connected to a current source and to a triad of circuit devices respectively adapted to extract electric charges, extract current, and inject electric charges. By way of explanation, a charge extracting device is the equivalent of a current extractor which is only activated for a given time period to produce extraction of a predetermined quantity of electric charges from the base of the second transistor. More specifically, as the comparator is input a signal exceeding a threshold value, it will output an enable signal to the charge extracting device which turns the second transistor off. The enable signal is also supplied to the current extracting device which, by drawing the current I supplied continuously from the cited current source connected to the base of the second transistor, will hold said second transistor in the off state. Further, the enable signal is also supplied to the charge injection device through an inverter, with consequent deactivation of that device. Turning the second transistor off automatically results in the first transistor connected thereto being turned off, and the switch comprised of said transistor pair is to be regarded as in its open state. Likewise, a low logic value voltage signal applied to the comparator input causes its output to be changed over and the charge and current extractor devices consequently deactivated, to the benefit of the charge injector device and current source which will turn on the transistor pair forming the switch connected to the subscriber line interface circuit. This prior approach, while substantially achieving its object, has the serious drawback that the aforesaid extractor and injector devices, the inverter and current source are all supplied the high level supply voltage (-50 V) and continuously draw a current I even when such draw is not strictly necessary. For example, no current would be required to hold the switch-forming transistors off, and during the off phase, the charge extractor device would be only necessary. Likewise, during the on phase, additionally to the current source, the charge injector device would be required, while the other devices could be left in their off state. Another serious drawback of the conventional circuit resides in its slow action. In fact, when using such charge and current extractor and injector devices, before the change over can take place, one is to wait for the transient on or off phase to be completed. The technical problem underlying this invention is to provide a switching voltage regulator which affords the ability to change over an electronic switch with a low current draw and irrespective of the transient on or off phase of the switch, thereby obviating the drawbacks noted above in connection with the background art. This problem is solved by a switching voltage regulator as indicated being characterized in that it comprises: an ON-state sensor connected to the collector of the first transistor; an OFF-state sensor connected to the base of the first transistor; a pair of current extractor devices respectively associated with the related bases of the first and second transistors; first and second current sources, being each connected to a corresponding current amplifier and a third hold current source, the first of said amplifiers being connected to both said extractor devices and the second amplifier and said hold current source being connected to the base of the second transistor; an enabling circuit responsive to regulator enables signals at its input for producing two binary signals in reciprocal inverted logic states at a first and second output thereof; first and second dual input logic AND gates, the first gate having a first input associated with the output of said OFF-state sensor via a first storage means and a second input connected to said second input of the enabling circuit and the second gate having a first input associated with the output of said ON-state sensor via a second storage means and a second input connected to said first output of the enabling circuit; each said amplifiers being respectively tied operatively to the outputs of the first and second logic gates and said hold current source being tied operatively directly to the first output of the enabling circuit. The characteristics and advantages of the voltage regulator according to this invention will be more clearly understood from the following detailed description of an embodiment thereof, to be taken by way of example and not of limitation in conjunction with the accompanying drawings. In the drawings: Figure 1 is a schematical view of a switching voltage regulator and its connections to the supply voltage sources and a telephone subscriber line interface circuit; Figure 2 shows a block diagram of the voltage regulator according to the invention; and Figure 3 shows a wiring diagram of the regulator of Figure 2. With reference to the drawing views, the numeral 1 designates, comprehensively and schematically, a switching voltage regulator. The regulator 1 comprises a circuit portion 2 adapted to control the on/off states of an electronic switch SW connected to a telephone subscriber line interface circuit 16. This interface circuit is shown in the drawing limited to a resistive load represented by a resistor R L . The supply voltage V B has a high value, in the exemplary embodiment being described that value being -50 Volts, and powers the regulator 1 itself, which is also associated with a supply pole pair, V C and V E , at a low value equal to +/-5 V, respectively. Between said switch SW and the load R L , there are conventional circuit components effective to limit the voltage peaks during the transient phases due to the switch SW being changed over. Such components comprise a capacitor CD in parallel with the load R L , an inductor L connected between one end of said capacitor CD and the output terminal OUT of the switch SW, and a diode D connected between the other end of the capacitor CD and the terminal OUT. The electronic switch SW consists of a first transistor T1 and second transistor T2, interconnected into a so-called Darlington arrangement, with the collectors C1 and C2 connected together, and the emitter E2 of the second transistor T2 connected to the base B1 of the first transistor T1. A resistor R is further connected between the base B1 and the emitter E1, which is also connected to the negative pole of the voltage source V B . The collectors C1 and C2 form the aforementioned output terminal OUT. With specific reference to the example of Figure 2, the regulator 1 includes a first elemental storage cell 3 consisting of a bistable (flip-flop) of a type referred to as SR on account of its having a first so-called set input, indicated at S1, and a second so-called reset input indicated at R1, and provided with respective outputs Q1 and Q 1 which will be referred to hereinafter as the non-inverting output and inverting output. The non-inverting output Q1 is connected to the set input S 2 of a second bistable SR cell 4 of a type adapted to change over on the down front of the input, and to an input J of a logic gate 5 of the AND type with two inputs, which has its other input Y connected to the non-inverting output Q₂ of the second flip-flop 4. The inverting output Q 1 of the first flip-flop 3 is connected to the set input S 3 of a third bistable SR cell 6, also of a type adapted to change over on the down front of the input, and to an input K of a second logic gate 7 of the AND type with two inputs, which has its other input H connected to the non-inverting output Q3 of said third flip-flop 6. First A1 and second A2 current sources are connected to a respective amplifier, 8 and 9, each adapted to increase the current signal value. Each amplifier is respectively connected to the output, U1 and U2, of said first 5 and second 7 logic AND gates. The current amplifier 8 is connected to a pair of current extractor devices, 10 and 11, respectively connected to the base B2 of the second transistor T2 of the switch SW and to the base B1 of the first transistor T1 in the same switch. The base B1 of that first transistor T1 is further connected to the input of an OFF-state sensor 12 connected to and powered by the amplifier 8, and having its output connected directly to the reset input R3 of the third flip-flop 6. The second current amplifier 9, associated with the source A2 is connected with its output to the base B2 of the second transistor T2 via a summing node 13. A further third hold current source A3 is connected and operatively tied to the non-inverting output Q1 of the first flip-flop 3 and outputs directly to said summing node 13 and, hence, the base B2. An ON-state sensor 14 is connected with its input to the collectors C1 and C2 of the transistors T1 and T2 forming the switch SW. The sensor 14 is connected to and powered by the second current amplifier 9 and has its output connected directly to the reset input R2 of the second flip-flop 4. With particular reference to the example of Figure 3, there is shown in more detail a schematical view of the regulator 1 according to the invention. The storage cell 3 comprises a conventional cross-coupled flip-flop including transistors T3 and T4 with whose respective bases B3 and B4 there are associated the set input S1 and reset input R1. This flip-flop includes a further pair of emitter-coupled transistors T5 and T6 having their respective bases B5 and B6 connected to the emitters of the transistors T3 and T4 to provide the inverting output Q1 and non-inverting output Q1 of the storage cell 3. The collectors of the transistors T3 and T4 are connected directly to the positive supply pole V C at a 5-Volt level, whereas the collectors of the transistors T5 and T6 are connected to the pole V C via respective diodes D2 and D1. Three bias current sources, collectively designated A, are conventionally associated with the negative supply pole -V E at a -5-Volt level. The non-inverting output Q1 of the cell 3 is connected directly to the base B9 of an npn transistor T9 having three emitters and whose collector is connected directly to the pole V C . The first, E91, of such emitters is connected via a resistor R6 to the emitter E20 of a pnp transistor T20 which constitutes said third hold current source A3 connected to said summing node 13. The collector C20 of that transistor T20 is connected directly to the base B2 of the transistor T2 incorporated to the switch SW. The remaining emitters, E92 and E93, of the transistor T9 are respectively connected via a resistor R5 and a resistor R4 to the respective emitters of a transistor T19 and transistor T18, both of the pnp type. The transistor T19 constitutes said second current source A2. The bases B18, B19 and B20 of the respective transistors are conventionally connected to one another and the negative pole V E , through a bias current source A. The inverting output Q 1 of the flip-flop 3 is connected directly to the base B8 of a pnp transistor T8 having a pair of emitters E81 and E82. The first emitter E81 is connected to the emitter of a pnp transistor T10 via a resistor R7. The transistor T10 constitutes said first current source A1. The second emitter E82 is in turn connected to the emitter of a pnp transistor T11 via a resistor R8. Said transistors, T10 and T11, have their bases connected to each other and to the negative pole V E via a bias current source A. The storage cells 4 and 6 are each comprised of a flip-flop with coupled emitters. More specifically, the cell 6 comprises the npn coupled emitter transistors T15 and T16 whose bases form the set input S3 and reset input R3, respectively, for the flip-flop 6. Connected to the input S 3 is the collector C11 of the transistor T11 via a resistor R10. The non-inverting output Q3 of the flip-flop 6 consists of the collector of transistor T15 and is connected to the base H of a pnp transistor T28 having the emitter K connected to the collector of the transistor T10 forming the source A1. Said transistor T28 forms, in combination with the npn transistors T29 and T30, and with the diode D7, a current amplifier serving the function of a logic AND gate 7, since a current appears on the output U1 of that amplifier only when the source A1 and the transistor T28, activated through its base H, are enabled simultaneously. The logic gate 7 has an output U1 connected directly to the emitters of a transistor pair, T14 and T17, forming the amplifier 8 and having their bases connected to the negative pole V E . The amplifier 8 is thus tied operatively to the output U1 of the logic gate 7. In a similar manner, the storage cell 4 comprises the transistors T12 and T13 with coupled emitters, whose bases respectively form the set input S 2 and reset input R2 for the flip-flop 4. The input S 2 is connected to the collector C18 of the transistor T18 via a resistor R9, and the non-inverting output Q2 of the flip-flop 4 is provided by the collector of the transistor T12 and connected to the base Y of a pnp transistor T31 having the emitter J connected to the collector of the transistor T19 which forms the current source A2. The transistor T31 constitutes, in combination with the npn transistors T32 and T33 and the diode D8, a current amplifier functioning as a logic gate 5 at the output U2 whereof a current will only appear with the source A2 and transistor T31 enabled at the same time. The output U2 of the logic gate 5 is connected to the emitter of a pnp transistor T21 forming the amplifier 9 connected to the summing node 13. Thus, the amplifier 9 is interlocked with, or tied operatively to, the output U2 of the logic gate 5. The ON-state sensor 14 comprises an npn transistor T22 having its base and emitter interconnected by means of a diode D3; this sensor 14 is powered from the amplifier 9 via the transistor T21 collector connection to the base of the transistor T22. A diode D4 further connects input-wise the collectors C1 and C2 of the switch SW to the emitter of the transistor T22, which has its collector C22 connected directly to the reset input R2 of the second flip-flop 4. A pair of serially connected diodes D5 and D6 further connect the base of the transistor T22 to the base B2 of the transistor T2 and constitute said summing node 13. The OFF-state sensor 12 is formed of a single npn transistor T23 having its emitter connected to the base B1 of the transistor T1 via a resistor R11. The collector C23 of the transistor T23 is connected directly to the reset input R3 of the third flip-flop 6. The sensor 12 is powered from the amplifier 8 through the connection of the related base to the collector C17 of the transistor T17 and through the resistor R17. The current extractor device 10 comprises the npn transistors T24 and T25 having their respective emitters and collectors connected together and to the base B2 of the transistor T2 by means of a lead 15. The base B25 of the transistor T25 is connected to the emitter of an npn transistor T26, the base of an npn transistor T27, and the emitter E25 of the transistor T25 itself via a resistor R12. The emitter E25 of the transistor T25 and the emitter E27 of the transistor T27 are further connected to the high voltage negative supply pole V B . The base of the transistor T26 is connected to the respective collectors of the transistors T24 and T27 as well as to the base D25 via the resistors R14 and R13. The base of the transistor T24 is connected between said resistors R13 and R14. The device 10 is powered from the amplifier 8 through the connection of the collectors C14 and C27 of the respective transistors included with the amplifier 8 and the device 10. The current extractor device 11 is structurally identical with the device 10, and a description thereof will be omitted. The device 11 is connected to the base B1 of the transistor T1 and is in turn powered from the amplifier 8 and the negative voltage pole V B . The remainder of the circuit components shown in Figure 3 constitute conventional connections between the devices described hereinabove and the various power sources; accordingly, they will not be discussed herein. The operation of the voltage regulator according to this invention will be next described with reference to a starting condition wherein the non-inverting output Q1 of the storage cell 3 is at a logic low, as is the output Q3 of the second storage cell 6. For convenience of illustration, reference will be made hereinafter to the logic levels appearing on the inputs and/or outputs of the inventive regulator components by the abbreviated terms "low" and "high". Thus, the output Q1 of the cell 3 being at a low, the transistor T9 will be cut off and, therefore, the current sources A2 and A3 deactivated. No current flows to the base B2 of the transistor T2, and the switch SW will be in the OFF state. Further, the output Q3 of the second cell 6 being also at a low, the output U1 of the AND gate 7 will be at a low and the amplifier 8 held in the OFF state. As a result, off are also the current extracting devices 10 and 11 and the OFF-state 12 and ON-state 14 sensors, the latter on account of the output U2 being at a low. In order to change over the switch SW, an enable signal is supplied to the input S1 of the flip-flop 3. The output Q1 of the flip-flop 3 goes high and constitutes the high input signal to the flip-flop 4 whose output Q2 is held at a high value since this flip-flop changes over on the down front of the signal. Therefore, the logic gate 5 will have both inputs at a high, and produce a high output U2 which enables the ON state of the amplifier 9. Furthermore, the hold source A3 is enabled directly by the transistor T9 as turned on by the high value of the output Q1 of the first flip-flop 3. Consequently, the transistor T2 will be on, and the switch SW changes from an OFF condition over to an ON condition wherein it is closed to power the load R L formed by the interface circuit. The ON-state sensor 14 will then output a signal to the input R2 of the second flip-flop 4; this signal will switch the output Q2 of the flip-flop 4 to a low value which also induces a low value on the output U2 of the logic gate 5, thus disabling the amplifier 9. As a result, power is removed from the ON-state sensor 14 and the transistors T1 and T2 will only be held on by the weak current supplied by the hold current source A3. Simultaneously therewith, the inverting output Q 1 of the flip-flop 3 holds the transistor T8, amplifier 8, and current extractor devices 10 and 11 in the OFF state. In order to turn off the switch SW, a high signal is then passed to the reset input R1 of the flip-flop 3. The output Q1 of that flip-flop will go low and switch off the transistor T9, source A3, and amplifier 9. However, the inverting output of the flip-flop 3 will be at a high and cause the transistor T8 to be turned on and the output Q3 to be held at a high value of the third flip-flop 6, which only changes over on the down front of the signal. Consequently, the amplifier 8 will be activated through the high output U1 of the logic gate 7, and the current supplied by the source A1 amplified and passed to the extractor devices 10 and 11 which pick up current from the bases B2 and B1, respectively, of the transistors T2 and T1, driving the switch SW off. The output current from the amplifier 8 also powers the OFF-state sensor 12, which will sense the open state of the switch SW and send a signal to the reset input R3 of the flip-flop 6 to switch the output Q3 of that flip-flop over to a low value. The output U1 of the gate 7 is now also changed over, and the amplifier 8 is disabled, thereby the extractor devices 10 and 11 and the sensor 12 are turned off. Thus, the great advantage is afforded that, once the switch SW is turned off, all the circuit devices which partook in the switch turning off are also switched off. The regulator of this invention also affords the ability to perform the on and off phases independetly of the switch state, and therefore, irrespective of whether the switch is still at a transient off or on phase. As an example, where an on phase is to be initiated while an off phase is being performed, it should be noted that, prior to the transistors T1 and T2 being turned fully off, the output Q3 of the third flip-flop 6 is still at a high because the sensor 12 is yet to activate the input R3 of that flip-flop. Now, by sending a high signal to the set input S1 of the flip-flop 3, the output Q1 will be changed over to a high and the inverting output Q 1 to a low, thereby the amplifier 8 and OFF-state sensor 12 are turned off. In this manner, the off phase is terminated in advance by merely initiating the on phase. The switching voltage regulator according to the invention has, therefore, the great advantage of permitting the opening and closing times of the switch connected to the interface circuit to be reduced as desired, and is specially useful wherever deep fluctuations in the output voltage are necessary. Furthermore, this regulator minimizes the current draw from the various supply sources by that the high on or off currents are cut off after the change-over has been completed. Another advantage is that the circuits making up this regulator comprise transistors which operate in a non-saturated state, which brings about increased rate for the whole circuit.

Claims: A switching voltage regulator (1) for an interface circuit (16) in a telephone subscriber line, which regulator (1) is of a type controlling the on/off states of an electronic switch (SW) connected to said interface circuit (16) and comprising first (T1) and second (T2) transistors interconnected into a so-called Darlington arrangement, and characterized in that it comprises: an ON-state sensor (14) connected to the collector (C1) of the first transistor (T1); an OFF-state sensor (12) connected to the base (B1) of the first transistor (T1); a pair of current extractor devices (11,10) respectively associated with the related bases (B1, B2) of the first (T1) and second (T2) transistors; first (A1) and second (A2) current sources, being each connected to a corresponding current amplifier (8,9) and a third, hold current source (A3), the first (8) of said amplifiers (8,9) being connected to both said extractor devices (11,10) and the second amplifier (9) and said hold current source (A3) being connected to the base (B2) of the second transistor (T2); an enabling circuit (3) responsive to regulator enables signals at its input for producing two binary signals in reciprocal inverted logic states at a first (Q1) and second (Q1) outputs thereof; first (7) and second (5) dual input logic AND gates, the first gate (7) having a first input (H) associated with the output of said OFF-state sensor (12) via a first storage means (6) and a second input (K) connected to said second input (Q1) of the enabling circuit (3) and the second gate (5) having a first input (Y) associated with the output of said ON-state sensor (14) via a second storage means (4) and a second input (J) connected to said first output (Q1) of the enabling circuit (3); each said amplifiers (8,9) being respectively tied operatively to the outputs (U1, U2) of the first (7) and second (5) logic gates and said hold current source (A3) being tied operatively directly to the first output (Q1) of the enabling circuit (3). A voltage regulator according to Claim 1, characterized in that said enabling circuit (3) comprises a first bistable storage cell (3) the corresponding set and reset inputs (S1, R1) whereof are the input of the enabling circuit (3) for receiving said enable signals in the form of ON and OFF switching signals; said first (4) and second (6) storage means comprise a second (4) and third (6) bistable storage cells, respectively, having corresponding set inputs (S2, S3) adapted to change over on the down front of the signal and being respectively connected to said first output (Q1) and second output ( Q 1) of said enabling circuit (3), the respective non-inverting outputs (Q2,Q3) of said second (4) and third (6) storage cells being connected to said first input (Y,H) of said second (5) and said first (7) logic gates, respectively; said second (4) and said third (6) storage cells having their corresponding reset inputs (R2,R3) respectively connected to the output of said ON-state sensor (14) and said OFF-state sensor (12). A voltage regulator according to Claim 1, characterized in that said OFF-state sensor (12) and said ON-state sensor (14) are each connected to and powered from the first (8) and second (9) of said amplifiers, respectively. A voltage regulator according to Claim 2, characterized in that the first output (Q1) of said first storage cell (3) is connected to the base (B9) of a transistor (T9) having multiple emitters (E91,E93) each respectively connected to and powering the set input (S2) of said second storage cell (4), the second input (J) of said second logic gate (5) and said hold current source (A3). A voltage regulator according to Claim 2, characterized in that the second output ( Q 1) of said first storage cell (3) is connected to the base (B8) of a transistor (T8) having a pair of emitters (E81, E82) respectively connected to power the set input (S3) of said third storage cell (6) and the second input (K) of said first logic gate (7).

Inventors: POLETTO, VANNI
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: H04M19
IPC codes: H04Q3, H04M19, H04Q1