INTEGRATED HIGH VOLTAGE GENERATING SYSTEM

Abstract: This invention relates to an integrated high voltage generating system provided with a charge pump for raising the input power supply voltage sequentially while transferring the electric charges of capacitors one by one, by serially connecting unit circuits composed of diode elements and capacitors, and supplying clock signals of mutually reverse phases to adjacent capacitors. Source and drain electrodes of MOS transistor are connected between the first power supply output terminal and second power supply output terminal, and the gate electrode of this MOS transistor is connected to the input end of any one of the unit circuit of the charge pump, wherein the voltage of the first power supply output terminal is stepped down depending on the voltage applied to the gate electrode of the MOS transistor, and is delivered to the second power supply output terminal. In this way, since the voltage is not stepped down by using dividing circuit, a potential between input power supply voltage and the first input power supply voltage can be obtained from the second power supply output terminal, without consuming unnecessary current and without causing the chip area to be increased.

Description: This invention relates to an integrated high voltage generating system, and more particularly to an integrated high voltage generating system having a charge pump. Various products are recently made portable and compact, and, as a result, the power voltage tends to be lower and the power source to be single. For example, the power voltage of portable radio or portable tape recorder is about 1.5 to 3.0 V. When a high power voltage is required for a product, a high voltage generating system is incorporated in the product or a semiconductor device used in the product. In case of incorporating an integrated high voltage generating system in a semiconductor device, a high voltage is generated by using a charge pump. Furthermore if a high voltage power source with different potentials is needed, a high voltage is first generated by the charge pump, and this high voltage is divided down, and the output is controlled by using this divided voltage, thereby creating another high voltage power different from the original high voltage. However, since the current supply capacity of the charge pump in the device is smaller for its area, the electric power consumed in this dividing circuit cannot be ignored. A conventional integrated high voltage generating system using a charge pump is described below. Fig. 7 shows a conventional example of an integrated high voltage generating system using a charge pump for delivering two different power voltages, and it comprisies a charge pump having four unit circuits connected in series being composed of diode-connected N-channel MOS transistors 1 to 5 and capacitors 6 to 9, a dividing circuit composed of two MOS transistors 17, 18, and a step-down control part composed of a MOS transistor 11 gated by the divided voltage of the dividing circuit. The operation of the conventional integrated high voltage generating system is explained by referring to Fig. 7. The electric charge coming in through the MOS transistor 1 from power source V cc connected to the power source input terminal is sequentially transferred among four stages of unit circuit controlled by clock signals CL, CLK of normal and reverse phases with an amplitude of V cc , and is sequentially boosted in this process. The boosted power supply voltage is delivered to a first power supply output terminal OUT 1. Part of this power supply voltage is delivered to a second power supply output terminal OUT 2 as another power supply voltage, by way of a step-down MOS transistor 11 which is gated by the divided output of the dividing circuit composed of two MOS transistors 17, 18. However, when a dividing circuit is used within the integrated high voltage generating system, the stability and response of this circuit and the current consumption are contradictory to each other, and the current consumption cannot be decreased extremely. The reason is as follows. Usually, at the first power supply output terminal OUT 1, a current of about several microamperes is flowing. On the other hand, when the MOS transistors 17, 18 are fabricated according to the design rule of about 3 microns, the gate width (W) and gate length (L) of the gate electrode are usually about 60 microns and 3.0 microns respectively and their ratio W/L is about 20. At this time, the circuit IL flowing in the MOS transistors 17, 18 is about 5 mA. That is, when such MOS transistors 17, 18 are used, the majority of the current of several milliamperes delivered from the charge pump is consumed in the dividing circuit, and the function as the integrated high voltage generating system is sacrificed. Hence, as one of the methods of decreasing the current consumption in the dividing circuit to, for example about 5 µA, it may be considered to design the gate width (W) at about 3 microns and the gate length (L) about 1500 microns, that is, the W/L of about 0.002. In turn, however, when the gate of the MOS transistors 17, 18 is fabricated in such a size, since the gate width (W) itself is only about 3 microns, if its dimension varies about ±0.3 micron, the effect of fluctuation is significant, and the stability of the device is impaired. Or when the gate is reduced to such size, the stray capacitance of the gate increases. As a result, the response of the circuit is worsened. Thus, in the conventional integrated high voltage generating system using a dividing circuit, it was extremely difficult to lower the current consumption without spoiling the stability and response of the circuit. Besides, as another method of decreasing the current consumption, it may be considered to raise the dividing resistance. For example, when dividing 20 V into 15 V, in a 3-micron process, by using a MOS transistor of about 3 mm², the current consumption becomes about 100 µA. To reduce this current consumption, more MOS transistors as the dividing resistances should be inserted between the power supply terminals of the dividing circuit (more than a dozen in the above example). Thus, the value of the current flowing in the dividing circuit may be reduced to several microamperes, and the current consumption can be decreased. In this case, however, it becomes sensitive to fluctuations of the threshold voltages of the MOS transistors. In this method, too, accordingly the circuit stability is poor. On the other hand, the charge pump power supply is extremely small in the supply electric power per unit area, as compared with the power supplied by merely dividing the external power source. Therefore, if the capacity of the charge pump is increased in order to compensate for the slight power consumption in the dividing circuit, the area occupied by the charge pump within the semiconductor device becomes extremely large, and the chip size itself becomes bigger. The present invention provides an integrated high voltage generating system comprising: a charge pump comprising a plurality of unit circuits each comprising a capacitor and a diode element, a first end of each capacitor being connected to the input end of the respective diode element, said unit circuits being sequentially connected and uniformly arranged according to the polarity of the diode elements, the output end of the diode element of a preceding unit circuit being connected to the input end of the diode element of a succeeding unit circuit; means for applying clock signals of mutually reverse phases to respective second ends of the capacitors of adjacent unit circuits, electric charge stored in the capacitor of each preceding unit circuit thereby being sequentially transferred to the capacitor of the respective succeeding unit circuit, thereby raising the voltage step by step; a power supply input terminal connected to the input end of the diode element of the unit circuit at the first stage of said charge pump; a first power supply output terminal connected to the output end of the diode element of the unit circuit at the final stage of said charge pump; a second power supply output terminal; and a first MOS transistor having source and drain electrodes connected between said first and second power supply output terminals, wherein the voltage of said first power supply output terminal is stepped down according to the voltage applied to the gate electrode of said first MOS transistor, and is delivered to said second power supply output terminal; characterised in that: the gate electrode of said first MOS transistor is connected to the input end of one of said unit circuits of said charge pump. It is hence an advantage of this invention that an integrated high voltage generating system is presented which is capable of obtaining a potential between the input power supply voltage and the output power supply voltage without consuming unnecessary current. It is a second advantage of this invention that an integrated high voltage generating system is presented which is capable of obtaining a potential between the input power supply potential and the output power supply potential without causing the chip area to be increased. In this constitution, without consuming the unnecessary current as experienced in the dividing circuit, and without causing the chip area to be increased, a potential between the input power supply potential and the first power supply output potential may be obtained from the second power supply output terminal. Other features and objects of the present invention will be apparent from the following description taken in connection with the accompanying drawings. Fig. 1 is a circuit diagram of one embodiment of an integrated high voltage generating system of this invention ; Fig. 2 is a conceptual diagram modelling the voltage changes at each stage of the charge pump in Fig. 1 ; Fig. 3 is a circuit diagram of a second embodiment of this invention ; Fig. 4 is a circuit diagram of a third emboiment of this invention ; Fig. 5 is a circuit diagram of a fourth embodiment of this invention; Fig. 6 is a circuit diagram of a fifth embodiment of this invention ; and Fig. 7 is a circuit diagram of a conventional integrated high voltage generating system. Referring now to the drawings, this invention is described in detail below relating to some of the embodiments. Fig. 1 is a circuit diagram showing one of the embodiments of this invention. In this diagram, the charge pump constructed by series connection of four stages of unit circuit composed of diode-connected N-channel MOS transistor 1 to 5 and capacitors 6 to 9 is same as in the prior art, but in this charge pump an intermediate potential is taken out from the intermediate node (the second stage in the case of the embodiment in Fig. 1) between the power supply input terminal and power supply output terminal. This intermediate potential causes to gate a MOS transistor 11 which couples a first power supply output terminal OUT 1 and a second power supply output terminal OUT 2. The first power supply voltage V OUT 1 is supplied into a voltage detector circuit (not shown), while the second power supply voltage V OUT 2 is supplied into a load (not shown). Capacitors 10, 12 are smoothing capacitors in order to lessen the ripple of the first and second power supply output voltage V OUT 1, V OUT 2. At each stage of the charge pump, clock signals CLK, CLK of mutually opposite phases are applied to adjacent pumps, and their amplitude is V cc , equal to that of the power supply voltage. In this constitution, the electric charge running in through the MOS transistor 1 by way of the power supply V cc connected to the power supply input terminal is sequentially transferred among four stage of the charge pump being controlled by the clock signals CLK, CLK of normal and reverse phases with the amplitude of V cc . The conceptual drawing of the voltage waveform of each node of the charge pump at this time is shown in Fig. 2, in which the output of the first power supply output terminal OUT 1 is V OUT , the sum of the currents flowing out is I, and the threshold voltage of MOS transistors is VT. The first stage of the charge pump is explained. For the sake of simplicity, the clock signal is suppose to have no transient time and phases of the clock signals CLK and CLK are accurately reverse and the capacity of the capacitors 6 to 8 for the charge pump is supposed to be sufficiently larger than the stray capacitance. When the clock signal CLK connected to the capacitor 6 is LOW, the potential of this capacitor 6 is V cc -VT. At phase 1, the clock signal CLK rises, and the capacitor potential at the first stage instantly goes up to V cc -VT+V cc to reach the peak voltage. At this moment, the clock signal CLK for the capacitor of the next stage (second stage) falls, so that the electric charge stored in the capacitor 6 of the first stage is transferred to the capacitor 7 of the next stage via the MOS transistor 2. As a result, the potential of the capacitor 6 changes by -dV. At phase 2, since the clock signal CLK of the capacitor 6 falls, the potential of the capacitor 6 changes by -V cc . Accordingly the potential decreased to the bottom voltage in a moment and then receiving electric charges from the preceding stage, the potential changes by +dV, and the node potential becomes V cc -VT. Here, assuming the frequency of the clock signals CLK and CLK to be f [Hz] and the capacitance of the capacitor in the charge pump to be C [F], in the stationary state, the electric charge C·dV transferred once from the capacitor 6 to 7 is equal to the sum of the current I/f flowing out per one clock time. Hence, dV = I/fC. Such cycle occurs in each charge pump. This operation may be also explained as follows. In the actual charge pump, ON resistance of the transistors 2 to 5 are inserted in series to the input side of the diode-connected MOS transistors 2 to 5. Accordingly, each stage of the charge pump possesses some time constant due to capacitors 6 to 9 and ON resistances. Therefore, when clock signals CLK, CLK are applied to each stage, the potential of each intermediate node momentarily reaches the peak voltage (or the bottom voltage) when the clock signal rises (or falls), and then changes to a stationary voltage of high level (or low level) according to said time constant. If rise and fall of clock signals CLK, CLK are sufficiently steep, hence, the peak voltage at the n-th stage, stationary voltage of high level, stationary voltage of low level and bottom voltage are respectively expressed in equations (1) to (4). Peak voltage at the n-th stage: VHPn = n·(V cc -V T )+V cc - (n - 1)·I·Rs (1) High level stationary voltage at the n-th stage: VHn = n·(V cc -V T )+V cc - n·I·Rs (2) Low level stationary voltage at the n-th stage: VLn = n·(V cc -V T ) - (n - 1)·I·Rs (3) Bottom voltage at the n-th stage: VLPn = n·(V cc -V T ) - n·I·Rs (4) where Rs is an equivalent resistance per stage, Rs = I/fC . Incidentally, equations (1) to (4) may be also expressed as in equations (5) to (8) respectively, in terms of the first power supply output voltage V OUT 1 and the power supply voltage V cc . In these equations, N denotes the total number of stages of the unit circuit in the charge pump. VHn = n·V OUT 1/N+(N-n)·(V cc -V T )/N + V T (5) VHPn = VHn + I·Rs (6) VLn = (n - 1)·V OUT 1/N + (N - n + 1)·(V cc -V T )/N (7) VLPn = VLn - I·Rs (8) From equation (7) it is known that the low level stationary potential of the potential of the intermediate node obtained from the n-th stage is equal to the potential of interior division between the voltage V OUT 1 of the first power supply voltage OUT 1 and the value lower by V T than the voltage V cc of the power supply input terminal into N-n+1; n=1, that is, a divided voltage. In the embodiment shown in Fig. 1, an intermediate potential is obtained from the intermediate node at the second stage, which corresponds to a case of n=2. In this circuit, from the second power supply output terminal OUT 2, voltage lower than the maximum voltage applied to the gate of the MOS transistor 11 by V T (threshold voltage of the MOS transistor 11) is taken out as the second power supply output voltage V OUT 2. That is, the second power supply voltage V OUT 2 is V OUT '=n·V OUT 2/N+(N-n)·(V cc -V T )/N+I·Rs (9) As clearly understood from this embodiment, by selecting the intermediate node (that is, in this case, setting n to any one of 1 to 4), the value of the second power supply voltage V OUT 2 can be changed. Furthermore, in this circuit, since the dividing circuit as used in the conventional example shown in Fig. 7 is not used, a potential between the input power supply voltage and the second power supply output voltage V OUT 2 may be obtained without consuming any unnecessary current. Fig. 3 shows a second embodiment of this invention, combining two pieces of the embodiments shown in Fig. 1, and the parts indicated by reference numbers 1' to 11' are identical in function with 1 to 11 in Fig. 1, respectively. At the power supply input terminal of each charge pump, power supply V cc is connected, and the power supply output terminals are commonly connected. Furthermore, clock signals CLK, CLK are applied to each stage of two charge pumps so that the phase may be reverse to each other. Accordingly, the output voltages are same as in the first embodiment in Fig. 1, but the phase of operation of each charge pump is reverse to each other, so that the operation is effected in such a manner as to reduce the ripple of the first and second power supply output voltage V OUT 1, V OUT 2 of the first and second power supply output terminals OUT 1, OUT 2. That is, in the case of one line of charge pump as in Fig. 1, pulsating currents just as when half-wave rectifying voltage is smoothed are caused, and the ripple content increases, but when two lines of charge pump are driven alternately in reverse phases as shown in Fig. 3, the pulsating currents become as if full-wave rectifying voltage were smoothed, so that the ripple content is decreased correspondingly. Fig. 4 shows a third embodiment of this invention, in which a diode-connected MOS transistor 13 and a smoothing capacitor 14 are inserted between the intermediate node and the step-down MOS transistor 11 in Fig. 1. By constructing the circuit in this way, the gate voltage of the step-down MOS transistor 11 is stabilized, and the second power supply output voltage V OUT 2 is also stabilized. The reason is as follows. As stated above, from the second power supply output terminal OUT 2, voltage lower than the maximum voltage applied to the gate of the MOS transistor 11 by V T (the threshold voltage of the MOS transistor 11) is taken out as the second power supply output voltage V OUT 2. Since the voltage applied to the gate of the MOS transistor 11 is a voltage from the intermediate node, it fluctuates periodically in synchronism with the clock signals, CLK, CLK . Therefore, for instance, if the gate voltage fluctuates between 11 V and 16 V and the threshold voltage V T of the MOS transistor 11 is 1 V, the second power supply output voltage V OUT 2 has a possibility to vary between 10 V and 15 V. Accordingly, by connecting the diode-connected MOS transistor 13 and smoothing capacitor 14 between the intermediate node and the MOS transistor 11, the voltage applied to the gate of the step-down MOS transistor 11 can be flattened by the rectifying and smoothing action of the MOS transistor 13 and smoothing capacitor 14. As a result, the second power supply output voltage V OUT 2 is lower than the flattened gate voltage by the portion of threshold voltage V T , and an extremely stabilized voltage is obtained. In this circuit, the second power supply output voltage V OUT 2 is expressed as follows: Incidentally, a similar effect will be obtained by using an ordinary diode instead of the diode-connected MOS transistor 13. In the above embodiments, meanwhile, the gate potential of the step-down MOS transistor 11 is determined by the peak voltage of the intermediate node, or, in other words, the top value of the transient response at the moment of rise (or fall) of clock signals CLK, CLK . This top value of transient response is extremely suffered by fluctuations of ON resistances of MOS transistors 2 to 5 and phase deviations between two clock signals CLK, CLK . Therefore, it is not wise to determine the gate potential of the step-down MOS transistor by the top value. Accordingly, Fig. 5 shows a fourth embodiment of this invention which makes design easier and more precise than the foregoing embodiments. In this embodiment, the intermediate potential is taken out from the intermediate node through a MOS transistor 16 which is gated by the node signal in the previous stage. In this case, in the newly added MOS transistor 16, the gate potential and the charge pump side potential of the source drain are driven in opposite phases, and since the gate side is connected to the node of the previous stage (i.e. to one-stage lower voltage point), the maximum value of the intermediate potential is a low level stationary value (not the top value) of the n-th stage. Therefore, designing becomes easier and more precise. At this time, the second power supply voltage V OUT 2 is As clear from equation (11), in this embodiment, the second power supply output voltage V OUT 2 is determined only by two elements, that is, the first power supply voltage V OUT 1 and V cc -V T . (In all foregoing embodiments, the element of current I was contained.) Fig. 6 shows a fifth embodiment, in which the charge pump 19 contains the elements 1 to 10, 13, 14 or 16 shown in Figs. 1, 3, 4 and 5. A voltage detection circuit 20 is composed of a transistor 21 for detection of voltage, a load transistor 22 and an inverter 23. The output of the voltage detection circuit 20 controls the clock signal source 24. The input power supply voltage V cc is boosted by the charge pump 19, and when the voltage V OUT 1 of the first power supply output terminal OUT 1 exceeds a predetermined value, the voltage detection transistor 21 is turned on, and the output of the inverter 23 becomes high level. In consequence, the frequency of the clock signal source 24 decrease, and the first power supply output voltage V OUT 1 is lowered. As a result, when the first power supply output voltage V OUT 1 becomes lower than the predetermined voltage, the voltage detection transistor 21 is turned off, and the output of the inverter 23 becomes low level. Hence the frequency of the clock signal source 24 increase, and the first power supply output voltage V OUT 1 goes up. By repeating such operation, the first power supply output voltage V OUT 1 is maintained at a predetermined voltage. When the first power supply output voltage V OUT 1 is maintained at a predetermined voltage, the second power supply output voltage V OUT 2 is also maintained at a voltage lower by V T (threshold voltage of the MOS transistor 11). Therefore, the second power supply current voltage applied to the load can be stabilized. Particularly, as the charge pump 19 in Fig. 6, when the charge pump shown in the embodiment in Fig. 5 is used, the second power supply output voltage V OUT 2 is determined only by the two elements of the first supply output voltage V OUT 1 and V cc -V T , and the element of current I is not contained, so that the stabilization of the second power supply output voltage V OUT 2 becomes extremely easy. In the foregoing embodiments, meanwhile, the unit circuits of the charge pump were composed of diode-connected MOS transistors, bu the same effects will be obtained if composed of ordinary diodes. Thus, by using the integrated high voltage generation system of this invention, since an intermediate potential between the output end potential and input end potential is taken out from the intermediate node of the charge pump, there is no extra current consumption due to dividing circuit, and the layout area is not caused to increased due to dividing circuit, so that excellent effects may be obtained.

Claims: An integrated high voltage generating system comprising: a charge pump comprising a plurality of unit circuits each comprising a capacitor (6, 7, 8, 9) and a diode element (2, 3, 4, 5), a first end of each capacitor (6, 7, 8, 9) being connected to the input end of the respective diode element (2, 3, 4, 5), said unit circuits being sequentially connected and uniformly arranged according to the polarity of the diode elements (2, 3, 4, 5), the output end of the diode element (2, 3, 4) of a preceding unit circuit being connected to the input end of the diode element (3, 4, 5) of a succeeding unit circuit; means for applying clock signals of mutually reverse phases to respective second ends of the capacitors (6, 7, 8, 9) of adjacent unit circuits, electric charge stored in the capacitor (6, 7, 8) of each preceding unit circuit thereby being sequentially transferred to the capacitor (7, 8, 9) of the respective succeeding unit circuit, thereby raising the voltage step by step; a power supply input terminal connected to the input end of the diode element (2) of the unit circuit at the first stage of said charge pump; a first power supply output terminal (OUT 1) connected to the output end of the diode element (5) of the unit circuit at the final stage of said charge pump; a second power supply output terminal (OUT 2); and a first MOS transistor (11) having source and drain electrodes connected between said first and second power supply output terminals, wherein the voltage of said first power supply output terminal (OUT 1) is stepped down according to the voltage applied to the gate electrode of said first MOS transistor (11), and is delivered to said second power supply output terminal (OUT 2); characterised in that: the gate electrode of said first MOS transistor (11) is connected to the input end of one of said unit circuits of said charge pump. An integrated high voltage generating system according to claim 1, further comprising: a diode element (13) connected between the input end of one of said unit circuits of said charge pump and the gate electrode of said first MOS transistor (11). An integrated high voltage generating system according to claim 1, further comprising: a second MOS transistor (16) having drain and source electrodes connected between the input end of one of said unit circuits of said charge pump and said gate electrode of said first MOS transistor (11) with the gate electrode connected to the input end of the unit circuit at the previous stage of said charge pump. An integrated high voltage generating system according to claim 2 or 3, further comprising: a smoothing capacitor (14) connected between the gate electrode of said first MOS transistor (11) and a reference potential point. An integrated high voltage generating system according to claim 1 comprising: a further charge pump also comprising a plurality of unit circuits each comprising a capacitor (6', 7', 8', 9') and a diode element (2', 3', 4', 5') a first end of each capacitor (6', 7', 8', 9') being connected to the input end of the respective diode element (2', 3', 4', 5'), said unit circuits being sequentially connected and uniformly arranged according to the polarity of the diode elements (2', 3', 4', 5'), the output end of the diode element (2', 3', 4') of a preceding unit circuit being connected to the input end of the diode element (3', 4', 5') of a succeeding unit circuit; and means for applying clock signals of mutually reverse phases to respective second ends of the capacitors (6', 7', 8', 9') of adjacent unit circuits in said further charge pump, electric charge stored in the capacitor (6', 7', 8') of each preceding unit circuit thereby being sequentially transferred to the capacitor (7', 8', 9') of the respective succeeding unit circuit, thereby raising the voltage step by step, and the clock signals supplied to unit circuits of said further charge pump being reverse in phase to those supplied to the corresponding unit circuits of the first mentioned charge pump; the power supply input terminal also being connected to the input end of said diode element (2') of the unit circuit at the first stage of said further charge pump; the first power supply output terminal (OUT 1) also being connected to the output end of said diode element (5') of the unit circuit at the final stage of said further charge pump; and comprising a further MOS transistor (11') having drain and source electrodes connected between said first and second power supply output terminals, with the gate electrode connected to the input end of one of the unit circuits of said further charge pump. An integrated high voltage generating system according to any one of claims 1 to 5 further comprising: a voltage detection circuit (20, 21, 22, 23) connected to said first power supply output terminal (OUT 1) arranged to detect if the voltage of said first power supply output terminal exceeds a predetermined value; and means for maintaining the voltage of said first power supply output terminal at said predetermined value.

Inventors: KOJIMA, MAKOTO, MISAKI, HIROZUMI, OKADA, YASUYUKI
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1988
Main classification: H02M3
IPC codes: H01L21, H02M3, H01L27