Phase-locked loops

Abstract: A digital phase-locked loop using a binary overflowing accumulator as a numerically controlled oscillator 1 has external compensation to eliminate frequency-dependent phase offset problems while not requiring any second-order filtering. Operation of NCO adder 1 initiates with a value set by centre frequency control 2 and under the latching action of latch 4 clocked by reference oscillator 5 produces a linearly stepped output. Detection of the most-significant bit values produces a square wave at output 6. Phase detector latch 9 is used for phase correction, while comparator 13 eliminates steady-state phase error.

Description: The present invention relates to digital phase-locked loop circuit arrangements. A phase-locked loop is often susceptible to steady-state phase errors due to centre frequency offset. In an attempt to overcome such errors, the phase-locked loop may have a second-order loop filter to provide close tracking of the output to the input. However a second-order filter can add considerable complexity to the hardware necessary, thereby making the equipment more expensive. US Patent Specification No. 4577163 discloses a digital phase-locked loop which uses, as a numerically controlled oscillator, a binary adder. The carry output of the adder is sampled and the result fed back to the phase comparator via a frequency divider. A counter is incremented or decremented according to the state of the comparator output and the contents of the counter provides a second input to the adder. EP-A-0177076 discloses a digital phase-lock loop circuit with a digital processor in which a reference phase signal is generated which is a measure of the frequency/phase difference between a clock signal and a stable reference signal. An object of the present invention is to reduce or eliminate the phase errors in first-order phase-locked loops without requiring a second-order filter. The present invention provides a digital phase-lock loop circuit arrangement comprising adding means having first and second inputs, latch means whose data input is connected to receive the output of the adding means, whose data output is connected to said first input and whose latch signal input is connected to the output of reference oscillator means so that the latch means and adding means together form accumulator means, sampling means for sampling in response to an input signal to the phase-lock loop circuit arrangement the output signal of the latch means, a coupling loop from the output of the sampling means to said second input to provide phase correction of the output signal of the latch means relative to the sampling instants of the sampling means, the dynamic behaviour of the most significant bit of the output of the latch means constituting in operation a standard output signal of the phase-lock loop circuit arrangement. The sampling instants may be determined by transitions in an input square wave. The output signals of the sampling means may be arithmetically transformed before application to said second input to provide negative feedback around the phase-locked loop. Preferably, the the phase-lock loop circuit includes comparison means for comparing the input and output data of the sampling means the output signal of the comparison means constituting in operation a phase-corrected output signal of the phase-lock loop circuit arrangement. Thus, as distinct from US Patent Specification 4577163, in the present invention the output of the adder is sampled at regular intervals by the input signal to produce a number representing the magnitude as well as the sense of the phase error, and this number or its derivative is applied to the second input of the adder to provide correction. In this way, the present invention can effect second order correction by comparing the sampled correction with the input to the sampling means. An integrated circuit may incorporate the features hereinabove defined. In order that the invention may more readily be understood, a description is now given, by way of example only, reference being made to the accompanying drawings, in which:- Figure 1 is a block schematic diagram of a circuit embodying the present invention; and Figure 2 is a representation of the waveforms in the circuit of Figure 1. The circuit shown in Figure 1 consists of a digital phase-locked loop using a binary overflowing accumulator as a numerically controlled oscillator. The circuit provides elimination of frequency-dependent phase offset problems without requiring any second-order filtering, this being achieved by incorporating external compensation. Thus, assuming that numerically controlled oscillator adder 1 initially contains a binary signal with all digits "0", the application of the central frequency control word, G, from the central frequency control unit 2, via frequency offset adder 3 with no signal at its other input, produces a sum output which is also G. The output, A, from NCO latch 4 remains zero until the next clock pulse from reference oscillator 5 latches the sum. At this stage, the latch output then changes to a value of G and is fed back to NCO adder 1 to produce a new output with value 2G. This is latched on the next clock pulse to produce a new latch output of value 2G. This again is fed back to adder 1 to be added to input word G. The latch output therefore increases linearly in steps of value G until the contents of the adder 1 exceed the maximum (i.e. all "1") whereupon adder 1 resets to a remainder value close to zero and the cycle begins again. The cycle duration is therefore determined by input word G; halfway through the cycle the most significant bit of the latch changes from "0" to "1", and at the end of the cycle from "1" to "0". By detecting the most-significant bit, a square wave is produced at standard output 6 having equal mark and space with a frequency determined by B. Multiplier 7 which is controlled by loop bandwidth control unit 8 operates to adjust the loop gain and bandwidth, this multiplication preferably being implemented as a shift. A phase detector latch 9 samples the output value of multiplier 7 in response to a transition in the input square wave after output by signal source 10 and passage through limiter 11. If the two signals are not in phase, the number latched is non-zero and the output of latch 9, D, indicates the magnitude and sign of the correction needed to correct the phase error. To achieve this correction, the value of D is changed by processing unit 12, to produce a signal E to generate negative feedback, and applying signal E to frequency offset adder 3. Frequency offset adder 3 allows the centre frequency of the operation of the phase locked loop to be adjusted at will. The circuit described above is a type of first order PLL. A well known property of such systems is that there is a steady state phase error which varies as a function of the frequency difference between the input signal (F) and the centre frequency of the PLL. In order to substantially eliminate this steady state phase error, additional phase correction is provided by comparator 13, which compares the input and the output of the phase detector latch 9 and accurately tracks the positive-going transitions of the input waveform. Supposing the input of latch 9 is increasing from zero to the maximum "N" and the input from source 10 occurs when the input is M, the latch output is then also M; but since the input continues to increase, the input is greater than the output and the phase-correction output 14 remains high until the input exceeds N and becomes zero. Since the latch still contains M, the input is now less than the output and the output goes low and remains low until the input exceeds M, or whatever new number has been latched. The phase-corrected output 14 has the same frequency as the standard output 6, but its transitions are synchronised to those of the reference square wave. The phase detector based on latching the output of the numerically controlled oscillator can resolve arbitrarily small phase angles, and can produce an output which is linearly proportional to the phase error over a range of 360°. Figure 2 provides comparisons of the standard and phase-compensated outputs for three input frequencies. As shown by the broken lines, transitions of the phase-corrected outputs track the input phase accurately, as distinct from the tracking achieved by the standard outputs. The present invention is particularly suited for use in FSK modulation and demodulation e.g. in systems for signalling on electrical mains wiring. The present invention is also applicable to digital television receivers e.g. for locking with zero phase error to the line frequency or colour sub carrier.

Claims: A digital phase-lock loop circuit arrangement comprising adding means (1) having first and second inputs, latch means (4) whose data input is connected to receive the output of the adding means (1), whose data output is connected to said first input and whose latch signal input is connected to the output of reference oscillator (5) means so that the latch means (4) and adding means (1) together form accumulator means, sampling means (9) for sampling in response to an input signal to the phase-lock loop circuit arrangement the output signal of the latch means (4), a coupling loop from the output of the sampling means (9) to said second input to provide phase correction of the output signal of the latch means (4) relative to the sampling instants of the sampling means (9), the dynamic behavior of the most significant bit of the output of the latch means (4) constituting in operation a standard output signal of the phase-lock loop circuit arrangement. An arrangement as claimed in Claim 1, wherein said sampling instants are determined by transitions in an input square wave. An arrangement as claimed in Claim 1 or Claim 2, including comparison means (13) for comparing the input and output data of the sampling means (9), the output signal of the comparison means constituting in operation a phase-corrected output signal of the phase-lock loop circuit arrangement.

Inventors: WALTHAM RICHARD MILLER, WALTHAM, RICHARD MILLER
Applicants: EMI PLC THORN, THORN EMI PLC
Application year: 1988
Main classification: H03L7
IPC codes: H03L7