PHASE-LOCKED LOOP CIRCUIT

Abstract: The object of the description is a phase-locked loop circuit comprising e.g. in the form of an integrated circuit (IC) in sequential connection a digital phase comparator, to the input of which are supplied a reference frequency (fref), a loop filter and a voltage-controlled oscillator, from which a feedback branch is fed to the second input of the phase comparator. The voltage (OV; OR) of the pulses obtained from the digital phase comparator is disposed so as to be adjustable, thus enabling to modify the limiting frequency and rate of the loop. The adjustment of the voltage of the pulses can be carried out e.g. by adjusting the supply voltage of the phase comparator or by means of an exterior diode or transistor cutter (Q2, Q3). The circuit is usable e.g. in radiotelephone applications, in which a rapid loop is connected during channel switch.

Description: Phase-locked loαo circuit The present inv ntion relates to a phase-locked loop ci cu:' com rising in sequential con ction a digit l phase comparator; to o e input of which a reference frequency is supplied, a loop filter and a voltage-controlled oscillator, from whicn a feedback nch is connected to the second in ut of t e phase co pa to . Such s phase-locked loop is presented as a block diagram ir fig 1. In the figure, the reference frequency fref is taken to the in u of the phase comp a or. The outpu of the phase comp rator is connected to the loop filter 2 and this output further the voltage—controlled oscil lator 3. The ou u of the oscillat 3 is fed back to the phase comparator 1 so as to provide a loop that is set according to the reference frequ ncy fref at a cer¬ tain at . I s well nown to u e such a phase—locked loop fo i stance n frequency synthesizers. When a phase-locked loop is used in ? frequency synthesis, the ol age—controlled oscillato ( \ ) CO ' o which s frequency modulated, contradictory requirements sπ e a to the loop rate. When a rapid set ime is desired w en switch.!..~ from one channel to another, the limiting frequency of the loop should b as high as possible. On he other h nd, for the loop not to accentuate nor to damp the modulation, its limiting fre¬ quency should be low, more precisely, the limiting frequency should be far lower than the lowest modulation frequency. < * '• * ■ ' low limiting frequency has the addition l ad ntage o educing the residual modulation and of increasing the damping of th n a ■ =•= reference freπi.iency. Th>= 115 patent specifications ■=*8 86° nd •£- 516 08?; for ns¬ tance, and the P p te applic tio δ5 1.5 disclose a sc <~ei er■ t.irrn (if the loop filter h ch n ji-ng the resist nce lue c ths nteor *** •to' *** ' st a e o the f lte e t er h *** " ** hv shor oircuifcincj. Correspondingly, the reta a ion is based o a. removal of the short-circuits or an addition of resistors. In the US patent specification 156 855 the loop is additionall accelerated by increasing the current feeding the capacitor of the integrator stage by means of a. current pump. Controlling the resistors by means of connectors, however, dis¬ turbs the operation of the loop. Thu.s, at the moment- of connecti a slow loop, a momentary twitch usually appears in the adjusting voltaqe obtained from -the VCO, which is inadmissible for instanc in radiotelephone applications. The same happens in the case of sudden change of the current charging the int-eαrator, Consequently, a frequency synthesis formed by a phase-locked loo has been impossible to use without disturbances in cases where, on the one hand. a. rapid setting time, and on the other hand, a linear modulation frequency response are required. In cases, whe re a modulated frequency synthesis formed by a phase-locked loop has been impl mented, these have been compromises between the setting time, the linearity of the modulation frequency response and the reference frequency damping. For example, in radiotelephone applications requiring a short- setting time and a linear modulation frequncy response. ha * been necessary to use a. so-called transfer oscilJLator system, in which a modulated fixed transfer oscillator frequency i mixed with the recevier injection frequency. On the other ha.nd. a transfer oscillator has the drawback of prodLtcing a. great numbe of mixing results, which are difficult to damp. Another drawback is a. complicated and expensive circuit. The object of the present invention is to reduce the abo e prob¬ lems and to provide a. circuit that enables to u.se a od ! -.lated frequency synthesis also when both a rapid setting time an a I limitino frequ ncy of he loop are required. The inv ntion is b sed on a solution IΠVQ! vmq a modificatio c e gain o a phase-locked loop by ad usting the oltage cf -,ne Dulses ob ai ed from the digital phase comparator, w ic e a le e us of a i l tin frequ ncy, .e. a rap d loop durin3 settings and a low limiting frequency fter the settings. Si ce the transfer oscillator system s not used, no detrimental mixi results are produced. When modifying the gain of the phase—locked loop in this m nner by changing the voltage of the pulses obtained f om the digital h se comparator, the change of the gain does not dis urb the operat on of the loop. Mor ove , the circuit is simple and is appropriate for a commonly used two-output digital phase comparator and an integr tor of the operatio amplifier type. T e circuit according to the invention allows a stepless adjustment when desired, and the adjustment functions flawlessly even w th small phase diffe renc s . The m^in characteristics of the invention appear from t e enclo sed claim 1 and its preferred embodiments from the independent * claims 2 to 10. Accordi g to the invention, ttie oltage of the pulses obtained from a digital phase comparator can consequently be changed in phase comparator or ou side the phase comp rator for instance b diode, transistor, FET or some other circuit limiting the vol¬ tage. The ulse voltage limitation can be p ovided for instance either at the output of the phase comparator or by means of the circuit set u m the loop filter as descri ed abo e. In the pha comparator, the adjustment is feasible e.g. by changing the SUDD voltage of the phase comparator itsel , or of its outpu staoe- Jt is sential that by changi g t e oulse vol age n the circui the gain of the rjha e—1 ock loop ca be nf1uence . and t us h li mα freαuencv and rate o he lαe- * *, monπ others, ( a .-■-. mo i f l e d . It s alsc essenti l t at when chancing the loop ga n x,-. th s manner by modifying the voltage of the Dulses obtained from the phase comparator, the change of the gam αoes not disturb the operation of the loop. In addition, the gam is steplessly adjus abl . Thus, it is possible to employ a high lim t ng frequence' i.e. a rapid loop during the setting and to reduce the limit frequency after the setting it ou disturbing the operation cf the loo . In this way, a rapid setting time and a linear modulation fre- cuencv response, a small residual modulation and a oreat d m mq of the reference frequency are achieved. The circuit of the invention for adjusting the gam of a phase- locked loop is applicable several phase—lock applications, such as frequencv—synthesis, modulator or demodulator applica¬ tion- ιe.g. AM. FM , PM ' . a tracking filter, the regeneration of a clock signal, etc. The adjustment of a phase—locked loop qain is usahle m various applications, e.g. adjustment cf the limiting frequency of a loop * acceleration and retardation of the locρ, lineariza ion o the modulation frequency response, increasing the reference frequency damping, or e.g. compensating the change of the loop gam as the divisor changes. The circu t has the addition l a van age of bei"c simpl arc ec nomical , of providing a controllable adjustment, a stepless a-t- Tjstment and that the gam ad i-ustme—t dees net disturb the on.__.~ tion of the loop. Hcrecver- the circuit s anolicable to d c tsl nhase cetectors v *3*•** " αus tvoes . for * - instance one— two—cutout onase detec c"- τ e ann11c 11o cf t e in ntion to a FM odula frequency— synthesiser is described in detail below as an example and wit ** " re erence to the enclosed dra ings, in which igure 1 rep esents a block diagram o the phase-locked loop descr b d bove, figure 2 represents a block di gram of a frequency synthesizer comprising a phase-locked loop, figure 3 represents an embodiment of the circuit according to the invention, figure - represents ulse fi u es relating to figure 3, figu e 5 repres nts frequency esponses relating to igu e 3. figure 6 re resents figures relating to claims and 8, figure 7 represents figures relating to claims 8 and 9. In the frequency synthesiser of figure 2 the reference frequenc is provided by a stable crystal oscillator 4- fTCXO) the frequen¬ cy of which is divided by the dividing element 2 < by number f? ) order to ge er te an a propri e phase comp ra ive frequ ncy. The phase compar tive frequency obtained is directed to the phas comparator 1, and the s gnal supplied by its output is fed into the loop filter 2. This loop fil er is a filter of the low pass type, in which the change components are filtered from the stgna of t e phase comparator and a direct—current voltaqe is obtained at the cont ol of the voltage-controlled oscillator 3 < MC0 ' . From he output of the voltage—controlled oscillator 3 the feed¬ back s taken through the orescaler 6 and the division element 7 to t e second input of the phase comparator 1. When the re¬ quency divider 7 of the feedback loop ( divisor N ) s made progra mable- a plurality of frequencies can be svnthezised b chancino th d visor N . Th presca I r 6 is used to reπuce the frequency o he voltaπe—control led oscil lator Ξ to th onerat on ranqe cf t progra mable divisor 7. the frequency range of which usually is rela iv iv narrow. The output cf the vol.taqe—controlled oscillat 3 simul aneously or-ns the f n , ι t ^ f t e =yn hetιser ou out. Since thjs connection ) = w ll known 3 n principle to = osrs 1* " - t 11 1 c! r 1 • • *-hc Λ + . i_ w i J 1 net He ripn-t — . hsr * n ri ι= • •- a ■ > - 1 here. Finished integrated circuits are available today, which comprise e.g. the dividing elements 5, the phase comparator 1 a the programmable divider 7, such a circuit being marked by the reference IC in the figure. Figure 3 represents a circuit according to the invention, in which the above integrated circuit IC is of the type MC145156 (manufacturer Motorola) . This is consequently a two-output phase comparator, the outputs which are marked by βTJ and in figure 3. These outputs are taken through the resistors R5 and R6 to the integrator, which in the case of the figure is carried out by means of the diffe¬ rential amplifier A. The natural oscillation frequency fn of the phase-locked loop i in which K ' is the gain of the phase comparator Kvco is 2τr « Δfvco (2) ΔVvco N is the total divisor <fout/fref) C is approx. C2=C3 in the figure 3 and R is approx. R7=R8 in the figure 3. By changing KJZ^ is obtained. In other words, the natural oscillation frequency the loop is directly proportional to the square root of the gai of the phase comparator. I the described case the oltage of the pulses obtained cm t outputs β-V and JZR of the phase comparator is influenced as fαl- 1ows . In- bo h outputs 'bsequ πt to the resisto PΞ> vs, P6 the emitters of the cutting transistors 03 vs. 02 are connected and the collectors of the transistors ere connected to the su p voltage Vdd ( 5V ) . In a normal situation, a low limiting frequen cy i.e. a slow loop is swi ched on, the capacitor Cl a ing then been ch ged th ough the resisto R to +5V nd the t a ¬ sistor Q2 and Q3 cut the 5V vol ge pulses of the outputs , V a into puls s of appro . 0.5V, s pres nted n point a of figu . At the moment of switching channel, as the divisor information fed into the programmable divider of the circuit in use is acti vated, the activating pulse ( ' TSEN ') fed into the terminal 13 of the miσroσircuit also provides a control through the resistor R to the base of the switch transistor PI. 01 then becomes moment rily conductive and the charge of the capacitor Cl is discharge through the resistor P3. Under these circumstances, the base voltage of the tr nsistors 02 and 0 decreases to ca . O an the eight of the pulses on the emitters of the transistors ise momentarily to 5V , as illustrated in point b of figure 4. Owing to the increased loop ga the limiting frequency and rate of the loop also increase. Sustaining the rapid loop. i.e. the high qam. depends on the time constant determined b the capaci tor Cl. In the described case the rapid loop remains switched on for c . 50 s, which is enough for the loop to settle. The natur l oscillation frequency of the described pnase-1oc L eri loop with the desc ibed circuit eing oa , 80 Hz wi h a rapid loc ffni), the natural oscillation frequency < f > of a slow loop ι : appro*, 0,5/5 v 80 Hz, i.e. ca « 25 Hz. ( til - vco M = 2300 Hz- The set of curves of figure 5 illust at s the response of the lo ked loop of a. sample circuit with a. rapid loop as well as with a slow one. From the response both the natural oscillation frequency fn and the limit frequency of the locked loop -3 d are readable. Moreover, the modulation frequency response of this loop has been drawn in figure 5 both with a. rapid and with slow loop. The modulation frequency response remains direct with in the desired range 300 Hz to 10 kHz.

Claims: 1 a i πs _ , A phase—locked loop circu t comprisin m sequential connec¬ tion a digital phase comparator ι U, tα one input of which a re erence frequencv ' ' fref ' ) is supplied, a loop filter *■' > and a voltage-controlled oscillator ( 3 J , from which a feedback branch is connected to the second input of the phase comparator, characterized in that the voltage of the pulses obtained from the digital phase comparator ( 1 ) is disposed so as to e adjus¬ table, hereby the limitin quency and ate of the phase-loc^ loon are modifiable, 2. ώ circuit according to claim 1, chβrπctørize in th t the voltage of the pulses obtained from the digital phase co p ¬ r tor f ' l ' i is disposed so as to be adjustable i the phase compar tor itself or at its output stage for e ample by regulating the su pl voltage, 3. A circuit according to claim 1, charscterized in that the voltage of the pulses obt ined rom the digital phase comp r tor f 1 is disposed so as to be ad j ustable y a diode or transis tor circuit set up outside the phase comparator, or by some othe r rciIit limi in t e pulse olt ge. 4. A circuit according to claim 2 and 3, characterized in that the voltage of the pulses obtained from the digital phase compa¬ rator is adjusted so as to use a larger limiting frequency of the loop during the setti g ' locking' and a smaller limiting f αυenc fter the se11Inα . 5= A circuit according to claim 2 and 3, charβcterized in that the oltage of the pulses obtained from the digital phase com□ar• tor ι l ) is ad u ted while the loop is locked so as to modi y- th= gam and the limiting frequency o the loo - 10 6. A. circuit according to claim 4 and 5, D aracterized in that the voltage of the pulses obtained from the digital phase compa¬ rator f ) is disposed to be adjustable by reoulatinq the supplv voltage of a circuit connected between the phase comparator output and the loop filter, which modifies the pulse voltage (amplifies or damps) , whereby the voltage of the pulses obtained from the circuit ^output and thus the ca.in and limiting frequen¬ cy of the loop are adjustable. 7, A circuit according to claim 4 and 5, characterized in t-hat the voltage of the pulses obtained from a two-output digital pha se compara.tor is disposed so as to be adjustable by a. transistor cutter CQ4. 05) set up outside the phase comparator, in which th emitters of the transistors are connected through the resistors CR11. R12) to the outputs <. R, V) QjC the phase comparator, and the collectors to the supply voltage ( . +Vdd > ' , thus enabling, by regulating the base voltage (Us), to regulate the pulse height- o the emitters of the transistors and thus the oain and limiting frequency of the loop. S. A circuit according to claim 4 and 5, characterized in tha the voltage of the pulses obtained from the two-output digital ohase compa.ra.tor is disposed so as to be ad 7U.sta.bl by a. diode cutter CDl j D2) set up outside the phase comparator, in which th cathodes of the diodes are connected through the resistors CR13, R14) to the outputs < R, V) of the phase comparator, thus enab¬ ling, by regulating the anode voltage of the diodes CUs) to regu late the pulse height on the cathodes or the diodes and thus the gain and the limiting frequency of the loop, 9. A circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from a one-output digital πhase comparator is isposed so as to b adjustable y a r n i tor cutter '06, 07 ) set up outside the phase comparator, in wir. th emitters of the transistors re connected through the rs — . _ (P15) to the ouput fPd) of the phase comparator and the collect o th WPN transistor < % Q6 > to the supply voltage < +Vdd ) and the collecto of the P P transistor < Q7 " > is earth connected, thus n ling, by regulating th b s voltage < Ua , Ub ) o th transi tors (06, 07) to aαjust the pulse height on the emitters of the transistors and thu the qain and the limiting frequency of th loαo, 10. A circuit according to claim 4 and 5, characterized in that the voltage αf the pulses obtained from' a one-output digital ph comparator is disposed soas to be adjustable by a diode cutter <D3, D4> set up outside the phase compar tor, in which the cath of one diode f ' D3 " > and the anode of the oth r diode ( ' D > are con nected through the resistor (P16> to the output αf the phase co p rator ( Pd i , thus ena ling, by regulatin the nod volt ge t U αf one diode ( " D ) and the ca hode voltage fUb ι o the oth dio fD4 ) to ad ust the pulse height obtained from the output of the circuit and thu the gain and the limiting f equency αf the loo

Inventors: NIEMIOE MIKA ERIK, NIEMIOE, MIKA, ERIK
Applicants: NOKIA MOBIRA OY, NOKIA-MOBIRA OY
Application year: 1988
Main classification: H03L7
IPC codes: H03L7