Layer structure of a memory cell for a dynamic random access memory device and method for producing the same

Abstract: A layer structure of a memory cell for a dynamic random access memory device includes a semiconductor substrate (11), an insulation film (13, 17) formed on the semiconductor substrate having a first window (18A, 27A) through which a surface of the semiconductor substrate (11) is partially exposed, a first conductive film (18 1A , 18 1B , 28 1A , 28 1B ) formed on the insulation film so as to surround the contact window (18A, 27A) and form a second window (18A, 28A) above the first window (18A, 27A); a second conductive film (25 1A , 25 1B , 35 1A , 35 1B ) formed so as to be in contact with the first conductive film (18 1A , 18 1B , 28 1A , 28 1B ), and the semiconductor substrate (11) through the first and second windows (18A, 27A, 28A) the first and second conductive films constructing a storage electrode of a memory cell capacitor; a dielectric film (19 1A , 19 1B , 29 1A , 29 1B ) formed so as to cover the storage electrode (18 1A , 18 1B , 28 1A , 28 1B , 25 1A , 25 1B , 35 1A , 35 1B ); and a third conductive film (30₁) formed so as to cover the dielectric film (19 1A , 19 1B , 29 1A , 29 1B ).

Description: The present invention generally relates to a dynamic random access memory device, and more particularly to improvements in a layer structure of a memory cell for a random access memory device. As is well known, a memory cell used in a dynamic random access memory device (hereinafter simply referred to as a DRAM device) is composed of a memory cell capacitor (or a stacked capacitor) and a transfer transistor. In order to reduce the size of a DRAM device, it is necessary to reduce length and width of the memory cell, or an area of the memory cell which occupies a semiconductor substrate. However, when an area(defined by length and width)of the memory cell is equal to or less than 10 µm² , it has heretofore been considered impossible to obtain a memory cell capacitor having sufficient capacitance. In order to increase capacitance of the memory capacitor without increasing the area which the memory cell occupies on the semiconductor substrate, an improved memory cell capacitor structure has been proposed in Japanese Laid-Open Patent Application No. 62-48062. The disclosed improved structure has a memory cell capacitor in which a storage capacitor consists of a plate-shaped film and a vertical projection film, which are made of polysilicon. The plate-shaped film and vertical projection film are formed on an interlayer insulation film. The vertical projection film is in contact with a side wall of the plate-shaped film, and projects over an upper surface of the plate-shaped film. By virtue of the vertical projection film, it is possible to increase the capacitance of the memory cell capacitor. However, the disclosed improvement has disadvantages described below. As described in the above document, the vertical projection film is formed by etching a polysilicon film deposited so as to cover a patterned silicon dioxide film which is formed on the plate-shaped film formed on the interlayer insulation film. In the etching, an upper portion of the deposited polysilicon film in the vicinity of a top surface of the patterned silicon dioxide film is liable to be greatly etched (over-etching), compared with a lower portion of the deposited polysilicon film. As a result, it is very difficult to obtain a predetermined height of the vertical film. Therefore, the capacitance values of different memory cell capacitors are not identical to each other. Normally, the interlayer insulation film on which the plate-shaped and vertical projection films are formed, has recess and convex surface portions due to the presence of gate electrodes. Therefore, it is very difficult to form the vertical projection film on the recess and convex surface portions of the interlayer insulation film with high controllability. The aforementioned patterned silicon dioxide film is removed by isotropic etching in which a gas of HF is used. As a result, the interlayer insulation film on which the plate-shaped and vertical projection films are formed, must be made of silicon nitride (Si₃N₄). JP-A-59-231851 discloses a different type of memory cell structure, also intended to increase capacitance of the memory cell capacitors in a DRAM device. This structure includes a semiconductor substrate; an insulation layer forms over an upper main face of the semiconductor substrate and having a contact window above a contact region of the substrate; a first conductive film formed with an aperture which is above the said contact window; a second conductive film having a first portion in contact with the said contact region of the semiconductor substrate within the said contact window and having also a second portion extending above regions of the said first conductive film that surround the said aperture, which second portion is connected to the said first portion by a part of the said second conductive film that extends through the said aperture and the said contact window, the said first and second conductive films being in electrical connection with one another so as to form a storage electrode of a memory cell of the device; a dielectric film covering the storage electrode; and a third conductive film covering the dielectric film. This structure is essentially tree-like in form, having a central trunk and at least two levels of branches provided respectively by the first conductive film and the said second portion of the second conductive film. The branches are spaced apart vertically by dielectric films and by an interleaving conductive film portion forming part of an opposed electrode of the memory cell capacitor. The height of the structure, however, is relatively large, particularly when, as the document proposes, there are a plurality of levels of the branches, spaced apart one from the next by dielectric films and interleaved conductive film portions. According to a first aspect of the present invention there is provided a dynamic random access memory device including: a semiconductor substrate; an insulation layer formed over an upper main face of the semiconductor substrate and having a contact window above a contact region of the substrate; a first conductive film formed with an aperture which is above the said contact window; a second conductive film having a first portion in contact with the said contact region of the semiconductor substrate within the said contact window and having also a second portion extending above regions of the said first conductive film that surround the said aperture, which second portion is connected to the said first portion by a part of the said second conductive film that extends through the said aperture and the said contact window, the said first and second conductive films being in electrical connection with one another so as to form a storage electrode of a memory cell of the device; a dielectric film covering the storage electrode; and a third conductive film covering the dielectric film; characterised in that the said second portion of the second conductive film extends over the said first conductive film in direct contact therewith. In such a device the memory cells can have a desirably high capacitance value, whilst preserving acceptable electrical characteristics. According to a second aspect of the present invention there is provided a method of producing a random access memory device, including the steps of: forming an insulation layer over an upper main face of a semiconductor substrate having a contact region; forming a first conductive film; patterning the first conductive film and the insulation layer to form an aperture in the first conductive film and a contact window in the insulation layer, the said contact window being above the said contact region of the substrate and the said aperture being above the said contact window; forming a second conductive film so that the film has a first portion in contact with the said contact region of the semiconductor substrate within the said contact window and also has a second portion extending above regions of the sold first conductive film that surround the said aperture, which second portion is connected to the said first portion by a part of the said second conductive film that extends through the said aperture and the said contact window, the first and second conductive films being in electrical connection with one another; patterning the said first and second conductive films so as to define a storage electrode, formed from those films, of a memory cell of the device; forming a dielectric film so as to cover the storage electrode; and forming a third conductive film so as to cover the dielectric film; characterised in that the said second portion of the second conductive film is formed so as to extend over the said first conductive film in direct contact therewith. Such a method can permit desirably simple production of a DRAM device embodying the aforesaid first aspect of the present invention. Reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a cross sectional view of a preferred embodiment of the present invention; FIG.2 is a plan view of an essential portion of a DRAM device having a layer structure of a memory cell provided by the preferred embodiment of FIG.1; FIGS.3 through 8 are cross sectional views taken along the line I-I shown in FIG.1 at different production steps of the preferred embodiment of the present invention; FIGS.9 through 14 are cross sectional views taken along the line II-II shown in FIG.1 at different production steps of the preferred embodiment of the present invention; FIG.15 is a cross sectional view taken along the line I-I shown in FIG.1 for explaining the last manufacturing step of the first embodiment; FIG.16 is a cross sectional view of another preferred embodiment of the present invention; FIGS.17 through 20 are cross sectional views taken along the line I-I shown in FIG.1 at different production steps of another preferred embodiment of the present invention; and FIG.21 is a perspective view having the cross section of FIG.18. A description is given of the first embodiment of the present invention with reference to FIG.1. Referring to FIG.1, the DRAM device of the first embodiment comprises a p-type silicon semiconductor substrate 11, a field insulation film 12, a gate insulation film 13, gate electrodes 14₁, 14₂ and 14₃ of polysilicon, an n⁺-type source region 15 1A , an n⁺-type drain region 16 1A , and an interlayer insulation film 17 of silicon dioxide. An essential feature of the present embodiment is the layer structure of a storage electrode. The storage electrode consists of a first patterned conductive film 18 1A and a second patterned conductive film 25 1A . The second patterned conductive film 25 1A is in contact with the n⁺-type drain region 16 1A . The second patterned conductive film 25 1A is formed so as to overlie the first patterned conductive film 18 1A . The first and second patterned conductive films 18 1A and 25 1A are made of a polysilicon film which is doped with n⁺-type impurity ions such as arsenic ions (As⁺). A dielectric film 19 1A is formed so as to surround the storage electrode. An opposed electrode 20₁ is formed so as to cover the dielectric film 19 1A . An interlayer insulation film 21 is formed so as to cover the opposed electrode 20₁. A bit line 22₁ is formed so as to overlie the interlayer insulation film 21 and make contact with the n⁺-type source region 15 1A . The bit line 22₁ is coated with a passivation film 23. A plurality of word lines 24 are formed on the passivation film 23. A description is given of a method for producing the memory cell of FIG.1 with reference to FIGS.2 through 15. FIG.2 is a plan view of memory cells MC1 and MC2 formed in the DRAM device having the memory cell layer structure of FIG.1. FIGS.3 through 15 are cross sectional views observed at respective essential manufacturing steps. FIGS.3 through 8 and FIG.15 are cross sectional views each taken along the line X-X shown in FIG.2. FIGS.9 through 14 are cross sectional views each taken along the line Y-Y shown in FIG.2. In these figures, those parts which are the same are given the same reference numerals. It is noted that illustrated portions in some figures do not perfectly correspond to illustrated portions in other figures. Referring to Figs. 3 and 9, the field insulation film 12, the gate insulation film 13, the gate electrodes 14₁, 14₂, and 14₃ of polysilicon, the n⁺-type source region 15 1A , the n⁺-type drain region 16 1A , and the interlayer insulation film 17 of silicon dioxide are formed, by conventional production steps, on the p-type silicon semiconductor substrate 11. The gate electrode 14₁ belongs to the memory cell MC1, and the gate electrode 14₂ belongs to the memory coil MC2. The memory cell to which the gate electrode 14₃ belongs is not shown. Referring to Figs. 4 and 10, a polysilicon film 18 is deposited to a thickness of approximately 0.2 µm by chemical vapour deposition (CVD). The polysilicon film 18 is used for forming first patterned conductive films 18 1A and 18 1B , which first conductive films 18 1A and 18 1B provide, in the finished device, a part of respective storage electrodes of the memory cells MC1 and MC2. Referring to FIGS.5 and 11, after depositing a mask film on the entire surface of the silicon substrate 11, the polysilicon film 18 is selectively etched by a conventional photolithography technique (anisotropic etching based on reactive ion etching: RIE) so as to form a contact window 18A for the storage electrode of the memory cell capacitor. Subsequently, by using the same mask film, the interlayer insulation film 17 and the gate insulation film 13 are subjected to selective etching (RIE) so that a surface portion of the drain region 16 1A becomes exposed. It is noted that as shown in FIG.10, edges of the exposed surface of the drain region 16 1A which extend in the X direction shown in FIG.2, are defined by edges of the field insulation film 12 which extend in the X direction. A length of each edge of the exposed surface of the drain region 16 1A in the Y direction can be made smaller than the width of the contact window 18A in the X direction. Therefore, a bit line pitch which is defined as a distance between the centers of adjacent bit lines 22₁ and 22₂ arranged in the Y direction as shown in FIG.2, is made smaller than a word line pitch which is defined as a distance between the centers of adjacent word lines 14₁ and 14₂ arranged in the X direction. Therefore, it becomes possible to efficiently arrange sense amplifiers arranged in the Y direction with the bit line pitch. Thereafter, as shown in FIGS.6 and 12, a polysilicon film 25 is grown to a thickness of 0.1 µm by chemical vapor deposition. Subsequently, n⁺-type impurity ions such as phosphorus (P) ions are implanted into the polysilicon film 25. Thereby, the polysilicon film 25 is changed to an n⁺-type conductive polysilicon film. The polysilicon film 25 thus formed is used for forming second patterned conductive films 25 1A and 25 1B . In the finished device the second conductive films 25 1A and 25 1B provide respectively the remaining part of the respective storage electrodes of the memory cells MC1 and MC2. The polysilicon film 25 is in contact with the drain region 16 1A . Further, the polysilicon film 25 is in contact with an upper surface of the polysilicon film 18, and with an inner surface thereof which faces the contact window 18A. Then, the polysilicon film 25 and the polysilicon film 18 of FIGS.6 and 12 are subjected to a patterning process based on a conventional photolithography technique. Thereby, as shown in FIGS.7 and 13, there are formed the first patterned conductive films 18 1A and 18 1B , and the second patterned conductive films 25 1A and 25 1B . The first and second patterned conductive films 18 1A and 25 1A constitute the storage electrode in the memory cell MC1 shown in FIG.2. It is noted that the storage electrode composed of the first and second patterned conductive films 18 1A and 25 1A has a curved upper surface and high side walls and high inner walls. Therefore, an increased value of capacitance of the memory cell capacitor is obtainable. For example, in a case where the memory cell area is 7 µm² , when the thickness of the storage electrode consisting of the first and second patterned conductive films 18 1A and 25 1A is set to 0.5 µm , the plane area of the memory cell capacitor becomes approximately equal to the side area thereof. Therefore, an reduced plane area of the memory cell capacitor can be compensated by an increased side area thereof. It is further possible to obtain a 20% increase in the total surface area of the memory cell capacitor by the present embodiment. Further, the film thickness or height of the second conductive film 25 1A can be easily controlled by the CVD process. Additionally, the first and second conductive films 18 1A and 25 1A are constituted by plate-shaped films. Therefore, memory cell capacitors each having the second conductive film 25 1A of the same thickness can be formed with high controllability. It is noted that with the aforementioned conventional manufacturing process, it is very difficult to form a uniform height of the side wall film of the aforementioned memory sell capacitor, because the upper portion of the side wall film is over-etched. Moreover, the interlayer insulation film 17 is not limited to a silicon nitride film, but can be made of silicon dioxide. It is preferable to form the first patterned conductive film 18 1A thicker than that of the second patterned conductive film 25 1A . This is because a recessed portion 30 shown in FIG.8 can be made greater, and thereby an further increased surface area of the memory cell capacitor is obtainable. Then, as shown in FIGS.8 and 14, dielectric films 19 1A and 19 1B are formed on the upper surface of the respective second conductive films 25 1A and 25 1B , and side surfaces of the first patterned conductive film 18 A and 18 1B by thermal oxidation in which the silicon substrate 11 is placed in a wet atmosphere. Thereafter, as shown in FIG.15, the opposed electrode 20₁, which is the other electrode of the memory cell capacitor called a cell plate, is formed by depositing and then patterning a polysilicon film. It is preferable to provide the opposed electrode 20₁ with n⁺-type conductivity. Finally, by the conventional techniques, as shown in FIG.15, formed are the interlayer insulation film 21, hit lines 22₁ and 22₂, the passivation film 23 and the word lines 24. A description is given of a second preferred embodiment of the present invention with reference to FIG.16. In FIG.16, those parts which are the same as those in the previous figures are indicated by the same reference numerals. The embodiment of FIG.16 has an essential feature in which a first patterned conductive film 28 1A is formed above the gate electrodes 14₁ and 14₂ in the Y direction, and a second patterned conductive film 35 1A is formed so as to overlie the first patterned conductive film 28 1A and the interlayer insulation film 17. A description is given of the second preferred embodiment of FIG.16 with reference to FIGS.17 through 20 which are cross sectional views observed at different production steps, and FIG.21. In FIGS.17 through 21, those parts which are the same as parts in the previous figures are given the same reference numerals. As described previously, in the first embodiment the same mask film is used for forming the contact window 18A in the polysilicon film 18 1A and then forming the contact window 18A in the the interlayer insulation film 17 and the gate insulation film 13. On the other hand, in the second preferred embodiment, different respective mask films are used for forming a window in the polysilicon film 18 for forming a window in the interlayer insulation film 17 and the gate insulation film 13. The production steps until the polysilicon film 18 is formed, are the same as those in the first embodiment. Therefore, a description is given of a sequence of steps subsequent to the above steps. Referring to FIG.17, the polysilicon film 18 deposited on the interlayer insulation film 17 shown in FIGS.4 and 10, is selectively etched by a conventional photolithography technique so as to form a window 28A for the storage electrode of the memory cell capacitor. Hereinafter, the polysilicon film 18 in which the window 28A is formed is indicated by a reference numeral 28 to make clear a difference between the first and second embodiments. In the above-mentioned step, it is noted that the size of the window 28A is greater than that of the window 18A associated with the first embodiment described previously so that the window 28A extends above the gate electrodes 14₁ and 14₂. With the formation of the window 28A, it becomes possible to increase recesses and convexes on the surface portion of the storage electrode and to thereby increase the total surface area of the storage electrode, compared with the first embodiment. After removing the mask film used for forming the window 28A in its entirety, another mask film is deposited. Then, the interlayer insulation film 17 and the gate insulation film 13 are selectively etched so as to form a window 27A through which a surface portion of the drain region 16 1A is exposed. In this case, it is preferable to define edges of the exposed surface portion of the drain region 16 1A which extend in the X direction by edges of the field insulation film 17 extending in the X direction, as in the case of the first embodiment. Thereafter, as shown in FIG.18, a polysilicon film 35 is grown to a thickness of approximately 0.1 µm by chemical vapor deposition. Subsequently, n⁺-type impurity ions such as phosphorus (P) ions are implanted into the polysilicon film 35. The polysilicon film 35 is used for forming the second patterned conductive film of the storage electrode. The polysilicon film 35 is in contact with the drain region 16 1A and the polysilicon film 28. The polysilicon film 35 and the polysilicon film 28 of FIG.19 are patterned by a conventional photolithography technique. Thereby, as shown in FIGS.20 and 21, first patterned conductive films 28 1A and 28 1B , and second patterned conductive films 35 1A and 35 1B are formed which constitute storage electrodes. Referring to FIG.20, dielectric films 29 1A and 29 1B are formed so as to cover surfaces of the first and second patterned conductive films 25 1A , 25 1B and 35 1A , 35 1B by thermal oxidation in which the silicon substrate 11 is placed in a wet atmosphere. Production steps subsequent to the step for formation of the dielectric films 29 1A and 29 1B are the same as those described previously. With the layer structure of the second embodiment, an approximately 30 % increase in capacitance of the memory cell capacitor is obtainable.

Claims: A dynamic random access memory devise including: a semiconductor substrate (11); an insulation layer (13,17) formed over an upper main face of the semiconductor substrate (11) and having a contact window (18 A ) above a contact region (16 1A ,16 1B ) of the substrate; a first conductive film (18 1A ,18 1B ;28 1A ,28 1B ) formed with an aperture which is above the said contact window; a second conductive film (25 1A ,25 1B ;35 1A ,35 1B ) having a first portion in contact with the said contact region of the semiconductor substrate (11) within the said contact window and having also a second portion extending above regions of the said first conductive film that surround the said aperture, which second portion is connected to the said first portion by a part of the said second conductive film that extends through the said aperture and the said contact window, the said first and second conductive films being in electrical connection with one another so as to form a storage electrode of a memory cell of the device; a dielectric film (19 1A ,19 1B ;29 1A ,29 1B ) covering the storage electrode; and a third conductive film (20₁) covering the dielectric film; characterised in that the said second portion of the second conductive film extends over the said first conductive film in direct contact therewith. A dynamic random access memory device as claimed in claim 1, characterised in that the first conductive film (18 1A , 18 1B ; 28 1A , 28 1B ) is thicker than the second conductive film (25 1A , 25 1B ; 35 1A , 35 1B ). A dynamic random access memory device as claimed in claim 1 or 2, characterised in that the first conductive film (18 1A , 18 1B ; 28 1A , 28 1B ) and the second conductive film (25 1A , 25 1B ; 35 1A , 35 1B ) comprise polysilicon. A dynamic random access memory device as claimed in claim 1, 2 or 3, characterised in that the said contact window (18A) formed in the insulation layer (13, 17) is substantially equal in width to the said aperture (18A) formed in the first conductive film (18 1A , 18 1B ). A dynamic random access memory device as claimed in claim 1, 2 or 3, characterised in that the said aperture (28A) formed in the first conductive film (28 1A , 28 1B ) is greater in width than the said contact window (27A) formed in the insulation layer (13, 17), so that the said part of the second conductive film is in contact with the insulation layer (13, 17) within the said aperture (20A). A dynamic random access memory device as claimed in any preceding claim, characterised in the said part of the second conductive film (25 1A , 25 1B , 35 1A , 35 1B ), where it is in contact with side surfaces of the first conductive film (18 1A , 18 1B ; 28 1A , 28 1B ) bounding the said aperture (18A, 28A), is of such a thickness that the second conductive film does not fill the said aperture. A dynamic random access memory device as claimed in any preceding claim, wherein the said contact region (16 1A , 16 1B ) is an impurity diffusion region and the device further includes a field insulation film (12) formed between the said insulation layer (13, 17) and the semiconductor substrate (11) and having an opening below the said contact window (18A; 27A) and above the said contact region (16 1A , 16 1B ), the said opening being narrower than the said contact window in a predetermined direction so that opposite edge regions of the field insulation film which bound the said opening extend within the said contact window at opposite sides thereof respectively. A method of producing a random access memory device, including the steps of: forming an insulation layer (13, 17) over an upper main face of a semiconductor substrate (11) having a contact region (16 1A , 16 1B ); forming a first conductive film (18); patterning the first conductive film and the insulation layer to form an aperture in the first conductive film and a contact window (18A; 28B) in the insulation layer, the said contact window (18A; 27A) being above the said contact region of the substrate and the said aperture being above the said contact window; forming a second conductive film (25) so that the film has a first portion in contact with the said contact region of the semiconductor substrate within the said contact window and also has a second portion extending above regions of the said first conductive film that surround the said aperture, which second portion is connected to the said first portion by a part of the said second conductive film that extends through the said aperture and the said contact window, the first and second conductive films being in electrical connection with one another; patterning the said first and second conductive films so as to define a storage electrode, formed from those films, of a memory cell of the device; forming a dielectric film (19 1A , 19 1B ; 29 1A , 29 1B ) so as to cover the storage electrode; and forming a third conductive film (20₁) so as to cover the dielectric film; characterised in that the said second portion of the second conductive film is formed so as to extend over the said first conductive film in direct contact therewith. A method as claimed in claim 8, characterised in that, in the step of patterning the first conductive film (18) and the insulation layer (13, 17), the mask film that is used for patterning the first conductive film (18) serves also for patterning the insulation layer (13, 17). A method as claimed in claim 8, characterised in that, in the step of patterning the first conductive film (18) and the insulation layer (13, 17), different respective mark films are used for patterning the first conductive film (18) and for patterning the insulation layer (13, 17), the mask film used for patterning the first conductive film (18) being such that the said aperture (28A) exposes regions of the insulation layer (13, 17) that surround the said contact window (27A). A method as claimed in claim 8, 9 or 10, characterised in that the step of patterning the first conductive film (18) and the insulation layer (13, 17) is carried out by anisotropic etching. A method as claimed in any one of claims 8 to 11, characterised in that the first and second conductive films (18, 25) comprise polysilicon. A method as claimed in any one of claims 8 to 12, characterised in that the respective steps of forming the first and second conductive films (18, 25) are carried out such that the first conductive film (18) is thicker than the second conductive film (25). A method as claimed in any one of claims 8 to 13, wherein in the step of patterning the first and second conductive films the same mask film is used for patterning both of the conductive films (18, 25).

Inventors: EMA TAIJI, EMA, TAIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H01L27
IPC codes: H01L27, H01L21