CHARGE PUMP CIRCUITRY HAVING LOW SATURATION VOLTAGE AND CURRENT-LIMITED SWITCH

Abstract: A charge pump circuit in integrated form utilizes a dual emitter transistor switch having low saturation voltage. The low saturation voltage for the transistor is provided by deriving a base bias voltage from the doubled voltage (2V cc and a collector voltage from the voltage supply (V cc ). Current-limiting for the transis­ tor is provided by connecting one emitter to the base bias circuitry whereby the second emitter acts as a collector when the transistor saturates, thereby limiting the base drive and causing current-limiting.

Description: This invention relates generally to charge pump circuitry for generating positive and negative voltage potentials using a single supply voltage source, and more particularly the invention is directed to a charge pump integrated circuit. The technique of doubling a voltage from a supply voltage source by switchably charging a capacitor and altering the capacitor terminals with respect to the voltage source is well known. Such a charge pump enables flexibility in circuit operation by providing a plurality of voltage potentials to circuit elements. For example, the product designated ICL7660, manufactured by Maxim Integrated Products, Inc., of Sunnyvale, California, is a charge pump circuit operative in an inverting mode to produce voltage polarities opposite to that of the supply voltage from which they are generated. As a further example, a charge pump power supply disposed to operate in both inverting and non-inverting modes is described in U.S. Patent 4,636,930. This dual-mode charge pump circuit is designed to convert a unipolar supply voltage to a bipolar supply voltage of greater magnitude. The present invention is directed to an integrated circuit functioning with discrete capacitors as a charge pump in doubling a voltage from a voltage source and providing both positive and negative voltages therefrom. A preferred feature of the invention is the use of a transistor switch having a low saturation voltage. Another preferred feature of the invention is a switch that is current-limited and thus limits the supply current when charging a capacitor. The invention provides that within a charge pump circuit having a supply terminal for connecting to a voltage source, V cc , a ground terminal for connecting to a ground potential, a first capacitor serially connected with first and second switch means between said supply terminal and said ground terminal, a third switch means connected in parallel with said first switch means and said first capacitor, a second capacitor serially connected with fourth and fifth switch means between the common terminal of said first switch means and said first capacitor and said ground terminal, a third capacitor serially connected between a positive voltage (+2V cc ) terminal and said ground terminal, a fourth capacitor serially connected with a sixth switch means between said ground potential and the common terminal of said second capacitor and said fifth switch means, the common terminal of said fourth capacitor and said sixth switch means connected to a negative voltage (-2V cc ) terminal, and a seventh switch means connected in parallel with said second capacitor and said fifth switch means, whereby closure of said first and second switch means during a first operational phase generates a voltage V cc across said first capacitor, characterised by an eighth switch means connected between said positive voltage (+2V cc ) terminal and the common terminal of said first switch means and said first capacitor, whereby closure of said third, fourth, fifth and eighth switch means during a second operational phase transfers a voltage +2V cc to said second and third capacitors, and during a subsequent first operational phase closure of said sixth and seventh switch means induces a voltage -2V cc to be transferred to said fourth capacitor. The invention also provides a method of operating the charge pump circuit wherein said third switch means comprises a dual-emitter bipolar transistor, a method of limiting source current comprising the steps of providing bias circuitry for said bipolar transistor switch with the base bias for said bipolar transistor switch being derived from said second capacitor (2V cc ), and a collector voltage derived from said voltage source (V cc ), thereby operating said bipolar transistor with low saturation voltage, and connecting one emitter of said dual-emitter bipolar transistor switch to said bias circuitry whereby operation of said transistor is current-limited. The invention and objects of features thereof will be more readily apparent from the following detailed description of an example taken with the drawings, in which: Figs. 1A and 1B are schematics illustrating operation of a charge pump integrated circuit embodying the invention. Fig. 2 is a schematic of one embodiment of a charge pump integrated circuit in accordance with the invention. Referring now to the drawings, Figs. 1A and 1B illustrate operation of a charge pump integrated circuit in accordance with the invention. The circuit has two-phase operation in charging a capacitor and then transferring charge from the capacitor to generate positive and negative voltage potentials from a single voltage source. The circuit comprises a terminal connected to a voltage source, V cc , and a terminal connected to a circuit ground potential. Four discrete capacitors C1-C4 are interconnected between the supply voltage V cc and the ground potential by eight switches S1-S8 that are selectively closed in response to the two-phase clock 10. During phase 1, as illustrated in Fig. 1A, switches S1 and S2 serially interconnect capacitor C1 between the supply voltage V cc and circuit ground, thereby developing a voltage potential across capacitor C1 of V cc . Switch S7 connects one terminal of capacitor C2 to ground, and switch S8 connects the other terminal of capacitor C2 to a -V terminal, at which a voltage of -2V cc will be generated. During Phase 2, as illustrated in Fig. 1B, switches S1, S2, S7 and S8 are opened, and switch S3 connects the source voltage V cc to the negative terminal of capacitor C1. The positive terminal of capacitor C1 is interconnected through switch S4 to a +V terminal and charges capacitor C3 to a voltage potential of twice the supply voltage or 2V cc . The doubled supply voltage, 2V cc , is applied also through switch S5 to a terminal of capacitor C2, the other terminal of which is interconnected to ground through switch S6. Thus, a voltage potential of 2V cc is stored on capacitor C2 and capacitor C3. On the following Phase 1 of the clock, the positive terminal of capacitor C2 is tied to ground through switch S7, thereby causing the doubled voltage stored on capacitor C2 to appear on the negative terminal of capacitor C2. The doubled negative voltage is then stored in capacitor C4 through switch S8. Thus, a V+ voltage of 2V cc and a V- voltage of -2V cc are provided across capacitors C3 and C4, respectively. In designing the circuitry of Figs. 1A and 1B (less capacitors C1-C4) in integrated circuit form, it is important to have a switch S3 transistor with a low saturation voltage and which is current-limited in operation. This is achieved in the circuitry of Fig. 2 which corresponds to the circuitry of Figs. 1A and 1B. In this circuit, a Schottky diode D1 functions as switch S1, transistor Q4 functions as switch S2, a dual-emitter transistor Q1 functions as switch S3, a Schottky diode D2 functions as switch S4, a transistor Q5 functions as switch S5, Schottky diode D3 functions as switch S6, transistor Q6 functions as switch S7 and Schottky diode D4 functions as switch S8. In this embodiment, the dual-emitter transistor Q1 is an NPN transistor; a PNP transistor could be employed but would be larger in size. In order for an NPN transistor to have a low saturation voltage, the base of the transistor must be driven by a voltage that is greater than the collector voltage. This is accomplished in Fig. 2 with the base drive circuitry comprising transistors Q2 and Q3 which are interconnected to the self-generated V+ supply (2V cc ), thus providing transistor Q1 with a base voltage greater than the collector voltage (V cc ). Accordingly, the dual- emitter transistor Q1 will function with low saturation voltage. Due to the nature of the circuit design, the current drawn from the V+ potential will be one-half of the supply current from V cc . Thus, in order to keep the supply current at its lowest, the transistor Q1 must be current-limited. This is accomplished by connecting one emitter of transistor Q1 to the base drive circuitry comprising transistors Q2 and Q3. Thus, when transistor Q1 saturates, the second emitter acts as a collector and limits the base drive, thereby causing current-limiting. Charge pump circuitry in accordance with the invention has proved to be particularly advantageous in an integrated circuit. As described, the circuit functions with low saturation voltage and is current-limited, thereby limiting the supply current.

Claims: In a charge pump circuit comprising a supply terminal for connecting to a voltage source, V cc , a ground terminal for connecting to a ground potential, a first capacitor (C1) serially connected with first and second switch means (S1,S2) between said supply terminal and said ground terminal, a third switch means (S3) connected in parallel with said first switch means (S1) and said first capacitor (C1), a second capacitor (C2) serially connected with fourth and fifth switch means (S5,S6) between the common terminal of said first switch means (S1) and said first capacitor (C1) and said ground terminal, a third capacitor (C3) serially connected between a positive voltage (+2V cc ) terminal and said ground terminal, a fourth capacitor (C4) serially connected with a sixth switch means (S8) between said ground potential and the common terminal of said second capacitor (C2) and said fifth switch means (S6), the common terminal of said fourth capacitor (C4) and said sixth switch means (S8) connected to a negative voltage (-2V cc ) terminal, and a seventh switch means (S7) connected in parallel with said second capacitor (C2) and said fifth switch means (S6), whereby closure of said first and second switch means (S1,S2) during a first operational phase generates a voltage V cc across said first capacitor (C1), characterised by an eighth switch means (S4) connected between said positive voltage (+2V cc ) terminal and the common terminal of said first switch means (S1) and said first capacitor (C1), whereby closure of said third, fourth, fifth and eighth switch means (S3,S5,S6,S4) during a second operational phase transfers a voltage +2V cc to said second and third capacitors (C2,C3), and during a subsequent first operational phase closure of said sixth and seventh switch means (S8,S7) induces a voltage -2V cc to be transferred to said fourth capacitor (C4). The charge pump circuit as defined by claim 1 wherein said third switch means comprises a bipolar transistor (Q1), and further including biasing circuitry (Q2,Q3) interconnecting said positive voltage +2V cc to the base of said bipolar transistor (Q1) whereby said bipolar transistor has a low saturation voltage. The charge pump circuit as defined by claim 2 wherein said bipolar transistor (Q1) comprises a dual-emitter transistor, one emitter being connected to said biasing circuitry (Q2,Q3) whereby saturation of said transistor limits base drive and thereby causes current-limiting in said transistor. The charge pump circuit as defined in any preceding claim wherein said circuitry comprises an integrated circuit and discrete capacitors. The charge pump circuit as defined by claim 4 wherein said first switch means comprises a Schottky diode, said second switch means comprises a bipolar transistor, said fourth switch means comprises a bipolar transistor, said fifth switch means comprises a bipolar transistor, said sixth switch means comprises a Schottky diode, said seventh switch means comprises a Schottky diode, and said eighth switch means comprises a Schottky diode. A method of limiting source current using a dual-emitter bipolar transistor in a charge pump circuit according to Claim 3 comprising the steps of providing bias circuitry for said bipolar transistor switch with the base bias for said bipolar transistor switch being derived from said second capacitor (2V cc ), and a collector voltage derived from said voltage source (V cc ), thereby operating said bipolar transistor with low saturation voltage, and connecting one emitter of said dual-emitter bipolar transistor switch to said bias circuitry whereby operation of said transistor is current-limited. The method as defined by claim 6 wherein said dual-emitter bipolar transistor is an NPN transistor, said step of providing bias circuitry comprising providing a PNP bipolar transistor and an NPN transistor, the emitter of said PNP transistor and the collector of said NPN transistor of said bias circuitry transistors being connected to receive the voltage (2V cc ), the collector of said PNP transistor being connected to the base of said NPN transistor, the emitter of said NPN transistor being connected to the base of said dual-emitter transistor, and an emitter of said dual-emitter transistor being connected to the base of said NPN transistor and the collector of said PNP transistor.

Inventors: DOBKIN, ROBERT C., ESSAFF, ROBERT
Applicants: LINEAR TECHNOLOGY CORPORATION
Application year: 1988
Main classification: H02M3
IPC codes: H02M3, H01L27, H01L21