RELAXATION OSCILLATOR

Abstract: Oscillator in which a capacitor (1) is periodically charged and discharged. In accordance with the invention, two transistors (T3, T6) are connected parallel to the capacitor with their base-emitter paths in anti-parallel. When a voltage equal to the base-emitter voltage of one of the transistors is reached, this transistor is turned on so that: a) the capacitor is not charged further, and b) switching over takes place from charging to discharging (= charging in the opposite sense). Thus, the effect of noise on the instant of switching over is substantially reduced.

Description: The invention relates to a relaxation oscillator comprising a capacitor, a charging circuit, a discharging circuit, switching means for in a first position charging the capacitor by means of the charging circuit and for in a second position discharging the capacitor by means of the discharging circuit, and a feedback circuit which supplies a first feedback signal for setting the switching means from the first position to the second position after the capacitor voltage has reached a first value and which supplies a second feedback signal for setting the switching means from the second position to the first position after the capacitor voltage has reached a second value. A relaxation oscillator of this kind is known from IEEE Journal of Solid State Circuits, Vol. SC-18, No. 6, December 1983, pages 794-801. The feedback circuit thereof is formed by a flipflop circuit. As soon as the capacitor voltage exceeds one of the trigger points of the flipflop circuit, the flipflop switches over and the switching means are set to the first or the second position. A relaxation oscillator of this kind delivers a delta voltage whose peak-to-peak value is determined inter alia by said first and second voltage values, the hysteresis of the flipflop circuit, and the loop gain present at the instant of switching. The cited article discloses, explicitly or not, a number of possibilities for improving the noise behaviour of the relaxation oscillators, i.e. increasing the capacitor delta voltage, increasing the loop gain at the instant of switching, reducing the effect of the hysteresis of the flipflop circuit, and the fast switching over of the current by means of a fast flipflop circuit. The problem of noise in relaxation oscillators can usually be avoided by using other oscillator types displaying low-noise behaviour. However, considering the advantages offered by a relaxation oscillator, such as a wide frequency tuning range and the possibility of integration in an IC, further improvement of the noise behaviour of the relaxation oscillators is desirable. Therefore, it is an object of the invention to provide a relaxation oscillator which exhibits a further improved noise behaviour. To achieve this, the relaxation oscillator of the kind set forth in accordance with the invention is characterized in that the feedback circuit comprises a first and a second transistor which are connected in a mutually opposite orientation across the capacitor with their respective paths between gate electrode and first main electrode, the first and the second feedback signal, respectively, being derived from a voltage value on a second main electrode of the first transistor and the second transistor, respectively. In the embodiment of a relaxation oscillator which is shown in Figure 17 of the cited article, the feedback circuit comprises two independently operating transistor pairs in a differential amplifier configuration; because the present invention utilizes only two independently operating switching elements, i.e. only two independently operating bipolar transistors or mosfets, the noise behaviour of the relaxation oscillator in accordance with the invention will be much better. If desired, diodes can be connected in the base lead and/or the emitter lead or in the source lead. The transistors, now have a dual function: on the one hand they operate as a comparator for the capacitor voltage in order to derive the feedback signals for the switching means, and on the other hand they form an accurately defined limitation for the capacitor voltage. The feedback circuit in accordance with the invention may also comprise a low-pass filter which is connected to both switching elements. This low-pass filter also improves the noise behaviour of the relaxation oscillator; however, it introduces a delay in the switching over of the switching means. Because the switching elements constitute a limitation for the capacitor, however, despite the delay, the capacitor voltage will be maintained at a constant value during this delay. In accordance with the invention, the relaxation oscillator is characterized by its integration in an integrated circuit. The relaxation oscillator can be integrated as part of a larger circuit or as a circuit with only this function. The invention will be described in detail hereinafter with reference to the accompanying drawings; wherein: Figure 1 shows the circuit diagram of the known type of relaxation oscillator; Figure 2 shows an embodiment of a relaxation oscillator in accordance with the invention; and Figure 3 shows a diagram illustrating the operation of the embodiment shown in Figure 2. Corresponding parts in the Figures are denoted by corresponding reference numerals. The embodiment described with reference to the drawings is given merely by way of example and the invention is by no means restricted thereto. The relaxation oscillator which is diagrammatically shown in Figure 1 comprises a capacitor 1, a charging circuit 2, a discharging circuit 3, a switch 4, and a feedback circuit 5. The charging circuit 2 and the discharging circuit in Figure 1 are shown as current sources which draw a current I. When the switch 4 occupies the first position (as shown in Figure 1), the capacitor 1 is charged by the current source 2; when the switch 4 is set to the second position, the current source 3 draws a discharging current I from the capacitor 1. The capacitance C of the capacitor 1 is such that a substantially linear voltage variation occurs across the capacitor during charging and discharging, so that ultimately a substantially delta-shaped voltage variation will occur across the capacitor. The capacitor voltage Vc is applied to the feedback circuit 5. Therein it is compared with a first, higher voltage value Vref.1 and with a second, lower voltage value Vref.2. When the capacitor voltage reaches the value Vref.1, the feedback circuit 5 supplies a first feedback signal which sets the switch 4 from the first to the second position so that the capacitor 1 is discharged and the capacitor voltage Vc decreases. As soon as the capacitor voltage Vc subsequently reaches the value Vref.2, the feedback circuit 5 supplies a second feedback signal which sets the switch 4 from the second to the first position so that the capacitor 1 is charged again and hence the capacitor voltage Vc increases again. In the embodiment in accordance with the invention which is shown in Figure 2, the current sources 2 and 3, together with the switch 4, are formed by a bridge circuit which includes the capacitor 1. This bridge circuit is composed of the transistors T1, T2, T4, T5, T7 and T8, the current sources 6 and 7 and the resistors 8, 9, 10 and 11. The capacitor 1 is charged, for example when the transistors T1, T2 are turned on and the transistors T4, T5 are turned off. The capacitor 1 is discharged, i.e. charged with the opposite polarity, when the transistors T1, T2 are turned off and the transistors T4, T5 are turned on. The charging current flows via the resistor 9, the transistor T1, the capacitor 1, the transistor T2 and the current source 7. The voltage on the lead 12 should then be so "high" that the transistors T2 and T7 are turned on so that a voltage drop occurs across the resistor 11 such that the base voltage of the transistor T4 is "low" and, consequently, this transistor is turned off. Furthermore, the voltage on the lead 13 should then be so "low" that the transistors T5 and T8 are turned off, so that the base voltage of the transistor T1 is "high" and, consequently, this transistor is turned on. During the discharging of the capacitor 1, the current flows via the resistor 10, the transistor T4, the capacitor 1, the transistor T5 and the current source 7. The voltage on the lead 12 should be so "low" that the 6 transistors T2 and T7 are turned off, so that the base voltage of the transistor T4 is "high" and, consequently, this transistor is turned on. Furthermore, the voltage on the lead 13 should then be so "high" that the transistors T5 and T8 are turned on, so that such a voltage drop occurs across the resistor 8 that the base voltage of the transistor T1 is "low" and, consequently, this transistor remains turned off. Therefore, during charging the voltage on the lead 12 should be "high" and that on the lead 13 should be "low", whilst during discharging, i.e. during charging with the opposite polarity, the voltage on the lead 12 should be "low" and that on the lead 13 should be "high". Across the capacitor 1 there are arranged two switching elements which are in this case formed by the transistors T3 and T6. These transistors are connected across the capacitor 1 with the base and the emitter in anit-parallel. During the charging of the capacitor 1, the voltage across the capacitor increases until the base-emitter voltage Vbe(T3) of the transistor T3 is reached and this transistor is turned on. Similarly, during discharging, i.e. during charging with the opposite polarity, the voltage across the capacitor 1 decreases until it has increased in the negative sense to such an extent that the base-emitter voltage Vbe(T6) of the transistor T6 is reached and this transistor is turned on. Consequently, the capacitor voltage varies between two values Vref.1 and Vref.2, where: Vref.1 - Vref.2 = Vbe(T3) + Vbe(T6). Diodes may be connected between the base of the transistors T3 and T6 and the relevant connection to the capacitor 1. Similarly, diodes may also be connected between the emitter of the transistors T3 and T6 and the relevant other connection to the capacitor 1. The transistor T4 is turned off during charging; when the capacitor voltage reaches its upper limit and the transistor T3 is turned on, an increasing current flows via the resistor 10 and the transistor T3, which current is withdrawn from the charging current through the resistor 9 and the transistor T1; the total current drawn by the current source 7 via the transistor T2 remains constant. Consequently, the voltage at the point P increases and that at the point Q decreases. Due to this variation of the voltage values VP and VQ, the voltage values on the leads 12 are "reversed", i.e. they become "low" and "high", respectively, via a feedback circuit which includes a low-pass filter 14 and a control amplifier 15 in the present embodiment; consequently, the capacitor 1 is discharged until the capacitor voltage reaches its lower limit and the transistor T6 is turned on. The transistor T3 is turned off again during discharging. As soon as the transistor T6 is turned on, an increasing current will flow via the resistor 9 and the transistor T6, which current is withdrawn from the discharging current through the resistor 10 and the transistor T4; the total current drawn by the current source 7 via the transistor T5 remains constant. Consequently, the voltage at the point P decreases and that at the point Q increases. This variation of the voltage values VP and VQ causes "reversal" of the voltage values on the leads 12 and 13 to their former values again via said feedback circuit, so that the capacitor voltage can increase again. Thus, the transistors T3 and T6 on the one hand determine the instant at which the increase and the decrease, respectively, of the capacitor voltage must be interrupted, and on the other hand they ensure that the capacitor voltage is maintained at a constant value for as long as the capacitor voltage variation in the opposite direction has not yet started. The difference in time between the turning on of the transistors T3 and T6 and the start of reversed voltage variation across the capacitor is caused by the delay in the feedback circuit which is due notably to the low-pass filter 14. Even though this filter is extremely desirable for improving the noise behaviour of the relaxation oscillator, it does introduce a delay. The capacitor voltage is maintained constant during this delay. Figure 3 shows the voltage variation across the capacitor 1, which variation takes place, each time with a delay τ, between the two values Vref.1 and Vref.2. It will be apparent that the terms "charging" and "discharging" as used herein can be simply interchanged and that the circuit shown in Figure 2 can be modified in various ways without departing from the scope of the present invention. As has already been stated, for example diodes can be included in the base leads and emitter leads of the transistors T3 and T6.

Claims: 1. A relaxation oscillator comprising a capacitor, a charging circuit, a discharging circuit, switching means for in a first position charging the capacitor by means of the charging circuit and for in a second position discharging the capacitor by means of the discharging circuit, and a feedback circuit which supplies a first feedback signal for setting the switching means from the first position to the second position after the capacitor voltage has reached a first value and which supplies a second feedback signal for setting the switching means from the second position to the first position after the capacitor voltage has reached a second value, characterized in that the feedback circuit comprises a first and a second transistor which are connected in a mutually opposite orientation across the capacitor with their respective paths between gate electrode and first main electrode, the first and the second feedback signal, respectively, being derived from a voltage value on a second main electrode of the first transistor and the second transistor, respectively. 2. A relaxation oscillator as claimed in Claim 1, characterized in that, in series with at least one of said paths, a diode is provided across the capacitor. 3. A relaxation oscillator as claimed in Claim 1 or 2, characterized in that the transistors are of a bipolar type, said paths being base-emitter paths and the second main electrodes being collectors. 4. A relaxation oscillator as claimed in Claim 1 or 2, characterized in that the feedback circuit comprises a low-pass filter which is connected to both transistors. 5. Relaxation oscillator as claimed in any one of the preceding Claims, characterized by its integration in an integrated circuit.

Inventors: SEMPEL, ADRIANUS
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1988
Main classification: H03K3
IPC codes: H03K3, H03K4