Bias and precharging circuit for a bit line of EPROM memory cells in CMOS technology

Abstract: The bias and precharging circuit comprises a bias part (5) and a precharging part (6) of the bit line (1) together with a sensing amplifier (7) operating by comparison of the voltage of the bit line (1) and a dummy bit line (2). The precharging part (6) comprises means (21) for turning off the bias and precharging parts (5, 6) as soon as the sensing amplifier (7) has read the cell subjected to precharging. The bias part (5) comprises means (16) for amplifying the voltage unbalance produced by bias between the bit line (1) and the dummy bit line (2). It provides current-mirror means (13, 14, 15) to cause said voltage unbalance independently of the precharging part (6).

Description: The subject of the present invention is a bit line bias and precharging circuit for reading EPROM memory cells in CMOS technology. Known circuits of this type used for reading cells of an EPROM memory cell matrix comprise a part designed for bias of the bit line and a part designed for fast precharging of said bit line. There is also provided a sensing amplifier operating by comparison of the voltage of said bit line with that of a dummy bit line connected to comparison memory cells never subjected to programming. Said circuits are based on the principle that bias originates in the bit line a voltage which depends on the state of conduction of the cell being read and is thus unbalanced with that of the dummy bit line. The unbalance is sensed by the sensing amplifier, which converts it into a reading signal indicating the state of the cell being read. Precharging makes reading fast. The principal drawbacks of the abovesaid circuits are represented at present by high current consumption and the need for a very sensitive and hence rather complicated sensing amplifier which would be capable of sensing a rather small voltage unbalance at its ends. EP-A-0 102 485 teaches the idea of switching off bit line active loads in a ROM to save power. US-A-4 223 394 teaches the use of a cascode amplification stage for biasing a bit line. WO 84/02800 teaches the use of two current sources for biasing sensing nodes coupled to a bit line and to a dummy bit line with the same current. The object of the present invention is to realize a bit line bias and precharging circuit for reading EPROM memory cells in CMOS technology which is free from the aforesaid drawbacks and specifically provides very small current consumption and allows the use of a less sensitive and hence simpler sensing amplifier. In accordance with the invention said object is achieved by a bit line bias and precharging circuit as defined in claim 1. According to a preferred embodiment of the circuit in accordance with the invention the bias part comprises a cascode amplification stage placed on the bit line to amplify the voltage unbalance caused by bias of a cell at the input of the sensing amplifier. Further in accordance with a preferred embodiment of the invention the bias part comprises current-mirror means placed between the bit line and the dummy bit line to cause said voltage unbalance. As a result current consumption of the circuit is clearly reduced due to the effect of turning off the precharging and bias parts of the circuit at the end of the time strictly necessary for the sensing amplifier to read the state of the cell. At the same time amplification of the voltage unbalance by the cascode stage and use of a current mirror allow use of a less sensitive and hence simpler sensing amplifier. A preferred embodiment of the circuit in accordance with the invention is illustrated for greater clarity in the annexed drawing which shows the circuit diagram thereof. In the drawing reference numbers 1 and 2 indicate a bit line and a dummy bit line respectively which connect a voltage supply terminal 3 to an EPROM memory 4 with CMOS technology comprising in a known manner a matrix of memory cells selectable by means of a plurality of bit lines branching from the bit line 1 through a decoder and a plurality of word lines perpendicular to the bit lines as well as a plurality of comparison cells never subjected to programming to which is connected the dummy bit line 2. With the lines 1 and 2 is associated a bias and precharging circuit made up of a bias part 5 and a fast precharging part 6. There is also provided a sensing amplifier 7 placed between respective intermediate circuit nodes 8 and 9 of the lines 1 and 2. The bias part 5 is controlled through a P channel transistor 10 whose gate receives a control signal A which constitutes the negation of a control signal A for the precharging part 6, both signals being emitted by an appropriately controlled generator 11. Said bias part comprises on the dummy line 2 between the memory 4 and the circuit node 9 an N channel transistor 12 with gate controlled by a reference voltage Vref while between the circuit node 9 and the control transistor 10 are placed in parallel two equal P channel transistors 13 and 14 with gate terminals connected to respective drain terminals. To said transistors 13 and 14 corresponds on the line 1, in current mirror configuration, an equal P channel transistor 15 with gate terminal connected to the common gate and drain terminals of the transistors 13 and 14. Between the circuit node 8 and the memory 4, again on the bit line 1, there is placed an N channel transistor 16 controlled by the reference voltage Vref and constituting a cascode amplification stage for the voltage unbalance which occurs between the two lines 1 and 2 in the reading phase. The precharging part 6 comprises a P channel control transistor 17 placed between a supply terminal 18 and the memory 4 with an N channel transistor 19 in series and controlled by the reference voltage Vref. The gate of the transistor 17 is controlled by the output of a NAND logic port 20 which receives at one input the abovementioned control signal A and has another input connected to the output of a flip-flop 21 made up of two NAND logic elements 22 and 23. One input of the logic element 22 is connected to the circuit node 8 through an inverter 24. One input of the logic element 23 receives an initialization signal B. The output of said logic element 23 forms a signal C which acts on the generator 11 in such a manner as to switch the signals A and A to a logic level such as to turn off the precharging part 6 and the bias part 5 after reading by the sensing amplifier 7. An external reading signal D applied to the generator 11 is used to start precharging. Between the circuit node 8 and ground there is placed an N channel transistor 25 with gate controlled by the signal A . At rest, the output signal A of the generator 11 is at low level and the inverted output signal A is at high level; the transistors 17 and 10 therefore are off and the transistor 25 is on, thus connecting the circuit node 8 and, through the transistor 16, the bit line 1 to ground. When a cell reading operation is started, a reading signal D causes the generator 11 to bring the signal A to high level and the signal A to low level; the transistors 17 and 10 therefore are turned on and the transistor 25 is turned off. The transistor 10 provides the dummy bit line 2 with a first bias current and, therefore, with a first bias voltage at the circuit node 9, and further provides the bit line 1 with a second bias current and, therefore, with a second bias voltage at the circuit node 8. This second bias voltage depends on the programmed or non-programmed state of the cell being read, connected to the bit line 1. The sensing amplifier 7 compares the bias voltages at the nodes 8 and 9. The transistor 16 is, in usual way, an amplifier which amplifies the voltage unbalance at the inputs of the sensing amplifier 7. The transistor 17 and, generally speaking, the precharging part 6 have the purpose of rapidly raising the bias voltage of the bit line 1. When the transistor 17 is turned on, a strong current is fed to the bit line 1, therefore raising the voltage at the node 8 to a precharge voltage value. The turning on of the transistor 15 causes said precharge voltage value to increase or decrease according to whether the memory cell being read is a programmed or virgin cell. When the voltage at the node 8 reaches a high level precharge voltage value, the inverter 24 causes the flip-flop 21 to switch to a state in which the signal C causes the reset of the generator 11 to a state with the signal A at low level and the signal A at high level. The transistors 17 and 15 are therefore turned off to reduce to zero the current consumption of the circuit after reading.

Claims: A bit line bias and precharging circuit for an EPROM memory cell in CMOS technology arranged on a bit line (1), comprising a bias part (5) adapted to be connected to the bit line (1) and a precharging part (6) connected to the bias part (5) and adapted to be connected to the bit line (1), said bias part (5) including a sense amplifier (7) having a first input (9), a second input (8) and first switch means (10) activated in response to a reading signal (D) for feeding a first bias current to a dummy bit line (2) arranged in parallel with said bit line (1) to produce a first bias voltage at said first input (9) of the sense amplifier (7) and for feeding a second bias current to said bit line (1) to produce a second bias voltage depending on the state of the memory cell (4) being read at said second input (8) of the sense amplifier (7), characterized in that said precharging part (6) includes second switch means (17) activated in response to said reading signal (D) simultaneously with said first switch means (10) for connecting the bit line (1) to a voltage supply to precharge the bit line (1) at a precharge voltage value and means (24, 21, 20, 11) responsive to said precharge voltage value on said bit line (1) to cause deactivation of said first and second switch means (10, 17). Circuit in accordance with claim 1 characterized in that said bias part (5) comprises a cascode amplification stage (16) placed on the bit line (1). Circuit in accordance with claim 1 characterized in that said bias part (5) comprises current-mirror means (13, 14, 15) placed between the bit line (1) and the dummy bit line (2) to cause voltage unbalance between the two lines.

Inventors: GAIBOTTI MAURIZIO, SECOL MAURIZIO, GAIBOTTI, MAURIZIO, SECOL, MAURIZIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: G11C17
IPC codes: G11C16, G11C17