Improvement to digital filter sampling rate conversion method and device

Abstract: A digital filter providing output samples at a rate B while input samples are being provided at a rate A. The filter impulse response h(t) is sampled at a rate P = a.A = b.B, with P being the lowest common multiple to A and B, to derive Np filter coefficients (Ci) therefrom. Said coefficients are arranged into "a" sets of Np/a coefficients and stored. Output samples are then computed by feeding input samples Sn at incoming rate while permutating the sets of coefficients and generating output samples at said output rate.

Description: Field of Invention This invention deals with digital signal processing. Background of the Invention This invention deals more particularly with a method and device for digitally converting signal sampling rate from one given rate to another given rate. Conventional digital signal processing is achieved by sampling said signal, converting said samples into digital values and then performing mathematical operations over said digital values to achieve the desired processing. In many applications, one has to switch from one sampling rate to another in the course of the process. Assuming the rates are multiples to one another, up sampling may be achieved by interpolating in between consecutive samples, while down sampling would simply require regularly dropping samples. This process does not directly apply to systems wherein sampling rates ratio would not be an integer value or in other words the sampling rates would be relatively prime. On the other hand, an article by T.A. Ramstad: "Digital Methods for Conversion between Arbitrary Sampling Frequencies", published in IEEE Transactions on Acoustics, Speech and Signal Processing, vol. ASSP-32, no. 3, June 1984, pp 577 - 591, discusses in a rather general way possibilities for sampling rate conversion. The author acknowledging therein that for irrational rates ratio, "there will exist no periodic relation between the (filter) coefficients", proposes then to calculate new coefficients for each output sample. Another, rather straightforward solution would be achieved by converting the sampled signal back into the analog form and resampling it at proper rate. This solution would not only lack efficiency from a processing load standpoint, it might add to the coding error. Another method is disclosed in USP 4,460,890 wherein direct digital to digital conversion from a first sampling rate to a second sampling rate , not multiple to each other, is achieved using a rate multiplication means feeding an interpolating means. This solution is still considered rather complex and not cost optimized. Summary of the Invention One object of this invention is to provide a means for converting a sampled signal from one sampling rate to another within one single process. Another object is to provide a digital filter fed with input samples at a first rate and providing output samples at a second rate, by computing said output samples through permutations of filter coefficients sets in a predetermined order. The invention is set out in Claims 1 and 3. Further objects, characteristics and advantages of the present invention will be explained in more details in the following description with reference to the enclosed drawings which represent a preferred embodiment thereof. Brief Description of the Drawings Figures 1 and 3 are block diagrams of filters made according to the invention. Figure 2 is a flow chart of the filtering process operated with the device of figure 1. Description of Preferred Embodiment Even though the invention applies to any digital system wherein conversion is to be achieved between input and output sampling rates, the detailed description is given therein with reference to QAM-based digital modems and more particularly to digital filtering used within said modems. For details on said modems, one may refer to: A. Croisier and J.M. Pierret, "The Digital Echo Modulation", IEEE trans. Communication Technology, COM-18, pp 367-376 (1970). D. Godard and D. Pilost, "A 2400-Bits/s Microprocessor-Based Modem", IBM journal of Research and Development, Vol. 25, No.1, January 1981, pp 17-24. More particularly, assume a 19.2 Kbits/s modem is to operate at a symbol rate (baud rate) of 2742.85 symbols/s for transmitting and receiving 7 bits per symbol. Each symbol is selected within an (X,Y) represented constellation, and therefore is defined by two cartesian components an and bn. Conventional QAM modulation operations involve carrier modulating (= rotating) the symbol, then convolving (filtering) each selected and modulated symbol by a so called signal element impulse response. Said filter is a complex filter, but one may show that the system is fully defined by the real component r(t). For a modem operating at the 2472.85 symbols/s rate and assuming the filter impulse response be defined by six samples (coefficients) per baud time, then the filter clock should have a rate of 6 x 2742.85 = 16457.1 Hz. According to the conventional modem practice, the filter output is converted into analog form in a D/A converter and then filtered in a low cost analog low-pass filter prior to being fed to the transmission line. Naturally, the D/A clock should be rated at 16457.1 Hz. But assuming one wishes to use a D/A converter clocked at 14400 Hz, the filter output signal S(t) would need being resampled properly. Since 14400 and 16457 Hz or 2742.85 Hz are not multiple to each other, the sampling rate conversion operation cannot be achieved in a straightforward manner. One may interpolate input samples to achieve the rate conversion. But not only this solution means additional computing load which might affect the modem signal processor efficiency, it also affects the process precision by adding interpolation noise. A much improved solution to this rate conversion is proposed here, which, instead of focusing over the samples, focuses over the system transfer function. It combines both filtering and interpolation operations into one single operation, i.e. multi rate filtering or interpolating filtering. To that end, the filter impulse response h(t) is sampled at a rate higher than it should normally be; rate multiple of the symbols rate (A = 2742.85) and the D/A converter clock rate (B = 14 400). Optimal solution is provided by selecting said multiple to be equal to their lowest common multiple, i.e. P = 57.6 kHz since: P = a x A = b x B when a and b are integer values 57.6 = 21 x 2.74285 = 4 x 14.4 (NB= throughout this text, the symbol "." is used to designate a multiplication when no ambiguity may occur with decimals, in which case the multiplication symbol will be "x"). For an unchanged filter impulse response length (e.g. 12 symbols intervals long), the total number Np of filter coefficients would be: Said 252 coefficients are arranged into a = 21 sets, herein referenced Set(j) j=0 to 20 of 12 coefficients each. The multi-rate transmit filter is represented in Figure 1. It includes a 12 symbol cells long shift register wherein the symbols S(n) are fed at a rate 1/T = 2742.85 Hz. At the current time reference n, the delay line contains the samples Sn, Sn-1, Sn-2,... Sn-11. The symbol cells are provided with taps connected to multipliers (not shown), the second inputs of which is assigned a filter coefficient (i.e. filter impulse response sample, according to digital filtering theory). Said coefficients are spaced by T/21 over the impulse response and divided into 21 sets of 12 coefficients. The spacing between the subsequent sets is 4T/21 and corresponds to the output rate. The coefficient sets are used sequentially. They may be stored in a memory and fetched out when needed. The filter output sample X is computed according to the flow diagram of Figure 2. More particularly, when the process is started, i=0 and the first set of coefficients, i.e. Set(0) is fetched out of the storage (not shown). The first filtered sample X(n) is computed: X(n) = C0.Sn + C21.Sn-1 + ... + C231.Sn-11 New i value is computed: i = i+4 = 4 . Said i value being less than 21, the filter output sample computation is started again. X(n+1) = C4.Sn + C25.Sn-1 + ... + C235.Sn-11 i is again incremented to: i = i+4 = 8 X(n+2) = C8.Sn + C29.Sn-1 + ... + C239.Sn-11 i = i+4 = 12 X(n+3) = C12.Sn + C33.Sn-1 + ... + C243.Sn-11 i = i+4 = 16 X(n+4) = C16.Sn + C37.Sn-1 + ... + C247.Sn-11 i = i+4 = 20 X(n+5) = C20.Sn + C41.Sn-1 + ... + C251.Sn-11 i = i+4 = 24 being larger than 21, i is set to i-21 = 24 - 21 = 3 , a new baud time occurred, and a new filter input signal sample Sn+1 is fed into the filter delay line. The new filter output sample X(n+6) is computed: X(n+6) = C3.Sn+1 + C24.Sn + ... + C234.Sn-10 i = i + 4 = 7 X(n+7) = C7.Sn+1 + C28.Sn + ... + C238.Sn-10 i = i + 4 = 11 X(n+11) = C11.Sn+1 + C32.Sn + ... + C242.Sn-10 i = i + 4 = 15 X(n+15) = C15.Sn+1 + C36.Sn + ... + C246.Sn-10 i = i + 4 = 19 X(n+19) = C19.Sn+1 + C40.Sn + ... + C250.Sn-10 i = i + 4 = 23 > 21 i = i - 21 = 23 - 21 = 2 a new sample Xn+21 is computed. X(n+21) = C2.Sn+2 + C23.Sn+1 + ... + C233.Sn-9 and so on. The system keeps going on with switching among the filter sets of coefficients at 14 400 Hz rate (=21/4 T with 1/T = 2742.85 Hz) while keeping the filter input rate equal to the baud rate of 1/T = 2742.85 Hz. In other words, the rate conversion to be achieved, is combined with filtering operation by judiciously rotating the sets of filter coefficients at 14 400 Hz rate to compute a=21 filter output samples every b = 4 input samples. As may be seen from above, this implies 6 +5 +5 +5 = 21 output samples every 4 input samples. Therefore, the filter sets of coefficients are repetitively permutated in an order defined by: i new = (i old + b) modulo a meaning setting the next i value to (previous i + b) modulo "a" with i being initially set to the index of the first set of coefficients, i.e. i = 0. This may be expressed differently by stating that: i old + b = a . k + i new i being the previous coefficient set index, the above operation provides the number of shifts "k" to be applied to the shift register contents and the new set index (inew) for computing the new output sample. Thanks to this method, the filter input samples are fed into the filter shift register at their own incoming rate, while the output samples are computed by switching the filter coefficient sets at the required output rate. As mentioned, according to digital filtering theory, the filter coefficients are obtained by sampling the desired filter impulse response. The 252 coefficients may be computed accordingly by sampling the original impulse response at the rate of P = 57600 Hz. A slightly less precise result may be achieved by performing interpolation operations over the coefficients of a filter originally designed to operate at rate 16457, i.e. coefficients deriving from a filter impulse response sampled at rate 6/T. The rationale of this invention may be extended to apply to the modem receiver filter. The input samples derived from the received signal are fed into a receive (Hilbert) filter delay line at the rate of 21 samples per 4T which corresponds to a sampling frequency of 14400 Hz. The receive filter issues two complex symbols per time T (or 8 per 4T) which are then fed into a T/2-spaced equalizer delay line. The filter impulse response is sampled at a rate corresponding to the lowest common multiple of twice the symbol rate (2/T) and the A/D sampling frequency. Ft = K1 . (2/T) = K2 . (21/4T) with K1 and K2 being the lowest integer values verifying the above equation. Ft = 21 . (2/T) = 8 . (21/4T) = 42/T = 115,200 Hz Assuming the original impulse response was sampled to provide 54 coefficients over T/6 second, then, the number of coefficients for the multirate receive filter for the same length would be N p = 54 . (T/6) . (42/T) = 378 coefficients These coefficients are divided into 8 sets of coefficients corresponding to the 8 symbols generated per 4T. The number of coefficients is reduced to N' p = 376 coefficients or 8 sets of 47 coefficients, namely: A block diagram representation of the receive filter is shown in Figure 3. The incoming samples are fed into a 47 samples long delay line. After 4T, the sample Sn has been shifted by 21 positions and is stored into Sn-21. The different sets of 47 coefficients each, numbered Set(0) to Set(7), are stored in a memory (not shown). They are used in a specific order such that: New set number = (old set number + 21) modulo 8. In addition, before each output sample computation, the delay line contents is shifted by a number of samples given by the quotient of the division of the new index by 8. Old set number+21 = (8 . number of shifts)+New set Number In other words, assuming the previous set number be i, then i+21 = 8k+n,then, the new set reference number should equal to n and the number of shifts equals to k. For instance, lets assume the process starts with feeding the Sn input sample into the filter delay line. The output samples are computed and provided as follows: X(0) = Set(0) . (Sn, Sn-1, Sn-2, ..., Sn-46) i+21 = 21 = 8 . 2 + 5 New Set number = 5 Set(5) is selected. Number of shifts = 2. Therefore, no output sample is computed when Sn+1 is fed into the filter delay line. Next sample computation X occurs with Sn+2 arrival. X(1) = Set(5) . (Sn+2, Sn+1, Sn, ..., Sn-44) i+21 = 26 = 3 . 8 + 2 New Set number = 2 Set(2) is selected. Number of shifts = 3 X(2) = Set(2) . (Sn+5, Sn+4, Sn+3, Sn+2 ..., Sn-41) i+21 = 23 = 2.8+7 New Set to select = S(7) Number of shifts = 2 X(3) = Set(7) . (Sn+7, Sn+6, ..., Sn-39) i+21 = 28 = 3.8+4 X(4) = Set(4) . (Sn+10, Sn+9, ..., Sn-36) i+21 = 25 = 3.8+1 X(5) = Set(1) . (Sn+13, Sn+12, ..., Sn-33) i+21 = 22 = 2.8+6 X(6) = Set(6) . (Sn+15, Sn+14, ..., Sn-31) i+21 = 27 = 3.8+3 X(7) = Set(3) . (Sn+18, Sn+17, ..., Sn-28) i+21 = 24 = 3.8+0 The process starts rescanning the coefficients sets, i.e. Set(0), Set(5), Set(2), Set(7), Set(4), Set(1), Set(6), Set(4), etc... In summary, the algorithm may be expressed by: i old + 21 = 8 . k + i new For twenty one input samples, the filter provides eight output samples using the eight sets of coefficients Set(0) through Set(7) in a fixed order defined by the above equation.

Claims: A process for performing a digital signal filtering function with a filter impulse response h(t), while operating a rate conversion for providing the filtered output samples at a rate B while the filter is being fed at an input rate A, with A and B relatively prime, said process including: deriving Np filter coefficients C(i), i=0, 1, ..., Np-1, by sampling said impulse response h(t) at a rate P, with: P = a.A = b.B, wherein "a" and "b" are integer values selected such that P be the lowest multiple value of both A and B; splitting said Np coefficients into "a" sets, referenced Set(i) with i = 0, 1, ..., a-1, each set including N'p/a coefficients with N'p being substantially equal to Np, each set including the coefficients {C(i), C(i+A), C(i+2.A),.... C(i+N.a)}, N being an integer, and storing said sets of coefficients; computing "a" output samples while "b" input samples are being fed into the filter, each output sample computation involving using one Set(i), i being repetitively permutated in such a manner that each new set index inew be derived from the previous set index iold from: i new = (i old + b) modulo a . A process according to claim 1 wherein said filter input rate A is higher than the output rate B, whereby each output sample computation involves shifting the input samples k positions into said filter , with k being the quotient of the division of "a" plus the previous coefficient set index, by "b". A digital filter having a predefined impulse response h(t) for filtering an input signal sampled at a rate A into a filtered output signal sampled at a rate B, A and B being relatively prime, said filter including shift register means provided with N tap means, a set of N multiplier means having one input connected to one of said taps respectively, adding means connected to said multiplier means, and storage means for storing filter coefficients to be respectively applied to a second input of said multiplier means, said filter being characterized in that it includes: means for sampling h(t) at a rate substantially equal to the lowest common multiple P of A and B, i.e. P = a.A = b.B , wherein a and b are integer values, and deriving therefrom a number Np of filter coefficients C(j) with j = 0, 1 ..., Np-1; means for arranging a number N'p of said coefficients, N'p being substantially equal to Np, into "a" sets of coefficients, Set(i), i = 0, 1, ..., (a-1), with Set(i) including { Ci, C(i+a), C(i+2a), ..., C(i+N.a) }, N being an integer; means for feeding said input signal samples into said shift register means at said input rate; and, means for fetching said sets of filter coefficients in a predetermined permutated order defined by i new = (i old + b) modulo a, with i being initially set to zero, and applying said coefficients to said multiplier means respectively at a rate B; means for feeding said multipliers outputs into said adding means; whereby the output samples are being generated at the output of said adding means at said rate B.

Inventors: BELLOC JACQUES, GALAND CLAUDE, LANCON EMMANUEL, MILEWSKI ANDRE, QUINTIN MICHEL, BELLOC, JACQUES, GALAND, CLAUDE, LANCON, EMMANUEL, MILEWSKI, ANDRE, QUINTIN, MICHEL, Milewski, André
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H03H17
IPC codes: H03H17