CCD VIDEO CAMERA

Abstract: An output signal processing circuit for a CCD register, for example a horizontal output register of a CCD imager is provided. The CCD register includes an output precharge circuit with a capacitance, the voltage across the capacitance is supplied to an output terminal of the CCD register and has first, second and third durations repeatedly. The first duration is a precharge duration, the second duration is a reference duration and the third duraiton is a signal duration. The output signal processing circuit includes a clamp circuit(3) for clamping the output signal at the output terminal of the CCD in such a manner that the voltage of the reference duration becomes a stable clamp voltage, clip circuit (8) for clipping the output signal of the clamp circuit such that the voltage of the precharge duration is clipped to a clip level, and a low-pass filter (11)suppliedwith the output of the clip circuit(8) for generating the transferred signal.

Description: The present invention relates to a CCD viedeo camera. A CCD video camera having the features according to the preamble of claim 1 is known from JP-A-62-213 484 A similar known apparatus will now be explained based on Figs. 1-3. A solid-state image pickup apparatus comprising charge transfer device such as charge coupled device (CCD) has a photo-sensitive part to perform photoelectric conversion, a charge transfer part to transfer the signal charge obtained in the photo-sensitive part, and an output part for delivering an output signal based on the transferred signal charge. In an interline transfer system, for example, the signal charge from each photoelectric cell is transferred via a transfer gate to a light-shielded vertical register, and the signal charges are sent out sequentially from the vertical registers to light-shielded horizontal registers, so that an image pickup signal is obtained via an output circuit of a CCD register connected to the horizontal registers. The conventional output circuit of a CCD register known heretofore has a constitution shown in Fig. 1. Denoted by 31 and 33 in this circuit diagram are a horizontal register and a horizontal output gate, respectively, The horizontal register 31 is supplied with, for example, two-phase clock pulses 1 and 2 from terminals 32A and 32B respectively. Meanwhile the horizontal output gate 33 is supplied with a bias voltage of a predetermined level from a terminal 34. The drain-source of a field effect transistor 36 constituting a floating diffusion amplifier is inserted between the horizontal output gate 33 and a power supply terminal 35, and a capacitor 38 is formed equivalently between the horizontal output gate 33 and the ground. A precharge pulse P p synchronized with the transfer clock pulses 1 and 2 is supplied from a terminal 37 connected to the gate of the field effect transistor 36. The image pickup output signal obtained at the junction of the source of the field effect transistor 36 and the capacitor 38 is delivered to an output terminal 42 via a two-stage source follower circuit which consists of field effect transistors 39 and 40, and an emitter follower circuit consisting of a bipolar transistor 41. Fig. 2 graphically shows the relationship among the two-phase transfer clock pulses 1 and 2, the precharge pulse P p , and the output voltage Vo produced at one terminal of the capacitor 38. Fig. 3A shows the electrode structure of the output circuit of Fig. 1, and Figs. 3B, 3C and 3D show the potentials at different instants t1, t2 and t3 in Fig. 2 respectively. As is obvious from Fig. 3A, the horizontal register 31 has such an electrode structure as to transfer the signal charges Sn, Sn+1 and so forth rightward from the left hand in accordance with the two-phase clock pulses. The field effect transistor 36 has a floating diffusion region 43, a precharge gate 44 and a precharge drain 45 which correspond respectively to the source, gate and drain of the transistor 36 shown in Fig. 1. Referring now to Figs. 2 and 3, a description will be given below on how a CCD output signal is taken out. First, the field effect transistor 36 is turned on during the precharge time Tp in which a precharge pulse Pp is supplied to the gate of the field effect transistor 36 in a state where the pulse 1 is at a high level while the pulse 2 is at a low level. The relationship among the individual potentials at the instant (t = t1) within the precharge time Tp is such that, as shown in Fig. 3B, the potential of the precharge gate 44 is low. When the field effect transistor 36 is turned on, the capacitor 38 is charged immediately by the supply voltage Vb impressed to the terminal 35. And simultaneously the precharge pulse Pp fed to the gate of the field effect transistor 36 appears at the source side thereof through the parasitic capacitance formed substantially between the gate and source of the field effect transistor 36. Consequently, at one terminal of the capacitor 38, there is generated an output voltage Vo where the voltage Vp of the precharge pulse P1 is superimposed on the supply voltage Vb. The precharge time Tp is followed by a reference potential time To which is immediately before the charge transfer from the horizontal register 31 to the output circuit. In this referential potential time To during which the precharge pulse Pp is at a low level, the field effect transistor 36 is kept in its off-stage. Accordingly the output voltage Vo at one terminal of the capacitor 38 is lowered, in comparison with the value during the precharge time To, by the voltage Vp of the precharge pulse Pp to consequently become equal to the supply voltage (reference level) Vb. At the instant (t = t2) in the reference potential time To, as shown in Fig. 3C, the potential of the precharge gate 44 is raised while the potential of the floating diffusion region 43 is rendered equal to the reference potential. Next to the reference potential time To is a transfer time Tt during which the pulse 1 is at a low level and the pulse 2 at a high level. In the transfer time Tt, there is obtained an output voltage Vo of the data signal voltage Vs corresponding to the signal charge Sn transferred from the horizontal register 31. The individual potentials at the instant (t = t3) in the transfer time Tt are such as those shown in Fig. 3D. Thus, the signal charge Sn is transferred to the floating diffusion region 43. When the output voltage Vo is delivered as described above, the charge in the source-drain region (precharge gate region 44) of the field effect transistor 36 is moved between the floating diffusion region 43 and the precharge drain region 45 in the precharge time Tp (Fig. 3D), so that the potential of the floating diffusion region is forcibly equalized to the potential of the precharge drain region 45 and is thereby maintained in a stable state. When treating CCD signals in different channels, each channel being associated to one of a plurality of horizontal shift registers, problems may arise from this treatment of signals not in a single but in a plurality of channels. A CCD image pickup device having a plurality of horizontal shift registers is known from DE-A-3 520 222. It is the object of the present invention to provide a CCD video camera outputting reliable signals even though input signals are treated not in a single but in plurality of channels. This object is solved by a camera having either the features of claim 1 or the features of claim 2. The idea common to both solutions is that each channel comprises a selective delay means for delaying the signals in the different channels in a manner to prevent overlap between the signals, and to use means to adjust the signals from the different channels in a manner that they have the same output value in case of an extreme input value, be it either the white level or the black level. It has to be noted that in one of the plurality of channels the selective delay means may be no special device but that this channel may only show a normal delay which is established by the normal signal running time. However, in all other channels the selective delay means provides for an additional signal delay. These objects, features and advantages of the present invention will become apparent from the following detailed description of a preferred embodiment to be taken in conjunction with the accompanying drawings. Fig. 1 is a circuit diagram of a general CCD output circuit; Fig. 2 is a waveform chart for explaining the operation in the circuit of Fig. 1; Fig. 3 shows the configuration of and the potentials in the circuit of Fig. 1 for explaining the operation performed therein; Fig. 4 is a block diagram of an embodiment according to the present invention; Fig. 5 shows the constitution of a solid-state image pickup device employed in the embodiment of Fig. 4; and Figs. 6, 7 and 8 show signal waveforms for explaining the operation in the embodiment of Fig. 4. Hereinafter a description will be given on an embodiment of the present invention applied to a CCD video camera having a plurality of horizontal registers. In this embodiment, as shown in Fig. 4, there is employed a solid-state image pickup device of interline transfer system having, for example, four horizontal registers 104a, 104b, 104c and 104d. In Fig. 5 denoted by 101 is a p-type silicon substrate, and photo-sensitive elements 102a, 102b, 102c ... consisting of photodiodes are arranged into a matrix on the surface of the p-type silicon substrate 101. Although simplified in Fig. 5, a multiplicity of such photo-sensitive elements 102a, 102b, 102c ... are arrayed to form a matrix of 2000 x 1000 in an example of high-definition (HD) television color camera. And light-shielded vertical registers 103a, 103b, 103c ... are disposed in the proximity of the photo-sensitive elements 102a, 102b, 102c and so forth. And four horizontal registers 104a, 104b, 104c and 104d are provided in connection with the vertical registers 103a, 103b, 103c and so forth. Four of such vertical registers 103a, 103b, 103c ... are selectively connected to the horizontal registers 104a, 104b, 104c and 104d. Suppose now that, for the purpose of simplifying the explanation, eight vertical registers 103a, 103b, 103c ... are provided in all. In this example, the 1st vertical register 103a and the 5th vertical register 103e are connected to the horizontal register 104a; the 2nd vertical register 103b and the 6th vertical register 103f are connected to the horizontal register 104b; the vertical registers 103c and 103g to the horizontal register 104c; and the vertical registers 103d and 103h to the horizontal register 104d, respectively. During the vertical blanking interval, signal charges are read out from the photo-sensitive elements 102a, 102b, 102c ... to the vertical registers 103a, 103b, 103c ... in response to a gate pulse sv. The signal charges are transferred to the vertical registers 103a, 103b, 103c ... by four-phase clock pulses V1, V2, V3 and V4, and then are inputted into the horizontal registers 104a, 104b, 104c and 104d during the horizontal blanking interval. Two-phase transfer clock pulses H1 and H2 are fed to the horizontal registers 104a, 104b, 104c and 104d so that, during the horizontal video interval, the signal charges are read out from the horizontal registers 104a, 104b, 104c and 104d. The signal charges thus obtained from the horizontal registers 104a, 104b, 104c and 104d are supplied to output amplifiers 105a, 105b, 105c and 105d and then are taken out in the form of video signal voltages from output terminals 106a, 106b, 106c and 106d. The output amplifiers 105a, 105b, 105c and 105d consist of, for example, floating diffusion amplifiers and source follower transistors. Fig. 6A typically shows the signal voltage taken out from the output terminal 106a. Similarly, Figs. 6B, 6C and 6D typically show the signal voltages taken out from the output terminals 106b, 106c and 106d, respectively. Signal voltages S2a and S2e corresponding respectively to the photo-sensitive elements 102a and 102e are obtained from the output terminal 106a correspondingly to the signal charges obtained from the photo-sensitive elements 102a to 102h in Fig. 5. Similarly, signal voltages S2b and S2f corresponding to the photo-sensitive elements 102b and 102f are obtained from the output terminal 106b; signal voltages S2c and S2g corresponding to the photo-sensitive elements 102c and 102g are obtained from the output terminal 106c; and signal voltages S2d and S2h corresponding to the photo-sensitive elements 102d and 102h are obtained from the output terminal 106d. The output signals of such four horizontal registers 104a, 104b, 104c and 104d are combined with one another by a non-additive mixer, as will be described later, to become a video output signal shown in Fig. 6E. As is understood from the above description, due to the provision of N pieces of horizontal output registers, the signal charge transfer frequency in the horizontal registers is reduced to 1/N. Consequently, in a color camera for high-definition television where the number of pixels is great, the signal charges can be read out with more facility in comparison with the foregoing case of employing a single horizontal register. Now the above embodiment will be mentioned in further detail with reference to Fig. 4. An amplifier 110a, a variable-gain amplifier 110b, a variable-gain amplifier 110c and a variable-gain amplifier 110d are connected respectively to the output terminals 106a, 106b, 106c and 106d of the solid-state image pickup device having four horizontal registers as described. The variable-gain amplifiers 110b, 110c and 110d are provided to compensate for the gain dispersions resulting from the differences among the capacities of the respective floating diffusion regions in the output amplifiers 105a, 105b, 105c and 105d, as will be described later. The output signal SV₀ of the amplifier 110a is supplied to a clamp circuit 111a enclosed with a broken line. The clamp circuit 111a comprises a capacitor 112 inserted in series to the signal path, a switching element 113 inserted between one end of the capacitor 112 and the ground, and a fixed voltage source 114a for generating a clamp voltage. The output signals of the variable gain amplifiers 110b, 110c and 110d are supplied respectively to clamp circuits 111b, 111c and 111d enclosed with dotted lines. Such clamp circuits 111b, 111c and 111d each comprises a capacitor 112 and a switching element 113 in the same manner as the aforesaid clamp circuit 111a, and also variable voltage sources 114b, 114c and 114d, respectively. As will be described later, the variable voltage sources 114b, 114c and 114d are provided for correcting the black level dispersions. The switching elements 113 of the clamp circuits 111a to 111d are controlled by clamp pulses Pc fed from a terminal 115. An output signal SV1 of the clamp circuit 111a is supplied via a clip circuit 140a to a non-additive mixer 119. Meanwhile an output signal of the clamp circuit 111b is supplied via a clip circuit 140b to a delay circuit 116, whose output signal SV2 is then supplied to the non-additive mixer 119. An output signal of the clamp circuit 111c is supplied via a clip circuit 140c to a delay circuit 117, whose output signal SV3 is then supplied to the non-additive mixer 119. And an output signal of the clamp circuit 111d is supplied via a clip circuit 140d to a delay circuit 118, whose output signal SV4 is then supplied also to the non-additive mixer 119. Such clip circuits 140a to 140d are provided for removing the precharge pulse components contained in the respective output signals of the clamp circuits. The delay circuit 116 has a delay of T/4, in which T represents the transfer period of the information signal voltage in the output signal obtained from one horizontal register of the solid-state image pickup device. Meanwhile the delay circuit 117 has a delay of T/2, and the delay circuit 118 has a delay of 3T/4. The non-additive mixer 119 outputs the minimal level out of the four input signals SV1, SV2, SV3 and SV4. An exemplary circuit configuration of the non-additive mixer 119 is such that emitters of four pnp-type transistors are connected to a common constant current source while collectors thereof are connected in common to one another, and the output is obtained from the common junction of the emitters. The combined information signal SV5 from the non-additive mixer 119 is delivered via an amplifier 120 to an output terminal 121. When a precharge pulse Pp shown in Fig. 7A is supplied to the floating diffusion amplifiers 105a, 105b, 105c and 105d, the floating diffusion amplifier 105a, for example, produces an output signal SV0 shown in Fig. 7B. The operation performed in this case is the same as described previously with reference to Fig. 2. A clamp pulse Pc supplied to the clamp circuits 111a to 111d becomes a high level during the reference potential time To as shown in Fig. 7C, and the switching element 113 is turned on during the high-level time of the clamp pulse Pc. And the level (feed-through level) during the reference potential time To is clamped to a predetermined clamp voltage by the clamp circuit 111a. Consequently, as shown in Fig. 7D, the output signal SV1 of the clamp circuit 111a contains none of the reset noises Δn, Δn+1 and so forth due to the removal thereof. The above operation of removing such reset noises is performed also by the other clamp circuits 111b, 111c and 111d. Since the output signal of the clamp circuit 111b is fed via the delay circuit 116, it becomes a signal SV2 having a delay of T/4 from the signal SV1 as shown in Fig. 7E. Similarly, the output signal of the clamp circuit 111c fed via the delay circuit 117 becomes a signal SV3 having a delay of T/2 from the signal SV1 as shown in Fig. 7F. Meanwhile the output signal of the clamp circuit 111d fed via the delay circuit 118 becomes a signal SV4 having a delay of 3T/4 from the signal SV1 as shown in Fig. 7G. Such CCD output signals SV1, SV2, SV3 and SV4 are supplied to the non-additive mixer 119, so that the great amplitude portions thereof during the precharge time Tp are removed and are therefore not existent in the output signal SV5 of the mixer 119 as shown in Fig. 7H. And the information signal voltages Sa1, Sb1, Sc1, Sd1 and so forth are rendered continuous with the period T/4. Accordingly, the output signals of the four horizontal registers 104a, 104b, 104c and 104d are combined with one another by the non-additive mixer 119 to form an image pickup signal of one channel. Sample-and-hold circuits 123a, 123b, 123c and 123d are connected via a switch 122 to the output terminal of the amplifier 120 supplied with the output signal of the non-additive mixer 119. The sample-and-hold circuits 123a to 123d are supplied with sampling pulses a, b, c and d respectively. Comparative amplifiers 124, 125 and 126 are provided for detecting the gain difference or black level difference between one signal channel as a reference and each of the other three signal channels. The signal channel including the amplifier 110a is selected as the reference signal channel. Therefore the output signal of the sample-and-hold circuit 123a is supplied to one input terminal of each of the comparative amplifiers 124, 125 and 126, while the output signals of the sample-and-hold circuits 123b, 123c and 123d are supplied to the other input terminals of the comparative amplifiers 124, 125 and 126, respectively. The error signals outputted from the comparative amplifiers 124, 125 and 126 are supplied to averaging circuits 127, 128 and 129, respectively. The averaging circuits 127, 128 and 129 serve to smoothen the error signals in one field duration, and a vertical synchronizing signal is supplied from a terminal 130 to such averaging circuits 127, 128 and 129. The error signals thus averaged by the circuits 127, 128 and 129 are stored in a memory 131. Although an analog memory is employed as the memory 131 in the example shown in Fig. 4, it may be replaced with a digital memory as well. However, in the case of using a digital memory, an A-D converter is required for converting into a digital signal the error signal which is to be written in the memory 131, and further a D-A converter is also required for converting into an analog error signal the digital signal read out from the memory 131. The memory 131 comprises memory portions 132b and 133b for storing the error signal obtained from the averaging circuit 127, memory portions 132c and 133c for storing the error signal from the averaging circuit 128, and memory portions 132d and 133d for storing the error signal from the averaging circuit 129. And a switch 134 is provided in relation to the memory 131. The error signal relative to the gain is stored in the memory portions 132b, 132c and 132c, while the error signal relative to the black level is stored in the memory portions 133b, 133c and 133d. The error signals read out from the memory portions 132b, 132c and 132d respectively are supplied as gain control signals to the variable gain amplifiers 110b, 110c and 110d, whereby the gain of the signal channel including the amplifier 110a is equalized to the gain of the other three signal channels. The error signals read out from the memory portions 133b, 133c and 133d respectively are supplied as control signals to the variable voltage sources 114b, 114c and 114d. Then the values of clamp voltages are controlled by the variable voltage sources 114b, 114c and 114d respectively, whereby the black levels are so controlled as to be equalized among the four channels. The switch 134 is provided for selecting a gain adjustment mode or a black level adjustment mode. For example, the switch 134 is turned on to select the black level adjustment mode. In the gain adjustment mode, the image of an entirely white subject is picked up by a color camera, and the CCD output signal is introduced via the on-state switch 122 to the sample-and-hold circuits 123a to 123d. As shown in Fig. 8A, the level of the CCD output signal produced in picking up the image of the entirely white subject fails to be uniform among the four signal channels due to the existence of gain dispersions. Sampling pulses a, b, c and d of Fig. 8B are supplied respectively to the sample-and-hold circuits 123a to 123d, which then detect the individual white levels of the four signal channels. The output signals of the sample-and-hold circuits 123a to 123d are supplied to the comparative amplifiers 124, 125 and 126, so that the level difference is detected between the output signal of the sample-and-hold circuit 123a and that of each of the sample-and-hold circuits 123b, 123c and 123d. The one-field average values of the output signals of the comparative amplifiers 124, 125 and 126 are written in the memory portions 132b, 132c and 132d of the memory 131. The switch 122 is turned off upon completion of the setting operation, and the error signals read out from the memory portions 132b, 132c and 132d respectively are supplied as control signals to the variable gain amplifiers 110b, 110c and 110d. Then the gains in the individual channels are equalized to one another by the variable gain amplifiers 110b, 110c and 110d. Consequently, if the image of the entirely white subject is picked up after completion of the setting operation, the output signal levels in the individual channels are equalized to one another. In the black level adjustment mode, the iris diaphragm of the color camera is completely closed, and the switches 122 and 134 are both turned on. Then the black levels are detected and compared as in the aforementioned gain adjustment mode, and the error signals are written in the memory portions 133b, 133c and 133d of the memory 131. Subsequently the variable voltage sources 114b, 114c and 114d are controlled in accordance with the error signals read out from the memory 131, so that the black levels in the four channels are rendered coincident with one another. Once the setting is so carried out as to eliminate the differences among the gains or black levels in the individual channels, substantially no variation occurs thereafter except the secular change in the circuit. Consequently, the gain or clamp voltage is controllable by manually adjusting a variable resistor or the like, and adjustment may be so executed as to render the levels in the individual channels coincident with one another while measuring the CCD output signal obtained from the output terminal 121. It is generally customary that such presetting adjustment is carried out when the product is shipped from the factory.

Claims: A CCD video camera comprising: a solid-state image pickup device of charge coupled or CCD type including photo-sensitive elements (102) arranged into a matrix, a plurality of vertical shift registers (103) for shifting charges generated in said photosensitive elements in vertical direction; a channel comprising: a horizontal shift register (104) for shifting the charges from the selected one of said vertical shift registers in the horizontal direction and generating a pulsed video information signal (SV0) having a precharge duration (Tp), a reference duration (To) and a signal duration (Tt) repeatedly; and an output signal processing circuit connected to said horizontal shift register and including a clamp circuit (111) for clamping said pulsed video information signal in such a manner that the voltage of said reference duration becomes a stable clamp voltage; characterized in that a plurality of said channels is provided, each channel further comprising selective delay means (116 - 118) supplied with the output of the clamp circuit for selectively delaying the output signal of the same so that the delay imparted to the individual output (SV1, .., SV4) of each of said clamp circuits of the different channels becomes different from one another; and a white level detecting means (132 b-d) for detecting the white level of said pulsed video information signals, and gain controlled amplifier means (110 b-d) connected between the output of said horizontal shift register (104) and the input of said clamp circuit (111) and controlled by the output signal of said white level detecting means in such a manner that the white levels of said pulsed video information signals become equal to one another for the different channels; and in that a non-additive mixing circuit means (119) is provided which is supplied with the output signal (SV1, .., SV4) of said selective delay means of each channel for generating the video information signal (SV5). A CCD video camera comprising: a solid-state image pickup device of charge coupled or CCD type including photo-sensitive elements (102) arranged into a matrix, a plurality of vertical shift registers (103) for shifting charges generated in said photosensitive elements in vertical direction; a channel comprising: a horizontal shift register (104) for shifting the charges from the selected one of said vertical shift registers in the horizontal direction and generating a pulsed video information signal having a precharge duration, a reference duration and a signal duration repeatedly; and an output signal processing circuit connected to said horizontal shift register and including a clamp circuit (111) for clamping said pulsed video information signal in such a manner that the voltage of said reference duration becomes a stable clamp voltage; characterized in that a plurality of said channels is provided, each channel further comprising selective delay means (116 - 118) supplied with the output of the clamp circuit for selectively delaying the output signal of the same so that the delay imparted to the individual output (SV1, .., SV4) of each of said clamp circuits of the different channels becomes different from one another; and a black level detecting means (133 b-d) for detecting the black level of said pulsed video information signals, and for generating control output signals for controlling the clamp voltage of said clamp circuit (111) in such a manner that the black levels of said pulsed video information signals become equal to one another for the different channels, and in that a non-additive mixing circuit means (119) is provided which is supplied with the output signal of said selective delay means of each channel for generating the video information signal.

Inventors: ASAIDA, TAKASHI, YAMAMOTO, ISAMU
Applicants: SONY CORPORATION
Application year: 1988
Main classification: G11C27
IPC codes: G11C27, H01L29, H04N5, G11C19, H01L21