EMITTER COUPLED LOGIC CIRCUIT

Abstract: An emitter coupled logic circuit includes variable impedance circuit (20) which is connected to at least one of two output terminals of the ECL circuit for variably providing an impedance connected to the one output terminal. An impedance to be provided when both the levels of the two outputs are at a high-level is set to be smaller than an impedance to be provided when at least one of the two outputs is at a low-level.

Description: The present invention generally relates to an emitter coupled logic circuit, and in particular to an emitter coupled logic circuit capable of driving a load capacitor having a large capacitance. An emitter coupled logic circuit (hereafter simply referred to as an ECL circuit) is used in order to speed up the operation of a logic circuit. A transistor of the ECL circuit is not driven up to a saturated state, and is switched between an active state and a cut-off state. In the case where the ECL circuit drives a load capacitance having a large capacitance, the operation of the ECL circuit is delayed. Therefore, it is desirable to speed up the operation of the ECL circuit. It is well known that a load capacitance coupled with an output terminal of the ECL circuit increases as the integration density of a semiconductor integrated circuit which implements the ECL circuit increases. This is because a wiring pattern formed on a semiconductor chip is apt to be lengthened as the integration density increases. When a potential of the output terminal of the ECL circuit is switched from a high-level (hereafter simply referred to as "H") to a low-level (hereafter simply referred to as "L"), a charge stored in the load capacitance is discharged by a load impedance which is coupled with the output terminal. Therefore as the load impedance is reduced, a time necessary for the potential at the output terminal to completely reach "L" can be reduced. Such a time is referred to as a fall time. However, as the load impedance decreases, the power consumed in the ECL circuit increases. It is to be noted that the load impedance cannot be allowed to exceed a predetermined value because there is a limit with respect to the total power consumption in the integrated circuit. For this reason, the time necessary for the potential at the output terminal of the ECL circuit to be switched to "L" (the fall time) cannot be effectively shortened. Another ECL circuit has been proposed in US-A 4,539,493. This proposed ECL circuit employs an emitter follower circuit and utilizes a fact that when the output of the ECL circuit is switched from "H" to "L", a reverse logic output is switched from "L" to "H". The level change of the reverse logic output is supplied to a base of the emitter follower transistor through a capacitive coupling. Thereby the base level of the emitter follower transistor is increased, so that the change from "H" to "L" can be made faster. However, the operating speed of the proposed ECL circuit still depends on the magnitude of the load capacitance. A similar ECL circuit is disclosed in US-A 4,276,485, and has a similar disadvantage. Therefore, it is desirable to provide an emitter coupled logic circuit in which the above disadvantages of the conventional ECL circuits are reduced or eliminated. It is also desirable to provide an emitter coupled logic circuit in which the fall time can be reduced with minimum power increase in the ECL circuit. JP-A-61-16621 by Hitachi discloses an ECL circuit with a single output terminal connected to a variable impedance circuit, in accordance with the preamble of accompanying claim 1. According to the present invention, there is provided an emitter coupled logic circuit comprising a plurality of transistors constituting current switches for receiving input signals and outputting at least a first output signal, emitters of the plurality of transistors being mutually connected; a first emitter follower means for extracting the first output signal and supplying it to a first output terminal; and variable impedance means connected between a negative power source line and at least the first output terminal for variably providing an impedance to be coupled with that output terminal; characterised in that a second emitter follower means is provided for extracting a second output signal complementary to the first output signal; and in that said variable impedance means is arranged to provide a lower impedance when both the first and second output signals are at a high level, than when either output signal is at a low level. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a circuit diagram of a conventional ECL circuit; Fig. 2 is a circuit diagram for explaining the principle of the present invention; Fig. 3 is a circuit diagram of a preferred circuit structure of a variable impedance circuit shown in Fig. 2; Fig. 4 is a circuit diagram of a modification of the variable impedance circuit; Fig.5 is a circuit diagram of another modification of the variable impedance circuit; Fig. 6 is a circuit diagram of an application of the present invention; and Figs. 7(A) and 7(B) are views showing waveforms at portions of the circuit shown in Fig. 6. To facilitate the understanding of the present invention, a description is first given of a conventional ECL circuit with reference to FIG.1. Referring to FIG.1, transistors Q1 and Q2 constitute a current switch together with a transistor Q3. Emitters of the transistors Q1, Q2 and Q3 are mutually connected, and also to a constant current source 11. Inputs A and B are supplied to bases of the transistors Q1 and Q2, respectively, and a reference potential V REF is applied .to a base. An emitter follower transistor Q4 is connected to a collector of the transistor Q3. An emitter of the transistor Q4 is connected to an output terminal of the ECL circuit. An output A+B which is a result of an OR operation is obtained at the output terminal 10. A reverse logic output A+B is obtained at an emitter of a transistor Q5, which is connected to a constant current source 12. A reference label V CC denotes a positive power source voltage (a ground level in the illustrated example), and a reference V EE denotes a negative power source voltage. As described before, a capacitance of a load capacitor C L coupled between the output terminal 10 and the ground increases as the integration density of an integrated circuit which implements the illustrated ECL circuit increases. This is because a wiring pattern in the ECL circuit is lengthened. When the potential at the output terminal 10 is switched from "H" to L", a capacitance stored in the load capacitor C L is discharged through a load impedance Z. A fall time of the potential at the output terminal 10 can be decreased if the load impedance Z is reduced. However, as the load impedance Z decreases, the power consumed in the ECL circuit increases. It is to be noted that the load impedance Z cannot be allowed to lessen a predetermined value because there is a limit on the total consumed power in the integrated circuit. For this reason, the time necessary for the potential at the output terminal of the ECL circuit to be switched to "L" (the fall time) cannot be satisfactorily shortened. The present invention is directed to overcoming the above disadvantage of the conventional ECL circuit. FIG.2 is a circuit diagram for explaining the principle of the present invention. In FIG.2, the same elements as those in FIG.1 are indicated by the same references. The emitters of the transistors Q1, Q2 and Q3 are mutually connected, and one current switch is constituted by the transistors Q1, Q2 and Q3. The output of the current switch is extracted by the emitter follower transistor Q4 and is then applied to the output terminal 10. A variable impedance circuit 20 is connected between the output terminal 10 and the negative power source voltage -V EE . The variable impedance circuit 20 can provide two different impedances, depending on a level of the output obtained at the output terminal 10 and the reverse logic output obtained at the emitter of the transistor Q5. An impedance which is provided by the variable impedance circuit 20 when both the outputs are set at "H", is made smaller than an impedance which is provided by the variable impedance circuit when either one of the output signals is at "L". Therefore, it becomes possible to rapidly discharge the charge stored in the load capacitor C L when the potential at the output terminal 10, or the output signal is switched from "H" to "L". In detail, when the potentials at the output terminal 10 and the emitter of the transistor Q5 are both at "H", that is, when the fall of the potential at the output terminal 10 is delayed due to the load capacitor C L , the impedance provided by the variable impedance circuit 20 is decreased, so that the charge stored in the load capacitor C L can be rapidly discharged through the circuit 20. On the other hand, when either one of the potentials at the output terminal 10 and the emitter of the transistor Q5 is kept at "L" (this state is referred to as a stationary state), the impedance provided by the variable impedance circuit 20 is increased, so that the power consumed in the whole of the ECL circuit can be reduced. FIG.3 shows a detailed configuration of one example of the variable impedance circuit provided by a preferred embodiment of the present invention. Referring to FIG.3, transistors Q11, Q12 are paired by connecting emitters thereof to each other, and thereby constitutes a current switch. The transistors Q13 and Q14 are paired by connecting emitters thereof to each other, and thereby constitutes a current switch. Collectors of the transistors Q11 and Q13 are connected to the emitter of the transistor Q4 shown in FIG.2 through a terminal 21. Terminals 22 and 23 are connected to the emitters of the transistors Q4 and Q5, respectively. Collectors of the transistors Q12 and Q14 are connected to a base of a transistor Q15 and also to a terminal 24 through a resistor R C . The positive power source voltage V CC set at the ground level is applied to the terminal 24. Bases of the transistors Q12 and Q14 are connected to a terminal 25, to which a reference voltage V BB is applied. The reference voltage V BB is a constant voltage between "H" and "L" which are obtained at the output terminal. Emitters of the transistors Q11 and Q12 are connected to the first collector of a transistor Q16 which serves as a constant current source, and emitters of the transistors Q13 and Q14 are connected to the second collector of the transistor Q16. A collector of the transistor Q15 is connected to the terminal 24, and an emitter of the transistor thereof is connected, through a level shift diode D1, a resistor R F and a diode D2, to a terminal 26. The negative power source voltage -V EE is applied to the terminal 26. A base of the transistor Q16 is connected to a cathode of the diode D1, and an emitter thereof is connected to the terminal 26 through a register R E . The ON/OFF state of the transistor Q16 is controlled by the transistor Q15. In operation, when the potential at the terminal 10 falls from "H" to "L", both the emitters of the transistor Q4 and Q5, i.e., the terminals 22 and 23 transitionally have potentials at "H" due to the discharge of the load capacitor C L , until the potential at the terminal 10 reaches the reference voltage V BB . Therefore, the transistors Q11 and Q13 are allowed to conduct, while the transistors Q12 and Q14 are cut off. At this time, the base potential of the transistor Q15 is at the ground level (GND), and the emitter of the transistor Q16 has a potential (GND - 3V BE ), where V BE denotes a base-emitter voltage of each of the illustrated transistors. Therefore, a current I EF which passes through the resistors R E from the terminal 21 can be represented as (V EE - 3V BE )/R E . It is now assumed that the negative power source voltage -V EE is equal to-3.6 [V]. With the resistor R E equal to 1.2 [kΩ], the current I EF is approximately 1 [mA]. A current I RC which passes through the resistor R C is zero. A current I RF which passes through the resistor R F can be described as (V EE - 3V BE )/R F . In the case where the resistor R F is 10 [kΩ], the current I RF is approximately 0.12 [mA]. When either one of the terminals 22 and 23 has "H" and the other has "L" in the stationary state, for example when the terminal 23 has "H" and the terminal 22 has "L", the transistors Q12 and Q13 conduct, the currents I EF and I RC become identical to each other. In this case, the base potential of the transistor Q15 is (GND - I RC ·R C ) , and the emitter potential of the transistor Q16 is (GND - I RC ·R C - 3V BE ) . Both the currents I EF and I RC pass through the resistor R E , and thus each of the currents I EF and I RC can be expressed as (V EE - 3V BE )/(2R E + R C ) , and is approximately 0.12 [mA] where R C = 7.6 [kΩ] . The current I RF can be expressed as (V EE - 3V BE )2R E /[(2R E + R C )R F ] , and is approximately 0.03 [mA]. When the potentials at both the terminals 22 and 23 are at "L", the current I EF is zero, and the current I RC can be represented as (V EE - 3V BE )/(R E + R C ) . Assuming the above-described values, the current I RC is approximately 0.14 [mA]. And the current I RF can be represented as (V EE - 3V BE )R C /[R F (R E + R C )] , and is approximately 0.10 [mA]. In this manner, the variable impedance circuit 20 shown in FIG.2 is changed to a low impedance during the transitional time period in which the potential of the output terminal 10 is switched from "H" to "L". Thereby the current I EF becomes approximately 1 [mA] as described before, so that the variable impedance circuit 20 enables the charge stored in the load capacitor C L to be rapidly discharged. On the other hand, in the stationary state, the variable impedance circuit 20 is changed to a high-impedance state and permits the current I EF having a value of only 0.12 [mA] to pass therethrough. Further, a current flow through the whole of the circuit of FIG.3 is 1.12 [mA] during the transitional period, while current flow therethrough is only 0.24 [mA] in the stationary state. Further, the magnitude of the current I EF is determined depending on the resistor R E during the transitional time period and is determined depending on the resistors R E and R C in the stationary state. Therefore, it becomes possible to obtain an optimum value of the current I EF such that the current I EF is relatively large during the transitional period, and is relatively small in the stationary state, by setting the resistor R E to a small value and setting the resistor R C to a large value. FIG.4 shows a variation of the variable impedance circuit 20. The illustrated variation is different from the circuit structure of FIG.3 in the following matters. First, a multiemitter transistor Q17 is used in place of the transistors Q12 and Q14. A first emitter of the transistor Q17 is connected to the emitter of the transistor Q11, and a second emitter thereof is connected to the emitter of the transistor Q13. Secondly, transistors Q18 and Q19 are used in place of the transistors Q16. A collector of the transistor Q18 is connected to the emitter of the transistor Q13 and the second emitter terminal of the transistor Q17. A collector of the transistor Q19 is connected to the emitter of the transistor Q11 and the first emitter of the transistor Q17. An emitter of the transistor Q18 is connected to the negative power source voltage -V EE through a resistor R E1 , and an emitter of the transistor Q19 is connected to the negative power source voltage -V EE through a resistor R E2 . In operation, when both the terminals 22 and 23 are at "H", the current I EF is represented as (V EE - 3V BE )/R E where R E1 = R E2 = 2R E , and is approximately 1 [mA]. The current I RC is zero, and the current I RF is represented as (V EE - 3V BE )/R F . With the resistor R F equal to 12 [kΩ], the current I RF is approximately 0.1 [mA]. When either one of the terminals 22 and 23 is at "H", each of the currents I EF and I RC is represented as (V EE - 3V BE )/(2R E + R C ) , and is approximately 0.12 [mA]. Further when both the terminals 22 and 23 are at "L", the current I EF is zero, and the current I RC is expressed as (V EE - 3V BE )/(R E + R C ) and is approximately 0.14 [mA]. The current I RF is expressed as [R E (V EE - 3V BE )/R F ]/[(R E + R C )] , and is approximately 0.014 [mA]. FIG.5 shows another variation of the variable impedance circuit 20 shown in FIG.2. Emitters of transistors Q20 and Q21 are connected to each other, and thereby the transistors Q20 and Q21 constitute a current switch. Bases of the transistors Q20 and Q21 are connected to the terminals 22 and 25, respectively. A collector of the transistor Q20 is connected to the terminal 21, and a collector of the transistor Q21 is connected to the positive power supply V CC through the resistor R C . Emitters of transistors Q22 and Q23 are connected to each other, and thereby the transistors Q22 and Q23 constitute a current switch. A collector of the transistor Q22 is connected to the emitters of the transistors Q20 and Q21, and a collector of the transistor Q23 is connected to the positive power source V CC through the resistor R C . A base of the transistor Q22 is connected to an emitter of a transistor Q24 which is an emitter follower. A base of the transistor Q23 is supplied to a reference voltage V BB1 , which may be set equal to a voltage of (V BB - V BE ). The transistor Q24 is used for decreasing a potential level in order to apply a suitable bias voltage to the transistor Q22. A collector of the transistor Q24 is connected to the positive power source V CC , and a base thereof is connected to the terminal 23. An emitter of the transistor Q24 is connected to a constant current source 27. The emitters of the transistors Q22 and Q23 are connected to the collector of the transistor Q16 which serves as the constant current source. The collector of the transistor Q20 is connected to a collector of a transistor Q25. The transistor Q25 is provided in order to prevent the output terminal 10 of the ECL circuit from being set in the floating state in which the current I EF becomes zero when either the terminals 22 or 23 are at "L". The emitter terminal of the transistor Q15 is connected to the base of the transistor Q25 through diodes D1 and D2 used for the level adjustment. The base of the transistor Q25 is also connected to the base of the transistor Q16 and also to the negative power source -V EE through a resistor R F . An emitter of the transistor Q25 is connected to the negative power source -V EE through a resistor R G . In operation, when both the terminals 22 and 23 are at "H", a current passes through the transistors Q20, Q22 and Q16 in this sequence, and is represented as (V EE - 4V BE )/R E . At this time, a current which passes through the transistor Q25 is expressed as (V EE - 4V BE )/R G . Therefore, the current I EF is an addition of the current flow through the transistor Q16 and the current flow through the transistor Q25, and is represented as (V EE - 4V BE )(1/R E + 1/R G ) . When one of the terminals 22 and 23 or both of them are at "L", the transistor Q20 is maintained in the OFF state, and therefore the current is allowed to flow through a path composed of the resistor R C and the transistors Q21, Q22 and Q16, or a path composed of the resistor R C and the transistors Q23 and Q16. At this time, the current which passes through the transistor Q16 is expressed as (V EE - 4V BE )/(R E + R C ) . The current which passes through the transistor Q25 is R E /R G times greater than the current flow through the transistor Q16, that is, (V EE - 4V BE ) [1/(R E + R C )] (R E /R G ) . Because the transistor Q20 is kept in the OFF state, the current I EF is equal to the current which passes through the transistor Q25. With respect to the current I EF , when comparing the case where the terminals 22 and 23 are both at "H" with the other cases, (V EE - 4V BE )(1/R E + 1/R G ) is always larger than (V EE - 4V BE )[1/R E + R C )](R E /R G ) for any positive resistance value of the resistor R C . As a result, in the transitional state where both the terminals 22 and 23 are at "H", the current I EF having a value larger than values for the other states. FIG.6 shows an application of the ECL circuit of the present invention. The base inputs A and B of the transistors Q1 and Q2 are compared with the reference voltage V REF which is applied to the base of the transistor Q3. The OR operation result A+B is obtained at the output terminal 10, and the NOR operation result A+B is obtained at another output terminal 11 of the ECL circuit. To perform the NOR operation, transistors Q6 and Q7 of emitter followers are provided. A variable impedance circuit 30 is provided on the side of the OR operation, and a variable impedance circuit 31 is provided on the side of the NOR operation. The variable impedance circuit 30 is constituted by substituting the transistors Q12 and Q14 shown in FIG.3 with a transistor Q26 having two emitters such as the transistor Q17 shown in FIG.4. On the other hand, the variable impedance circuit 31 is the same as that shown in FIG.4. An emitter of the transistor Q7 is connected to the base of the transistor Q13 of the variable impedance circuit 31, and an emitter of the transistor Q6 is connected to the collectors of the transistors Q11 and Q13 and also to the emitter of the transistor Q11. The emitters of the transistors Q5 and Q7 are connected to the negative power source -V EE through resistors R₃ and R₄, respectively. In operation, when the level of the transistor Q5 is switched as shown in FIG.7(B), if the variable impedance circuit 30 is not provided in the ECL circuit, the potential at the output terminal 10 varies as shown by a broken line shown in FIG.7(A), and the fall time of the potential at the output terminal 10 would be lengthened. On the other hand, in the illustrated circuit having the variable impedance circuit 30, the potential at the output terminal 10 varies as shown by a solid line shown in FIG.7(A), so that the fall time can be greatly decreased. The present invention is not limited to the embodiments described above; for example, in place of the transistor Q16, the pair of the transistors Q18 and Q19 shown in FIG.4 may be used. Further, the present invention includes an emitter coupled logic circuit having three or more inputs.

Claims: An emitter coupled logic circuit comprising a plurality of transistors (Q1, Q2, Q3) constituting current switches for receiving input signals and outputting at least a first output signal, emitters of the plurality of transistors being mutually connected; a first emitter follower means (Q4) for extracting the first output signal and supplying it to a first output terminal; and variable impedance means (20) connected between a negative power source line (V EE ) and at least the first output terminal for variably providing an impedance to be coupled with that output terminal; characterized in that: a second emitter follower means (Q5) is provided for extracting a second output signal complementary to the first output signal; and in that said variable impedance means (20) is arranged to provide a lower impedance when both the first and second output signals are at a high level, than when either output signal is at a low level. An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance circuit comprises a first pair of transistors (Q11, Q12), emitters of which are connected to each other; a second pair of transistors (Q13, Q14), emitters of which are connected to each other, a collector of one (Q11) of the first paired transistors and a collector of one (Q13) of the second paired transistors being connected to each other, a collector of the other (Q12) of the first paired transistors and a collector of the other (Q14) of the second paired transistors being connected to each other and also to a positive power source (V CC ) through a resistor (R C ), a base of said one (Q11) of the first paired transistors being connected to the first output terminal of the first emitter follower means (Q4), a base of said one (Q13) of the second paired transistors being connected to the second output of the second emitter follower means (Q5), bases of said the others (Q12, Q14) of the first and second paired transistors being supplied with a reference voltage (V BB ); constant current source means being connected between the emitters of each of the first and second paired transistors and a negative power source (-V EE ); and third emitter follower means (Q15) being connected to the collectors of said the other (Q12, Q14) of the first and second paired transistors for controlling ON/OFF states of the constant current means (Q16). An emitter coupled logic circuit as claimed in claim 2, characterized in that said the other transistors of the first and second paired transistors are constituted by one transistor (Q17) having two emitters. An emitter coupled logic circuit as claimed in claim 2, characterized in that said constant current source means comprises two transistors (Q18, Q19), one of which is connected to the emitter of the first paired transistors (Q11, Q12), and the other of which is connected to the emitters of the second paired transistors (Q13, Q14), and in that bases of said two transistors are connected to the negative power source through a third register (R F ) and a diode (D₂), and are also connected to the third emitter follower means, and emitters of said two transistors are connected to the negative power source through respective emitter resistors (R E1 , R E2 ). An emitter coupled logic circuit as claimed in claim 2, characterized in that said constant current source comprises one transistor (Q16) having two collectors, one of which is connected to the emitters of the first paired transistors (Q11, Q12), and the other of which is connected to the emitters of the second paired transistors (Q13, Q14), and in that a base of said one transistor of the constant current source is connected to the negative power source through a third resistor (R F ) and a diode (D₂) and also to the third emitter follower means (Q15), and an emitter of said one transistor having the two collectors is connected to the negative power source (-V EE ) through an emitter resistor (R E ). An emitter coupled logic circuit as claimed in claim 2, characterized in that the third emitter follower means comprises a transistor (Q15), a base of which is connected to the collectors of said the others (Q12, Q14) of the first and second paired transistors, an emitter of which is connected to the constant current source through a level shift diode (D1), and a collector of which is connected to the positive power source (V CC ). An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance means comprises a first pair of transistors (Q20, Q21), emitters of which are connected to each other, a collector and base of one (Q20) of the first paired transistors being connected to the first output of the first emitter follower means (Q4), a base of the other of the first paired transistors being supplied with a reference voltage (R REF ); a second pair of transistors (Q22, Q23), emitters of which are connected to each other, a collector of one of the second paired transistors being connected to the emitters of the first pair of the transistors (Q20, Q21), a collector of the other (Q23) of the second paired transistors being connected to a collector of the other (Q21) of the first paired transistors, a base of the other (Q23) of the second paired transistors being supplied with another reference voltage (V BB1 ); a level adjusting transistor (Q24) for adjusting a bias level to be applied to a base of said one (Q22) of the first paired transistors, the level adjusting transistor being controlled by the second emitter follower means (Q5); constant current source means (Q16) being connected to the mutually connected emitters of the second pair of transistors (Q22, Q23); a driving transistor (Q15) for controlling ON/OFF states of the constant current source means (Q16); and a controlling means (Q25) for forming a current path between the first output terminal and the negative power source. An emitter coupled logic circuit as claimed in claim 7, characterized in that the constant current source comprises a transistor (Q16), a collector of which is connected to the emitters of the second pair of the transistors (Q22, Q23), an emitter of which is connected to the negative power source through a resistor (R E ), a base of which is connected to a base of the controlling transistor (Q25), and in that a collector of the controlling transistor (Q25) is connected to the collector of said one (Q20) of the first pair of transistors, an emitter of the controlling transistor (Q25) is connected to the negative power source through an emitter resistor (R G ), the base of which is connected to the negative power source through a base resistor (R F ). An emitter coupled logic circuit as claimed in claim 7, characterized in that the level adjusting transistor (Q24) is an emitter follower, and characterized in that an emitter of the emitter follower transistor is connected to the base terminal of said one (Q22) of the second paired transistors, a collector of which is connected to the positive power source (V CC ), and a base of which is connected to the output of the second emitter follower means. An emitter coupled logic circuit as claimed in claim 7, characterized in that the third emitter follower means comprises a transistor (Q15), a base of which is connected to said one (Q20) of the first paired transistors, a collector of which is connected to the positive power source (V CC ), and a base of which is connected to the constant current source means (Q16) through a level shift diode (D1, D2) and also to a base of the controlling transistor (Q25). An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance means (20) is provided at each of the first and second output terminals.

Inventors: KOKADO, MASAYUKI
Applicants: FUJITSU LIMITED
Application year: 1988
Main classification: H03K19
IPC codes: H03K17, H03K19