GaAs ELECTRICAL CIRCUIT DEVICES WITH LANGMUIR-BLODGETT INSULATOR LAYER

Abstract: A GaAs circuit structure is described which interposes a Langmuir-Blodgett (L-B) layer between the substrate and a conductive contact. The thickness of the layer is controlled to determine the operating characteristics of the device. The L-B layer has been found to both increase the gate barrier height for an FET, and to passivate dangling bonds and surface defects in the GaAs substrate to enable inversion mode operation. Specific FET and diode devices are described.

Description: GaAs ELECTRICAL CIRCUIT DEVICES WITH LANGMUIR-BLODGETT INSULATOR LAYER BACKGROUND OF THE INVENTION Field of the Invention This invention relates to electrical circuit devices such as field effect transistors (FETs) , and more par- ticularly to such devices and a method of fabricating the same on a gallium arsenide (GaAs) substrate. Description of the Related Art GaAs devices have been developed which offer con- siderably higher speed operation than other semi-conductor materials, for both discrete devices and digital in¬ tegrated circuits. However, GaAs is a difficult material to work with because its surface is typically charac¬ terized by dangling bonds and surface defects which ser- iously limit the range of the gate voltage that can be applied to an FET. Present GaAs technology limits the positive gate voltage swing to between about 0 and 0.7 volts. This places severe noise margin limits of about 20 to 30 mV on these devices, and imposes rigid controls on circuit designs and processing. Whereas other semiconductor materials such as silicon and indium phosphide can support metal-oxide-semiconductor FETs (MOSFETs) , attempts to use GaAs with a deposited dielectric (e.g., Siθ 2 ) as a gate insulator have resulted in large surface state and surface defects densities. This in turn "pins" the Fermi level to about 0.8 eV below the conduction band, such that it cannot be controlled by the gate voltage. To avoid this, the gate contact is made directly to the semiconductor substrate surface to form a Schottky junction, rather than forming a dielectric insu- lating layer between the gate contact and the channel as with silicon or InP. Unsuccessful attempts have been made for many years to locate or devise a dielectric that can successfully passivate the surface states encountered with GaAs, and increase the gate barrier height beyond 0.7 volts. This problem is discussed in greater detail in S.D. Offsey et al., "Unpinned (100) GaAs Surfaces in Air Using Photochemistry," Applied Physics Letter 48. (7) pp.475 (Feb. 1986). The attainment of larger gate voltage swings would greatly improve the prospects of being able to use GaAs in large complex digital integrated circuits. Another desired application for GaAs devices would be to use them in an inversion mode such as that employed by enhancement- type FETs, rather than the present limitation to a deple- tion/accumulation mode of operation. The present limita¬ tion in the Schottky gate barrier height (due to "pinning" of Fermi level) prevents GaAs devices from being operated in an inversion mode. For silicon and InP devices in which gate insulators are commonly used, investigations have been reported concerning the use of Langmuir-Blodgett (L-B) films as the insulating medium. L-B films are formed from amphiphilic molecules with a hydrophobic "tail" and an ionizable "head", and are reported for example in an article by Hans uhn, "Functionalized Monolayer Assembly Manipulation," Thin Solid Films, 99, pp.l (1983). A laboratory set-up was reported for InP by G.G. Roberts, et al., Solid State & Electron Devices, "InP/Langmuir-film m.i.s.f.e.t. ,", Vol. 2, No. 6, pp.169, Nov. 1978. In the described set- up, source and drain electrodes were evaporated onto an InP surface, with a gap between the source and drain defined by a tungston wire stretched across the source- drain mask. An L-B film was substituted for Siθ2 as the gate insulator. The described fabrication process result¬ ed in relatively large scale devices and was not applic- able to small integrated circuit processing for micro¬ electronics. A comparable laboratory approach to forming rudimentary silicon devices with L-B film substituted for the usual Siθ2 gate insulator was described in Lloyd, et al. , "Amorphous Silicon/Langmuir-Blodgett Film Field Effect Transistor", Thin Solid Films, Vol. 99, pp.297 (1983) . Neither of these reports, however, were suggested as being applicable to GaAs, which heretofore has not been capable of supporting an insulating gate layer. SUMMARY OF THE INVENTION In view of the problems previously encountered with GaAs devices, the purpose of the present invention is to provide an electrical circuit structure employing a GaAs substrate, and in particular an FET device, in which the gate voltage is increased beyond 0.7 volts without the accompanying'problems of an excessively high surface state density and a reduction in noise immunity. The invention also seeks to produce a GaAs FET which is compatible with inversion mode operation and accompany- ing higher voltage swings, and to provide a fabrication method for GaAs devices which successfully meets all of these criteria and is compatible with IC processing. In accordance with the invention, an L-B layer is formed over a portion of a GaAs substrate, with a conduc- tive contact overlying and contacting at least a portion of the L-B layer. The L-B layer can be fabricated as either a single film about 30 angstroms thick or as a composite of multiple L-B films each about 30 angstroms thick. These latter types of devices are capable of MOSFET-type inversion mode operation, with the L-B layer functioning as a gate insulator and also passivating dangling bonds and surface defects in the GaAs. In fabricating an FET, ohmic metal source and drain contacts are formed on either side of the channel and are coated with a layer of metal, preferably nickel, having a hydrophilicity similar to that of the GaAs. The L-B layer is then formed as a continuous film over both the channel areas and the source and drain contacts, and a gate con¬ tact is thereafter made to the portion of the L-B layer over the channel region. The L-B material is then removed from the device except where it is covered by the gate contact. To avoid damaging the L-B layer, the gate con¬ tact is formed by depositing a succession of metal layers and cooling the device after each layer has been deposit- ed. Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of preferred embodiments, taken to¬ gether with the accompanying drawings, in which: DESCRIPTION OF THE DRAWINGS FIGS. 1(a) - 1(e) are sectional views, not to scale, of successive steps in the fabrication of an FET in accor¬ dance with the invention with a single L-B gate film; FIG. 2 is a sectional view, not to scale, of an FET with a multi-film L-B gate layer; FIG. 3 is a sectional view, not to scale, of a diode constructed in accordance with the invention with a single L-B film layer; and FIG. 4 is a capacitance-voltage graph for the diode shown in FIG. 3. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In contrast with prior GaAs devices which have conductive contacts in direct contact with the GaAs sub¬ strate via a reverse biased Schottky junction, the present invention interposes an insulative layer between the contact and the substrate. The layer is provided in the form of one or more L-B films, with the aggregate thick¬ ness of the films tailored to the intended use of the device. The preferred fabrication sequence for an FET with a single L-B gate insulating film is shown in FIGS. 1(a)- 1(e). The resulting device is comparable to a MΞSFET (metal-semiconductor FET) , but with a greater gate voltage swing than has previously been attainable. Since a par¬ tially insulating layer is placed between the gate contact and channel, the device is referred to as a metal-insula¬ tor FET (MISFET) . Referring to FIG. 1(a), a GaAs substrate 2 is shown which includes an n-type silicon channel implant . Alternately, boron could be implanted to produce a p-tγpe channel, or other n or p dopants may be implanted. Mole¬ cular beam epitaxy or chemical vapor deposition could also be employed to establish the doped channel region 4. The wafer is annealed after the doped layer 4 is formed. N + regions 6 and 8 are then implanted into the sub¬ strate to provide source and drain regions, respectively, as illustrated in FIG. 1(b). After another anneal, ohmic metal contact pads or bodies 10 and 12 are deposited respectively over the source and drain implants 6 and 8, and annealed (FIG. 1(c)). Contact pads 10 and 12 are typically formed from gold. However, it has been found that L-B films tend to develop discontinuities and to break up when deposited over heterogeneous materials such as gold and GaAs. Accordingly, the contact pads 10 and 12 are capped by the deposition of respective layers of metal 14, 16 having a hydrophobicity sufficiently similar to the GaAs surface to permit the formation of a continuous L-B layer in a subsequent step. Nickel is a suitable cap material. Other Group VIII metals with the same valence as nickel, such as platinum and palladium, .might also be suitable. A continuous L-B layer 18 is next deposited over the device by a dipped coating method that is consistent with semiconductor clean room practices, as shown in FIG. 1(d). The L-B layer 18 consists of a single film, which with present fabrication techniques is about 30 angstroms thick. The invention has been demonstrated using ω-tri- cosenoic acid L-B film but, as discussed below, other L-B formulations may be more desirable in various circumstan¬ ces. The L-B layer 18 forms a continuous film over both the ohmic contacts 10 and 12 and the intervening channel portion of the n- implant 4. If a blanket implant was initially employed, the substrate is preferably treated with an O 2 implant before laying down the L-B film to isolate the channels; the O 2 is not needed if isolated channel implants are employed. Still referring to FIG. 1(d) , a gate contact 20 is next formed over the portion of the L-B layer in alignment with the channel from aluminum or other suitable metal. The gate contact is preferably established by evaporating a film of the contact metal over the entire wafer, fol¬ lowed by the evaporation of a nickel cap 22 over the gate contact portion of the evaporated aluminum. The nickel cap acts as a mask, permitting the aluminum to be etched away except under the cap. The aluminum layer is prefer¬ ably about 1,000 angstroms thick. To avoid damaging the underlying L-B layer from the heat associated with the aluminum evaporation, five successive evaporations of aluminum are preferably performed, each about 200 ang¬ stroms thick. The wafer is permitted to cool after each layer is formed while the evaporator is turned off. Alternately, a low temperature evaporation process can be employed. One disadvantage of aluminum, is a tendency to oxidize. Other metals could be substituted for the gate contact, with an L-B layer that could withstand higher temperatures than those associated with aluminum evapora¬ tion. In the final step of fabrication, illustrated in FIG. 1(e), the exposed L-B layer is removed, preferably with an O 2 plasma, leaving only the portion of the L-B layer below the gate contact 20. The gate contact itself is typically about 2 microns wide, while the source and drain contacts 10, 12 are typically separated by about 5 microns. In a particular implementation the n-channel implant was im¬ planted with Si 28 at a density of 5 x 10 3 - 2 /cm 2 and an implant energy of 70 keV to form a depletion mode device. Its transconductance was determined to be about 15 mS/mm, and there was no indication of gate leakage current with a gate bias of 2 volts. By contrast, a similar aluminum gate MESFET without the L-B layer was found to have a transconductance of about 23 mS/mm, and gate leakage current resulted from gate biases in excess of 0.8 volts. A similar FET employing the techniques of the inven- tion is shown in FIG. 2, in which elements which are the same as in FIGS. 1(a) - 1(e) are identified by the same reference numerals. The device shown in FIG. 2 is capable of "inversion mode" operation. This is the type of opera¬ tion obtained with an MOSFET, in which the gate contact is separated from the channel by an insulating oxide layer. For a p-channel MOSFET, the source and drain are doped n while the channel is doped p. A positive gate voltage attracts electrons into the channel area adjacent the insulator layer, thereby permitting conduction between the source and drain. In the device of FIG. 2, the channel 24 is doped p. A plural succession of L-B layers 26a, b, c, d and e separate the gate contacts 20 from channel 24. The device is fabricated in a manner similar to that illustrated in FIGS. 1(a) - 1(e), but 5 L-B films are laid down in succession to provide a thicker L-B composite layer. A different number of L-B films could be used, but with each film 30 angstroms thick. Thus, the composite L- B layer insulates the gate contact 20 from the underlying channel 24. It has also been discovered that the L-B material provides the distinct advantage of passivating dangling bonds and surface defects in the underlying GaAs channel. As noted previously, dangling bonds and surface defects have been a long standing problem that had prevented the fabrication of MISFET-type devices with GaAs. The solu- tion of this problem with the present invention opens up an entire new area of circuit design. By lowering the surface state density of the GaAs such that its surface is not "pinned" at 0.8 Ev below the conduction band, voltage swings in the 1-4 volt range can be tolerated. One result of this improvement is the ability to offer better device performance for digital signal processing, thereby allow¬ ing VLSI circuits to be produced due to improved noise immunity and larger achievable gate voltage. L-B films are currently under investigation, and the exact mechanism by which the GaAs dangling bonds and surface defects are passivated is still a matter of some speculation. However, it is currently felt that the ionized "head" of the L-B molecules attaches to the sur¬ face of the GaAs to passivate it. The type of head group present in the L-B film is currently felt to be an impor¬ tant aspect in the degree of passivation attained, and also in increasing the gate voltage threshold. The GaAs surface quality is highly dependent upon the particular type of fabrication procedure employed, and varies with factors such as etching, polishing, chemical treatment and the degree of oxidation employed. Accordingly, although to date the invention has been demonstrated only with ω- tricosenoic acid L-B films, it is felt that even better performance may be obtainable with other L-B types. It is also believed that some L-B films may work better with certain GaAs surfaces and other types of L-B films may work better with other GaAs surfaces,' and that the parti¬ cular choice of L-B film will ultimately be selected to optimize the performance characteristics for the particu¬ lar GaAs surface under consideration. A capacitance-voltage trace for the diode with a single L-B film is shown in FIG. 4. This exhibits the characteristic shape of an MIS (metal-insulator-semi¬ conductor) capacitor with a transition from accumulation to depletion. The flat band voltage which occurs in the vicinity of zero volts implies a lowering of interface states or unpinning of the GaAs surface. A novel type of semiconductor device has thus been shown and described which combines the fast response of GaAs with the advantages of gate insulation that have heretofore been unobtainable with GaAs. Specific types of devices have been shown, but it should be understood that the invention is applicable in general to GaAs devices in which an insulating or barrier layer is desirable between a contact and the substrate. For example, the described technique is also compatible with the fabrication of self- aligned substitutional gate MISFETs. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

Claims: WE CLAIM: 1. An electrical circuit structure, comprising: a GaAs substrate, a Langmuir-Blodgett (L-B) layer overlying and in contact with a portion of the substrate, and a conductive contact overlying and contacting at least a portion of the L-B layer, and separated thereby from the substrate. 2. The electrical circuit structure of claim 1, the L-B layer comprising a single L-B film. 3. The electrical circuit structure of claim 1, the L-B layer comprising a composite of a plurality of L-B films. 4. The electrical circuit structure of claim 1, the circuit structure including at least one ohmic metal body contacting the substrate " lateral to the conductive con¬ tact, and a layer of metal having a hydrophilicity similar to that of the GaAs substrate over the body. 5. The electrical circuit structure of claim 4, wherein said metal layer is formed from nickel. 6. An electrical circuit structure, comprising: a GaAs substrate, a Langmuir-Blodgett (L-B) layer overlying and in contact with at least a portion of the substrate, and means for applying a voltage differential across the L-B layer and GaAs substrate. 7. The electrical circuit structure of claim 6, the L-B layer comprising a single L-B film. 8. The electrical circuit structure of claim 6, the L-B layer comprising a composite of a plurality of L-B films. 9. A metal-insulator-semiconductor field effect transistor (MISFET) , comprising: a GaAs substrate, spaced source and drain regions in the sub- strate, a channel region in the substrate between the source and drain regions, a Langmuir-Blodgett (L-B) layer overlying the channel region, the L-B layer being thin enough to permit tunneling therethrough to the channel region in response to an applied voltage, and electrical contacts respectively on the source and drain regions, and on the L-B film over the channel region. 10. The MISFET of claim 9, the L-B layer comprising a single L-B film. 11. The MISFET of claim 10, said L-B film being approximately 25 angstroms thick. 12. The MISFET of claim 9, wherein the electrical contacts for the source and drain each comprise an ohmic metal body with a layer of metal having a hydrophilicity similar to that of the GaAs substrate over the body. 13. A metal-insulating-semiconductor field effect transistor (MISFET) comprising: a GaAs substrate, spaced source and drain regions in the sub- strate, a channel region in the substrate between the source and drain regions, a Langmuir-Blodgett (L-B) layer overlying the channel region, the L-B layer being thick enough to insu¬ late the channel region and at least partially passivating the substrate surface, and electrical contacts respectively on the source and drain regions, and on the L-B film over the channel region. 14. The MISFET of claim 13, the L-B layer comprising a composite of a plurality of L-B films. 15. The MISFET of claim 14, wherein each of said L-B films is approximately 25 angstroms thick. 16. The MISFET of claim 13, wherein the electrical contacts for the source and drain each comprise an ohmic metal body with a layer of metal having a hydrophilicity similar to that of the GaAs substrate over the body. 17. A method of forming an electrical circuit struc¬ ture, comprising: forming a Langmuir-Blodgett (L-B) layer on a portion of a GaAs substrate, and forming a conductive contact over at least a portion of the L-B layer. 18. The method of claim 17, wherein said L-B layer is formed as a single film. 19. The method of claim 18, wherein the thickness of said film is approximately 25 angstroms. 20. The method of claim 17, wherein said L-B layer is formed as a composite of a plurality of adjacent L-B films. 21. The method of claim 20, wherein the thicknesses of each of said films is approximately 25 angstroms. 22. The method of claim 17, further comprising the steps of: forming at least one ohmic metal body on the substrate lateral to the conductive contact area prior to forming said contact, forming a layer of metal over each of said bodies, said metal layers having a hydrophobicity similar to that of the GaAs substrate, forming said L-B layer as a substantially con- tinuous layer over said portion of the substrate and over each ohmic metal body prior to forming said conductive contact, and removing said L-B layer from the areas not under said conductive contact after forming said contact. 23. The method of claim 22, wherein said conductive contact is formed by placing a layer of conductive contact material over said continuous L-B layer, masking a portion of the conductive contact material with another conductive material, and removing the unmasked portion of the conduc¬ tive contact material to expose the underlying L-B layer for removal.

Inventors: JOSEFOWICZ JACK, RENSCH DAVID B, JOSEFOWICZ, JACK, RENSCH, DAVID, B.
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L29