Digital signal processor comprising address generator accessing data stored in bidirectional space of data memory

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a digital signal processor capable of efficiently carrying out the arithmetic or interruption processing mainly of successive signals at a high speed through a small number of steps. Description of the Prior Art EP-A-0 047 439 representing the closest prior art from which the invention proceeds discloses an address expanding system comprising an instruction register which is coupled to a main memory and which stores an instruction read from the main memory, the instruction including a common address modification field for specifying an index address modification and base address modification and a displacement, a plurality of general registers which are connected through a bus to the instruction register, the contents of one of the general registers being added to a logical address in the index address modification, a plurality of base registers which are coupled through the bus to the instruction register, the contents of one of the base registers being added to the logical address in the base address modification, base register address generating means which receives a first data from the common address modification field and which produces a second data to specify one of the base registers, and adding means which is coupled to the instruction register, the general registers and the base registers and which adds the contents of the general registers, the base registers and the displacement. US-A-4616313 represents another prior art which discloses a high-speed address calculation circuit wherein a first data selector selects either the address from a memory address register or data from a designated index register of a register file and a second selector selects either data from an increment register or displacement data from a field include in each instruction. An adder selectively adds displacement data to the content of either a base register or index register when no move or vector instruction is executed, the result being supplied to the memory address register, and said adder adds the content of the memory address register to the increment register, both registers being preset by a calculation unit, in order to access equidistant locations of operand addresses when a move or vector operation is decoded. Fig. 1 shows a further prior art and is a block diagram indicating the structure of an address generator based on the address control system of the prior art disclosed, for example, in the "USER's MANUAL TMS32020" issued by Texas Instruments Inc. In this figure, 701 is data bus for data transfer, 702 is data bus to an auxiliary register pointer save register (ARB) 191 from the data bus 701, 191 is auxiliary register pointer save register (ARB), 704 is data save bus extending from auxiliary register pointer (ARP) 192, 705 is data bus between auxiliary register pointer (ARP) 192 and data bus 701, 707 is selection signal to select auxiliary register (AR) 193 from the auxiliary register pointer (ARP) 192, 193 is auxiliary register (AR = AR0 - AR4) providing 5 words, 709 is relative (indirect) address output from auxiliary register (AR) 709, 710 is address data sent from the auxiliary register (AR) 193, 711 is new address data obtained by updating address data 710 in the operation unit only for auxiliary register (ARAU) 194, 195 is data memory page pointer for direct address (DP), 714 is data memory page data output from data memory pointer for direct address (DP) 195, 196 is multiplexer (MUX) which generates direct address 717 by multiplexing the direct address data indicated by immediate value and data memory page data 714, 717 is direct address, 197 is selector which selects direct address 717 and relative address 709, 719 is address output, 720 is address control code, 721 is auxiliary register pointer save register control signal, 722 is auxiliary register pointer control signal, 198 is decoder for decoding address control code 720, 724 is control signal which controls operation unit only for auxiliary register (ARAU) 194, 725 is selection control signal which selects direct address 717 and relative address 709, 726 is data input/output bus between auxiliary register (AR) 193 and data bus 701, 727 is data input/output bus between data memory page pointer for direct address (DP) 195 and data bus 701. Fig. 2 is a table for explaining operation of address generator of Fig. 1 by the address control code. Next, operations of address generator of the prior art are explained. In case, the input address control code 720 is designated by direct address, the decoder 198 outputs the direct address data 716 indicated by the immediate value of 7 bits in the instruction code. This direct address data 716 and data memory page data 714 of 8 bits held by the data memory page pointer for direct address (DP) 195 are multiplexed by the multiplexer (MUX) 196 to generate the direct address 717. Finally, the address register selects the direct address 717 from the selector 197 with the selection control signal 725 and outputs the address output 719. Next, in case the input address control code 720 is designated by relative address, one of the auxiliary registers (AR) 193 indicated by the auxiliary register pointer control signal 722 output from the decoder 198 is output as the relative address 709. This is selected by the selector 197 with the selection control signal 725 to output the address output 719. Thereafter, the operation unit only for auxiliary register (ARAU) 194 executes the specified update processing for the one of the selected auxiliary registers (AR) 193 to calculate the relative address 709 to be used by the next instruction. The relative address 709 is used in the following five modes. 1. The auxiliary register (AR) 193 indicated by the auxiliary register pointer (ARP) 192 is used as the data memory address. 2. Access to data memory is made with content of auxiliary register (AR) 193 indicated by the auxiliary register pointer (ARP) 192 and thereafter "1" is subtracted from such content. 3. Access to the data memory is made with content of auxiliary register (AR) 193 indicated by the auxiliary register pointer (ARP) 192. 4. Access to data memory is made with content of auxiliary register (AR) 193 indicated by the auxiliary register pointer (ARP) 192 and thereafter content of auxiliary register (ARO) 193 is subtracted from such content. 5. Access to data memory is made with content of auxiliary register (AR) 193 indicated by the auxiliary register pointer (ARP) 192 and thereafter content of auxiliary register (ARO) 193 is added to such content. Namely, the addressing using the auxiliary register (AR) 193 is roughly classified into following two kinds in the prior art and these are equivalent to the kinds of calculation of the operation unit only for auxiliary register (ARAU) 194. A. Ordinary relative addressing by addition of "1"/subtraction of "1" for the auxiliary register (AR) 193 B. Relative addressing with index modification based on content of auxiliary register (ARO) These address modes can be thought to be suited to the simplified data address among the unidimensional data addresses mainly for voice signal processing. However, when addressing is carried out for the data on the bidimensional space, the address of leading reference point must be set to the address register and the pipeline of a series of calculations breaks, deteriorating the efficiency. Fig. 3 shows data series on the bidimensional space, and Fig. 4 is a flowchart of addressing operation for the data series of Fig. 3 by the address generator. In the data series of Fig. 3, it is assumed that the bidimensional data of M data in the horizontal direction and L data in the vertical direction are stored in the data memory with the unidimensional address. It is also considered here that the reference points in the block in such bidimensional data (2m data in the horizontal direction, one data in the vertical direction) are sampled in the direction of sequential horizontal scanning. First, the address of the point P 1 is initially set to the one auxiliary register AR1 (ARP = 1) of the auxiliary registers (AR) 8 as the address register and "2" is set to AR0. For the reference points on the same horizontal line, addressing is carried out depending on the address control mode No. 9 shown in Fig. 2, namely AR1 ← AR1 + AR0. However, the address of the leading reference point P m+1 of the next line cannot be generated by updating the value of AR1 and must be newly set. Accordingly, a step for calculating the leading address of line using the data calculator and setting it to AR1 is required. The subsequent processings are carried out in the same way as those for the first line. As can be seen in the above processing procedures, it is obvious that the intrinsical calculation processings are intermitted every time the line changes for the secondary data and thereby pipeline efficiency is lowered and processing period increases due to increase of a number of instruction steps. Since the address control system of the prior art is constituted as explained above, in case it is used for bidimensional signal processing such as processing of video signals, it results in problems that address calculation must be often carried out in the data calculation section and program software of signal processing algorithm is complicated. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital signal processor with an address generating system for signal processing comprising multifunction address generator intended to two-dimensional signal processing such as video signal processing by employing comparatively short control code bit length and simplified circuit structure. To achieve the above object, in accordance with the present invention, there is provided a digital signal processor as defined in claim 1. Further advantageous embodiments are defined in the dependent claims. The address generating system for signal processing of the present invention makes relative addressing depending on the address displacement indicated by an intermediate value in the control code in addition to the index modification address through combination of the address register and index modification register and also intermediately carries out address designation for every microinstruction in the relevant field among the horizontal microinstructions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram indicating the structure of an address generator based on the address control system of the prior art; Fig. 2 is a table for explaining operations by the address control code of the address generator of Fig. 1; Fig. 3 is a data series on the bidimensional space; Fig. 4 is a flowchart indicating addressing operations for data series of Fig. 3 by the address generator of Fig. 1; Fig. 5 is a block diagram indicating the structure of address generator adopted to the address generating system for signal process as a preferred embodiment of the present invention; Fig. 6 is a flowchart indicating addressing operation for data series of Fig. 3 by means of the address generator of Fig. 5, Fig. 7 is an example of address control code in the address generator of Fig. 5; Fig. 8 is a table for explaining operations by address control code of Fig. 7; Fig. 9 is a block diagram indicating the structure of signal processor adopting the address generating system for signal processing of Fig. 5; and Fig. 10 is an example of instruction code in the signal processor of Fig. 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 5 is a block diagram of the structure of address generator adopted to the address generating system for signal processing as a preferred embodiment of the present invention. In this figure, 701 is data bus used for data transfer, 728 is address register (ARx) used for generation of relative address, 726 is data bus for input and output of initial value from data bus 701 to address register (ARx) 728, 730 is index modification register (IXRx), 31 is data bus for input and output of initial value from data bus 701 to index modification register (IXRx) 730, 732 is one desired data output among address registers (ARx) indicated by address control code 720, 733 is one desired data output among index modification registers (IXRx) 730, 734 is adder [ADD (1)] which adds data output 732 and data output 733, 735 is data output of addition result of adder 734, 736 is selector (1) which selects data output 735 of the addition result when IXR is ON or data output 732 when IXR is OFF depending on the index modification (IXR) ON/OFF signal 746, 737 is adder [ADD (2)] which adds selected output of selector (1) 736 and displacement data 742 output from decoder 723, 738 is data output of addition result of adder [ADD (2)], 718 is selector (2) which selects data output 738 of addition result and direct address data 743 output from the decoder 723, 739 is selected data output of selector (2) 718, 740 is latch which outputs data output 739 in synchronization with cycle timing, 741 is address output synchronized with cycle timing, 720 is address control code, 723 is decoder which decodes address control code 720, 742 is displacement data indicated by immediate value from the address control code 720, 743 is direct address data indicated by immediate value from the address control code 720, 744 is address register selection signal for selecting the one of a plurality of address registers (ARx) 728, 745 is index modification register selection signal which selects the one of a plurality of index modification register (IXRx) 730, 746 is index modification ON/OFF signal output from the decoder 723, and 747 is direct address ON/OFF signal output from the decoder 723. Fig. 6 is a flowchart indicating addressing operation for data series of Fig. 3 by the address generator of Fig. 5. Fig. 7 shows an example of address control code in the address generator of Fig. 5. Fig. 8 shows a table for explaining operations of address control code of Fig. 7. Fig. 9 is a block diagram indicating the structure of signal processing processor adopting the address generating system for signal processing of Fig. 5. In these figures, 750 is instruction memory consisting of program memory, 751 is instruction address, 752 is instruction code read from address of instruction memory 750 corresponding to instruction address 751, 753 is instruction register (IR) which holds the instruction code 752 and decodes it, 754 is program counter (PC) which outputs the instruction address 751, 755 is program control circuit (program controller) which controls the program counter (PC) 754 depending on the instruction code 752, 756 is program bus (P-BUS) which distributes instructions to respective section from instruction register (IR) 753, 757 is data memory for storing calculation data, 758-is bus interface register (BIR) for data transfer between the program bus (P-BUS) 756 and the data bus (D-BUS) 701, 759 is multiplexer (MUX) which selects line of data bus (D-BUS) 701, 760 is address generator (AGU) indicated in Fig. 5, 761 is input/output data between data memory 757 and data bus (D-BUS) 701, 762 is input data to data calculation part 763 from data bus (D-BUS) 701, 763 is data calculation part which executes calculations, 764 is working register (WR) used for data calculation processing, 765 is input/output data between the working register (WR) 764 and the data bus (D-BUS) 701, and 770 is operation code for indicating instruction operations. Fig. 10 is an example of instruction code in the signal processor of Fig. 9. In this figure, 770 is operation code which specifies instruction operations and 720 is address control code which controls address of data memory 757. Next, the address generating operations of address generating system for signal processing as an embodiment of the present invention explained above are then explained hereunder. First, in case the input address control code 720 is provided for direct address designation, the decoder 723 outputs the direct address data 43 indicated by the immediate value. Next, the direct address ON/OFF signal 747 is turned ON and thereby the data output 739 can be obtained by selecting the direct address data 743 from the selector (2) 718. Finally, the data output 739 is held in the latch 740 for synchronization with the machine cycle and the address output 741 is provided. Next, in case the input address control code 720 is provided for relative address designation, only one of the address registers (ARx) 728 indicated by the address register selection signal 744 output from the decoder 723 is selected. In the same way, in the case of index modification, only one of the index modification registers (IXRx) 730 is selected. The data output 732 and data output 733 which are contents of these two registers are added in the adder [ADD (1)] and the data output 735 completed index modification can be obtained. The data output 735 is input to the one adder [ADD (2)] 737 by selecting the selector (1) 736 in accordance with the index modification ON/OFF signal 746 and it is then added with the displacement data 742 input to the other adder to obtain the relative address data output 738. With this data output 738, the one content of address registers (ARx) 728 is updated and simultaneously data output 738 is selected in the selector (2) 718 to output the data output 739 of address. It is then synchronized with the machine cycle by the latch 740 to obtain the address output 741. In case the index modification is not carried out, the selector (1) 736 inputs, during above operations, the data output 732 of address register (ARx) 728 to the one input of the adder [ADD (2)] 737. Therefore, the one of index modification registers (IXRx) 730 is not selected. Meanwhile, in case the addition of displacement data 742 is not carried out, the displacement data 742 indicated by immediate value in the address control code 720 is set to "0" and it is input to the other input of adder (ADD) 737. The relative address mode includes following four kinds of modes any combination can be selected for each control cycle. 1. Access to data memory 757 is made with content of the one address register (ARx) 728. 2. After the displacement data 742 indicated by immediate value is added to the one content in the desired address register (ARx) 728, the access is made to the data memory 757 with the result of such addition and simultaneously content of address register (ARx) 728 is reviewed. 3. After the one content in the desired address register (ARx) 728 is added to the one content in the desired index modification register (IXRx) 730, access is made to the data memory 757 with the result of addition and simultaneously content of address register (ARx) 728 is updated. 4. After the one content in the desired address register (ARx) 728 is added to the one content in the desired index modification register (IXRx) 730, the displacement data 742 indicated by immediate value is added to the result of addition. Access is made to the data memory 757 with the result of addition and simultaneously content of address register (ARx) 728 is updated. Fig. 7 shows an example of address control code 720 for address control, and Fig. 8 is a table for explaining operations depending on content of address control code 720. For example, when the bidimensional data are arranged in the horizontal direction in the sequence of address of data memory 757 by the relative address mode, if the horizontal size of bidimensional data is M, flexible address control can be realized by combining the relative address modes as indicated hereunder. A. In case access is made to data memory 757 in every a-address in the horizontal direction: +a or -a is designated to the displacement data 742 in the mode of address register (ARx) 728 + displacement data 742. B. In case access is made to data memory 757 in every a-address in the vertical direction: a x M or -a x M is set to the index modification register (IXRx) 730 and the mode of address register (ARx) 728 + index modification register (IXRx) 730 is used. C. In case access is made to data memory 757 in the oblique direction (for example, diagonal direction): M or -M is set to the index modification register (IXRx) 730 and the mode of address register (ARx) 728 + index modification register (IXRx) 730 + displacement data 742 is used. Here, Fig. 6 shows a flowchart of addressing operations for the data series shown in Fig. 3. First, a value of (M - 2m) is initially set to the one IXR0 in the index modification registers (IXRx) 730 and the address of point P 1 is initially set to the one AR0 in the address registers (ARx) 728. Operations heretofore are the same as those in the prior art. For the leading reference point P 1 of the first line, the addressing is made in the address control mode No. 1, namely in the mode of AR0 → AR0 shown in Fig. 8 and for the next reference point on the same line, addressing is carried out in the address control mode No. 2, namely in the mode of AR0 + disp (= 2) → AR0. Next, when the line is changed, the addressing can also be made in the address control mode No. 4, AR0 + IXR0 + disp → AR0. Accordingly, in an example of Fig. 3, addressing can be made continuously to the (m x 1) data. As explained previously, it is no longer necessary to carry out the address calculation by intermitting calculation in every change of line in the bidimensional data, the pipeline processing can be realized effectively and the program itself can also be simplified in the address generating system for signal processing of the present invention. In case a series calculation process is carried out continuously for a plurality of data series, the address value of leading reference point of each data series is previously calculated, it is then stored in the particular region of data memory, the leading address value of data series corresponding to the start of calculation process is read from the data memory 757 and it is then initially set to the particular address register in the address generators through the data bus 701. As explained previously, the present invention employs the structure which is capable of designating address register, index register and displacement for each microinstruction in the address generating system for signal processing and realizing relative addressing through combination of additions of three items and therefore provides such excellent effect as simplifying description of complicated address control for bidimensional data and realizing high speed signal processing.

Claims: A digital signal processor comprising: an instruction memory (750) which stores microinstructions indicating calculation contents and data address control contents, a data bus (701) for transferring data, a calculator (763) for performing calculation depending on the microinstruction for one or more data read simultaneously from the data bus (701) and an address generating means (760) comprising one or more address registers (728) which are capable of inputting or outputting initial values (726) from the data bus (701), and one or more index registers (730) which are capable of inputting or outputting address modification values (731) from the data bus (701), for respectively selecting one address register and index register among such address registers (728) and index registers (730) in accordance with the microinstruction, and means for calculating a current address data by combination of additions of at maximum three items taken among the content of the selected address register (728), the content of the selected index register (730) specifying the index relative value, and a displacement specifying a relative modification value indicated by an immediate value in the code of microinstruction, wherein an initial value to the address register (728) and one or more index registers (730) are preset through the data bus (701), characterized in that a plurality of data memories (757) are provided for storing series of data, respectively, the calculator (763) performs data input/output operation to and from the data memories (757) in parallel for one microinstruction, and the address generating means comprises a plurality of address generators (760) which generate, independently corresponding to input data in accordance with the microinstruction, addresses for reading data (762) from the data memories (757), wherein each of the address generators (760) comprises said one or more address registers (728), said one or more index registers (730), said calculating means as well as means for updating the content of the selected address register (728) with said calculated current address, and selecting means (718) for selecting either said calculated current address provided by said calculating means when relative address processing is instructed wherein the location of a first reference point to be accessed of a bidimensional data series being stored in a bidirectional space in the associated data memory (757) is the content of a particular address register being designated, and wherein said calculated current address data for the subsequent reference points, in every microinstruction, of said bidimensional data series is based on the current address value stored in said particular address register (728), a designated index register (730) and displacement, said designated index register (730) being preset with a value dependent on dimensional data related to said bidirectional space, or direct address data indicated by an immediate value in said microinstruction for data system of stored irregular data arrangement. A digital signal processor for signal processing according to claim 1, wherein in case data on the two-dimensional space extending for M data in the horizontal direction and for L data in the vertical direction, M, L are positive integers, are stored in said data memory (757) with the scalar address by the sequential scanning, address designation is carried out for the first reference point of data series having the two-dimensional arrangement using initialization value of the particular address register (728) in the address generator (760); for the subsequent reference points, in case the current reference point is separated by m data, m is displacement indicated by an integer within the settable range, in the horizontal direction and by I data in the vertical direction for the preceding reference point, when I is "0", namely the current reference point exists on the same horizontal line, a value of m is set to the displacement with the current instruction code (752) and address designation is carried out using an adding value of the content of particular address register (728) and displacement to which the value of m is set, when I is not "0", an index register (730) to which a value of I x M + a, a is an integer, is preset is designated by the current instruction code (752) and the processing for address designation is instructed with the instruction code (752) in every reference point by the adding value of three items of content of particular address register (728), content of designated index register (730) and displacement to which a value of m - a is set by the current instruction code (752). A digital signal processor for signal processing according to claim 1 or 2, wherein the address generator (760) is capable of setting the data previously stored in the designated address of data memory (757) or output data of the calculator (763) to the particular address register (728) or index register (730) through the data bus (701) and transferring content of particular address register (728) or index register (730) to the data memory (757) through data bus (701) or to this calculator (763) as the input data (762) of calculator (763). A digital signal processor according to claim 1 to 3, wherein in case the relative addressing is to be carried out to the data series consisting of a plurality of data, an address data value previously calculated and stored to the particular address (741) of data memory (757) or output data of calculator (763) is initially set to the particular address register (728) through the data bus (701) as the address of leading reference point of such data series.

Inventors: KAMEYAMA MASATOSHI, KAMIZAWA KOH, KATOH YOSHIAKI, KINJO NAOTO, MURAKAMI TOKUMICHI, OHIRA HIDEO, KAMEYAMA, MASATOSHI, KAMIZAWA, KOH, KATOH, YOSHIAKI, KINJO, NAOTO, MURAKAMI, TOKUMICHI, OHIRA, HIDEO, Kameyama, Masatoshi, c/o Mitsubishi Denki K. K., KAMIZAWA, KOH, C/O MITSUBISHI DENKI K. K., Katoh, Yoshiaki, c/o Mitsubishi Denki K. K., KINJO, NAOTO, C/O MITSUBISHI DENKI K. K., MURAKAMI, TOKUMICHI, C/O MITSUBISHI DENKI K. K., Ohira, Hideo, c/o Mitsubishi Denki K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1988
Main classification: G06F9
IPC codes: G06F9, G06F13, G06F15