Multi-frequency capacitance sensor

Abstract: The ratio C₁/C₂ between the capacitances of two capacitors is obtained by connecting them into the frequency-determining circuit of an oscillator in at least three different combinations, namely C₁ alone, C₂ alone and both or neither of C₁ and C₂; the resultant oscillation frequencies are measured, and a signal representative of changes in C₁/C₂ derived from the oscillator frequencies, preferably by means of digital circuitry. In one preferred mode C₁/C₂ is obtained by forming signals proportional to and in another preferred mode proportional to In still another preferred mode C₁/C₂ -1 is obtained from the expression T₁-T₃/T₂-T₃ and used as the indication of changes in C₁/C₂. In the foregoing, f₁, f₂, f₃ and f₄ are the oscillator frequencies produced respectively by connecting C₁ alone, C₂ alone, neither C₁ nor C₂, and both C₁ and C₂ into the frequency-determining circuit, and T₁, T₂, T₃ and T₄ are the periods of oscillations at f₁, f₂, f₃ and f₄ respectively.

Description: This invention relates to an electrical system (e.g. method and apparatus) for providing indications of capacitance values, and particularly to such method and apparatus for measuring the ratio between the capacitances C₁ and C₂ of two capacitors. As an example, it is known to measure pressure in a fluid by using a fixed capacitor and another capacitor subject to a variable pressure, and sensing changes in the ratio of the capacitances of the two capacitors. In other cases the two capacitances are arranged to change in opposite directions in response to a physical parameter such as pressure. There are other known situations as well in which it is desired to measure such ratio between the values of two capacitors. Typically the two capacitance values are nearly equal at some point in their expected range of variation in value, so that extraneous factors tending to affect the value of C₁/C₂ will be to a great extent cancelled out when the ratio C₁/C₂ is formed. One general method which may be employed to measure C₁/C₂ (or, equivalently, C₂/C₁) is to place C₁ and C₂ alternately into a position in an oscillator circuit in which the capacitor affects the frequency of oscillation, preferably so that changes in the oscillation frequency are substantially inversely proportional to the value of the capacitance placed in the circuit. By using the same circuit to generate the oscillations for both capacitors, and by switching the capacitors in and out of the circuit frequently and rapidly, sources of error other than noise and drift of circuit component values are to some extent eliminated; by deriving a signal proportional to the ratio of the values C₁ and C₂, the effects of drifts in circuit parameters, such as resistances and amplifier gains, are reduced. A system for measuring the ratio between capacitances by charging a pair of capacitors in an oscillator means is described in US-A-4 633 168 and this document is acknowledged in the ambit of the following claim 1. However, in such circuits there is always present some additional fixed or parasitic capacitance, here designated C p , continuously present in the circuit and affecting the frequency of oscillation. C p determines the frequency of oscillations which occur in the absence of both C₁ and C₂, and as used herein includes not only stray circuit capacitances but also any fixed lumped capacitance continuously present in the circuit. Accordingly, the foregoing procedures serve not to measure C₁/C₂, but instead measure (C₁+C p )/(C₂+C p ) . The latter ratio is not in general the desired ratio C₁/C₂, and inaccuracy therefore results, especially where the values of C₁ and C₂ are small. In addition, in such cases the ratio will have an unpredictable temperature coefficient of span or gauge factor, due to the unpredictable temperature coefficient of C p . It is therefore an aim of this invention to provide a new and useful method and apparatus for providing electrical indications of the ratio between the capacitances C₁ and C₂ of a pair of capacitors in an accurate and reliable manner. What constitutes the invention is set out in the following claim 1 and in essence relates to a method and apparatus for measuring the ratio between the capacitance values C₁ and C₂ of a pair of capacitors by intermittently connecting the capacitors into an active position in the frequency-determining circuit of an oscillator in various combinations; at one time one capacitor is connected into the active frequency-determining position to cause oscillation at a frequency f₁, at another time the other capacitor is so connected to produce an oscillator frequency f₂, and at still another time neither or both of the capacitors are so connected to produce another oscillator frequency f₃ (if neither connected) or f₄ (if both connected). From the three oscillator signals of frequencies f₁, f₂, and f₃ or f₄ there is derived a signal value representative of the ratio between C₁ and C₂, as desired. This ratio value is substantially free of errors due to parasitic capacitance, yet the apparatus and method are simple, reliable, and economical to make and use. The embodiment of the invention which uses the frequency f₃, produced by making both capacitors inactive in the oscillator circuit, will be designated herein as the M₃ mode, and that which uses the frequency f₄ produced by connecting both capacitors actively in the frequency-determining circuit, as the M₄ mode. At the present time the M₄ mode is preferred for applicant's purposes. As will be demonstrated hereinafter, the capacitance ratio using the M₄ mode is given by either of the following equivalent expressions: where T₁, T₂, T₄ are the cycle periods of the oscillations at f₁, f₂ and f₄ respectively. Accordingly, one may produce the desired signal value representing C₁/C₂ by apparatus which forms the difference (f₂-f₄), multiplies it by f₁, forms the difference (f₁-f₄), multiplies it by f₂, and then forms the quotient shown at (1) above. Or, more easily in many cases, the periods T₄, T₂ and T₁ are measured, signals representing the numerator (T₄-T₂) and the denominator (T₄-T₁) formed, and the numerator divided by the denominator, as also indicated in expression (1) above. The latter procedure is presently preferred for its ease of implementation. In the M₃ mode, Again, while apparatus for obtaining the value of C₁/C₂ may calculate either the frequency-containing expression or the expression in terms of the period T, the latter is presently preferred. The oscillator circuit presently preferred for these purposes employs an inverting hysteresis circuit with its output fed back to its input through a non-inverting amplifier having unity gain; the capacitors to be measured are connectable between the input and the output of the amplifier (inactive position) or between the input of the amplifier and circuit ground (active position). In the preferred embodiment, the capacitors are automatically and cyclically switched into and out of their active positions, and the durations T of the cycles of the resultant oscillator signals at three different frequencies are measured from which the signal value representing C₁/C₂ is derived. The theory of the invention is as follows. The frequency of the oscillator is inversely proportional to the active capacitance in the frequency-determining position in the oscillator circuit - in the preferred example, between the amplifier input and circuit common or ground. If there were no parasitic capacity, one could alternately switch C₁ and C₂ into the active position, and measure the corresponding frequencies f₁ and f₂, or the periods T₁ and T₂. C₁/C₂ would then equal f₂/f₁, or T₁/T₂ (times an appropriate scaling factor). However, parasitic capacity is present, and can be represented by a capacitance C p added to the active capacitance. The effective capacitances are then C₁+C p and C₂+C p , and their ratio (C₁+C p )/(C₂+C p ) is not the same as the desired ratio C₁/C₂. The corresponding actually-measured ratio's f₂/f₁ and T₁/T₂, in a two-frequency system, therefore do not represent C₁/C₂ accurately because of the effects of C p . However, in accordance with the teachings of this invention, the two capacitors are capable of being connected actively in the circuit in any of four combinations, with the results as shown in the following Table: In the above, R represents the resistive parameters in the oscillator circuit and K represents the other constant circuit parameters determining the frequency of oscillation. C p is as defined previously. In the above expressions K, R and C p are assumed to be constant. Using the first three of the above-listed conditions, by algebraic manipulation it can be shown that: C₁/C₂ = (T₁-T₃)/(T₂-T₃) = f₂(f₃-f₁)/f₁(f₃-f₂) (3) Using the first two and the fourth relations in the Table above, C₁/C₂ = (T₄-T₂)/(T₄-T₁) = f₁(f₂-f₄)/f₂(f₁-f₄). (4) Any one of the four expressions for C₁/C₂ given above may be used to obtain the desired signal value for C₁/C₂. The expression (T₄-T₂)/(T₄-T₁) in the M₄ mode is presently preferred. It is not only easy to implement, but also is more likely to produce better compensation, since f₄ (produced with both C₁ and C₂ active) is a lower frequency than f₃ (produced by neither C₁ nor C₂ active), and hence the values of KR and C p will be more nearly exactly constant for the three frequencies f₁, f₂ and f₄, as desired for good compensation. The invention will now be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a broad diagrammatic representation of a system embodying the invention; Figures 1A and 1B are graphs of waveforms in the circuit of Fig. 1; Figure 2 is a more detailed schematic diagram of a multi-mode oscillator as used in a preferred form of the invention; Figure 3 is a schematic diagram showing in more detail a preferred form of the arrangement for converting the oscillations at three frequencies into an analog signal representing the ratio between the capacitances C₁ and C₂ of the two capacitors; Figure 4 is a timing diagram showing, at A through E, five waveforms produced at five points in the system of Fig. 3, to a common horizontal time scale; and Figure 5 is a block diagram illustrating another form of embodiment of the invention which is preferred for certain purposes. Referring first to Fig. 1 which illustrates certain basic aspects of the invention in broad outline, there is shown a multi-mode oscillator (MMO) capable of oscillating at any of four frequencies f₁, f₂, f₃ or f₄, depending upon whether capacitor C₁, capacitor C₂, neither capacitor, or both capacitors are actively connected in the frequency-determining circuit. More particularly, the oscillator comprises a non-inverting operational amplifier 10 having unity gain by virtue of the direct connection of its output to its minus (inverting) input terminal; an inverting bistable hysteresis amplifier 12 is supplied with the output of the non-inverting amplifier 10, and the output of the bistable amplifier is fed back through a feed back resistance 14 to the plus (non-inverting) input terminal of amplifier 10. The frequency-determining circuit in this embodiment is that extending between the plus input terminal of the amplifier 10 and circuit ground or common, i.e. the same ground to which the two amplifiers are returned. The value of capacitance connected in this position controls the frequency of oscillation of the oscillator, the greater the capacitance the lower the frequency. More particularly, the feedback resistance and the capacitance provide an integrator action such that the voltage V at the input to the bistable amplifier increases at a rate determined by the capacitance actively connected into the circuit, until it reaches a trigger level of voltage V h at which the bistable amplifier is triggered to its opposite state, whereupon its input voltage falls to a minimum level V L . This input variation is shown in Fig. 1A. The corresponding output voltage of the bistable amplifier is a generally rectangular wave which switches between its high and low levels in synchronism with the above-described input waveform, as shown in Fig. 1B. The amount of frequency-controlling capacitance actively connected in the frequency-determining circuit is controlled by two independent single-pole, double-throw switches 20 and 22 which control the connection to ground of the sides of capacitors C₁ and C₂ opposite from the sides which are connected to the plus input terminal of amplifier 10. By operating these switches to their various combinations of positions, either C₁ or C₂, or neither or both, may be actively connected into the frequency-determining circuit to determine the frequency of the oscillator. Such switching is typically done by appropriate electronic switches. In this way the output pulse waveform shown in Fig. 1B may be provided at the frequencies f₁, f₂ and either f₃ or f₄ as desired. Figure 2 shows in more detail the presently-preferred circuit for use in the general system of Fig. 1, and corresponding parts are designated by corresponding numerals. In Fig. 2, the bistable hysteresis amplifier 12 comprises a series input resistor 50 and three CMOS complementary pairs 52, 54 and 56 connected in tandem; a feedback resistor 57 is connected between the input terminal of the first CMOS pair 52 and the output of the second CMOS pair 54. The output of the third CMOS pair 56 is connected back to the plus input terminal of amplifier 10 through feedback resistor 14. The third CMOS pair serves as an inverter and as a low-impedance output driver. The connecting of the capacitors C₁ and C₂ in and out of these active positions in the frequency-determining circuit is effected by a conventional commercially-available CMOS dual single-pole, double-throw switch 60, controlled by two mode control lines 62 and 64, so as to connect C₁ or C₂, neither of them, or both of them, to ground (active position); that capacitor at any time not connected to ground is instead connected to the output of amplifier 10 and is inactive so far as affecting frequency is concerned, since the amplifier 10 exhibits unity gain. In Fig. 2, as an example only, when measuring values of C₁ and C₂ of the order of 15 picofarads, resistor 14 may have a value of about 6 megohms, resistor 50 a value of about 0.25 megohm, and resistor 57 a value of about 1 megohm. Turning now to Figs. 3 and 4, the manner in which these output signals are processed to derive a signal value representing C₁/C₂ will now be described in detail. Fig. 3 shows schematically a conventional capacitive sensor 100 made up of two capacitor plates 102 and 104 between which is mounted a flexible central plate 106 exposed on one side to a pressure P₁ and on the other side to a pressure P₂. When P₁ and P₂ are equal, the central plate is flat and half way between the two outer plates 102 and 104. When P₁ and P₂ differ, the central plate bows toward one or the other outer plate dependent upon whether P₁ or P₂ is greater, as shown by the curved broken lines in the drawing. In this case C₁ is the capacitance between the central plate 106 and outer plate 102, and C₂ is the capacitance between the central plate and the outer plate 104, the ratio C₁/C₂ being 1 when P₁=P₂ , greater than 1 when the central plate bulges toward outer plate 102, and less than 1 when it bulges toward outer plate 104. Capacitive sensors operating on this principal are well known in the art for measuring fluid pressures, for example. Leads 110, 112 and 114 from the outer plate 102, the central plate 106 and the outer plate 104, respectively, connect C₁ and C₂ to the MMO (multi-mode oscillator) 116 which is shown in detail in Figs. 1 and 2. The overall function of the system of Fig. 3 is to produce an analog signal level on output line 120 which represents the ratio C₁/C₂, which as explained above equals (T₄-T₂)/(T₄-T₁) . The timing and sequencing for the system is controlled by the ACL (Asynchronous Control Logic) 121. Two of the ACL outputs, on lines 126 and 128, are the two bits which control the sequential and repetitive connection of the capacitances C₁ and C₂ into active positions on the frequency-determining circuit of the MMO, in this preferred embodiment thereby producing at an output line 132 of the MMO the three sequential frequencies f₁, f₂ and f₄, as described previously. In order to measure more easily and accurately the periods T₁, T₂ and T₄ of the oscillators at frequencies f₁, f₂ and f₄, it is preferred to divide all such frequencies by a constant factor n, thereby to obtain longer periods T for measurement. In this example it is assumed that a frequency divider 140 divides the frequencies by a factor n=3, before supplying them to the ACL. This scaling-up of the periods T by a factor of 3 is cancelled out in the final output signal from the system. The scheme for forming the numerator T₄-T₂ and the denominator T₄-T₁ is as follows. A capacitor 144 is connected through a switching device 146 to a constant-current source 148 of conventional form. The switching device has four states: one in which the constant-current source charges capacitor 144 with a constant current I c ; a second in which capacitor 144 is discharged (charged negatively) with a constant current -I c ; a third in which the capacitor is open-circuited so as to retain its charge; and a fourth in which the capacitor is short-circuited to reset its charge to zero. Which state it assumes is controlled by the two bits of control information supplied to switching device 146 over lines 150 and 152. When 3T₄ is to be measured (and thereby the period T₄), the control bits place the switching device in its first state in which the initially discharged capacitor 144 is charged by the constant current I c for the time 3T₄ to be measured, and the voltage to which the capacitor charges in that time is a measure of 3T₄. When T₂, or T₁, is to be subtracted from T₄, the control bits change the switching device 146 to its second state in which the capacitor is discharged by the reverse constant current -I c for the duration 3T₁ (or 3T₂) and the voltage in the capacitor decreases from its 3T₄ level to a level representing 3(T₄-T₂) [or 3(T₄-T₁)]. The levels 3(T₄-T₂) and 3(T₄-T₁) are separately supplied to an analog divider 185 which calculates the desired ratio (T₄-T₂)/(T₄-T₁) = C₁/C₂ . The nature and operation of the portion of the system of Fig. 3 which forms the numerator and denominator representing signals will be more easily understood by considering Fig. 3 with relation to the timing diagram of Fig. 4. In Fig. 4, it is assumed that, at time t₁, the capacitor 144 has been reset to zero by being changed to its fourth state by the control bits on lines 150,152, and that at this time the start of a cycle of the f₄/3 signal in the ACL causes switching device 146 to change to its charging state. The signals at f₁, f₂ and f₄ are shown at A in Fig. 4, while the signals at f₁/3, f₂/3 and f₄/3 are shown at B. The value of capacitor 144 is designated as C i . Fig. 4c shows the voltage level on capacitor 144, designated as V ci . At t₁, it begins to be charged with a current I c , and continues to charge linearly upwardly until t₂, when the period 3T₄ ends and the switching device 146 changes to its open-circuit state in which capacitor 144 holds its charge constant at a level proportional to I c T₄/C i . At t₂, the ACL then switches the MMO to its f₂ oscillation frequency (C₂ connected actively), corresponding to a period T₂. The system remains in this state until t₃, allowing the circuits to stabilize at the new frequency f₂. The next pulse of f₂/3 frequency causes switching device 146 to switch to the state in which it supplies a constant current -I c to capacitor 144, thus discharging capacitor 144 until the end of the interval 3T₂, which occurs at t₄. This results in a decrease of the voltage in capacitor 144 by an amount proportional to I c T₂/C i , and accordingly the level on that capacitor at t₄ becomes proportional to I c (T₄-T₂)/C i . The switching device then switches to its open-circuit state in which it remains, holding the latter value of voltage, until the ACL causes the switching device to reset the capacitor 144 to its zero-charge condition at t₅. During the interval t₄ to t₅, the ACL produces the transfer pulse shown at D of Fig. 4, which is applied to a normally non-transmissive gate 172 to render it momentarily transmissive, whereby the voltage level on capacitor 144 representing the numerator of the desired ratio is transferred through a high-input impedance unity-gain non-inverting operational amplifier 176 to a capacitor 180, which stores the present value proportional to I c (T₄-T₂)/C i . The latter stored value is applied through a unity-gain non-inverting operational amplifier 182 to the numerator input terminal of the conventional analog divider 185, which may be a National type LH0094 Multi-Function IC using the logarithmic characteristics of a diode to generate an output voltage proportional to its numerator input divided by its divisor input. After this transfer of voltage to capacitor 180, the resetting of capacitor 144 to zero charge occurs, and the process is repeated except that the interval between t₈ and t₉ in Fig. 4C is proportional to T₁ rather than T₂, so that the voltage level on the capacitor 144 becomes proportional to I c (T₄-T₁)/C i . Also, the latter voltage is passed through a gate 190 during the denominator pulse-shown in Fig. 4E and generated by the ACL, to be stored on a capacitor 194 and supplied through operational amplifier 196 to the denominator input of divider 185, whereby the output of the divider on line 120 becomes (T₄-T₂)/(T₄-T₁) , as desired. In a typical application of the invention, the sensing capacitances C₁ and C₂ have values of the order of tens of picofarads, f₁ and f₂ about 8KHz, and f₄ about 3KHz; if the M₃ mode is used, f₃ may have a value of about 15KHz. In some cases it may be desirable intentionally to include a fixed, continuously-present capacitance in the frequency-determining circuit, for example by connecting a fixed capacitor continuously between the plus input and the output of the unity-gain amplifier 10. This will shift the values of f₁, f₂, f₃ and f₄ downwardly, but the system will still operate as described to produce proper output indications of C₁/C₂; the lumped capacitance acts the same as stray capacitance, and is therefore considered herein as a part of C p . The above described apparatus can just as easily be used to compute the capacitance ratio in the M₃ mode by appropriate substitution of variables T₁, T₂, and T₃. Specifically referring to Fig. 4, if 3T₁ is substituted for the time period t₁ to t₂, 3T₃ for t₃ to t₄, 3T₂ for t₆ to t₇, and 3T₃ for t₈ to t₉, then the resultant output will be (T₁ - T₃)/(T₂ - T₃) as would be desired for M₃ operation. In general the apparatus of Fig. 3 can be used to compute the result of any expression which is in the form of the quotient of two different terms. A useful variation of the M₃ and M₄ expressions is to subtract 1 from them so that the result is zero based. For example, in the design of capacitive pressure sensors, C₁ and C₂ are typically equal at null conditions and the desired output is zero, increasing in a positive direction for positive pressure and decreasing in a negative direction for negative pressure. When 1 is subtracted from either the M₃ or M₄ expressions the resultant general form of the equation remains the same and can thus be computed by the apparatus of Fig. 3 by appropriate substitution of terms. Specifically the zero based expression for M₃ becomes: (T₁ - T₂)/(T₂ - T₃) , and for M₄ becomes: (T₁ - T₂)/(T₄ - T₁) . If it is desired to use the M₃ or M₄ modes in the forms involving frequencies rather than periods [see expressions (1) and (2) above], this is preferably done by using a programmed microprocessor supplied with the several different frequencies produced by the MMO. Such an arrangement is shown in Fig. 5. A multi-mode oscillator 210, connected to C₁ and C₂ as described with reference to Figs. 1, 2 and 3, produces signals of the several different frequencies on its output line 212. The latter signals are supplied to a programmed microprocessor 216, which in turn produces an output signal proportional to C₁/C₂ on its output line 220. Although the arrangement of Fig. 5 can be used to provide operation in only the M₃ mode, or in only the M₄ mode, in this example it is shown as permitting the operator to use either mode M₃ or M₄ as desired. To this end a manually-operable mode switch 222 is provided for actuating the system to either mode; the mode switch is connected to the MMO to cause it to produce either f₁, f₂ and f₃ or f₁, f₂ and f₄, as desired, and simultaneously to switch the microprocessor to the corresponding program for M₃ or M₄. The necessary subtractions, multipiications or divisions necessary to be performed by the microprocessor can be performed by conventional known apparatus and need not be described in detail herein. While the conversion of the output signals of the MMO to signals proportional to their frequencies can be accomplished by analog devices such as phase-locked loop circuits, positioned between MMO and microprocessor, it is preferred to perform this step also in the microprocessor, which is easily and conventionally accomplished, for example by counting the number of clock pulses recurring within a cycle of each signal. It will be appreciated that there are many ways in which the formulae given above can be digitally evaluated by the microprocessor, any of which are satisfactory so long as they produce the proper output value representative of changes in C₁/C₂ .

Claims: A system for producing a signal value representative of the ratio between the capacitance C₁ of a first capacitor and the capacitance C₂ of a second capacitor, characterised in that it comprises: oscillator means having a frequency-determining circuit and oscillating at a frequency which varies substantially inversely proportionally with the total value of capacitance actively connected in said circuit; said frequency-determining circuit inherently including a fixed, continuously-present capacity C P for determining the frequency of oscillations of said oscillator means in the absence of said capacitors C₁ and C₂; said first and second capacitors having four possible combinations in which they could be associated with said frequency-determining circuit, namely: (a) only said first capacitor actively connected in said circuit; (b) only said second capacitor actively connected in said circuit; (c) neither of said first and second capacitors actively connected in said circuit; (d) both said first and second capacitors actively connected in said circuit; means for associating said first and second capacitors with said frequency-determining circuit in said combination (a) at a first time, to produce oscillations at a first frequency f₁, and for associating said first and second capacitors with said circuit at a second time in said combination (b), to produce oscillations at a second frequency f₂; means for associating said first and second capacitors with said frequency-determining circuit at a third time in one of said combinations (c) and (d), to produce oscillations at one of two corresponding different frequencies f₃ and f₄; and means responsive to said oscillations at frequencies f₁, f₂ and one of said frequencies f₃ and f₄ to produce signal values representative of the values of said ratio between C₁ and C₂, substantially undistorted by the effects of said fixed capacitance C p . The system of Claim 1, wherein said capacitors C₁ and C₂ are associated with said frequency-determining circuit in said combinations (a), (b) and (c), and said means responsive to said osciliations produces signal values representative of (T₁-T₃)/(T₂-T₃) , where T₁, T₂ and T₃ are the periods of the cycles of oscillations at frequencies f₁, f₂ and f₃, respectively. The system of Claim 1, wherein said capacitors C₁ and C₂ are associated with said frequency-determining circuit in said combinations (a), (b) and (d), and said means responsive to said oscillations produces signal values representative of (T₄-T₂)/(T₄-T₁) , where T₁, T₂ and T₄ are the periods of the cycles of oscillations at frequencies f₁, f₂ and f₄, respectively. A system according to any preceding claim, wherein the oscillator means comprises an inverting hysteresis circuit (12) with its output fed back to its input through a non-inverting amplifier (10) having unity gain.

Inventors: CHANG CHIH CHEN, CHANG, CHIH CHEN
Applicants: MOORE PRODUCTS CO, MOORE PRODUCTS CO.
Application year: 1988
Main classification: G01R27
IPC codes: G01R27, H03K3