Circuit for detecting a synchronizing signal

Abstract: A circuit for detecting a synchronizing signal comprises a gate circuit (35) to which reproduced synchronizing signal (SYNC) and window signal (LMASK) are supplied. A first counter (36, 40) which is synchronized with output signal (MSYNC) from the gate circuit (35) counts a clock signal (PLC) formed from reproducing signal and generates an insertion synchronizing signal (ISYNC). A second counter (37, 41) which is synchronized with output signal from the gate circuit (35) counts a fixed clock signal (FIC) and generates the window signal (LMASK). The output signal (MSYNC) from the gate circuit (35) or the insertion syn­ chronizing signal (ISYNC) is made a synchronizing detection signal thereby the frame synchronizing signal can be detected stably.

Description: The present invention relates to a circuit for detecting a synchronizing signal. In the prior art, an apparatus for reproducing digital audio data recorded in an optical disk is known as an example to which a circuit for detecting a synchronizing signal according to the invention can be applied. Reproduced signal of the digital audio data has frame structure divided by frame synchronizing signal. The reproduced signal is subjected to the EFM (Eight-Fourteen) modulation, and in order to demodulate this, data within the frame must be distinguished with respect to the frame synchronizing signal. Therefore a circuit for detecting a sinchronizing signal is installed. As a matter of fact, the reproduced signal from the disk may include signal similar to the frame synchronizing signal generated due to flaw of the disk or the like, or lack of the frame synchronizing signal may be produced. In order to deal with this problem, a protection circuit of the frame synchronizing signal is required. In such a detection and protection circuit of synchronizing signal, for example, as disclosed in Jananese patent application laid-open No. 58-98813, protection by window is performed in order to prevent detection of the signal other than the frame synchronizing signal from being mistaken for the synchronizing signal, and insertion protection is performed in order to deal with the lacking of the frame synchronizing signal. Also, if the insertion protection continues prescribed times, the window is opened until the reproduced synchronising signal is obtained. When the window is opened, if the reproduced synchronizing signal is obtained, the window is immediately closed. In the detection and protection circuit of synchronizing signal in the prior art, however, bit clock formed in PLL is used to form the window signal. Since the bit clock is synchronous with reproduced signal, it varies following also the reproduced signal disturbed by flaw of the disk or the like. As a result, if the window is closed by in correct reproduced synchronizing signal, the timing of the window signal may be shifted, even when the correct frame synchronizing signal is obtained. From the EP-A-0096885 a synchronizing circuit for detecting and interpolating sync signals is known. The synchronizing circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect the sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signal and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit in a case where noise is output from the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter. A digital data synchronizing circuit is disclosed in the GB-A-2109203. According to the disclosure a circuit for reproducing a signal is associated with synchronization with a digital data signal. The digital data signal includes a combination of a plurality of pulses each having a predetermined pulse width. The reproducing circuit comprises a logic circuit for discriminating the pulse width of at least one of the plurality of pulses, an oscillator and a frequency divider connected with the oscillator and responsive to the output of the logic circuit to generate a clock signal timed with the output of the logic circuit. The object of the invention is to provide a circuit for detecting a synchronizing signal wherein the detection of the frame synchronizing signal can be performed stably. The object of the invention is solved by the features of claim 1. A further advantageous developement of the invention is given by claim 2. An embodiment of the invention is described hereafter with relation to the drawing, in which: FIG. 1 is a schematic diagram illustrating frame constitution of reproduced signal of digital audio data; FIG. 2 is a block diagram illustrating an example of an apparatus for reproducing digital audio data to which a circuit for detecting a synchronizing signal according to the invention can be applied; FIG. 3 is a block diagram illustrating an embodiment of a frame synchronizing detecting circuit according to the invention; and FIG. 4A - 4K and FIG. 5A - 5K are timing charts illustrating operation of the frame synchronizing detecting circuit shown in Fig. 3. An embodiment of a circuit for detecting a synchronizing signal according to the invention will now be described referring to the accompanying drawings. First, referring to FIG. 1, frame constitution of modulated digital audio data recorded in an optical disk will be described. Frame synchronizing signal of 24-channel bits is positioned on the front of one frame, and one symbol of subcode for control and indication is positioned to the next. Subsequently, a PCM audio signal of 12 symbols, parity of 4 symbols of error correction code, a PCM audio signal of 12 symbols and parity of 4 symbols are positioned in sequence. One symbol is composed of 14-channel bits. Between each symbol and the frame synchronizing signal are inserted margin bits of each 3-channel bit to couple these, therefore 34-margin bits exist per one frame. Consequently, one frame is constituted by 588-channel bits. This frame constitution is as well known already, and the detailed description shall be omitted. FIG. 2 shows an example of a player of an optical disk where digital audio data having the above-mentioned frame constitution is recorded. Modulated digital audio data reproduced from an optical disk 1 by an optical pickup 2 is supplied to a reproducing amplifier 3. Output signal of the reproducing amplifier 3 is supplied to a clock extraction circuit 4 constituted by PLL. Reproduced data signal and bit clock from the clock extraction circuit 4 are supplied to a frame synchronizing signal detection and protection circuit 5. The frame synchronizing signal detection and protection circuit 5 detects frame synchronizing signal and protect the detected frame synchronizing signal as hereinafter described. An EFM demodulating circuit 6 is installed on output of the frame synchronizing signal detection and protection circuit 5. The EFM modulation is channel coding which converts patterns of 8 bits of one symbol into prescribed patterns of 14-channel bits which can decrease the DC component and facilitate the extraction of the bit clock. Demodulated data with one symbol returned into 8 data bits by the EFM demodulator 6 is supplied to a decoder 7. In the decoder 7, error correction code called cross interleave read solomon code is decoded thereby error correction is performed. A memory 8 in which the demodulated data is written for deinterleaving or the like is installed in relation to the decoder 7. Signal indicating that frame synchronization is not locked due to track jump or the like is supplied from the frame synchronizing signal detection and protection circuit 5 to the decoder 7. Decoded digital audio data outputted from the decoder 7 is supplied to a data interpolation circuit 9. In the data interpolation circuit 9, interpolation such as mean value interpolation, previous value hold or the like is performed regarding the error data which could not be corrected by the decoder 7. Output signal of the data interpolation circuit 9 is supplied to D/A converters 10L and 10R, and respective output signals of these D/A converters 10L and 10R are taken as analog audio signal through low pass filters 11L and 11R to output terminals 12L and 12R. A subcode decoder 13 is installed on output side of the frame synchronizing signal detection and protection circuit 5. Subcode data obtained from the subcode decoder 13 is supplied to a system controller 14. An operation member 15 and an indicator 16 are installed in relation to the system controller 14. A motor 17 to rotate the optical disk 1 is driven in CLV (Constant Line Velocity, by a spindle servo circuit 18. A feed servo circuit 19, a tracking servo circuit 20 and a focus servo circuit 21 are installed in relation to the optical pickup 2. As above described, the player of the optical disk also is well known already, and further description shall be omitted. FIG. 3 shows an example of the frame synchronizing and detection and protection circuit 5. Reproduced data signal EFMX from a data input terminal 32 is taken in a shift register 31 by bit clock PLC supplied to a clock input terminal 33 and extracted from the reproduced data signal EFMX by the clock extraction circuit 4. The shift register 31 is of 23 bits, and output signal of the shift register 31 is supplied to a frame synchronizing detecting circuit 34. The frame synchronizing detection circuit 34 can detect frame synchronizing signal of prescribed bit pattern. Reproduced synchronizing signal SYNC from the synchronizing detection circuit 34 is supplied to the AND gate 35. Other input of the AND gate 35 is supplied with window signal mask MASK as described hereinafter, and detected synchronizing signal MSYNC is outputted. On the other hand, counters 36 and 37 are constituted by counters of mod. 588 respectively. The counter 36 counts clock PLC from a terminal 38, and the counter 37 counts clock FIC from a terminal 39. The clock FIC is a fixed stable clock formed, for example, by a crystal oscillation circuit (not shown). Frequency of the clock FIG is 4.3218 MHz being equal to the center frequency of the clock PLC. Output of the counters 36 and 37 are supplied to decoders 40 and 41 respectively. Insertion synchronizing signal ISYNC is generated from the decoder 40 every time the output of the counter 36 becomes 588, and window signal LMASK which becomes "1" in width of ±8 clock about the timing of the output of the counter 37 becoming 588 is generated from the decoder 41. The counters 36 and 37 are reset by detected synchronizing signal MSYNC from the AND gate 35. The detected synchronizing signal MSYNC is supplied to an AND gate 42 and an inverter 43. Output signal of the inverter 43 is supplied to an AND gate 44. Insertion synchronizing signal ISYNC from a decoder 40 is supplied to these AND gates 42 and 44. Signal GDSY is taken from the AND gate 42, and signal NGSY is taken from the AND gate 44. The signal GDSY is that obtained when the detected synchronizing signal MSYNC and the insertion synchronizing signal ISYNC are generated simultaneously. The signal NGSY is that obtained when the insertion synchronizing signal ISYNC is generated but the detected synchronizing signal MSYNC is not generated. Also an RS flipflop 45 which is set and reset by these signals GDSY and NGSY is installed, and signal GFS is taken from the RS flipflop 45. The signal GFS represents that while this signal is outputted the correct frame synchronizing signal is obtained, and is supplied to a system controller or the like. The insertion synchronizing signal ISYNC from the decoder 40 and the detected synchronizing signal MSYNC from the AND gate 35 are supplied to an OR gate 46, and reset signal RESET is taken to an output terminal 47. The reset signal RESET is output signal to specify the timing corresponding to the frame synchronizing signal in the reproduced data signal. That is, each symbol of the reproduced data signal EFM is separated by data clock with respect to the reset signal RESET. As shown in FIG. 3, signal GDSY from the AND gate 42 is supplied as clock input to an N1 counter 48. Signal NGSY from the AND gate 44 is supplied as clock input to an N2 counter 49. Carry output of the N1 counter 48 is made reset input of itself through an OR gate 50, and also made reset input of an RS flipflop 52. Carry output of the N2 counter 49 is made reset input of itself through an OR gate 51, and supplied to an OR gate 53. Detected synchronizing signal MSYNC from the AND gate 35 is supplied as other input of the OR gate 51. Output signal of an AND gate 54 and signal from a terminal 55 are supplied to the OR gate 53. The output signal GDF of the RS flipflop 52 and the signal NGSY from the AND gate 44 are supplied to the AND gate 54. The signal from the terminal 55 is that becoming "1" when tracking error or the like is generated. Output signal of the OR gate 53 is supplied as respective set inputs to SR flipflops 52 and 56, and made reset input of the N1 counter 48 through the OR gate 54. The detected synchronizing signal MSYNC from the AND gate 35 is supplied as reset input of the RS flipflop 56. Signal GTOP obtained on output of the RS flipflop 56 is supplied to an OR gate 57. Window signal LMASK from the decoder 41 is supplied to the OR gate 57. The N1 counter 48 is installed for such a protection as to detect that the signal GDSY is generated N1 times, i.e., that detection of the frame synchronization is locked. On the other hand, the N2 counter 49 is installed for such a protection as to detect that the signal NGSY is generated N2 times, i.e., that the lock is failed. For example, it is set that (N1 = 2) and (N2 = 3). FIG. 4A - 4K is a timing chart illustrating the operation of the embodiment when the detected synchronizing signal is detected correctly. FIG. 4A shows the reproduced synchronizing signal SYNC from the frame synchronizing detection circuit 34. FIG. 4B shows the window signal MASK supplied to the AND gate 35. Since the signal GTOP shown in FIG. 4J is "0" usually, the window signal LMASK in width of ±8 clocks from the decoder 41 becomes the window signal MASK. Consequently, the detected synchronizing signal MSYNC as shown in FIG. 4C is obtained correctly. Since the clock PLC has jitter, if the detected synchronizing signal MSYNC is reset before the counter 36 counts 588, the insertion synchronizing signal is not obtained. On the contrary, if the counter 36 counts 588 before reset by the detected synchronizing signal MSYNC, the insertion synchronizing signal ISYNC is outputted slightly early. Consequently, as shown in FIG. 4D, the insertion synchronizing signal ISYNC includes bit slip with period being different from normal one or disappearance. From the detected synchronizing signal MSYNC and the insertion synchronizing signal ISYNC, the signal GDSY being output of the AND gate 42 shown in FIG. 4E and the signal NGSY being output of the AND gate 44 shown in FIG. 4F are formed. If the detected synchronizing signal MSYNC and the insertion synchronizing signal ISYNC are coincident in the timing with the high frequency, as shown in FIG. 4G, the counter 48 to count the signal GDSY counts to 2 of the count value and therefore is reset by the carry output and also the RS flipflop 52 is reset. Consequently, the output signal GDF of the RS flipflop is "0" as shown in FIG. 4I and therefore the AND gate 54 is not opened. Even if the signal NGSY is generated occasionally, since the N2 counter 49 does not count to 3 as shown in FIG. 4H and is reset by the detection synchronizing signal MSYNC, the carry output is not generated. Consequently, the RS flipflop 56 is not set, and since the output signal GTOP is "0" as shown in FIG. 4J, the window signal MASK is not opened and therefore incorrect synchronizing signal is not detected. Since the insertion synchronizing signal ISYNC and the detected synchronizing signal MSYNC are supplied to the OR gate 46 shown in FIG. 3, the reset signal RESET shown in FIG. 4K is taken to the output terminal 47. If both the insertion synchronizing signal ISYNC and the detected synchronizing signal MSYNC are produced in the reset signal RESET, the period between the insertion synchronizing signal ISYNC and the detected synchronizing signal MSYNC becomes period of burst error. However, the period of the burst error is relatively short, and therefore can be corrected by the error correction code of the digital audio disk. FIG. 5A - 5K is a timing chart illustrating the operation in the embodiment when the reproduced synchronizing signal cannot be detected correctly due to the track jump or the like. As shown in FIG. 5A, if the reproduced synchronizing signal SYNC disappears continuously as indicated by "a" or is generated at the position shifted from the window signal MASK, every time the counter 36 counts 588, the insertion synchronizing signal ISYNC is obtained from the decoder 40, and reset signal RESET shown in FIG. 5K is obtained at the output terminal 47 of the OR gate 46 shown in FIG. 3B. However, if the detected synchronizing signal MSYNC is not obtained, as shown in FIG. 5E, F, the signal GDSY from the AND gate 42 disappears and only the signal NGSY from the AND gate 44 is outputted. Consequently, the N1 counter 48 is not incremented as shown in FIG. 5G and only the N2 counter 49 is incremented as shown in FIG. 5H, and if it counts to 3, the carry output is generated and the RS flipflops 52 and 56 are set through the OR gate 53. Consequently, respective output signals GDF, GTOP become "1" as shown in FIG. 5I, 5J, and the window signal MASK is opened by the signal GTOP until the detected synchronizing signal MSYNC is obtained. In this case, if the reproduced synchronizing signal SYNC is generated as indicated by symbol x in FIG. 5A, since the detected synchronizing signal MSYNC is outputted from the AND gate 35, the N2 counter 49 is reset through the OR gate 51, and the RS flipflop 56 is also reset and the output signal GTOP becomes "0" as shown in FIG. 5J. Since the counter 37 is also reset by the detected synchronizing signal MSYNC, rear half of the window signal LMASK in width of +8 clocks is outputted from the decoder 41 and the window signal MASK is outputted through the OR gate 57. Consequently, if the detected synchronizing signal MSYNC is obtained, the window signal MASK is closed after 8 clocks. However, when the reproduced synchronizing signal SYNC is not correct, if the window signal MASK is formed only by the window signal LMASK afterwards, the correct reproduced synchronizing signal SYNC being may remain undetected. Consequently, even if the reproduced synchronizing signal SYNC is detected, it is not trusted but the RS flipflop 52 is held to the set state until the GDSY from the AND gate 42 is generated three times. Consequently, if the NGSY from the AND gate 44 is generated even one time, the RS flipflop 56 is again reset through the AND gate 54 and the OR gate 53, and the window signal MASK is opened. Thus the correct reproduced synchronizing signal SYNC is obtained, and if the signal GDSY is obtained two times from the AND gate 42, the carry output is generated from the N1 counter 48 and the RS flipflop 52 is reset and the output signal GDF becomes "0" as shown in FIG. 5I, and subsequently the operation is returned to the state shown in FIG. 4A - 4K. The reset signal RESET as shown in FIG. 5K is taken to the output terminal 47 of the OR gate 46. The burst error is produced during the period of the signal GTOP being "1". The error period can be reduced. As clearly understood from the above description of operation, the N1 counter 48 performs operation of such a protection as to detect that the detecting operation of frame synchronization is returned to normal, and the N2 counter 49 performs operation of such a protection as to detect that the detecting operation of the frame synchronization is mistaken. The protection of both can detect rapidly that the detecting operation of frame synchronization becomes abnormal, and that the detecting operation is returned to normal. According to the embodiments, since the counter counts the fixed clock signal and therefore forms the window signal, the window signal is generated in the prescribed timing which is not affected by bit clock extracted from the regenerative signal. Consequently, when the normal frame synchronizing signal is generated, the frame synchronizing signal can be detected securely.

Claims: A circuit for detecting a synchronizing signal comprising: a gate circuit (35) supplied with a reproduced synchronizing signal (SYNC) and a window signal (LMASK); first counter means (36, 37, 40, 41) synchronized with an output signal (MSYNC) from said gate circuit (35) and for counting a clock signal (FIG) so as to generate an insertion synchronizing signal (ISYNC) and the window signal (LMASK); means (46) for generating a synchronizing detection signal (RESET) based on the output signal form said gate circuit (35) or the insertion synchronizing signal; characterized by means (42, 43, 44) for generating coincidence signal (GDSY) and uncoincidence signal (NGSY) respectively representing coincidence and uncoincidence between the output signal of said gate circuit (35) and the insertion synchronizing signal (ISYNC); second counter means (49, 51) for counting the uncoincidence signal (NGSY) to detect, if the uncoincidence signal (NGSY) is generated for a first predetermined number indicating that the lock of the synchronizing signal is failed, whereby the second counter means (49, 51) are reset at least by the output signal (MSYNC) of the gate circuit (35); third counter means (48, 50) for counting the coincidence signal (GDSY) to detect, if the coincidence signal (GDSY) is generated for a second predetermined number indicating that the synchronizing signal is locked, whereby the third counter means (48, 50) are reset at least by the output of second counter means (49, 51) if the second counter means (49, 51) have reached the first predetermined number; and control means (52, 53, 54, 56, 57) to control the period of the window signal (LMASK) by generating a control signal (GTOP), which is combined with the window signal (LMASK) by a logical OR-combination, whereby the control signal (GTOP) is set by the uncoincidence signal (NGSY), if the second counter means (49, 51) have reached the first predetermined number before the third counter means (48, 50) have reached the second predetermined number, and the control signal (GTOP) is reset by the output signal (MSYNC) of the gate circuit (35). A circuit for detecting a synchronizing signal according to claim 1 characterized in that the control circuit comprises a first RS flipflop (52), which reset terminal is connected to the most significant bit of the third counter means (48, 50); a AND gate (54), which first input terminal is supplied with the uncoincidence signal (NGSY) and which second input terminal is connected to the output of the first RS flipflop (52); a first OR gate (53) with a first input terminal connected to the output of the AND gate (54) and a second input terminal connected to the most significant bit of the second counter means (49, 51), whereby the set terminal of the first RS flipflop (52) is connected to the output of the first OR gate (53); a second RS flipflop (56), which set terminal is connected to the output of the first OR gate (53) and which reset terminal is supplied with the output signal (MSYNC) of the gate circuit (35); and a second OR gate (57) with a first input terminal supplied with the window signal (LMASK) and a second input terminal connected to the output of the second RS flipflop (56).

Inventors: KURODA HIROKAZU C O SONY CORPO, SHIMIZUME KAZUTOSHI C O SONY C, KURODA, HIROKAZU C/O SONY CORPORATION, SHIMIZUME, KAZUTOSHI C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: G11B20
IPC codes: G11B20, G11B27, H03L7