Bus structure for integrated circuit chip

Abstract: An integrated circuit chip comprising plural gates (12) connected in parallel to a power supply network (V+) by a first bus (14) which extends from a bonding pad (18) and which is disposed adjacent said gates, and a second bus (16) having a portion disposed parallel to and adjacent said portion of said first bus, wherein - in order to control the voltage drop along ground and power buses - at least a portion of said first bus lying adjacent said gates has a width which decreases with increasing distance from said bonding pad in proportion to the magnitude of the current conducted in the bus; said portion of said second bus has a width which increases in a manner complementary to the width of said portion of said first bus and in proportion to the magnitude of current conducted in said second bus; and said gates are connected in parallel to each of said first and second buses.

Description: The present invention is directed to large scale integrated circuit chips, and more particularly to wiring arrangements for such chips that provide for more uniform voltage distribution to the gates on the chip. It is an object of the present invention to provide a uniform distribution of voltage to the individual gates on a chip so that each gate receives the same amount of current. The present invention addresses this object by the features cited in claim 1; the dependent claims refer to preferred embodiments of the concept of claim 1. The present invention is closely related to the wiring technique disclosed and claimed by co-granted European Patent 138 650 which also explains in detail why it is desirable to locate the supply bond pads adjacent to one another. EP-A-74 825 discloses a wiring scheme for a gate array wherein the width of a supply line feeding a plurality of juxtaposed cells decreases from both of its ends towards the middle. In this way, the supply of sufficient voltage for the unitcells can be maintained at the middle of the IC whilst the area available for interconnections is increased. The attached drawing illustrates in plan view an embodiment of the present invention. In accordance with the present invention, the voltage gradient in the power and ground busses is controlled so that the same amount of current flows through each of the logic gates, or stages. Since the resistance to flow of a current is proportional to the length of a conductor through which the current must flow, it will be appreciated that a voltage gradient will be established along each of the power and ground busses. If this voltage gradient is not controlled or otherwise accounted for in the design of the chip, it is possible that different magnitudes of current will flow through the various logic gates connected along the lengths of the power and ground busses. In some circumstances, a current differential between gates could lead to logic errors or other failures. For example, in integrated injection logic the current in a grounded emitter switching transistor or in a grounded base current injector transistor can be exponentially proportional to the voltage difference between the power and ground busses. Thus, it is desirable to have the same voltage difference between these two busses for each logic gate connected thereto, so that all gates will operate with the same amount of current. In furtherance of this objective, two basic principles are employed in the design of the power and ground busses. First, the direction of current flow is the same in both busses at their points of connection to the gates. With this approach, the combined lengths of the power and ground busses through which the current must flow is the same for every gate. Referring to the Figure, the direction of current flow in the power bus 14 is from left to right as viewed in the Figure. Similarly, the current flows in the same direction in that portion of the ground bus 16 which is connected to the gates 12. Thus referring to the extreme left- and right-hand gates G1 and G6 shown in the Figure, the current path in the power bus 16 for current supplied to the right-hand gate G6 exceeds that for the left-hand gate G1 by five unit lengths, with a unit conductor length ℓ in this case being equal to the distance between the connections of two adjacent gates to the power bus. However, in the ground bus, the current path for current from the right-hand gate G6 is shorter than that for the left-hand gate G1 by the same five unit lengths. The same relationship holds true for all other pairs of gates. Thus, the total current path from the power bonding pad to the ground bonding pad is the same for all gates connected to the power and ground busses. In order to enable the power and ground bonding pads to be located physically adjacent one another the ground bus 16 is looped back on itself after the last connection in the direction of current flow. Although this return portion of the ground conductor is illustrated as being located in the gates, it will be appreciated that it can overlay the connection portion of the ground bus in a separate layer. The second design principle that is employed to control the voltage gradient relates to the cross-sectional area of the busses. More particularly, the cross-sectional area of each unit length is proportional to the amount of current carried by that unit length. The width of each of the power and ground busses is stepped so that each conductor is widest where the magnitude of current is greatest and narrowest where the current is smallest. With this arrangement, the current density in each conductor is constant throughout the length of the conductor. Therefore, the voltage drop along each unit length of the conductors will be the same, so that the voltage gradient from gate to gate is uniform. Typically, the height of each conductor will remain the same throughout the entirety of its length, due to the metallization process that is employed to deposit the metal layer on the substrate. Therefore, the control of the cross-sectional area of the conductor is obtained by regulating its width. In other words, the width of each unit length of the conductors is proportional to the current carried in that portion of the conductor. As illustrated, the variation in the width of each conductor is provided by means of discrete steps located along the length of the conductor. Although it is alternatively possible to employ a uniform taper along the length of the conductor, the discrete step approach is preferred because it lends itself more readily to computer-aided design (CAD) of integrated circuit chips. Furthermore, the changes in current magnitude within the conductor occur at discrete points, i.e. the points where the gates are connected, rather than continuously. Thus, it is most logical to locate the changes in width of the conductor commensurate with the increments of load along the busses. Since the current flows in the same direction in both the power and ground busses at their points of connection to the gates, the width changes of these two busses are complementary to one another. Consequently, it is possible to "nest" the two conductors with one another, achieving a savings in space on the surface of the chip. More particularly, the total width of the area occupied by the two busses along the portion of their lengths which is connected to the gates comprises the width of one of the busses at its widest point, the distance of the spacing between the conductors, and the width of the other conductor at its narrowest point. In contrast, two busses of constant width would occupy an area having a width equal to their total width plus the space between them. The control of the voltage gradient across the gates has been described thus far with respect to the power and ground busses. It will be appreciated that the foregoing principles should be applied to all conductors which carry current to or from the gates. For example, as illustrated the current is conducted between each gate 12 and the busses 14 and 16 by means of a second set of conductors 50 and 52. The total length of the current path along these conductors should also be the same for each gate. To this end, the conductor 50 to the power bus 14 is connected to this bus along its edge that is closest to the gates, since that edge is the same distance from each gate. Conversely, the conductor 52 to the ground bus 16 is connected to the edge of bus that is farthest from the gates, since this edge is also a constant distance from each gate. Thus, each pair of conductors 50 and 52 has the same length for all gates. It is not necessary that the conductors 50 and 52 be connected to the edges of the busses, or that all conductors connected between one of the busses and the various gates have the same length. Rather, the criterion that is controlling is that the total current path from the power source to the ground reference be the same for each gate.

Claims: An integrated circuit chip comprising plural gates (12) connected in parallel to a power supply network (V+, GND) including a first bus (14) extending from a current supply bond pad (18) and having a first portion adjacent said gates and including further a second bus (16) connected to a current sinking bond pad and having a first portion extending adjacent and parallel to said first portion of said first bus, characterized in that said first portion of said first bus has a width which decreases with increasing distance from said bond pad in proportion to the magnitude of current conducted in said first bus, and that said first portion of said second bus has a width which increases in a manner complementary to the width of said first portion of said first bus and in proportion to the magnitude of current conducted in said second bus. The integrated circuit chip of claim 1 wherein said first portion of said first and second buses have stepped widths, and wherein each gate is connected to said buses by conductors connected to said buses at locations adjacent an allocated step in the bus width. The integrated circuit chip of claim 2 wherein all of the conductors connecting the gates to said first bus have the same length and all of the conductors connecting the gates to the second bus have the same length. The integrated circuit chip of claim 2 wherein the total length of the pair of conductors which respectively connect a gate to said first and second buses is the same for each gate. The integrated circuit chip of claim 2 wherein said second bus has a second portion connecting said first portion to said current sinking bond pad disposed adjacent said current supply bond pad. The integrated circuit chip of claim 5 wherein said second portion of said second bus is disposed on a different layer of said chip than said first bus and said first portion of said second bus and overlies said first bus and said first portion of said second bus. The integrated circuit chip of claim 5 wherein said bond pads are successive pads located along an edge of the chip.

Inventors: EARLY JAMES M, EARLY, JAMES M.
Applicants: FAIRCHILD SEMICONDUCTOR, FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1988
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L23