METHOD OF ERASING LIQUID CRYSTAL DISPLAY AND AN ERASING CIRCUIT

Abstract: When the display is to be erased from active matrix-type liquid crystal display elements which have a source bus drive circuit (16) and a gate bus drive circuit (17), pixel signals for turning the pixels off are supplied in an amount of one line to the source bus drive circuit and, at the same time, a clear signal (CL) is given to a gate bus drive circuit (17) to apply a voltage simultaneously to all gate buses (151 to 15m) to turn on the transistors (13) in all of the pixels. Provision is made of a power source holding circuit (22) for holding the power of the power source (V1) supplied to the gate bus drive circuit (17) for a predetermined period of time even after the power source is turned off, and a voltage drop detect circuit (24) for detecting the turn-off of the power source. A clear signal (CL) is produced in response to the detect signal and is sent to the gate bus drive circuit (17). In response to the clear signal, the gate bus drive circuit supplies a voltage for turning on the transistors (13) of all pixels simultaneously to all of the gate buses to erase the display in a short period of time after the power source is turned off.

Description: TECHNICAL FIELD The present invention relates to a method and a circuit for erasing a display of an active matrix type liquid crystal display cell having a capacitive storage effect. TECHNICAL BACKGROUND While an active matrix type liquid crystal display cell having a plurality of pixels each being controlled via a respective thin film transistor is disclosed in EP-A-0 035 382, a brief description will be given first, with reference to Fig. 1, of a typical prior art active matrix type liquid crystal display cell which has a capacitive storage effect. Fig. 1 shows a liquid crystal display panel 10 in which display pixels 12 are arranged in the form of a matrix (with m rows and n columns) and their display electrodes 12a are connected to drains of TFTs (Thin Film Transistors) 13, respectively. The TFTs 13 have their sources and gates connected to those of perpendicularly intersecting source buses 14₁ to 14 n and gate buses 15 which correspond to them, respectively. The display pixels 12 each include a counter electrode (also referred to as a common electrode) 12b disposed opposite the display electrode 12a. A source bus drive circuit 16 is provided for driving the source buses 14₁ through 14 n . From a main body (not shown) of the liquid crystal display device the source bus drive circuit is supplied with a pixel clock PCK, a horizontal synchronizing signal Hs and a control signal M for converting the power supply voltage into an AC form, such as shown in Fig. 2, and pixel data (a binary code representing logic "1" or "0") D which is applied in the horizontal direction in synchronism with the pixel clock PCK, though not shown. In the source bus drive circuit 16 the pixel data D of one row are sequentially loaded into a shift register 16a in synchronism with the pixel clock PCK, and in correspondence to the pixel data D, signals S₁ to S n to be displayed on the pixels of one row of the liquid crystal display panel 10 are simultaneously provided on the source buses 14₁ to 14 n upon each occurrence of the horizontal synchronizing signal Hs. The signals S₁ to S n are also called source bus drive signals, and they have voltages E₁ and E₂ (in the case of a field M = 1) or E₂ and E₃ (in the case of a field M = 0) depending upon the logic "1" and "0" of the pixel data D, as shown in Fig. 2D in which one signal S j is exemplified. Here, E₂ = (E₁ + E₃)/2. The source bus drive circuit 16 operates on the DC voltages E₁, E₂ and E₃ and a common potential EG (zero volt) from the main body of the liquid crystal display device. The liquid crystal display panel 10 is also supplied with the common potential EG from the main body of the display device and the counter electrodes 12b of the respective pixels are each supplied with a voltage corresponding to the voltage E₂. The common potential EG (zero volt) and the voltages E₁, E₂ and E₃ are selected such that E₁ > EG > E₂ > E₃, for instance. A gate bus drive circuit 17 drives the gate buses 15₁ to 15 m high-level one after another upon each occurrence of the horizontal synchronizing signal Hs, thereby turning ON the TFTs of one row from the first to the mth row in a sequential order. As a result of this, the source bus drive signals S₁ to S n are applied to the corresponding pixels, respectively. The gate bus drive circuit is made up principally of an m-stage shift register 18 and a gate bus driver 19. A vertical synchronizing signal Vs (Fig. 2E) is applied, as a start signal, to a data terminal D of the first-stage shift register, and the horizontal synchronizing signal Hs is applied to a clock terminal CK of each stage. Pulses, which result from sequential delaying of the start signal for the horizontal synchronizing signal period, are provided from output terminals Q of the respective stages to the gate bus driver 19. In the gate bus driver 19 the input pulses are converted in level, providing on the gate buses 15₁ to 15 m gate bus drive signals G₁ to G m (Fig. 2F) each of which has a voltage level V₁ or V₃ depending on whether the input pulse from the corresponding stage is high- or low-level. From the main body of the device the power supply voltages V₁ and V₂ are supplied to the shift register 18 and the gate bus driver 19 and the power supply voltage V₃ is supplied to the gate bus driver 19. These voltages are selected such that V₁ > V₂ > V₃, and in many cases, V₁ - V₂ = 5 volts. To clear a display at a desired time, pixel data for one field (m rows) which have logic "0" for erasing displays of respective pixels are provided from the main body of the device, and upon each occurrence of the horizontal synchronizing signal Hs, voltage E₂ signals for m rows are simultaneously applied from the source bus drive circuit 16 to the source buses 14₁ through 14 n and the gate buses 15₁ through 15 m are sequentially driven high-level by the gate bus driver 19, whereby the display of one field is cleared. That is, clearing of one field display needs a time mT H (where T H is the cycle of the horizontal synchronizing signal) at the shortest. This is not preferable because, for example, when the liquid crystal display panel 10 is used with a computer, the higher the display-clearing frequency, the longer the time for which the computer is occupied. To stop the display device from the display operation, it is customary to turn OFF the power supply switch of the display device main body without involving any particular display clearing operation mentioned above. Upon turning OFF the switch, various signals provided to the liquid crystal display panel disappear and various power supply voltages also drop to the common potential (the ground potential) within a short time. The output G i of the gate bus driver also disappears and drops to the common potential. Consequently, all the TFTs 13 of the liquid crystal display panel 10 are turned OFF, and charges stored in pixel capacitances remain undischarged for a relatively long period of time, because their external discharge paths are cut off. This allows residual images to remain on the display screen, impairing the display quality. Furthermore, to leave the pixels stored with charges as mentioned above means that DC voltage remains unremoved from the liquid crystal, shortening its life and lowering its reliability. The document US-A-4,380,008 discloses a method of driving a matrix type liquid crystal display panel having a plurality of Y- or column electrodes and a plurality of X- or row electrodes. To display an image the row electrodes are sequentially driven while at the same time the picture signals corresponding to the driven row are applied to the column electrodes. Before a part of the picture or the whole picture is rewritten, the corresponding part or all of the picture is erased. To that end, all of the column lines and all row lines involved are simultaneously supplied with a zero voltage. The document JP-A-62 165 630 discloses an erasing circuit for erasing a display on a matrix type liquid crystal display device. The purpose of this prior art is to avoid an unnecessary display during non-use of the display device by erasing the display upon detection that a power source is turned off. In this prior art, the smoothing capacitor normally included in a power source is increased to provide a power holding function after the power source has been turned off. A power-off detector detects the moment of turning off the power source and delivers a control signal immediately to a display controller. The display controller controls a driver for driving row electrodes and a driver for driving column electrodes such that the row electrodes are successively activated while erasing signals are applied to the column electrodes so that the electric field applied to the liquid crystal is made zero. The document JP-A-61 162 029 discloses a circuit arrangement used to prevent a liquid crystal display element from having an abnormal voltage applied at the moment when the power source to the element is turned off. A liquid crystal driver is connected through a diode and power supply switch to a DC power source, and a capacitor is connected between the power supply terminal of the liquid crystal driver and earth, thus forming a power holding circuit. After switching off the power supply switch, the voltage applied from the capacitor to the liquid crystal driver gradually decreases at a relatively large time constant, so that the driver circuit continues its operation. An input terminal of the liquid crystal driver is connected to the node between the power supply switch and the diode, so that the voltage applied to this input terminal quickly decreases after the power supply switch has been turned off. Upon detecting this voltage decrease, the driver stops supplying a driving voltage wave to the liquid crystal display element. It is an object of the present invention to provide a method and a liquid crystal display erasing circuit which permit clearing of a residual image in a short time upon turning off the power supply of a display device and prevent shortening the life of a liquid crystal and lowering its reliability. This object is achieved with a method and a liquid crystal display erasing circuit as claimed in claims 1 and 2, respectively. Preferred embodiments of the invention are subject-matter of dependent claims. Furthermore, according to the present invention, a power holding circuit is provided for holding power of the operating power supply to the gate bus drive circuit for a predetermined period of time after turning OFF of the power supply of the display device. Moreover, means is provided for detecting the turning OFF of the power supply of the display device, and by its detecting signal, the outputs of the gate bus drive circuit are simultaneously held at the active level for a predetermined period of time. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining the arrangement of conventional active matrix type liquid crystal display elements; Fig. 2 is a waveform diagram for explaining the operation of the display elements shown in Fig. 1; Fig. 3 is a diagram illustrating the arrangement of liquid crystal display elements embodying the liquid crystal display erasing method of the present invention; Fig. 4 is a block diagram illustrating a modified form of a gate bus drive circuit 17 in Fig. 3; Fig. 5 is a block diagram illustrating a display erasing circuit according to another embodiment of the present invention; and Fig. 6 is a voltage waveform diagram for explaining the operation of the erasing circuit depicted in Fig. 5. BEST MODE FOR CARRYING OUT THE INVENTION In Fig. 3 there is shown an embodiment of the present invention as being applied to the liquid crystal display elements of Fig. 1, the parts corresponding to those in Fig. 1 are identified by the same reference numerals and no detailed description will be given of them. The source bus drive circuit 16 and the liquid crystal display panel 10 are identical with those in Fig. 1. In the embodiment of Fig. 3, the shift register 18 in the gate bus drive circuit 17 is made up of cascade-connected presettable D-type flip-flops, which are adapted so that their preset terminals P can be supplied with a clear signal CL at the same time. The clear signal CL is created in accordance with an operator's instruction or under control of a program in a computer connected to the display device. According to the present invention, in the case of clearing a display image, pixel data D of logic "0" for clearing the display, corresponding to one row of the display panel 10, is provided to the source bus drive circuit 16, from which source bus drive signals S₁ through S n of voltage corresponding to the above-mentioned pixel data, i.e. voltage E₂ equal to the voltage of the common electrodes 12b, are simultaneously applied to the source buses 14₁ through 14 n within one horizontal synchronization cycle. In synchronization with this, the clear signal CL is provided to the preset terminal P of each stage of the shift register 18 in the gate bus drive circuit 17 as depicted in Fig. 3. The duration T of the clear signal CL needs only to be equal to or longer than one cycle of the horizontal synchronizing signal Hs. Upon application of the clear signal Hs, the Q output of each stage of the shift register 18 goes to a high level for the time T and the outputs G₁ through G m of the gate bus driver 19 also go to the high level. (In general, this level needs only to be high enough to activate the TFTs 13 of the liquid crystal display panel 10.) Thus all the TFTs 13 are simultaneously rendered ON during the time T. Consequently, the source bus drive signals S₁ through S n for clearing the display are supplied to all pixels with m rows and n columns, by which display images are cleared all at once within the time T. Fig. 4 illustrates another embodiment of the present invention, in which an OR circuit 20 is provided between the shift register 18 and the gate bus driver 19 in the gate bus drive circuit 17 in Fig. 1. Each OR gate of the OR circuit 20 is supplied at one input with the output of the corresponding stage of the shift register 18 and at the other input with the clear signal CL, and the output of each OR gate is applied to the gate bus driver 19. The gate bus driver 19 yields high-level signals G₁ through G m all at once during the duration T of the input clear signal CL. Consequently, display images can be cleared all over the display screen within one cycle of the horizontal synchronizing signal Hs as is the case with the embodiment shown in Fig. 3. The source bus drive circuit 16 and the display panel 10 are identical with those in Fig. 1, and hence are not shown. Fig. 5 illustrates another embodiment of the present invention in which the clear signal CL in the embodiment of Fig. 1 is produced upon turning OFF of the power supply of the display device main body. The source bus drive circuit 16 and the liquid crystal display panel 10 are identical with those in Fig. 1, and hence are not shown. In this embodiment, as shown in Fig. 5, when the liquid crystal display elements are in operation, that is, when the power supply of the display device main body is ON, a large-capacity capacitor 22b is charged via a diode 22a with the power supply voltage V₁ (which is the same as the voltage V₁ in the prior art example depicted in Fig. 1) which is applied from the liquid crystal display device main body to a terminal 21, and at the same time, the voltage V₁ is provided to the gate bus drive circuit 17. The diode 22a and the capacitor 22b constitute a power holding circuit 22 which holds and supplies power to a load for a predetermined period of time after turning OFF of the power supply of the display device main body. If it is disadvantageous that the output voltage V₁′ of the power holding circuit drops below the input voltage V₁, it is also possible to increase the input voltage V₁ in compensation for the voltage drop or provide a DC-DC converter at the input side of the power holding circuit 22 for boosting the input voltage. The output of the power holding circuit 22 is also applied to a power circuit 23, wherein a voltage V₂′ is created as a substitute for the source voltage V₂ which is supplied from the device main body in the prior art, and the voltage V₂′ is provided to the gate bus drive circuit 17. Other voltages are the same as those used in the prior art example. That is, the gate bus drive circuit 17 is supplied with the voltage V₃ (which is a low-level voltage of the gate bus drive signal G i and is used to turn OFF the TFT 13), and though not shown, the source bus drive circuit 16 is supplied with voltages E₁, E₂ and E₃ from the display device main body and the counter electrodes 12b of the liquid crystal display panel 10 are supplied with the voltage E₂. The supply of these voltages V₁, V₃, E₁, E₂ and E₃ is stopped when the power supply of the display device main body is turned OFF. Now, assuming that the power switch of the display device main body is turned OFF at a time t₁, the voltage V₁ drops to the zero volt (the common potential) at a time t₃ (Fig. 6A). Yet the output voltage V₁′ of the power holding circuit 22 gradually decreases with a large time constant C₂₂R L (where C₂₂ is the capacitance of the capacitor 22b and R L is the load resistance of the power holding circuit 22) (Fig. 6C). On the other hand, the voltage drop of the voltage V₁ is detected by a voltage drop detector 24, and at a time point t₂ when the voltage V₁ has dipped, for instance, 20% below a reference value, the voltage drop detector 24 changes to a low level its output V B held at a high level until then (Fig. 6B). The output V B of the voltage drop detector 24 is applied to the output side of the power holding circuit 22 via a capacitor 25 and a resistor 26. The junction F between the capacitor 25 and the resistor 26 is connected to an input terminal of an inverter 27. The voltage V F at the junction F drops at the time t₂ and then gradually approaches, with a time constant CR (where C and R are the capacitance of the capacitor 25 and the resistance of the resistor 26, respectively), the output voltage V₁′ of the power holding circuit 22 (Fig. 6C). To the inverter 27 are applied, as its operating voltages, the voltages V₁′ and V₂′. After the time point t₂ the voltage V₂′ also drops to the common potential with a gradually decreasing time constant, together with the voltage V₁′. Since the threshold level V th of the inverter 27 is set to a level intermediated between the voltages V₁′ and V₂′ as depicted in Fig. 6C, the inverter 27 yields a high-level output V CL as the clear signal for a period of time T (t₂-t₄) during which the input voltage V F to the inverter 27 is lower than the threshold level V th (Fig. 6D). The waveform of the output V CL from the inverter 27 is substantially the same as that of the voltage V₁′ in the time intervalbetween t₂ and t₄ but is nearly equal to the waveform of the voltage V₂′ except that time interval. The pulse width T of the output clear signal CL from the inverter 27 is set to a value a little greater than the time during which the voltages E₁, E₂, V₁ and V₃ supplied to the liquid crystal display panel drop to the common potential when the power supply is turned OFF. That is, T > (t₃-t₂). The output clear signal CL from the inverter 27 is applied to the preset terminal P of each stage of the shift register 18, and the Q output from each stage is rendered high-level (nearly equal to the voltage V₁′) during the time T, and consequently, the outputs G₁ through G m of the gate bus driver 19 are also made high-level (which level needs only to be high enough to activate or turn ON the TFTs 13, substantially equal to the voltage V₁′ in this instance). All the TFTs 13 of the liquid crystal display panel 10 described previously in conjunction with the prior art example are simultaneously turned ON during the time T, and consequently, the display electrode 12a of each pixel 12 is electrically connected via the TFT to the source bus driver 16b. The source bus driver 16b is arranged so that the potential at its output terminal goes to the common potential EG at substantially the same time as the operating voltages E₁, E₂ and E₃ drop to the common potential. That is, the source bus driver is designed so that the source bus driver signals S₁ through S n drop to the common potential within the time T. The display electrode 12a and the counter electrode 12b (the latter being supplied with the voltage E₂) are both supplied with the common potential within the time T, and charges stored in each pixel capacitance in accordance with the display being provided are entirely discharged by the end of the time T. In other words, the time T includes the time necessary for discharging the charges stored in the pixel capacitances. It is evident that the gate bus drive circuit 17 in Fig. 5 may also be replaced with the circuit shown in Fig. 4. While the source bus drive circuit 16 in Fig. 3 has been described to drive the source buses 14₁ through 14 n in such a manner as to provide a binary or ON-OFF display in response to a binary pixel signal as is the case with the prior art example shown in Fig. 1, it is also easy for those skilled in the art to construct the source bus drive circuit 16 so that a half tone display may be provided using an analog video signal which has a half tone pixel level. As described above, according to the present invention, display images can be cleared within one cycle of the horizontal synchronizing signal, which is as short as l/m (where m is the number of rows forming the display screen) of the one-field time needed in the past. Consequently, the display panel of the invention, when used as a display of a computer, is very advantageous in that the time for which the computer is occupied for clearing display images can be reduced accordingly. Moreover, according to the present invention, the turning OFF of the power supply of the liquid crystal display device is automatically detected and the detection signal is used to hold the TFTs of the liquid crystal display elements in the ON stage for a predetermined period of time so that charges stored in the pixel capacitances can be discharged in a short time. This ensures clearing of residual images in a short time and prevents the reduction of the life of the liquid crystal and lowering of its reliability.

Claims: A method of erasing a display on an active matrix type liquid crystal display device having a capacitive storage effect and comprising a source bus drive circuit (16) for driving a plurality of source buses (14₁ - 14 n ) and a gate bus drive circuit (19) for driving a plurality of gate buses (15₁ - 15 m ), wherein an image is displayed by driving the source buses in accordance with pixel signals and selectively activating the gate buses one after the other, said method comprising the steps of: detecting the moment of turning off of a power source, and after said moment has been detected, maintaining, for a predetermined period of time, power supply to only said gate bus drive circuit, immediately generating a clear signal and applying it to only the gate bus drive circuit and, in response to said clear signal, holding said gate buses all at once in an activated state for a fixed period of time. A liquid crystal display erasing circuit for erasing a display on an active matrix type liquid crystal display device, said active matrix type liquid crystal display device including an active matrix type liquid crystal display panel (10) having a capacitive storage effect which is comprised of a plurality of display pixels (12), each having a display electrode (12a) and a counter electrode (12b), arranged in a row and column matrix, and a plurality of switching transistors (13), each having a control electrode and two electrodes between which an electric path can be formed, also arranged in a row and column matrix, said control electrode of each transistor being connected to a corresponding one of said gate buses (15₁ - 15 m ), and one of said two electrodes of each transistor being connected to a corresponding one of said source buses (14₁ - 14 n ) with the other of said two electrodes connected to one electrode of a corresponding one of said display pixels (12); a source bus drive circuit (16) for driving said source buses (14₁ - 14 n ); a gate bus drive circuit (17) for driving said gate buses (15₁ - 15 m ); a power holding circuit (22) supplied with a power from the power source for said liquid crystal display device and being capable of holding power for a predetermined period of time after said power source has been turned OFF; voltage drop detecting means (24) for detecting the voltage drop caused by the turning OFF of said power source and generating a voltage drop detection output; and clear signal generating means (27) responsive to said voltage drop detection output from said voltage drop detecting means (24) for immediately generating a clear signal; characterized by further comprising all gate bus select means operative to provide said clear signal to only said gate bus drive circuit (17) for causing said gate bus drive circuit (17) to simultaneously supply all of said gate buses (15₁ - 15 m ) with a voltage that turns ON all of said transistors all together thereby discharging all charges stored in said display pixels (12) immediately after the turning OFF of said power supply, wherein said source bus drive circuit (16) is directly connected to the power source while said gate bus drive circuit (17) is connected to the power source via said power holding circuit (22). The circuit of claim 2, wherein said gate bus drive circuit (17) includes a shift register (18) comprised of a plurality of cascade-connected D-type flip-flops operative to shift one stable state along said flip-flops in synchronization with a horizontal synchronizing signal, and a plurality of gate bus drivers (19) for driving said gate buses (15₁ - 15 m ) in accordance with outputs from respective output stages of said shift register, and wherein said all gate bus select means is connected in common to preset terminals of said D-type flip-flops and responds to said clear signal to simultaneously preset all of said D-type flip-flops. The circuit of claim 2, wherein said gate bus drive circuit (17) includes a shift register (18) comprised of a plurality of cascade-connected D-type flip-fops operative to shift one stable state along said flip-flops in synchronization with a horizontal synchronizing signal, and a plurality of gate bus drivers (19) for driving said gate buses (15₁ - 15 m ) in accordance with outputs from respective output stages of said shift register, and wherein said all gate bus select means is connected to inputs of said gate bus drivers (19) and simultaneously applies said clear signal to all of said gate bus drivers. The circuit of claim 3 or 4, wherein said power holding circuit (22) includes a diode connected in its forward direction to said power supply, and a capacitor connected to the cathode of said diode for storing a fixed amount of power supplied from said power supply. The circuit of claim 3 or 4, wherein said clear signal generating means (27) generates said clear signal for a substantially fixed period of time immediately after the detection of the voltage drop by said voltage drop detecting means (24).

Inventors: UENISHI NORIYOSHI, YASUI MASARU, UENISHI, NORIYOSHI, YASUI, MASARU
Applicants: HOSIDEN CORP, HOSIDEN CORPORATION
Application year: 1988
Main classification: G09G3
IPC codes: G09G3