LIQUID CRYSTAL COLOR TELEVISION

Abstract: The liquid crystal color TV comprises providing a video signal transfer circuit (3) for sampling and transferring each chrominance signal of red, green and blue separated from a video singal at a predeter­ mined period at every horizontal scanning time and also at every field, driving on matrix a plurality of liquid crystal cells with red, green and blue color filters arrayed in a predetermined pattern according to an output of the transfer circuit.

Description: The invention relates to a liquid crystal color display device in accordance with the precharacterizing portion of claim 1. A known liquid crystal color display device as later on discussed with regard to figure 8 comprises a set of red, green and blue color filters covering the pixel mosaic fashion. Each pixel is driven by a thin-film transistor (TFT), the source of each transistor being connected to a source line, and the gate of each transistor being connected to a gate line. For a better understanding of a liquid crystal color display device with regard to the prior art it is now referred to figure 8. In Figur 8, 1a, 1b denote an odd gate line driver and an even gate line driver for driving odd gate lines G₁, G₃,... ... and even gate lines G₂, G₄ ... ... of the aformentioned TFT-transistor respectively, 2a, 2b denote an odd source line driver and an even source line driver for driving odd source lines S₁, S₃, ... ... and even source lines S₂, S₄, ... ... of the TFT-transistor respectively, and a pixel is formed at each intersection of each gate and each source line. Then, R, G, B color filters are arrayed in a stripe pattern on the pixels as illustrated. In a liquid crystal color TV having a LCD panel contructed as above, an odd field component of TV signals is driven by an odd gate, and an even field component is driven by an even gate. Then, signals (D₁, D₂, ... ...) having amplified video signals to a predetermined voltage (capable of driving the liquid crystal) are fed to each pixel through a source line, thus displaying a color picture on LCD panel. This well-known liquid crystal color display device further comprises a gate line driver with an odd gate line driver for sequentially selecting alternate gate lines of the set of gate lines and an even gate line driver for sequentially selecting alternate gate lines which are situated between the gate lines driven by the odd gate line driver. The source line driver further comprises an odd source line driver for connected inputs from the video signal transfer circuit to alternate source lines of the set of source lines in sequence and an even source line driver for connecting inputs from the video signal transfer circuit to alternate source lines in sequence. These source lines being situated between the source lines driven by the odd source line driver. In EP-B1 0 167 408 a liquid crystal color display device is disclosed which is similar to the prior art in accordance with fig. 8. From the publication "IEEE Transactions on Consumer Electronics, vol. Ce-31, no. 1, Feb. 1985, pp. 39 to 45" it is also known that a liquid crystal color display device comprises the separation of drivers into even and odd drivers, similarly as discussed with regard to the prior art as shown in figure 8. With regard to the prior art, no problem may arise where an array pattern of color filters is stripe-like, but if the color filters are arrayed mosaically in the manner shown in Figure 1, the order of R, G, B changes accordingly to a selected gate line, and thus the LCD panel cannot be driven. This problem to be solved by this invention is to avoid this drawback. The problem is solved by the features as incorporated in the main claim. Prefered embodiments of the inventions are claimed in the subclaims. In accordance with the invention the video signal transfer circuit comprises a plurality of multiplexers controlled by the digital control signal. The multiplexers are controlled such that each of the three outputs of the video signal transfer circuit may correspond to signals represented by any of the colors red, green or blue chrominance signals. Additionally the source line drivers comprise switches for connecting a first, second and third of the three driver input signals to the (3n)th, the (3n + 1)th, the (3n + 2)th source line respectively of the source lines. Switches are activated in sequence of the outputs of a shift register, whereby a signal of the correct colors output to each of the source lines is depending upon the gate line which is presently selected. By this design even mosaic patterns are exactly ON/OFF switched. This operation was impossible by the conventional row or column control process. One preferred embodiment of the invention will now be described with reference to the accompanying drawings. The figures are showing: Figure 1: a schemating block diagram of a LCD panel for a liquid crystal color display device relating to the invention; Figure 2 : a detailed drawing showing the interior of the panel of Figure 1; Figure 3 : a concrete circuit diagram of a video signal transfer circuit; Figure 4a, b : block diagrams showing in detail a multiplexer as used in Figure 3; Figure 5 : a waveform drawing showing a sampling timing of chrominance signal; Figure 6 : a block diagram showing in detail a source line driver; Figure 7a, b : time charts showing a transfer mode of chrominance signals; Figure 8 : a block diagram showing a liquid crystal color display device in accordane with the prior art. Fig. 1 shows a schematic construction of a liquid crystal color display device which is hereinafter sometimes defined as LCD panel. The LCD panel comprises an odd gate line driver 1a, an even gate line driver 1b, an odd source line driver 2a and an even source line driver 2b, as in the case of the prior art. Further the LCD panel comprises a matrix array of pixels in which each pixel is driven by a thin-film transistor (TFT), whereby the source of each transistor 4 is connected to a source line S₁, S₂, ... ... and the gate of each transistor 4 is connected to a gate line G₁, G₂, ... ... R, G, B color filters 5, each of them forming a pixel, are arrayed mosaically as illustrated, whereby each pixel is driven by a thin-film transistor 4. The source of each transistor 4 is connected to a sourse line lines S₁, S₂, ... ... and the gate of each transistor 4 being connected to a gate line G₁, G₂, ... ..., so that the intersections of gate lines and source lines are forming each pixel. Further a video signal transfer circuit 3 is provided for sampling and transferring each chrominance signal of R, G, B separated from a video signal at a predetermined period at every horizontal scanning time and also for every field. The video signals are applied to the video signal transfer circuit 3. From these video signals the chrominance signals a, b, c and a', b', c' are separated and output from the transfer circuit 3 as well as fed to the source line drivers 2a, 2b via input terminals V A1 , V B1 , V C1 , V A2 , V B2 , V C2 respectively. Thus each liquid crystal cell is driven in a matrix fasion. Figur 2 is a drawing showing a construction of the interior of the aforementioned panel in detail. As described above, TFT-transistor 4 and R, G, B color filters 5 are arrayed on each pixel at the intersection of each gate line G₁, G₂, ... ... and each source line S₁, S₂, ... ..., and each liquid crystal display cell is driven in a matrix fashion. Figur 3 shows a concrete circuit diagram of the video signal transfer circuit 3. The circuit 3 is provided with amplifiers 6a, 6b for amplifying each chrominance signal of R, G, B (the signals separated from the video signals) inputted from input terminals I₁ to I₃ to a predetermined voltage, namely a voltage capable of driving the liquid crystals, six multiplexers U₁ to U₆ for transferring analog signals output from the amplifiers 6a, 6b, and the multiplexers U₁ to U₆ are controlled on a 2-bit control signal from input terminals I₄, I₅ and INHIBIT signal from input terminals I₆, I₇. The aforementioned 2-bit control signal becomes an output signal from a ternary counter concretely. Then, each chrominance signal of R. G. B can be transferred and output to the source line drivers 2a, 2b of Fig. 1 from output terminals O₁ to O₆. Each multiplexer U₁ to U₆ is shown in detail in Fig. 4. The multiplexer comprises a converter for converting a logic level of output signals (A, B) of the aforementioned ternary counter and INHIBIT signal (INH), a decoder and a switch unit. The function will be described hereinafter. Each chrominance signal of R, G, B (which is separated from the video signals) is input to the source line drivers 2a, 2b via the video signal transfer circuit 3, sampled at every three lines here and then fed to each source line. For example, signals input from the terminals V A1 , V A2 are sampled at every 3n - 2 (n = 1, 2 ... ...) lines and then output. Further, chrominance signals input from the terminals V B1 , V B2 are sampled at every 3n - 1 lines, and signals input from V C1 , V C2 are sampled at every 3n lines and then output. In this case, the source lines are divided into odd lines and even lines to lower a sampling frequency, and sampling clocks are assigned half each as shown in Fig. 5. Fig. 6 shows the source line drivers 2a, 2b in detail. As described above the signals a, b, c from the video signal transfer circuit 3 which are amplified to a voltage capable of driving the liquid crystals are sampled by a buffer BF. In this case, a switch SW is operated every time a data (horizontal scanning start pulse) STH is shifted by a 60-bit shift register SR on a shift clock CPH, and the signals a, b, c (a', b', c') are fed to the buffer BF for sampling. The switch SW is provided correspondingly to each chrominance signal in this case, and outputs (D₁, D₂, ... ...) of the circuit are also coordinated with inputs (a, b, c, a', b', c'), thus relating as a(a') = D 3n-2 , b(b') = D 3n-1 , c(c') = D 3n . Then in the drawing, LS denotes a level shifter, PS denotes a power unit capable of adjusting a luminance of the liquid crystals, and a plurality of powers (V b , V BB1 to V BB3 , V DD , V SS ) different in voltage are fed externally to the circuit. With reference to a relation between the electrode connection of each pixel and the color filter 5, as shown in Fig. 1 or 2, when a gate line G₁ is turned on in the odd field, outputs D₁, D₄, ... ... D 3n-2 on source side must be R signals on the odd source line driver 2a, outputs D₂, D₅, ... ... D 3n-1 must be B signals, outputs D₃, D₆, ... ... D 3n must be G signals, and also outputs D 3n-2 must be G signals on the even source line driver 2b, outputs D 3n-1 must be R signals and outputs D 3n must be B signals. Thus, signals R, B, G are inputted to a terminal V A1 of the odd source line driver 2a, a terminal V B1 and a terminal V C1 respectively, while signals G, R, B are inputted to a terminal V A2 of the even source line driver 2b, a terminal V B2 and a terminal V C2 respectively. Thus, signals proper for each color filter can be fed to each pixel. However, a gate line G₃ will be turned on at the next horizontal scanning time, therefore signals corresponding thereto must be fed to each terminal of the source line drivers 2a, 2b. That is, feed signals must be transferred properly so as to secure signals a = G signal , b = R signal , c = B signal , and also a' = B signal , b' = G signal , c' = R signal . Further, these must be transferred likewise at the next horizontal scanning time, and then the three combined states must be transferred in order from the next horizontal scanning time on. Then, in the even field, combined states different from the aforementioned three combined states of the odd field must also be transferred in order. Now, in the embodiment, signals R, G, B are transferred on the video signal transfer circuit 3 shown in Fig. 3. That is, the circuit has 2-bit control signals A, B and an inhibit signal inputted by six analog multiplexers U₁ to U₆, and controls two sets of 3 channels on a 2-bit signal. To describe concretely, it is necessary that the signals a, b, c and a', b', c' be any of the signals R, G, B, as described hereinbefore, at every horizontal scanning time and also at every field, and thus outputs of the ternary counter are inputted to the multiplexers U₁ to U₆ as the control signals A, B. In this case, however, a source signal corresponding to the gate line G₁ is fed at the horizontal scanning time before the first gate line G₁ is turned on, therefore a display action starts before the gate line G₁ is turned on. In the multiplexers U₁ to U₆, when the control signals A, B become "L" (low level), X terminal and XCOM terminal (common terminal), Y terminal and YCOM terminal shown in Fig. 4 (b) get conductive, therefore signals R, B and G are inputted to X terminal and Y terminal of the multiplexer U₁ and Y terminal of the multiplexer U₃ respectively. Then, in the odd field, the inhibit signal inputted to the multiplexers U₁, U₃, U₅ is retained to "L" to keep the multiplexers U₁, U₃, U₅ active, and the inhibit signal inputted to the multiplexers U₂, U₄, U₆ is kept at "H" (high level) to get outputs high in impedance. Thus, the signals are fed as a = R sig nal , b = B signal , c = G signal , and a' = G' signal , b' = R' signal , c' = B' signal . At the next horizontal scanning time, the control signals A and B are kept at "H" and "L" respectively, and 1X terminal and XCOM terminal, 1Y terminal and YCOM terminal of the multiplexers U₁ to U₆ are conductive each, therefore the signals G and R are inputted to 1X terminal and 1Y terminal of the multiplexer U₁ respectively, the signals B and R' are inputted to 1Y terminal and 1X terminal of the multiplexer U₃, and the signals B and G are inputted to 1X terminal and 1Y terminal of the multiplexer U₅ respectively. Accordingly, since the inhibit signal is unchanged, the signals are fed as a = G signal , b = R signal , c = B signal , and a' = B' signal , b' = G' signal and c' = R' signal . Then, at the next horizontal scanning time, the control signals A and B are kept at "L" and "H" respectively, 2X terminal and XCOM terminal, 2Y terminal and YCOM terminal of the multiplexers U₁ to U₆ are conductive each, and thus the signals are fed likewise as a = B signal , b = G signal , c = R signal , and a' = R' signal , b' = B' signal and c' = G' signal . Further at the next horizontal scanning time, since the control signals A, B are output signals of the ternary counter, the signals A, B are kept at "L" both, and the aforementioned operation is repeated. In the even field, on the other hand, with the inhibit signal inputted to the multiplexers U₁, U₃, U₅ at "H" and the inhibit signal inputted to the multiplexers U₂, U₄, U₆ at "L", the multiplexers U₁, U₃, U₅ are kept at high impedance and the multiplexers U₂, U₄, U₆ are kept active, and the three-way combinations are repeated likewise. Thus, in LCD panel having color filters 5 arrayed mosaically as shown in Fig. 1, signals corresponding to colors of the filters 5 can be fed, and a color picture can be displayed accordingly. Fig. 7 (a) and (b) are time charts showing a mode wherein signals in the aforementioned odd field and even field are transferred. As illustrated, each gate line is selected at rise of a horizontal synchronizing pulse, and signals R, G, B (R', G', B') are fed at every field. As described, LCD panel of interlacing drive can be driven through a simple construction utilizing analog multiplexers, and a predetermined color picture is obtainable even in case color filters are arrayed in a mosaic pattern. Then, an array other than the mosaic patter is also available by changing the order of video signals inputted to each multiplexer. As described above, according to the invention, since a video signal transfer circuit for sampling and transferring each chrominance signal of R, G, B which is separated from video signals at a predetermined period at every horizontal scanning time and also at every field is provided, a predetermined color picture is obtainable through driving LCD panel of interlacing drive even in case R, G, B color filters are arrayed mosaically.

Claims: A liquid crystal colour display device comprising a matrix array of pixels, a set of source lines (S₁, S₂, ...) and a set of gate lines (G₁, G₂, ...) orthogonal to the said source lines (S₁, S₂, ...), in which each pixel is driven by a thin-film transistor (4), the source of each transistor (4) being connected to a source line (S₁, S₂, ...), and the gate of each transistor (4) being connected to a gate line (G₁, G₂, ...) a set of red, green, and blue colour filters (5) covering the pixels in a mosaic fashion such that horizontally adjacent and vertically adjacent pixels are covered by mutually different coloured filters, in a repetetive pattern a video signal transfer circuit (3) receiving as inputs video signals for supplying three output chrominance signals (a, b, c) representing the coulours red, green and blue to each of an odd source line driver (2a) and an even source line driver (2b) a gate line driver comprising an odd gate line driver (1a) for sequentially selecting alternate gate lines (G₁, G₃, ...) of the set of gate lines (G₁, G₂, ...) and an even gate line driver (1b) for sequentially selecting alternate gate lines (G₂, G₄ ...) which are situated between the gate lines (G₁, G₃, ...)driven by the odd gate line driver (1a) the source line driver comprising an odd source line driver (2a) for connecting inputs from the video signal transfer circuit (3) to alternate source lines (S₁, S₃, ...) of the set of source lines (S₁, S₂, ...) in sequence and an even source line driver (2b) for connecting inputs from the video signal transfer circuit (3) to alternate source lines (S₂, S₄, ...) in sequence, the source lines (S₂, S₄, ...) driven by the even source line driver being situated between the source lines (S₁, S 3, ...) driven by the odd source line driver (2a) characterized in that the video signal transfer circuit (3) comprises a plurality of multiplexers (U₁ - U₆) controlled by a digital control signal, the multiplexers (U₁ - U₆) being controlled such that each of three output lines of the video signal transfer circuit (3) connected to a first, second and third input line respectively of the odd source line driver (2a) and each of three output lines of the video signal transfer circuit (3) connected to a first, second and third input line respectively of the even source line driver (2b) is selected to convey one of the chrominance signals, the chrominance signal which a given output line is selected to convey being cyclically varied the source line drivers (2a, 2b) comprise switches (SW) for connecting the first, second and third of the three driver input lines to the (3n)th, the (3n + 1)th, the (3n + 2)th source line respectively of the source lines (S₁, S 2, ...) to be driven by that driver (2a, 2b), where n is a natural number, the switches (SW) being activated in sequence by the outputs of a shift register (SR), whereby a chrominance signal representing the correct colour is output to each of the source lines (S₁, S₂, ...) in dependence upon the gate line (G₁, G₂, ...) which is presently selected. A liquid crystal colour display device in accordance with claim 1, characterized in that the multiplexers (U₁ - U₆) are controlled by a 2-bit control signal from input terminals (I₄, I₅) and a 2-bit INHIBIT-Signal from input terminals (I₆, I₇). A liquid crystal colour display device in accordance with claim 1 or 2, characterized in that the 2-bit control signal (I₄, I₅) is an output signal from a ternary counter. A liquid crystal colour device in accordance with at least one of the claims 1 to 3, characterized in that the outputs a first and a second group of three multiplexers (U₁ - U₃; U₄ - U₆) are connected with the odd source line driver (2a) or the even source line drivers (2b), respectively. A liquid crystal colour device in accordance to claim 1, characterized in that each source line driver (2a, 2b) controls sampling of the chrominance signals input thereto (red, green, blue) via a shift register (SR) which activates the switches (SW).

Inventors: AKIYAMA, RYOICHI
Applicants: STANLEY ELECTRIC CO., LTD.
Application year: 1988
Main classification: H04N3
IPC codes: H04N3, G09G3, H04N9