Display mode switching system for plasma display apparatus

Abstract: An access to a CGA I/O port (16) or an EGA I/O port (18) by a CPU (9) is detected by an NMI generator (7). The NMI generator (7) then supplies an interrupt signal to the CPU (9). The CPU (9) accesses an I/O monitor RAM (5), and detects the accessed I/O port. The CPU (9) refers to a CGA/EGA display flag (21), and when the accessed I/O port is different from a display mode set in the flag, the CPU sets a display mode corresponding to the accessed I/O port in the CGA/EGA display flag (21). The CPU (9) sets, in a display timing register (25), a display timing parameter corresponding to the display mode set in the flag (21).

Description: The present invention relates to a display mode switching system for a plasma display apparatus. A plasma display apparatus is employed as a display apparatus for a personal computer such as a lap-top computer. For a conventional plasma display apparatus, two display adapters are included as standard equipment. One is a color graphic adapter (to be referred to as a CGA hereinafter), and the other is an enhanced color graphic adapter (to be referred to as an EGA hereinafter). The CGA and EGA are formed on, e.g., boards. A conventional plasma display apparatus has a slot for receiving one of CGA and EGA boards. Therefore, a user must insert one of the CGA and EGA boards in correspondence with a display function of an application program to be used. However, in the conventional plasma display apparatus, when an EGA application program is to be executed when a CGA board is connected, it cannot be executed. Therefore, a demand has arisen for a plasma display apparatus which can execute a loaded application program regardless of a CGA or EGA application program. Prior art document EP-A-0 195 203 discloses a display controller which displays an image on either one of a cathode ray tube (CRT) display unit and a liquid crystal display (LCD) unit having upper and lower screens in accordance with image data stored in a memory. When the CRT display unit is driven, an address generating circuit calculates at the beginning of each horizontal scanning an address of the memory corresponding to the leftmost display position, and when the LCD unit is driven, the address generating circuit calculates at the beginning of each horizontal scanning two addresses of the memory corresponding respectively to the leftmost display positions on the current horizontal scanning lines on the upper and lower screens. The switching operation between the CRT display unit and the LCD unit is performed in accordance with a value set in a register: Display unit selection data C/L which indicate the kind of a display unit to be selected, and are rendered "0" when the CRT display unit is used, and are rendered "1" when the LCD unit is used, are stored in this register. A clock pulse generator is connected with the register and generates different clock frequencies in accordance with the value set in the register. It is an object of the present invention to provide a display mode switching system and method for a plasma display apparatus, which can automatically or manually switch CGA and EGA display modes when either CGA or EGA application program is executed in the plasma display apparatus having CGA and EGA boards. To solve this object the present invention provides a display mode switching system and method as specified in claims 1 and 18. According to the present invention, the plasma display apparatus comprises both the CGA and EGA boards. Therefore, even if a display mode is switched in accordance with an application program, the display mode can be switched automatically or by inputting a command. Therefore, a cumbersome operation, i.e., replacement of a board like in a conventional apparatus, need not be performed. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Other objects and features of the present invention will be apparent from the following description taken in connection with the following drawings in which: Fig. 1 is a block diagram showing an embodiment of a display mode switching system for a plasma display apparatus according to the present invention; Figs. 2A through 2D are views showing formats of display screens of different display resolutions; Figs. 3A through 3D are timing charts of control signals in a CRT display apparatus; Fig. 4 is a view showing one horizontal and vertical period in the CRT display apparatus; Figs. 5A through 5F are timing charts of control signals in a plasma display apparatus; Fig. 6 is a view showing one horizontal and vertical period in the plasma display apparatus; Fig. 7 is a flow chart showing AAS processing; Fig. 8 is a flow chart showing MAS processing; Fig. 9 is a flow chart showing set-up processing; and Fig. 10 is a circuit diagram of a protect mechanism which inhibits updating of a content of a display timing register after a CGA or EGA display timing parameter is set in the display timing register. Fig. 1 is a block diagram showing an embodiment of a display control system for a plasma display apparatus according to the present invention. Referring to Fig. 1, main memory 1 has a pointer for indicating a start address of AAS processing (to be described later). The AAS pointer is a start address of an AAS processing routine of a basic input/output system program (BIOS). Set-up random access memory (RAM) 3 stores CGA or EGA information input at keyboard 10. Set-up RAM 3 is backed up by a battery. Therefore, even if a main power switch is turned off, the content of the set-up RAM is not erased. Input/output (I/O) monitor RAM 5 stores an input/output write (I/O W) signal output from central processing unit 9 (CPU) onto system bus 27. NMI generator 7 determines whether control data has been written in CGA and EGA I/O ports 16 and 18. If the control data has been written, NMI generator 7 supplies a non maskable interrupt signal to CPU 9. BIOS 11 is constituted by a read only memory (ROM). BIOS 11 has AAS processing routine 13 shown in Fig. 7, MAS processing routine 15 shown in Fig. 8, and set-up processing routine 17 shown in Fig. 9. Display subsystem 19 is, e.g., a plasma display apparatus, and comprises CGA/EGA switching flip-flop 21 for selectively displaying CGA and EGA display modes, and cathode ray tube 23 (CRT) controller (to be referred to as a CRTC hereinafter). In this embodiment, a CRT display unit may optionally be connected to system bus 27, and can be display-controlled by CRTC 23. CRTC 23 comprises color graphic adapter 20 (CGA), CGA I/O port 16, enhanced color graphic adapter 22 (EGA), EGA I/O port 18, and display timing register 25. Display timing parameters in a CGA mode of the CRT and plasma displays and in an EGA mode of the plasma display are set in display timing register 25. The display timing parameters are changed in correspondence with differing display apparatuses such as CRT and plasma displays and a difference of display modes such as the CGA and EGA modes. More specifically, display resolutions are different in different display modes. Therefore, in a plasma display apparatus, the format of a display screen must be changed, as shown in Figs. 2A through 2D. Fig. 2A shows a physical display screen of a plasma display apparatus when a dot matrix corresponds to 720 × 400 dots. When a display resolution corresponds to 720 × 350 dots, the format of a display screen is as shown in Fig. 2B. When a display resolution corresponds to 640 × 400 dots, the format of a display screen is as shown in Fig. 2C. When a display resolution corresponds to 640 × 350 dots, the format of a display screen is as shown in Fig. 2D. The display timing parameters must be changed in correspondence with the changes of the display screen. As shown in Figs. 3A through 3D and Figs. 5A through 5D, since the CRT and plasma displays have different sync signal timings, the parameters are set as follows. In the CRT display, one horizontal period is set to be 1H = 45.764 µs (21.85 kHz), as shown in Fig. 4, and one vertical period is set to be 1V = 16.749 µs (59.7 Hz). On the other hand, in the plasma display apparatus, horizontal and vertical sync signals are as shown in Figs. 5A through 5F. In this case, one horizontal period is set to be 43.1 µs, as shown in Fig. 6, and one vertical period is set to be 19.97 ms. CPU 9 controls the entire system. Main memory 1, set-up RAM 3, I/O monitor RAM 5, NMI generator 7, display subsystem 19, BIOS 11, keyboard 10, and CPU 9 are connected to each other via system bus 27. In this invention, the switching of the CGA and EGA modes can be performed by three methods. The first method is automatic adapter selector (AAS) processing. In the AAS processing, the CGA and EGA modes are automatically switched. The second method is manual adapter selector (MAS) processing. In the MAS processing, the CGA and EGA modes are manually switched. The third method is set-up processing. In the set-up processing, when the power switch of the system is turned on, a display mode written in set-up RAM 3 is designated. When the content of set-up RAM 3 is updated, a desired display mode is designated at keyboard 10 to change the content of set-up RAM 3. The AAS processing will be described with reference to the flow chart shown in Fig. 7. An application program is normally programmed so that an image is displayed in either the CGA or EGA display mode. In this case, the application program is programmed such that a CGA or an EGA display mode write signal is supplied from CPU 9 to CGA or EGA I/O port 16 or 18. Therefore, a timing is detected when CPU 9 accesses either CGA or EGA I/O port 16 or 18, and a non maskable interrupt (NMI) signal is supplied to CPU 9. Upon reception of the NMI signal, CPU 9 interrupts the currently executing job, and reads I/O monitor RAM 5. I/O monitor RAM 5 stores I/O access information from the time the power switch of the main system is turned on to the present state. Therefore, the access information can be checked so as to determine whether or not the display mode has been switched. It is then determined in step 27 whether the NMI signal has been supplied from NMI generator 7. If YES in step 27, CPU 9 reads AAS pointer 13 in main memory 1 in step 29. The start address of the AAS processing routine is set in AAS pointer 13. Therefore, the start address is set in a program counter (not shown), thereby executing the AAS processing routine. In the AAS processing routine, CPU 9 reads I/O monitor RAM 5 in step 31. I/O monitor RAM 5 stores information indicating one of CGA and EGA I/O ports 16 and 18 which has been accessed by CPU 9. Therefore, it is determined in step 33 whether CGA I/O port 16 has been accessed. If YES in step 33, it is then determined in step 35 whether CGA/EGA switching F/F 21 has been set in the CGA display mode. If YES in step 35, switching is not required, and the AAS processing is ended. However, if NO in step 35, CGA/EGA switching F/F 21 is set in the CGA display mode in step 37. In step 39, a timing parameter for the CGA display mode is set in display timing register 25 in CRTC 23. However, if it is determined in step 33 that CGA I/O port 16 has not been accessed, it is then determined in step 41 whether or not 41 EGA I/O port 18 has been accessed. If NO in step 41, other NMI processing is performed in step 49. However, if YES in step 41, it is checked in step 43 whether CGA/EGA switching F/F 21 has been set in the EGA display mode. If YES in step 43, switching is not required, and the AAS processing is ended. However, if NO in step 43, CGA/EGA switching F/F 21 is set in the EGA display mode in step 45. In step 47, a timing parameter for the EGA display mode is set in display timing register 25. As a result, CRTC 23 controls the plasma display apparatus in accordance with the display timing parameter set in display timing register 25. A case will be described with reference to the flow chart of MAS processing shown in Fig. 8, wherein the CGA and EGA display modes are manually switched. In the MAS processing, a command (e.g., "MASCGA" or "MASEGA") which can be operated on a disk operating system (DOS) is provided. A user inputs the DOS command to switch the display mode. More specifically, in step 49, CPU 9 receives the DOS command input at keyboard 10. It is determined in step 51 whether or not the input DOS command is for the MAS processing. If NO in step 51, CPU 9 executes processing in accordance with the input DOS command in step 53. However, if YES in step 51, the display mode is determined in step 55. In step 57, the CGA display mode is set in CGA/EGA switching F/F 21. In step 59, a display timing parameter for the CGA display mode is set in display timing register 25. If the EGA display mode is detected in step 55, the EGA display mode is set in CGA/EGA switching F/F 21 in step 61. In step 63, a display timing parameter for the EGA display mode is set in display timing register 25. The MAS processing has the same effect as the AAS processing described above. In the AAS processing, each time CGA or EGA I/O port 16 or 18 is accessed, the processing shown in Fig. 7 is executed, and this processing takes a slightly longer period of time than that of the MAS processing. When the application program is programmed to correspond to both the CGA and EGA modes, the AAS processing cannot often determine the display mode. In this case, the MAS processing is more effective. The set-up processing will be described below. In the set-up processing, either display mode (in this embodiment, the CGA display mode) is written in advance in set-up RAM 3. Therefore, when the power switch of the main system is turned on, CPU 9 reads the contents of set-up RAM 3. Then, CPU 9 sets a display mode in CGA/EGA switching F/F 21 and sets a display timing parameter in display timing register 25 in accordance with the read content. When a display mode has been temporarily switched, a user can rewrite the contents of set-up RAM 3. This rewrite operation can be achieved by providing a DOS command for switching the contents of set-up RAM 3. Alternatively, a CGA/EGA selection menu can be displayed on the display screen, and selection information may be input at the keyboard. After the display mode has been temporarily rewritten, the initial display mode can be resumed after the system has been reset. More specifically, in step 65 of the set-up processing flow chart shown in Fig. 9, the CGA or EGA display mode is input at keyboard 10. In step 67, CPU 9 stores one of input CGA and EGA display mode data in set-up RAM 3. In step 69, CPU 9 reads the contents of set-up RAM 3. It is determined in step 71 whether the contents of set-up RAM 3 corresponds to the CGA or EGA display mode. If the CGA display mode is detected, CGA/EGA switching F/F 21 is set in the CGA display mode in step 73. In step 75, a timing parameter for the CGA display mode is set in display timing register 25. If the EGA display mode is detected in step 71, CGA/EGA switching F/F 21 is set in the EGA display mode in step 77. In step 79, a timing parameter for the EGA display mode is set in display timing register 25. In this manner, after the display timing parameter has been set in display timing register 25, the contents of the display timing parameter must be kept unchanged until the application program has been executed. A protection mechanism for inhibiting the changing of the parameter will be described with reference to the circuit diagram of Fig. 10. Fig. 10 is a partially detailed circuit diagram of plasma display apparatus 19 shown in Fig. 1. When the CGA or EGA display timing parameter is set in display timing register 25, CPU 9 supplies it to register 25 through system bus 27. CPU 9 supplies a display timing set signal to one input terminal of AND gate 81, and supplies an enable signal to a D input terminal of protect flip-flop 83. Then, protect F/F 83 supplies the enable signal to AND gate 81 in synchronism with a clock signal supplied from a clock signal generator (not shown). As a result, AND gate 81 supplies a display timing set signal to CRTC 23. In response to the display timing set signal, CRTC 23 sets the CGA or EGA display timing parameter in display timing register 25. When the display timing parameter is set in register 25, CPU 9 supplies a disable signal to protect F/F 83. As a result, the disable signal from protect F/F 83 is continually supplied to the other input terminal of AND gate 81 until the corresponding application program has been executed. Therefore, if a new display timing parameter is set in register 25, it will be blocked by AND gate 81.

Claims: A display mode switching system for a flat panel display apparatus operable in a selected one of a plurality of display modes in accordance with a corresponding display timing parameter, each display timing parameter corresponding to a specified resolution, the system being characterized by comprising: designating means (3, 10, 9, 7) for designating one of the plurality of display modes as a selected display mode; display timing parameter memory means (25) for storing a display timing parameter corresponding to the selected display mode; and display mode setting means (9) for setting, in said display timing parameter memory means (25) the display timing parameter for said flat panel display apparatus corresponding to the selected display mode. A system according to claim 1, characterized by further comprising display mode information storing means (3) for storing display information indicating which display mode is selected by the designating means (3, 10, 9, 7). A system according to claims 1 or 2, characterized by further comprising a central processing unit (CPU) (9), and wherein said designating means (3, 10, 9, 7) comprises detection means for detecting one of the plurality of display modes designated by said CPU (9), in accordance with a display mode defined by an application program executed by said CPU (9), wherein the designating means (10) designate the display mode detected by said detecting means as the selected display mode. A system according to claim 1 or 2, characterized in that said designating means (3, 10, 9, 7) comprises input means (10) for inputting information indicating one of said plurality of display modes as the selected display mode, and means (9) for designating the selected display mode in accordance with the information from said input means (10). A system according to claim 4, characterized in that the information indicating one of the plurality of display modes is in the form of a command executable in a disk operating system program. A system according to claim 1, characterized in that said designating means (3, 10, 9, 7) comprises display mode information memory means (3) for storing display mode information indicating a display mode to be selected when a power switch of said system is turned on, means for retrieving the contents of said display mode information memory means (3), and means for designating a display mode corresponding to the retrieved contents when the power switch of said system is turned on. A system according to claim 6, characterized by further comprising input means (10) for inputting information indicating one of the plurality of display modes, and means for rewriting display mode information in said display mode information memory means (3) in accordance with the display mode information input by said input means (10). A system according to claim 1 or 2, characterized by further comprising display mode flag means (21) for storing data indicating a present display mode, wherein the display mode setting means (9) comprises means for setting the selected display mode in said display mode flag means (21) in accordance with the display information. A system according to any one of claims 1 to 8, characterized by further comprising inhibition means (81, 83) for inhibiting the contents of said display timing parameter memory means from being changed by said display mode setting means (9) for setting the display timing parameter after the display timing parameter has been set in said display timing parameter memory means (25). A system according to any one of claims 1 to 9, characterized in that the plurality of display modes comprises at least a color graphic adapter (CGA) mode and an enhanced color graphic adapter (EGA) mode. A system according to claim 3, characterized by further comprising display mode switching means for setting, in said display timing parameter memory means (25), the display timing parameter of said flat panel display apparatus to the display timing parameter corresponding to the detected display mode indicated by the detection signal from said display mode detection means. A system according to claim 11, characterized by further comprising inhibiting means (81, 83) for inhibiting the contents stored in said display timing parameter memory means (25) from being changed by said display mode switching means after the display timing parameter has been set in said display timing parameter memory means (25) by said display mode switching means. A system according to claim 1 or 2, characterized by input means (10) for inputting information indicating one of the plurality of display modes. A system according to claim 13, characterized in that the contents stored in said display timing parameter memory means (25) are inhibited from being changed by said means (9) for setting the display timing parameter after the display timing parameter has been set in said display timing parameter memory means (25). A system according to claim 13 or 14, characterized in that the information indicating one of the plurality of display modes is in the form of a command executable in a disk operating system program. A system according to any one of claims 2, 3, 6, 8 and 11, comprising at least a color graphic adapter (CGA) and an enhanced color graphic adapter (EGA), for switching the display mode of the flat panel display apparatus and an optional CRT display apparatus in accordance with a disk operating system (DOS) command, each of the display modes operating in accordance with a corresponding display timing parameter and each display timing parameter corresponding to a specified resolution, comprising: input means for inputting the DOS command for designating one of CGA and EGA display modes and wherein: said display timing parameter memory means stores a display timing parameter corresponding to the CGA display mode or a display timing parameter corresponding to the EGA display mode; DOS command decoding means decodes the DOS command input from said input means (10) and outputs a CGA or an EGA designation signal; and said display mode setting means (9) stores, in said display timing parameter memory means (25), the display timing parameter corresponding to the display mode designated by said DOS command decoding means (9). A system according to claim 16, characterized by further comprising inhibiting means (81, 83) for inhibiting the contents stored in said display timing parameter memory means (25) from being changed by said display mode setting means (9) after said display mode setting means (9) has set the display timing parameter in said display timing parameter memory means (25). A display mode switching method for a flat panel display apparatus and an optional CRT display apparatus, each operable in a selected one of a plurality of display modes in accordance with a corresponding display timing parameter and each of which selectively operates in one of the plurality of display modes, each display timing parameter corresponding to a specified resolution, the flat panel display apparatus being provided with display timing parameter memory means (25) for storing a display timing parameter, and display mode flag means (21) indicating a present display mode, said method being characterized by comprising the steps of: a) storing, in display mode information storing means (3), display mode information indicating which display mode is to be selected when power is turned on; b) reading the display mode information stored in the display mode information memory means (3); c) setting the selected display mode in the display mode flag means (21) in accordance with the selected display mode; and d) setting a display timing parameter for said flat panel display apparatus corresponding to the display mode set in the display timing parameter memory means (25). A display mode switching method according to claim 18, characterized by further comprising the steps of: e) inputting information indicating one of the plurality of display modes; and f) rewriting the display mode information stored in the display mode information memory means (3) in accordance with the input display mode information. A display mode switching method according to claim 18, characterized by further comprising the step of inhibiting the display timing parameter memory from being changed after the display timing parameter has been set in the display timing parameter memory means (25). A display mode switching method according to claim 18 for a system having at least a color graphic adapter (CGA), a CGA I/O port (16), an enhanced color graphic adapter (EGA), and an EGA I/O port (18) for switching the display mode of a flat panel display apparatus and an optional CRT display apparatus in accordance with an application program, a CPU (9) for executing said application program, for accessing the CGA and EGA I/O ports (16, 18), and for generating an input/output write signal; access information memory means (5) for storing the input/output write signal; said display mode flag means (21) indicating whether a present display mode is a CGA or an EGA display mode; and access detection means (79) for detecting that one of the CGA and EGA I/O ports (16, 18) has been accessed by said CPU (9) and for supplying an interrupt signal to said CPU (9), said method comprising the steps of: a) referring to said access information memory means (5) in response to the interrupt signal so as to detect if the access has been made to said CGA I/O port (16) or to said EGA I/O port (18); b) determining if the access information in the detected I/O port corresponds to the content of said display mode flag means (21), and wherein if the access information of the detected I/O port does not correspond to the content of said display mode flag means; c) setting said display mode flag means (21) in a new display mode and setting a display timing parameter corresponding to said new display mode in said display timing parameter memory means (25). A display mode switching method according to claim 21, characterized by further comprising the step of inhibiting the contents stored in said display timing parameter memory means (25) from being changed by said CPU (9) after said CPU (9) sets the display timing parameter in said display timing parameter memory means (25). A display mode switching method according to claim 18, characterized by further comprising the steps of: if said system is reset after step a) has been executed, said reading step b) includes reading the stored display mode information stored in the display mode information memory means (3), after said system reset.

Inventors: ZENDA HIROKI PATENT DIVISION, ZENDA, HIROKI PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: G09G3
IPC codes: G09G3, G09G5, G06F3