Semiconductor memory device with protection cells

Abstract: For preventing sense amplifier circuits associated with memory cells from misjudgment, there is proposed a semiconductor memory device comprising protection cells (42 and 43) formed between memory cell array (1) and peripheral circuits (21 and 28), and the protection cells are coupled to an additional bit line pair (44) precharged to a predetermined voltage level approximately equal to those of bit line pairs (13 and 14) coupled to the memory cells, so that no difference voltage takes place between the additional bit line pair and the neighboring bit line pair, thereby eliminating a difference in characteristics of the sense amplifier circuits (7, 8 and 48) coupled thereto.

Description: This invention relates to a semiconductor memory device and, more particularly, to protection cells for protecting data informations preserved in memory cells against destruction. BACKGROUND OF THE INVENTION In general, a dynamic type semiconductor memory device is arranged to have a memory cell array located at a central zone of a semiconductor chip and peripheral circuits such as, for example, a data input/output buffer circuit and an address buffer/decoder circuit formed in a peripheral zone of the semiconductor chip. The dynamic type semiconductor memory device thus arranged is responsive to address signals accompanied by some control signals to preserve or retrieve data informations into or from the memory cell array. In these operations, the peripheral circuits are activated to assist the memory cell array accompanied by a plurality of sense amplifier circuits, so that electric charges discharged from the peripheral circuits flows into the semiconductor chip during those operations. On the other hand, the data informations are preserved in the form of electric charges, then the data informations are liable to be affected by the electric charges discharged from the peripheral circuits. In a serious situation, some of the data informations are inverted in logic level. The minimum device dimension has been reduced on the basis of recent research and development efforts, and, accordingly, the amount of charges accumulated in each memory cell is decreased with the minimization of the device size. Then, the problem of inversion is more crucial. One of the solutions is to provide additional memory cells along the peripheral circuits. The addition memory cells are coupled to a pair of bit lines and the bit lines are directly supplied from a source of voltage. This means that the potential on the bit line pair coupled to the additional memory cells tends to be different from the bit line pair coupled to the memory cells of the memory cell array. However, another problem is encountered in the proposed dynamic type semiconductor memory device in operation of the sense amplifier circuits. In detail, the minimization of the device size results in reduction of a distance between the neighboring bit line pairs. Then, a bit line pair is capacitively coupled to the neighboring bit line pairs, so that each of the bit line pair tends to be influenced by the neighboring bit line pairs, especially, the potentials on the neighboring bit line pairs. Under the influence of the neighboring bit line pairs, the sense amplifier circuits are also affected by the potentials on the neighboring bit line pairs. As a result, if a bit line pair does not neighbor the bit line pair coupled to the additional memory cells, the sense amplifier circuit is not under the influence of the difference between the neighboring bit line pairs. On the other hand, if a bit line pair neighbors the bit line pair coupled to the additional memory cells, the sense amplifier circuit operates with a characteristic different from that of the sense amplifier circuit which is free from the influence of the different potential. GB-A-2 112 568 shows a memory device according to the preamble part of claim 1 in which protection cells located between the peripheral circuits and the memory cell array are provided. The additional bit lines are coupled with a normal sense amplifier circuit and with switching transistors which are always in off-state such that no data bits can be written into the protection cells. This results in that so voltage levels in the protection cells are indeterminate. It is therefore an important object of the present invention to provide a semiconductor memory device with protection cells which is suitable for high density integration. It is also an important object of the present invention to provide a semiconductor memory device which is free from the problem inherent in the prior-art semiconductor memory device. These objects are achieved by a semiconductor memory device as defined in claim 1; the dependent claims are related to further developments of the invention. The data information may have a high voltage level or a low voltage level, and, accordingly, the reference information may have a voltage level between the high voltage level and the low voltage level. The reference means may comprise a plurality of dummy cells each coupled to the first or second bit line of each bit line pair coupled to the memory cells in each column, and each of the dummy cells may be operative to produce the piece of reference information. Each of the sense amplifier circuits associated with the bit line pair coupled to the memory cells in each column may comprise first and second n-channel type field effect transistors, the first n-channel type field effect transistor has a gate electrode coupled to a drain node of the second n-channel type field effect transistor, and the second n-channel type field effect transistor has a gate electrode coupled to a drain node of the first n-channel type field effect transistor, source nodes of the first and second n-channel type field effect transistors are coupled to the interconnecting means. In order to activate the reference means, the semiconductor memory device may further comprise a dummy word line pair having first and second dummy word lines, and the first and second dummy word lines interconnect the addressing circuit and the dummy cells. For direct controlling of the switching circuit associated with the bit line pair coupled to the protection cells, another implementation may be arranged to have the sense amplifier circuit provided with third and fourth n-channel type field effect transistors, and the third and fourth n-channel type field effect transistors have respective gate electrodes coupled to the first and second dummy word lines, respectively. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of a semiconductor memory device with protection cells according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawing in which figure is a circuit diagram showing the circuit arrangement of a semiconductor memory device embodying the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT In the figure, there is shown a part of the circuit arrangement of a semiconductor memory device embodying the present invention. The semiconductor memory device is of the dynamic type and fabricated on a semiconductor substrate, typically mono-crystalline silicon substrate. The semiconductor memory device largely comprises a memory cell array 1 formed in a central zone 2 of the semiconductor substrate 3 and a peripheral circuit located in the peripheral zone 4 of the semiconductor substrate 3. In this instance, the memory cell array 1 is accompanied by precharging circuits 5 and 6 and sense amplifier circuits 7 and 8, so that these circuits 5, 6, 7 an 8 are also formed in the central zone, however the precharging circuits and sense amplifier circuits may be formed in the peripheral zone 4 in another implementation. The memory cell array comprises a plurality of memory cells 9, 10, 11 and 12 arranged in rows and columns, but only two rows and two columns are illustrated in the figure, so that description will be made for the two rows and the four columns associated with the precharging circuits 5 and 6 and the sense amplifier circuits 7 and 8, but this description does not mean that the memory cell array 1 has a small number of memory cells only. The memory cell array 1 is accompanied by a plurality of bit line pairs 13 and 14, and each of the bit line pairs 13 and 14 extends in column directions. Each bit line pair 13 or 14 has a first bit line 15 or 16 and a second bit line 17 or 18, and interconnects the precharging circuit 5 or 6 and the sense amplifier circuit 7 or 8. The first bit lines 15 and 16 are coupled to the memory cells 9 and 11 in every two columns, and the second bit lines 17 and 18 are coupled to the memory cells 10 and 12 in the other columns. Though not shown in the drawing, each of the memory cells 9 to 12 has a series of an n-channel field-effect type switching transistor and a capacitor coupled between the first or second bit line and the ground, so that a data information is preserved in the memory cell 9, 10, 11 or 12 in the form of electric charges. In this instance the data information has a positive high voltage level or the ground level depending upon a logic level thereof. Reference numerals 19 and 20 designate two of word lines extending in row directions, and each of the word lines 19 and 20 are coupled to the gate electrodes of the n-channel field-effect type switching transistors of the memory cells 9 and 11, or 10 and 12 in each row. The word lines 19 and 20 are coupled at one ends thereof to an address buffer/decoder circuit 21 forming part of the peripheral circuits, and the address buffer/decoder circuit 21 is capable of activating one of the word lines 19 and 20 in response to an address signal supplied from the outside thereof. Namely, the address buffer/decoder circuit 21 allows one of the word lines, for example the word line 19, to go up to a positive high voltage level, the respective switching transistors of the memory cells 9 and 11 turn on to provide conduction paths between the capacitors and the first bit lines 15 and 16, respectively. Each of the precharging circuits 5 and 6 comprises three n-channel field-effect type transistors 22, 23 and 24, or 25, 26 or 27, and the n-channel field-effect type transistor 22 or 25 is capable of providing a conduction path between a source of positive high voltage Vdd and the first bit line 15 or 16. On the other hand, the n-channel field-effect type transistor 23 or 26 is capable of providing a conduction path between the source of positive high voltage Vdd and the second bit line 17 or 18, but the n-channel field-effect type transistor 24 or 27 can provide a conduction path between the first bit line 15 or 16 and the second bit line 17 or 18 for equalizing in voltage level. All of the n-channel field-effect type transistors 22 to 27 have respective gate electrodes commonly coupled to one of output nodes of a control signal generator circuit 28 which also forms part of the peripheral circuits. When the control signal generator circuit 28 produces a precharging signal Sp of the positive high voltage level in response to external control signals fed from the outside thereof, all of the n-channel field-effect type transistors 22 to 27 turn on to charge up the first and second bit lines 15 to 18 of the bit line pairs 13 and 14. The semiconductor memory device illustrated in the figure further comprises a dummy word line pair 29 provided with first and second dummy word lines 30 and 31, and the dummy word lines 30 and 31 extend in parallel to the word lines 19 and 20. The first dummy word line 30 is coupled to dummy cells 32 and 33, and the dummy cells 32 and 33 provide a reference voltage level between the positive high voltage level and the ground level to the first bit lines 15 and 16 when the address buffer/decoder circuit 21 allows the first dummy word line 30 to go up to the positive high voltage level. Similarly, the second dummy word line 31 is coupled to dummy cells 34 and 35, and the dummy cells 34 and 35 provide the reference voltage level to the second bit lines 17 and 18 when the address buffer/decoder circuit 21 allows the second dummy word line 31 to go up to the positive high voltage level. The address decoder circuit 21 complementarily provides the positive high voltage level to the first word line 19 and the second dummy word line 31 or the second word line 20 and the first dummy word line 29, so that a difference voltage takes place between the first and second bit lines of each bit line pair 13 or 14. Each of the sense amplifier circuits 7 and 8 comprises first and second n-channel field effect type transistors 36 and 37, or 38 and 39. The first n-channel field-effect type transistors 36 and 38 have respective gate electrodes coupled to drain nodes of the second n-channel field-effect type transistors 37 and 39, respectively, and, similarly, the second n-channel field-effect type transistors 37 and 39 have respective gate electrodes coupled to drain nodes of the first n-channel field-effect type transistors 36 and 38, respectively. The drain nodes of the first n-channel field-effect type transistors 36 and 38 are coupled to the first bit lines 15 and 16, respectively, but the drain nodes of the second n-channel field-effect type transistors 37 and 39 are coupled to the second bit lines 17 and 18, respectively. However, all of the source nodes of the transistors 36 to 39 are commonly coupled to a shared discharge line 40, and the shared discharge line 40 is coupled the ground when an n-channel field-effect type transistor 41 is turned on. Namely, the n-channel field-effect type transistor 41 has a gate electrode coupled to another output node of the control signal generator circuit 28, and the control signal generator circuit 28 produces an activation signal Sv of the positive high voltage level which is supplied to the gate electrode of the n-channel field-effect type transistor 41. Then, with the activation signal Sv, the n-channel field-effect type transistor 41 turns on, thereby activating the sense amplifier circuits 7 and 8. The semiconductor memory device illustrated in the figure further comprises protection cells each similar in construction to the memory cells 9 to 12, so that no further description is incorporated for the construction of each protection cell. Each of the protection cells thus arranged is capable of preserving a dummy information in the form of electric charges which may be attacked by the electric charges discharged from the peripheral circuits into the semiconductor substrate 3. However, the dummy information is not read out to the outside thereof, so that no inversion is detected from the outside thereof. Moreover, the electric charges fed into the semiconductor substrate 3 are consumed by the attacks on the dummy informations, so that data informations in the memory cells are protected from the electric charges fed into the semiconductor substrate 3. Only two of the protection cells are shown in the drawing and are designated by reference numerals 42 and 43, respectively. Moreover, the figure shows the protection cells 42 and 43 located between the left side of the memory cell array 1 and the peripheral circuits, however there are formed protection cells between the right side of the memory cell array 1 and the peripheral circuits. On both sides of the protection cells 42 and 43 is provided an additional bit line pair 44 which has first and second additional bit lines 45 and 46 both extending in parallel to the bit line pairs 13 and 14. The additional bit line pair 44 interconnects an additional precharging circuit 47 and a switching circuit 48, and the protection cells 42 and 43 are coupled to the first and second additional bit lines 45 and 46, respectively. The additional precharging circuit 47 is similar in construction to the precharging circuits 5 and 6, and comprises three n-channel field-effect type transistors 49, 50 and 51 with gate electrodes commonly coupled to aforesaid output node of the control signal generator circuit 28 where the precharging signal Sp appears. However, the switching circuit 48 is slightly different in construction from the sense amplifier circuits 7 and 8. Namely, the switching circuit 48 comprises third and fourth n-channel field-effect type transistors 52 and 53, and the third and fourth n-channel field-effect type transistors 52 and 53 have respective gate electrodes coupled in parallel to the first and second dummy word lines 30 and 31, respectively. Drain nodes of the third and fourth n-channel field-effect type transistors 52 and 53 are coupled to the additional bit lines 45 and 46, respectively, but source nodes thereof are commonly coupled to the shared discharge line 40. Description will be hereinunder made for a read-out operation on the assumption that an external device such as, for example, accesses the data information preserved in the memory cell 9. The control signal generator circuit 28 produces the precharging signal Sp of the positive high voltage level, and the precharging signal Sp is supplied to not only the precharging circuits 5 and 6 but also the additional precharging circuit 47. With the precharging signal Sp, all of the precharging circuits 5 and 6 and the additional precharging circuit 47 are activated to charge up the bit line pairs 13 and 14 and the additional bit line pair 44. After completion of the precharging operation, the control signal generator circuit 28 shifts the precharging signal Sp from the positive high voltage level to the ground level, so that the bit line pairs 13 and 14 and the additional bit line pair 47 are cut off from the source of positive high voltage Vdd. When the bit line pairs 13 and 14 and the additional bit line pair 44 are cut off from the source of positive high voltage, the address buffer/decoder circuit 21 allows the word line 19 and the dummy word line 31 to go up to the positive high voltage level, then the memory cells 9 and 11 and the dummy cells 34 and 35 are activated to transfer the data informations and the dummy informations preserved therein to the first bit lines 15 and 16 and the second bit lines 17 and 18, respectively. As described hereinbefore, the dummy information has the intermediate voltage level between the positive high voltage level and the ground level, so that a small difference in voltage level takes place between the first and second bit lines 15 and 17 and between the first and second bit lines 16 and 18, respectively. On the other hand, the n-channel field-effect type transistors 52 and 53 are turned off and on, respectively, due to the voltage level of the dummy word lines 30 and 31. Subsequently, the control signal generator circuit 28 produces the activation signal Sv of the positive high voltage level which is supplied to the gate electrode of the n-channel field-effect type transistor 41. Then, the n-channel field-effect type transistor 41 turns on to allow the shared discharge line 40 to be grounded. When the shared discharge line 40 is grounded, the sense amplifier circuits 7 and 8 are activated to increase the differences between the first and second bit lines 15 and 17 and between the first and second bit lines 16 and 18, respectively. Though not shown in the drawing, one of the differences on the bit line pairs 13 and 14 is selected by a suitable selector circuit and, thereafter, transferred to a output buffer circuit 8 (not shown). On the other hand, the additional bit line 46 is coupled to the shared discharge line 40 through the n-channel field-effect type transistor 53, however the additional bit line 45 remains in the positive high voltage level because the n-channel field-effect type transistor 52 is turned off. For this reason, the protection cell 42 accumulates the electric charges fed from the additional bit line 44. However, the additional bit line 45 goes up to the predetermined positive high voltage level equal to the bit line pairs 13 and 14, so that no unbalance in voltage level takes place between the bit line pair 13 and the additional bit line pair 44, so that the sense amplifier circuit 7 is prevented from the undesirable operation. In the embodiment hereinbefore described, the protection cells 42 and 43 and the additional precharging circuit 47 are similar in construction to the memory cells 9 to 12 and the precharging circuits 5 and 6, so that no additional process is needed to form the protection cells and the additional precharging circuit 47 on the semiconductor substrate 3. As will be understood from the foregoing description, the semiconductor memory device according to the present invention is advangageous over the prior-art semiconductor memory device in that all of the sense amplifier circuits operate with the same characteristics regardless of the position thereof. In the embodiment described above, each of the bit line pairs 13 and 14 is associated with two of the columns, and the words "bit line pair " is used in view of precharging circuit, but it is possible to say that each bit line is associated with each column in view of addressing.

Claims: A semiconductor memory device fabricated on a semiconductor substrate (3), comprising: a) a memory cell array (1) having a plurality of memory cells (9, 10, 11, 12) each capable of preserving a bit of data information in the form of electric charges, said memory cells being arranged in rows and columns, b) a pluralilty of bit line pairs (13, 14) each associated with said memory cells in two of said columns and having first and second bit lines coupled to said memory cells in said two of said columns, respectively, c) charging means (5, 6) operative to supply each of said bit line pairs with electric charges for equalizing the potentials of said first bit line and said second bit line, d) a plurality of word lines (19, 20) each coupled to said memory cells in each row, e) reference means (32 to 35) selectively activated by dummy word lines (30, 31) for supplying said first bit lines or said second bit lines with a piece of reference information upon activation thereof, f) peripheral circuits including an addressing circuit (21) operative to select one of said dummy word lines for activation of said reference means, said addressing circuit being further operative to activate one of said word lines so as to allow said memory cells coupled thereto to be electrically connected to said second bit lines or said first bit lines for transferring said bits of data information, a voltage difference developing between said first and second bit lines of each bit line pair on the basis of said bit of data information and said piece of reference information, peripherical circuits selected from said peripheral circuits discharging electrical charges into said semiconductor substrate, g) a plurality of sense amplifier circuits (7, 8) each associated with each of said bit line pairs and operative to decide a logic level of said bit of data information on the basis of said voltage difference between said first and second bit lines of each bit line pair when the sense amplifier circuit is activated, h) interconnecting means (41) operative to couple said sense amplifier circuits through a node (40) to a constant voltage source for activation of said sense amplifier circuits, and i) protection cells (42, 43) located between said peripheral circuits and said memory cell array, capable of preserving bits of dummy information each in the form of electric charges, and coupled to an additional bit line pair (44), characterized by j) a switching circuit (48) having two switching transistors (52, 53) coupled between the additional bit line pair and said node (40) and respectively controlled by said dummy word lines for causing one of the bit lines of said additional bit line pair to couple with said interconnecting means when the addressing means activate said reference means with a selected one of said dummy word lines, whereby said bits of dummy information prevent said data information from said electric charges discharged from said peripheral cicuits. A semiconductor memory device as set forth in claim 1, in which said bit of data information has a high voltage level or a low voltage level. A semiconductor memory device as set forth in claim 2, in which said reference means comprise a plurality of dummy cells (32 to 35) each coupled to the first or second bit line of each bit line pair coupled to said memory cells in each column, each of said dummy cells being operative to produce said piece of reference information with a voltage level between said high voltage level and said low voltage level. A semiconductor memory device as set forth in claim 3, in which each of said sense amplifier circuits (7, 8) associated with said bit line pair coupled to said memory cells in each column comprises first and second n-channel type field effect transistors (36, 37; 38, 39), said first n-channel type field effect transistor having a gate electrode coupled to a drain node of said second n-channel type field effect transistor, said second n-channel type field effect transistor having a gate electrode coupled to a drain node of said first n-channel type field effect transistor, source nodes of said first and second n-channel type field effect transistor being coupled to said inter-connecting means. A semiconductor memory device as set forth in claim 4, in which said addressing circuit (21) selectively supplies one of said first and second dummy word lines with the high voltage level.

Inventors: MUROTANI TATSUNORI C O NEC COR, MUROTANI, TATSUNORI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G11C7
IPC codes: G11C11, G11C7, G11C29