Semiconductor device with source and drain depth extenders and a method of making the same

Abstract: A semiconductor device (17) having a layer of semiconductor material disposed on an insulating substrate (12) is disclosed. Source and drain depth extenders (18,20; 22,24) are provided within the semiconductor material for extending the respective source and drain regions (34,36; 38,40) to the insulating substrate. This device is fabricated in a manner which minimizes damage that often occurs to the gate oxide layer (27) when high energy implants are used to form self-aligned source and drain regions.

Description: This invention relates to a semiconductor device which includes a layer of semiconductor material disposed on an insulating substrate and a method of making the same. More particularly, the present invention relates to a MOS/SOI device which includes source and drain depth extenders within the layer of semiconductor material. Semiconductor devices having a layer of semiconductor material disposed on an insulating substrate are generally known in the art. An example of such a device is a silicon-on-insulator (SOI) semiconductor device which includes a silicon island formed on the surface of an insulating material. When the insulating material is a sapphire substrate, the structure is known as a silicon-on-sapphire (SOS) semiconductor device. Metal-oxide-semiconductor (MOS) transistors or other active devices are formed in and on the silicon island. MOS/SOI transistors generally have higher speed and improved radiation hardness in comparison with MOS transistors formed in bulk silicon. MOS/SOI transistors are conventionally fabricated by first forming an island of semiconductor material, such as single-crystalline silicon, on the surface of an insulating substrate, such as sapphire. The silicon island is generally doped to have a first conductivity type. A gate oxide layer and a gate electrode are then formed on the island. Source and drain regions of a second conductivity type are formed in the silicon island using conventional ion implantation techniques. During the implantation step, the gate electrode acts as a masking layer so that self-aligned source and drain regions are formed in the silicon island. Then, the device is completed using conventional MOS processing techniques. When fabricating complementary metal-oxide-semiconductor (CMOS) devices in a common island of semiconductor material, it is advantageous to extend the source and drain regions to the insulating substrate so as to avoid a large leakage current between the drain of the P-channel transistor and the source of the N-channel transistor. There can also be leakage between the drain of the N-channel transistor and the source of the P-channel transistor. J. Ohno in U. S.-A- 4,507,846 entitled "Method For Making Complementary MOS Semiconductor Devices," issued April 2, 1985, has addressed this problem by disclosing a method of extending the source and drain regions to the insulating substrate. In this process, a portion of the semiconductor layer between the gate electrodes is removed before the source and drains regions are formed. U. S.-A- 4,507,846 also describes another process for extending the source and drain regions to the insulating substrate by using an additional set of photolithography and ion implantation steps for each MOS transistor. Even when a single MOS transistor is formed in a single island of semiconductor material, it is desirable to extend the source and drain regions to the insulating substrate. If the source and drain regions do not reach the insulating substrate, the large junction areas form high source and drain capacitance with the body of the channel region. This high source and drain capacitance reduces the speed of the device. When fabricating MOS/SOI devices, it is desirable to use silicon islands which have a thickness of about 550 nm (5500Å) or larger so that good quality heteroepitaxial silicon is present in the channel region. However, very high implant energies are needed in the conventional fabrication process to extend the self-aligned source and drain regions to the insulating substrate. When using these implant energies, the dopant ions can pass through the gate electrode, which is acting as a mask, and damage the underlying gate oxide. As discussed in the article by R. K. Smeltzer, entitled "Trap Creation In Channel Oxides Due To Ion Penetration Of Polycrystalline Silicon," Applied Physics Letter , 41(9), November 1, 1982, pp. 849-851, the implanted ions produce a large concentration of hole traps in the gate oxide. These traps cause a very large shift in the threshold voltage of the MOS device. Thus, it would be desirable to fabricate MOS/SOI semiconductor devices in a thick island of semiconductor material, e.g. greater than about 550 nm (5500Å), with the source and drain regions extending to insulating substrate such that damage to the gate oxide is minimized during the implantation process. In Japanese Journal of Applied Physics, Vol. No. 18, suppl. 18-1, (1979), page 57-62; N. Sasaki et al: "A CMOS/SOS Synchronous static RAM fabricated with advanced SOS technology", there is disclosed a means of reducing junction capacitance in an SOS device by ensuring that the depletion layer extends to the silicon-sapphire interface. This is done by reducing the dopant concentration in the silicon film, and is contrasted to prior methods wherein the source and drain regions directly contact the silicon-sapphire interface. Whilst such method is suitable for the described application of static RAM, the high channel resistance limits applications for the method. The present invention provides a semiconductor device, comprising: an insulating substrate; a layer of semiconductor material disposed on said insulating substrate; source and drain regions of a first conductivity type disposed within said layer of semiconductor material; characterized by source and drain depth extenders of a first conductivity type disposed within said layer of semiconductor material so that at least a portion of each of said extenders has a common boundary with said insulating substrate and each of said source and drain depth extenders subtending and contacting the respective source and drain regions, said source and drain regions each having an impurity concentration which is greater than the impurity concentration of the respective source and drain depth extenders and a depth which is less than the thickness of said layer of semiconductor material. In a further aspect, the invention provides a method of fabricating a semiconductor device, comprising the steps of providing an insulating substrate with a layer of semiconductor material disposed thereon; forming source and drain regions of a first conductivity type by selective doping of said layer of semiconductor material; characterized by forming source and drain depth extenders of a first conductivity type and a first impurity concentration within said layer of semiconductor material by controlled doping to such a depth that at least a portion of each of said extenders has a common boundary with said insulating substrate and each of said source and drain depth extenders subtending and contacting the respective source and drain regions, said source and drain regions being formed by controlled doping to a second impurity concentration which is greater than the first impurity concentration of the respective source and drain depth extenders and being formed to a depth which is less than the thickness of said layer of semiconductor material. The semiconductor device of the present invention includes source and drain regions formed in a layer of semiconductor material which is disposed on an insulating substrate. The source and drain regions each have a depth which is less than the thickness of the layer of semiconductor material. Source and drain depth extenders of the same conductivity type as the source and drain regions are formed in the layer of a semiconductor material so that they have a common boundary with the insulating substrate. In the accompanying drawing: FIGURE 1 is a cross-sectional view of a CMOS device of the present invention incorporating source and drain depth extenders. In this device, the P-channel and N-channel transistors are formed in separate islands of semiconductor material. FIGURE 2 is a cross-sectional view of an alternative CMOS device of the present invention wherein the N-channel and P-channel transistors are formed in a common island of semiconductor material. FIGURES 3 to 5 are cross-sectional views illustrating the various steps of the method of the present invention for fabricating a CMOS device with source and drain depth extenders. The embodiment now to be described uses single-crystalline silicon as a semiconductor material which is disposed on an insulating substrate of single-crystalline sapphire. However, it should be understood that other conventional semiconductor materials, such as IIb-VIa and IIIa-Va semiconductor·compounds, may be substituted for silicon. Additionally, other conventional insulator substrates, such as spinel, beryllium oxide, and silicon dioxide disposed on a semiconductor material, may be substituted for sapphire. Referring to FIGURE 1, a complementary metal-oxide-semiconductor device incorporating the source and drain depth extenders of the present invention is generally designated as 10. A first silicon island 13 is provided on a sapphire substrate 12 for the N-channel transistor. A second silicon island 15 is also provided on the sapphire substrate 12 for the P-channel transistor. The N-channel transistor formed in the first silicon island 13 has a P-type region 14 disposed between N-type source and drain depth extenders 18 and 20, respectively. Heavily doped N-type source and drain regions 34 and 36, respectively, are disposed above the respective source and drain depth extenders 18 and 20. The source and drain regions 34 and 36, respectively, each have a depth which is less than the thickness of the first silicon island 13. The source and drain depth extenders 18 and 20, respectively, subtend and contact the respective source and drain regions 34 and 36. The source and drain depth extenders 18 and 20, respectively, have a common boundary with the sapphire substrate 12. FIGURE 1 also illustrates that the source and drain depth extenders 18 and 20, respectively, are separated by a distance which is greater than the channel length between the source and drain regions 34 and 36, respectively. The heavily doped source and drain regions 34 and 36, respectively, have an N-type impurity concentration which is about three orders of magnitude greater than the N-type impurity concentration of the respective source and drain depth extenders 18 and 20. Typically, the source and drain regions 34 and 36, respectively, each have an impurity concentration of about 10²⁰ cm⁻³ while the source and drain depth extenders 18 and 20, respectively, each have an impurity concentration of about 10¹⁷ cm⁻³. The first silicon island 13 also contains a gate oxide layer 26 and a gate electrode 30. The second silicon island 15, where the P-channel transistor is located, has an N-type region 16 which separates P-type source and drain depth extenders 22 and 24, respectively. Heavily doped P-type source and drain regions 38 and 40, respectively, are disposed above the respective source and drain depth extenders 22 and 24. The source and drain depth extenders 22 and 24, respectively, each have a common boundary with the sapphire substrate 12. As with the N-channel transistor formed in the first silicon island 13, the source and drain depth extenders 22 and 24, respectively, subtend and contact the respective source and drain regions 38 and 40. The source and drain regions 38 and 40, respectively, each have a depth which is less than the thickness of the second silicon island 15. The channel length between the source and drain regions 38 and 40, respectively, is less than the distance separating the source and drain depth extenders 22 and 24, respectively. The heavily doped source and drain regions 38 and 40, respectively, have a P-type impurity concentration which is about three orders of magnitude greater than the P-type impurity concentration of the respective source and drain depth extenders 22 and 24. The source and drain regions 38 and 40, respectively, will typically each have an impurity concentration of about 10²⁰ cm⁻³ while the source and drain depth extenders 18 and 20, respectively, each have an impurity concentration of about 10¹⁷ cm⁻³. A gate oxide layer 28 and a gate electrode 32 are also provided on the second silicon island 15. Turning now to FIGURE 2, a common island complementary metal-oxide-semiconductor device embodying the present invention is generally designated as 50. The N-channel and P-channel transistors are formed in a single silicon island 17 which is disposed on a sapphire substrate 12. A gate oxide layer 27 is also disposed on the silicon island 17. The remaining reference numerals which are common to FIGURES 1 and 2 identify like parts. The method for fabricating the semiconductor device shown in FIGURE 1 is illustrated by FIGURES 3 to 5. Referring now to FIGURE 3, the method begins with a sapphire substrate 12 upon which a continuous layer of N-type single-crystalline silicon, having an impurity concentration of about 10¹⁷ cm⁻³, is grown using conventional heteroepitaxial deposition techniques. A masking layer (not shown), such as a layer of silicon dioxide, is applied and patterned so that the first and second silicon islands 13 and 15, respectively, can be defined through the use of an anisotropic plasma or wet etching technique. The masking layer (not shown) is then removed. A first photoresist layer 42 is applied and patterned in the manner shown in FIGURE 3. The regions of the first silicon island 13 which correspond to the source and drain depth extenders 18 and 20, respectively, are masked. Also, the N-type region 16 of the second silicon island 15 is masked by the first photoresist layer 42. Then, P-type dopants, such as boron, are ion implanted into the respective islands, to form the P-type region 14 in the first silicon island 13 and the source and drain depth extenders 22 and 24, respectively, in the second silicon island 15. The P-type region 14 and the source and drain depth extenders 22 and 24, respectively, each have an impurity concentration of about 10¹⁷ cm⁻³. Then, the first photoresist layer 42 is removed using a conventional solvent. Referring now to FIGURE 4, the gate oxide layers 26 and 28 are formed over the respective silicon islands 13 and 15 by heating the structure in an oxidizing atmosphere to a temperature of about 850°C. An N-type polycrystalline silicon layer (not shown) is formed over the silicon islands 13 and 15 by chemical vapor deposition. Then, the polycrystalline silicon layer is patterned using conventional photolithographic and etching techniques to form the gate electrodes 30 and 32. A second photoresist layer 44 is applied over the entire second silicon island 15. The source and drain regions 34 and 36, respectively, are formed in the first silicon island 13 by ion implanting N-type dopants, such as phosphorus, until an impurity concentration of about 10²⁰ cm⁻³ is achieved. The implant energies are controlled so that the self-aligned source and drain regions 34 and 36, respectively, each have a depth which is less than the thickness of the first silicon island 13. The source and drain regions have this limited depth because the implant energies are selected so that the dopant ions do not penetrate the gate electrode 30 and damage the underlying portion of the gate oxide layer 26. The second photoresist layer 44 is then removed using a conventional solvent. As shown in FIGURE 5, a third photoresist layer 46 is applied over the entire first silicon island 13. The P-type self-aligned source and drain regions 38 and 40, respectively, are formed in the second silicon island 15 by ion implanting P-type dopants, such as boron, until an impurity concentration of about 10²⁰ cm⁻³ is achieved. The implant energies used to form the P-type source and drain regions 38 and 40, respectively, are also controlled in the manner described with regard to FIGURE 4 so that each of these regions has a depth which is less than the thickness of the second silicon island 15. The third photoresist layer 46 is removed using a solvent. The device is then completed using conventional CMOS processing techniques. A method similar to that illustrated by FIGURES 3 to 5 is used to form the common island CMOS device 50 shown in FIGURE 2. During the implantation step illustrated in FIGURE 3, the patterning step used to define the first photoresist layer 42 is modified so that the photoresist layer 42 overlies the regions of the silicon island 17 which correspond to the N-type source and drain depth extenders 18 and 20, respectively, and the N-type region 16. The second 44 and third 46 photoresist layers used in steps illustrated by FIGURES 4 and 5, respectively, are applied so they do not overlie the adjacent MOS transistor. Although the method illustrated by FIGURES 3 to 5 utilizes N-type single-crystalline silicon as the island material, P-type single-crystalline silicon could also be used. In the latter case, the step illustrated by FIGURE 3 would be modified by using N-type dopants with a reverse image of the photoresist pattern shown. The present invention is also considered to include the formation of source and drain depth extenders in a single MOS transistor. Another embodiment of the present invention would include the use of intrinsic single-crystalline silicon as the island material. The step illustrated by FIGURE 3 would be carried out to form the P-type source and drain depth extenders 22 and 24, respectively, and the P-type region 14. The N-type source and drain depth extenders 18 and 20, respectively, would then be formed by implanting N-type dopants into the first silicon island 13 using a masking layer which is the reverse image of the first photoresist layer 42 shown overlying the first silicon island 13 in FIGURE 3. During the latter implantation step, the P-type source and drain depth extenders 22 and 24, respectively, are covered with a masking layer while the central region of the second silicon island 15 is exposed so that the N-type region 16 is formed. However, it may be desirable to mask the entire second silicon island 15 during the N-type implantation step for the source and drain depth extenders 18 and 20, respectively. The mask over the entire second silicon island 15 is removed and a new masking layer is formed over the first silicon island 13. The central region of the second silicon island 15 is then appropriately doped so as to form the channel region for the P-channel transistor. All of the devices produced with the intrinsic single-crystalline island material would then be completed using the steps illustrated in FIGURES 4 and 5. The damage to the gate oxide layer that occurs when high energy source and drain implants are performed in the conventional method in order to extend the source and drain regions to the insulating substrate is avoided with the method of the present invention. The high energy implant used in the present invention to form the source and drain depth extenders is carried out before the gate oxide layer is grown. Thus, silicon island thicknesses on the order of 550 nm (5500Å) or larger can be utilized. The thicker silicon island helps to ensure that good surface mobility will be present in the channel region of the MOS transistor. When the source and drain implants are carried out in the present invention after the gate oxide and gate electrode are formed, only low energy implants are required since the source and drain region have a depth which is less than the silicon island thickness. Ions implanted at these energies will not pass through the gate electrode and damage the gate oxide. Because of the extension of the source and drain regions of a common island CMOS device to the insulating substrate, current leakage between adjacent MOS devices is eliminated. In addition to reducing leakage between adjacent devices, the source and drain depth extenders also increase the speed of the CMOS device because there is a lower source/drain capacitance with the body of the channel region. This lower source/drain capacitance is achieved because the junction area between the source and drain regions and the channel is greatly reduced and because the source and drain depth extenders have an impurity concentration of about 3 orders of magnitude less than the respective source and drain regions. The device junction leakage current is also lowered due to the smaller junction area with the channel body. Also, the back-channel length between the source and drain depth extenders is greater than the channel length between the source and drain regions. This longer back-channel provides for a higher series resistance between the source and drain regions. The higher series resistance helps to suppress radiation-induced back-channel leakage in N-channel transistors.

Claims: A semiconductor device, comprising: an insulating substrate (12); a layer of semiconductor material (13) disposed on said insulating substrate; source and drain regions (34-36) of a first conductivity type disposed within said layer of semiconductor material; characterized by source and drain depth extenders (18-20) of a first conductivity type disposed within said layer of semiconductor material so that at least a portion of each of said extenders has a common boundary with said insulating substrate and each of said source and drain depth extenders subtending and contacting the respective source and drain regions, the region between said source and drain extenders being of a second conductivity type, said source and drain regions each having an impurity concentration which is greater than the impurity concentration of the respective source and drain depth extenders and a depth which is less than the thickness of said layer of semiconductor material. A semiconductor device in accordance with claim 1, further comprising: a channel region (14) having a defined channel length disposed between said source and drain regions; and said source and drain depth extenders being separated by a distance greater than said channel length. A semiconductor device in accordance with claim 2 wherein said source and drain regions each have an impurity concentration of at least three orders of magnitude greater than the impurity concentration of the respective source and drain depth extenders. A semiconductor device according to any preceding claim, including a P-channel metal-oxide-semiconductor transistor disposed in a first predetermined portion (15) of said layer of semiconductor material and an N-channel metal-oxide-semiconductor transistor disposed in a second predetermined portion (13) of said layer, P-type source and drain depth extenders (22,24) for said P-channel transistor disposed within said first predetermined portion (15) of said layer so that at least a portion of each of said extenders has a common boundary with said insulating substrate (12); N-type source and drain depth extenders (18,20) for said N-channel transistor disposed within said second predetermined portion (13) of said layer so that at least a portion of each of said extenders has a common boundary with said insulating substrate (12); P-type source and drain regions (38,40) disposed within said first predetermined portion (15) of said layer so that each of said P-type source and drain depth extenders subtend and contact the respective P-type source and drain regions (22,24), and N-type source and drain regions (34,36) disposed within said second predetermined portion (13) of said layer so that each of said N-type source and drain depth extenders subtend and contact the respective N-type source and drain regions (18,20). A semiconductor device according to claim 4 wherein said first and second predetermined portions are disposed in a common island (17) of said layer of semiconductor material. A semiconductor device according to claim 4 wherein said first and second predetermined portions are disposed in separate islands (13,15) of said layer of semiconductor material. A method of fabricating a semiconductor device, comprising the steps of: providing an insulating substrate (12) with a layer of semiconductor material (13-15) disposed thereon; forming source and drain regions (34,36) and (38,40) of first and second conductivity types respectively by selective doping of said layer of semiconductor material; characterized in the following step prior to the formation of said source and drain regions (34-40): forming source and drain depth extenders (18-24) of the same conductivity type as said source and drain regions (34-40) and a first impurity concentration within said layer of semiconductor material by controlled doping to such a depth that at least a portion of each of said extenders has a common boundary with said insulating substrate and each of said source and drain depth extenders subtending and contacting the respective source and drain regions, the region between said source and drain extenders being of the opposite conductivity type to that of source and drain regions, said source and drain regions being further formed by controlled doping to a second impurity concentration which is greater than the first impurity concentration of the respective source and drain depth extenders and being formed to a depth which is less than the thickness of said layer of semiconductor material. A method of fabricating a semiconductor device in accordance with claim 7 wherein said source and drain depth extenders are formed by selectively doping said layer of semiconductor material (13) so that two regions (e.g. 18,20) of a first conductivity type are separated by a region of a second conductivity type (14), said two regions of a first conductivity type forming said source and drain depth extenders. A method of fabricating a semiconductor device in accordance with claim 8, further comprising: forming a gate oxide layer (26) on at least a portion of said region of a second conductivity type after said source and drain depth extenders are formed; and forming a gate electrode (30) on said gate oxide layer. A method of fabricating a semiconductor device in accordance with claim 9 wherein the source and drain regions (34,36) are formed so that they are separated by a distance less than the distance between said source and drain depth extenders (18,20).

Inventors: PLUS DORA, SMELTZER RONALD KEITH, PLUS, DORA, SMELTZER, RONALD KEITH
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1988
Main classification: H01L21
IPC codes: H01L29