Programming method using a Petri net and structured data processing system

Abstract: A method of composing a set of instructions for directly executing a data-flow type program by using a Petri net directed to structured data of at least one of, or a combination of, Cartesian product, direct union and sequence, and a structured data driven type processor system for executing a program containing such instructions. In composing a set of instructions, desired data paths, i.e., links (L), are provided in accordance with the Petri net, and the links are defined by a data type which defines the data to be processed. A work node (W) connected to the link at the input side of the work node is defined which work node takes data from the link at the input side of the work node, performs a desired calculation to take the calculation result out to the link at the output side of the work node. A data type defining data on the link at the output side is restricted by a calculation function of the work node. Instruc­ tions associated with data structure include a decomposi­ tion instruction (Fig. 7A - 9A) for decomposing structured data into constituent elements and a composition instruc­ tion (Fig. 7B - 9B) for composing data of Cartesian product, direct union or sequence from constituents elements. The decomposition and composition instructions are added to instruction languages of the data driven type system.

Description: The present invention relates to a method using a petri net and composing a set of instructions for executing a data-flow program which processes structured data including records, unions and lists, and to a structured data driven type processor system suitable for directly handling data-flow type software specifications. As discussed, for example, in "Iwanami Lectures On Microelectronics 8 VLSI Computer I", December 10, 1984, pp. 70 to 75, and its source paper, Dennis, J.B. et al "A Preliminary Architecture for a Basic Data-Flow Processor", Proc. of 2nd Annual Int. Symp. on Computer Architecture, 1975, pp. 126 to 132, a conventional structured data driven type processor system is allowed to be programmable and has a high performance in its parallel operations, although operand data of an instruction are limited to simple numerical values. The above conventional technique concerns data-flow processing only for primitive data such as integers and bit string, and does not consider processing structured data. In order to process such structured data, it is necessary to decompose the structured data into basic or element data such as integers or real numbers. It takes therefore a lot of time (labor) in programming and there arises a problem of a very poor readability of a program. A programming method using a Petri net is disclosed in IEEE 1986 National Aerospace and Electronics Conference, NAECON 1986, pages 727-732; G.S. Hura et al.: "Petri Net Models of Programming Languages: A unified modelling approach". Also this document considers only the processing of individual simple data items. A method for handling more complex data structures is not disclosed. SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a method to compose a data-flow program handling not only primitive data but also structured data, and to provide a processor system also capable of handling such structured data. This object is achieved by the method specified in claim 1 and the data processor system set forth in claim 3. Preferred embodiments are specified in the subclaims. For interpreting a Petri net as a programming language, the present invention provides a rule or meaning by which structured data of records, unions and lists can be handled. Namely, data having a data type of Cartesian product, direct union and sequence are directly coupled to a data path or link corresponding to a "place" in the Petri net model diagram. Therefore, it becomes possible to compose a set of instructions capable of directly executing a data-flow type program while structured data to be processed are flowing. The Petri net model is detailed in Robert E. Filman & Daniel P. Friedman "Coordinated Computing: Tools and Techniques for Distributed Software" 1984, Mc-Graw Hill, and the structured data programming method is detailed in Q. J. Dahl, E. W. Dijkstra, and C. A. R. Hoare "Structured Programming" Academic Press, 1972. The total instruction execution performance can be improved by parallel operations of the plurality of processors using the composition and decomposition instructions. For the decomposition instruction structured data are used as an input operand, and decomposed into constituent elements which in turn are used as output operands, and for a composition instruction constituent elements are used as input operands, and composed into structured data which in turn are used as an output operand. As a result, structured data can be used for the calculation (arithmetic operation) without converting structured data into non-structured basic data as in conventional technique. The operands of the composition and decomposition instructions are described in the format designating a link on which data are present. Such link informations are all stored in a link buffer to perform an exclusive control thereof by a link controller, to enable efficient parallel operation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the arrangement of an embodiment of a structured data driven type processor system according to the present invention; Figs. 2A and 2B show an example of data-flow of non-structured data; Figs. 3A and 3B shows an example of a rule for converting a data-flow diagram into a program; Fig. 4 shows an example of a data-flow program; Figs. 5A, 5B and 5C show data structures; Fig. 6 shows a specific data structure; Figs. 7A and 7B illustrate an operation of data with a Cartesian product structure; Figs. 8A and 8B illustrate an operation of data with a direct union structure; Figs. 9A and 9B illustrate an operation of data with a sequence structure; Figs. 10A to 10F show operations of structured data expressed in the form of texts; Fig. 11 shows an example of data-flow handling structured data; Figs. 12A and 12B illustrate an example of an instruction format and an example of a data-flow program handling structured data; Figs. 13A and 13B illustrate data arrangement in a link buffer; Fig. 14 shows an example of arrangement of the link buffer; Fig. 15 is a flow chart illustrating processes executed by an execution controller; Fig. 16 is a flow chart illustrating processes executed by a processor unit; and Figs. 17A to 17C are flow charts illustrating processes executed by a link buffer controller. DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiments to be described hereinbelow, objective data-flow is described in a bi-parted graph which interconnects work nodes and link nodes alternately by arrows. A program used for data-flow is a set of instructions, each having an instruction code defined to a work node, and operands present on link nodes at the input and output of the work node. In executing a program, executable instructions among a set of instructions are caused to be executed in parallel. The executable instruction herein used means an instruction which has all the data of a link node or nodes at the input of a work node concerned. The instruction execution herein used means an operation wherein data are taken from each input link to perform an operation for conversion defined by the instruction code, and the resultant data are taken out to each output link. Data-flow will be described taking a problem of solving roots of a quadratic equation by way of example. Fig. 2A shows a data-flow for solving roots of a quadratic equation. Input data include a coefficient a of the second-order term, a coefficient b of the first-order term and a constant term c , and the calculation result is two roots. The diagram is described using the notation as shown in Fig. 2B, wherein rectangles representing work nodes and circles representing link nodes are alternately connected by arrows to form a bi-parted graph. Work nodes are labeled W1 to W16 with an instruction code depicted within a rectangle. Link nodes are labeled ℓ1 to ℓ24. A link node circle having a tangent line is called a constant link and always provides a constant value specific to the link node. For the convenience of description, a character or characters are affixed at the side of a link node circle, which characters represent a data value calculated from the starting inputs of a , b and c . Of instruction codes OP, "+" represents addition, "-" subtraction, "*" multiplication, "/" division, "↑" power, "NEG" sign inversion, "SQRT" square root, and "DUP" duplication. For example, by the instruction code DUP at the work node W1, data are taken from the input side link ℓ1 and the same data are put to both the output side links ℓ4 and ℓ5. By the instruction code at the work node W4, data are taken from the link ℓ5 as a first operand while data are taken from the constant link supplying a value 2 as a second operand, and the power of 2 of the first operand is calculated to put it to the output side link ℓ9. Similar operations are performed by other work nodes. A rule of converting a data-flow into a program is shown in Figs. 3A and 3B. Fig. 3A shows a general data-flow diagram of each work node, wherein W represents a label of the work node, OP an instruction code, ℓ1 to ℓn labels of input side link nodes, and k1 to km labels of output side link nodes. A program instruction corresponding to the above data-flow diagram is expressed as in Fig. 3B. Fig. 4 shows a set of program instructions converted from the data-flow diagram shown in Fig. 2A in accordance with the rule. Executable instructions are those having all the data of input operands as described previously. In a case of a program shown in Fig. 4, first data a , b and c are put to links ℓ1, ℓ2 and ℓ3, respectively as their initial value (refer to Fig. 2A). At this initial state executable instructions are those at W1 and W2. After completion of executing the two instructions, the data on the link ℓ1 and ℓ2 disappear and they are put to links ℓ4, ℓ5, ℓ6 and ℓ7. At this state, executable instructions are those at W3, W4, W7 and W8. Similarly, executable instructions are caused to be executed sequentially or in parallel to repeat calculation operations in the following procedure until it becomes a state where there is no executable instruction. In the present embodiment, the execution continues until data are put to the links ℓ23 and ℓ24. The data structure includes three basic structures, i.e., Cartesian product, direct union and sequence structures. It is assumed that sets of data are D1 and D2. Then, a set of Cartesian data of D1 and D2 is a set of elements each element being a pair of D1 element and D2 element, and is expressed as shown in Fig. 5A. A set of direct union data of D1 and D2 is a set of elements each element being D1 element or D2 element, and is expressed as shown in Fig. 5B. A set of sequence data of D1 is a set of elements each element having no D1 element or D1 elements more than 1, and is expressed as shown in Fig. 5C. An optional combination of these basic structures is used to form a data structure. Fig. 6 shows a particular example of a combined data structure. A set of data "Current Year Pay Sequence" is constructed of a list of "Current Year Pay". "Current Year Pay" is a Cartesian product of "Name" and "Pay Amount". "Pay Amount" is a direct union of "Extra Pay Increase" and "Base Pay". "Extra Pay Increase" is a Cartesian product of "Base Pay" and "Pay Increase". The above data structures are coupled to link in the data-flow. Namely, the data structures are always associated with the links. A series of instructions are defined to the data structures. For the Cartesian data structure, there are prepared a product decomposition instruction and a product composition instruction. A general arrangement of Cartesian product decomposition is shown in Fig. 7A. The data structure D at the input side link L of a work node W is a Cartesian product of D1 to Dn, an instruction code assigned to the work node is a product decomposition instruction PD, and the data structure at the output side links L1 to Ln of the work node W are D1 to Dn. In this condition, when a value V of D is set at the link L, the work node becomes executable. Upon execution by the work node W, the value V is taken from the link and decomposed into elements V1 to Vn to set them at the output side links L1 to Ln, respectively. A general arrangement of Cartesian product composition is shown in Fig. 7B. The data structures at the input side links L1 to Ln of a work node W are D1 to Dn, an instruction code assigned to the work node is a product composition instruction PC, and the data structure D at the output side link L of the work node W is a Cartesian product of D1 to Dn. In this state, when values V1 to Vn of the data structures D1 to Dn are set at the links L1 to Ln, the work node W becomes executable. Upon execution by the work node W, the values V1 to Vn are simultaneously picked up to the work node to compose the values V1 to Vn into a value V which is set at the link L. For the direct union structure, there are prepared a union decomposition instruction and a union composition instruction. A general arrangement of direct union decomposition is shown in Fig. 8A. The data structure D at the input side link L of work nodes W1 to Wn is a direct union of D1 to Dn, an instruction code assigned to each work node is a union decomposition instruction UD, and the data structures at the output side links L1 to Ln of the work nodes W1 to Wn are D1 to Dn. In this condition, when a value V of D is set at the link L and the value V belongs to Di (i = 1 to n), the work node Wi becomes executable. Upon execution by the work node Wi, the value V is taken from the link and set at the link Li as the element of Di. A general arrangement of direct union composition is shown in Fig. 8B. The data structures D at the input side links L1 to Ln of work nodes W1 to Wn are D1 to Dn, an instruction code assigned to each work node is a direct union composition instruction UC, and the data structure D at the output side link L of the work nodes W1 to Wn is a direct union of D1 to Dn. In this condition, when a value Vi belonging to a link Li among the links L1 to Ln is set, the work node Wi becomes executable. Upon execution by the work node Wi, the value Vi is taken from the link and set at the link L as an element of D. For a sequence data structure, i.e., list, there are prepared a sequence decomposition instruction and a sequence composition instruction. A general arrangement of sequence decomposition is shown in Fig. 9A. The data structure D (e.g., list) at the input side link L of a work node W is a list of D1 (e.g., one line of the list), an instruction code assigned to the work node W is a sequence decomposition instruction SD, and the data structure at the output side link L1 is D1. In this condition, when a value V of D is set at the link L, the work node W becomes executable. Upon execution by the work node W, the value V is taken from the link and decomposed into sequence structure elements V1 to Vn all of which are set at the link L1 while maintaining this order of elements. A general arrangement of sequence composition is shown in Fig. 9B. The data structure at the input side link L1 of a work node W is D1, an instruction code assigned to the work node is a sequence composition instruction SC, and the data structure at the output side link L is a list of D1. In this condition, when values V1 to Vn (n is 1 or more) of D1 at the link L1 are set, the work node becomes executable. Upon execution by the work node W, the values V1 to Vn are simultaneously picked up to the work node to compose them into an element V of the sequence structure data D and set it at the link L. The formats of program instructions shown in Figs. 7A, 7B, Figs. 8A, 8B and Figs. 9A, 9B are shown in Figs. 10A to 10F. An example of data-flow handling such data structures is shown in Fig. 11. An embodiment of an automatic processing system as one of the applications of the present invention will be described next. Fig. 1 illustrates a block diagram showing a structured data driven type processor system of the invention by which a data-flow program handling structured data can be executed. The structured data driven type processor system of this embodiment includes a processor unit 1, a link buffer 2, a link buffer controller 3, an instruction buffer 4 and an execution controller 5. The processor unit 1 is comprised of a plurality of processors 6₁, 6₂, 6₃, ... The link buffer 2 is composed of an instance area 7 and a definition area 8, the former being comprised of a plurality of instance cells 9₁, 9₂, ... and the latter composed of a plurality of definition cells 10₁, 10₂, ... The instruction buffer 4 is composed of a plurality of instruction cells 11₁, 11₂, 11₃, ... Information on program instructions conforming with the instruction format shown in Fig. 3B is stored in the instruction cells 11₁, 11₂, 11₃, ... of the instruction buffer 4. The information is called an instruction packet in this specification. The format of the instruction packet is shown in Fig. 12A by way of example. An instruction packet is constructed of an instruction code, link information at the input side, and link information at the output side. How an instruction packet group for the data-flow shown in Fig. 11 is stored in the instruction buffer is shown in Fig. 12B by way of example. Link information of the data-flow program is stored in the instance cells 9₁, 9₂, 9₃, ... within the instance area 7 of the link buffer 2. Each link is labeled a number to uniquely identify the link. A value stored in a link is associated with the data structure for that link. Such data structure information is stored as a pointer to the definition cell 8. A format of a instance cell is shown in Fig. 13A by way of example. Data structure information is stored in the definition cells 10₁, 10₂, ... within the definition area 8 of the link buffer 2. Stored in a definition cell 10i (i = 1 to n) is structure information of Cartesian product, direct union and sequence shown in Fig. 5 or basic data type information. Fig. 13B shows examples of the format of the definition cells 10₁, 10₂, ... An example of the format of the link buffer 2 for the data-flow shown in Fig. 11 is shown in Fig. 14. Fig. 15 shows a flow chart illustrating an execution procedure of the execution controller 5 shown in Fig. 1. In operation of the execution controller 5, an instruction packet signal 12 is received (step 101) from the instruction buffer 4 to collect input operands of the instruction packet and generate an input link number string (step 102). Next, in order to judge if the state that an instruction becomes executable only when values at all the input links concerned have been set, is met or not, the input link number string signal 14 is sent to the link buffer controller 3 and the resultant judgement signal 13 is received (step 103). It should be understood that if an input link having only a single data value (token) is connected to a plurality of work nodes and the token is picked up by one of the work nodes, then the other work nodes enter into a disable state and are not executed with the packet being returned to the instruction buffer. If the judgement signal 13 indicates an executable state, the instruction packet signal 16 is sent to the processor unit 1 (step 104). If not, the instruction packet signal 15 is returned to the instruction buffer 4 (step 105). The above processes can be executed in parallel for each instruction cell 11 to thus improve the operating performance. Fig. 16 shows a flow chart showing the execution procedure of the processor unit 1 shown in Fig. 1. The processor unit 1 is comprised of a plurality of processors 6₁, 6₂, 6₃, ... so that a plurality of instruction packets can be processed in parallel. The operation of the processor unit 1 is as in the following. When the processor unit 1 receives an instruction packet signal 16 from the execution controller 5 (step 201), it assigns an idle processor to the execution of the instruction packet. After deriving input link numbers from the received instruction packet, a link number string signal 18 is sent to the link buffer controller to obtain values stored in the associated links, and a resultant link data string signal 17 is received (step 202). In the case of a failure of obtaining the link data, the instruction packet is returned to the instruction buffer without executing it (step 205). In the case of a success of obtaining the link data, based on the obtained values, a calculation is performed in accordance with the instruction code of the instruction packet (203). The resultant calculated data string is sent to the link buffer controller 3 as the output link data string signal 18 (step 204). After the calculation, the instruction packet signal 19 is sent to the instruction buffer 4 (step 205). Figs. 17A to 17C show flow charts illustrating the execution procedures of the link buffer controller 3 shown in Fig. 1. the link buffer controller 3 is used for performing an exclusive control of accesses to the link information of a data-flow program in accordance with a priority order. The procedures in accessing to link information include an execution judgement by the execution controller 5, a data acquisition and a data setting by the processor unit 1, all of which can be executed in parallel. The operation of the processor unit 1 is as in the following. Fig. 17A shows a flow chart illustrating the procedure of the execution judgement. When the link buffer controller 6 receives an input link number string signal 16 from the execution controller 5 (step 301), it stands by until all the links included in the link number string becomes unlock state (step 302), locks all the links to perform an exclusive control of link accesses from other processes (step 303), and judges if a value is set at each link (step 304). If all the links have set values, a judgement signal 13 indicative of executable state is sent to the execution controller 5 (step 306). If even one of the links has not a set value, a judgement signal 13 indicative of disable state is sent to the execution controller 5 (step 305). Lastly, the lock state of the links is released (step 307). Fig. 17B shows a flow chart illustrating the procedure of data acquisition. When the link buffer controller 3 receives a link number string signal 18 from the processor unit 1, it stands by until all the links included in the link number string becomes unlock state (step 309), locks all the links to perform an exclusive control of link accesses from other processes (step 310), is set at each link (311). If even one of the links has not a set value, a control signal 17 indicative of a failure of data acquisition is sent to the processor unit 1 (step 312). If all the links have set values, the link data are taken therefrom and the associated link data string signal 17 is sent to the processor unit 1 (step 313) to thereafter erase the taken data from the link (step 314). Lastly, in a similar manner to the above, the lock state of all the links is released (step 315). Fig. 17C shows a flow chart illustrating the procedure of data setting. When the link buffer controller 3 receives a resultant calculated output link data string signal 18 from the processor unit 1 (step 316), it stands by until all the links included in the output link data string signal 18 from the link buffer become unlock state (step 317), locks all the links to perform an exclusive control of link accesses from other processes (step 318), and sets data designated by the output link data string signal 18 at each link (step 319). Lastly, the lock state of all the links is released (step 320). According to the structured data driven type processor systems described in the above embodiments, not only conventional basic data can be processed, but also structured data having records, unions and lists can be directly processed. Therefore, a data-flow program which is more abstract and more easy to be understood by human can be developed, and the reliability of a program can be improved due to its easy understanding. Further, an operation handling structured data is introduced which operation can be performed in the similar manner as of other calculations. Therefore, parallel execution is ensured to thus improve the execution speed of a program. In the above embodiments, structured data driven type processor systems embodying the present invention have been described by way of example. However, it is obvious to those skilled in the art that the invention is not limited to structured data driven type processor systems, but it is also applicable to Von-Neumann type processor systems.

Claims: A method implemented in a computer, said method comprising a set of instructions for a data-flow program from a Petri net diagram modelling said program and being directed to structured data of at least one of, or a combination of, Cartesian product of sets, direct union of sets, and lists, said method comprising the steps of providing desired data paths (l1 ... ln), i.e. places in said Petri net diagram, each path having an associated data structure which defines the data to be processed; providing work nodes (W1 ... W9), i.e. transitions in said Petri net diagram, said work nodes including nodes (PD, UD, SD) to decompose such structured data into its constituent basic elements and nodes (PC, UC, SC) to compose constituent basic elements into such structured data; and converting said Petri net diagram so that for each work node a corresponding instruction is generated, each instruction having its respective input and output paths as operands. The method of claim 1, wherein said instructions include a decomposition instruction wherein structured data are used as an input operand and decomposed into constituent elements which in turn are used as output operands, and a composition instruction wherein constituent elements are used as input operands and composed into structured data which in turn are used as an output operand. A structured data processor system comprising an instruction buffer (4) for holding instructions in executing a data-flow program, execution control means (5) for judging whether fetched instructions are executable and sending them to a plurality of processors (1), and means for interconnecting said execution control means (5), said instruction buffer (4) and said plurality of processors (1), wherein those instructions having a complete set of operand data can be executed in parallel, characterised in that a link buffer (7) is provided for storing information on links representing a data-flow program diagram, said link buffer (7) having a storing area (8, 10) for storing information on a data structure which includes a Cartesian product of sets, direct union of sets and/or lists, that link buffer control means (3) are provided for performing an exclusive control of said information on said links and cooperating with said execution control means (5) for sending said information on said links to said plurality of processors (1) in accordance with instruction information from said instruction buffer, and that said instruction buffer comprises a storing area 11₁, 11₂, 11₃, ...) adapted to store a code indicating a decomposition instruction and a composition instruction, said decomposition instruction decomposing data for said program having said structure of a Cartesian product of sets, direct union of sets or lists, or data convertible into such data structure, into constituent elements in dependence on said data to be processed, and said composition instruction composing data of the aforesaid structure from constituent elements. The system of claim 3, characterised in that the link buffer (7) includes a storing area (9) for storing operands of instructions. The system of any of claims 3 to 4, characterised in that the format of the instructions stored in the instruction buffer (4) is an instruction packet including an instruction code and link information on the input and output of said instruction.

Inventors: OTSUKI SHIGERU, OTSUKI, SHIGERU
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1988
Main classification: G06F9
IPC codes: G06F9, G06F15