SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device determines a level of a select control signal according to a level of drive signals for two systems as generated in the preceding access cycle, and a level of the least significant bit of an address to fetch data in a desired serial access cycle. According to this select signal, a select cir­ cuit (10) selects one of the drive signals as generated by drive signal generating circuits (55, 58), and sup­ plies the selected signal to two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62). The function of this select circuit allows one of the two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62) to first start the data access operation.

Description: This invention relates to a serially-accessed type semiconductor memory device, and more particularly, to a semiconductor memory device of the type where, during the time a given address is being serially accessed, a serial access operation can be performed in relation to another address. Serially-accessed type memory devices have been developed which can operate at a high speed. In the memory devices, two data selecting/fetching systems are provided in a single semiconductor chip. When one of the data selecting/fetching systems is outputting data, the other is setting up other data to be output. This type of memory device is also referred to as an interleave type memory device. Fig. 1 illustrates, in block form, a major part of an interleave type semiconductor memory device described in unexamined Japanese Application No. 63-9096 published on 14.01.88. In this figure, a system A as one of the two selecting/fetching systems, contains data registers 51₁, 51₂, .... A system B as the other of those two data selecting/fetching systems contains data registers 52₁, 52₂, bit data as previously stored in a memory array (not shown). Column select gates 53₁, 53₂ .... select the data in data register 51 of system A, according to the signals on column select lines CA0, CA1, ... of system A. Similarly, column select gates 54₁, 54₂, ... select data in data register 52 of system B, according to the signals on column select lines CB0, CB1, ... of system B. Data buses DBA and DBA , incorporated in system A, are supplied with the data selected by column select gate 53, also incorporated in system A. Likewise, data buses DBB and DBB , incorporated in system B, are supplied with the data selected by column select gate 54, which is incorporated in system B. A drive signal generator 56 supplies a drive signal to address generator 55. Reference numeral 57 designates a serial address generator in the system B. A drive signal generator 58 in the system B supplies a drive signal to address generator 57. Address decoders 59₁, 59₂, ... in the system A are supplied with an output address from serial address generator 55. Address decoders 61₁, 61₂, ... in the system B is supplied with the output address from serial address generator 57. Column select gate drivers 61₁, 61₂, ... of the system A are supplied with a decoder output of address decoder 59. Column select gate drivers in the system B 62₁, 62₂, ... are supplied with the decoder output of address decoders 60, respectively. Data bus select gate 63 selects a data of data bus DBA or DBA . Data bus select gate 64 selects a data of data bus DBB or DBB . Output driver 65 outputs data OUT. Drive signal generators 56 and 58 of the systems A and B generate drive signals input to serial address generators 55 and 57, and other drive signals for controlling other circuits of these systems. The other drive signals contains signals to selectively activate column select gates 53 and 54, and data bus select gates 63 and 64. The drive signals generated by those signals generators are not illustrated, for simplicity. The conventional semiconductor memory shown in Fig. 1 operates as illustrated by timing charts shown in Figs. 2A to 2D. In this instance, the data access, or the data outputting from the data registers is performed in the order of data registers 51₁, 51₂, .... A serial access to be described is for the case of a cycle time to access the data of data register 51 contained in the system A. Specifically, since the preceding cycle is the cycle to access the system B, data bus select gate 63 in the system A is inactive, or in an off state, as in step S1 of Fig. 2B. Data bus select gate 64 in the system B is active, or in an on state, as in step S16 of Fig. 2C. In the system B, as shown in the subsequent steps S17 and S18, the data of the data register in the system B, e.g., the data of data register 52₁, is transferred to output driver 65, via data buses DBB and DBB . In the system A, which is disconnected from output driver 65 in the preceding cycle, an address is set by serial address generator 55, according to the drive signal output from drive signal generator 56 (step S2), address decoder 59 of the system A is selected (S3), and the decoder output renders column select line CA1 active (step S4), and the data of data register 51₂ is transferred to data buses DBA and DBA , as shown in step S5. When the serial access enters the present cycle, data bus select gate 64 of the system B is made inactive as shown in step S11, and the data bus select gate 63 of the system A is made active as shown in step S6. As a result, the data buses DBA and DBA in the system A are connected to output driver 65, so that the data from data register 51₂ is transferred to output driver 65, as shown in step S8. Then, it is output from output driver 65. At this time, in the system B which is disconnected from output driver 65, an address is set by serial address generator 57 according to the drive signal, which is output from drive signal generator 58 during the period from step S11 to S15, to select address decoder 60 in the system B. Further, column select line CB1 is made active by the decoder output. As a result, the data in data register 52₂ is transferred to data buses DBB and DBB bar, thereby completing the set-up for access in the next cycle. As seen from the foregoing description, the memory device of the interleave type substantially halves the cycle time when comparing with the memory device of other access system, and the access time is remarkably improved. In the memory device of the interleave type, the circuits in the systems A and B operate at the period, which is twice the period of an external serial access control signal (Fig. 2A) applied to drive signal generators 56 and 58, and these circuits operate with half-period staggered phase. To cause serial address generators 55 and 57 of the systems A and B to set addresses, drive signals with different phases must be generated by drive signal generators 56 and 58. It is assumed now that a serial access control signal applied to drive signal generators 56 and 58 is SC, and that the drive signals of the two systems which are generated by these drive signal generators 56 and 58 and vary at the double period of the period of signal SC, are designated by X and Y, respectively. These drive signals X and Y vary like the least significant bit signal of the address for serial access. As a matter of course, the serial address generator 55 of the system A is constantly supplied with drive signal X as generated by the drive signal generator 56 in the system A. Likewise, the serial address generator 57 of the system B is constantly supplied with drive signal Y as generated by the drive signal generator 58 in the system B. The above serial access system in which the drive signal X of the system A is supplied to the circuits of the system A and the drive signal Y of the system B is supplied to the circuits of the system B, involve the following problems. At the start of or during the serial access, if a start address of the serial access must be designated, one of the systems A and B must be started earlier than the other according to the least significant bit (LSB) of the serial access at that time. In the conventional serial access system of the memory device, however, the systems A and B alternately operate according to serial access control signal SC, and it is impossible to start the system A or B in a desired operation cycle. For this reason, the conventional memory device cannot execute various applied operations of the serial access, such as designation of the serial start address, and jump during the serial access. As described above, in the conventional serially-accessed semiconductor memory device which uses the two data selecting/fetching systems and alternately operates them for data fetching, it is impossible to start a desired one of those two systems earlier than the other in a desired operation cycle. Therefore, the conventional memory device cannot execute the various applied operations of the serial access. US-A-3 691 534 describes a permanent storage memory system comprising first and second memory units each having data stored thereon in different predetermined patterns. The outputs of each memory unit are connected to a common memory output. Timing signals are applied to each memory unit in reverse order and the selected data is transferred to the common memory output from one unit and then the other during the first and second of these signals, respectively. For each memory unit, data is blocked from the output during the period of the timing signal in which the data is not being transferred, thereby enabling ready combination of the data signals from each unit at the memory output. Data from each unit may be scanned in a predetermined sequence, that sequence being initiated from a location in that unit determined by an address signal applied to the unit. The selection of that initial memory location is performed by means of a shift register in combination with a logic unit. The latter receives an address signal and presets the shift register in accordance therewith. Accordingly, an object of this invention is to provide a serially-accessed semiconductor memory device in which any of the two selecting/fetching systems can be first started for serial access in a desired operation cycle, and which can execute various types of applied operations based on the serial access. According to this invention, there is provided a serially-accessed type memory device comprising a plurality of registers for storing data and two data selecting/fetching systems alternately operated for fetching data from said registers in an interleaved fashion, each of said systems comprising a serial address generating circuit and a drive signal generating circuit for generating a drive signal in response to a serial access control signal, the drive signals having different phases, characterized by a selection circuit for selectively applying one of said drive signals to one of the address generating circuits and applying the other one of the drive signals to the other one of the address generating circuits. The semiconductor memory device determines a level of a select control signal according to a level of drive signals for two systems as generated in the preceding access cycle, and a level of the least significant bit of an address to fetch data in a desired serial access cycle. According to this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional serially accessed type semiconductor memory; Figs. 2A to 2D are flowcharts for illustrating the data read operation by the semiconductor memory device shown in Fig. 1; Fig. 3 is a block diagram of a major part of a serially-accessed type semiconductor memory device according to this invention; Fig. 4 is a circuit diagram of a select circuit used in the semiconductor memory device of Fig. 3; Fig. 5 shows a table showing level relationships among drive signals input to the select circuit of Fig.4, select control signals, and drive signals output from the select circuit; Fig. 6 shows a select control signal generator for generating a select control signal to be input to the select circuit of Fig. 4; Figs. 7A to 7H show timing charts used in explaining the operation of the memory device shown in Fig. 3; and Fig. 8 is a circuit diagram of the select circuit used in the Fig. 3 memory device according to this invention. Preferred embodiments of this invention will be described referring to the accompanying drawings. In Fig. 3, like portions are designated by like reference symbols in Fig. 1 illustrating the conventional circuit arrangement, for simplicity of illustration. A serially-accessed semiconductor memory device comprises two data selecting/fetching systems A and B. Each of the systems A and B is made up of a data register (51 or 52), a column select line (CA or CB), a column select gate (53 or 54), data buses (DBA and DBA or DBB or DBB ), a drive signal generator (56 or 58), a serial address generator (55 or 57), an address decoder (59 or 60), a column select gate driver (61 or 62) and a data bus select gate (63 or 64). This memory device is based on the interleave access system in which the system A, for example, sets up data to be outputted, while the system B is outputting data. As shown in Fig. 3, the memory device of this embodiment uses a select circuit inserted between a pair of drive signal generators 56 and 58 and a pair of serial address generators 55 and 57. According to select control signals "α" and " α ", the select circuit selects a drive signal X generated by drive signal generator 56 and applies it to serial address generators 55 or 57 of both the systems A and B. Likewise, the select circuit selects a drive signal Y generated by drive signal generator 58 and applies it to serial address generators 55 or 57 of both the systems A and B. In Fig. 4, there is shown a circuit diagram of select circuit 10. As shown, the sources or drains of N channel MOS transistors 11 and 12 are connected together. The connection point is coupled for reception with drive signal X from drive signal generator 56. Similarly, the sources or drains of N channel MOS transistors 13 and 14 are connected together. The connection point is coupled for reception with drive signal Y from drive signal generator 58. The sources or drains of MOS transistors 11 and 14 are connected together. The signal at this connection point is output as drive signal A to serial address generator 55 in the system A. Similarly, the sources or drains of MOS transistors 12 and 13 are connected together. The signal at this connection point is output as drive signal B to drive signal generator 57 in the system B. The gates of MOS transistors 11 and 13 are coupled for reception with select control signal "α", while the gates of MOS transistors 12 and 14 are coupled for reception with select control signal " α ", which is the inversion of the signal "α". The levels of these control signals "α" and " α " are set as shown by a table of Fig. 5. At the start of a desired serial access cycle or during the serial access cycle, when a new serial address is designated, the drive signals X and Y as generated in the preceding access cycle are denoted as X′ and Y′, respectively. AO or BO indicate the levels of the least significant bit of the new serial address. The levels of select control signals "α" and " α " may be set by a circuit as shown in Fig. 6. Control signal "α" is formed by inputting the drive signal X′ and the LSB AO of the new serial address to exclusive OR gate 21. When the control signal "α" thus obtained is passed through inverter 22, the control signal " α " is obtained. The operation of the memory device thus arranged will be described referring Figs. 7A to 7H. According to serial access control signal SC shown in Fig. 7A, drive signal generators 56 and 58, respectively, generate drive signals X and Y at the period twice as long as that of control signal SC, and with different phases. Serial address generators 55 and 57 set addresses according to the drive signals A and B which are applied to serial address generators 55 and 57, from select circuit 10. In this way, the interleave serial access is performed for reading out data. It is assumed now that a desired address is designated in period T0 (Figs. 7A to 7F). To designate an address implies one of two cases; the system A first outputs data in the succeeding serial access cycle or the system B first outputs in the same cycle. State 1 shown in Fig. 7D indicates the case that the system A first outputs data in the addressed cycle. State 2 shown in Fig. 7E indicates the case that the system B first outputs data in the addressed cycle. In the cycle before period T0, the system to first output data cannot be specified. For this reason, those figures illustrate both the cases that drive signals A and B are logical "0" and "1". It is assumed that when the "1" level of drive signals X or Y are applied to serial address generators 55 and 57, the systems A and B are in a data outputting condition. It is assumed now that when it is state "1", an address to cause the system A to output data in period T0 is designated. In this case, the LSB AO of this serial address is logical "1". The drive signals X′ and Y′ in the cycle preceding to period T0 are logical "0" and "1", respectively (Figs. 7B and 7C). Therefore, control signals "α" and " α " become logical "1" and "0" in level, as seen from the Fig. 5 table. At this time, in the select circuit of Fig. 4, transistors 11 and 13 are turned on. Drive signal X as generated by drive signal generator 56 is input as signal A to serial address generator 55. Similarly, drive signal Y as generated by drive signal generator 58 is input as signal B to serial address generator 57. Accordingly, during period T1 starting at period T0, the system A first outputs data. In state 2, an address to cause the system B to output data in period T0. At this time, the LSB AO of this address is logical "0". Control signals "α" and " α " are logical "0" and "1", as shown in Fig. 5. In the select circuit of Fig. 4, transistors 12 and 14 are turned on. Drive signal X generated by drive signal generator 56 is input as signal B to address generator 57. Similarly, drive signal Y generated by drive signal generator 58 is input as signal B to address generator 55. Thus, in state 2, the system B first outputs data in serial access period T1 starting at period T0. As seen from the foregoing, in a designated access cycle, any of the systems A and B may first operate to output data. Therefore, the memory device according to this invention can executes various types of applied operations of the serial access, such as designation of the serial top address, and jump during the serial access operation. Since the memory device is based on the interleave access system, a high speed access is secured. In the above-mentioned embodiment, select circuit 10 selects one of the drive signals generated by drive signal generators 56 and 58, and supplies it to serial address generators 55 or 57. The function of this circuit 10 is applicable to other drive signals generated by drive signal generators 56 and 58, such as drive signals to control other circuits of the systems A and B. Such drive signals are those for selectively activating column select gates 53 and 54, and data bus column select gates 63 and 64. Fig. 8 shows a modification of the select circuit of Fig. 3. In the figure, the output terminal of inverter 81 is connected to the input terminal of clocked inverter 83, and the output terminal of inverter 82 is connected to the input terminal of clocked inverter 84. The connection point of the output terminal of inverter 81 and the input terminal of clocked inverter 83 is connected to the input terminal of clocked inverter 85. The connection point of the output terminal of inverter 82 and the input terminal of clocked inverter 84 is connected to the input terminal of clocked inverter 86. The output terminal of clocked inverter 85 is connected to the output terminal of clocked inverter 84, and the output terminal of clocked inverter 86 is connected to the output terminal of clocked inverter 83. In the select circuit thus arranged, drive signal X is applied to the input terminal of inverter 81, and drive signal Y is applied to the input terminal of inverter 82. Select control signals "α" and " α " are applied to the control terminals of clocked inverters 83 to 86, as shown in Fig. 8. The select circuit of Fig. 8 produces drive signals A and B, as in the Fig. 4 select circuit. The serially-accessed type memory device may operate according to these drive signals, as in the Fig. 4 case. It is evident that the N channel MOS transistors in the Fig. 4 select circuit may be replaced by P channel MOS transistors, if necessary.

Claims: A serially-accessed type memory device comprising a plurality of registers (51,52) for storing data and two data selecting/fetching systems (A,B) alternately operated for fetching data from said registers in an interleaved fashion, each of said systems comprising a serial address generating circuit (55,57) and a drive signal generating circuit (56,58) for generating a drive signal in response to a serial access control signal (SC), the drive signals having different phases, characterized by a selection circuit (10) for selectively applying one of said drive signals to one of the address generating circuits (55,57) and applying the other one of the drive signals to the other one of the address generating circuits. The memory device according to claim 1, characterized in that said selection circuit (10) is so arranged that when a new address to fetch data is designated, said selection circuit selectively applies said drive signals to the serial address generating circuits in accordance with the state of the least significant bit of said new address and the state of the drive signals in the previous serial access cycle, for fetching data.

Inventors: OHSHIMA, SHIGEO C/O PATENT DIVISION, SAHARA, HIROSHI C/O PATENT DIVISION, TODA, HARUKI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: G11C7
IPC codes: G11C8, G11C11, G11C7