FAST-TAG TRANSFER IMPROVEMENT

Abstract: Disclosed are techniques for quickly transferring data between a disk drive multi-control unit (cf. string controller) and a plurality of disk files, each file including a microprocessor, a R/W control stage, a servo stage plus an interface unit adapted to communicate with the multi-control unit. A principal feature is that the interface unit is provided with a "fast-tag buffer" adapted to provide special data storage and fast-transfer capability, and so communicate directly with the multi-control unit.

Description: FAST TAG TRANSFER IMPROVEMENT This disclosure relates to disk drive control means, and particularly to techniques for transferring instructions ("tags") to and from such. Workers in the art of controlling high speed disk drives for computer use will recognize there are certain problems that persist today. One problem involves the extent of time that a disk drive controller (e.g., for a set or "string" of disk actuators) must remain connected to a drive actuator to "pass" tag parameters; this can be a significant clog in securing fast system throughput. Conventionally, a drive microprocessor receiving and acknowledging command information is the limiting factor In the speed of transfer. Unless an invention similar to the embodiment described herein is used, there are few ways to increase such data transfer, with none of them particularly palatable. For instance, the microprocessor could be used with a faster basic clock speed; but a faster microprocessor clock reduces reliability by introducing more noise into the system. Alternatively, one could reduce the amount of microprocessor software needed to process command information; however, to reduce the amount of time in the software code routine one must eliminate or reduce other features like "zero seek detect" or fault checks. Such would also reduce system reliability and throughput. Alternatively, one might write commands to RAM memory via a DMA operation or one might use a multi-port RAM to read.old commands while executing present commands. These alternatives are not particularly efficient or desirable, either. -For example, in the present Memorex 3680 disk drive, performing a "seek to target" (tag 1A) requires passing three parameters to the drive (CAR high, CAR low, sector) . In the drive, the transfer is handled by the microprocessor (MPU) which runs at a basic cycle of 520 nsec. (see FIG. 2 and controllers 1 and 2 tied to a particular disk stack on a single spindle involving two actuators, each having two ports). Because of the MPU cycle speed and because of additional "drive-status-checking" performed, the following approximate times are required to transfer the three parameters (first tag gate up to "last tag valid up"). Best case: (actual seek-on-track) — 78 usec. Worst case: (zero seek, not on track) — 82 usec. For a string controller group like the mentioned #3680, if "tag valid" were returned immediately from the drive, the string controller could transfer four parameters in approximately 8 usec. (This assumes "First tag gate up to last tag gate down" and Best case with immediate "tag valid".) It can be seen that a substantial increase in throughput could be realized if the drive could accept parameters at the same rate that the string can send them. Such is the problem addressed by the present invention. The disclosed βrodimeπt proposes solving this problem by establishing a special "low order tag" (tag 0A) with the format shown in FIG. 1A and proposes adding hardware to implement this tag by providing for the reception and temporary storage of the (three or four) parameters to be passed. Additional hardware would be required for the direct loading of the head address register (HAR) by the MPU. FIG. 1 shows a block diagram of a logic block for controlling one actuator, e.g., of the type described aoove. Here, it should be assumed that interface stage DINT is advised by the microprocessor DMPU that the controller CC is "ready" to input data. The microprocessor DMPU is known to be relatively "slow" as compared with the controller CC, e.g. , it will take the order of 80 microseconds to validate all data bits, etc. , as known in the art. This forces the faster controller CC to either wait and waste valuable computer time, or else turn away from DINT* emporarily and divert to other tasks — in any event delays and complications result. Also, the. time involved in a "handshake" with the DMPU (that is, 80+usec. assumed) is relatively long and wasteful, since the CC is so fast (e.g., about 8 usec. ) . The disclosed errixdiπeTt proposes modifying things so that there is essentially no wait when controller CC makes a data transfer to a drive unit — allowing it to transfer at maximum speed via a "fast tag buffer" FTB (particularized below) which is faster than controller CC. Thus, for instance, when a controller wants to direct an actuator where to go for the next track input/output, the controller is released from waiting for the actuator and its associated DMPU to finish their tasks — instead it deals directly with this buffer FTB. (Note re: FIG. 2: there are two data paths to each actuator so that either of the two controllers can communicate with either actuator by either of two paths — cf. two actuators per HDA or spindle; two HDAs or four independent actuators per box; and four boxes per 3682 disk drive: a total of 16 actuators and 16 associated controllers.) The overall picture is as follows. In a disk drive like the Memorex 3682, commands ("tags") from a controller CC to a given actuator can involve "hardware tags" or "processor commands" (the MPU gets involved in the latter, e.g. , during a seek motion) . There are certain basic commands that a string controller gives to an actuator unit (such as a "Seek" command) where the MPU is involved, but this MPU will be recognized as relatively slow (e.g., transferring information over an 80 usec. period typically) as opposed to the controller CC (about 8 usec). Therefore, workers want to minimize the time that controller CC spends "handshaking" with an MPU — both to optimize the time usage by controller CC and also to keep from holding up the entire 3682 system, in some cases. We address this problem by providing a prescribed FTB buffer storing prescribed information to be transferred from a controller CC, thus allowing the controller to get on-line and off-line very quickly. As detailed below (e.g., see FIG. 3A) this buffer FTB allows controller CC to access the unit (DINT) any time, regardless of what the associated DMPU is doing, as long as the buffer FTB is "empty." Further, once buffer FTB has been emptied, it may be re-filled with the next command from the controller. According to a related feature of the so improved system it enables a controller CC to send information to a given actuator (DINT) at any time and as fast as possible, also to spend a minimum time contacting this DINT — thus it can be redirected to other tasks without delay. This improvement obviously frees-up controllers and microprocessors, to do other work and operate with less restriction. There will, of course, be a basic "preparation sequence," to allow a microprocessor to see if our new buffer FTB is ?full, " whereupon it may transfer the contents thereof into a given RAM memory and signal the controller CC to insert the next tag. In FIG. 3A, a portion of interface DINT will be seen as allocated to this buffer memory FTB, FTB preferably being operativel associated, with a buffer-full counter BC adapted, as known in the art, to indicate when FTB has been filled Buffered FTB may, for instance, comprise a four-byte, "pipeline register chip" (e.g., by AMD Corp.). This improvement feature will be appreciated by those skilled in the art as effected with only a few ve simple, readily available components and as involving little change in the normal software associated with a disk drive controller — e.g., needing only instruction for the MPU to look at, and extract the contents of, a buffer FTB (e.g., doing so only if the buffer is indicated as "full"). Brief Description of the Drawings: These and other features and advantages of the disclosed errbodimaπt of the present invention will be appreciated by workers as the become better understood by reference to the following detailed description of the present preferred embodimen which should be considered in conjunction with the accompanying drawings, wherein like reference symbols denote like elements: FIG. 1 is a schematic idealized block diagram o a control arrangement for a given disk drive actuator serving an associated disk stack; FIG. 1A is an exemplary arrangement of command information ( -parameters) as used with a subject embodiment; while FIG. 1AA illustrates a like arrangeme for a 3-parameter embodiment; FIG. 2 schematically indicates control data between an exemplary string controller and a pair of actuators served thereby; FIGS. 3A, 3B, and 4A, 4B, and 5 are block diagram details of respective DINT, DMPU, and DRWC units of the arrangement in FIG. 1; One preferred implementation of this embodiment is functionally indicated in the block diagram of FIG. 7, with the associated buffer; and FIG. 6 is an exemplary circuit implementation of a 3-parameter embodiment. Description of the Preferred Embodiment —General description, background: FIG. 7 schematically illustrates a fast tag buffer FTB and associated means constructed according to principles of this invention (implemented in the circuit of FIGS. 3A, 3B, and 6) . This, and other means discussed herein, will generally be understood as constructed and operating as presently known in the art, except where otherwise specified. And, except as otherwise specified, all materials, methods and devices and apparatus herein will be understood as implemented by known expedients according to present good practice. —Tag Description (four parameter) : Referring now to FIG. 1A, it will be understood that the first parameter passed would be HAR bits (only four HAR bits are needed here; the remaining bits could be special, "tag-modified" bits as discussed below) . The remaining three parameters would be the same as for a conventional "seek-to-target" (tag 1A). The second parameter would be the high-order cylinder address (CAR high), SA track identification and sector window definition. The third parameter would contain cylinder address low (CAR low). The fourth parameter would contain the target sector information. The special "tag-modified" bits in the first parameter (Ml, M2, M3, M4) change the meaning in execution of the tag; for example to indicate: 1. "Ignore HAR" (do seek and sector search but don't switch heads). 2. "Ignore CAR" (do HAR and sector search but do not seek). 3. "Ignore sector search" (do HAR and seek only) . 4. "Don't interrupt when sector found." 5. "Execute all parameters but interrupt at end of seek." 6. "Multiply window by a factor of 2 n " (that is, 2 2 , 2 4 , 2 8 , etc.). The above examples are not at all exhaustive, but give some indication of the possibilities. FIG. 7 shows a block diagram of our buffer FTB and associated counter BC and other exemplary hardware in a preferred embodiment. Here, buffer FTB may be viewed as a • "pipeline register" which is preferably configured as a "one byte-by-four" shift register. Register FTB is used to receive and store the incoming parameters. Data is clocked-in by "tag valid". The configuration can then be changed so that the MPU can read any one of the four registers in einy order. The associated counter BC is used to count the number of parameters passed and to generate a "buffer full" signal which tells the' MPU that all four parameters have been transferred and to start processing the tag data. Various MPU register bits are needed to allow the MPU to change "pipeline register" mode, to seϊect which register to read, and to detect status. Direct MPU loading of HAR would be required. Preferably, this arrangement in FIG. 7 would function as follows. Upon selection, parameters would be passed as with any conventional low-order tag. Parameters would be clocked-in (via "tag valid, " equals tag gate and no interface check). "Bus out" would be echoed to "bus in." When the "buffer full" signal is generated, it will cause a "drive busy" status to be posted. The "buffer full" signal will also cause the MPU to proceed to execute the tag. At the appropriate time in the cycle, the MPU will reset the "buffer full" signal and post the current drive status. —Tag Description (three parameters): Referring now to FIG.1AA, it will also be understood that three (3) parameters can be used. Here, the first parameter passed would be "tag-modified" bits as discussed below and the high-order cylinder address (CAR high). The second parameter would contain cylinder address low (CAR low). The third parameter would contain the target sector information. The special "tag-modified" bits in the first parameter (Ml, M2, M3, M4) change the meaning in execution of the tag; for example to indicate: 1. "Seek to Target" with window parameter. 2. "Set Sector" with window parameter. 3. "Seek to cylinder" only. Here, all elements will be arranged and function as before (FIG. 7) , except that, where counter BC is used to count the number of parameters passed and to generate a "buffer full" signal, it will tell the MPU that the three (3) parameters have been transferred and to start processing the tag data. —Results: Workers will recognize that the foregoing embodiment accomplishes many desirable results, particularly in reducing the time during which the drive and the string controller must be coupled for the controller to pass command information to the drive. Thus, a system so enhanced can use a relatively slow microprocessor and still prove quick and reliable in communicating with the controller. Conventional softwar can be maintained and enhancements provided without complication. In addition, this "fast tag" feature increases system throughput by allowing the next command information to be given to the drive while the microprocessor is busy with a current command. In particular, workers should focus on the fact that, using this invention, a disk drive can receive new "seek" or "sector search" commands, while executing present commands — a capability not presently provided in the art. - li ¬ lt will be understood that the preferred embodiment described herein are only exemplary, and that the invention is capable of many modifications and variations in construction, arrangement and use without departing from the spirit of the invention. Further modifications of the disclosed erbodiri HT t is also possible. For example, the means and methods disclosed herein are also applicable to other high density disk files, as well as to related systems. Also, the present invention is applicable for enhancing other like control systems. The above examples of possible variations of the present invention are merely illustrative. Accordingly, the present invention is to be considered as including all possible modifications and variations coming within the scope of the invention as defined by the appended claims.

Claims: What is claimed is: 1. A method of quickly transferring data between disk drive multi-unit control means C and a plurality of file units A, each unit A including microprocessor means mP, read/write control means R/W and servo means S, along with interface means I adapted to communicate with said multi-unit control means C; wherein the interface means I is provided with fast-tag buffer means B adapted to provide special data storage and related transfer capability for faster communi ' cating directly with control means C 2. The invention of claim 1 wherein buffer means B is arranged and controlled to transfer data much faster than microprocessor means mP with speed akin to that of control means C and is arranged to avoid the need for microprocessor mP transferring data to or from control means C. 3. The invention of claim 2 wherein buffer means B is arranged and adapted to allow control means C to access unit A virtually any time, regardless of what microprocessor means mP is doing. 4. The invention of claim 3 wherein buffer means B is arranged and adapted to be automatically filled, or re-filled, without intervention by microprocessor means mP. 5. The invention of claim 1 wherein buffer means B is arranged and adapted to allow control means C to communicate with unit A via buffer means B at virtually any time and at controller-speed, means C comprising a controller, unit CU. 6. The invention of claim 5 wherein microprocessor means mP is arranged and adapted to prepare unit A for insertion of a tag by controller unit CU by transferring the contents of buffer means B into storage provided therefor and also indicating this to controller unit CU. 7. The invention of claim 6 wherein buffer means B comprises a "pipeline register" chip means. 8. The invention of claim 7 wherein buffer means B includes counter means B-C arranged and adapted to count parameters passed to the register chip and means to signal "Buffer-Full" to microprocessor means mP. 9. The invention of claim 3 wherein buffer means B comprises a "pipeline register" chip means. 10. The invention of claim 9 wherein buffer means B includes counter means B-C arranged and adapted to count parameters passed to the register chip means and signal "Buffer-Full" to microprocessor means mP. 11. Disk drive file unit comprising a stack of recording disks, actuator-head means adapted to position R/W transducer means across respective disk surfaces; servo actuator means S adapted to control such positioning; read/write control means R; microprocessor means P and interface means I arranged and adapted to communicate with means S, R, and P as well as with external controller means CC, said interface means I being provided with fast-tag buffer means B adapted to communicate directly, and quickly, with controller means CC, being adapted to store data therefor.

Inventors: GLIDER JOSEPH, TORTORELLI DANIEL W, WARNER NICHOLAS M, GLIDER, JOSEPH, TORTORELLI, DANIEL, W., WARNER, NICHOLAS, M.
Applicants: UNISYS CORP, UNISYS CORPORATION
Application year: 1988
Main classification: G06F3
IPC codes: G06F3, G06F12