Semiconductor device comprising a field effect transistor

Abstract: A semiconductor device comprising a semiconductor substrate (1), a field effect transistor (Q) formed in the substrate (1), and a diode (D) connected to the field effect transistor (Q) and formed on the insulation film (11) formed on the substrate (1). Since the diode (D) is electrically insulated from the substrate (1) by the insulation film (11), no parasitic PNPN thyristor is formed in the semiconductor substrate (1). Therefore, a latch-up is prevented from occurring in the semiconduc­ tor device.

Description: The present invention relates to a semiconductor device and to a method of manufacturing same. EP-A2-0 060 635 discloses a semiconductor integrated circuit device including a vertical type MOSFET and a gate protection element for the MOSFET in which the vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n + -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n + -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film, and uses the silicon substrate as the drain, and in which the gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and has an n + -p-n + structure. EP-A2-0 060 635 also discloses a main integrated circuit and a protection element for protecting same. The main integrated circuit comprises a memory circuit connected to an external terminal, and further comprises another circuit. The protection element is connected between the external terminal and ground. Fig. 1 is a cross-sectional view of a conventional semiconductor device, which is known to the applicant but not disclosed in a pre-published document, having a field effect transistor to which a diode is connected, and in which a current flows in a specified direction. This semiconductor device comprises semiconductor substrate 1, N - type epitaxial layer 2 formed on substrate 1, and P type element-isolating layer 7 formed on substrate 1 and separating N - type epitaxial layer 2 into two portions. A field effect transistor is formed in the first portion of N - type epitaxial layer 2. The field effect transistor comprises P-channel region 3 formed in the first portion of epitaxial layer 2, N + type source region 4 formed in P-channel region 3, N + type drain region 5 in the first portion of epitaxial layer 2, insulation film 11 formed on epitaxial layer 2 and element-isolating layer 7, and gate electrode 6 formed on insulation layer 11 and located above N + type source region 4. A diode is formed in the second portion of N - type epitaxial layer 2. This diode comprises N + type cathode region 9 and P + type anode region 8. N + type cathode region 9 is electrically connected by aluminum wire 10 with N + type drain region 5 of the field effect transistor. When a current flows in the forward direction within the semiconductor device shown in Fig. 1, it flows into the drain region 5 of the field effect transistor through P + type anode region 9, N + type cathode region 8, and aluminum wire 10. Since the field effect transistor and the diode are formed tow epitaxial layers both formed on the same substrate, another current may flow, in some cases, from P + type anode region 8 the anode into N + type drain region 5 of the field effect transistor through N - type epitaxial layer 2 and P type element-isolation layer 7, due to a surge voltage generated when the semiconductor device is switched on or off or when the power-supply voltage of the device varies. In other words, a current may flow through epitaxial layer 5 and isolation layer 7 as if the PNPN thyristor parasitic in this device were turned on. This phenomenon is generally known as "latch up." Generally it is difficult to prevent a latch-up form taking place within semiconductor devices. When a latch-up occurs in a semiconductor device, heat is generated in the device, destroying the elements formed within the device in some cases. It is accordingly the object of this invention to provide a semiconductor device in which a latch-up does not occur, and to provide a method of manufacturing same. According to the invention indicated in claim 1 with respect to the device, no parasitic PNPN thyristors are formed within the substrate. Therefore, a latch-up is prevented from occurring in the semiconductor device. According to the invention indicated in claim 5 with respect to the method, the diode and the field effect transistor are formed at the same time, not in independent processes. Therefore, the semiconductor device of this invention can easily be manufactured. Moreover, no element-isolations need to be formed to isolate the diode and the field effect transistor from each other, and the semiconductor device can, therefore, be comparatively small. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-sectional view of a conventional semiconductor device comprising a semiconductor substrate, a field effect transistor formed in the substrate, and a diode formed in the same substrate and connected to the field effect transistor; Figs. 2A to 2F are diagrams explaining how a semiconductor device according to this invention is manufactured; Fig. 3A is an equivalent circuit diagram of the semiconductor device according to the present invention; Fig. 3B shows a circuit using the semiconductor device shown in Fig. 3A; Fig. 4A is a cross-sectional view of a semiconductor device including the circuit shown in Fig. 3B; and Fig. 4B is a cross-sectional view of another semiconductor device including the circuit shown in Fig. 3B. An embodiment of the invention, which is a semiconductor device comprising a double diffused MOS transistor (hereinafter referred to as "DMOS transistor") and a diode connected to the DMOS transistor, is manufactured in the manner illustrated in Figs. 2A to 2F. First, N - type epitaxial layer 2 is formed on semiconductor substrate 1. Then, element-isolation layer 7 is formed in epitaxial layer 2, as is shown in Fig. 2A. SiO 2 insulation film 11 having a thickness of 700 nm (7000 Å) is formed on epitaxialy layer 2 and element-isolating layer. As a result, the unfinished product shown in Fig. 2A is obtained. Two portions of insulation film 11 are removed, thereby exposing those portions of epitaxial layer 2 in which the source and drain regions of DMOS transistor Q will be formed. SiO 2 films 12 having a thickness of 100 nm (1000 Å) are formed on these exposed portions of epitaxial layer 2 by means of steam oxidation performed at 1000°C for 10 to 15 minutes. Then, polycrystalline silicon layer 13 is formed on SiO 2 insulation film 11 and 12 by means of the CVD method, thereby forming the unfinished product shown in Fig. 2B. Thereafter, polycrystalline silicon layer 13 is patterned, leaving only those two portions of layer 13 which will be diode D and gate electrode 6 of DMOS transistor Q, respectively. As a result, the structure shown in Fig. 2C is completely formed. Photo-etching is then applied to the unfinished product. Boron ions are implanted into that portion of epitaxial layer 2 in which the source region of DMOS transistor will be formed, in a dose of 5 × 10 13 atom/cm 2 , by applying an acceleration voltage of 60 KeV. Boron ions are also implanted into that portion of polycrystalline silicon layer 13 which will be used as the anode of diode D, also in the dose of 5 × 10 13 atom/cm 2 , by applying an acceleration voltage of 60 KeV. The boron, thus ion-implanted, is thermally diffused, whereby a P-channel region 3 is formed in epitaxial layer 2, and P + type anode 8 is formed, as is illustrated in Fig. 2D. P-channel region 3 horizontally extends, with its one end located below gate electrode 6 of DMOS transistor Q. During the thermal diffusion of boron, the crystal grains of silicon layer 13 grow, the polycrystalline silicon layer 13 changes to almost a single-crystal layer. Hence, the flowing of the leak current which flows when the PN junction of diode D is reversely biased can be reduced. Insulation films 12 are photographically etched, thereby exposing those portions of epitaxial layer 2 in which the source and drain of DMOS transistor Q will be formed. Ions of phosphorus or arsenic are implanted into the exposed portions of layer 2, in the dose of 1 × 10 16 atom/cm 2 by applying an acceleration voltage of 30 KeV. Simultaneously, phosphorus or arsenic ions are implanted into, under the same conditions, polycrystalline silicon layer 6 and that portion of polycrystalline silicon layer 13 which will be used as the cathode of diode D, in the same conditions. The phosporus or arsenic, thus ion-implanted, is thermally diffused, thus forming N + type source region 4, N + type drain region 5, gate electrode 6, and N + type cathode region 9 of diode D. As a result, the unfinished product shown in Fig. 2E is obtained. Thereafter, SiO 2 insulation film 14 having a thickness of 700 nm (7000 Å) is formed on insulation films 11 and 12 by means of the CVD method. The entire structure is then heat-treated. Contact holes are made in insulation film 14, thereby exposing source region 4 and drain region 5 of DMOS transistor Q, and also exposing anode region 8 and cathode region 9 of diode D. An aluminum film is formed on the upper surface of the entire structure, and is then patterned, thereby forming electrodes 10, one of which electrically connects drain region 5 of DMOS transistor Q with cathode region 9 of diode D. Thus, the unfinished product shown in Fig. 2F is obtained. A passivation film (i.e., a silane coating) is formed on the upper surface of the unfinished product, whereby the semiconductor device of this invention is manufactured. The equivalent circuit of this device is shown in Fig. 3A. As is evident from this figure, the cathode of diode D is coupled to the drain of DMOS transistor Q. Fig. 3B illustrates a circuit consisting of the device shown in Fig. 2F and DMOS transistor Q2. The anode of diode D is connected to the source of DMOS transistor Q2, and the drain of DMOS transistor Q1 (or Q) is connected to the gate of DMOS transistor Q2. This circuit can be used as a push-pull (bi-directional) output circuit. Figs. 4A and 4B are cross-sectional views of semiconductor devices, each using the circuit shown in Fig. 3B. In the device shown in Fig. 4A, drain 5 of DMOS transistor Qlis connected to cathode 9 of diode D by means of electrode 10, and source 4 of DMOS transistor Q2 is connected to anode 8 of diode D by means of other electrode 10. In the device shown in Fig. 4B, both DMOS transistors Q1 and Q2 are of a vertical type. Two island regions, each consisting of N + type layer 15 and N- type epitaxial layer 2 formed in layer 15, are formed in semiconductor substrate 1 by refill epitaxial growth method. Using these island regions, DMOS transistors Q1 and Q2 are formed. As can be understood from Fig. 4B, drain 5 of transistor Q1 is coupled to cathode 9 of diode D by electrode 10, and source 4 of transistor Q2 is connected to anode 8 of diode D by other electrode 10. Even if a power-supply voltage of 200 V or more is applied to the devices shown in Figs. 4A and 4B, no latch-up occurs in the push-pull circuits, unlike in the conventional device shown in Fig. 1 wherein the diode is formed in N - type epitaxial layer 2. Thus, the devices illustrated in Figs. 4A and 4B can operate without making errors even if the power-supply voltage is 200 V or more. The present invention is not limited to the embodiments described above. Various changes and modifications can be made.

Claims: A semiconductor device comprising: a semiconductor substrate (1); an epitaxial layer (2) formed on said substrate (1); an element-isolation layer (7) formed in said epitaxial layer (2); a first double diffused field effect transistor (Q1) formed in said epitaxial layer (2) and having a source electrode (4), a drain electrode (5), and a gate electrode (6); a second double diffused field effect transistor (Q2) formed in said epitaxial layer (2) and having a source electrode (4), a drain electrode (5) and a gate electrode (6); an insulation film (11) formed on said semiconductor substrate (1); and a diode (D) formed on said insulation film (11) and having an anode electrode (8) and a cathode electrode (9), said anode electrode (8) being connected to said source electrode (4) of said second double diffused field effect transistor (Q2) and said cathode electrode (9) being connected to said drain electrode (5) of said first double diffused field effect transistor (Q1). The semiconductor device according to claim 1, wherein said diode (D) and said gate electrodes (6) of said first and second double diffused field effect transistors (Q1,Q2) are made of the same material. The semiconductor device according to claim 2, wherein said material is almost single crystal silicon. The semiconductor device according to claim 2, wherein said material is polycrystalline silicon. A method of manufacturing a semiconductor device comprising the steps of: a) forming an epitaxial layer (2) on a semiconductor substrate (1), forming an insulating film (11) on a major surface of said epitaxial layer (2); b) forming an almost single crystal film (13) or a polycristalline film on said insulating film (11); c) forming a gate electrode (6) formation area and a PN junction (8,9) diode (D) formation area by patterning said almost single crystal film (13) or said polycrystalline film; d) simultaneously forming a channel region (3) of a double diffused field effect transistor and an anode (8) of said diode (D) by introducing a first impurity into said epitaxial layer (2) and said diode (D) formation area, respectively and thermally diffusing said first impurity; e.1) simultaneously forming a source region (4), a drain region (5), and a gate electrode (6) of said double diffused field effect transistor and a cathode (9) of said diode (D) by e.2) introducing a second impurity into said channel region (3) where said source region (4) is to be formed, e.3) simultaneously introducing said second impurity into said epitaxial layer (2) where said drain region (5) is to be formed and into those portions (6, 13) of said almost single crystal film (13) or said polycristalline film where said gate electrode (6) and said cathode (9) are to be formed, and e.4) thermally diffusing said second impurity; and f) forming a connection electrode (10) which electrically connects said drain region (5) to said cathode (9) of said diode (D).

Inventors: KAWAMURA KEN, SHIRAI KOJI, KAWAMURA, KEN, SHIRAI, KOJI, KAWAMURA, KEN C/O PATENT DIVISION, SHIRAI, KOJI C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1988
Main classification: H01L27
IPC codes: H01L29, H01L27