Voltage supply switching device for nonvolatile memories in MOS technology

Abstract: Two P channel selection transistors (5, 6) are inserted in respective connecting circuit branches between two external pins (2, 3) with voltages Vcc and Vpp respectively and an internal node (4). A switching circuit (12) controls said selection transistors (5, 6). Circuit means (11) are provided to hold the body bias of the selection transistors (5, 6) at a voltage equal to the highest voltage present from time to time at said external pins (2, 3).

Description: The present invention relates to a voltage switching device for nonvolatile memories in CMOS technology. In particular the invention is applicable to EPROM memories for switching an internal node between normal supply voltage (Vcc) and a higher programming voltage (Vpp) to perform programming or writing of the memory. The invention also allows use of the programming pin , i.e. the pin normally designed to receive the programming voltage, for other purposes, e.g. as the input/output element in a microprocessor. As known, an EPROM Memory receives part of the supply through an internal node which is alternately connected to a supply pin with voltage Vcc (5V) or a programming pin with voltage Vpp (12.5V) depending on whether the memory is subjected to reading, programming or writing. For switching said internal node between one voltage and the other there is usually employed a switching device comprising two N channel selection transistors placed one on one and the other on the other of two circuit branches connecting two external pins with voltage Vcc and Vpp and the aforesaid internal node and a switching circuit assigned to control of said selection transistors. To pilot the transistor placed on the branch which leads to the programming pin there is provided a voltage multiplier which allows application to the gate of said transistor of a voltage higher than Vpp. This leads to circuit complexity and layout problems related to the voltage multiplier. An object of the present invention is to accomplish a switching device for the above use which would not necessitate a voltage multiplier and would thus be much simpler to construct as compared with the known art. Another object is to accomplish a switching device for the above use which would also allow the use of the programming pin for other purposes, e.g. as the input/output element in a microprocessor. The Patent Abstract of Japan, Vol.7, no. 224 (P-227) [1369], October 5th, 1983 discloses a switching device having all the features in the preambule of Claim 1. US-A-4 658 156 discloses an analog voltage detection circuit including a voltage comparator for detecting an input voltage Vpp larger in absolute value than the power supply voltage Vcc. It appears clear that the use of P channel transistors pilotable in conduction with zero gate voltages in place of the N channel transistors (pilotable in conduction with positive gate voltages higher than the source voltage of said transistor) makes it possible to dispense with the voltage multiplier with the resultant advantages of circuit simplicity and layout. At the same time the P channel transistors require their body to be held at a voltage equal to the highest voltage present in the circuit so as to prevent charge injections into the substrate. In the present case this problem is worsened by wishing to use the programming pin as an input/output element so that said pin is susceptible of accepting lower voltages equal to or higher than the supply voltage Vcc. In accordance with the invention this problem is solved by a switching device as defined in claim 1. An embodiment of the present invention is illustrated for greater clarity and as an example in the annexed drawings wherein - FIG. 1 shows in the most general terms the use of a switching device in accordance with the invention for voltage control in an internal node of an integrated circuit comprising a nonvolatile memory accomplished with CMOS technology, FIG. 2 shows a block diagram of the switching device in accordance with the invention, and FIGS. 3, 4 and 5 show the circuit details of the three blocks which make up the switching circuit of FIG. 2. With reference to FIG. 1 reference number 1 indicates the switching device as a whole inserted in a single monolithic structure with a memory, e.g. EPROM (not shown), while reference numbers 2 and 3 indicate the external terminals or pins which carry the normal supply voltage Vcc and the programming voltage Vpp respectively and reference number 4 indicates the internal node selectively switchable to one or the other of the two voltages As shown in FIG. 1 the switching device comprises two P channel selection transistors 5 and 6 each of which is inserted in one of the two circuit branches 7 and 8 respectively which connect the supply terminals 2 and 3 to the internal node 4. The gate terminals of the two transistors 5 and 6 are piloted by a switching control unit 9 which also receives the two supply voltages Vcc and Vpp and is subjected to two control signals PRG and EPR which will be explained below. A block diagram of the switching control unit 9 is shown in FIG. 2 where it is seen to comprise an analog comparator 10, a body bias circuit 11 for the P channel transistors and a switching circuit 12 to control the switching of the selection transistors 5 and 6. All the above circuits 10, 11 and 12 receive the two supply voltages Vcc and Vpp. The comparator 10 compares them and emits a digital output signal UC whose high or low logic level indicates whether Vpp is higher or lower than Vcc. It also holds its output signal level low each time it receives a high level signal EPR indicating the intention to use the programming pin 3 as the input/output element or other. Depending on the logic level of the output UC of the comparator 10 the bias circuit 11 makes available at its output terminals 13 and 14 two bias voltages Vb and Vbb which are the same and are equal to the voltage from time to time the higher of the two supply voltages Vcc and Vpp. The switching circuit 12, which also receives the two bias voltages Vb and Vbb, performs switching control of the two transistors 5 and 6 on the basis of the logic level of the output signal UC of the comparator 10 and under the general control of the programming signal PRG coming from the general control unit of the integrated circuit (not shown). The analog comparator 10 is illustrated in its circuit details in FIG. 3 where it is seen to comprise a comparison stage 15 formed of a first circuit branch including two N channel transistors 16 and 17 in series between the supply Vcc and ground and a second circuit branch including two N channel transistors 18 and 19 also in series between the supply Vcc and ground. The transistor 16 is gate piloted with the Voltage Vcc while the transistor 18 is gate piloted with the voltage Vpp. The two transistors 17 and 19 have a common gate connected to the source of the transistor 17. An intermediate node 20 between the transistors 16 and 17 is connected to ground through an N channel transistor 21 which has its gate connected to an intermediate node 22 between the transistors 18 and 19. The node 22 is also connected to ground through an N channel transistor 23 which has its gate connected to the node 20. The two nodes 20 and 22 are also connected to ground through respective N channel transistors 24 and 25 whose gate terminals are connected to respective drain terminals. Between the transistors 16 and 18 and the circuit nodes 20 and 22 are placed respective P channel transistors 26 and 27 with the body connected to Vcc, whose gate terminals are capable of receiving the EPR signal. The same thing takes place for an N channel transistor 28 placed between the circuit node 22 and ground. An inverter 29 is placed between the circuit node 22 and an input of a NOR gate 30 whose other input is connected to the output of an inverter 31 which receives the programming voltage Vpp. The digital output signal UC of the analog comparator 10 is made available at the output of the NOR gate 30. The body bias circuit 11 is illustrated in detail in FIG. 4 and comprises an inverter 32 which has its input connected to the output UC of the comparator 10 and its output connected to the gate terminal of a P channel transistor 33 with the body connected to the source and of an N channel transistor 34, said transistors 33 and 34 being connected in series between a voltage supply terminal Vpp and ground. The output of the inverter 32 is also connected to the gate terminal of a P channel transistor 35 with body connected to the drain placed between the terminal with voltage Vpp and the bias terminal 13 (voltage Vb). This is connected to the gate terminal of a P channel transistor 36 with body connected to the voltage bias terminal Vb placed between the terminal with voltage Vpp and the bias terminal 14 (voltage Vbb). An intermediate node 37 between the transistors 33 and 34 is in turn connected to the gate terminal of a P channel transistor 38 with body connected to the drain placed between the terminal with voltage Vcc and the bias terminal 13, as it is also connected to the gate terminal of a P channel transistor 39 with body connected to Vb, which is placed between the terminal with voltage Vcc and the bias terminal 14. The switching circuit 12 illustrated in detail in FIG. 5 comprises a NAND gate 40 to the inputs of which are applied the output signal UC of the comparator 10 and the programming signal PRG. The output signal of the NAND gate 40 is applied to the input of a voltage translator 41 which has the task of supplying the desired control voltages to the gate terminals of the selection transistors 5 and 6. The voltage translator 41 comprises four P channel transistors 42-45 with body connected to Vbb and which are placed on four parallel circuit branches between Vbb and ground and in series with respective N channel transistors 46-49. The transistors 42 and 45 have their gate terminals connected to an intermediate node between the transistors in series 43 and 47 while the transistors 43 and 44 have their gate terminals connected to an intermediate node between the transistors in series 42 and 46. The transistors 46 and 47 have their gate terminals connected to the output of the NAND gate 40 directly and through the inverter 50 respectively. The transistor 48 has its gate terminal connected to an intermediate node 51 between the transistors 45 and 49 as well as to the gate of the selection transistor 5 which has its body connected to the drain. The transistor 49 has the gate terminal connected to an intermediate node 52 between the transistors 44 and 48 as well as to the gate of the selection transistor 6 which has its body connected to Vb. Finally the switching circuit 12 comprises an N channel transistor 53 placed between Vcc and the gate of the selection transistor 6. The gate of the transistor 53 is controlled by the voltage Vpp through an inverter 54. Due to the effect of the described structure the switching device illustrated as an example in the drawings is designed to operate in the following manner. The analog comparator 10 (FIG. 3) continually compares Vcc (always 5V) with Vpp (12.5V in the programming phase and 5V in the reading phase). When Vpp is higher than Vcc as in the programming phase the transistor 18 conducts more than the transistor 16 so that the circuit node 22 of the comparison stage 15 rises to a high level voltage and, through the inverter 29 and the NOR port 30, originates a high level output UC. When Vpp is equal to or lower than Vcc as in the reading phase the transistor 16 conducts more than the transistor 18 so that the circuit node 22 falls to a low level with resulting similar fall of the output signal UC. Basically therefore UC is high level if Vpp is higher than Vcc and low level if not. This latter situation also occurs when it is desired to use the programming pin 3 for purposes other than memory programming. In this case a high level signal EPR turns off the P channel transistors 26 and 27 and causes conduction of the N channel transistor 28 so that the circuit node 22 falls to low level and causes a similar fall of the output UC of the comparator. Current consumption for this use is thus small. Through the inverter 31 and the NOR gate 30 it is possible to obtain an immediate fall of the level of the output signal UC in case of a sudden fall of voltage Vpp due for example to breaking of the supply circuit. The voltage level of the output signal UC of the comparator 10 is used by the body bias circuit 11 and the switching circuit 12. The body bias circuit 11 (FIG. 4) uses it specifically to hold at the highest voltage available, Vpp or Vcc, body bias of all the P channel transistors which might have source and drain bias higher than body bias. As is known this is essential to prevent charge injections into the substrate. When UC is at high level indicating that Vpp is higher than Vcc, i.e. the memory is in the programming phase, the gate terminals of the P channel transistors 35 and 36 are low level so that said transistors conduct and transfer to the terminals 13 and 14 the voltage Vpp, i.e. creating bias voltages Vb and Vbb equal to Vpp. At the same time the transistors 38 and 39 are turned off, the circuit node 37 being at high level due to the effect of the conduction of the P channel transistor 33 and turning off of the N channel transistor 34 caused by the low level applied to their gate terminals. In this situation all the P channel transistors have their body at voltage Vpp, i.e. at the highest voltage present at that moment in the circuit. When UC is low level, indicating that Vpp is lower than or equal to Vcc, i.e. the reading phase prevails or the programming pin 3 is used for other purposes according to a high level signal EPR or there is a sudden fall of the voltage Vp, the gate terminals of the transistors 35 and 36 are at high level so that said transistors are extinguished while the transistors 38 and 39 conduct, the circuit node 37 being at low level due to the effect of the conduction of the transistor 34 and of extinction of the transistor 33. At the terminals 13 and 14 there are therefore present bias voltages Vb and Vbb equal to Vcc. In this situation all the P channel transistors have their body at voltage Vcc, i.e. at the highest voltage present in the circuit at that moment. If a high level signal EPR is present, the voltage Vpp at the external pin 3 cannot be higher than Vcc. As already mentioned the voltage level of the output UC of the comparator is also used by the switching circuit 12 (FIG. 5). Said signal is combined with the signal PRG at the NAND port 40 so as to enable said signal PRG to control the alternate switching of the selection transistors 5 and 6 and hence application of the voltage Vcc (in memory reading phase or for uses of the pin 3 other than programming of said memory) or of the voltage Vpp (in the programming phase of the memory) to the internal node 4 depending on the voltage level of the output UC and hence based on the voltage Vpp present at the pin 3. It should be noted that the bias voltages Vb and Vbb generated by the bias circuit 11 ensure the desired body bias at the highest voltage level present in the circuit to the various P channel transistors shown in FIG. 5. The high level UC signal allows the programming signal PRG to control for the internal node 4 selection of the programming voltage Vpp which said signal UC indicates at that moment as being higher than Vcc and hence suitable for programming the memory. With two high level signals UC and PRG the output of the NAND gate 40 goes to low level and through the voltage translator 41 causes application of a voltage 0 to the gate of the selection transistor 6 and of a voltage equal to Vbb (i.e. Vpp i.e. 12.5V) to the gate of the other selection transistor 5. Hence the latter is open while the former conducts and transfers the programming voltage Vpp to the internal node 4. In this situation the inverter 54 and the transistor 53 have the task of immediately turning off the transistor 6 in case of a sudden fall of the voltage Vpp. A low level signal UC, indicating the absence of a suitable programming voltage Vpp equal to 12.5V, whether because the reading phase prevails or because the pin 3 is being used for purposes other than programming or because power has suddenly been removed, blocks the output of the NAND gate 40 at high level, disabling the programming signal PRG and causing through the voltage translator circuit 41 application of a voltage 0 to the gate of the selection transistor 5 and a voltage equal to Vbb (i.e. Vcc i.e. 5V) to the gate of the selection transistor 6. The latter is thus turned off while the former conducts and transfers the supply voltage Vcc to the internal node 4.

Claims: Voltage supply switching device for nonvolatile memories in CMOS technology, comprising two selection transistors (5, 6) of P channel type inserted in respective circuit connection branches between two external pins (2, 3) with voltage Vcc and Vpp respectively and an internal node (4), and a switching circuit (12) controlling said selection transistors (5, 6), characterized in that it also comprises an analog comparator (10) to compare said voltages Vcc and Vpp and generate an output signal (UC) at either one of two voltage levels depending on the result of said comparison, and circuit means (11) including means (32-39) responsive to said output signal (UC) to vary the body bias of the selection transistors (5, 6) according to the voltage level of said output signal (UC), so as to hold the body bias of said selection transistors (5, 6) at a voltage (Vb, Vbb) equal to either one of the voltages (Vcc or Vpp) present at said external pins (2, 3), whichever is the higher one of the two voltages (Vcc, Vpp). Device in accordance with claim 1 characterized in that said analog comparator (10) also comprises an input for a signal (EPR) for the forced switching of said output signal (UC) to the same voltage level which is generated when the voltage Vpp is lower than Vcc and said signal (EPR) is off. Device in accordance with claim 1 characterized in that said circuit means (11) comprise at least one pair of P channel bias switching transistors (35, 38; 36, 39) inserted in respective connecting circuit branches between terminals with voltage Vpp and Vcc and a bias terminal (13, 14) for production of the bias voltage (Vb, Vbb) and means (32, 33, 34) sensitive to the voltage level of the output signal (UC) of the comparator (10) which control said bias switching transistors (35, 38; 36, 39) in such a manner as to transfer to said bias terminal (13, 14) the voltage, Vpp or Vcc, which said output signal (UC) indicates to be higher than the other. Device in accordance with claim 3 characterized in that said circuit means (11) comprise two pairs of said bias switching transistors (35, 38; 36, 39) for production of equal bias voltages (Vb, Vbb), one (Vb) for the body bias of the P channel transistors of said circuit means (11) and one (6) of said selection transistors (5, 6) and the other (Vbb) for body bias and supply of the P channel transistors of said switching circuit (12), the other (5) of said selection transistors (5, 6) having the body biased by said internal node (4). Device in accordance with claim 1 characterized in that said switching circuit (12) comprises means (40) for combination of said output signal (UC) of the analog comparator (10) with a programming signal (PRG) and means (12) for converting the result of said combination into control signals for said selection transistors (5, 6). Device in accordance with claim 5 characterized in that said switching means (12) comprise a voltage translator supplied with said bias voltage (Vbb).

Inventors: GAIBOTTI MAURIZIO, SECOL MAURIZIO, GAIBOTTI, MAURIZIO, SECOL, MAURIZIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1988
Main classification: G11C5
IPC codes: H01L29, H01L27, H01L21, G11C16, G11C5, G11C17