APPARATUS AND METHOD FOR SYNCHRONIZATION OF ARITHMETIC EXCEPTIONS IN PARALLEL PIPELINED EXECUTION UNITS

Abstract: A data processing system central processing unit (11) is disclosed having a plurality of parallel pipelined execution units (e.g., 25 Fig. 4), and other apparatus (22) for implementing a special, DRAIN instruction, to permit the processor (11) to complete instructions preceding the DRAIN instruction which are currently being processed by the execution units (25), but prevent later processing of instructions until all currently executing instructions are completed and all outstanding exception conditions are resolved. After all the preceding instructions are executed, central processing unit (11) continues to execute the sequential program instructions when no arithmetic exception has been identified, or invokes an exception handling procedure when an arithmetic exception has been identified. The DRAIN instruction permits the response to arithmetic exceptions identified after the execution of the DRAIN instruction to be handled in the same context environment in which the instruction was initiated.

Description: Apparatus and method for synchronization of arithmetic exceptions in parallel pipelined execution units RELATED APPLICATIONS This application is related to the following Patent Applications, all of which were filed in the U. S. Patent and Trademark Office on the filing date of the present Patent Application. APPARATUS AND METHOD FOR RECOVERING FROM MISSING PAGE FAULTS IN VECTOR DATA PROCESSING OPERATIONS invented by David N. Cutler, David A. Orbits, Dileep Bhandarkar, Wayne Cardoza and Richard T. Witek; having Serial No. 069.372 ; filed on March 20, 1987 and assigned to the assignee of the present U.S. Patent Application. APPARATUS AND METHOD FOR .PROVIDING AN EXTENDED PROCESSING ENVIRONMENT FOR NON-MICROCODED DATA PROCESSING SYSTEMS invented by David N. Cutler, David A. Orbits, Dileep Bhandarkar, Wayne Cardoza and Richard T. Witek; having Serial No. 069 ,365 ; filed on March 20, 1987 and assigned to the assignee of the present U.S. Patent Application. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generall to data processing systems and more particularly to data processing systems in which the system architecture permits parallel execution of a plurality of instructions . During the operation of the data processing system, events can occur within the system that require the execution of a procedure that is outside the explicit activity required for the completion of the currently executing program. When the events are relevant primarily to the currently executing program, the system response typically is to invoke a software procedure which is executed in the same context as the current program. The notification of such an event is termed an exception. When the event is primarily relevant to other software procedures or to the system as a whole, the response must be processed in a system-wide context. The notification of this latter type event is termed an interrupt. This invention relates to a set of exceptions referred to as arithmetic exceptions. 2. Description of the Related Art In order to achieve high performance in a data proc-essing system, one technique is to provide apparatus for executing a plurality of instructions in parallel (i.e., instructions whose execution overlap in time). However, when one or more of the currently executing instructions results in an arithmetic exception, such as an integer overflow, exponent overflow or underflow, etc, the determination of the exact location of the instruction that produced the arithmetic exception can be extremely difficult. In addition, the diversity of possible exception origins complicates the creation of a software environment for efficiently responding to the arithmetic exceptions. Computer architectures, such as the DEC VAX data processing systems and the IBM System/370 data processing systems respond to an arithmetic exception by aborting all instructions that were initiated after the first instruction to signal an exception condition. For a multiplicity of reasons, such as the differences in instruction execution speed, this technique is difficult to implement in the parallel execution of multiple instructions environment. Other high performance data processing architectures, such as the CDC-7600 data processing system and the Cray-1, Cray-XMP and the Cray-2 data processing systems simply stop executing instructions at a convenient point in the program environment and provide no method for identifying instructions that signalled an exception condition. In addition, these architectures provide no mechanism for synchronizing the instruction execution with an environment created to respond to the identification of an arithmetic exception. A need has therefore been felt for a technique to provide a systematic response to the identification of and response to arithmetic exceptions in a data processing unit that can have a plurality of instructions in simultaneous execution. FEATURES OF THE INVENTION It is an object of the present invention to provide an improved data processing unit. It is a feature of the present invention to provide an improved data processing system in which multiple instructions can be in simultaneous execution. It is yet another feature of the present invention to provide an instruction that permits the completion of the instructions currently in execution. It is a still further feature of the present invention to provide an instruction that assists in providing a synchronized response to arithmetic exceptions in the data processing system environment wherein a plurality of instructions can be in simultaneous execution. SUMMARY OF THE INVENTION The aforementioned and other features are accomplished, according to the present invention, by- providing an instruction, hereinafter referred to as the DRAIN instruction, and apparatus supporting that instruction, that permits all instructions for which execution has been initiated, but has not been completed when the Drain instruction is initiated, to be completed before further instructions can be executed in the data processing system. The invention also provides for an arithmetic exception summary mask for scalar and vector registers that designates which registers received exceptional results. The DRAIN instruction is used to respond to the detection of an arithmetic exception within the data processing context environment in which the exception has been identified. The same arithmetic exception within a different data processing context environment can have different implications. These and other features of the present invention will be understood upon reading of the following description along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A and Figure IB are block diagrams of exemplary data processing system configurations capable of utilizing the present invention. Figure 2 is an exemplary block diagram of a central processing unit capable of effective utilization of the instant invention. Figure 3 is a general timing diagram illustrating the complexity of recovering from detection of an arithmetic exception in a multi-execution unit environment. Figure 4 is a block, diagram illustrating the apparatus required to implement the present invention. Figure 5 illustrates the operation of the DRAIN instruction according to the present invention. Figures 6A , 6B and 6C define the arithmetic exception frame generated as a result of the identification of an arithmetic exception according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures Referring now to Fig. • 1A and Fig. IB, two exemplary data processing system configurations capable of using the present invention is shown. In Fig. 1A, the central processing unit (#1) 11 is coupled to a system bus 19. Other central processing units (e..g., #N) 12 can also be coupled to the system bus 19. The central processing unit(s) 11 (through 12) process groups of logic signals according to the structure of the central processing unit(s) in conjunction with central processing unit control programs, the control programs being comprised of groups of logic signals entered in the central processing unit or resident in the central processing unit (i.e., in firmware apparatus). The groups of non-resident logic signals are typically stored in the main memory unit 15 and transferred to and from the central processing unit(s) via the system bus 19. Input/output unit(s) {#1} 16 (through {#n} 17) couple devices such as mass memory storage units, user terminal devices and communication devices to the data processing system by means of the system bus 19. The mass storage units store the logic signal groups required by the data processing unit(s). Sets of logic signal groups, ypically designated as pages of data, required for the operation of the central processing units 16 through 17 are transferred from the mass storage units, having relatively slow accessibility, to the main memory unit to hich access by the central processing unit is relatively fast. The bus oriented system has an advantage in the relative ease to reconfigure the system but has the disadvantage that the each system component requires control apparatus to provide an interface with the system bus 19. Referring next to Fig. IB, a data processing system is shown in which the central processing unit(s) 11 (through 12) and the input/output unit(s) 16 (through 17) are coupled to the main memory unit 15 through a memory control unit 14, the memory control unit 14 replacing the system bus 19 of the data processing system configuration shown in Fig. IB and the control function performed by the individual data processing system components in the bus oriented configuration of Fig. 1A. The memory control unit 14 provides a centralized control and monitoring of the transfer of logic signal groups that can be more efficient than the bus oriented configuration of Figure 1A, but with the loss of flexibilit . Referring next to Fig. 2, a block diagram of an exemplary central processing unit capable of effective utilization of the present invention is illustrated. The issue unit 22 is responsible " for for providing (decoded) instructions to the plurality of specialized execution units comprising scalar operation address generation unit 24, at least one execution unit (#1) 25 (through execution unit {#Q} 26) and a vector operation unit 28, the vector operation unit including vector operation processing unit 28A,. vector operation address generation unit 28B and vector operation registers 28C. The logic signal groups processed by the execution units are typically extracted from the scalar registers 23 or the vector registers 28C. The output logic signal groups from the execution units are stored in scalar registers 23, in the vector registers 28C or in the data cache memory unit 27. The data cache memory unit 27 can be viewed as a cache memory unit providing an interface between the main memory unit 15 and the central processing unit 11. (The data cache memory unit 27 is shown as being coupled directly to the main memory unit in Fig. 2. As illustrated in Fig. 1A and Fig. IB, the actual coupling can include intervening data processing apparatus.) The issue unit 22 includes apparatus for determining which execution unit will process a selected signal group and for determining when the selected execution unit is available for processing a logic signal group. This latter feature' includes ascertaining that the destination storage location will be available to store the processed logic signal group. The instruction cache memory unit 21 stores the instructions that are decoded and forwarded to the appropriate execution unit by the issue unit 22. The issue unit 22 has the apparatus to attempt to maximize the processing operations of the execution units. Thus, the issue unit 22 includes pre-fetch apparatus and algorithms to insure that the appropriate instruction (including any branch instruction) is available to the issue unit 22 as needed. The plurality of execution units are, as indicated by the scalar operation address generation unit 24 and the vector operation unit 28, specialized processing devices, each for handling certain classes of processing operation. For example, an execution unit can be configured to handle floating point operations, or integer arithmetic operations, etc. The issue unit 22 has associated therewith scalar registers 23 that can store logic signal groups required for the execution of the program or for providing a record of the data processing operation. For example, one register is the Program Counter register that stores the (virtual) address of the next instruction, in the executing program instruction sequence, to be processed. The scalar operation address generation unit 24 is used to convert virtual addresses to physical locations in the main memory unit 15. The issue unit 22 is also responsible for reordering the logic signal groups from the execution units in the correct sequence when the execution units process instructions at different rates. In order to increase the processing speed of the « data processing system, the execution units are implemented using pipelined techniques in addition to providing for the parallel execution of multiple instructions. This implementation technique can be understood by reference to Fig. 3 which illustrates features of the pipelining process. The execution unit processing instruction #n in the instruction sequence actually performs the associated operation in five stages, each occupying a time interval of "T". The sum of T Q through T 4. i.e., 5X"T" , can occupy a time interval to perform the associated operation that can exceed the time interval needed to perform the operation in the same technology, but without the multiplicity of stages. The advantage arising from the pipelined implementation is that an instruction can be completed by the execution unit every "T" time interval. When the "T" time interval is appreciably shorter than the time interval for non-pipelined operation, then an instruction sequence can be executed more rapidly. Referring again to Fig. 3, when instruction # n is applied to an execution unit performing an arithmetic operation and begi»ns the activity identified by the instruction during time interval T n , after a sequence of suboperations , each occupying a time interval "T", the results of the instruction are available during time interval T, for the illustrated 5-stage pipelined processor unit. However, during the normal course of operation, the issue unit will apply new instruction # n+1 during time interval T, , instruction #n+2 during time interval T„ and instruction #n+3 during time interval T,, instructions #n+l , #n+2, and #n+3 all being applied to an execution unit, but not necessarily the same execution unit, before the execution unit result for instruction #n and possible arithmetic exception associated therewith is available during time interval T, . To further complicate the processing environment, the different execution units can have different times to complete the execution an instruction (e.g., the number of pipelined stages can be different. Thus, for example, the execution unit result and possible arithmetic exception for instruction #n+2 can be available before the execution unit result and possible arithmetic exception detected for instruction #n. Referring next to Fig. 4, the apparatus required to implement the present invention is illustrated. .In the issue unit 22, an instruction register 221 is provided in which the current instruction is decoded and applied to the appropriate execution unit. When the DRAIN instruction of the present invention is entered in the instruction register 221, decision network 222 responds to the instruction by preventing the next sequential instruction from being entered into the instruction register 221 , not permitting decoding of the next instruction or some other appropriate activity that prevents the issuance of the next instruction until all instructions currently in ^ execution have been completed without identification of an arithmetic exception. In the meantime, each execution unit 25 applies to the (decision network 222) of the issue unit 22 a signal from signal apparatus 253 indicating when any instruction executing in the execution unit is complete. Because the issue unit 22 maintains files of uncompleted execution activity, the issue unit 22 can determine when all activity is complete. In addition, in the execution unit 25, exception apparatus 252 is coupled to the output apparatus 251 of the execution unit 25. Referring next to Fig. 5, instead of instruction #n+3 being applied from the issue unit 22 in time interval T« as shown in Fig. 3, the DRAIN instruction is applied at this point. Then, in time interval " T , the next instruction is either the procedure for responding to the detected arithmetic exception(s) when an exception is detected or the next sequential instruction when no arithmetic exception is detected. Referring next to Fig. 6A , Fig. 6B and Fig. 6C, the arithmetic exception frame generated hen an arithmetic exception is identified according to the preferred embodiment is illustrated. In the arithmetic exception frame 600 of Fig. 6A, the first longword (i.e. , 4 bytes of logic signals) 601 of the exception frame stores the exception summary information (i.e., from the exception summary register. The contents of this parameter or longword are described below. The second longword 602 stores the vector register write mask, while the longwords 603 and 604 store the scalar register write mask. The register write masks of longwords 602, 603 and 604 identify the register into which were written the results identified as an arithmetic exception. A one-to-one correspondence exists between the position of bits in the mask and registers that can receive the exceptional results. For example, in the preferred embodiment, 64 scalar registers are present and each bit field of longword 604 and 605 is associated with a scalar register, i.e. 0 through 63. The parameter in longword 605 is the processor status (i.e. , the contents of the processor status register), which is described below. In longword 606, the virtual address of the next instruction is stored. This address in parameter 606 is the address of the instruction following the drain instruction. Referring next to Fig. 6B, the definition of the exception summary parameter 601 is shown. The bit 0 position 611, designated FUN in Fig 6B indicates that a floating point arithmetic or conversion operation underflowed the destination exponent. The bit 1 position 612, FDZ, indicates that a division by zero in a floating point operation was attempted. The bit.2 position 613, FRS, indicates that an attempt was made to perform a floating point arithmetic, conversion,- or comparison operation and at least one of the operands was reserved. The bit 3 position 614, FOV, indicates that an attempt to perform an floating point arithmetic or conversion operation resulted in an overflow of the destination exponent. The bit 4 position 615, IDZ, indicates that an attempt was made to perform an integer divide operation with a divisor of zero. The bit 5 position 616, IOV, indicates that an integer arithmetic operation or conversion from floating point format to integer format overflowed the precision available at the destination location. The bit 6 position 617, COE, indicates that a co-processor read or write with a trap enable set was executed hen a co-processor exception was identified. In Fig. 6C, the processor status parameters 605 are identified. For these parameters, bit 0 position 621, CM, indicates the access mode of the currently executing program wherein a "0" logic signal indicates a privileged mode of operation and a "1" logic signal indicates a non-privileged or user mode of operation. The bit 1 position 622, VMM, indicates a processor execution mode that is not directly related to the present invention. The bit 2 position 623, VRF, is set in the processor status parameter when a vector restart frame has been saved during initiation of an exception. The bit 3 position 624, VEN, controls whether vector instructions can be executed. hen this position has a signal set therein, vector instructions can issue normally. Otherwise, an attempt to issue a vector instruction will result in a vector operation enable fault. The bit 4-6 positions 624, IPL, define the interrupt priority level for the current processor execution activity. 2. Operation of the Preferred Embodiment The central processing unit having pipelined execution units of Fig. 2 was implemented in the preferred embodiment subject to several constraints, however, other design implementations can utilize the present invention. The central processing unit includes a plurality of execution units, each execution unit adapted to execute a class of instructions. By way of example, one execution unit, the scalar address generating unit 24, controls the transfer of the logic signal groups between the central processing unit and the main memory unit 15, i.e., executes the load/store instructions. One execution unit can be adapted to execute data signal group shifting operations, one execution unit for floating point add/subtract operations, one execution unit for integer and floating point multiply operations and one execution units for integer and floating point divide operations. The specialized execution units can be, but are not necessarily implemented in a pipelined configuration. The other features of the central processing unit are the following. The instruction in the currently executing sequence of instructions is transferred to the issue unit 22 from the instruction cache memory unit 21. In the issue unit 22, the instruction is broken down into its constituent parts and data-dependent control signals and address signals are generated therefrom. However, before an instruction can begin execution (i.e., be issued), several constraints must be satisfied. All source and destination registers for the instruction must be available, i.e., no write operations to a needed register can be outstanding. The register write path must be available at the future cycle in which this instruction will store the processed quantity. Only one result can be stored into the registers per cycle. All instructions (with the exception of load operations which are predicted on the basis of cache memory unit hits) have a fixed, data independent execution time. The execution unit to be required for processing the instruction during the execution must be available to perform the operation. All units (with the exception of the divide execution unit) can be pipelined and can accept a new scalar instruction each machine cycle. The divide execution unit is iterative and can execute a new divide operation only when the previous divide operation is completed. With respect to the vector operation unit, a vector operation reserves an execution unit for the duration of the vector operation. When a memory load/store instruction experiences a cache memory unit miss, the load/store unit busy flag will cause the subsequent load/store instructions to be delayed until the cache memory miss response is complete. When an instruction does issue, the destination register and the write path cycle for the result are reserved. During operand set-up, all instruction-independent register addresses are generated, operands are read and stored, and data-dependent control signals -are generated. The instruction operands and control signals are passed to the the associated execution unit for execution. The result generated by the execution unit is stored in the register files or in the data cache memory unit 15 as appropriate. Once an instruction issues, the result of the processing may not be available for several machine cycles. Meanwhile, in the next machine cycle, the next instruction can be decoded and can be issued when the requisite 'issue conditions are satisfied. Thus, the instructions are decoded and issued in the normal instruction sequence, but the results can be stored in a different order because of the varying instruction execution times of the execution units. " This out of order storing of the results of the processing operations can complicate the excep t ion handling and the retry of failing instructions. However, these events are relatively rare and the out of order storing provides execution and hard are advantages . The execution of a DRAIN instruction provides that all the instructions, currently in execution in a data processing system will be completed before a next instruction is executed. Therefore, a principal use Drain instruction is between changes in the context environment ' . When all active instructions have been completed, either the next instruction will be issued or an arithmetic exception procedure will begin execution. This selection ensures that all arithmetic exceptions generated from previously issued, but uncompleted instructions, are processed in a consistent software environment or processing contex . The presence of an arithmetic exception does not necessarily mean that the data signal group causing the arithmetic exception is defective. The 3 data processing context environment determines whether the data signal group causing the arithmetic exception is defective. This relationship indicates why the processing of an arithmetic exception in the appropriate data processing context environment is important. For example, a program or routine can be in execution for which arithmetic overflows and underflows are an expected result. The presence of an arithmetic exception in this context environment can cause the subroutine or program to scale the data signal groups in an attempt to avoid the exceptional condition. However, if the data processing context environment had been altered between the identification of an arithmetic exception and the resulting response, the response to the arithmetic exception can be inappropriate, In order to facilitate response -to the identification of an arithmetic exception, once the instructions in execution are completed, an exception summary mask is developed that identifies the (scalar and vector) registers that have received results that are identified as exceptional, (i.e., results that are not correct because of an arithmetic exception condition). This summary mask is made available to the privileged operating system software along with the continuation program counter. The summary mask .and the contents of the continuation program counter permit operating system exception handling software to identify the instructions resulting in the arithmetic exception conditions. It will be clear to those skilled in the art of data processing system design that the DRAIN instruction (and the apparatus implementing execution of the drain instruction) can be used to verify hardware implementation of data processing system circuit designs and can be use to assist in the verification of software programs. The DRAIN instruction can be inserted in the executing program instruction sequence immediately following instructions for which a problem is anticipated. In this manner, the results of the instruction sequence to the location of the DRAIN instruction can be verified. High level programming language compilers can use the DRAIN instruction when the program is compiled for debugging. In this application, the Drain instruction is positioned between groups of program instructions that comprise -the translation of the high level language statement. When the instruction sequence generates an arithmetic exception, the verification (debugging) procedure can identify the statement in the source program that resulted in an arithmetic exception. The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.

Claims: What is Claimed is; 1. In a data processing unit of a data processing system in which multiple instructions can be in simultaneous execution, apparatus responsive to at least one predetermined condition in said data processing system comprising: first means responsive to a preselected group of logic signals for permitting completion of currently executing instructions and for preventing execution of additional instructions until said ' currently executing instructions are completed; and second means responsive to said preselected logic signal group and said at least o e predetermined condition for executing a next instruction when said at least one predetermined condition is not present and for executing a responsive procedure when said at least one predetermined condition is present. 2. The condition responsive apparatus of Claim 1 wherein said at least one predetermined condition is an arithmetic exception conditions. 3. The condition responsive apparatus of Claim 2 further comprising register means for storing signals from selected registers after completion of execution of said instructions being executed after application of said preselected signal group. 4. The condition responsive apparatus of Claim 3 wherein said preselected signal group is included in a program being executed by said data processing system, said preselected signal group being included in the next sequential program location after a program instruction potentially resulting ' in detection of said at least one predetermined condition in s'aid data processing unit. 5. The condition responsive apparatus of Claim 4 wherein said preselected signal group is a D IN instruction. 6. The method of responding to an arithmetic exception in a multi-execution unit central processing unit of a data processing system comprising the steps of: providing a predefined instruction, said predefined instruction resulting in the steps of: causing all instructions executing when said predefined instruction is initiated to complete execution; and preventing a next sequential instruction from initiating execution until all said executing instructions are complete. 7. The method for responding to an arithmetic exception condition of Claim 6 further comprising the step of providing a procedure for responding to an arithmetic exception condition generated prior to completion of said executing instruction. 8. The method for responding to an arithmetic exception condition of Claim 7 further comprising the step of executing a next sequential program instruction when no arithmetic fault is signaled prior to completion of said executing instructions. 9. The method of responding to an arithmetic exception condition of Claim 8 further comprising the step of testing a program by placing said predefined instruction after an instruction capable of producing an arithmetic exception. 10. A data processing system comprising: at least one central processing unit, each said at least one central processing unit including: an issue unit for controlling execution of an instruction sequence; and a plurality of execution units for processing said instruction sequence, each of said execution units including signal means for signaling to said issue unit a presence of an arithmetic exception, said issue unit including apparatus responsive to a predetermined instruction for permitting said execution units to complete currently executing instructions, said prede ermined instruction preventing an instruction from issuin from said issue unit until said currently executing instruction are complete. 11. The data processing unit of Claim 10 wherein said predetermined instruction is a DRAIN instruction . 12. The data processing unit of Claim 11 further comprising exception handling means, said predetermined instruction causing said exception handling means to execute a procedure when at least one of said currently executing instructions causes an arithmetic exception. 13. The data processing unit of Claim 12 wherein said predetermined instruction causes a next instruction in said instruction sequence to be issued when said currently executing instructions do no t result in an arithmetic exception. 14. The data processing unit of Claim 13 wherein said exception handling means includes storing a context of the data processing unit at an occurrence of an arithmetic exception. 15. The data processing unit of Claim 13 wherein a next sequential instruction is issued by said issue unit after each arithmetic exception has been responded to by said exception handling means.

Inventors: BHANDARKAR DILEEP, CARDOZA WAYNE, CUTLER DAVID N, ORBITS DAVID A, WITEK RICHARD T, BHANDARKAR, DILEEP, CARDOZA, WAYNE, CUTLER, DAVID, N., ORBITS, DAVID, A., WITEK, RICHARD, T.
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1988
Main classification: G06F9
IPC codes: G06F9, G06F17