VECTOR PROCESSOR SUITED FOR SORTED VECTOR DATA

Abstract: Vector elements are compared with vector elements that precede the vector elements in synchronism with the supply of the vector elements to the arithmetic unit, and the operation to be effected for the individual vector elements is selected depending upon the compared results. Namely, a break is detected between the elements arranged in ascending order and the elements arranged in descending order that are subsequently read in parallel with the merging operation for the vector element read in the previous time, and the merging for the vector elements subsequently read is effected for either the ascending order elements or the descending order elements depending upon the detected result.

Description: BACKGROUND OF THE INVENTION The present invention relates to a vector processor, and more specifically to a vector processor suited for processing symbols such as sorting the symbols. So far, an apparatus has been known which consists of a specially designed hardware for sorting data sequences at high speeds relying upon vector processing as disclosed in EP-A-0 149 213. This apparatus makes it possible to sort the mergings in the form of vectors that could not hitherto been treated in the form of vectors. According to the above prior art, however, no attention has been given to the cases where data sequences that are to be sorted are biased, e.g., where input data sequences have almost all been sorted already from the first time. This problem will now be described briefly with reference to drawings. Fig. 10 is a diagram which schematically illustrates the sorting method using a vector processor according to the conventional art. When the input vector elements to be sorted consist of 2, 5, 7, 4, 1, 6, 8 and 3 according to this method, the vector elements are divided at the center into two vectors, i.e., x = (2, 5, 7, 4) and Y = (1, 6, 8, 3). Next, based on a prerequisite that the data are arranged in a random fashion in the vectors X and Y, the length of ascending order elements in each of the vectors is designated to be 1 to serve as a parameter at the time of executing the merge sorting instruction, and the data are merged one by one from the start of the vectors X and Y. The merging stands for a processing in which the elements of X and Y are compared and a smaller one (or a larger one) is produced. As a result, vectors 1, 2, 5, 6, 7, 8, 3 and 4 are produced in which successive two elements have been sorted. Therefore, the vectors are divided again into a vector X = (1, 2, 5, 6) and a vector Y = (7, 8, 3, 4). The merge sorting instruction now designates that there are ascending order elements having a length 2 in each of the vectors, and then the successive two elements are merged. As a result, vectors 1, 2, 7, 8, 3, 4, 5 and 6 are produced in which successive four elements are sorted. The vectors are divided again into X = (1, 2, 7, 8) and Y = (3, 4, 5, 6). This time, the elements are merged with the length of ascending order elements as 4, and the sorting of the whole elements is completed. According to this system, it is allowed to designate only those elements having a predetermined length as ascending order elements in the vectors, but it is not allowed to process the vectors that consist of elements having varying lengths. That is, the length of the ascending order elements is doubled for each merging, i.e., the length increases to 1, 2, 4, ---for each merging. Therefore, if the length of the input vector is N, the merging must be carried out log₂ N times. In this case, the merging must be carried out log₂ 8 = 3 times. This system is based on the presumption that the input vectors are arranged in a random fashion. In practically inputting the data, however, the data are biased in many cases. For instance, the data may be arranged nearly in ascending order from the first time. This system, however, is not capable of utilizing the nature of such data elements. EP-A-0 184 828 describes a vector processor having the features included in the first part of claim 1. Similar to the prior art referred to above, this vector processor also uses a merge-sort method which is based on a merging of data elements to be sorted and which is executed in a pipeline manner. A known method adapted to the scalar processor consists of utilizing the properties that exist in the data elements to increase the efficiency (e.g., see Knuth, E.E.: "The Art of Computer Programming Vol. 3, Sorting and Searching", Addison-Wesley (1973)). By merging the ascending order data elements having varying lengths or the descending data elements having varying lengths in the input data elements, it is made possible to perform the sorting with a reduced number of mergings compared with the merging by the conventional scalar processor. The above-mentioned literature, however, does not disclose how the above method can be adapted to the vector processor. SUMMARY OF THE INVENTION The object of the present invention is to provide a vector processor which is suited for processing vectors that consist of ascending order or descending order elements having varying lengths at high speeds. This object is met by the vector processor defined in claim 1 and the method defined in claim 9. According to the present invention, vector elements are compared with vector elements that precede the vector elements in synchronism with the supply of the vector elements to the arithmetic unit, and the operation to be effected for the individual vector elements is selected depending upon the compared results. Concretely speaking according to the present invention, a break is detected between the elements arranged in ascending order and the elements arranged in descending order that are read subsequently in parallel with the execution of the merging for the vector element read in the previous time, and the merging for the vector elements subsequently read is effected for either the ascending order elements or the descending order elements depending upon the detected result. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram illustrating the whole structure of a vector processor according to an embodiment of the present invention; Fig. 2 is a diagram illustrating an instruction format; Fig. 3 is a time chart which illustrates the operation; Fig. 4 is a diagram illustrating the structure of a timing control circuit; Fig. 5 is a diagram illustrating the structure of an operand control circuit; Fig. 6 is a diagram illustrating the structure of a mode control circuit; Fig. 7 is a diagram illustrating the structure of an address control circuit; Fig. 8 is a diagram illustrating the structure of an operation circuit; Fig. 9 is a truth table which illustrates the operation of a next operation control logic; Fig. 10 is a diagram illustrating a method of merge sorting using a conventional vector processor; and Fig. 11 is a diagram which schematically illustrates the merging according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Prior to describing the invention in detail, the merging according to the embodiment will be described briefly with reference to Fig. 11. An input vector consisting of vector elements 2, 5, 7, 4, 1, 6, 8 and 3 is processed starting from both ends thereof. First, the neighboring consecutive vector elements are compared with regard to their magnitudes in order to examine whether the data are arranged in ascending order or in descending order. For instance, 2 < 5 holds true from the upper end and 3 < 8 holds true from the lower end, indicating that the vector elements are arranged in ascending order. The operation mode includes an ascending merge mode and descending merge mode, and values "0" and "1" are set to the operation mode register to correspond thereto. If now an initial value "0" is set to the operation mode register, the operation is started with the ascending merge mode. In the ascending merge mode, the elements are produced in the order of increasing magnitude. Therefore, the element "2" is produced, first. The next consecutive two elements from the upper end are compared to be 5 < 7; i.e., the ascending order is still maintained. Therefore, the operation mode does not change, and "3" is produced. The next consecutive two elements from the lower end are compared to be 8 > 6; i.e., the ascending order is changed to the descending order. Here, since there is no ascending order element from the lower end, the ascending order element "5" from the upper end is produced. As a result, the consecutive two elements from the upper end are compared to be 7 > 4; i.e., the ascending order is changed into the descending order. Between "7" and "8", therefore, the larger one is produced, i.e., "8" is produced. Here, since the first ascending order element no more exists, the operation mode register is renewed to "1", and the descending order vector elements are merged. In the descending order merging mode, the elements are produced in the decreasing order. Therefore, "8" is produced first. Like the case of the ascending order vector elements, the descending order vector elements are merged. Similarly, when there exists neither ascending order vector element nor descending order vector element, the mode is renewed and elements of the next subsequence are merged. This makes it possible to detect the break among the subsequences of elements in parallel with the merging operation. It is further allowed to carry out the ascending mode merging and the descending mode merging without re-starting the instruction in response to the ascending order and descending order vector elements, making it possible to carry out pipeline processing maintaining good efficiency. The present invention can be adapted not only to such merge processing but also to any other processing. An embodiment of the present invention will now be described in detail in conjunction with the drawings. First, the structure and operation of the vecotr processor according to an embodiment of the present invention will be briefly described with reference to Fig. 1. A vector merging instruction stored in a main storage 111 is read onto an instruction word register 101 through a data path 129. In response to this instruction, a timing control circuit 105 produces a variety of control signals. In parallel with this, data required for executing the instruction are sent from a group of general-purpose registers 103 to an operand control circuit 106, address control circuits 109a to 109c and to a mode control circuit 107, and are set up thereto to initialize these circuits. After initialized, the timing control circuit 105 repetitively sends to the main storage 111 the fetch request FREQ of elements of a first vector (hereinafter referred to as vector X) and a second vector (hereinafter referred to as vector Y) that are to be operated as well as the storage request SREQ of elements of a vector (hereinafter referred to as vector Z) obtained as a result of operation. An X-address control circuit 109X and a Y-address control circuit 109Y successively generate addresses of requests that are to be read by the vectors X and Y. A Z-address control circuit 109Z successively generates write addresses of requests of the vector Z. The main storage 111 which has received the fetch request FREQ reads vector elements of vectors X and Y according to fetch addresses XADR and YADR sent from the address control circuits 109X and 109Y via a data path 124. The element XDATA of the vector X and the element YDATA of the vector Y that are read out, are sent to a merging operation circuit 110Z. The merging operation circuit 110Z consists of a comparator 806 that compares the data XDATA with the data YDATA, and a selector 800. The selector 800 selects the data XDATA or the data YDATA (whichever the smaller). The data that is selected is written onto the main storage as an element of the vector Z as a result of operation. The writing address for this purpose is generated by the aforementioned Z-address control circuit 109Z. Thus, the merging operation is completed for the pair of data. A vector element that follows a vector element (e.g., XDATA) selected by the above selector 800 is read by a corresponding address control circuit, e.g., by the X-address control circuit 109X, supplied to the merging operation circuit 110Z, and is subjected to the merging operation again together with the data (e.g., YDATA) that was not selected in the previous time. The same operation is repeated hereinafter. As the operand control circuit 106 detects the termination, a control signal END0 that indicates this fact is sent to a timing control circuit 105, whereby the fetch request FREQ and the store request SREQ are no more sent, and the instruction is terminated. Thereafter, the next instruction is taken out from the main storage 111 and is set to the instruction word register 101 to continue the processing. The operation mentioned above is the same as the merging operation using the conventional vector processor. The feature of this embodiment is as described below. Namely, the feature of this embodiment resides in the provision of an X ascending order judging circuit 110X, a Y ascending order judging circuit 110Y, a mode control circuit 107, and a next operation control logic 108 which operates in response to the outputs of these circuits and the output of the comparator 806. The X ascending order judging circuit 110X compares the vector element XDATA with the element of the previous vector X, and judges whether the vector element XDATA is in the ascending order. The Y ascending order judging circuit 110Y performs the same operation for the element YDATA of the vector Y. The mode control circuit 107 stores a mode signal MODE which designates which one of ascending order merging (i.e., operation for selecting the smaller data between the two input data) or the descending order merging (i.e., operation for selecting the larger data between the two input data) be performed by the merging operation circuit 110Z. That is, the element XDATA of the vector X read from the main storage 111 is sent to the X ascending order judging circuit 110X and is compared with the element of the previously read vector X, and where it is judged whether the data XDATA is in ascending order relative to the previous data. A signal CMP1 represents the result of judgement. Similar judgement is rendered by the Y ascending order judging circuit 110Y for the element YDATA of the vector Y, and a signal CMP3 is produced to represent the result of judgement. In response to the signals CMP1, CMP2 and a mode signal stored in the mode control circuit 107, the next operation control logic 108 determines whether the ascending order merging operation mode or the descending order merging operation mode be effected for the data XDATA, YDATA supplied to the merging operation circuit 110Z, and sends a signal UPMC to the mode control circuit 107 when the mode is to be changed. Depending upon the output CMP2 of the comparator 806 for the data XDATA, YDATA and the operation mode determined above, the selector 800 is so controlled as to select either one of these data. Furthermore, the X ascending order control circuit 110X and the Y ascending order control circuit 110Y are controlled by the address control circuits 109X, 109Y and 109Z. The signals UP1, UP2 and UP3 work to carry out these control operations. Thus, it is made possible to dynamically change the kind of operations depending upon the result of operation while one vector is being processed. In the case of merge sorting, for example, the operation is carried out in such a manner that the merge outputs are produced in an increasing order (ascending order merging) for the vectors of ascending order subsequence and that the merge outputs are produced in a decreasing order (descending order merging) for the vectors of descending order subsequence while looking for the vectors of ascending order subsequence or descending order subsequence among the vectors. Therefore, the vector operation is carried out efficiently accompanied by neither the divide overhead into subsequence vectors nor the start up overhead for vector instruction. Prior to describing the vector processor of Fig. 1 in detail, the instruction format of vector instruction according to the embodiment will now be described with reference to Fig. 2, wherein a vector instruction consists of 32 bits. The upper 16 bits 201 of the instruction represent the kind of vector instruction. An R1 field 202 represents a binary integer consisting of 4 bits, and designated a general-purpose register 204 that has a number indiated by the R1 field as well as the registers 205, 206, 207, 208 and 209 that follows 205 among a group of 16 general-purpose registers 103. Similarly, an R2 field designates a general-purpose register 210 having a number indicated by the R2 field as well as the registers 211, 212 and 213 that follows 210. The general-purpose registers 204, 206 and 208 hold start addresses of the vector X, vector Y and vector Z. The general-purpose registers 205, 207, and 209 hold the total number of elements of the vectors X, Y and Z. The general-purpose registers 210, 211 and 212 hold processed vector elements of the vectors X, Y and Z. The general-purpose register 213 constitutes one of the features of the present invention, and holds the operation mode. The vector operation that performs the processing of Fig. 11 will hereinafter be referred to as multi-mode merging operation. As shown in Fig. 1, the vector X consists of data elements in the form of vectors that are to be sorted, and the vector Y consists of those of the vector X but which are arranged in a reverse order. Concretely speaking, the address of a start of the vector Y is set to be equal to the address of a final element of the vector X, the address of the final element is successively reduced as will be described later, the address of an element of the vector X to be read is generated as an element of the vector Y, the main storage 111 is accessed relying upon the address that is generated, and the elements of the vector X are read out in reverse order as the vector Y. Therefore, there is no need of forming the vector Y from the vector X in advance to store it in the main storage 111. For the purpose of easy comprehension in Fig. 1, the vector Y is described separately from the vector X. The invention, however, can be adapted quite in the same manner even when the vector Y is quite another thing from the vector X. In this embodiment, it is presumed that the number of vector elements is all "8" in the general-purpose registers 205, 207, 209. Further, "O" may be set as an initial value for the number of the processed elements in the general-purpose registers 210, 211 and 212. Zero is also set as an initial value for the operation mode 213. Next, operation of the vector processor will be described in detail with reference to Fig. 11. Concretely speaking, the flow of time chart of Fig. 3 that shows the progress of processing will also be referred to while taking the structures of the related logic circuits (Figs. 4 to 9) into consideration. Fig. 3 is a time chart that illustrates the operation of the vector processor of Fig. 1. As shown in Fig. 3, the vector processor employs clock signals of two phases CK₀ and CK₁ for maintaining synchronism. Fig. 4 is a diagram which illustrates the sturcture of the timing control circuit 105, wherein FF denotes a flip-flop. When it is determined as a result of decoding by a decoder circuit 102 that the vector instruction of the form shown in Fig. 2 sent from the instruction register 101 via a data path 112, is a multi-mode merging instruction, the timing control circuit 105 sends control signals iNiTO to iNiT3 (117a to 117a) that initialize the circuits. At the same time, a hold-type flip-flop 401 is set to indicate that the multi-mode merging instruction is being processed. Fig. 5 illustrates the structure of the operand control circuit 106, wherein reference numerals 501 to 503 denote operand counters for counting the numbers of the processed elements in the vectors X, Y and Z. The counter 501 consists of an operand count register 501A, a +1 adder 501B for renewing the value of the operand count register 510A, and a selector 501C. Other counters 502 and 503 are also constructed in the same manner. Being designated by an iNiTO signal 117a, the value of the general-purpose registers 210, 211 and 212, i.e., the initial value "O", is set to the operand count registers 501A, 502A and 503A in the operand control circuit 106 via selectors 501C, 502C and 503C. Being designated by the iNiTO signal, furthermore, the value of the general-purpose registers 205, 207 and 209, i.e., "8" is set to the total element number registers 504A, 502A and 506A. Thus, the operand control circuit 106 is initialized. The comparator 504B compares the number of the processed vector elements in the register 501A with the number of the vector elements in the register 504A. Other comparators 505B and 506B also operate in the same manner. When a coincidence signal is detected from any one of these comparators, the termination signals END0 and END1 are produced. Fig. 6 is a diagram illustrating the structure of the mode control circuit 107. Being designated by an iNiT2 signal 117C, the initial value GRDATA (0 in this case) of operation mode stored in the general-purpose register 213 is initially set to the operation mode count register 601 via selector 601B. Initialization of the mode control circuit 107 is thus completed. Reference numeral 601A denotes an adder that adds +1 to the content of the register 601. The counter is constituted by the adder 601A and the register 601. Fig. 7 is a diagram illustrating the structure of the address control circuits 109X, 109Y and 109Z. The X address control circuit 109X consists of an address register 701A which holds the addresses of X vector elements, a +4 adder 701B for renewing the value thereof by +4, and a selector 701C. The Y address control circuit 109Y consists of an address register 702A for holding the addresses of Y vector elements, a -4 adder 702B for renewing the value thereof by -4, and a selector 702C. The Z address control circuit 109Z is constituted in the same manner as the X address control circuit 109X. Being designated by an iNiT1 signal 117b, the start addresses (a1, a2, a3) of the vectors X, Y and Z stored in the general-purpose registers 204, 206 and 208 are set to the address registers 701A, 702A and 703A. Initialization of the address control circuits 109X, 109Y and 109Z is thus completed. Subsequent to one clock of DEC signal 113, a fetch request signal FREQ is sent from the timing control circuit 105 (Fig. 4) to the main storage 111. Thereafter, the signal FREQ is produced after every other clock until the operation is terminated. Upon receipt of the first fetch request signal (1 ○ of Fig. 3), the main storage 111 reads the vector elements XDATA and YDATA using the X vector element address XADR and Y vector element address YADR sent from the address registers 701A and 702A via data paths 124a and 124b as fetch addresses, and send them to the X ascending order judging circuit 110X, Y ascending order judging circuit 110Y and the operation circuit 110Z. Fig. 8 illustrates the structure of the X ascending order judging circuit 110X, Y ascending order judging circuit 110Y and operation circuit 110Z. The X ascending order judging circuit 110X consists of a work register 801 (hereinafter referred to as WXN register) for holding the vector element XDATA, a register 803 (hereinafter referred to as WXC register) for holding the vector element that was read earlier than the above vector element, and a comparator 805 that compare the values of these registers. The Y ascending order juding circuit 110b is also constructed in the same manner. The operation circuit 110C consists of a comparator 806 that compares the X vector elements and the Y vector elements in the registers 803 and 804, and a selector 800 that selects one of these comparators. In Fig. 8, symbol FF denotes a flip-flop. The start elements "2"and "3" of the vectors X and Y read from the main storage 111 are set by an iNiT3 signal 117d to the WXN register 801 and the WYN register 802, respectively. Upon receipt of a 2-clock delay signal of iNiT1 signal 117b, the address registers 701 and 702 in the address control circuits 109a and 109b (Fig. 7) gain values +4 and -4, respectively to assume addresses for the next elements. The vector elements "5"and "8" designated by these addresses are read according to the fetch request (2 ○ in Fig. 3) of the second time, and are sent to the X ascending order judging circuit 110X, Y ascending order judging circuit 110Y and operation circuit 110Z (Fig. 8). The vector elements "5" and "8" that are sent are set by a 3-clock delay signal of iNiT3 signal to the XWN register 801 and WYN register 802. At the same time, the data "2" and "3" stored in the WXN register 801 and WYN register 802 are transferred to the WXC register 803 and WYC register 804, respectively. The comparators 805, 806 and 807 compare contents of the WXN register 801 and the WXC register 803, contents of the WXC register 803 and the WYC register 806, and contents of the WYN register 802 and the WYC register 804, respectively, and the compared results COMP1, COMP2 and COMP3 are sent to the next operation control logic 108 via signal lines 126a, 126b and 127c. Fig. 9 is a truth table which illustrates the operation of the next operation control logic 108. Depending upon the value of a signal MODE (122) that represents a value of the operation mode register 601, the next operation control logic 108 can be divided into entry numbers 1 to 6 (108a) and entry numbers 7 to 13 (108b). That is, 108a represents the case of the ascending order merging mode (MODE = 0) and 108b represents the case of the descending order merging mode (MODE = 1). Here, the signal COMP1 represents 2 ≦ 5, the signal COMP2 represents 2 ≦ 3, and the signal COMP3 represents 3 ≦ 8. In the operand control circuit 106 (Fig. 5), furthermore, the numbers OC1, OC2 and OC3 of the processed elements are all "0" in the operand counter registers 501A, 502A and 503A, and the values are all "8" in the element number register 504B, 505B and 506B. Therefore, the signal END0 or END1 is "0". Furthermore, since the value of the operation mode register 601 is "0", the signal MODE (122) consisting of the least significant bit also assumes "0". Therefore, the operation (ascending order merging) of entry number 1 is selected in the truth table of Fig. 9, and the output signals UP1 (120a), UP2 (120b), UP3 (120c) and UPMC (123) are produced having values "1", "0", "1" and "0", respectively. These output signals are sent to the operand control circuit 106, mode control circuit 107 and address control circuit 109, and the registers are renewed. When the operation of the entry number 1 is designated in Fig. 9, the signal UP1 (120a) and the signal UP3 (120c) assume the level "1" and whereby the vector element counter registers 501A and 502A (Fig. 5) of the vectors X and Z are counted up by +1. Further, the address registers 701A and 703A (Fig. 7) are renewed (+4) to designate the next vector elements. On the other hand, the signal UP2 (117b) assumes the level "0", and the vector element counter register 502A of the vector Y and the address register 702A (Fig. 7) are not renewed. Similarly, since the signal UPMC (123) remains at the level "0", the operation mode register 601 (Fig. 6) is not renewed, either. This means the following fact. That is, as described above with reference to Fig. 9, the signal MODE (122) assumes the level "0", i.e., the ascending order vector merging is effected from the entry number 1 through up to the entry number 6 (108a), and the signal MODE assumes the level "1", i.e., the descending order vector merging is effected from the entry number 7 through up to the entry number 13 (108b). On the other hand, the initial value of the operation mode register 601 is "0" which designates the ascending order mode. Here, it is obvious from the results of COMP1 (126a) and COMP3 (126c) that the data are arranged in the ascending order, and there is no need of changing the mode. The fetch request of the third time (3 ○ in Fig. 3) is generated according to the renewed addresses. That is, the X operand address XADR is "a1 + 8" and the Y operand address YADR is "a2 - 4" . Therefore, the data "7" and "8" are read from the main storage 111. That is, as for the vector Y, the same vector elements as those for the fetch request of the second time are read out. The data "7" and "8" that are read out are sent to the X ascending order judging circuit 110X, Y ascending order judging circuit 110Y and operation circuit 110Z. The vector element "7" of the vector X is set to the WXN register 801 (Fig. 8) since UP1 = 1. However, since UP2 = 0, the vector element "8" of the vector Y is not set to the WYN register 802 (Fig. 8), and the content of this register is not renewed. Similarly, the initial value "5" of the WXN register 801 is set to the WXC register 803, but the content of the WYN register 804 is not renewed. Here, since UP1 = 1, the initial value "2" of the WXC register 803 is set to the WX register 808 that stores the data. After a clock of the fetch request signal FREQ (3 ○ of Fig. 3) of the third time, a first store request signal SREQ (131b) is sent from the timing control circuit 105 to the main storage 111. The store request is effected using the content ZADR of the address register 703A of the Z address control circuit 109C (Fig. 7) as the store address and the content of the WZ register 808 (Fig. 8) as the store data STDATA (134). Therefore, "2" is stored in the address "a3" as the first element of the vector Z. A next operation result is produced from the next operation control logic 108 in parallel with the storing operation, i.e., after one clock of the fetch request (3 ○ of Fig. 3) of the third time. This time, the signal CMP1 (126a) represents 5 ≦ 7, CMP2 (126b) represents 5 > 3, CMP3 (126c) represents 3 ≦ 8, END0 and END1 represent 0, and MODE (122) represents 0. Therefore, the operation of the entry number 2 is selected, i.e., the operation of the case where the side of the vector Y is small is selected in the ascending order mode merging, so that UPI (120a) assumes 0, UP2 (120b) assumes 1, UP3 (120c) assumes 1, and UPMC (123) assumes 0. Accordingly, the address register 701A and the operand count register 501A are not renewed, 4 is subtracted from the address register 702A so that it assumes a2 - 8, and 1 is added to the operand count register 502A so that it assumes 1. Moreover, 1 is added to the operand count register 503A so that it assumes 2. A fetch data "6" corresponding to the fetch request (4 ○ of Fig. 3) of the fourth time is set to the WYN register 802, "8" is input to the register 804, and "3" is set to the WZ register 134 and is stored as the second element of the vector Z. Contents of the WXN register 801 and WXC register 803 are not renewed. The operation hereinafter is continued in the same manner. In the operation for the fetch data that corresponds to the fetch request (4 ○ of Fig. 3) of the fourth time, CMP1 (126a) represents 5 ≦ 7, CMP2 (126b) represents 5 ≦ 8, and CMP3 (126c) represents 8 > 6. From the results of CMP1 and CMP3, it is obvious that the elements in the vector X are still arranged in the ascending order but there no longer exist ascending order element in the vector Y. The operation of the entry number 3 (ascending order mode) is selected in Fig. 9, the operand count registers 501A, 503A of the side of the vectors X and Y are renewed, address registers 701A and 703A are renewed, and WXN register 801, WXC register 803 and WZ register 808 are renewed, and the data "5" of the side of the vector X is stored as a next element of the vector Z. In response to the fetch request (5 ○ in Fig. 3) of the fifth time, "4" is set to the WXN register 801 and "7" is set to the WXC register 803. As a result of operation, CMP1 represents 7 > 4, CMP2 represents 7 ≦ 8, and CMP3 represents 8 > 6, from which it is learned that there no longer exists any ascending order element in the vector X. This time, therefore, the operation is switched to the descending order element merging. Concretely speaking, the operation of the entry number 5 is selected in Fig. 9, and the operand count registers 501A and 503A for the vectors X and Y, address registers 701A, 703A, and work registers 801 and 803 are renewed, and the data "7" on the side of the vector X is stored as an element of the vector Z. Since the ascending order vector merging has been finished as mentioned earlier, the signal UPMC (123) is rendered to assume "1" and the operation mode register 601 is renewed (+1) in order to change the operation to the descending order vector merging. Therefore, the signal MODE (122) assumes 1. In response to the fetch request (6 ○ in Fig. 3) of the sixth time, "1" is set to the WXN register 801 and "4" is set to the WXC register 803. As a result of operation, CMP1 represents 4 ≧ 1, CMP2 represents 4 ≦ 8, CMP3 represents 8 ≧ 6, and MODE is 1. Therefore, the merging is effected for the descending order vector elements. Concretely speaking, the operation (descending order mode) of the entry number 7 is selected in Fig. 9, and whereby the operand count registers 502A, 503A for the vectors Y and Z, address registers 702A, 703A, and WYN register 802, WYC register 804 and WZ register 808 are renewed, respectively. Here "8" is stored in the main storage 111 (the larger one is produced since the descending order merging is being carried out). The mode remains unchanged since both the vectors X and Y are in the descending order. In response to the fetch request (7 ○ in Fig. 3) of the seventh time, "1" is set to the WYN register 802 and "6" is set to the WYC register 804. As a result of operation, CMP1 represents 4 ≧ 1, CMP2 represents 4 ≦ 6, and CMP3 represents 6 ≧ 1. Like the previous time, therefore, the operation (descending order mode) of the entry number 7 is selected in Fig. 9, and whereby the operand counter registers 502A, 503A for the vectors Y and Z, as well as address registers 702A, 703A, WYN register 802, WYC register 804 and WZ register 808 are renewed, respectively. The data "6" of the side of the vector Y is stored as a next element of the vector Z. In response to the fetch request (8 ○ in Fig. 3) of the eighth time, "4" is set to the WYN register 802 and "1" is set to the WYC register 804. As a result of operation, CMP1 represents 4 ≧ 1, CMP2 represents 4 > 1, and CMP3 represents 1 < 4, from which it is learned that the descending order vector element still exists on the side of the vector X but no descending order vector element exists on the side of the vector Y. Here, the operation (descending order mode) of the entry number 9 is selected in Fig. 9, and whereby the operand count registers 501A, 503A for the vectors X and Z, as well as address registers 701A, 703A, WXN register 801, WXC register 803 and WZ register 808 are renewed, respectively, and the data "4" on the side of the vector X is stored as an element of the vector Z. In response to the fetch request (9 ○ in Fig. 3) of the ninth time, "6" is set to the WXN register 801 and "1" is set to the WXC register 803. As a result of operation, CMP1 represents 1 < 6, CMP2 represents 1 ≦ 1, and CMP3 represents 1 < 4. This time, however, since the element number register 503A of vector Z has "7", the END0 and END1 signals (116, 121) assume "1", and the operation of the entry number 13 is selected in Fig. 9. Accordingly, the operand count register 503A of the side of the vector Z, the address register 703A, and the WZR register 808 are renewed, and the data of the side of the vector Y is stored as an element of Z. The END0 signal (116) is sent to the timing control circuit 105, a flip-flop 401 is reset to indicate that the multi-mode merging instruction is being executed, the fetch request signal FREQ (131a) is no more produced, and after 3 clocks, the store request signal SREQ (131b) is no more produced. Moreover, values 4, 3 and 7 of the final status of the operand count registers 501A, 502A and 503A, as well as a value 1 of the final status of the operation mode register 601 are written back onto the corresponding general-purpose registers 210, 211, 212, and 213 via data paths 132a, 132b, 132c and 133, and whereby the processing of the multi-mode merging instruction is completed. In describing the operation of this embodiment, the initial value of the mode register 601 was started with "0" which is an even number. This means that the operation is started looking for the ascending order vector elements first. The data are stored in ascending order even in the vector Z. If the initial value of the mode register 601 is started with an odd number such as "1", then the data are stored in descending order in the vector Z. Accordingly, the sorted results are obtained in ascending order if the multi-mode merging is repeated with the initial value of the mode register being set to an even number at all times, and the sorted results are obtained in descending order if the initial value is started with an odd number at all times. The present invention can further be applied to the below-mentioned case. Namely, in the aforementioned embodiment, the ascending order vector elements and the descending order vector elements in the vectors were detected, and the consecutive two elements were compared. The detection can be effected even by using a mask vector. That is, a mask vector M1 is prepared in which M1(i) = 1 corresponds to the ascending order vector elements X(i) in the vector X and M1 (j) = 0 corresponds to the descending order vector elements X(j). A mask vector M2 is prepared in the same manner even for the vector Y. Then, the merging operation unit is prepared based upon the two mask vectors such that the elements X(k) and Y(ℓ) of the vectors X and Y are merged in the descending order when M1(k) = 0 and M2(ℓ) = 0, and are merged in the ascending order when M1(k) = 1 and M2(ℓ) = 1. According to the present invention as described above, when the vector operand that is input consists of a plurality of partial vectors having various properties, the elements for each of the partial vectors are operated, breaking portions among the partial vectors are detected, and the kind of operation is changed depending upon the properties of the partial vectors, all of these operations being carried out in parallel with each other making it possible to perform the processing at high speeds. In the case of the multi-mode merging instruction, for instance, the ascending order and descending order vector elements that spontaneously exist in the input vector operand are detected and, at the same time, the merging operation is carried out in a different mode depending upon the ascending order vector elements and the descending order vector elements. Therefore, the number of times of the merging operation can be decreased compared with when there are not utilized the ascending order and descending order vector elements in the input vector operand. In practice, the data to be sorted are often biased such as being almost all sorted. In particular, the greatest effects are obtained when the inputs have been sorted in advance, and the multi-mode merging instruction needs be operated one time using the vector processor of the present invention. Using the conventional vector processor, however, the merging must be effected log₂ N number of times (when the number of the elements is N). Further, the number of vector elements in each merging can be selected to be N. Moreover, since there is no decomposition into partial vectors nor overhead for starting up the vector instruction, the time required for one time of merging is the same as that of the conventional art. Therefore, the operation speed of the vector processor of the present invention is increased by log₂ N times for the inputs that have been sorted in advance. When the ascending order and descending order vector elements that spontaneously exist in the input vectors are to be utilized, it is necessary to know whether the sorting is completed or not after the multi-mode merging instruction has been executed. According to the method of Fig. 10 which does not utilize the partial vectors, the sorting is necessarily completed after log₂ N times of merging. According to the method of Fig. 11, however, the sorting may have already been completed after the merging of one time. According to the present invention which counts the number of reversals of the mode, therefore, the value of the mode counter is examined after the multi-mode merging instruction is executed. When the value is the same as before the multi-mode merging instruction is executed, it means that the whole inputs are arranged in ascending order or in descending order. Therefore, there is no need of effecting. the scanning to examine whether the sorting has been completed or not after the execution, and the operation can be carried out efficiently.

Claims: A vector processor comprising a data storage means (111), means (109X, 109Y) for reading from said data storage means (111) the vector elements of two vectors to be merged, and operation means (110Z) for performing a merging operation on any two vector elements supplied by said reading means (109X, 109Y) characterised by means (110X, 110Y) for detecting whether each of said two vectors pertains to a sequence in which the vector elements are arranged in ascending order or to a sequence in which the vector elements are arranged in descending order, and determining means (107, 108) for causing said operation means (110Z) to effect either an ascending order merging operation or a descending order merging operation on the two vector elements, depending upon the results of detection by said detecting means (110X, 110Y). The vector processor of claim 1, wherein said detecting means (110X, 110Y) is operable to detect a subsequent vector element in parallel with the execution of the operation on the preceding vector element by said operation means (110Z). The vector processor of claim 1, including means for changing the ascending order merging operation to the descending order merging operation when the two vector elements to be merged by said operation means (110Z) are both start elements in a sequence of vector elements arranged in ascending order, and for changing the descending order merging operation to the ascending order merging operation when the two vector elements to be merged by said operation means (110Z) are both start elements in a sequence of vector elements arranged in descending order. The vector processor of claim 1, wherein said reading means (109X, 109Y) reads vector elements of a vector to be sorted in first and second different orders and supplies the vector element sequence read in said first order and the vector element sequence read in said second order to said operation means (110Z) as two vector elements to be merged. The vector processor of claim 1, wherein said reading means includes first supply means (109X) for successively reading vector elements of a first group from said data storage means (111) and successively supplying them to said operation means (110Z), and second supply means (109Y) for successively reading vector elements of a second group from said data storage means (111) and successively supplying them to said operation means (110Z), wherein said detecting means includes first comparator means (110X) for comparing a first group vector element being read with the preceding vector element of said first group, and second comparator means (110Y) for comparing a second group vector element being read with the preceding vector element of said second group, and wherein said determining means (107, 108) determines the operation to be effected on the first group vector element being read or on the second group vector element being read in response to the outputs of said first and second comparator means (110X, 110Y). The vector processor of claim 5, wherein said operation means (110Z) includes a comparator (806) for comparing a vector element of said first group supplied by said first supply means (109X) with a vector element of said second group supplied by said second supply means (109Y), and select means (800) for selecting a first operation to operate the larger one of the vector elements of said first and second groups, or a second operation to operate the smaller one of the vector elements of the first and second groups, said determining means (107, 108) causing said select means (800) to effect either said first or said second operation, depending upon the outputs of said first and second comparator means (110X, 110Y). The vector processor of claim 6, wherein said determining means (107, 108) includes means for causing said select means (800) to select a vector element from said first or second group in response to said determined operation and the output of said comparator (806), and means for instructing said first and second supply means (109X, 109Y) such that a vector element next to the one selected by said selection and a vector element not selected by said selection are supplied to said operation means (110Z) as the pair of vector elements to be operated next. The vector processor of claim 7, wherein said first supply means (109X) successively reads out vector elements to be sorted, starting from the first element, and said second supply means (109Y) successively reads out vector elements to be sorted, starting from the last element. A method of merging vector elements of two vectors, comprising the steps of (a) detecting whether the two vectors pertain to a vector element sequence in which the vector elements are arranged in ascending order or to a vector element sequence in which the vector elements are arraged in descending order, (b) determining whether the two vector elements to be merged are to be subjected to ascending or descending order merging, based upon the result of said detecting step (a) and (c) effecting the thus determined merging operation for the said two vector elements, wherein all steps (a) to (c) are effected by a vector processor. The method of claim 9, wherein said detection is effected in parallel with the merging operation for the respective preceding vector elements in said two vectors. The method of claim 9, wherein said step (b) includes detecting whether the result of the step (a) for the two vector elements to be merged next is different from that for the two vector elements merged previously, and performing said step (b) based upon a change in said detection. The method of claim 11, wherein said step (b) includes changing the ascending order merging operation to the descending order merging operation when the two vector elements to be operated next are both start elements in a sequence of vector elements arranged in ascending order, and changing the descending order merging operation to the ascending order merging operation when the two vector elements to be operated next are both start elements in a sequence of vector elements arranged in descending order.

Inventors: KOJIMA, KEIJI
Applicants: HITACHI, LTD.
Application year: 1988
Main classification: G06F7
IPC codes: G06F7, G06F17