Bipolar-complementary metal oxide semiconductor circuit

Abstract: A bipolar-complementary metal oxide semiconductor circuit includes a p-channel MOS transistor (M1), an n-channel MOS transistor (M2), first and second bipolar transistors (Q1, Q2). A base of the first bipolar transistor (Q1) is connected to a negative power source (V EE ) through the n-channel MOS transistor (M2). A diode (D1) is connected to the base and emitter of the first bipolar transistor (Q1). The diode (D1) functions to prevent a reverse-biased voltage exceeding a base-emitter breakdown voltage (V out - V B ) from being applied between the base and emitter of the first bipolar transistor (Q1).

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a bipolar-complementary metal oxide semiconductor circuit, and more particularly to an improvement of a circuit structure of a bipolar-complementary metal oxide semiconductor circuit. Recently, there has been considerable activity in the development of a bipolar-complementary metal oxide semiconductor circuit (hereinafter simply referred to as a Bi-CMOS circuit). It is well known that CMOS circuits have advantages of high integration density and low power consumption. On the other hand, bipolar transistor circuits have advantages of high driving capability and high mutual conductance. Bi-CMOS circuits have the advantages of both the CMOS circuit and bipolar transistor circuit. A Bi-CMOS circuit includes a logic circuit portion composed of CMOS transistors and a load driving circuit portion composed of two bipolar transistors. A first bipolar transistor of the load driving portion is used for charging up a capacitive load connected thereto. A second bipolar transistor of the load driving portion is used for discharging the capacitive load. Currently, two types of Bi-CMOS circuits are known. In a type of Bi-CMOS circuit, when the first bipolar transistor is turned OFF, a base thereof becomes connected to a negative power source through a current path for supplying the second bipolar transistor with a base current produced by a charge stored in the capacitive load connected to the Bi-CMOS circuit. In the other type of Bi-CMOS circuit, when the first bipolar transistor is turned OFF, the base thereof becomes connected to the negative power source through an n-channel MOS transistor which is a part of a complementary MOS inverter in the logic circuit. However, the conventional Bi-CMOS circuit of the first has type a disadvantage described below. When the first bipolar transistor is turned OFF, a reverse-biased voltage is applied between the emitter and base thereof. This is because the base voltage of the first bipolar transistor decreases fast to a negative power source voltage, compared with a decrease of the emitter voltage of the first bipolar transistor. When the reverse-biased voltage exceeds a base-emitter breakdown voltage of the first bipolar transistor, it may be damaged. SUMMARY OF THE INVENTION It is therefore a general object of the present invention to provide a novel and useful Bi-CMOS circuit in which the aforementioned disadvantage is eliminated. A more specific object of the present invention is to provide a Bi-CMOS circuit having a function of preventing a reverse-biased voltage higher than a base-emitter breakdown voltage from being applied between the base and emitter of a bipolar transistor used for charging up a capacitive load connected thereto. Another object of the present invention is to provide a Bi-CMOS circuit in which the application of the reverse-biased voltage exceeding the base-emitter breakdown voltage can be effectively provided with a slight increase of a pattern area on a semiconductor chip. The above objects of the present invention can be achieved by a Bi-CMOS circuit comprising first and second power sources; a logic circuit comprising first and second metal oxide semiconductor (MOS) transistors serially connected between the first and second power sources, an input signal being applied to gates of the first and second MOS transistors; a first bipolar transistor having a collector coupled to the first power source and a base coupled to a connecting point between the first and second MOS transistors; a second bipolar transistor having an emitter coupled to the second power source and a collector coupled to the emitter of the first bipolar transistor and used as an output terminal of the circuit; a third MOS transistor connected between a base of the second bipolar transistor and the output terminal of the circuit, a gate of the third MOS transistor being supplied with the input signal; and a diode having an anode connected to the emitter of the first bipolar transistor and a cathode connected to the base of the first bipolar transistor. Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a circuit diagram of a conventional Bi-CMOS circuit; FIG.2 shows waveforms of signals in the Bi-CMOS circuit shown in FIG.1; FIG.3 is a circuit diagram of another conventioanl Bi-CMOS circuit; FIG.4 shows waveforms of signals in the Bi-CMOS circuit of FIG.3; FIG.5 is a circuit diagram of a preferred embodiment of the present invention; FIG.6 shows waveforms of signals in the preferred embodiment of FIG.5; FIG.7A is a plan view of a bipolar circuit portion in the circuit of FIG.5; FIG.7B is a cross sectional view taken along a line I-I; FIG.7C is a cross sectional view taken along a line II-II; FIG.8 is a circuit diagram of a diode shown in FIG.5; and FIG.9 is a circuit diagram of another preferred embodiment of the present invention. DETAILED DESCRIPTION To facilitate the understanding of the present invention, a description is given of conventional Bi-CMOS circuits with reference to FIGS.1 through 4. FIG.1 is a conventioanl Bi-CMOS circuit of the first type as disclosed e.g. in EP-A-0 145 004. The illustrated circuit constitutes a NOT gate. An npn-type bipolar transistor Q1 is used for charging up a capacitive load C L to approximately a positive power source voltage V CC (5 volts). An npn-type bipolar transistor Q2 is used for discharging the capacitive load C L . A CMOS inverter is constructed by a p-channel MOS transistor M1 and an n-channel MOS transistor M2. The CMOS inverter controls ON/OFF state of the bipolar transistor Q1. An n-channel MOS transistor M3 is used for controlling ON-OFF state of the bipolar transistor Q2, and also used for passing a current from the capacitive load C L therethrough when an input signal V in applied to an input terminal IN is switched from a low level to a high level. An n-channel MOS transistor M4 is used for discharging a base capacitor of the bipolar transistor Q2. When the input signal Vin is switched from high level to low level, the MOS transistor M1 is turned ON and the bipolar transistor Q1 is turned ON so that an output voltage Vout becomes high level. According to the increase of the output voltage Vout, the MOS transistor M4 is turned ON so as to make the bipolar transistor Q2 turn OFF by discharging the base capacitor of the bipolar transistor Q2. When the input signal V in is switched to high level, the MOS transistors M2 is turned ON. Thereby, the bipolar transistor Q1 is turned OFF. At this time, the MOS transistor M3 is also turned ON. Therefore a current passes from the capacitive load C L to a negative power source V EE (a ground level) through the MOS transistors M3 as a base current of the bipolar transistor Q2. Thereby, the bipolar transistor Q2 is turned ON, and the capacitive load C L is discharged therethrough. As a result, an output voltage V out at an output terminal OUT becomes zero. FIG.2 shows waveforms of the input signal V in , the output signal V out , and the base voltage V B of the transistor Q1. It can be seen from FIG.2(a) that when the input signal V in is switched to the high level, the base voltage V B of the transistor Q1 decreases fast to the negative power source voltage V EE through the MOS transistor M2. On the other hand, the output signal V out decreases slowly, compared with decrease of the base voltage V B . This is because the capacitive load C L is coupled with the output terminal OUT. During the time when the output signal V out decreases, a reverse-biased voltage shown in FIG.2(b) is applied between the base and emitter of the transistor Q1. The reverse-biased voltage corresponds to a difference between the output signal voltage V out and the base voltage V B . As shown, as the base voltage V B decreases, the reverse-biased voltage increases. Normally, a bipolar transistor has a breakdown voltage of approximately 3 to 5 volts. Therefore, the reverse-biased voltage causes breakdown of the transistor Q1 when the reverse-biased voltage exceeds the base-emitter breakdown voltage during the discharge of the capacitive load C L . The present invention intends to overcome the above-mentioned disadvantage. A description is given of a preferred embodiment of the present invention with reference to FIG.5. In FIG.5, those parts which are the same as those in FIG.1 are given the same reference numerals. Referring to FIG.5, an essential feature of the embodiment of the present invention is the presence of a diode D1 connected between the base and emitter of the transistor Q1. A cathode of the diode D1 is connected to the base of the transistor Q1, an anode of the diode D1 is connected to the emitter of the transistor Q1. Other portions of the circuit of FIG.5 are the same as that of the circuit of FIG.1. That is, the input signal V in is applied to gates of the MOS transistors M1, M2 and M3. The source of the MOS transistor M1 is connected to the positive power source V CC , and the drain thereof is connected to the drain of the MOS transistor M2 and the base of the transistor Q1. The source of the MOS transistor M2 is connected to the negative power source V EE . The collector of the transistor Q1 is connected to the positive power source V CC , and the collector of the transistor Q1 is connected to the emitter of the tansistor Q2, the drain of the MOS transistor M3, and the gate of the MOS transistor M4. The output signal V out appears at the collector of the transistor Q2. The source of the MOS transistor M3 is connected to the base of the transistor Q2 and the drain of the MOS transistor M4. The emitter of the transistor Q2 and the source of the MOS transistor M4 are connected to the negative power source V EE . The MOS transistor M4 is used for discharging the parastic base capacitor of the bipolar transistor Q2. Referring to FIG.6, after the input signal V in starts increasing, the base voltage V B starts decreasing at a time t₁. Then the output signal V out begins decreasing. Thereby the reverse-biased voltage (V out - V B ) begins increasing. The voltage difference between the base and emitter of the bipolar transistor Q1 biases the diode D1 in the forward direction. At a time t₂, the reverse-biased voltage becomes equal to approximately 0.8 volts, which corresponds to a voltage drop of the diode D1 in the forward direction. Therefore, the diode D1 is turned ON. Thereby, the transistor Q1 is clamped at approximately 0.8 volts. in other words, even if the base voltage V B decreases fast, the reverse-biased voltage does not exceed a voltage of 0.8 volts. As a result, the disadvantage of the conventioanl B-CMOS is eliminated. It is particularly noted that the diode D1 functions to clamp the base-emitter voltage of the transistor Q1 at a voltage resulting from the forward voltage drop of the diode D1. The inventors are aware of a conventional Bi-CMOS circuit of the aforementioned second type as shown in FIG.3 (see Japanese Laid-Open Patent Application Nos.62-102621 and 62-169520, for example). The illustrated Bi-CMOS circuit has a diode D2 which is different from the diode D1 shown in FIG.5 in function. A diode D2 is connected between an emitter and a base of an npn-type bipolar transistor Q3. The diode D2 is provided for forming a current path for supplying a base of the bipolar transistor Q4 with a base current from the capacitive load C L . When the input signal V in is switched to the high level, an n-channel MOS transistor M13 is turned ON. Thereby, a current passes from the capacitive load C L to the negative power source V EE through the diode D2, the MOS transistor M13 and an n-channel MOS transistor M14. The current also passes from the capacitive load C L to the base of the bipolar transistor Q4. This current is the base current of the bipolar transistor Q4. It is noted that the output terminal coupled with the capacitive load C L is connected to the base of the bipolar transistor Q3 through the diode D2. Therefore, the base voltage of the bipolar transistor Q3 changes depending on change of the output signal V out . As shown in FIG.4(a), when the input signal V in is switched to the high level, the output signal V out decreases slowly because of the presence of the capacitive load C L . Therefore, the base voltage of the bipolar transistor Q3 also decreases slowly. As a result of the above operation, the reverse-biased voltage (V out - V B ) does not increase greatly. As explained above, the base of the bipolar transistor Q3 is not connected to the negative power source V EE through the independent MOS transistor like M2 in FIG.5. And the MOS transistor M14 has a large impedance. Therefore, in the Bi-CMOS circuit of FIG.3, there is no problem of the large reverse bias voltage against the emitter and the base junction of the bipolar transistor Q3. A description is given of a device structure of the embodiment having the aforementioned circuit configuration with reference to FIGS.7A through 7C. FIG.7A is a plan view of a pattern of a bipolar circuit portion 100 shown in FIG.5 formed on a semiconductor chip. FIG.7B is a cross sectional view taken along a line I-I, and FIG.7C is a cross sectional view taken along a line II-II. The bipolar circuit portion 100 is formed within a substrate region surrounded by an isolation region 10 which is a p-type region of a silicon semiconductor substrate 18. In the region surrounded by the isolation region 10, there are formed the bipolar transistors Q1 and Q2, and the diode D1. A reference numeral 10A indicates a region in which the bipolar transistor Q1 is formed. In the bipolar transistor region 10A, there are formed a collector contract 11, a base contact 12, and an emitter contact 13. A reference numeral 10B indicates a region in which the bipolar transistor Q2 and the diode D1 are formed. An emitter contact 14 and a base contact 15 of the bipolar transistor Q5 are formed in the region 10B. The base of the bipolar transistor Q2 is formed by a p-type diffusion region 20, which is formed in an n-type diffusion region 19 surrounded by the p-type isolation region 10. As shown in FIGS.7B and 7C, an n⁺-type buried layer 29 is formed under the n-type diffusion region 19. The emitter of the bipolar transistor Q2 is formed by an n⁺-type diffusion region 21 formed in the p-type diffusion region 20. An interconnection layer 16 made of a metallic material such as aluminum and an alloy of aluminum and silicon, is in contact with the n⁺-diffusion region 21. Similarly, an interconnection layer 17 is in contact with the p-type diffusion region 20. In the present embodiment, the diode D1 shown in FIG.5 is constructed by an npn bipolar transistor Q5, as shown in FIG.8. A base and a collector of the bipolar transistor Q5, is mutually connected. Turning to FIGS.7A through 7C, a base contact 22 and an emitter contact 23 of the bipolar transistor Q5 are formed in the region 10B. The base of the bipolar transistor Q5 is formed by a p-type diffusion region 27 formed in the n-type diffusion region 19. The emitter of the bipolar transistor Q5 is formed by an n⁺-type diffusion region 28 formed in the p-type diffusion region 27. An interconnection layer 25 is in contact with the n⁺-type diffusion region 28. An interconnection layer 26 is in contact with the p-type diffusion region 27. The interconnection layer 25 is also in contact with the base of the bipolar transistor Q1. A reference numeral 29 indicates a collector contact of the bipolar transistors Q2 and Q5. As shown in FIG.7C, the collectors of the transistors Q2 and Q5 are formed in common by an n⁺-type diffusion region 30 formed in the n-type diffusion region 19. As shown in FIG.7A, the interconnection layer 26 includes the emitter contact of the bipolar transistor Q1, the base contact 22 of the bipolar Q5, and the collector contact 29 of the bipolar transistors Q2 and Q5. As described above, the collector of the bipolar transistor Q5 which functions as the diode D1, is formed in common to the collector of the bipolar transistor Q2. Further, the collector region of the n⁺-type diffusion region 30 is formed in the region surrounded by the isolation region 10. Moreover, the diode D1 may be constituted by a diode having a small current capacity. From these regions, the bipolar transistor Q5 can be formed with an slight increase of the pattern area. Additionally, parastic capacitance is made small. FIG.9. shows a circuit of a two-input NAND gate of another preferred embodiment of the present invention. The NAND gate includes p-channel MOS transistors M5 and M6, and n-channel MOS transistors M7 through M11. Two input signals V in and V in ' are applied to gates of the respective MOS transistors M7 and M8. The output signal V out is outputted from a node at which a drain of the MOS transistor M9 and a gate of the MOS transistor M11, and the anode of the diode D1 are mutually connected. The diode D1 is connected between the emitter and collector of the bipolar transistor Q1. When the input signals V in and V in ' are switched to the low level, the base voltage V B of the bipolar transistor Q1 decreases fast to the negative power source voltage V EE . At this time, the current derived from the charge stored in the capacitive load C L flows to the negative power source V EE through the diode D1, the MOS transistors M7 and M8. Therefore, the base-emitter voltage of the bipolar transistor Q1 is clamped at the anode-cathode forward voltage of the diode D1. The positive power source voltage V CC is a ground level, and the nagative power source voltage is a negative voltage level.

Claims: A bipolar-complementary metal oxide semiconductor circuit comprising first and second power sources (V CC , V EE ); logic means comprising first and second metal oxide semiconductor (MOS) transistors (M1, M2) serially connected between said first and second power sources (V CC , V EE ), an input signal (V in ) being applied to the gates of said first and second MOS transistors (M1, M2); a first bipolar transistor (Q1) having a collector coupled to said first power source (V CC ) and a base coupled to a connecting point between said first and second MOS transistors (M1, M2); a second bipolar transistor (Q2) having an emitter coupled to said second power source (V EE ) and a collector coupled to an emitter of said first bipolar transistor (Q1) and used as an output terminal (OUT) of the circuit; and a third MOS transistor (M3) connected between a base of said second bipolar transistor (Q2) and said output terminal (OUT) of the circuit, a gate of said third MOS transistor (M3) begin supplied with said input signal (V in ), characterized in the circuit comprises a diode (D1) having an anode connected to the emitter of said first bipolar transistor (Q1) and a cathode connected to the base of said first bipolar transistor (Q1). A bipolar-complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that when the input signal (V in ) is switched from a low level to a high level, a current passes from the output terminal (OUT) to the second power source (V EE ) through the diode (D1) and the second MOS transistor (M2). A bipolar-complementary metal oxide semiconductor circuit as claimed in any of claims 1 or 2, characterized in that the diode (D1) is constituted by a bipolar transistor (Q5) in which the anode of the diode (D1) is collector and base of said bipolar transistor (Q5) mutually connected, the cathode of the diode (D1) is an emitter of said bipolar transistor (Q5). A bipolar-complementary metal oxide semiconductor circuit as claimed in claim 3, characterized in that the collector of the bipolar transistor (Q5) of the diode (D1) and the collector of the first bipolar transistor (Q2) are formed in common by an impurity diffusion region (30) formed in a semiconductor substrate (18). A bipolar-complementary metal oxide semiconductor circuit as claimed in any of claims 1 to 4, further comprising a fourth MOS transistor (M4) between the output terminal (OUT) and the negative power source (V EE ).

Inventors: FUKUSHI ISAO, MUROI TAKAHISA, FUKUSHI, ISAO, MUROI, TAKAHISA
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1988
Main classification: H03K17
IPC codes: H03K19, H03K17, H01L29, H01L21, H01L27