Photoelectric converting apparatus

Abstract: There is provided a photoelectric converting apparatus having accumulating device to accumulate a signal from a photoelectric converting device(s). This apparatus comprises a first accumulating portion(C1) to accumulate a readout signal of the photoelectric converting device; and a second accumulating portion(C2) to accumulate the remaining signal after the photo­ electric converting device was refreshed, wherein the signals of the first and second accumulating portions are superposed and output, thereby obtaining an output signal (HL) in which the remaining signal was eliminated from the readout signal.

Description: The present invention relates to a photoelectric converting apparatus having accumulating means for accumulating a signal from a photoelectric converting device and, more particularly, to a photoelectric converting apparatus which intends to eliminate a variation in dark signal and to eliminate unnecessary components such as drive noises and the like. Fig. 1 is a schematic arrangement diagram showing an exmaple of a conventional photoelectric converting apparatus. In the diagram, readout signals from photo sensors S₁ to S n are accumulated into accumulating capacitors C₁ to C n . When transistors Q h1 to Q hn are sequentially turned on in accordance with an operating timing of a scan circuit 101, the readout signals are successively transmitted onto an output line 102 and are output to the outside through an amplifier 103. However, such a conventional apparatus has a problem such that the unnecessary components such as dark signals, drive noises, and the like of the photo sensors are included in the readout signal and the readout signal is output in this state. The drive noises are the noises which are generated when the signals are read out by driving the photo sensors. The drive noises denote the noises which are caused due to a variation in device shape or the like upon manufacturing and the smears or the like which depend on an amount of light irradiation due to a separation of the device or the like. On the other hand, the dark signal denotes the dark current of the photo sensor. A variation in the dark signal largely depends on the accumulating time of the photo sensor and the temperature. Those unnecessary signals such as drive noises, dark signals, and the like cause a problem particularly when an image is picked up under the condition of a low illuminance. In the low-illuminance image pickup mode, the information signal level by the image pickup operation decreases, so that the S/N ratio is eventually reduced and the picture quality is deteriorated. Therefore, in order to improve the picture quality, those unnecessary signals need to be reduced. However, as mentioned above, since the dark signals largely depend on the temperature and accumulating time and the drive noises hardly depend on them, in order to remove these unnecessary signals, it is necessary to separate both of those signals and to independently determine correction coefficients. For this purpose, a number of memories are needed. Consequently, there occur problems of the complication of the signal processes, increase in costs, and enlargement of the image pickup apparatus. EP-A-0232593 discloses a photosensor arrangement in which a dark current signal and a light signal are stored on respective capacitors connected to respective parallel output lines, so that an output circuit receives both signals. In one embodiment the output circuit comprises a differential amplifier having one input connected to the output line for the dark current signal and the other input connected to the output line for the light signal. EP-A-0260954 was published on 23 March 1988, after the first priority dated claimed by the present application and before the second priority date claimed by the present application. EP-A-0260954 discloses a photosensor arrangement in which a light signal and a drive noise signal are stored on respective capacitors and are output in turn to a difference processing circuit. The signals are amplified in the difference processing circuit and the amplified signals are applied to the input side of a capacitor. While the amplified noise signal is applied, the output side of the capacitor is grounded, and then the amplified light signal is applied while the output side of the capacitor floats, so that the capacitor outputs the difference between the amplified signals. According to the present invention there is provided photoelectric converting apparatus as set out in claim 1. The remaining claims set out optional features. Embodiments of the present invention, given by way of non-limiting example, will now be described with reference to the accompanying drawings. Fig. 1 is a schematic arrangement diagram showing an example of a conventional photoelectric converting apparatus; Fig. 2A is a circuit diagram for explaining a fundamental arrangement of the first embodiment of a photoelectric converting apparatus according to the present invention; Fig. 2B is a timing chart for explaining the operation of the circuit shown in Fig. 2A; Figs. 3A and 3B are connecting diagrams of capacitors for explaining the operation of the circuit shown in Fig. 2A; Fig. 4 is a circuit diagram of the embodiment; Fig. 5 is a timing chart for explaining the operation of the embodiment; Fig. 6 is a schematic circuit diagram showing a fundamental arrangement of the second embodiment of a photoelectric converting apparatus according to the invention; Figs. 7 and 8 are timing charts showing the first and second examples of the practical operations of the photoelectric converting apparatuses in the second and third embodiments of the present inventions; Fig. 9 is a schematic circuit diagram showing a fundamental arrangement of the third embodiment of the invention; Fig. 10 is a schematic circuit diagram of another embodiment of a solid-state image pickup apparatus according to the invention; Fig. 11 is a timing chart for explaining the operation of the embodiment shown in Fig. 10; Fig. 12 is a schematic circuit diagram of an example of a scan circuit for use in the invention; Fig. 13 is a timing chart for explaining the operation of the scan circuit shown in Fig. 12; Fig. 14A is a timing chart for explaining the lump resetting operation in this example; Fig. 14B is a timing chart for explaining the lump high-level setting operation; and Fig. 15 is a schematic arrangement diagram of an example of an image pickup system using a two-dimensional image pickup appratus. Fig. 2A is a circuit diagram for explaining a fundamental arrangement of the first embodiment of a photoelectric converting apparatus according to the present invention. In Fig. 2A, an emitter electrode of a photoelectric converting cell S is connected to a vertical line VL and grounded through a transistor Q r . The vertical line VL is connected to the accumulating capacitors C₁ and C₂ through the transistor Q₁ . The capacitor C₁ is further grounded through the transistor Q₂. A horizontal output line HL is connected through a transistor Q h to a node of the capacitor C₁ and transistor Q₂. On one hand, a pulse ₁ is applied to a gate electrode of the transistor Q₁. A pulse ₂ is applied to a gate electrode of the transistor Q₂. A pulse  r is further applied to a gate electrode of the transistor Q r . A pulse  d to read out and to refresh drive is applied to a capacitor electrode of the photoelectric converting cell S. On the other hand, a pulse  h is applied to a gate electrode of the transistor Q h . Since the photoelectric converting cell S has been described in detail in Japanese Laid-Open Patent Gazette No. 60-12759, which has already been filed by the applicant of the present invention, its description is omitted here. The operation will now be described. Fig. 2B is a timing chart for explaining the operation of the circuit shown in Fig. 2A. First, the transistors Q₁, Q₂, and Q r are first turned on by setting the pulses ₁, ₂, and  r to the high level for a time interval from t₁ to t₂, thereby clearing the capacitors C₁ and C₂ (for a period of time T₁). Next, the transistors Q₁ and Q₂ are turned on by setting the pulses ₁ and ₂ to the high level for a time interval from t₃ to t₄ and at the same time, a high level pulse  d is applied to the capacitor electrode of the photoelectric converting cell S, so that a signal accumulated in the cell S is read out and accumulated into the capacitors C₁ and C₂ (for a period of time T₂). Subsequently, the transistors Q₁ and Q r are turned on by setting the pulses ₁ and  r to the high level for a time interval from t₅ to t₆, the capacitor C₂ is cleared, and the pulse  d which is held at the high level for this period of time is applied to the capacitor electrode of the cell S, so that the refreshing operation of the cell S is executed (for a period of time T₃). After completion of the refreshing operation, the transistor Q₁ is turned on by the high level pulse ₁ for a time interval from t₇ to t₈ and at the same time, the high level pulse  d is applied to the capacitor electrode of the cell S, so that the remaining signal after the cell S was refreshed is accumulated into the capacitor C₂ (for a period of time T₄). After both of the readout signal and the remaining signal after completion of the refreshing operation of the cell S were respectively accumulated in the capacitors C₁ and C₂, the transistor Q h is turned on by the high level pulse  h for a subsequent time interval from t₉ to t₁₀, thereby allowing the charges accumulated in a series circuit of the capacitors C₁ and C₂ to be output to the horizontal output line HL (for a period of time T₅). Fig. 3 is a diagram showing the charge accumulating states of the capacitors C₁ and C₂ at that time. A switch SW dentoes the transistor Q h . The capacitor C₃ denotes a line capacitance of the output line HL. Fig. 3A shows a state just after the period T₄. The charges of -C T (V S + V N ) and C r (V S + V N ) are accumulated at both ends of the capacitor C₁, respectively. The charges of C N V N and -C N V N are accumulated at both ends of the capacitor C₂, respectively. The capacitor C₃ is cleared. C T , C N , and C H denote capacitances of the capacitors C₁, C₂, and C₃. V S and V N indicate voltages of the information signal read out of the photoelectric converting cell S and of the unnecessary signal. Fig. 3B shows a state in the period T₅. Assuming that an amount of charges accumulated in the capacitor C₃ is set to Q, the following voltage equation is satisfied. Therefore, Now, assuming that we have Thus, Q = - C TOT V S Therefore, a voltage across the capacitor C₃, that is, an output signal S out appearing on the output line HL is obtained by Consequently, it will be udnerstood that the output signal S out consists of only the information signal in which the unnecessary signal was removed from the readout signal of the cell S. As explained above, the signal S out is the signal from which the unnecessary components such as dark signal and drive noises and the remaining components were eliminated. The signal S out accurately corresponds to the illuminance of the incident light. In particular, the unnecessary components on the low illuminance side are effectively removed and this embodiment contributes to the improvement of the picture quality. Fig. 4 is a circuit diagram of a line sensor using the embodiment. This embodiment is constructed by arranging n circuits shown in Fig. 2A. In the diagram, emitter electrodes of photoelectric covnerting cells S₁ to S n are respectively connnected to vertical lines VL₁ to VL n , The circuit similar to that shown in Fig. 2A is connected to each of these vertical lines. Gate electrodes of the transistors Q r of the vertical lines are commonly connected and the pulse  r is applied to these gate electrodes. On the other hand, the gate electrodes of the transistors Q₁ are also commonly connected and the pulse ₁ is applied to these gate electrodes. The gate electrodes of the transistors Q₂ are also commonly connected and the pulse ₂ is applied to these gate electrodes. Gate electrodes of the transistors Q h corresponding to the photoelectric converting cells are together connected to parallel output terminals of a scan circuit 1 and pulses  h1 to  hn are applied to the corresponding gate electrodes. On the other hand, the transistors Q h are connected to the output line HL. The output line HL is connected to an amplifier 2 and is also grounded through a transistor Q hr . A reset pulse  hr is applied to a gate electrode of the transistor Q hr . The operation of the embodiment having the foregoing construction will now be briefly described with reference to Fig. 5. Fig. 5 is a timing chart for explaining the operation of the embodiment. As already described above, the capacitors C₁ and C₂ corresponding to the photoelectric converting cells are cleared for the period T₁ and the readout signals of these cells are accumulated into the capacitors C₁ and C₂ for the period T₂. Subsequently, the capacitor C₂ is cleared and each photoelectric converting cell is refreshed for the period T₃. The remaining signal of each cell after it was refreshed is accumulated into the capacitor C₂ for the period T₄. After the readout signal and remaining signal of each photoelectric converting cell were accumulated, the pulse  h1 is applied from the scan circuit 1 to the gate electrode of the transistor Q h for the period T₅. As mentioned above, the signal obtained by removing the remaining signal accumulated in the capacitor C₂ from the readout signal of the photoelectric converting cell S₁ accumulated in the capacitor C₁ is transferred as an information signal onto the output line HL in accordance with the connecting state of the capacitors C₁ and C₂. This information signal is transmitted through the amplifier 2 and generated as the output signal S out . After the signal of the cell S₁ has been output, the transistor Q hr is turned on by the pulse  hr and the charges remaining on the output line HL are eliminated. In a manner similar to the above, the information signals of the photoelectric covnerting cells S₂ to S n are transferred to the output line HL by the pulses  h2 to  hn and are sequentially output as the signals S out through the amplifier 2. Although the embodiment has been described with respect to a voltage readout system, the invention can be also similarly applied to the case of a current readout system in which a load resistor RL is also connected to the output line HL as shown by a broken line in Fig. 4. On the other hand, although the embodiment has been described with regard to a one-dimensional line sensor, the invention can be also obviously applied to a two-dimensional area sensor. As described in detail above, according to the photoelectric covnerting apparatus of the invention, the photoelectric conversion signal of a high S/N ratio can be obtained on-chip by using a simple method whereby the unnecessary components such as dark signal, drive noises, and the like of the photoelectric converting device are removed from the readout signals due to the connecting relation between the first capacitor to accumulate the readout signals of the photoelectric converting cells and the second capacitor to accumulate the remaining signals after completion of the refreshing operation. Fig. 6 is a schematic circuit diagram showing a fundamental arrangement of the second embodiment of a photoelectric converting apparatus according to the invention. In the diagram, the emitter electrode of the transistor connected to an output terminal of the photo sensor cell S is grounded through the transistor Q r . The pulse  r is input to the gate electrode of the transistor Q r . Further, the emitter electrode is grounded through the capacitor C₂ and is also connected to the horizontal output line HL through the capacitor C₁ and transistor Q h . Although not shown, the horizontal scan pulse  h is input from a shift register (not shown) to the gate electrode of the transistor Q h . The horizontal output line HL is grounded through the reset transistor Q hr . The pulse  hr is input ot a gate electrode of the transistor Q hr . Figs. 7 and 8 are timing charts showing the first and second examples of the practical operations of the photoelectric covnerting apparatuses in the second and third embodiments according to the invention. The first example shown in Fig. 7 relates to the example of the operation to first read out the noises and then read out the signal. The second example shown in Fig. 8 relates to the example of the operation to first read out the signal and then read out the noises. In Fig. 7, the photo sensor S is refreshed and the pulse  hr and all of the scan pulses  h1 to  hn are set to the high level for a period a, thereby clearing all of the capacitors C₁. Subsequently, the pulses  hr and  h1 to  hn are held and the capacitor C₁ is grounded through the transistors Q h and Q hr . The pulse  r is set to the low level, thereby setting the emitter of the photo sensor S into the floating state. Thus, the noise components after the photo sensor S was refreshed are transferred and accumulated into the capacitors C₂ and C₁ (for a period of time b). Then, the drive pulse ₁ trails to a reference potential and the photo sensor S starts the accumulating operation (for a period of time c). For this accumulating period c, the pulse  r is set to the high level and the capacitor C₂ is cleared. Subsequently, after completion of the accumulating period c, the pulse ₁ is set to the high level and the sensor signal corresponding to the incident light amount is read out and transferred and accumulated into the capacitor C₂ (for a period of time d). At this time, since the pulses  h1 to  hn and  hr are at the low level, the transistors Q h and O hr are turned off and the capacitor C₁ is in the floating state. Next, the horizontal scan pulses  h1 to  hn are sequentially set to the high level. The signals S out in which the noise components were removed from the sensor signals are sequentially output from the horizontal output line HL to the outside. In this case, each time the signal of one pixel is output, the transistor Q hr is turned on by the pulse  hr and the remaining charges on the horizontal output line HL are cleared (for a signal readout period of time f). Fig. 9 is a schematic circuit diagram showing a fundamental arrangement of the third embodiment of the invention. In this embodiment, a transfer transistor Q t and a capacitor C t are provided between the capacitor C₁ and transistor Q h in the second embodiment, and prior to horizontally scanning, the signal from which the noise components were removed is accumulated into the capacitor C t . The case where the circuit of the third embodiment is operated on the basis of the second operation example shown in Fig. 8 will be described. First, after completion of the accumulating period of time c, the pulses  h1 to  hn ,  hr , and  t are set to the high level and the capacitor C t is cleared and at the same time, the other end of the capacitor C₁ is grounded. The pulse ₁ is set to the high level, and the sensor signal from the photo sensor cell S is read out and accumulated into the capacitors C₂ and C₁ (for the signal transfer period of time d). Next, by setting the pulse  r to the high level, the transistor Q r is turned on, the emitter of the photo sensor cell S is grounded, the refreshing operation is performed, and the capacitor C₂ is cleared (for the period of time a). Next, the pulse ₁ is held at the high level and the pulse  r is set to the low level to turn off the transistor Q r , and the noise components of the photo sensor S are transferred to the capacitor C₂ (for the period b). The photo sensor S starts the accumulating operation (for the period c). On the other hand, when the transistor Q t is turned on by setting the pulse  t to the high level, the signal from which the noise components were removed is transferred and accumulated into the capacitor C t (for the period e). The signals are successively transferred to the horizontal output line HL by the horizontal scan pulses  h1 to  hn and  hr and output to the outside (for the period f). As mentioned above, since the emitter of the photo sensor S is directly connected to the capacitors C₁ and C₂ in the second and third embodiments, the load capacitance of the photo sensor S can be lightened and the reading efficiency can be improved. In addition, since a fluctuation of a voltage V b of the transistor due to variations in temperature, manufacturing, and the like is also simultaneously eliminated together with the removal of the noises, even if the readout signal is amplified by the amplifier arranged at the post stage, the signal of a high S/N ratio can be obtained. The circuit of the second embodiment shown in Fig. 6 can be also operated on the basis of the second operation example shown in Fig. 8. The circuit of the third embodiment can be also operated on the basis of the first operation example shown in Fig. 7. Fig. 10 is a schematic circuit diagram of another example of a solid-state image pickup apparatus using the second embodiment of the invention. In the diagram, the same parts and components as those in the embodiment shown in Fig. 4 are designated by the same reference numerals. The embodiment shown in Fig. 10 differs from that shown in Fig. 4 with respect to a point that the transistor Q₂ and pulse ₂ in Fig. 4 are omitted. The operation of the embodiment having such a construction will now be simply explained with reference to Fig. 11. Fig. 11 is a timing chart for explaining the operation of the embodiment. As already been described, for a period of time T₁, the capacitors C₁ and C₂ corresponding to the photoelectric converting cells are cleared. For a period of time T₂, the readout signals of the cells are accumulated into the capacitors C₁ and C₂. Then, for a period of time T₃, the capacitor C₂ is cleared and each of the photoelectric covnerting cells is refreshed. For a period of time T₄, the remaining signal of each cell after it was refreshed is accumulated into each capacitor C₂. After the readout signal and remaining signal of each cell were accumulated, the pulse  h1 is applied from the scan circuit 1 to the gate electrode of the transistor Q h for a period of time T₅. As mentioned above, the signal in which the remaining signal accumulated in the capacitor C₂ was removed from the readout signal of the photoelectric converting cell S₁ accumulated in the capacitor C₁ is transferred as the information signal onto the output line HL in accordance with the connecting state of the capacitors C₁ and C₂. This information signal is output through the amplifier 2 to the outside as the output signal S out . After the signal of the cell S₁ was output, the transistor Q hr is turned on by the pulse  hr and the charges remaining on the output line HL are eliminated. In a manner similar to the above, the information signals of the photoelectric covnerting cells S₂ to S n are transferred to the output line HL by the pulses  h2 to  hn and sequentially output as the signals S out through the amplifier 2. Although the embodiment has been described with respect to the voltage readout system, the invention can be also similarly applied to the case of a current readout system in which the load resistor RL is also connected to the output line HL as shown by the broken line in Fig. 10 as mentioned before in conjunction with Fig. 4. Although the embodiment has been described with regard to the one-dimensional line sensor, the invention can be also applied to a two-dimensional area sensor. On the other hand, since the noise components can be removed from the sensor signal by the single vertical line VL, the structure can be simplified and the manufacturing yield is also improved. Fig. 12 is a schematic circuit diagram of an example of a scan circuit for use in the embodiment. In this example, drive pulses  c1 and  c2 different from drive pulses Φ h1 and Φ h2 are input, thereby turning on/off transistors M₃, M₄, M₇, M₈, M₁₁, M₁₂, ---. On the other hand, in the circuit such that an arbitrary scan pulse is returned to a unit circuit which is preceding by two stages and the transistors M₅, M₉, M₁₃, --- are turned on, transistors Q₁, Q₂, ---are connected to the respective feedback lines, and the transistors Q₁, Q₂, --- are turned on/off by the drive pulse  c1 or  c2 . The operation of this embodiment will now be explained. Fig. 13 is a timing chart for explaining the operation of this embodiment. First, in a unit circuit at the front stage, when a start pulse  hs is input, the transistor M₁ is turned on by the pulse Φ h1 and a voltage V₁ rises. Since the voltage V₁ corresponds to a gate potential of the transistor M₂, the transistor M₂ indicates a conductance corresponding to the potential V₁. Subsequently, when the pulse Φ h1 trails and the pulse Φ h2 rises, a voltage V₂ increases through the transistor M₂. This increased voltage V₂ is fed back to a gate of the transistor M₂ through the capacitor C₁, so that the voltage V₁ further rises. Thus, the conductance of the transistor M₂ further increases and the pulse Φ h2 appears as the voltage V₂ without a voltage drop. In this state, the drive pulse  c2 of a narrow pulse width is input. Thus, the transistor M₃ is turned on and a voltage V₃ of the unit circuit at the first stage is raised. Subsequently, the drive pulse Φ h1 of a wide pulse width is set to the high level, thereby increasing a voltage V₄ through the transistor M₆ and further raising the voltage V₃ through the capacitor C₂. Thus, the pulse Φ h1 directly appears as the voltage V₄ and is output as the scan pulse  h1 . At the same time, the transistor M₁ is turned on by the pulse Φ h1 and the potential V₁ decreases to a reference potential. When the voltage V₄ is held at the high level, the drive pulse  c1 of a narrow pulse width rises, the transistor M₇ in the unit circuit at the first stage is turned on, and a voltage V₅ of the unit circuit at the second stage rises. When the drive pulse Φ h2 rises, a voltage V₆ increases by the transistor M₁₀ and capacitor C₃ and is output as a scan pulse  h2 . At this time point, since the transistor Q₁ connected to the feedback line is in the OFF state, the transistor M₅ is held in the OFF state. Thus, the voltage V₃ at the first stage is also at the high level and the scan pulse Φ h1 is also held at the high level. Subsequently, when the drive pulse  h1 trails, the voltage V₄ (scan pulse  h1 ) trails and the voltage V₃ also decreases. Next, when the drive pulse  c2 rises, the transistor M₁₁ is turned on to raise a voltage V₇ and at the same time, the transistors M₈, Q₁, and M₃ are turned on. When the transistor M₈ is turned on, the voltage V₄ is reset to a reference potential V rs . When the transistor Q₁ is turned on, the transistor M₅ is turned on by the scan pulse  h2 and the voltage V₃ is set to the earth potential. Further, since the transistor M₃ is turned on, the voltage V₂ is also reset to the earth potential. In this manner, as shown in Fig. 8, the scan pulses  h1 ,  h2 ,  h3 , --- are overlappingly successively output at the timings of the drive pulses Φ h1 and Φ h2 . That is, a scan pulse output of a wide pulse width of a duty ratio of 50 % or more can be derived. Fig. 14A is a timing chart for explaining the lump resetting operation in the embodiment. Fig. 14B is a timing chart for explaining the lump high-level setting operation in the embodiment. As shown in Fig. 14A, the lump resetting operation is executed by simultaneously setting the drive pulses  c1 and  c2 to the high level in the state in which the reference voltage V rs is held at the low level. In the case of the period T₁, the lump resetting operation is executed while the scan pulse is being output. In the case of the period T₂, the lump resetting operation is performed at the start of the scan. Such a lump resetting function is useful for an enlargement reading operation in an image pickup apparatus, which will be explained hereinlater. As shown in Fig. 14B, the lump high-level setting operation is executed by setting the drive pulses  c1 and  c2 to the high level in the state in which the reference voltage V ns is set to the high level. In the case of the period T₄, by setting the pulse  c2 to the high level, the transistors M₈, M₁₆, --- are turned on and the scan pulses  h1 ,  h3 , ---,  h(2n+1) are set to the high level. In the case of the period T₅, the scan pulses  h2 ,  h4 , ---,  h2n are set to the high level. The period of time T₃ shows the case of the foregoing lump resetting operation. Fig. 15 shows a schematic arrangement diagram of an example of an image pickup system using a two-dimensional image pickup apparatus. In the diagram, an image pickup device 301 corresponds to a two-dimensional apparatus of the apparatus shown in Fig. 10. The output signal S out of the image pickup device 301 is subjected to processes such as a gain control and the like by a signal processing circuit 302 and is output as a standard television signal such as an NTSC signal or the like. On the other hand, each of the pulses to drive the image pickup device 301 is supplied by a driver 303. The operation of the driver 303 is controlled by control means 304. The control means 304 adjusts the gain or the like of the signal processing circuit 302 on the basis of an output of the image pickup device 301 and also controls exposure control means 305, thereby adjusting an amount of incident light to the image pickup device 301.

Claims: Photoelectric converting apparatus in which: an output line (HL) is coupled to a plurality of signal lines (VL) through a plurality of first switch means (Qh) for receiving signals from the signal lines (VL), the signal lines (VL) each being capacitively coupled to a fixed potential and each for receiving signals from a respective photoelectric converting device (S); each signal line (VL) comprises a capacitor means (C1) having an input side coupled to receive signals from the respective photoelectric converting device (S) and an output side coupled to provide signals to the respective first switch means (Qh) for passing to the output line (HL); second switch means (Q2, Qhr, Qtc) is provided for holding the output sides of the capacitor means (C1) at a predetermined potential; and control means is operable, in respect of each capacitor means (C1) (a) to read a first signal from the photoelectric converting device (S) and apply it to the input side of the capacitor means (C1) while the second switch means (Q2, Qhr, Qtc) holds the output side of the capacitor means (c1) at the predetermined potential, and (b) to read a second signal from the photoelectric converting device (S) and apply it to the input side of the capacitor means (C1) while the output side of the capacitor means (C1) is floating, so that the capacitor means (C1) outputs to the first switch means (Qh) a signal corresponding to the difference between the first and second signals. Apparatus according to claim 1 in which each said capacitor means (C1) has a respective second switch means (Q2, Qtc) coupled to a point between its output side and the first switch means (Qh). Apparatus according to claim 1 in which a plurality of capacitor means (C1) share a common second switch means (Qhr) coupled to a point the far side of the first switch means (Qh) from the capacitor means (C1). Apparatus according to any one of claims 1 to 3 in which the or each second switch means comprises an insulated-gate FET. Apparatus according to any one of the preceding claims in which each first switch means (Qh) comprises an insulated-gate FET. Apparatus according to any one of the preceding claims in which each said signal line (VL) has a third switch means (Qr) for connecting it to a fixed potential while the output side of the capacitor means (C1) is floating after application of the first signal to the capacitor means (C1) and before application of the second signal to the capacitor means (C1). Apparatus according to claim 6 in which the third switch means (Qr) comprises an insulated-gate FET. Apparatus according to any one of the preceding claims in which one of the first and second signals is a noise signal and the other is a signal generated in response to exposure of the photoelectric converting device (S) to radiation. Apparatus according to claim 8 in which the noise signal is a dark current signal. Apparatus according to claim 9 in which the control means conducts an operation for refreshing the photoelectric converting device (S), and the noise signal is read out from the photoelectric converting device (S) following the refreshing operation.

Inventors: HARADA TADANORI, HASHIMOTO SEIJI, HARADA, TADANORI, HASHIMOTO, SEIJI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1988
Main classification: H04N5
IPC codes: H04N3