Cache memory with hit predictive logic

Abstract: A cache memory, when receiving an operand read request and the operand address from a central processing unit, responds with a signal indicative of operand available in the cache, before having checked if such operand is effectively in the cache, if in a previous operand request the effective operand presence in the cache had occurred, or starts a memory read operation, before having checked if such operand is effectively not present in the cache, if in a previous operand request, the effective absence of the operand from the cache has occurred. The decision among the two alternatives is determined by a state logic which stores the previously occurred HIT condition (requested operand present in the cache) or MISS condition (requested operand absent from the cache) and the state of which is updated in the course of a current read operation if a predicted HIT is followed by an effective MISS or if a predicted MISS is followed by an effective HIT.

Description: The present invention relates to a hit predictive cache memory. It is known that cache memories are very fast memories, having small capacity, used in modern data processing systems to store portions of the working memory contents, which portions are from time to time, more frequently used or expected to be used. Cache memories essentially comprise an operand store section and an associative memory or CAM storing the addresses of the operands contained in the cache. If a central processor, with it own cache, needs an operand, the cache checks if the operand address coincides with one of the addresses stored in the CAM section. If this occurs, this means that the operand is stored in the cache, which generates and forwards to the processor a "hit" signal and immediately thereafter sends the requested operand to the processor, without need to perform a read operation in the working memory. If the requested operand is not stored in the cache, a read operation of the working memory is started by the cache, which generally, in addition to transferring the operand read out from working memory to the processor, provides to store the same operand into one of its memory locations, in replacement of an operand already contained therein. Even if, within the cache, the address comparison operation requires only a very short time, in the order of few nanosecond tens, in the modern data processing systems which use faster and faster microprocessors, such time may be excessive and hampers the microprocessor performances. The microprocessor has to wait for the hit signal and the subsequent data availability. The situation is further made worse in the modern systems which use a virtual memory. In such systems, the central processor addresses the operands with a logical address which has to be converted into a memory physical address by a memory address management unit. In order to avoid system problems and cache complexity, the caches usually operate by comparing physical memory addresses. Between the time instant at which a central processor generates an operand request, identified by a logical address and the instant at which the cache is ready to provide a hit signal, a time interval elapses which is the sum of the time required to convert the logical address into a physical address plus the comparison time of the cache associative memory. During this time interval the central processor must generally stay idle and wait, with consequent reduction of the performances even if the central processor generally allows for a certain time delay between the reception of a signal confirming the next occurring availability of the operand (possibly the hit signal) and the effective operand availability. The cache memory which is the object of the present invention overcomes, at least in part, this disadvantages. The cache of the invention operates according to a hit predictive concept. In other words, the cache sends a prehit signal to the central processor, requesting an operand, before the physical operand address is compared with the CAM contents. If, after comparison, a hit occurs, the operand is made available. If the comparison is not successful, that is a "miss" occurs, the prehit signal is invalidated by a subsequent error signal which is forwarded to the central processor. The prehit signal generation is not systematic, but is performed on the basis of the immediately preceding history of the operand requests. This history defines the status of a hit/miss indicator circuit. If the hit/miss indicator provides a prehit signal and thereafter the comparison is not successful and a miss occurs, the indicator is set to provide a premiss signal. At the receipt of a next following operand request the premiss indication allows to start a memory access operation, even if the requested operand may be present in the cache. As a possible alternative the start of the memory access operation may be conditional to the occurrence of a miss signal from the cache. If the operand is present in the cache the indicator is set to generate a prehit signal and the operand, read out from working memory, is delivered to the central processor. If the operand is not present in the cache, once it has been read out from the main memory, not only it is delivered to the central processor, but it is also loaded into the cache. The prehit/premiss indicator is however left in premiss state. By this predictive mechanism the following advantages are achieved. In case of confirmed prehit, the access to an operand contained in the cache may occur without wait states of the central processor. An operand request operation is repeated only in case the prehit is not confirmed. In case of premiss, the main memory read operations are started without waiting for a confirmation of the effective need to perform them. Since the operands, being them instructions or data, are mostly arranged in blocks, with sequential addressing, in most of the operand request operations the confirmed prehit condition occurs and the cache is exploited at the best. In confirmed premiss condition the main memory is exploited at the best. It is only when there is a change from one condition to the other that time waste occurs, either for performing a working memory access, following a non confirmed prehit, or for the superfluous execution of a memory access operation, following a non confirmed premiss. In this way the performances obtainable from a system including a central processor, a cache and a working memory are greatly increased. The sequential arrangement of instruction operands is generally distinct from the sequential arrangement of data operands. Therefore the prehit/premiss indicator is suitably arranged to provide a distinct indication for data and for instructions. These features and the advantages of the invention will appear more clearly from the following description of a preferred form of embodiment of the invention and from the enclosed drawings were: Figure 1 shows in block diagram a data processing system including the predictive cache of the invention. Figure 2 shows in timing diagram the several signals which control read and write memory operations and which are exchanged between the central unit and the working memory or the cache in the system of Figure 1. Figure 3 shows in circuit diagram the control logic for the predictive cache of the invention Figure 4 shows in timing diagram the signals which are exchanged between the central unit and the cache in the system of Fig. 1, in case of hit prediction by the cache. Figure 5 shows in timing diagram the signals which are exchanged among the central unit, the cache and the working memory in case of miss prediction by the cache. Figure 1 shows in block diagram a data processing system including the predictive cache of the invention. The system comprises a central processing unit or CPU 1, a memory address management unit or MMU 2, the cache memory 3, a memory control unit or MCU 4, an oscillator 6 for generating a preiodical timing signal, and a working memory 7. CPU 1, MM 2 may be implemented in several ways, but for clearness of description it is advantageous to refer to a CPU 1 consisting in microprocessor MC68020, manufactured by the firm MOTOROLA and to the related MMU consisting in the integrated circuit MC68851. At the block diagram level of Fig. 1, the system architecture is conventional: CPU 1 is connected to the working memory 7 for information transfer (read/write) through a bidirectional data bus DBUS 8. The memory address where to peform the transfer is supplied by CPU1 on a channel ABUS 9 and received by MMU 2, which converts the virtual address into a physical memory address, present on channel PADD 11, which connects MMU 2 to MCU 4. Control signals are exchanged among CPU 1, MMU 2, cache 3 and control unit 4, through a control bus CBUS 10. Cache memory 3 is further connected to channel PADD 11 for receiving addresses and to channel DBUS 8 for receiving or outputting information. Channels DBUS 8, PADD 11, CBUS 10, constitute in the whole a communication port for the control unit 4, which is preferably of the two port type. It is provided with a second port 5 connected to a communication channel 24 for connection to input/output processors and generically to peripheral control units. MCU 4 provides, in known manner, to resolve conflicts in the access requests received from the two ports, according to suitable priority criteria. For a better understanding of the invention, timing diagrams of Figure 2 summarize the operation of CPU 1 and MMU 2 for memory transfers. The operation of CPU 1 develops in the course of timing cycles defined by a periodical clock signal CK, generated by oscillator 6, along with a negated clock signal CK . Signal CK has (by way of example) a period of 60 nsec and comprises two square wave half periods of 30 nsec each. Each half period defines a working state of the CPU. A memory read operation requires 6 working states and a variable number of wait states, depending on the speed at which the memory can fulfill the CPU 1 request. During a first state S0, CPU 1 places a logical address AO-31 on the address channel and a set of control signals on the control channel. Among such signals there is a signal R/W at logic level 1, to indicate a read operation and signals FCO-2 which, depending on their logic level, define the nature of the requested operand as a user data, a user program instruction, a supervisor data, a supervisor program instruction. During state S1, CPU 1 drops to 0 a signal AS, to validate the signals present on the address and control channels. MMU 2 receives the logical address AO-31, the function code FCO-2 and strobe signal AS. Within a maximum delay of 45 nsec from receipt of the logical address it puts on channel PADD the physical address PAO-XX corresponding to the logical address and lowers a strobe and validation signal PAS on an omonimous lead. This event occurs in the state SX immediately following state S2. If CPU 1 does not receive a signal DSACK at level 0, if is placed in a wait state SX comprised of one or more clock periods. Signal DSACK, received by CPU1 must guarantee to the CPU1, that the requested information will be available on the data bus with a delay, not exceeding one clock period at most. When DSACK is received, CPU 1 moves to states S3 and S4 and by the end of state S4 it loads the information present on data bus, into an internal register. This is performed only if a signal BERR is at level 1 on a control lead to indicate that the read operation has been correctly performed and no error is present in the read out data. In case of error, the BERR signal must be lowered at level 0 at least 20 nsec before the transition from state S4 to state S5. Once the read operation is concluded, during state S5, CPU 1 raises again to 1 signal AS and removes the address and the commands from the respective channels. When receiving AS=1, MMU 2 and the unit which has generated the DSACK signal (MCU 4 or cache memory 3) must respectively raise to 1 signal PAS and DSACK. If, together with signal BERR=0, the CPU 1 receives also a signal HALT=0, CPU 1, at the conclusion of state S5, performs a rerun operation, that is tries again the previous read operation. Substantially similar is the operation in case of a write transfer, with the only difference that in this case CPU 1 puts the operand to be written on data channel DBUS 8, during state S2 (Diagram DBUS (W), and in the course of the next following state, lowers to 0 a signal DS on a control lead to indicate that the data is present on the bus. DS raises to 1 during state S5 together with AS. From the preceding summary it appears that MCU 4 needs, in order to operate with CPU1, an input/output data channel, an address input channel, an input signal for memory activation, and signal AS or PAS may perform such function, an input for signal R/W and possibly DS and must be capable of generating a signal DASTRO which performs the function requested to signal DSACK, that is guarantees that the read out information will be available with a delay not exceeding 60 nsec (a clock period) as to the DASTRO transition from 1 to 0. MCU 4, as well as memory 7 may be of a conventional type and do not deserve any detailed description. It will be noted only that, even if a read or write operation performed by CPU 1 requires as a minimum 6 states, that is 180 nsec, the time interval between the availability of the logical address, validated by AS=0, and the need to have a read out data available on DBUS 8 channel is of 3 states only (states S2, S3, S4). It is known that in currently used dynamic memories, organized in rows and columns, it is possible to start a memory cycle even if an address portion only is known, the portion corresponding to a row address. The address portion corresponding to a column address may be rendered available at a subsequent time. It is also known that in virtual memory systems the conversion from logical to physical address affects a field only of the address and that portion which identifies a memory row address may be expressed with a logical address which coincides with a physical address. Memory 7 could therefore start a memory cycle on receipt of signal AS=0. However, even so, it should be capable of completing the read operation in the course of three states that is within 90 nanosec. This operatin time is, at the state of the technology, unattainable, and dynamic memories of large capacity and low cost are manufactured which feature a memory cycle in the order of 200 nanoseconds only. The introduction of wait state, in the operation of CPU1 is therefore unavoidable, or the adoption of a cache memory, such as memory 3 is required to overcome this unconvenient. Cache memory 3 essentially comprises a content associative memory or CAM 12, having an internal comparator, a cyclic counter 13, a fast read/write memory 14, a set of bidirectional tristate gates 15 and a control logic 16. Because the invention essentially resides in the control logic 16, a brief description only of the other functional elements is provided. Through a loading process which will be described hereinafter a physical memory address is loaded into the associative memory 12, at each addressable location, and at the same time the operand which, in the working memory, is present at the same physical address is loaded in a corresponding location of fast memory 14. Fast memory 14 is therefore a partial copy of the working memory. A list of each of the addresses of the operands stored in fast memory and related thereto is stored in CAM 12. When CPU 1 interrogates the working memory 7 and the cache memory 3, for a read operation, the physical address present on channel PADD 11 is transferred to CAM 12 and compared simultaneously with all the addresses stored in CAM 12. In case of successful comparison, CAM 12 outputs a "HIT" signal on lead 18 and an addressing code on output channel 19. Such code, in addition to indicating which is the particular CAM 12 location for which a hit occurred, enables the selection of that particular memory 14 location where the related operand is contained. Such operand may be read out and transferred on channel DBUS 8, through gates 15. It is clear that in hit case, the working memory 7 is not activated. On the contrary, in case of unsuccessful comparison, CAM 12 outputs a "MISS" signal to indicate that the requested operand is not contained in fast memory 14. In this case it is required to start a working memory 7 read operation and to update the contents of the cache memory 3. The so called FIFO method may be used. Cyclic counter 13 outputs an address code to CAM 12, the code, decreased by one, indicating which has been the last CAM 12 location (and correspondingly the last memory 14 location) to be loaded. Therefore the code indicates which, among the several locations, has been the first to be loaded. In case of a "miss" the physical address present on channel PADD is loaded into the CAM12 location pointed by cyclic counter 13 and thereafter the counter is incremented by one. The preexisting information stored therein is therefore erased. Furthermore, the operand made available by working memory 7 on channel DBUS 8 is loaded in the memory 14 location corresponding to the updated CAM 12 location. The architectural arrangements which enable to reduce the number of constitutive components of CAM 12 are beyond the scope of the invention. It suffices to note that control logic 16, which receives signals HIT, MISS, must provide an increment command INCR to counter 13, a write command DATL to memory 14 and control signals (DATIN-DATEN) to bidirectional gates 15 to enable them to a transfer in one direction or the other. Typically CAM 12 may have a maximum response time in the order of 30 nsec and the fast memory 14 a maximum response time in the order of 25 nsec. As a consequence, being the physical addresses available at least in the first half of state S2, an operand present in fast memory 14 can be made available on channel DBUS 8 within state S4, without need of wait states, and the hit signal can be made available within state S3. Therefore, in case of hit, CPU1 may virtually obtain the requested operand from cache memory 3, with a read operation performed in six subsequent states S0-S5 and without wait states. However, it is required to provide the CPU 1 with a signal DSACK=0 within state S2 and such signal cannot be originated from the hit signal, because this one is available only in state S3. Hence the need to use a predictive HIT signal, which is issued in advance and only later confirmed or non confirmed. The control logic 16 shot in Fig. 3 provides such signal as a function of previously occurred events. The control logic of Fig. 3 comprises a decoder 25, fifteen JK flip flops 26,27,28,29,30,31,32,33,34,35,45,46,52,53,54, a multiplexer 36, three NAND gates 37,38,39, three NOR gates 40,41,42, three AND gates 43,44,45, two inverters 47,48, three open collector drivers 49,50,51, a delay element 52 and two open collector NAND gates 56,57. The operation of the control logic 16 may be easily understood with reference to Figure 3 and to Figures 4 and 5 which show in timing diagram the status of several components shown in Figure 3 and the signal level present at some points of the control logic for different operating conditions. Flip flop 30, delay element 52 and NAND gate 37 constitute a timing logic which define an active state for the cache. Flip flop 30 receives signal AS, CPU 1 generated, at the J,K inputs and signal CK at the clock input. Therefore, when CPU1 controls an external operation and drops signal AS during state S1, flip flop 30, normally set, is reset by the next following leading edge of CK, that is at the beginning of state S2. At the same time a signal CS2 at level 0 is produced at the direct output of flip flop 30. This signal is maintained till the first leading edge of the CK clock signal next following the raising again of AS to Level 1, that is till the end of CPU 1 state S5. During this time interval, a number of wait states may be comprised between state S2 and state S3, which depends on the time at which CPU 1 receives DSACK at logical level 0. With the return of flip flop 30 in set state, the signal present at the inverting output of flip flop 30 drops to 0 and is input, with a delay imposed by element 52 to an input of NAND 37 which receives at a second input signal CS2 already raised to logical level 1. Therefore, with the raising again to 1 of CS2 a short pulse CLR.at logical level 0 appears at the output of NAND 37, this output being normally at level 1. This pulse is used to reset the several elements of the control logic. It ends each activation cycle of the control logic. Figure 4 shows in timing diagram the status of signals CK, AS, CS2 and CLR. Decoder 25, flip flops 26,27,28,29 and multiplexer 36 form a hit prediction and hit updating logic. Flip flops 26,27,28,29, when set, indicates that in the course of a read operation preceding a current reading a hit had occurred between physical memory address and an address stored in the CAM 12, respectively for an address pertaining to a user data field (flip flop 26) a user program field (flip flop 27) a supervisor program field (flip flop 28), a supervisor data field (flip flop 29). The signals in output from the direct output of flip flops 26,27,28,29, respectively UDI,UPI,SPI,SDI, are input to the inputs, respectively I2,I1,I3,I4, of multiplexer 36 which receives function code FCO-2 at the control and selection inputs. Therefore if, in the course of a current operand request from external source, CPU 1 generates the function code FCO-2=100 to indicate that the requested operand is a user data (pertaining to the user data field), multiplexer 36 selects and outputs signal UDI present at input I2. If UDI signal is at level 1, it indicates that in the course of a preceding operand request a hit had occurred, that is the operand was contained in the cache. In general way, for each operand request issued by CPU1, multiplexer 36 outputs a signal PRHIT at Level 1 to indicate that an operand of the same nature (user program data/instruction, supervisor program data/instruction) had been previously found in the cache, or at level 0 to indicate that an operand of the same nature had not been previously found in the cache. Signal PRHIT, being the result of the selection operation performed by multiplexer 36 due to function code FCO-2 is already available in the course of the state S1 and is inputted to NAND 36, together with signal R/ W , generated by CPU1 and indicating. When at level 1 that the requested operation is a read. NAND gate 39 receives a signal NOCAC at a third input. NOCAC is normally at logic level 1. The output of gate 39 is therefore at level 1 for a write operation and depends on the status of PRHIT signal for a read operation. The case in which PRHIT=1 and R/ W =1 (read operation with prehit) is now considered. In this case, shown in the timing diagram of Fig. 4, the output of gate 39 is at logical Level 0. The output of gate 39 is connected to an input of NOR gate 40, which receives signal CS2 at a second input. Therefore, as soon as CS2 falls to 0, the output of gate 40 raises to 1 and outputs a signal ACK=1 which is inputted to a NOR gate 41. The output of NOR 41 falls to 0 and outputs a signal DSACK=0 which is forwarded to CPU1 to indicate that the requested operand will soon be available. The falling of DSACK to 0 clearly occurs during state S2 (Figure 4 diagram DSACK). Signal ACK=1 is further input to the J,K inputs of flip flop 32, normally reset. Flip flop 32 is set by the raising edge of signal CK corresponding to the beginning of state S3 and generates at the direct outpout a signal CACK=1 which is applied to a second input of NOR gate 41 and holds signal DSACK at level 0 even if PRHIT signal drops to level 0. The inverting output of flip flop 32 is connected to an input of NOR gate 42 which receives signal CS2=0 at a second input. Thus, in state S3, signal DATEN (Fig. 4) at the output of gate 42 raises to logical level 1 and enables tristate gates 15 to transfer the information read out from fast memory 14 onto data channel DBUS 8. The address to fast memory 14 is obviously provided by CAM 12 which in turn receives, from channel PADD 11, a physical address valid at least within state S2, and is therefore able to provide a selection address for the fast memory 14 at least within state S3, together with a HIT or MISS signal. In case of HIT the operand request operation is concluded by CPU 1 reading the information transferred from fast memory 14 onto data channel DBUS 8. This occurs during state S4. During state S5 CPU 1 raises signal AS to 1. This has the effect of disabling tristate gates 15 because DATEN signal falls to 0, and immediately thereafter, with the raising to 1 of signal CK (end of state S5) signal CS2 raises again to 1 and signal CLR resets flip flop 32. As a conseguence DSACK signal raises again to 1. In case of MISS=1 generated within state S3, MISS signal, inputted to AND 55 together with signal CACK, raises to 1 the gate 55 output, which is connected to an input of NAND gates 56, 57,38. Gates 56,57 receive signal CK at a second input and have their output connected to control channel leads for transferring respectively signals HALT and BERR to CPU 1. Gate 38 receives signal CK and a MASK signal, normally at level 1, at a second and third input respectively. Therefore at the beginning of state S4, in case of MISS=1, that is of absence of the request operand from the cache, a signal MISRE=0 (Fig. 4) is generated at the output of gate 38. At the same time signal HALT and BERR are dropped to 0. MISRE signal is input both to decoder 25, both to the reset input of flip flop 31. When MISRE=0 decoder 25 raises at the outputs, depending on function code FCO-2 present at the input, one of the signals RUPI,RUDI,RSPI, RSDI, respectively. These signals are input to the clock input of flip flops 27,26,28,29 respectively. The J,K inputs of such flip flops are connected to level 0 so that they are reset on receipt of the clock signal (RUPI,RUDI,RSPI,RSDI). Therefore the flip flop indicator related to the data/instruction field identified by the current function code FCO-2 is reset. Signal MISRE=0, input to the set input of flip flop 31, resets it. The inverting output of flip flop 31 is connected to the input of drivers 49, 50, having an output, of the open collector type, connected to the control channel leads used to transfer signals HALT, BERR respectively, and keeps signal BERR, HALT at level 0 even after the termination of clock pulse CK and until the end of state S5. Then, with the reset of flip flop 32, whose direct output is connected to the reset input of flip flop 31, these signals are raised again to 1. MISRE signal, on the contrary, raises to 1 at the end of state S4, owing to the dropping to 0 of signal CK. Flip flop 54, which has J,K inputs connected to the direct output of flip flop 32 (to receive signal CACK) has the function of generating a masking signal to avoid that at the end of state S5 and at the beginning of the next following state S0, when flip flop 32 is not yet in reset, due to unavoidable propagation times, signal MISRE at the output of gate 38 could be dropped, by the clock pulse CK corresponding to state S0. Flip flop 54 is reset by signal CLR received at the reset input. It must be noted, to summarize, that in both cases (HIT,MISS) the memory access request is "captured" by the cache memory 3 which, in one case supplies the requested information without modifying the status of the hit prediction logic (flip flops 26,29); in the other case generates the BERR and HALT signals and updates the status of the hit prediction logic. On receipt of the error (BERR) signal the CPU1, performs a "rerun" operation, that is it retries the read operation at the same address. It is of interest to consider how the control logic of Fig. 3 responds to this request, and more generally how it operates in case of a read operation, when the prediction logic indicates a MISS situation. The operation is shown in the timing diagram of Figure 5. As soon as AS=0 is received, the already considered timing logic is activated and at the beginning of state S2 signal CS2 is dropped to 0. In this case, the PRHIT signal is at logic level 0, because the corresponding hit indicator has been reset. The output of NAND gate 39 is connected to the JK inputs of flip flop 34, which receives at the clock input signal CS2 (present at the inverting output of flip flop 30). Being the output of gate 39 at logic level 1, flip flop 34 is set at the beginning of state S2 and generates a signal NOCAC at the direct output (Fig. 5). NOCAC is forwarded to the memory control unit 4 as a memory access request. After a time which depends on the duration of the memory cycle and also on the circumstance that the memory access request can be immediately honoured or queued to other running or pending access requests (assumption has been made that MCU 4 is double port type) the MCU 4 responds to the request by raising a signal DASTRO at logic level 1. Signal DASTRO is applied at an input of NOR gate 41 which outputs signal DSACK=0 towards CPU1. Signal DASTRO is applied to the J input of flip flop 33, which has the K input connected to logic level 0. Flip flop 33 receives at the clock input signal CK (inverted CK) generated by oscillator 6. Therefore, by the first raising edge of CK following the reception of DASTRO, and corresponding in the CPU1 to the beginning of state S3, flip flop 33 is set and a signal DATIN is raised at its direct output. DATIN enables bidirectional gates 15 to transfer the information present on channel DBUS 8 into fast memory 14 at the address pointed by cyclic counter 13. DATIN is further inputted to the clock input of flip flop 52, which receives at the J input the signal MISS, generated by CAM12. In case MISS=1 flip flop 52 is set and generates a signal MISS1=1 at the direct output. DATIN is also input to the J input of flip flop 35 which receives signal CK at the clock input and logic level 0 at the K input. By the raising edge of CK following the one which set flip flop 33, that is at the end of CPU 1 state S4, flip flop 35 is set too and its direct output rises to logical level 1, Direct output of flip flop 35 is connected to an input of AND gate 44, which receives signals MISS1, MERR and R/W at other inputs. MISS1 is generated by flip flop 52, R/W is generated by CPU1 and MERR is generated by MCU4 together with the data read out from memory and is at logical level 1 in case of no error (in the data). Thus, if the requested information is not contained in the cache and therefore MISS=1 and the memory operation has been correctly performed and therefore MERR=1, the output of gate 44 raises to 1 and generates a signal DATL which is forwarded to CAM 12 and to the fast memory 14 in order to load (at the occurrence of DATL raising edge) the address present on channel PADD and the data present on channel DBUS 8 into CAM 12 and memory 14 respectively, the memory 14 addressed location being identified by cyclic counter 13. At the end of CPU state S5, signal CLR resets flip flops 33,35,52. They drop to 0 signals DATIN, DATL and MISS1 respectively. DATL signal generates, through inverter 48, the signal INCR, which, by its raising edge at the end of state S5 causes the cyclic counter 13 to increment. In case of read error, the updating operation of the associative memory contents is not performed and signal MERR=0 is transferred, through driver 51, to CPU 1 for suitable error handling.. In the preceding case of "rerun", that is memory read following a non confirmed prehit, it is clear that signal MISS is necessarily at level 1 and it can be noted that the state of the prehit indicators 26,27,28,29 is not modified. The case is now considered in which the prehit indication is false (PRHIT=0) and therefore a read memory operation is immediately started, but in the course of its execution CAM 12 provides a HIT indication. Therefore the requested information is already in the cache. In this case the memory read operation proceeds normally but no contents updating is performed in the cache. In fact signal MISS=0 inhibits the generation of signals DATL and INCR, By reverse an updating is performed of the prehit indicators status. To this purpose signal NOCAC is input to the J input of flip flop 45 which receives CK signal at the clock input and signal CLR at the reset input. The direct output of flip flop 45 is connected to the J input of flip flop 46 which receives CK signal at the clock input and CLR signal at the reset input. The direct output of flip flop 46 is connected to the J input of flip flop 53 which receives CK signal at the clock input and CLR signal at the reset input. Flip flops 45,46,53 operate as a shift register: When signal NOCAC raises to 1, flip flops 45,46,53, normally reset, are set in sequence at each transition of CK signal. At the direct output of flip flop 46 a signal CT150 raises at level 1 150 nsec following the beginning of a state S0 and at the inverting output of flip flop 53 a signal CT180 drops at Level 0 180 nsec following the beginning of state S0. The two signal are both at logic level 1 in a time interval of 30 nsec in which the hit signal, in case of hit, is present in stable way. Signals CT150, CT180 are input to decoder 25, together with signals R/ W and HIT. The joint presence of such signals at level 1 causes the generation (by decoder 25) of one set pulse at logic level 0, among four possible set pulses SUPI,SUDI,SSPI,SSDI, depending on the function code FCO-2 in input to the decoder 25. Therefore, if the instruction under execution is related to a user program instruction, pulse SUPI=0 is generated. SUPY is applied to the set input of flip flop 27 and sets it. In order to avoid that the indicator state change provides a prehit indication, through multiplexor 36, in the course of the current read operation and the consequent activation of flip flop 32, NAND gate 39 has an input connected to the inverting output of flip flop 34. Even if not relevant to the scope of the invention it is advisable to consider the operation of the control logic in case the CPU 1 requests memory write operations. In this case it is essential to guarantee that the contents of the cache memory coincide with the contents of the working memory. Therefore signal R/ W =0, in input to NAND gate 39 causes the set of flip flop 34 and the start of a memory cycle. In addition, if the write address is an address contained in CAM 12 and consequently the HIT condition is verified, when signal DASTRO=1 is received from MCU 4 flip flops 33, 35 are set. The direct output of flip flop 35 is connected to an input of AND gate 43, which receives as inputs signals HIT and R /W (obtained from R/ W through inverter 47). AND gate 43 outputs signal DATL. Therefore the information present on channel DBUS 8, in addition to being written in the working memory is also written into the cache (and more precisely into memory 14) at the address specified by CAM 12. The described method is known as "write through" It is clear that the cache memory and particularly the control logic which has been described with reference to the drawings is only a preferred form of embodiment of the invention and that several changes and additions can be made to it. For instance flip flop 45, 53 as well as flip flops 33, 35 may be substituted with shift registers. The logical level of the signals, may be changed in whole or in part and consequently the logical function performed by the several gates will have to be adapted to the different circumstances. In addition, if it is foreseen at software level, that I/O processors can access to the same memory fields used by CPU 1 and it is desired to avoid the use of memory blocks protection at software level it is possible to add "watching" circuits to the cache control logic. "Watching" circuits monitor the write operations performed by I/O processors within the working memory, so that, if such operations modify information which is also contained in the cache memory, such information is also modified in the cache or invalidated. Likewise, the HIT prediction logic which provides a prehit/ premiss indications, severed for data/instructions of supervisor/user programs so as to fully exploit the performances offered by the particular used microprocessor (MC68020) may be simplified and provide a specific prehit signal for two only categories of operands (data-instructions) or more simply, even if less efficaciously in term of performances increase, a single prehit signal for both data and instructions. Other changes may relate to the prehit, premiss concepts, which may be used in partial way only. For instance, it is possible to arrange for a control logic which provides a prehit signal in case of previous hit, but that in case of premiss does not start immediately a memory read operation and waits for the result of the comparison performed in the associative memory. In this case, the memory read operation may be activated only in case of effective miss, that is in case of effective need. In case of hit, the requested information may be provided by the cache. For the purpose of rendering more clear the wording of the appended claims it is also noted that signals CS2 and CS2 , whose generation is univocally determined by signal AS generated by CPU 1, in synchronism with clock signal CK, may be considered as generated or anyhow derived from CPU 1 and constitute an address strobe signal synchronized with the clock signal.

Claims: Hit predictive cache memory wherein an associative memory contains addresses of operands stored in a working memory and a fast memory contains the operands corresponding to said addresses, said associative memory, when interrogated by a central processing unit, providing a hit or miss signal to indicate respectively that a requested operand is present or not present in said fast memory, characterized in that said predictive cache memory comprises: a control logic (25,26,27,28,29,36) comprising at least a storage element (26,27,28,29) to store a hit or miss condition occurred during a preceding interrogation of said cache memory and to provide a corresponding prehit or premiss indicator signal, first logic circuits (39,40,32,34) receiving memory read interrogation signals (CS2,R/ W ), obtained from said central processing unit, and said indicator signal, and providing to said central processing unit a signal (CACK) indicative of operand present in said cache memory, irrespective of the effective presence of said operand, when said indicator signal is a prehit indicator, and for providing a memory access signal (NOCAC), second logic circuits (55,38,56,57,31,49,50,54) receiving said miss signal from said associative memory, and said signal (CACK) indicative of operand present in said cache memory, for generating an error signal (BERR), for delivery to said central processing unit which then retries the read operation at the same address, and a reset signal (MISRE) for said storage element, whereby said storage element provides a premiss indication, if said miss signal and said signal indicative of operand present in the cache are jointly received, third logic circuits (33,35,52,44) receiving a signal (DASTRO) indicative of operand available, issued by said working memory, and said miss signal from said associative memory, to generate a load signal (DATL) for loading said associative memory and said fast memory, if said miss signal and said signal indicative of operand available are jointly received and fourth logic circuits (45,46,53,25) receiving said memory access signal (NOCAC) and said hit signal from said associative memory to provide a set signal to said storage element, for storing therein a hit condition if said hit signal and said memory access signal are jointly received. Hit predictive cache memory as claimed in claim 1 wherein said control logic comprised further; fifth logic circuits (39,34) receiving said memory read interrogation signals (CS2, R/ W ), obtained from said central processor, and said indicator signal and providing, as input to said working memory, said memory start signal (NOCAC) for reading an operand out of said working memory, irrespective of the absence of said operand in said cache memory, when said indicator signal is a prehit indicator, the absence of said operand from said cache being subsequently confirmed or non confirmed by said associative memory.

Inventors: FIACCONI CLAUDIO, FIACCONI, CLAUDIO
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS ITALIA S.P.A.
Application year: 1988
Main classification: G06F12
IPC codes: G06F12