VIDEO DISPLAY INTERFACE

Abstract: A video display interface adapted for use with D.C. electroluminescent display panels and constant current display drivers is disclosed. The video display interface receives serial video data at a frame rate of 60 Hz, converts it into eight bit words and stores it in a double-buffered video memory according to a memory map having ten sections corresponding to ten logical display sections. The video display interface reads stored video data out of the memory map, converts it to ten bit parallel output words and outputs the ten bit words to display drivers to drive multiple sections of the display simultaneously at an output frame rate of 240 Hz. The video display interface also generates constant current and pre-charge control signals that are used by the display drivers to generate constant current and pre-charge signals for driving the display.

Description: VIDEO DISPLAY INTERFACE BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to inter¬ faces for video displays and more particularly to a digital video display interface that is adapted to provide high speed data output and constant current drive control for flat panel D.C. electroluminescent displays and other displays which benefit from such features. 2. Statement of the Related Art Flat panel video displays are typically used in portable computers and other applications where there is a need to visually display information but where a traditional cathrode ray tube (CRT) display is unsuitable or not cost effective. At present, liquid crystal display (LCD) technology is the most widely used flat panel display technology due to its relatively low cost, low current consumption, and relatively long life span. LCD technology is not without problems, however. LCD displays often provide inadequate contrast and visibility, particularly in conditions of low ambient light. Such displays also typically have severe viewing angle limitations. Gas plasma and electroluminescent flat panel display technologies generally provide much better contrast and visibility, even in poor ambient light conditions. However, in the past these technologies were not widely used due to their relatively high cost, high current consumption, and relatively short life spans. Advances in these technologies have succeeded in reducing the cost and current consumption of such panels, but until recently the relatively short life expectancy of such panels, and of electroluminescent panels in particular, continued to be a problem. With respect to D.C. electroluminescent panels in particular, it has been found that intense heating effects associated with excessive, non-uniform power dissipation in such panels is a major cause of the undesirably short effective life span thereof. It has also been recently discovered that the effective life span of such panels can be greatly increased by using relatively low-level constant current drive signals to reduce the average power dissipation and attendant heating thereof. Low-level drive signals generally produce lower peak luminence levels in the luminescent material of electroluminescent panels than do higher level drive signals. However, the lower peak luminence can be compensated for and suitable brightness and contrast obtained by refreshing the panel at a sufficiently rapid rate. An output frame rate of 240 Hz has been suggested as a suitable rate, for example. One consid¬ eration in this regard is that the luminescent materials used in such panels typically have a degree of natural capacitance associated therewith which tends to oppose instantaneous switching of the material between off and on states. In order to operate an electroluminescent panel at the desired relatively high rate of 240 Hz, for example, it is necessary to rapidly overcome this natural capacitance. According to the teaching of co-pending United States Patent Application Serial No. 934,958 filed on November 26, 1985 and en¬ titled Constant Current Display Driver, which is owned by the assignee of this application, desirably rapid electroluminescent display output can be accomplished by initially driving the panel concurrently with a rela¬ tively low-level constant current drive signal and an additional pre-charge pulse having a selected amplitude. The pre-charge pulse is applied for a short time to rapidly bring the the voltage across a particular luminescent element or pixel to just under the lumina- tion threshold thereof. The pre-charge pulse is then removed and the low-level constant current drive signal continues to drive the element to cause it to luminesce. It has been found that the use of constant current drive signals can have beneficial results with other display technologies as well. For instance, it has been found that using constant current drive signals to drive gas plasma displays generally results in improved uniformity of illumination and hence improved visibility. The ability to refresh the display at a relatively high rate is also beneficial with panels other than D.C. electroluminescent panels. For instance, with A.C electroluminescent panels, the refresh rate determines the overall brightness of the display. By selectably varying the refresh rate, various brightness levels can be obtained. There is presently a need for a video display interface that is capable of operating in conjunction with constant current display drivers such as those described in the above-identified co-pending applica¬ tion to take advantage of the recent improvements in electroluminescent display technology. This need encompasses specific needs for an interface that can provide constant current and pre-charge control for such drivers and that can output data at a suitably high frame rate, e.g. 240 Hz. Accordingly, it is an object of the invention to provide such an interface that is adapted for use with D.C. electroluminescent display technology as well as other display technologies that might benefit from the use of constant current drive signals. It is another object of the invention to provide such an interface that is adapted to flexibly accommodate a variety of digital video controllers and displays with varying specifications. It is still another object of the invention to provide such an interface that accomplishes the above objectives at minimal cost. SUMMARY OF THE INVENTION The foregoing objects and attendant advantages are ' obtained by providing a video display interface that receives video data and that generates at least one control signal adapted to selectably control a plurality of substantially constant current display drive signals, such as those generated by constant current display drivers, corresponding to the video data. The control signal and the ideo data are output together to generate a video display. Also provided, is a video display interface of the above type that also generates at least one second control signal adapted to selectably control a plurality of pre-charge display drive signals. The at least one second control signal is also output with the video data to generate a video display. In another aspect of the invention, a video display interface is provided that receives video data and temporarily stores it in a storage having a plurality of logical sections corresponding to a plurality of display sections at a first selected rate. The interface then reads the stored video data by reading successive portions of the total data from each section. The interface repetitively outputs the video data at a second selected rate higher than the first selected rate. BRIEF DESCRIPTION OF THE DRAWINGS The novel features that are believed to be characteristic of the invention are set forth in the appended claims. The invention itself, together with the foregoing objects and attendant advantages thereof, will be best understood by reference to the following detailed description of a presently preferred embodi¬ ment of the invention, taken in conjunction with the drawing, in which: FIG. 1 is a block diagram illustrating a video display interface embodying the principles of the invention in an exemplary arrangement with a computer, a video display, video memory banks, display drivers, and other external elements; FIG. 2 is a block diagram illustrating a preferred logical division of the display and a corre- sponding memory map employed by the preferred video display interface; FIG. 3 is a block diagram illustrating the format in which video data is read out of the memory map illustrated in FIG. 2 by the preferred video dis- play interface; FIG. 4 is a block diagram illustrating generally the internal functional components and interconnections of a preferred video display interface circuit embodying the principles of the invention; FIGs. 5a through 5c inclusive are schematic diagrams illustrating the details of the video delay logic illustrated generally in FIG. 4; FIG. 6a is a schematic diagram illustrating the details of the reverse clock logic illustrated generally in FIG. 4; FIGs. 6b through 6f inclusive are schematic diagrams illustrating the details of the internal clock logic illustrated generally in FIG. 4; FIG. 7a is a schematic diagram illustrating the details of the line width program sub-logic of the program logic illustrated generally in FIG. 4; FIG. 7b is a schematic diagram illustrating the details of the constant current time select sub- logic of the program logic illustrated generally in FIG. 4; FIG. 7c is a schematic diagram illustrating the details of the pre-charge time select sub-logic of the program logic illustrated generally in FIG. 4; FIGs. 8a and 8b are schematic diagrams illustrating the details of the video input sub-logic of the write logic illustrated generally in FIG. 4; FIG. 8c is a schematic diagram illustrating the details of the write control sub-logic of the write logic illustrated generally in FIG. 4; FIG. 8d is a schematic diagram illustrating the details of the write address counter sub-logic of the write logic illustrated generally in FIG. 4; FIGs. 9a through 9d inclusive are schematic diagrams illustrating the details of the memory read sub-logic of the read logic illustrated generally in FIG. 4; FIG. 9e is a schematic diagram illustrating the read address counter sub-logic of the read logic illustrated generally in FIG. 4; FIGs. 9f through 91 inclusive are schematic diagrams illustrating the details of the read control sub-logic of the read logic illustrated generally in FIG. 4; FIGs. 10a through lOd inclusive are schematic diagrams illustrating the details of the read/write mux illustrated generally in FIG. 4; FIG. 11 is a schematic diagram illustrating the details of the column clock logic illustrated generally in FIG. 4; FIGs. 12a and 12b are schematic diagrams illustrating the details of the row driver data/clock logic illustrated generally in FIG. 4; FIG. 13 is a schematic diagram illustrating the details of the ramp power supply control logic illustrated generally in FIG. 4; FIG. 14 is a schematic diagram illustrating the details of the reset logic illustrated generally in FIG. 4; FIGs. 15a and 15b are timing diagrams illustrating the relative timing of the signals input to the video display interface; and FIGs. 16a through 16c inclusive are timing diagrams illustrating the relative timing of the signals output by the preferred video display interface. DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENT Referring to the drawing, FIG. 1 illustrates a video display interface (VDI) 10 which represents a presently preferred embodiment of the invention. The VDI 10 is shown in an exemplary arrangement with a digital computer 20, video memory banks 30 (A) and 40 (B), a video display 50, display column and row drivers 60 and 70 respectively, a high voltage power supply 80, a watchdog RC timer 90, and a power-on reset RC timer 100. In its preferred form, the VDI 10 is embodied in an integrated circuit chip which may be suitably fabricated with conventional two micron CMOS technology using conventional programmable logic array technology available from Siliconix, Inc., Seiko, and numerous other vendors. In the preferred chip form, the VDI 10 may be mounted, together with the external memory, driver, and power supply components illustrated in FIG. 1, on one or more conventional printed circuit boards (not shown) which may in turn be mounted in computer 20 or integrally with display 50, for example. The- preferred VDI 10 is connected to the computer 20 by two video data channels 12 and 14, a clock line 16, and sixteen (16) program and control lines 18, which are described in detail below. It is understood that any suitable source of digital video data, clock, and control signals can be substituted for computer 20 as desired. The preferred VDI 10 is con¬ nected to the two video memory banks A and B respec¬ tively by means of conventional data 32, 42, address 34, 44, and control 36, 46 busses. The VDI 10 is connected to the high voltage power supply 80 by means of two (2) power control lines 82. The VDI 10 is connected to the display column drivers 60 by means of ten (10) parallel data lines 62, two (2) clock lines 64, and four (4) control lines; and to the display row drivers 70 by a data line 72 and a clock line 74. The preferred VDI 10 is also connected to the power-on reset timer 100 by a line 102 and to the watchdog RC timer 90 by a line 92. The VDI 10 of the invention is particularly suited for use with flat panel D.C. electroluminescent displays and display drivers capable of delivering pre- charge and constant current drive signals as described above. The co-pending United States Patent Application Serial No. 934,958 identified above contains a detailed description of certain column and row drivers having this capability and specifically arranged to drive a 640 column by 200 row electroluminescent or similar display. That description is incorporated herein by reference. The preferred embodiment of the VDI 10 is specifically adapted for use with those drivers and with a display having those dimensions. Accordingly, the description thereof is incorporated herein by reference. It is understood, however, that the inven¬ tion is not limited by the particular preferred dimen- sions of the display or by the particular design or arrangement of the drivers. Each of the video memory banks A and B, 30 and 40 respectively, consists of two 256K-bit dynamic random access memories (DRAM's) each being arranged as 64K 4-bit wide words. The DRAM's in each bank are connected in parallel to provide a total of 64K 8-bit wide words of video data storage in each bank. Each word is identified and accessed by a unique row and column address. Fujitsu MB81464 DRAM's and equivalents thereof have been found to provide suitable performance at a reasonably low cost and are therefore preferred. The high voltage power supply 80 may be any conventional D.C. power supply capable of delivering sufficient voltage and current to drive the display 50. Preferably, although not necessarily, the supply 80 will have some form of output regulation. The exact output requirements of the supply 80 are dependent upon the specifications of the particular panel selected for use. This information is readily available from the manufacturers of such panels. The power-on reset RC timer 100 consists of a series resistor R2 and capacitor C2 connected between the VDI supply voltage Vcc and ground. The supply voltage Vcc is approximately 5 volts. The power-on reset timer 100 generates a low power-on reset signal POR at the junction of the series resistor R2 and capacitor C2 which is conducted by line 102 to the VDI 10 and which preferably holds the VDI 10 reset on power-up for approximately 1.5 milleseconds to ensure that all memory is reset and all logic is in a known state. When the voltage across the capacitor C2 reaches about 1.25 volts, the reset condition is lifted and the VDI logic begins operating. The watchdog RC timer 90 also consists of a series resistor Rl and capacitor Cl connected between the supply voltage Vcc and ground. The watchdog timer 90 generates a high reset signal WDRC at the junction of the resistor Rl and capacitor Cl which is conducted to the VDI 10 by line 92 and which causes the VDI 10 to ramp down the high voltage power supply 80 and disable the column drivers 60 in order to protect the display 50 in the event * the computer 20 fails to transmit a horizontal sync signal HDEN within a predetermined time period of approximately 4-7 milleseconds. Both the HDEN signal and the operation of VDI 10 in response to the watchdog timer 90 are described in detail below. At some time following .power-up, the computer 20 outputs a digital -clock signal DOTCLK on the clock line 16, digital video data signals VIDEOA and VIDEOB on one or both of the video channels 12 and 14, and horizontal and vertical sync signals HDEN and VDEN respectively on two of the program and control lines 18. The DOTCLK signal preferably has a nominal fre- guency of approximately 14.3 MHz, although a frequency in the range of 13.1 to 16.0 Mhz is acceptable, a duty cycle of approximately fifty (50) percent, and a nominal period of approximately 70 nanoseconds. The VIDEOA and VIDEOB signals are bit-serial signals with each bit corresponding to a pixel of the display 50 and the state of each bit representing the on or off state of the corresponding pixel. In the preferred embodiment, a zero or low bit corresponds to the off state and a one or high bit corresponds to the on state. The VIDEOA and VIDEOB signals are preferably synchronized with the DOTCLK signal so that each rising edge of the DOTCLK signal clocks one bit of the VIDEOB and/or VIDEOA signals into the VDI 10. The video data bits of the VIDEOA and VIDEOB signals are ordered beginning with the bit corresponding to the pixel in the uppermost row and leftmost column of the display 50, then proceeding left to right across the columns and down the rows of the display. The computer 20 outputs one horizontal sync signal HDEN per line of video data it outputs, i.e., one cycle of the HDEN signal for each group of 640 bits of video data. The HDEN signal goes high approximately 20 nanoseconds prior to the first DOTCLK of the group and goes low approximately 50 nanoseconds after the last DOTCLK of the group goes high. The HDEN signal has an approximate high time of 44.8 microseconds and an approximate low time of 18.8 microseconds for a total period of approximately 63.6 microseconds. The computer 20 outputs one vertical sync signal VDEN for each frame of video data it outputs. In the preferred embodiment, an input frame of video data is defined as 200 rows of 640 bits each. Accordingly, one cycle of the VDEN signal corresponds to 200 cycles of HDEN. The VDEN signal goes high approximately 20 nanoseconds prior to the first HDEN signal of a frame and goes low approximately 50 nanoseconds after the last HDEN signal of a frame. The VDEN signal has an approximate high time of 12.6 milleseconds and an approximate low time of 4 milleseconds for a total period of approximately 16.67 milleseconds. The computer 20 also generates other control and program signals on the control and program lines 18 that control certain functions and operations of the preferred VDI 10 and which are described in detail below. One such control signal VIDSEL selects whether the preferred VDI 10 is to operate in single or dual video mode. In the single video mode, the VDI 10 operates on a full speed clock signal DOTCLK in the range identified above and accepts only the VIDEOA signal, which is transmitted by the computer 20 at a data rate of one bit per clock on video channel 12. In the dual video mode, the VDI 10 operates on a half speed DOTCLK signal in the range of 6.55 to 8.0 MHz and accepts both VIDEOA and VIDEOB signals simultaneously on video channels 12 and 14. Both the VIDEOA and VIDEOB signals are transmitted at a data rate of one bit per clock. In the single video mode, the VIDEOA signal contains both the even and the odd display column data bits. In the dual video mode, the VIDEOA signal contains only the even display column data bits and the VIDEOB signal contains only the odd display column bits. The ability of the preferred VDI 10 to operate in either single or dual video mode allows it to accomodate computers 20 having a variety of output designs and specifications. The horizontal and vertical sync signals HDEN and VDEN are not affected by changes in the video mode. Regardless of whether the VDI 10 operates in single or dual video mode, it receives and stores the bit-serial video data in one of the memory banks A or B at a maximum frame rate of approximately 60 Hz which corresponds to the 16.67 millesecond nominal period of the vertical sync VDEN. The computer 20 completes the transmission of an entire frame of video data to the VDI 10 during the time that VDEN is high. However, as will become apparent below, the VDI 10 uses the entire VDEN time period to read and output stored video data to the display drivers 60 and 70 at a desirably higher frame output rate which is preferably an integer multiple of the input frame rate. The VDI 10 utilizes the memory banks A and B as a double-buffer, double-frame video memory. In the preferred embodiment, each memory bank stores one frame of video data. During the time interval that the pre¬ ferred VDI 10 receives and stores one input frame of video data into one memory bank, i.e., one write cycle, it simultaneously performs four cycles of reading an output frame of stored video data out of the other memory bank and sending it to the column drivers 60, i.e., four read cycles. Thus, the preferred VDI 10 receives video data at a first frame rate of approx¬ imately 60 Hz and outputs video data to the display at a desirable higher frame rate of approximately 240 Hz. It should be apparent that in other embodiments, the VDI 10 could be adapted to perform more or fewer read cycles per write cycle in order to increase or decrease the video output rate with respect to the preferred rate. When the VDI 10 finishes a write cycle on one of the memory banks, it switches banks and begins a write cycle on the other bank. Simultaneously, it performs four read cycles on the other memory bank as described above. In order to provide the increased frame output rate described above, the preferred VDI 10 employs a unique memory bit mapping scheme. Referring to FIG. 2, the preferred VDI 10 logically divides the display 50 into ten (10) equal vertical sections (A-J) each being 64 columns or bits wide. During a write cycle, the preferred VDI 10 stores the received video data in memory as 8-bit parallel words according to a memory map 120 that has ten sections 122-140, each section corresponding to one of the logical screen sections A-J as illustrated. The memory map 120 illustrated corresponds to one row of video data and is repeated for each of the 200 rows comprising a complete frame. During a read cycle, the VDI 10 reads a selected number of bits from each memory section 122-140, and generates a parallel output word having one bit corresponding to each logical screen section. The VDI 10 sends this word to the column drivers 60 which in turn drive each of the sections A-J of the screen simultaneously. By filling up ten screen sections simultaneously, the time necessary to output an entire frame of data is reduced significantly, thus allowing the VDI 10 to complete four read cycles in each VDEN period. Many other logical display divisions and corresponding memory maps are also possible. However, the ten section division and corresponding memory map described above correspond to the arrangement of the preferred column drivers 60 disclosed in the co-pending application identified and incorporated above and are preferred for that reason. The application discloses an arrangement of the column drivers into two sets of ten drivers each, with each driver having circuitry to drive 32 display columns. One group of ten drivers drives the odd columns of each display section A-J and the other drives the even columns. The disclosed ten section division and corresponding map enable the VDI 10 to alternately provide video output data simulta¬ neously to each of the drivers in one group, then the other, to alternately drive an odd column in each section A-J of the display simultaneously, then an even column in each section simultaneously. There are a number of alternative ways to implement the preferred memory map 120. One way, for example, is to have separate memories for each section 122-140 of the map 120 and to write into the memories sequentially and read out of them in parallel. How¬ ever, this implementation requires the use of a relatively large number of memory chips for each memory bank 30, 40, which increases cost. In order to mini¬ mize the number of memory chips required per memory bank and the attendant cost, the preferred VDI 10 writes the received video data into each section of the memory map 120 and reads the stored video data out of each section of the memory map 120 in a unique manner. As a result, only two memory chips of the preferred type (per memory bank) and a double-buffered 4 x 10 output shift register are required to implement the preferred ten section display division. Referring to FIGs. 2 and 3, during each write cycle, the VDI 10 exchanges the upper and lower four bits of the 8-bit words written into successive map sections. For example, the VDI 10 sequentially writes the first group of eight 8-bit words into the first section 122 of the map 120 with the upper and lower four bits of each word in its normal position. The VDI 10 writes the second group of eight 8-bit words sequentially into the next section 124 of the map 120 with the upper and lower four bits of each word exchanged. The next group of eight words is written sequentially into the third section 126 with the upper and lower four bits of each word in the normal position, and so on until all of the map sections are filled with a complete row of video data. Next, a new row is selected and the map 120 for that row is filled in the same manner. This procedure is repeated until an entire frame of 200 rows of video data is written into memory. During a subsequent read cycle, the VDI 10 reads video data out of memory in 8-bit words according to the memory map 120 for each row. The VDI 10 initially reads each word in such a way that the upper four bits of the word are comprised of the lower four bits of a word in one map section, and the lower four bits thereof are comprised of the upper four bits of the corresponding word in the next successive map section. For example, on the first memory read of the cycle, the VDI 10 reads an 8-bit word, the upper four bits of which are bits 0-3 from the first word (COL. 0) in the first map section 122, and the lower four bits of which are bits 64-67 from the first word (COL. 8) in the second map section 124. On the second read of the cycle, the VDI 10 reads bits 128-131 from the first word (COL. 16) of the third map section 126 and bits 192-195 from the first word (COL. 24) of the fourth map section 128. The VDI 10 continues reading from memory in this fashion until it has read four bits from each map section, i.e., for five memory reads. Thus, the last word read is comprised of bits 512-515 from the first word (COL. 64) of map section 138 and bits 576-579 from the first word (COL. 72) of map section 140. The VDI 10 stores the five words read from memory in the described manner in a 4 x 10 shift register 150. Each 4-bit wide section 152-170 of the shift register 150 corresponds to one of the logical display sections A-J and contains the first four consecutive bits of video data for one row of such section. On the next set of five memory reads, the VDI 10 reads the lower four bits of each word from the upper four bits of a word in one map section and the upper four bits from the lower four bits of the corre- sponding word in the next successive map section. The VDI then exchanges the upper and lower four bits of the word before storing it in a second 4 x 10 shift register 180. For example, on the sixth memory read the VDI 10 reads bits 4-7 of the first word (COL. 0) of the first map section 122 as the low order four bits and bits 68-71 of the first word (COL. 8) of the second map section 124 as the high order four bits. The VDI 10 exchanges the upper and lower four bits so that when the word is stored in the second shift register, bits 4-7 are the upper four bits and bits 68-71 are the lower four bits. The VDI 10 continues reading from memory in this fashion until the next four consecutive video data bits are read from each, of the ten map ■ sections 122-140 and stored in each of the corresponding ten sections 182-199 of the second shift register 180. Thus, each of the ten sections 182-199 of the second shift register 180 contains the next four successive bits for one row of video data for each of the ten logical display sections A-J. Next, the VDI 10 begins reading from the second word (COL. 1) of the first map section 122 and storing the words in the first shift register 150 in the manner described above, and so on for the third word of each section until all eight words from each section are read. During the time that the VDI 10 is reading from memory into one of the shift registers 150, the other register 180 is alternately shifting out the video data from the previous five memory reads to one and then the other of the two groups of column drivers 60 in 10-bit parallel words. Each bit of the 10-bit word corresponds to one of the ten logical dis¬ play sections A-J so that one row of the display 50 is filled in ten sections simultaneously. After a shift register 180 has shifted out all four consecutive bits corresponding to each of the display sections A-J, the VDI 10 switches registers and continues reading data into the first register 180 while the second register 150 shifts out the next consecutive four bits of data to each of the display sections A-J. The above-descibed cycle of reading from the memory map 120, and alternately storing and shifting the video data out of the shift registers 150, 180 to the drivers 60 to simultaneously fill each of the ten display sections A-J is repeated for each 640-bit line of video data until an entire frame of video data is read out of memory and output to the drivers 60. The VDI logic associated with this function is then reset and a new read cycle starts with the same frame of video data being read from the same memory bank. As previously described, four such read cycles are performed during each VDEN period to provide a frame output rate of 240 Hz. FIG. 4 illustrates a detailed functional block diagram of the preferred VDI 10. The preferred VDI 10 is comprised of read logic 200, write logic 220, a read/write MUX 240, program logic 250, video delay logic 260, reverse clock and internal clock logic 262 and 264, column clock logic 266, row driver data/clock logic 268, ramp power supply control logic 270, and reset logic 272. The read logic 200 is further com¬ prised of read control sub-logic 210, read address counter sub-logic 212, and memory read sub-logic 214. The write logic 220 Is further comprised of video input sub-logic 230, write -address counter sub-logic 232, and write control sub-logic 234. The program logic is further comprised of line width program sub-logic 252, pre-charge time select sub-logic 254, and constant current time select sub-logic 256. VIDEO DELAY LOGIC The video delay logic 260 provides a con¬ trolled delay or advance of the video data signals VIDEOA and VIDEOB relative to the horizontal video sync signal HDEN. The video delay logic 260 receives the VIDEOA and VIDEOB signals together with delay control signals VIDDLO and VIDDL1, and the sync signals HDEN and VDEN from the computer 20. The video delay logic 260 also receives clock signals DCLK1 and MHZ8 from the internal clock logic 264. The video delay logic 260 in turn generates video data signals VIDA and VIDB which are the VIDEOA and VIDEOB signals respectively advanced or delayed by one cycle of the DCLK1 signal relative to the HDEN signal depending upon the states of the VIDDLO and VIDDL1 signals. In the preferred embodiment, when VIDDLO and VIDDL1 are both low or both high, the video delay logic 260 does not shift the VIDEOA or VIDEOB signals. When VIDDLO is low and VIDDL1 is high, the video delay logic 260 delays VIDEOA and VIDEOB by one clock cycle with respect to HDEN. When VIDDLO is high and VIDDL1 is low, the video delay logic 260 advances VIDEOA and VIDEOB by one clock cycle with respect to HDEN. The one clock cycle shift control is useful for ensuring that the VDI 10 receives the first or last bit of each frame of video data if the sync, clock, and data signals output by the computer 20 are misaligned. The video delay logic 260 can compensate for signal misalignment of up to one clock cycle in either direction. The video delay logic 260 also generates a delayed horizontal sync signal HDEN8 which is the HDEN signal with the trailing edge delayed by eight (8) cycles of the MHZ8 clock signal. Delaying the trailing edge of the HDEN signal by eight clock cycles ensures that the last eight bits of video data for each 640 bit line are written into memory before the VDI logic is reset to receive the next line of data. The delay is necessary because as will be seen, eight clock cycles are required to convert eight bits of serial data into an 8-bit word. Thus, there is a delay of eight clock cycles before each word is written into memory. The video delay logic 260 also generates two reset signals VDENRS and LWPCLR which are used by the VDI 10 internally. The VDENRS signal is a two MHZ8 clock pulse wide negative-going reset signal that goes low simultaneously with the rising edge of the VDEN vertical sync signal at the beginning of each frame and goes high on the rising edge of the second MHZ8 clock signal occurring thereafter. The VDENRS signal pre¬ loads the line width program sub-logic 252 with a predetermined count value as described in detail below, and resets the row driver data/clock logic 268, the read control sub-logic 210, and the write address counter at the beginning of each new frame of data. The LWPCLR signal is a one MHZ8 clock pulse wide nega¬ tive going reset signal that goes low simultaneously with the rising edge of the VDEN signal and goes high on the rising edge of the first MHZ8 clock signal occurring thereafter. The LWPCLR signal resets the line width program sub-logic 252 at the beginning of each new frame. FIGs. 5a through 5c inclusive illustrate the details of the video delay logic 260. Referring to FIG. 5a, the video delay logic 260 includes D-latches 300 and 302, 8-bit shift register 304, AND gate 306, and OR gate 308. The latches 300 and 302 are clocked by the DCLK1 clock signal and reset by the POR signal. The shift register is clocked by the MHZ8 clock signal and reset by the POR signal. HDEN and VDEN are gated by the AND gate 306 in order to ensure that the HDEN signal is occurring during a valid frame period. The latches 300 and 302 clock the HDEN signal through to the shift register 304 delayed by two DCLK1 cycles. The output HDEN8 of the OR gate 308 goes high with the rising edge of the HDEN signal and the shift register ■ 304 prevents the output of the OR gate 308 from going low for eight clock cycles following the trailing edge of the HDEN signal. FIG. 15a is a timing diagram which illustrates the relative timing of the HDEN and HDEN8 signals. Referring to FIG. 5c, video delay logic 260 also includes D-latches 310 and 314, and NAND gates 316 and 318. .D-latches 310 and 314 are clocked by the MHZ8 signal and reset by the POR signal. D-latches 310 and 314 and NAND gate 316 cooperate to cause the VDENRS signal at the output of NAND gate 316 to go low for two MHZ8 clock cycles on the rising edge of the VDEN signal and then to return high. D-latch 310 and NAND gate 318 cooperate to cause the LWPCLR signal at the output of the NAND gate 318 to go low for one MHZ8 clock cycle on the rising edge of the VDEN signal and then to return high. FIG. 15b is a timing diagram which illustrates the relative timing of the VDEN, VDENRS, and LWPCLR signals. Referring to FIG. 5b, video delay logic 260 further includes a first set of series D-latches 320, 322, and 324, and a second set of series D-latches 326, 328, and 330. The first .set of series latches has the VIDEOA signal as a data input. The second set of series latches has the VIDEOB signal as a data input. All. of the latches are clocked by the DCLK1 signal. Associated with series latches 320, 322, and 324 are NOR gates 332, 334, 336, and 338. The VIDA signal appears at the output of NOR gate 338. Associated with series latches 326, 328, and 330 are NOR gates 340, 342, 344, and 346. The VIDB signal appears at the output of NOR gate 346. A set of NAND gates 348, 350, and 352, and an exclusive OR gate 354 cooperate with NOR gates 332, 334, 336, and 338 to decode the VIDDLO and VIDDLl signals such that the VIDA signal is delayed by one, two, or three DCLKl cycles relative to the VIDEOA signal depending on the states of VIDDLO and VIDDLl. Likewise, the NOR gates 340, 342, 344, and 346 cooperate with the NAND gates 348, 350, and 352, and the exclusive OR gate 354 so that the VIDB signal is delayed by one, two, or three DCLKl cycles relative to the VIDEOB signal depending on the states of VIDDLO and VIDDLl. The VIDDLO and VIDDLl signals are decoded so that when both are low or both high, the VIDEOA and VIDEOB signals are delayed by two clock cycles. When VIDDLO Is low and VIDDLl is high, the VIDA and VIDB signals are delayed by three clock cycles. When VIDDLO is high and VIDDLl is low, the VIDA and VIDB signals are delayed by one clock cycle. Since, as illustrated in FIGs. 5a and 5c, the HDEN signal is always delayed by two DCLKl cycles, delaying the VIDA and VIDB signals by one clock cycle provides a relative advance of one cycle, delaying them by two clocks provides no delay or advance, and delaying them by three clock cycles provides a relative delay of one clock cycle. REVERSE CLOCK LOGIC Referring again to FIG. 4, the reverse clock logic 262 provides controlled alteration of the phase of the clock signal DOTCLK internally to the VDI 10 to compensate for misalignment of the DOTCLK signal and the video data signals VIDEOA and VIDEOB in order to ensure proper detection of the video data bits by the VDI 10. The reverse clock logic 262 receives the clock signal DOTCLK and a clock phase control signal SELCLK from the computer 20. A low SELCLK signal causes the reverse clock logic 262 to alter the phase of the 5 DOTCLK signal internally to the VDI 10 by 180 degrees. A high SELCLK signal disables the reverse clock logic from altering the phase of the DOTCLK signal. The reverse clock logic 262 outputs a clock signal DCLKl which corresponds to the DOTCLK signal with or without ' 10 phase alteration depending upon the state of the SELCLK signal. The reverse clock logic 262 outputs the DCLKl signal to the internal clock logic 264, the video input sub-logic 230, and the video delay logic 260. FIG. 6a illustrates the details of the reverse 15 clock logic 262. The reverse clock logic 262 is simply comprised of an exclusive OR gate 360 and an inverter 362 which cooperate to invert the DOTCLK signal when the SELCLK signal is low and to pass the DOTCLK signal unchanged when the SELCLK signal is high. The DCLKl 20 signal appears at the output of the exclusive OR gate 360. INTERNAL CLOCK LOGIC As illustrated in FIG. 4, the internal clock logic 264 derives various clock and clock decode 25 signals used internally by the other logic blocks of the VDI 10 from the single clock signal provided by the computer 20. The internal clock logic 264 receives the video mode select signal VIDSEL and the vertical sync signal VDEN from the computer 20, the DCLKl clock 30 signal from the reverse clock logic 262, and the delayed horizontal sync signal HDEN8 from the video delay logic 260. The internal clock logic 264 generates a MHZ8 clock signal which it outputs to the video delay logic 260. The MHZ8 signal is the same as the DCLKl signal or is the DCLKl signal divided by two depending upon the state of the VIDSEL signal. A low VIDSEL signal selects the undivided DCLKl signal. The Internal clock logic also generates a MHZ16 clock signal which it outputs to all three sub-logic blocks of the program logic 250, to the write control sub-logic 234 of the write logic 220, to the read control sub-logic 210 of the read logic 200, to the row driver data/clock logic 268, and to the ramp power supply control logic 270. The MHZ16 clock signal is the MHZ8 clock signal multiplied by two. The internal clock logic 264 also generates an X2DIV3 clock signal which it outputs to the read control sub-logic 210 of the read logic 200. The X2DIV3 clock is the MHZ8 clock signal multiplied by two and divided by three. In addition, the internal clock logic 264 outputs an X2DIV6 clock signal to the write address counter sub-logic 232 and the write control sub-logic 234 of the write logic 220. The X2DIV6 clock signal is the X2DIV3 clock signal divided by two. The internal clock logic 264 also outputs TFRAME and EFRAME clock signals to the read/write MUX 240 for switching between memory banks A and B on alternate frames. The TFRAME signal is the VDEN vertical sync signal divided by two. FFRAME is the inverse of TFRAME. Additionally, the internal clock logic 264 generates clock decode signals DEC2, DEC3, DEC10, DEC16, DEC38, DEC45, DEC60, and DEC61 which are positive-going one MHZ16 clock wide pulses decoded from the MHZ16 clock signal. The internal clock logic 264 outputs the DEC60 signal to the pre-charge time select sub-logic 254 and the constant current time select sub-logic 256 of the program logic 250, the DEC2 signal to the row driver data/clock logic 268, and the DEC3, DEC10, DEC16, DEC38, and DEC45 signals to the ramp power supply control logic 270. FIGs. 6b through 6f illustrate the details of the internal clock logic 264. Referring to FIG. 6b, the internal clock logic 264 includes a D-latch 364 connected in a divide-by-two configuration. The D-latch 364 is clocked by the DCLKl signal and reset by the POR signal. The DCLKl signal divided by two appears at the output of the D-latch 364. The DCLKl signal and the Q output of the D-latch 364 are gated by the AND gates 366 and 368 respectively depending ' -on the state of the VIDSEL signal. A high VIDSEL signal gates the 0 output of the D-latch 364 through the AND gate 368 to the output of the OR gate 370. A low VIDSEL signal gates the DCLKl signal through the AND gate 366 to the output of the OR gate 370. The signal at the output of the OR gate 370 is the MHZ8 signal. Referring to FIG. 6c, the internal clock logic 264 includes a D-latch 374 arranged in a divide- by-two configuration. The D-latch 374 is clocked by the VDEN signal and reset by the POR signal. The signal appearing at the output of the latch 364 is the TFRAME signal and the signal appearing at the / output is the FFRAME signal. Referring to FIG. 6e, the internal clock logic 264 includes a D-latch 380 having its data input tied to Vcc. The D-latch 380 is clocked by the MHZ8 signal and reset by POR. The high signal appearing at the output of the D-latch 380 after it is clocked by the MHZ8 signal is input with the MHZ8 signal to a delay line comprised of series D-latches 386, 388, and 390 through NAND gate 382 and inverter 384. The output of the delay line, which appears at the Q output of latch 390, is exclusive OR' d with the non-delayed signal output by inverter 384. The signal appearing at the output of the inverter 404 has twice the frequency of the MHZ8 signal and is designated the MHZ16 clock signal. The internal clock logic also includes D-latches 406, 408, and 410, NOR gates 412, 414, 416, and 418, and inverter 420. The latches 406 and 408 are clocked by the MHZ16 signal. The latch 410 is clocked by the MHZ16 signal inverted by the inverter 420. All of the latches 406, 408, and 410 are reset by the POR signal. The latches 406, 408, and 410 cooperate with NOR gates 412, 414, 416, and 418 to produce a signal at the output of the NOR gate 416 which has a frequency one third the frequency of the MHZ16 signal. The signal is designated the X2DIV3 clock signal. Referring to FIG. 6f, the internal clock logic 264 also includes a D-latch 424 and AND gate 425. The D-latch 424 is connected in a divide-by-two configuration and is clocked by the X2DIV3 clock signal. The output of the AND gate 426 resets the D-latch 424 when POR goes low and at the end of each line of video data received by the VDI 10 on the falling edge of the HDEN8 signal. The signal X2DIV6 appearing at the Q output of the D-latch 424 has half the frequency of the X2DIV3 signal and one sixth the frequency of the MHZ16 signal. The /X2DIV6 signal at the / output is the inverse of the X2DIV6 signal. Referring to FIG. 6d, the internal clock logic 264 includes clock decoder logic 430 comprised of counters 432 and 434, NAND gates 435 to 446 inclusive, numbered consecutively from left to right, NOR gates 447 to 454 inclusive, numbered consecutively from left to right, an 8-channel latch 456, Inverters 458, 460, 462, 464, 466, 468, and 470, and AND gate 472. The counters 432 and 434, which are connected to form a 6-bit counter, are clocked by rising edges of the MHZ16 clock signal appearing at the output of the AND gate 472. The counters 432 and 434 are reset by the ANYCLR signal at the end of each line, at the beginning of each frame, and at the end of every fourth frame of video data received. The inverters 458, 460, 462, 464, 466, and 468, NAND gates 435-446, and NOR gates 447-454 decode the counter outputs. The outputs of each of the NOR gates 447-454 is a one clock cycle wide positive-going pulse that occurs on a leading edge of the MHZ16 signal. The pulse output by the NOR gate 447 occurs on the second rising edge of the MHZ16 signal following reset. The pulse output by the NOR gate 448 occurs on the third rising edge. The pulse output by the NOR gate 449 occurs on the tenth rising edge. The pulse output by the NOR gate 450 occurs on the sixteenth rising edge. The pulse output by the NOR gate 451 occurs on the thirty-eighth rising edge. The pulse output by the NOR gate 452 occurs on the forty-fifth rising edge. The pulse output by the NOR gate 453 occurs on the sixtieth rising edge. The - pulse output by the NOR gate 454 occurs on the sixty- first rising edge. Each of the decoded clock pulses is latched by the 8-channel latch 456 on the rising edge of the MHZ16 signal. The latch 456 is cleared by the ANYCLR signal. The 8Q through 1Q outputs of the latch 456 correspond to the outputs of the NOR gates 447-454 respectively and the signals appearing at the latch outputs 8Q through 1Q are respectively designated the DEC2, DEC3, DEC10, DEC16, DEC38, DEC45, DEC60, and DEC61 clock decode signals. The output of the inverter 470 disables the MHZ16 clock from further clocking the counters 432, 434 or latch 456 after the DEC61 signal is latched. WRITE LOGIC VIDEO INPUT SUB-LOGIC Referring again to FIG. 4, the write logic 220 consists of video input sub-logic 230, write address counter sub-logic 232, and write control sub-logic 234. The video input sub-logic 230 receives the bit-serial video data signals VIDA and VIDB and the HDEN8 signal from the video delay logic 260, the VIDSEL signal from the computer 20, and the DCLKl clock signal from the reverse clock logic 264. The state of the VIDSEL signal determines whether the video input sub- logic 230 operates in single or dual video mode. In single video mode, the video input sub-logic 230 receives bit-serial video data from the VIDA signal at the rate of one bit per DCLKl cycle. In dual video mode, It receives video data serially in two-bit parallel from the VIDA and VIDB signals at the rate of two bits per DCLKl cycle. The video input sub-logic 230 converts the bit serial video data into 8-bit parallel words and exchanges the upper and lower four bits of the words stored in every other memory map section 124, 128, 132, 136, and 140 as described above. The video input sub-logic 230 outputs each parallel word in duplicate to the read/write MUX 240. The duplicate parallel words are identified in FIG. 4 as D0A-D7A, which corresponds to video memory bank A, and D0B-D7B, which corresponds to video memory bank B. FIGs. 8a and 8b illustrate the details of the video input sub-logic 230. The video input sub-logic 230 comprises two 8-channel 2 into 1 MUX' s 430 and 434, two 8-channel D-latches 432 and 436, and an inverter 438. The first MUX 430 receives the VIDA signal on channels 1A and 2B and the VIDB signal on channel IB. MUX 430 channel A or B is selected by the inverted VIDSEL signal. A low VIDSEL signal is inverted by inverter 438 and selects channel B which corresponds to dual video mode. A high VIDSEL signal is inverted by inverter 438 and selects channel A which correponds to single video mode. The MUX 430 and latch 432 are connected in a feedback arrangement such that the two together function as a serial-in-parallel-out shift register. The MUX 430 receives as an input either one or two serial bits of video data per DCLKl cycle depending on the state of the VIDSEL signal and the latch 432 outputs an 8-bit parallel word at its 10-8 ■ outputs. The outputs 1Q-8Q of the latch 432 are connected directly to the 1A-8A inputs of ' the MUX.434. The 1 -40 outputs of the latch 432 are also connected to the 5B-8B inputs of the MUX 434 and the 5Q-80 out- puts of the latch 432 are also connected to the 1B-4B inputs of the MUX 434. The A or B channel of the MUX 434 is selected by a FLIP signal. When FLIP is low, channel A is selected and the upper and lower four bits of the- 8-bit word pass through the MUX unchanged. However, when FLIP is high, channel B is selected and the upper and lower four bits of the word are exchanged at the output of the MUX 434. The output of the MUX 434 is connected to the input of the latch 436. When the latch 436 is clocked by the rising edge of a LATCH signal, the 8-bit word on its input is latched into the read/write MUX 240 as duplicate data words DA0-DA7/ DB0-DB7 to be written into memory in accordance with the memory map 120 described above. FIG. 8b illustrates the details of the section of the video input sub-logic circuitry that generates the FLIP and LATCH signals. This section includes two 4-bit binary counters 440 and 442 connected as an 8-bit counter, NAND gates 444, 446, 448, 450, 452, and 454, D-latches 456 and 458, inverter 460, and AND gate 462. The counters are clocked by rising edges of the DCLKl signal and are reset by a low output from the AND gate 462 on power-up and after each line of video data is received when HDEN8 goes low. The NAND gates 444, 446, and 448 decode the outputs of the counter 440 to provide a LATCH signal. The LATCH signal, which appears at the / output of the D-latch 456, goes high every fourth rising edge of DCLKl when VIDSEL is low (dual video mode) and every eighth rising edge of DCLKl when VIDSEL is high (single video mode). Thus, regardless of the video mode selected, the LATCH signal goes high to clock the D-latch 436 once for every eight bits of video data received. The NAND gates 450, 452, and 454 decode the outputs of the counter 442 to provide a FLIP signal. The FLIP signal, which appears at the Q output of the latch 458, goes high on every thirty-second rising edge of DCLKl when VIDSEL is low, and every sixty-fourth rising edge of DCLKl when VIDSEL is high. Thus, regardless of the video mode selected, the FLIP signal changes state every 64 bits of video data and changes the selected channel of MUX 434 to cause the upper and lower four bits of the 8-bit words written into every other map section to be exchanged as described above. WRITE ADDRESS COUNTER SUB-LOGIC Referring to FIG. 4, the write address counter sub-logic 232 generates the column and row addresses required to store the video data words D0A-D7A/ D0B-D7B in the video memory banks 30, 40 according to the memory map 120. The write address counter sub-logic 232 also generates row addresses used to refresh the preferred memory ' chips. The write address counter sub-logic 232 receives as inputs the X2DIV6 clock signal from the internal clock logic and the HDEN8 and VDENRS horizontal sync and frame reset signals from the video delay logic 260. The write address counter sub-logic 232 also receives an R/C row/column address select signal from the write control sub-logic 234. The write address counter sub-logic 232 outputs an 8-bit parallel address word ADD0A-ADD7A to the read/write MUX 240. The state of. the R/C signal determines whether the word ADD0A-ADD7A is a row or a column address. When the R/C signal goes high, the write address counter 232 outputs a row address. When the R/C signal goes low, the write address counter 232 outputs a column address. The R/C signal also acts as a clock signal to increment the column address generated by the address counter sub-logic 232. The HDEN8 horizontal sync signal acts as both a reset signal and a clock signal to the write address counter sub-logic 232. When HDEN8 goes low after each line of video data is received, it resets the column address and simultaneously acts as a clock to increment the row address generated by the write address sub-logic 232. When HDEN8 is low, it also causes the write address counter sub-logic 232 to output row addresses and to increment them at the rate of the X2DIV6 clock signal in order to refresh the preferred memory chips. The falling edge of the VDENRS signal resets the row and refresh row addresses generated by the address counter sub-logic 232 at the beginning of each frame. FIG. 8d illustrates the details of the write address counter sub-logic 232. The write address counter sub-logic 232 includes a column address counter 465 comprised of two 4-bit counters 468 and 470 connected as an 8-bit counter, a row address counter 475 comprised of two 4-bit counters 478 and 480 connected as an 8-bit counter, and a row address refresh counter 485 comprised of two 4-bit counters 486 and 488 connected as an 8-bit counter. The column address counters 468 and 470 are clocked by rising edges of the R/C signal and are reset by a low output from an AND gate 490 on power-up and after each line of video data on the falling edge of HDEN8. The row address counters 478 and 480 are clocked by the output of the inverter 500 at the end of each line of video data on the falling edge of the HDEN8 signal. The row address refresh counters 486 and 488 are clocked on rising edges of the X2DIV6 signal by the output of an AND gate 492. A D-latch 494 disables the output of the AND gate 492 from going high and clocking the counters 486 and 488 for one complete cycle of the X2DIV6 clock signal after the HDEN8 signal goes low. This is done in order to prevent the occurrence of a very short clock pulse after HDEN8 goes low which could be missed and result in the refreshing of the same row address twice and the consequent failure to refresh a subsequent row address. The write address counter sub-logic 232 also includes two 8-channel 2 into 1 MUX's 496 and 498. The MUX 496 selects either the output of the column address counter 465 or the row address counter 475 depending on the state of the R/C signal. A low R/C signal selects the output of the column address counter 465 and a high R/C signal selects the output of the row address counter 475. The MUX 498 selects either the counter output selected by the MUX 496 or the row refesh address counter 485 output depending on the state of the inverted HDEN8 signal generated by an inverter 500. When HDEN8 is high and video data is being received by the VDI 10, the row or column address counter output selected by the MUX 496 is selected and the address word ADD0A-ADD7A corresponds to either the current row or column address. When HDEN8 is low, the output of the row refresh address counter 485 is selected and the address word ADD0A-ADD7A corresponds to the row refresh address. WRITE CONTROL SUB-LOGIC Referring to FIG. 4, the write control sub-logic 234 generates the memory address strobe signals required by the video memory chips and the R/C signal described above. The write control sub-logic 234 outputs a row address strobe signal WRAS and a column address strobe signal WCAS to the read/write MUX 240. The WRAS signal strobes the current address ADD0A-ADD7A from the write address counter sub-logic 232 into the row address buffer of the video memory chips. The WCAS signal strobes the current address ADD0A-ADD7A into the column address buffers of the video memory chips. The LATCH signal from the video input sub-logic 230 acts as a trigger signal to cause the write control sub-logic 234 to generate the WRAS and WCAS signals whenever an 8-bit data word D0A-D7A/D0B-D7B is present at the output of the video input sub-logic 230. The LATCH signal also triggers the write control sub-logic 234 to generate the R/C signal to control the address output of the write address counter sub-logic 232. In addition to the LATCH signal, the write control sub-logic 234 receives as inputs the X2DIV6 and MHZ16 clock signals from the internal clock logic 264 and the HDEN8 horizontal sync signal from the video delay logic 260. The MHZ16 signal provides timing signals for generating the WRAS and WCAS signals. The HDEN8 signal acts as both a reset signal and a select signal for the write control sub-logic 234. When HDEN8 is high, the write control sub-logic 234 decodes the MHZ16 clock signal to generate WRAS and WCAS signals having the timing required by the preferred memory chips identified above. Specific timing information is readily available from the manufacturer of the chips. When HDEN8 goes low after a line of data has been received, it resets the write control sub-logic 234 and causes WRAS to track the X2DIV6 clock signal, thereby synchronizing the WRAS signal with the output of the row refresh address counter 485 of the write address counter sub-logic 232. FIG. 8c illustrates the details of the write control sub-logic 234. When HDEN8 is high, the occurrence of a positive-going LATCH signal clocks a D-latch 506 which enables the MHZ16 clock to clock a 4-bit counter 508. The counter outputs are decoded by an inverter 510 and NAND gates 512, 514, 516, 518, and 520. The decoded signals are synchronized by clocking them through D-latches 522 and 524.on the falling edge of MHZ16. The 0 output of the latch 522 is gated by NAND gates 526 and 528 to generate the WRAS signal. The /0 output of the latch 524 is gated by NAND gate 530 to generate- the WCAS signal. The signal at the Q_ output of the latch 522 is also delayed by one half clock cycle by a D-latch 532 and is output at the Q output of the latch 532 as the R/C signal. The counter outputs are decoded such that the WRAS signal goes low to strobe the address word ADD0A-ADD7A into the row address buffers * of the memory on the second falling edge of the MHZ16 after LATCH goes high. The R/C signal goes low on the rising edge of the next MHZ16 cycle to change the address word ADD0A-ADD7A to a column address, and the WCAS signal goes low on the next falling edge to strobe the column address into the column buffers of the memory chips. Both the WRAS and the WCAS signals go high on the sixth falling edge of MHZ16 and R/C goes high on the next rising edge of the MHZ16 signal. When HDEN8 goes low, counter 508 is reset and the MHZ16 clock is disabled from clocking the counter 508. The output of the AND gate 519 goes low, forcing the output of NAND gate 530 high which forces the WCAS signal high. In addition, the NAND gate 526 is disabled ' from gating the output of the D-latch 522 through to the output of NAND gate 528. Instead a NAND gate 534 is enabled to gate the X2DIV6 signal through to the output of NAND gate 528 as the WRAS signal. When HDEN8 is low, the WCAS signal is forced high and WRAS is toggled at the X2DIV6 rate in synchronization with the refresh row address counter 485 to perform a RAS only refresh of the memory chips. READ LOGIC Referring again to FIG. 4, the read logic 200 is comprised of three sub-logic blocks: the memory read sub-logic 214, the read address counter sub-logic 212, and the read control logic 210. The read logic 200 reads the stored video data from the memory banks A and B according to the memory map 120 in the unique manner previously described, and outputs the video data in 10-bit parallel words to the column drivers 60. MEMORY READ SUB-LOGIC The memory read sub-logic 214, reads 8-bit data words DA0-DA7 and DB0-DB7 through the read/write MUX 240 from video memory banks A and B respectively. Each video data word DA0-DA7/DB0-DB7 is read with its upper and lower four bits coming from corresponding words of adjacent memory map sections as described above. The memory read sub-logic 214 receives REG1CLK and REG2CLK shift register clock signals, SELA and SELB output data select signals, and a SWAP signal from the read control sub-logic 210. Under the control of the REG1CLK, REG2CLK, SELA, SELB, and SWAP signals, the memory read sub-logic 214 stores each video data word DA0-DA7 or DB0-DB7 in one of two 4 x 10 shift registers 150, 180 and outputs 10-bit parallel data words CD0-CD9 to the column drivers 60 in the manner described above. The REG1CLK signal supplies five positive going transitions to clock a first group of five 8-bit words of video data into one shift register 150 as described above. The REG2CLK signal supplies five positive-going transitions to clock a second group of five 8-bit words into the other shift register 180 also as described above. The REG1CLK and REG2CLK clock signals are mutually exclusive, i.e. when REG1CLK is active and clocking data into the first shift register, REG2CLK remains low, and vice versa. The state of the SWAP signal determines which shift register is shifting out data to the drivers and which is receiving data from the memory map 120. A low SWAP signal causes the memory read sub-logic 214 to output CD0-CD9 from the first register 150 and a high SWAP signal causes the memory read sub-logic 214 to output CD0-CD9 from the second register 180. As described in detail below, the SELA and SELB signals sequentially count through four different state combinations to cause the memory read sub-logic 214 to shift out each of the four bits in each 4-bit section of the shift register selected for output. FIGs. ' 9a through 9d inclusive illustrate the details of the memory read sub-logic 214. Referring to FIG. 9a, the memory read sub-logic 214 comprises an 8-channel 2 into 1 MUX 506, a first 4 x 10 shift register 150, a second 4 x .10 shift register 180, and a 10-channel 2 into 1 MUX 508. Data words DA0-DA7 and DB0-DB7 from the read/write MUX 240 are input to channels A and B respectively of the MUX 506. The MUX 506 selects either the DA0-DA7 data from video memory bank A or the DB0-DB7 data from video memory bank B depending on the state of the TFRAME signal. A low TFRAME selects the DA0-DA7 data. A high TFRAME selects the DB0-DB7 data. The 1Y-8Y outputs of the MUX 506 are connected without rearrangement to the D0-D7 inputs of the first shift register 150, but the 1Y-4Y outputs are connected to the D4-D7 inputs of the second register 180, and the 5Y-8Y outputs are input to the D0-D3 inputs of the second register 180. Thus, each word stored in the second shift register has its upper and lower four bits exchanged as described above. Each word DA0-DA7/DB0-DB7 is stored in one of the shift registers 150, 180 in the format illustrated in FIG. 3. Each of the shift registers 150, 180 has a 4-bit deep, ■ 10-bit wide parallel output CD0-CD9 which is clocked out in serial fashion by the SELA and SELB signals which step through four state changes from 00 to 11 in a binary counting sequence. The MUX 508 selects, the outputs of the first register 150 or the second register 180 based on the state of the SWAP signal. The SWAP signal changes states after every fifth memory read. When SWAP is low, the MUX 508 passes the output CD0-CD9 of the first register 150 to the column drivers 60. When SWAP is high, the MUX 508 passes outputs CD0-CD9 from the second register to the column drivers 60. FIGs. 9c and 9d taken together as shown in FIG. 9b illustrate the detail of one of the 4 x 10 shift registers 150. Shift register 180, which is not illustrated, is identical except that it is clocked by REG2CLK. In the preferred embodiment, each shift register comprises ten 4-bit serial-in-parallel-out shift registers 510-528 and- ten 4-channel digital switches 530-550 interconnected as illustrated. READ ADDRESS COUNTER SUB-LOGIC Referring to FIG. 4, the read address counter sub-logic 212 generates the row and column address signals required to read the video data words DA0-DA7 and DB0-DB7 out of the memory map 120 in the unique manner described above. The read address counter sub-logic 212 generates an 8-bit parallel address word ADD0B-ADD7B and an additional address signal ADD3BX both of which it couples to the read/write MUX 240. Depending on the state of an SLCT row/column select signal received from the read control sub-logic 210, the address word may be either a column or a row address. A high SLCT signal causes the read address counter sub-logic 212 to output a row address and a low SLCT signal causes the read address counter sub-logic 212 to output a column address. When a row address is selected, the read address counter sub-logic 212 outputs ADD3BX and ADD3B signals having the same state. However, when a column address is selected, the read address counter sub-logic 212 outputs the ADD3BX and ADD3B signals as inverses. In order to read four bits from each of two adjacent memory map sections simultaneously as described above, the read address counter sub-logic 212 inserts the ADD3B signal in the column address of one DRAM chip and the inverse ADD3BX signal in the column address of the other DRAM chip in the memory bank being read from. Thus, for example, when hexadecimal column address 00 is input to DRAM1, bits 0-3 of the first word (COL. 0) in the first map section 122 are read. At the same time, the hexadecimal column address 08 is presented to DRAM2 because ADD3BX, being the inverse of ADD3B, is high. Accordingly, bits 64-67 of the first word (COL. 8) of the second map section 124 are read from DRAM2. All of the other address values ADD0B-ADD2B and ADD4B-ADD7B are the same for both chips. In addition to inverting the ADD3B and ADD3BX signals to read data from adjacent map sections simultaneously, the read address counter sub-logic 212 also increments the upper four bits ADD4B-ADD7B of the column address word for every memory read so that the column address for each read is incremented by sixteen. Each occurrence of an RCAS column address strobe signal from the read control sub-logic 210 signals a read to the read address counter sub-logic 212 and causes it to increment the upper four bits ADD4B-ADD7B of the column address word. Following the example above, after the first occurrence of RCAS, the next four bits read from DRAM1 would be at hexadecimal column address 10 which corresponds to bits 128-131 of the first word (COL. 16) of the third map section 126. Simultaneously, the next four bits read from DRAM2 would be at hexadecimal column address 18 which corresponds to bits 192-195 of the first word (COL. 24) of the fourth map section 128. The read address counter sub-logic 212 increments the upper four address bits ADD4B-ADD7B of the column address in response to four consecutive RCAS signals without changing the value of the lower four column address bits. The five 8-bit words read from the memory map 120 in this manner each has its upper and lower four bits arranged as described previously and as illustrated in FIG. 3. After the fifth RCAS signal, the read address counter sub-logic 212 resets the upper four address bits ADD4B-ADD7B to zero and switches the states of ADD3B and ADD3BX. Following the example above, on the sixth RCAS the ADD3B signal is switched high and the ADD3BX signal is switched low. The read address counter sub-logic 212 still does not increment the lower column address bits ADD0B-ADD2B. Thus, on the sixth RCAS the four bits read from DRAM2 are at column address 00 which corresponds to bits 4-7 of the first word (COL. 0) of the first map section 122. Simultaneously, the four bits read from DRAM 1 are at column address 08 which corresponds to bits 68-71 of the first word (COL. 8) of the second map section 124. For the next four RCAS signals, the read address counter sub-logic 212 increments only the upper four address bits ADD4B-ADD7B so that the column address for each read is incremented by sixteen. After the fifth RCAS signal, the read address counter sub-logic 212 again clears the upper four address bits ADD4B-ADD7B and switches the states of the ADD3B and ADD3BX signals. In addition, it also increments the value of the lower column address bits ADD0B-ADD2B so that on subsequent reads the second word of each map section 122-140 will be addressed. The read address counter sub-logic continues operating in the above-described cycle with the upper column address bits ADD4B-ADD7B being reset and the states of the ADD3B and ADD3BX signals being reversed every fifth RCAS signal and the lower column address bits ADD0B-ADD2B being incremented every tenth RCAS signal until an entire line of video data is read out of the memory map 120. The read address counter sub-logic 212 repeats the cycle for each line of an entire frame, i.e. a complete read cycle, for four frames during each period of VDEN. In addition to the address signals ADD0B-ADD7B and ADD3BX, the read address counter sub-logic 212 also outputs the current row address RA0-RA7 to the read control sub-logic 210 and the row driver data/clock logic 268, which are described below. In addition to the RCAS and SLCT signals, the read address counter sub-logic 212 also receives as inputs an ENDRAS control signal, and RESETX, VD240, and ANYCLR reset signals from the read control sub-logic 210. The ENDRAS control signal acts as a clock signal to cause the read address counter sub-logic 212 to increment the row address. The ENDRAS signal is a positive-going pulse that occurs at the end of each row of video data read from memory. The RESETX and VD240 signals reset the row address generated by the read address counter sub-logic 212 at the beginning of the first frame (RESETX) and at the end of each subsequent frame (VD240). The ANYCLR signal resets the column address generated by the read address counter sub-logic 212 at the beginning of the first frame, after each line of video data has been read from memory and output to the display drivers 60, and after each complete frame of video data has been read and output. FIG. 9e illustrates the details of the read address counter sub-logic 212. The read address counter sub-logic 212 includes a row address counter 560 comprised of two 4-bit counters 562 and 564 which are connected as an 8-bit ' counter. It also includes a column address counter 565 comprised of 4-bit counters 566 and 568, D-latch 570, NAND gates 572, 574, and 576, inverter 578, OR gate 580, and AND gate 582. The row counters 562 and 564 are clocked by the ENDRAS signal at the end of each line of data read and are cleared at the beginning of the first frame and at the end of each subsequent frame by the RESETX and VD240 signals. When SLCT is high and a row address is selected, the OR gate 580 and NAND gates 576 and 574 output the RA3 row address signal as the ADD3BX signal. The column address counter " 566 for the upper four column address bits ADD4B-ADD7B is clocked by the RCAS signal. On the fifth RCAS, both CA4 and CA6 go high causing ' he NAND gate 572 and AND gate 582 to reset the . counter 566. At the same time, the NAND gate 572 and inverter 578 clock the D-latch 570, thereby changing its output state for the next five RCAS signals. The signal at the 0 output of the D-latch 570 is the CA3 signal. When SLCT is low and a column address is selected, the CA3 signal at the output of the D-latch 570 is also inverted by the OR gate 580 and NAND gates 576 and 574 and output as the column address signal ADD3BX. The lower column address bits counter 568 is clocked by the /0 output of the D-latch 570. The D-latch is connected in a divide-by-two configuration so that the /O output only goes high to clock the counter 568 every second clock signal or in other words every tenth RCAS. The row and column addresses are selected by an 8-channel 2 into 1 MUX 584. A low SLCT selects the column address counter 565 outputs to be outputs to be output as the address word ADD0B-ADD7B. A high SLCT signal selects the row address counter outputs to be output as the address word ADD0B-ADD7B. The ADD3BX signal is always output. READ CONTROL SUB-LOGIC Referring to FIG. 4, the read control ' sub-logic 210 generates the memory address strobe signals RRAS (row address strobe) and RCAS (column address strobe) required to latch the column and row address words ADD0B-ADD7B into the memory chips and outputs them to the read/write MUX 240. In addition, the read control sub-logic 210 generates the row/column address select signal SLCT, the ENDRAS signal, and the RESETX, ANYCLR, and VD240 reset signals which are coupled to the read address counter sub-logic 212. The VD240 reset signal is also coupled to the row driver data/clock logic 268, which is described below. In addition, the read control sub-logic 210 generates a CK signal which it couples to the column clock logic 266 which is described below. The read control sub-logic 210 also generates and outputs to the memory read sub-logic 214 the REG1CLK, REG2CLK, SELA, SELB, and SWAP signals. The VD240 signal is a positive-going reset signal that goes high at the end of each frame of video data read by the read logic 200 and goes low with the falling edge of the VDEN vertical sync signal. The RESETX signal is a positive-going reset signal that occurs coincident with the VDENRS reset signal at the beginning of each frame of video data read by the read logic 200 and at the end of every fourth frame of video data read by the read logic 200 coincident with the VD240 signal. The ANYCLR signal is a negative-going reset signal that occurs coincident with the VDENRS signal at the beginning of each frame of video data read by the read logic 200, at the end of each video data line width period coincident with the LWPOUT reset signal generated by the line width program sub-logic 252 described below, and at the end of every fourth frame of video data read by the read logic 200 coincident with the VD240 reset signal. As inputs, the read control sub-logic 210 receives an LWPOUT reset signal from the line width program sub-logic 252 of the program logic 250, the VDENRS reset signal from the video delay logic 260, 5CNT and 23CNT signals which are decoded from the CK signal by the column clock logic 266, and X2DIV3 and MHZ16 clock signals from the internal clock logic 264. The read control logic 210 also receives the row address output word RA0-RA7 generated by the row address counter 560 of the read address counter sub-logic 212. The LWPOUT signal is a negative-going reset signal that occurs at the end of each video data line width period. The line width period is established by the line width program sub-logic 252 as described below and defines the maximum time period the read logic 200 has to read and display a complete line of video data. The LWPOUT signal causes a master reset of the read control sub-logic 210. The VDENRS ' signal also resets the read control sub-logic 210 at the beginning of each frame of data read by the read logic 200. The 5CNT and 23CNT decode signals are used by the read control sub-logic 210 to generate the SELA, SELB, REG1CLK, and REG2CLK signals. The X2DIV3 clock signal provides memory read timing signals which are decoded by the read control sub-logic 210 to generate RRAS and RCAS signals having the timing required by the preferred memory chips previously identified. This timing information is readily available from the manufacturer of the chips. In the preferred embodiment, the X2DIV3 signal completes a minimum of 89 low to high transitions during each video line width period. The read logic 200 reads each row of video data (640 bits) from the preferred memory chips in two page mode reads. Each page mode read is initiated by the RRAS signal going low. A total of 85 low to high RCAS transitions are required to read and output a complete line of 640 video data bits from memory. During the first page mode read, 43 RCAS positive-going transitions are completed. During the second page mode read, 42 positive-going transitions of the RCAS signal are completed. Between page mode reads, the read control sub-logic 210 causes the RRAS signal to go high for one cycle of the X2DIV3 clock. The ENDRAS signal goes high on the eighty-ninth rising edge of X2DIV3 to signal that a complete line of data has been read. The ENDRAS signal stays high until the first page mode read of the next line. FIGs. 9f through 91 inclusive illustrate the details of the read control sub-logic 210. Referring to FIG. 9f, the read control sub-logic 210 includes NAND gates 586 and 588, NOR gate 590, and inverters 592-598, which combine to decode the row address word RA0-RA7 to produce a positive-going signal at the output of NAND gate 590 when the row address reaches 202. The D-latch 600 latches the signal at its O output as the VD240 signal on the next rising edge of the MHZ16 clock. Referring to FIG. 9g, the read control sub-logic 210 also includes a 4-bit serial-in-parallel-out shift register 602, a D-latch 604, a NAND gate 606, an inverter 608, and an AND gate 610 which generate the RESETX, RESET, and ANYCLR reset signals with the relative timing described above. FIGs. 9h and 9i illustrate the details of the logic for decoding the X2DIV3 timing signal and generating the RRAS and RCAS row and column address strobe signals respectively. As shown in FIG. 9h, the X2DIV3 signal clocks a pair of 4-bit counters 612 and 614 which are connected as an 8-bit counter. Inverters 616-623, numbered consecutively from top to bottom, NAND gates 624-638, numbered consecutively from left to right, NAND gates 640, 642, and 656, NOR gates 644, 646, 648, 650, 652, and 654, and inverters 658, 660, 662, and 663 decode the counter outputs. The resulting ENDRAS signal at the output of the NOR gate 648 is a positive-going pulse occurring on the eighty-ninth rising edge of the X2DIV3 signal. The resulting DECRAΞ signal at the output of the inverter 662 is a positive-going, one X2DIV3 cycle wide pulse occurring on the forty-fourth rising edge of the X2DIV3 signal. The counters 612 and 614 are reset by the ANYCLR reset signal. As shown in FIG. 9i, the X2DIV3 signal clocks the DECRAS signal through a first D-latch 664. The MHZ16 clock signal clocks the DECRAS signal through second and third D-latches 666 and 668. An OR gate 672 gates the X2DIV3 signal with the Q output of the D-latch 668 to generate the RCAS signal. The RRAS signal appears at the Q output of the D-latch 666 and is clocked through a fourth D-latch 670 by the inverted MHZ16 clock signal at the output of the inverter 669. The SLCT signal appears at the output of the D-latch 670. All of the D-latches 664, 666, 668, and 670 are initially set by the ANYCLR signal. Accordingly, the RRAS, RCAS, and SLCT signals are all initially high. The rising and ' falling edges of the RCAS signal occur substantially simultaneously with those of the X2DIV3 signal except during the X2DIV3 cycle when the DECRAS signal is high. On that cycle, the trailing edge of the RCAS signal is delayed by two MHZ16 clock cycles. The RRAS signal goes low to initiate the first page mode read of a line one MHZ16 clock cycle after the first rising edge of the X2DIV3 signal. The RRAS signal goes high one MHZ16 clock cycle after the DECRAS signal goes high, and goes low to initiate the second page mode read of the line one MHZ16 clock cycle after the DECRAS signal goes low. The SLCT signal is initially high and causes the read address counter sub-logic 212 to output the present row address when the- RRAS signal goes low. One half MHZ16 clock cycle after the RRAS signal goes low, the SLCT signal goes low, thereby causing the read address counter sub-logic 212 to output a column address which is strobed into the memory when the RCAS signal goes low on the falling edge of the X2DIV3 signal. Referring to FIG. 9j, a NAND gate 674 gates the RCAS signal and the O output of a D-latch 676 to • generate the CK signal. Each falling edge of the RCAS signal clocks a ' 4-bit counter 682. A NAND gate 678 and inverter 680 decode the output of the counter 682 to clock a high state through the D-latch 676 on the falling edge of the sixth RCAS signal of the first page mode read of each line of video data. The CK signal is initially high. On the sixth falling edge of the RCAS signal, the NAND gate 674 is enabled to invert the RCAS signal to generate the CK signal. A D-latch 686 initially has its O output low and its /O output high after being reset by ANYCLR. The Q output of the latch 686 is gated with the RCAS signal by an AND gate 688 to generate the REG2CLK signal. The /Q output of the latch 686 is gated with the RCAS signal by an AND gate 690 to generate the REG1CLK signal. On the falling edge of the sixth RCAS signal of the first page mode read of a line, the output of a NAND gate 684 goes low and then high to clock the D-latch 686. The D-latch 686 is configured in a divide-by-two arrangement and each time it is clocked its Q and /Q outputs switch states. After the D-latch 686 is initially clocked, the next five RCAS signals generate five corresponding REGICLK clock signals at the output of the AND gate 690. The REG2CLK signal remains low during this time. On the falling edge of the fifth RCAS signal, i.e. the rising edge of the fifth CK signal, the 5CNT signal goes ' low and causes the NAND gate 684 to clock the D-latch. The next five RCAS signals generate five corresponding REG2CLK signals at the output of the AND gate 688. The REGICLK signal remains low during this time. Therafter, the 5CNT signal goes low on the rising edge of every fifth RCAS signal to clock the D-latch 686 and cause alternating sets of five REGICLK and five REG2CLK signals to be generated at the outputs of the AND gates 690 and 688 respectively. The SWAP signal appears at the / output of the D-latch 686. It is initially high during the first page mode read and alternates between high and low states every five RCAS signals as the D-latch 686 is clocked by the 5CNT signal. Referring to FIG. 9k, the 23CNT signal generated by the column clock logic 266 is clocked through two series D-latches 692 and 694 by the MHZ16 clock signal to generate the SELB signal. The 23CNT signal is high during the second and third cycles of every five cycles of the CK signal and is low during the first, fourth and fifth cycles thereof. Referring to FIG. 91, the MHZ16 signal clocks the REG2CLK, REGICLK, TPCLK, and BTCLK signals through a 4-channel D-latch 696. The TPCLK and BTCLK signals are column driver clock signals generated by the column clock logic 266. The MHZ16 signal also clocks the BTCLK signal through a second D-latch 698 to generate the SELA signal. Thus, the SELA signal is the BTCLK signal delayed by one MHZ16 clock cycle. Referring to FIG. 11, the BTCLK signal is high when the counter 816 output is binary 001 or Oil and is low when the counter 816 output is binary 000, 010, or 100. The 4-channel latch 696 synchronizes the REGICLK, REG2CLK, TPCLK, and BTCLK signals. The 4-channel latch 696 and D-latches 692, 694, and 698 synchronize the SELA and SELB signals. READ/WRITE MUX The read/write MUX 240 illustrated in FIG. 4 performs the function of switching video memory banks A and B every VDEN period so that each bank is alternately written into and read out of by the write logic 220 and read logic 200 respectively. FIGs. 10a through lOd illustrate the details of the read/write MUX 240. Ref rring -to FIG. 10a, the read/write MUX 240 includes a data MUX 900 comprised of sixteen parallel tri-state transceivers, two of which, 902 and 918, are illustrated. The transceivers are divided into two groups of eight with one group corresponding to video memory bank A and the other to video memory bank B. The transmitters of each of the transceivers in the group corresponding to bank A are enabled by a low FFRAME signal and the transmitters of each of the transceivers in the group corresponding to bank B are enabled by a low TFRAME signal. The data MUX 900 receives the duplicate video, data words DOA-D7A and DOB-D7B from the write logic 220. The transceivers in the group corresponding to memory bank A transmit the data word DOA-D7A on the corresponding data lines of the memory chips comprising memory bank A when enabled and the transceivers in the group corresponding to memory bank B transmit the DOB-D7B word on the corresponding data lines of the memory chips comprising memory bank B when enabled. The receivers in the group corresponding to memory bank A receive the data word DA0-DA7 from the corresponding data lines of the memory chips comprising bank A and the receivers in the group corresponding to bank B receive the data word DBO-DB7 from the corresponding data lines of the memory chips comprising bank B. Referring to FIG. 10b, the read/write MUX 240 includes a MUX for switching the ADD3A and ADD3BX signals between memory bank A and memory bank B each frame so that the ADD3A signal is always directed to the bank being written to and the ADD3BX to the bank being read from. The logic is comprised of NAND gates 920, 922, 924, 926, 928, and 930, and drivers 932, and 934. When the TFRAME signal is high and the FFRAME signal is low, the ADD3A and ADD3BX signals appear at the outputs of drivers 932 and 934 respectively. When the TFRAME signal is low and the FFRAME signal is high, the signals are reversed at the outputs of the drivers 932 and 934. Referring to FIG. 10c, the read/write MUX 240 includes an address MUX comprised of two 8-channel 2 into 1 ' MUX's 982 and 983 and associated drivers 984-991 and 992-999 respectively. Both MUX's 982 and 983 select between the address word ADDOA-ADD7A on channel A and ADD0B-ADD7B on channel B. The MUX 982 is selected by the FFRAME signal and the MUX 983 ' is selected by the TFRAME signal. Since TFRAME and FFRAME are inverses, when channel A of the MUX 982 is selected, channel B of the MUX 983 is selected and vice-versa so that the read and write addresses alternate between memory banks A and B each input frame. Referring to FIG. lOd, the read/write MUX 240 also includes a RAS/CAS MUX comprised of NAND gates 936-958, inverters 958-964, NAND gates 966, 972, and drivers 974-980. When TFRAME is high and FFRAME is low, WRAS and WCAS are directed to the outputs of drivers 974 and 976 respectively and RRAS and RCAS are directed to the outputs of drivers 978 and 980 respec¬ tively. When TFRAME is low and FFRAME is high, RRAS and RCAS are directed to the outputs of the drivers 974 and 976 respectively and WRAS and WCAS are directed to the outputs of the drivers 978 and 980 respectively. The drivers 974 and 976 drive the RAΞ and CAS lines of the memory chips-in bank A and the drivers 978 and 980 drive the RAS and CAS lines of the memory chips in bank B. PROGRAM LOGIC LINE WIDTH PROGRAM SUB-LOGIC As shown in FIG. 4, the program logic 250 is comprised of three sub-logic blocks: the line width program sub-logic 252, the pre-charge time select sub-logic 254, and the constant current time select sub-logic 256. The line width program sub-logic 252 provides a programmable interface that allows the computer 20 to set the nominal video data line width for the read logic 200 as a selected number of cycles of the 16MHZ clock signal. The line width period is based on the full speed frequency of the DOTCLK signal. The video data line width is the maximum time period in MHZ16 clock cycles which the read logic 200 has to read a complete line (640 bits) of video data from the video memory and output it to the display drivers 60, 70. The preferred embodiment of the VDI 10 operates on a nominal line period of 20.6 microseconds per line which is based on the preferred frame output rate of 240 Hz. Each output frame consists of 202 lines of 640 bits each, where 200 lines constitute display data and two are non-visible overscan lines. As described above, the VDI 10 accepts a DOTCLK clock signal anywhere be¬ tween 13.1 and 16.0 MHz from the computer 20. Accord¬ ingly, the nominal line width in MHZ16 clock cycles can range between approximately 268 and 330 MHZ16 cycles. The line width program sub-logic 252 calculates the line width from a 5-bit parallel line width program word LWP0-LWP4 supplied by the computer 20. The word LWP0-LWP4 specifies the number of clock cycles per line in two MHZ16 clock cycle increments from 268 to 330 clock cycles. The line width program sub-logic 252 calculates the line width in MHZ16 clock cycles accord¬ ing to the expression 268 + 2* (LWP0-LWP4) , where LWPO- LWP4 is the decimal value of the line width program word. Three MHΣ16 clock cycles after the expiration of each line width period, the line width program sub- logic 252 outputs a negative-going signal LWPOUT which resets the read control sub-logic 210 as described above. The line width program sub-logic 252 also resets itself and then starts counting MHZ16 clock cycles corresponding to the line width period for the next line. The line width program sub-logic 252 receives as inputs the MHZ16 clock signal from the internal clock logic 264, and the VDENRS and LWPCLR reset signals from the video delay logic 260. The LWPCLR and VDENRS signals reset the line width program output signal LWPOUT and reload the line width program word LWP0-LWP4 into the line width program sub-logic 252 at the beginning of each frame of video data received by the VDI 10. FIG. 7a illustrates the details of the line width program sub-logic 252. The line width program sub-logic 252 includes a NAND gate 700, NOR gate 702, exclusive NOR gates 704 and 706, inverters 708, 710, 712, and 714, and a reloadable 10-bit down counter 715 comprised of two 4-bit up/down counters 716, 718, and one 2-bit up/down counter 720. The counter 715 is loaded with a value equal to 268 plus two times the decimal value of the line width program word LWP0-LWP4. The counters 716, 718, and 720 receive a load signal from a D-latch 722 at the beginning of each frame of data received by the VDI 10. Also at the beginning of each frame, the LWPCLR signal sets the LWPOUT signal high through an AND gate 733. The 10-bit down counter is clocked by the MHZ16 clock signal and its output is decoded by NOR gates 722 and 724, and NAND gate 726 to generate a negative-going signal at the output of the NAND gate 726 when the count reaches zero. Three series D-latches 728, 730, and 732 provide up to three MHZ16 clock cycles of delay of this signal. A self-reset signal appears at the 0 output of the first D-latch 728. The LWPOUT signal appears at the 0 output of the third latch 732. Thus, one MHZ16 clock signal after the count reaches zero the self-reset signal goes low and causes an AND gate 734 to go low, resetting the D-latch 722 and reloading the line width value into the counter 715. Three MHZ16 clock cycles after the count reaches zero, the LWPOUT signal goes low for one MHZ16 clock cycle. PRE-CHARGE TIME SELECT LOGIC Referring to FIG. 4, the pre-charge time select sub-logic 254 and the constant current time select sub-logic 256 provide a programmable interface for generating control signals to control the pre-charge and constant current characteristics of the drive signals generated by the display drivers 60, 70. The pre-charge time select sub-logic 254 generates a column pre-charge signal CPC which controls the duration of the pre-charge drive signal generated by the column drivers 60 to overcome the capacitance of the luminescent material of the display 50. The CPC signal corresponds to the PRECHARGE signal described in the co-pending patent application for the preferred electroluminescent display drivers which is identified and incorporated above. As illustrated in FIG. 16a, the CPC signal goes high at the same time as the output of the external power supply 80 and stays high for one to four periods of 14-MHZ16 clock cycles each depending on the state of a pre-charge control word PCT0-PCT1 received from the computer 20. When PCT0-PCT1 has the value 00, for example, one period of 14-MHZ16 clock cycles is selected. When PCT0-PCT1 has a value of 11, four periods of 14-MHZ16 clock cycles are selected. In addition to the pre-charge control word PCT0-PCT1, the pre-charge time select sub-logic 254 receives as inputs the DEC60 clock decode signal and the MHZ16 clock signal from the internal clock logic 264, and the ANYCLR reset signal from the read control sub-logic 210. The MHZ16 signal is used by the pre-charge time select sub-logic 254 to time the duration of each pre-charge period selected by the pre-charge control word PCT0-PCT1. The DEC60 signal is a positive-going signal that causes the pre-charge time select sub-logic to start counting the precharge duration value established by the PCT0-PCT1 word and forces the CPC signal to go high on the sixtieth cycle of the MHZ16 clock of the first page mode read for each line of video data read from memory. The ANYCLR signal resets the pre-charge time select sub-logic 254 and loads the precharge duration value at the end of each line, at the beginning of each frame, and at the end of every fourth frame of video data read and output. FIG. 7c illustrates the details of the pre-charge time select sub-logic 254. The pre-charge time select sub-logic 254 includes up/down counters 740 and 742 connected as a 6-bit down counter 745. The inverters 741 and 743 decode the PCT0 and PCT1 signals and initially load the down counter 745 with a count value equal to fourteen times the decimal value of the PCT0-PCT1 pre-charge control word when the ANYCLR signal goes low. The counter 745 is clocked by the MHZ16 signal and its outputs are decoded by an inverter 746, NOR gates 748 and 750, and a NAND gate 752. After a reset by ANYCLR, the / output of the latch 758 is high which forces the output of NOR gate 760 to go low to load the counter 745. The high /0 output of latch 758 also forces the CPC signal at the output of NAND gate 754 low. When the DEC60 signal goes high, it clocks a low state through a D-latch 744 to the NAND gate 754 and causes the CPC signal to go high. The low state is inverted to a high state ' by a NAND gate 756 and is clocked through a D-latch 758 by the rising edge of the MHZ16 signal. The resulting low /O output of latch 758 causes the output of NOR gate 762 to go high and enables the counter 745 to start counting down the preloaded value. The resulting high O output of the D-latch 758 is inverted by a NOR gate 760 and resets the D-latch 744. Thereafter, when the output of the down counter 745 reaches a count of two, the low signal appearing at the output of the NAND gate 752 is gated to the D-latch 758 by NAND gates 764 and 756.- On the next rising edge of the MHZ16 signal, the /0 output of the D-latch 758 goes high and causes the CPC signal appearing at the output of the NAND gate 754 to go low. CONSTANT CURRENT TIME SELECT SUB-LOGIC Referring to FIG. 4, the constant current time select sub-logic 250 outputs a constant current source disable signal CSD to the reset logic 272 which gates it out to the display drivers 60, 70 as described below. The CSD signal controls the duration of the constant current drive signals generated by the display drivers 60, 70 to cause the luminescent material of the display 50 to luminesce. The CSD signal corresponds to the CCD constant current disable signal described in the co-pending patent application for the preferred constant current electroluminescent display drivers identified above. As illustrated in FIG. 16a, the CSD signal goes low simultaneously with the output of the external power supply 80 going high. The CSD signal stays low, thereby enabling the constant current display drivers for a period of 114, 171, 206, or 220 MHZ16 clock cycles depending on the state combination of the CCHTO-CCHTl constant current control word. For example, a 00 state combination selects a CSD period of 114 cycles while a 11 state combination selects a period of 220 cycles. When the CSD signal goes high, it disables the constant current column drivers 60. The computer 20 can override the programmed CSD period and maintain the drivers 60 enabled for as long as desired by supplying a low CCOE signal to drive the CSD signal low. When the CCOE signal is brought high, the CSD signal returns to its programmed state. In addition to the CCHTO-CCHTl constant current control word, the constant current time select sub-logic 256 also receives as inputs the DEC60 clock decode signal and the MHZ16 clock signal from the internal clock logic 264, and the ANYCLR signal from the read control sub-logic 210. The DEC60 signal synchronizes the CSD and CPC signals. The MHZ16 signal provides the timing for the constant current time period selected by the CCHTO-CCHTl constant current control word. The ANYCLR signal resets and reloads the constant current time select sub-logic 256 at the beginning of each frame, and at the end of each line, and at the end of every fourth frame of video data read and output. FIG. 7b illustrates the details of the constant current time select sub-logic 256. Inverters 770 and 772, NAND gates 776, 778, and 782, NOR gate 774, and exclusive OR gate 780 decode the CCHT0 and CCHT1 signals and load a value of either 114, 171, 206, or 220 into an 8-bit down counter 785 depending on the states of the CHHTO and CCHT1 signals. The down counter 785 is comprised of 4-bit up/down counters 784 and 786 and is clocked by the MHZ16 signal. The outputs of the counter 785 are decoded by an inverter 788, NOR gates 790 and 794, and NAND gate 792. The CSD signal, which appears at the output of a NOR gate 796, is initially high after a reset by the ANYCLR signal. The ANYCLR signal also causes the /0 output of the latch 804 to go high. The high /0 output is inverted by a NOR gate 806 and loads the constant current time period into the counter 785. When the DEC 60 signal goes high, It clocks a low state through a D-latch 798. The low state is inverted by a NAND gate 800 and applied to the NOR gate 796 to cause the CSD signal to go low. The low state is also inverted by a NAND gate 802 and the inverted signal is clocked through a D-latch 804 by the MHZ16 clock signal. The resulting high signal appearing at the /0 output of the D-latch 804 is inverted by a NOR gate 808 and resets the D-latch 798. Thereafter, the CSD signal remains low until the output of the down counter 785 reaches two. At two, the output of the NAND gate 792 goes low for one MHZ16 clock cycle. The low signal is gated to the D-latch 804 by NAND gates 810 and 802 and is clocked through the latch 804 by the MHZ16 clock. The resulting high state at the /Q output of the latch 804 causes the output of the NAND gate 800 to go high and the CSD signal at the output of the NOR gate 796 to go high. It is also inverted by a NOR gate 806 and reloads the down counter 785 with the constant current time period established by the CCHTO-CCHTl control word. The CSD signal remains high until the next occurrence of the DEC60 signal. The computer 20 can override the programmed constant current time by sending a low CCOE constant current overrride enable signal. An inverter 812 inverts the low CCOE signal and applies it to the NOR gate 796, thereby forcing the CSD signal low until the CCOE signal goes high. COLUMN CLOCK LOGIC Referring to FIG. 4, the column clock logic 266 generates alternating TPCLK and BTCLK clock signals to alternately latch successive 10-bit output words CD0-CD9 from the shift registers 150, 180 of the memory read sub-logic 214 to each group of ten column drivers 60. The BTCLK clock signal simultaneously clocks one bit of the CD0-CD9 output word into each of the ten even numbered column drivers (e.g. column 0, 2, 4, etc), and the TPCLK clock signal clocks the CD0-CD9 output word simultaneously into the ten odd numbered column drivers (e.g. columns 1, 3, 5, etc. ). As illustrated in FIG. 16b, the rising edges of the TPCLK and BTCLK signals alternate so that the rising edge of the BTCLK signal corresponds to the first output word CD0-CD9 of a line, the rising edge of the TPCLK signal corresponds to the second output word, and so on. Each CD0-CD9 pulse illustrated in FIG. 16b represents a time period during which the particular CD0-CD9 output word is valid. As inputs, the column clock logic 266 receives the CK clock signal and the ANYCLR reset signal from the read control sub-logic 210. The ANYCLR signal resets the column clock logic 266 at the beginning of each frame, at the end of each line, and at the end of every fourth frame of video data read and output. As described above, the CK clock signal is the inversion of the RCAS signal and is delayed by six RCAS cycles. The TPCLK and BTCLK clock signals are decoded from CK so that for each line of video data read and output to the column drivers 60, no BTCLK or TPCLK signals occur until after six memory reads have occurred. This ensures that the first shift register 150 has been completely filled before any clock signals occur to latch the contents thereof to the column drivers 60. Therafter, the BTCLK signal is high when the output of the counter is binary 001 and 011 and low when the output of the counter 816 is binary 000, 010, and 100. The TPCLK signal is high when the output of the counter 816 is binary 010 and 100 and is low when the output of the counter 816 is binary 000, 001, and 011. As' illustrated in FIG. 16b, 32 cycles of both BTCLK and TPCLK must occur to latch a complete line of video data to the column drivers 60. The column clock logic 266 also decodes a 5CNT and a 23CNT signal from the CK signal and couples these signals to the read control sub-logic 210 which generates the REGICLK, REG2CLK, SELA, SELB, and SWAP signals therefrom. The details of the column clock logic 266 are illustrated in FIG. 11. The CK signal clocks a modulo five counter 815 comprised of 4-bit counter 816 and AND gate 818. NAND gates 820, 822, 824, 826, 828, and 838, and inverters 830, 832, 834, 836, and 840 decode the outputs of the counter 816. The counter is reset by the ANYCLR signal. The 5CNT signal at the output of the NAND gate 820 goes low on the rising edge of every fifth CK signal thereby causing the output of the AND gate 818 to go low and reset the counter 816. The 23CNT signal appearing at the output of the NAND gate 828 is high when the output of the counter 816 is binary 010 and 011 and is low when the counter 816 output is binary 000, 001 and 100. The TPCLK and BTCLK signals are decoded as described above. ROW DRIVER DATA/CLOCK LOGIC Referring to FIG. 4, the row driver data/clock logic 268 generates a row driver output data signal RDO and a row driver data clock signal RDC which are available to the row drivers 70. The preferred row drivers 70 described in the co-pending patent applica¬ tion identified above are arranged in two groups of 100 drivers, each driver of each group corresponding to a row of the display 50. Similarly to the arrangement of the preferred column drivers 60, one group of row drivers drives the even numbered rows of the display, i.e. rows 0, 2, 4 and so on through row 198, and the other group drives the odd numbered rows, i.e. rows 1, 3, 5 and so on through row 199. Each group of row drivers has a serial-in-parallel-out shift register (not shown) associated with it. Each shift register has a data output for each driver of the associated group. Both shift registers are clocked by positive- going transitions of the RDC clock signal which has a period equal to two rows duration. Where the preferred row drivers are used, a pair of enable signals are derived externally of the VDI 10 from the RDC signal. The enable signal for the even numbered row drivers is the inverted RDC signal. The enable signal for the odd numbered row drivers is the uninverted RDC signal. Thus, both shift registers are clocked to output row data to two successive rows for periods of two rows duration. However, the shift registers are only enabled to output row data on alternate rows. As illustrated in FIG. 16c, the row driver output data signal RDO is a negative-going pulse that occurs once at the second row, i.e. row number 1, of each output frame and remains low for a one row period, e.g., the period of row 1. The low RDO signal is clocked into the shift registers for both the even numbered and odd numbered row drivers by the rising edge of the RDC clock signal after the first column data CD0-CD9 for the line is latched into column drivers 60. Thereafter, the RDO signal goes high for the remainder of the output or 240 Hz frame, i.e. until all 200 rows of the display and two overscan rows have been scanned. ' The RDO signal is decoded from the row address word RA0-RA7 which is supplied by the read address counter sub-logic 212. The RDC signal is ' triggered by the DEC2 clock decode signal for each line of video data. During each line, the occurrence of the DEC2 signal causes the RDC signal to change state. Thus, the RDC signal is essentially a clock signal having a period of two video data lines duration. In addition to the row address word RA0-RA7, the row driver data/clock logic 268 receives as inputs the VDENRS reset signal from the video delay logic 260, the MHZ16 clock signal and the DEC2 clock decode signal from the internal clock logic 264, and the VD240 reset signal from the read control sub-logic 210. The VDENRS and VD240 signals reset the row driver data/clock logic 268 at the beginning and end of each output frame. The MHZ16 clock signal and the DEC2 clock decode signal provide timing information from which the RDC signal is generated. FIGs. 12a and 12b illustrate the details of the row driver data/clock logic 268. Referring to FIG. 12a, the MHZ16 signal clocks the DEC2 signal through a D-latch 842 to clock a second D-latch 844 connected In a divide-by-two configuration. The RDC signal, which appears at the /Q output of the second latch 844, is initially high after a reset by either VD240 or VDENRS. The RDC signal changes state for every line with the occurrence of the DEC2 signal. Referring to FIG. 12b, an inverter 846, NOR gates 848 and 850, and a NAND gate 852 decode the row address word RA0-RA7 so that the RDO signal is low at hexadecimal row address count 01, i.e. the second row, and is high at all other row address values. RAMP POWER SUPPLY CONTROL LOGIC Referring again to FIG. 4, the ramp power supply control logic 270 generates control signals RPSC and XRPSC for controlling the output state of the external power supply 80 used by the drivers 60 and 70 to drive the display 50. In addition, the ramp power supply control logic 270 generates a column latch enable signal CLE for enabling the latches (not shown) associated with the preferred column drivers 60 to accept the video data output word CD0-CD9 from the read logic 200. The RPSC and XRPSC signals are coupled to the reset logic 272. The CLE signal is available directly to the column drivers 60. In the preferred embodiment of the VDI 10, a low RPSC signal ' is a ramp up signal and a high RPSC signal is a ramp down signal. Thus, as illustrated in FIG. 16a, when RPSC goes high the output of the external power supply ramps down and when RPSC goes low the output of the supply 80 ramps up. The RPSC and XRPSC signals are derived by the ramp power supply control logic 270 from the DEC3, DEC10, DEC38, and DEC45 clock decode signals supplied by the internal clock logic 264. A positive-going RPSC signal is derived from the DEC3 and DEC45 clock decode signals for each line of video data to displayed in order to ramp the power supply down for a sufficient time to allow the column driver latches and outputs to be enabled and the output data word CD0-CD9 to be loaded into the column drivers 60. A positive-going XRPSC signal is also derived for each line of video data from the DEC10 and DEC38 clock decode signals. The rising edge of the XRPSC signal trails the rising edge of the RPSC signal by seven MHZ16 clock cycles. The falling edge of the XRPSC signal precedes the falling edge of the RPSC signal by seven 16MHz clock cycles. It is not strictly necessary to utilize both control signals with all types of power supplies. However, the additional XRPSC signal is useful where a power supply of the push-pull type is used. The ramp power supply control logic 270 derives the column latch enable signal CLE from the DEC16 signal during the time that the RPSC signal is high and the power supply output low between lines. The CLE signal is a positive-going one MHZ16 clock cycle wide pulse that corresponds to the latch enable signal described in the co-pending patent application for the preferred electroluminescent display drivers identified above. FIG. 16a illustrates the relative timing of the RPSC, XRPSC, and CLE signals. FIG. 13 illustrates the details of the ramp power supply control logic 270. D-latches 858-868 are all clocked by the MHZ16 signal and are all reset by the ANYCLR signal. MHZ16 clocks the DEC2 signal through latch 856 to generate the CLE signal. The MHZ 16 signal also clocks the DEC3 signal through the latch 858 to clock latch 862. The RPSC signal which appears at the Q output of latch 862 goes high on the rising edge of DEC3. The MHZ16 signal clocks the DEC45 signal through latch 860. The /0 output of the latch 860 is gated by an AND gate 870 to reset the latch 862 and drive the RPSC signal low at the rising edge of DEC45. The XRPSC signal is generated similarly by latches 864, 866, and 868, and AND gate 872 from the DEC10 and DEC38 signals. RESET LOGIC Referring again to FIG. 4, the reset logic 272 passes the low POR reset signal from the power-on reset RC timer 100 to hold all of the major logic blocks of the preferred VDI 10 reset during power-up as previously described. The VDI logic begins to operate when the POR signal reaches a value of approximately 1.25 volts. In addition, the reset logic 272 gates the ramp power supply control signals RPSC, XRPSC and the column driver current source disable signal CSD with the WDRC reset signal from the watch dog RC timer 90 before making them available to the power supply 80 and drivers 60. The WDRC timer 90 times occurrences of the HDEN signal. If after going low, HDEN should for any reason fail to go high again within a time period approximately equal to 4-7 milleseconds (50-60 HDEN cycles), the WDRC signal preferably increases to a value of approximately 1.25V which causes the reset logic 272 to hold the RPSC, XRPSC, and CSD signals high to ramp down the power supply 80 and disable the column drivers 60. Also, the reset logic 272 generates a column output enable signal COE which is the inverse of the RPSC signal. The COE signal corresponds to the column driver output enable signal described in the co-pending patent application for the preferred electroluminescent display drivers identified and incorporated above. In the preferred embodiment, a high COE signal enables the column outputs of the preferred drivers 60 and a low COE forces the column outputs to a low state. As- illustrated in FIG. 16a, when the RPSC signal goes low and causes the power supply output to ramp up, the COE signal goes high to enable the column output gates. When the WDRC signal is at or above the 1.25V threshold, the reset logic 272 holds the COE signal low, thus driving the column driver outputs low. The details of the reset logic 272 are illustrated in FIG.. 14. When HDEN goes low, an in¬ verter 876 disables a tri-state buffer 878 and enables the capacitor Cl of the watchdog RC timer 90 to charge. When HDEN returns high, the inverter 876 enables the buffer 878 which discharges the capacitor Cl to ground. Inverters 879 and 881 are preferably connected between ground and the input of the buffer 878 to allow the buffer 878 to discharge capacitor Cl when enabled. If HDEN fails to go high before the capacitor Cl charges to a level of approximately 1.25 volts, the threshold voltage of a Schmitt trigger 880, the output of the Schmitt trigger 880 goes high. When the output of the Schmitt trigger 880 goes high, the NOR gates 882, 884, and 886, and inverters 888, 890, and 892 force the XRPSC, CSD, and RPSC signals respectively high and the COE signal low. What have been described are various aspects of a video display interface which comprises a pre- sently preferred embodiment of the invention. It is understood that the foregoing description and accompanying illustrations are merely exemplary, the scope of the invention being defined by the appended claims. Various changes and modifications to the preferred embodiment will be apparent to those skilled in the art. For example, displays having other than 640 x 200 resolution; different arrangements of the display drivers; different types, arrangements, and amounts of video memory; and different memory maps can be substituted without varying from the spirit or scope of the invention. In addition, various component substitutions can be made, including but not limited to different latches, counters, or shift registers, for example. Moreover, the invention is not limited to use with electroluminescent displays but can also be used in conjunction with gas plasma and other similar dis¬ plays which benefit from constant current driving as well. All such changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, it is intended that all such changes and modifications and all other equivalents be covered by the appended claims.

Claims: WE CLAIM: 1. A video display interface, comprising: means for receiving video data; means for generating at least one control signal adapted to selectably control a plurality of substantially constant current display drive signals corresponding to said video data; and means for outputting said video data together with said at least one control signal for generating a video display. 2. The video display interface defined in claim 1 wherein said means for receiving video data comprises means for receiving video data at a first selected rate and wherein said means for outputting said video data comprises means for outputting said video data at a second selected rate higher than said first selected rate. 3. The video display interface defined in claim 1 including means for receiving program signals, and wherein said means for generating at least one control signal includes means responsive to said program signals for selectably controlling the generation of said at least one control signal. 4. A video display interface, comprising: means for receiving video data; means for generating at least one first con¬ trol signal adapted to selectably control a plurality of substantially constant current display drive signals corresponding to said video data; means for generating at least one second con¬ trol signal adapted to selectably control a plurality of pre-charge display drive signals corresponding to said plurality of substantially constant current dis¬ play drive signals; and means for outputting said video data together with said at least one first and said at least one second control signal for generating a video display. 5. The video display interface defined in claim 4 wherein said means for receiving video data comprises means for receiving video data at a first selected rate and wherein said means for outputting said video data, comprises means for outputting said video data at a second selected rate higher than said first selected rate. 6. The video display interface defined in claim 4 including means for receiving program signals, and wherein said means for generating at least one first control signal and said means for generating at least one second control signal include means responsive to said program signals for selectably controlling the generation of said at least one first control signal and said at least one second control signal respec¬ tively. 7. A video display system, comprising: video display interface means, including: means for receiving video data; means for generating at least one con¬ trol signal adapted to selectably control a plurality of substantially constant current display drive signals corresponding to said video data; and means for outputting said video data together with said at least one control signal; video display means; and display driver means responsive to said output video data and to said at least one control signal for generating a plurality of substantially constant current display drive signals corresponding to said output video data for driving said video display means. 8. The video display system defined in claim 7 wherein said video display means comprises electro¬ luminescent display means. 9. The video display interface defined in claim 7 wherein said means for receiving video data comprises means for receiving video data at a first selected rate and wherein said means for outputting said video data comprises means for outputting said video data at a second selected rate higher than said first selected rate. 10. A video display system, comprising: video display interface means, including: means for receiving video data; means for generating at least one first control signal adapted to selectably control a plurality of substantially constant current display drive signals corresponding to said video data; and means for generating at least one second control signal adapted to selectably control a plurality of pre-charge display drive signals corresponding to said plurality of substantially constant current display drive signals; means for outputting said video data together with said at least one first and said at least one second control signal; video display means; and display driver means responsive to said output video data and to said at least one first and said at least one second control signal for generating a plurality of substantially constant current display drive signals corresponding to said output video data and a corresponding plurality of pre-charge display drive signals for driving said video display means. 11. The video display system defined in claim 10 wherein said video display means comprises electro¬ luminescent display means. 12. The video display interface defined in claim 10 wherein said means for receiving video data comprises means for receiving video data at a first selected rate and wherein said means for outputting said video data comprises means for outputting said video data at a second selected rate higher than said first selected rate. 13. A video display interface, comprising: data receiving means for receiving video data; data storage means having a plurality of logical sections corresponding to a plurality of logical display sections for temporarily storing the received video data at a first selected rate; means for reading stored video data from each of said sections of said data storage means; and means for repetitively outputting said video data from each section of said data storage means simul¬ taneously so that said video data is output at a second selected rate higher than said first selected rate. 14. The video display interface defined in claim 13 wherein said data receiving means comprises means for receiving serial video data. 15. The video display interface defined in claim 13 wherein said means for reading and said means for outputting are adapted to read and output said video data at a second selected frame rate at least four said means for outputting comprising means for outputting stored video data simultaneously from each section of the data storage means corresponding to said means for reading. 16. The video display interface defined in claim 13, including: said data storage means comprising identical first and second data storage banks each having a plurality of logical sections corresponding to a plurality of logical display sections; means for alternately storing successive frames of video data In said first and second data storage banks; said means for reading comprising means for alternately retrieving stored video data from each of said sections of said first and second storage banks; said means for storing and said means for reading being synchronized to simultaneously store and read respectively to and from different storage banks; and said means for outputting comprising means for outputting stored video data simultaneously from each section of the data storage means corresponding to said means for reading. 17. The video display interface defined in claim 13 wherein said means for outputting comprises: first means for alternately storing a first portion of the stored video data read from each section of said data storage means and then simultaneously outputting video data from said first portion of each section simultaneously; second means for alternately storing a second portion of the stored video data read from each section of said data storage and then outputting video data from said second portion of each section simultaneously; said first and second means alternately stor¬ ing and outputting video data synchronously such that while one of said and first and second means is storing data, the other of said first and second means is outputting data. 18. An interface for a video display having a predetermined frame size, comprising: means for receiving bit-serial digital video data corresponding to pixels of said display; data storage means having a plurality of logical sections corresponding to a plurality of logical sections of said display for temporarily storing the received video data; timing means for establishing a selected time period; means for writing at least one frame of said serial video data into corresponding logical sections of said data storage means during said selected time period; means for repetitively reading video data from each logical section until said at least one frame of video data has been read out of said data storage means a selected plurality of times during said selected time period; and data output means connected to said means for reading for repetitively outputting video data simul¬ taneously from each logical section to said display until said at least one frame of video data has been output to said display a corresponding selected pluralit of times during said selected time period.

Inventors: CHANNING DEAN A, CHIANG LIH W, CHANNING, DEAN, A., CHIANG, LIH, W.
Applicants: CHERRY CORP, THE CHERRY CORPORATION
Application year: 1988
Main classification: G09G3
IPC codes: G09G3