Driving circuit and method for a liquid crystal display with a delayed pixel-erase function on power switch-off

Abstract: A ferroelectric liquid crystal display is driven by an improved circuit. A visual information is erased when the display system is switched off. By this configuration, "printing" due to after image is avoided.

Description: The present invention relates to a circuit and a method for driving and switching off a liquid crystal display device having a ferroelectric liquid crystal layer as indicated in the precharacterizing parts of claims 1 and 2. In such a prior art (DE-A-3 501 982) circuit and method, the driving means apply a drive signal as a so-called erasing signal to the display device before applying the normal drive signals for writing in selected information into the display device for visually indicating this information to a user. EP-A-0 211 599 discloses a liquid crystal display device having a plurality of liquid crystal pixels arranged in a matrix form, and driving circuits for applying drive signals to the signal electrodes and to scanning electrodes of the liquid crystal display. Furthermore, a means is provided for inverting the polarity of the voltage that is to be applied to the liquid crystal layer whenever a clock signal has counted a predetermined number. Because of this, a liquid crystal device is provided free from spurious signals in display due to the inversion of polarity of voltage applied to liquid crystal display elements. IEEE Transactions on Consumer Electronics, Vol. CE-28, No. 3, August 1982, pages 196 to 200, discloses a liquid crystal display device having a voltage dividing circuit for producing and supplying a plurality of different voltage levels to an operational and driving circuit for outputting the drive signals to the liquid crystal display device. Liquid crystal displays utilizing ferroelectric liquid crystals have memory functions which are desirable in some applications. However, if a displayed image remains for a long time in the liquid crystal display after the display system is switched off, the quality of the images displayed is degraded when the operation of the system is resumed, due to the "printing" of the previous displayed image (after image). It is the object of the invention to provide a driving circuit for liquid crystal display without the adverse effect due to "after image" after the display system is switched off. This object is solved by the features of claims 1 and 2. One embodiment of the invention is now explained in detail in connection with the drawings, in which Figures 1(A) and 1(B) are diagrams showing a driving circuit for liquid crystal display in accordance with the present invention. Figures 2(A) and 2(B) are schematic diagrams showing the driving signal during operation and the erasing signal respectively. Figure 3 is a timing chart illustrating the operation of the driving circuit in accordance with the present invention. Referring now to Figures 1(A) and 1(B), a driving circuit of liquid crystal display is illustrated in accordance with the present invention. The display to be driven by the circuit is a ferroelectric liquid crystal display comprising a number of pixels arranged in a matrix. The circuit consists of a voltage divider 1 and an operational circuit 3. The function of the voltage divider illustrated in Figure 1(A) is to divide the voltage between Vdd (+5V) and Vee connected to a voltage source of -20V through a transistor TR1 and output three intermediate voltage levels V₁, V₂, and V₃ to the operational circuit illustrated in Figure 1(B). The operational circuit produces necessary voltage levels by use of the three voltage levels and outputs driving signals 5 such as illustrated in Figure 2(A) to the liquid crystal display 7. The signal portion 9 causes a pixel to take "1" state while the signal portion 11 to take a "0" state. The four level appearing in Figure 2(A) are obtained in the operational circuit by carrying out the addition and the subtraction among the voltage levels supplied thereto. A pixel of the display takes a "1" state at the lowest level and a "0" state at the highest level. The two intermediate states cause no change to the pixels. The divider functions to modify the voltage levels supplied to the operational circuit in order to obtain driving signals as illustrated in Figure 2(B), when the display device is closed. This is accomplished by shorting the terminals of V₁ and V₂. For example, in case that the highest level corresponds to V₁ and the next high level to V₂, the next high level is elevated to the highest level. Next, the operation of the divider will be described. Four resistances R1, R2, R3, and R4 are connected between the Vdd terminal and the Vee terminal in series in order to produce divided levels at the V₁ terminal, the V₂ terminal and the V₃ terminal. A transistor TR5 is coupled with the resistor R2 in parallel. The base terminal of the TR5 is connected to the Vdd terminal through a transistor TR4 and a resistor R5. The base terminal of the TR4 is connected to a power-off terminal Poff through a resistor R6. The level at Poff is maintained at +5V (= the Vdd level) during operation and grounded (OV) when the display system is switched off. During operation, the TR4 and the TR5 are turned off and a predetermined voltage is given across the R2. When the display system is switched off and the Poff level is ground, the TR4 and the TR5 are turned on and the V₁ terminal and the V₂ terminal are shorted. The voltage level at the Poff terminal indicative of the on-off condition of the display system is supplied also to the base terminal of a TR3 through a delay circuit comprising a resistor RB and a capacitor CB. The TR3 is connected between the Vdd terminal and the base terminal of a transistor TR2 through a resistor R8. The emitter terminal of the TR2 is connected to the Vdd terminal through a resistor R9 and the collector terminal to the base terminal of a transistor TR1. A resistor R10 is connected between the base and emitter terminals of the TR1. During operation, the TR3 is turned off with the Poff level being 5V and the TR2 and the TR1 are kept turned on. When the Poff level is ground, the TR3 is turned on after the delay time of the delay circuit, followed by turning off of the TR2 and the TR1. Eventually, the Vee terminal is disconnected from the voltage source of -20V. Accordingly, when the display system is switched off, the modified driving signals are supplied to the liquid crystal display 7 and then the system is completely shut off after the time delay. This is schematically illustrated in Figure 3. While several embodiments have been specifically described, it is to be appreciated that modifications and variations can be made. Particularly, although a driving signal pattern is illustrated in Figure 2(A), various types of driving signal patterns have been employed.

Claims: A driving and switching off circuit (1,3) for a liquid crystal display device (7) having a ferroelectric liquid crystal layer and a plurality of pixels, each pixel having the capability of exhibiting two states in accordance with an electric field applied thereto, said circuit (1,3) comprising: driving means (3) for applying an erasing drive signal to said display device (7) in response to a turn-off signal, to cause all of said pixels to uniformly exhibit one of said two states; characterized by delay means (RB, CB) for providing a delay turn-off signal ending after a time delay during which said erasing drive signal is applied to the display device (7); and means (TR1,TR2) responsive to said delay means (RB,CB) for switching off said display device (7) at the end of said time delay. A method for driving and switching off a liquid crystal display device (7) having a ferroelectric liquid crystal layer and a plurality of pixels, each pixel having the capability of exhibiting two states in accordance with an electric field applied thereto, said method comprising the steps of: generating a turn-off signal to turn off said display device (7); applying an erasing drive signal, in response to said turn-off signal, to said display device (7) to cause all of said pixels to uniformly exhibit one of said two states; and delaying said turn-off signal to provide a delay turn-off signal ending after a time delay during which said erasing drive signal is applied to the display device (7); thereafter, at the end of said time delay, switching off said display device (7).

Inventors: SAKAYORI HIROYUKI, SAKAYORI, HIROYUKI
Applicants: SEMICONDUCTOR ENERGY LAB, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Application year: 1988
Main classification: G09G3
IPC codes: G09G3, G02F1