Digital-to-analog converter circuit

Abstract: For reduction in component elements, there is disclosed a digital-to-analog converter circuit for converting a digital input signal consisting of high-order bits and low-order bits into an analog output signal, comprising, a) a first digital-to-­ analog converting circuit (21) operative to produce a first current the amount of which corresponds to a value represented by the high-order bits, b) a memory circuit (23) storing an error data information in each address specified by each of values represented by the high-order bits, c) an arithmetic circuit (24) operative to carry out an arithmetic operation on the low-order bits and the error data information to produce an amended low-­ order bits, d) a second digital-to-analog converting circuit (22) operative to produce a second current the amount of which is corresponds to a value represented by the amended low-order bits, and e) an analog adder (25) operative to add the first current weighted by a predetermined factor to the second current to produce an analog output signal, so that the analog output signal precisely corresponds to the digital input signal.

Description: FIELD OF THE INVENTION This invention relates to a digital-to-analog converter circuit and, more particularly, to a regulation circuit for matching a digital input data information to an analog output data information. BACKGROUND OF THE INVENTION A typical example of the digital-to-analog converter circuit is illustrated in Fig. 1 and comprises a high-order digital-to-analog converting stage 1, a low-order digital-to-analog converting stage 2, and a weighted analog adder 3. In operation, high-order m-bits HB1 to HBm of a digital signal are supplied to the input nodes 4 of the high-order digital-to-analog converting stage 1, and low-order n-bits LB1 to LBn of the digital signal are concurrently supplied to the input nodes 5 of the low-order digital-to-analog converting stage 2. Each of the high-order digital-to-analog converting stage 1 and the low-order digital-to-analog converting stage 2 is formed to have a circuit arrangement well-known in the art such as, for example, a resistive ladder, so that no further description will be incorporated. When the digital signal is applied to the input nodes 4 and 5, the high-order digital-to-analog converting stage 1 is operative to produce a current the amount of which corresponds to a value represented by the high-order bits of the digital signal, likewise the low-order digital-to-analog converting stage 2 is operative to produce a current the amount of which corresponds to a value represented by the low-order bits of the digital signal. The current fed from the high-order digital-to-analog converting stage 1 is added to the current fed from the high-order digital-to-analog converting stage 3 by the analog adder 4, and the current fed from the high-order digital-to-analog converting stage 1 is weighted in the analog adder 3 to have a value which increased by a factor of 2 n with respect to the current fed from the low-order digital-to-analog converting stage 2. The digital-to-analog converter circuit thus arranged produces the total amount of current which corresponds to a value represented by the input digital signal supplied thereto, and the total amount of current is supplied from the output node of the analog adder 3 to an electric circuit (not shown). However, a problem had been encountered in the prior-art digital-to-analog converter circuit illustrated in Fig. 1 in that the number of bits is limited in view of accuracy of the conversion. In detail, a digital-to-analog converter is allowed to have the driftage of the output current only less than a half of the smallest increment, and the smallest increment is equivalent to the value represented by the least significant bit of the input digital signal. For this reason, the prior-art digital-to-analog converter circuit should have an accuracy of 1/2 m+n . If the input digital signal consists of 8 bits i.e., m=4 and n=4, the accuracy is calculated as 1/2⁸ x 100 = 0.4 %, and, in the case of the 18-bit input digital signal, the accuracy should be 0.0004 %. It is impossible to realize these accuracies without any trimming of component element such as the resistive ladder. One of the approaches to form the digital-to-analog converter circuit without any trimming has been disclosed in Japanese patent application laid-open (Kokai) No. 168522/1982. The circuit arrangement of the digital-to-analog converter circuit disclosed in the Japanese patent application laid-open is illustrated in Fig. 2 of the drawings and largely comprises an input latches 11 for temporary storing an input digital signal, a high-order digital-to-analog converting stage 12 supplied from the input latches 11 with high-order bits of the input digital signal to produce a current corresponding to a value represented by the high-order bits of the input digital signal, a low-order digital-to-analog converting stage 13 supplied from the input latches 11 with low-order bits of the input digital signal to produce a current corresponding to a value represented by the low-order bits, a programmable memory 14 such as an erasable programmable read-only memory storing digital data for error correction, an auxiliary digital-to-analog converting stage 15 supplied from the programmable memory 14 with the digital data and producing a correction current corresponding to the error value inherent in this digital-to-analog converter circuit, an analog adder 16 supplied with the currents fed from the low-order digital-to-analog converter stage 13 and the digital-to-analog converter stage 15 for error correction, and an analog adder 17 supplied with the currents fed from the analog adder 16 and the high-order digital-to-analog converter stage 12 to produce an output current corresponding to a value represented by the input digital signal. The digital-to-analog converter circuit thus arranged is free from the expensive trimming process, because the programmable memory 14 preserves the digital data representative of the error values inherent in that digital-to-analog converter circuit for production of the correction current. However, another problem is encountered in the digital-to-analog converter circuit disclosed in the above mentioned patent application laid-open in circuit complexity and, accordingly, the number of component element. This is because of the fact that the correction current produced by the digital-to-analog converter stage 15 on the basis of the digital data supplied from the programmable memory 14 is added to the current produced by the low-order digital-to-analog converting stage. Digital-to-analog converting circuits according to the preamble of claim 1 are known from Patents Abstracts of Japan, Vol. 2, No. 88 (E-78) (4027) and ELECTRONICS LETTERS, November 23, 1978, pages 790-791. To carry out an arithmetic operation between the low-order bits and the stored error data information, a digital adder-subtracter or a digital full adder can be used. Examples of such circuits are shown in Figures 3 and 4. It is an object of the invention to provide a digital-to-analog converter which is free from the expensive trimming process. It is an further object of the invention to provide a digital-to-analog converter circuit which has a simple circuit arrangement for regulation of an analog output signal. These objects are achieved by a digital-to-analog converter circuit as defined in claim 1; the dependent claims are related to further developments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of a digital-to-analog converter circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a block diagram showing the circuit arrangement of a prior-art digital-to-analog converter circuit; Fig. 2 is a block diagram showing the circuit arrangement of another prior-art digital-to-analog converter circuit disclosed in Japanese patent application laid-open No. 168522/1982; Fig. 3 is a block diagram showing the circuit arrangement of a digital-to-analog converter circuit useful for understanding the present invention; Fig. 4 is a block diagram showing the circuit arrangement of another a digital-to-analog converter circuit useful for understanding the present invention; Fig. 5 is a block diagram showing the circuit arrangement of an embodiment of a digital-to-analog converter circuit according to the present invention; Fig. 6 is a block diagram showing the circuit arrangement of a further embodiment of a digital-to-analog converter circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to Fig. 3 of the drawings, there is shown the circuit arrangement of a digital-to-analog converting circuit which comprises a high-order digital-to-analog converter circuit 21 serving as first digital-to-analog converting means, a low-order digital-to-analog converting circuit 22 serving as second digital-to-analog converting means, a read only memory 23 serving as memory means, an adder-subtracter 24 serving as arithmetic means, and an analog adder 25. All of the circuits and memory 21 to 25 are fabricated on a single semiconductor chip 26, typically a silicon chip, together with electric circuits (not shown) using an analog output signal fed from the analog adder 25. The high-order digital-to-analog converter circuit 21 is supplied with high-order m-bits HB1 to HBm of a digital input signal and operative to produce a first current the amount of which corresponds to a value represented by the m-bits of the digital input signal. The high-order digital-to-analog converter circuit 21 is supplied with the m-bits of the digital input signal, so that the high-order bits represents one of 2 m values. Then, the amount of first current produced by the converter circuit 21 is stepwise increased by the increment in value. The high-order m-bits are simultaneously supplied to the read only memory 23 as an address signal, and the read only memory 23 has 2 m memory addresses each fixedly storing an n-bit error data information. The n-bit error data information represents a deviation from the theoretical amount of first current in terms of a value represented by the least significant bit of the digital input signal or the lowest bit of low-order n-bits LB1 to LBn. The read only memory 23 thus arranged supplies one of the n-bit error data informations stored in the address specified by the high-order bits to first input nodes of the adder-subtracter 24. The adder-subtracter 24 further has second input nodes where the low-order n-bits of the digital input signal are supplied, so that the adder-subtracter 24 carries out an arithmetic operation, either addition or subtraction depending upon the n-bit error data information, on the n-bit error data information and the low-order bits LB1 to LBn to form an amended low-order bits. The low-order digital-to-analog converter circuit 22 is supplied with the amended low-order bits fed from the adder-subtracter 24 and operative to produce a second current the amount of which corresponds to a value represented by the amended low-order bits. Each of the digital-to-analog converter circuit 21 or 22 largely comprises a switching circuit associated with a decoder circuit and a resistor network, however the circuit arrangement of each digital-to-analog converter circuit 21 or 22 is well known in the art, so that no further description will be incorporated. Both of the first and second currents are supplied to the analog adder 25, and the first current is weighted by a predetermined factor so as to cause the amount of first current to correspond to the high-order bits HB1 to HBm. As described above, the amended low-order bits reflects the error data information, so that an analog output signal fed from the analog adder 25 precisely corresponds to the digital input signal. Of course, no correction is made for the low-order digital-to-analog converter circuit 22, however the digital-to-analog converter circuit illustrated in Fig. 3 is improved in accuracy to be 1/2 n times better than the prior-art digital-to-analog converter circuit without trimming. Moreover, no digital-to-analog converter circuit for correction use is incorporated in the digital-to-analog converter circuit illustrated in Fig. 3, so that the circuit arrangement is simplified with respect to the digital-to-analog converter circuit disclosed in Japanese patent application laid-open No. 168522/1982. Turning to Fig. 4 of the drawings, another circuit arrangement of a digital-to-analog converter circuit useful for understanding the present invention is illustrated and largely comprises a high-order digital-to-analog converter circuit 31 serving as first digital-to-analog converting means, a low-order digital-to-analog converting circuit 32 serving as second digital-to-analog converting means, a programmable read only memory 33 serving as memory means, a digital adder 34 serving as arithmetic means, and an analog adder 35. All of the circuits and memory 31 to 35 are fabricated on a single semiconductor chip 36, typically a silicon chip, together with electric circuits (not shown) using an analog output signal fed from the analog adder 35. In this implementation, the high-order digital-to-analog converter circuit 31, the low-order digital-to-analog converter circuit 32, read only memory 33 and the analog adder 35 are similar in construction to those of the digital-to-analog converter circuit illustrated in Fig. 3, so that detailed description for those circuits is omitted for the sake of simplicity. The digital-to-analog converter circuit illustrated in Fig. 4 uses a digital full adder 34; the description will be focused upon the digital adder 34. The digital adder 34 has two sets of input nodes each consisting of a error data information and the low-order bits of the input digital signal are supplied to the two sets of input nodes. With the error data bits and the low-order bits, the digital adder performs an addition to produce an amended low-order bits. This addition sometimes results in an amended low-order bits consisting of a certain bits more than the input data bits because of a carry bit, so that the digital adder 35 has output nodes increased in number than the input nodes by one, and the digital adder serves as a full adder. The output nodes of the digital adder 34 are coupled in parallel to the input nodes of the low-order digital-to-analog converter circuit 32. In operation, when an digital input signal is supplied to the digital-to-analog converter circuit illustrated in Fig. 4, the high-order bits HB1 to HBm are supplied in parallel to the input nodes of the high-order digital-to-analog converter circuit 31 and to the address nodes of the memory cells 37. With the high-order bits HB1 to HBm of the digital input signal, an error data information corresponding to the value represented by the high-order bits are read out from the memory cells 37. The error data information is transferred to the full adder 34. The low-order bits of the digital input signal have been already supplied, so that the error data bits are added to the low-order bits of the digital input signal to produce an amended low-order bits. As a result of the addition, the amended low-order bits may include a carry bit. The amended low-order bits are supplied to the low-order digital-to-analog converter circuit 32, and a second current takes place at the output node of the low-order digital-to-analog converter circuit 32 based on the amended low-order bits. A first current also takes place at the output node of the high-order digital-to-analog converter circuit 31. The first current is weighted by a predetermined factor so as to reflect the value of the high-order bits in the digital input signal. Then, the analog adder 35 delivers an analog output signal the amount of which corresponds to the value represented by the digital input signal. In a modification, the digital adder 34 may be replaced by a digital subtracter, and, similarly, the output nodes of the subtracter are arranged to be different in number to the input nodes thereof. Turning to Fig. 5 of the drawings, a circuit arrangement of a digital-to-analog converter circuit embodying the present invention is illustrated and largely comprises a high-order digital-to-analog converter circuit 41 serving as first digital-to-analog converting means, a low-order digital-to-analog converting circuit 42 serving as second digital-to-analog converting means, a programmable read only memory 43 serving as memory means, a full adder 44 serving as arithmetic means, and an analog adder 45. All of the circuits and memory 41 to 45 are fabricated on a single semiconductor chip 46, typically a silicon chip, together with electric circuits (not shown) using an analog output signal fed from the analog adder 35. In this implementation, the high-order digital-to-analog converter circuit 41, the low-order digital-to-analog converter circuit 42, the full adder 44 and the analog adder 45 are similar in construction to those of the digital-to-analog converter circuit illustrated in Fig. 4, so that no further description for those circuits is hereinunder incorporated for the sake of simplicity. The digital-to-analog converter circuit illustrated in Fig. 5 is characterized by the programmable read only memory 43, the description will be focused upon the programmable read only memory 43. The programmable read only memory 43 comprises a plurality of memory cells 47 grouped by four corresponding to four error data bits of an error data information, a write-in circuit 48 operative to write each error data information into each of the addresses, a single sense amplifier circuit 49 capable of decide a logic level, a high-logic level or a low-logic level, of an error data bit, an address counter 50 responsive to a clock signal CL to allow the four error data bits of an error data information to be serially transferred from the memory cells 47 to the sense amplifier circuit 49, and a serial-in-parallel-out shift register circuit 51. Each of the memory cells 47 is of the fusible-link type, however another type of memory cells such as, for example, a floating-gate type may be used in another implementation. The error data information stored in the memory cells has a value representing the total sum of the deviation from the theoretical amount of the first current and a certain positive value. The deviation is determined in terms of the value of the least significant bit, and the positive value is selected in such a manner that no negative total sum is avoided. The programmable read only memory 43 thus arranged operates with a source of single voltage level, so that the circuit arrangement is simplified in comparison with the implementation using the adder-subtracter. The digital-to-analog converter circuit illustrated in Fig. 5 is further advantageous in reduction in occupation area. This is because of the fact that only one sense amplifier circuit 49 is incorporated in the memory 43. In general, if the memory cells 47 are relatively small in number, the peripheral circuits such as a sense amplifier circuit occupies a larger amount of area in comparison with the memory cells. In this instance, the memory cells 47 are formed by 2⁴ x 4 = 64 cells, so that reduction of the peripheral circuit is conducive to reducing the occupation area. Although the single sense amplifier circuit 49 is necessary to be accompanied by the address counter circuit 50 and the shift register circuit 51, three sense amplifier circuits are removed from the memory 43, thereby being capable of reduction in occupation area. On the other hand, the full adder 44 has two sets of input nodes each consisting of four nodes, and the four error data bits of the error data information and the four low-order bits of the input digital signal are supplied to the two sets of input nodes. With the error data bits and the low-order bits, the full adder performs an addition to produce an amended low-order bits. This addition sometimes results in an amended low-order bits consisting of five bits, so that the full adder has five output nodes coupled in parallel to the input nodes of the low-order digital-to-analog converter circuit 42. In operation, when an digital input signal is supplied to the digital-to-analog converter circuit illustrated in Fig. 5, the high-order bits HB1 to HBm are supplied in parallel to the input nodes of the high-order digital-to-analog converter circuit 41 and to the address nodes of the memory cells 47. With the high-order bits HB1 to HBm of the digital input signal, an error data information corresponding to the value represented by the high-order bits are read out from the memory cells 47. The address counter circuit 50 allows the error data bits of the error data information to be serially transferred to the sense amplifier circuit 49 in response to the clock signal CL, so that the error data bits are supplied in succession to the sense amplifier circuit 49, thereby being decided the logic level thereof. Each of the error data bits is supplied to the serial-to-parallel shift register circuit 51 after decision of the logic level thereof and stored in the serial-to-parallel shift register circuit 51. When all of the error data bits are stored in the shift register circuit 51, the error data information is transferred to the full adder 44. The low-order bits of the digital input signal have been already supplied, so that the error data bits are added to the low-order bits LB1 to LBn of the digital input signal to produce an amended low-order bits. As a result of the addition, the amended low-order bits may include a carry bit, then the total number of the amended low-order bits are selected to be five. The amended low-order bits are supplied to the low-order digital-to-analog converter circuit 42, and a second current takes place at the output node of the low-order digital-to-analog converter circuit 42 based on the amended low-order bits. A first current also takes place at the output node of the high-order digital-to-analog converter circuit 41. The first current is weighted by a predetermined factor so as to reflect the value of the high-order bits in the digital input signal. Then, the analog adder 45 delivers an analog output signal the amount of which does not correspond to the value represented by the digital input signal, because a small amount of current corresponding to the certain positive value is included in the analog output signal. This means that the analog output signal includes a constant d. c. current , however the constant d. c. current does not affect an operation of a certain electric application such as, for example, an audiofrequency system. Turning to Fig. 6 of the drawings, there is shown the circuit arrangement of a digital-to-analog converter circuit according to another embodiment of the present invention. The digital-to-analog converter circuit illustrated in Fig. 6 is similar in construction to the digital-to-analog converter circuit illustrated in Fig. 5 except for the level shifting circuit 61, so that circuits corresponding to those denoted by reference numerals 41 to 45 are designated by the same reference numerals and detailed description will be omitted for the sake of simplicity. The analog adder 45 is coupled to the level shifting circuit 61, and the circuit arrangement of the level shifting circuit 61 is well known in the art, so that no further description thereof is incorporated. As described hereinbefore, the analog output signal of the analog adder 45 includes a constant d. c. current, and this d. c. current does not affect some application such as a audiofrequency device. However, it is better to eliminate the d. c. current from the analog output signal in some application, so that the level shifting circuit 61 is arranged to cancel the d. c. current caused by the predetermined value in each of the error data informations. As a result, the digital-to-analog converter circuit illustrated in Fig. 6 can find wide applications.

Claims: A digital-to-analog converting circuit for converting a digital input signal (HB1 to HBm; LB1 to LBn) into an analog output signal, said digital input signal consisting of high-order bits (HB1 to HBm) representing one of plural values and low-order bits (LB1 to LBn) including the least significant bit, comprising: a) first digital-to-analog converting means (41) operative to produce a first analog signal the amount of which corresponds to said one of said plural values; b) read only memory means (43) storing pieces of error data information in the digital form, and allowing said pieces of error data information to be selectively read out therefrom; c) arithmetic means (44) operative to carry out an arithmetic operation between said low-order bits and one of said pieces of error data information to amend said low-order bits; d) second digital-to-analog converting means (42) operative to produce a second analog signal the amount of which is corresponds to a value represented by the amended low-order bits; and e) an analog adder (45) operative to add said first analog signal to said second analog signal to produce said analog output signal, said first analog signal being weighted by a predetermined factor in said analog adder, characterized in that said memory means is implemented by a programmable read only memory comprising a plurality of memory cells (47) respectively assigned addresses and each storing one of said pieces of error data information for each of said plural values, a write-in circuit (48) for writing said pieces of error data information into said memory cells in a non-volatile manner, and a read-out circuit (49/50/51) operative to read out one of said pieces of error data information from the address specified by said high-order bits, each of said pieces of error data information being represented by a predetermined number of error data bits, said read-out circuit comprising an address counter (50) responsive to a clock signal (CL) and operative to successively specify the error data bits of said one of pieces of error data information, a single sense amplifier (49) successively supplied from said plurality of memory cells with the error data bits of said one of said pieces of error data information, and operative to decide a logic level of each error data bit, and a serial-in-parallel-out shift register (51) successively supplied from said single sense amplifier with the error data bits of said one of said pieces of error data information, and operative to simultaneously transfer the error data bits to said arithmetic means (44). A digital-to-analog converting circuit as set forth in claim 1, in which each of said error data informations has a value determined in terms of the value of said least significant bit. A digital-to-analog converting circuit as set forth in claim 1, in which said error data bits are equal in number to said low-order bits. A digital-to-analog converting circuit as set forth in claim 1, in which each of said memory cells is of the fusible-link type. A digital-to-analog converting circuit as set forth in claim 1, wherein said digital-to-analog converting circuit further comprises processing means operative to execute a corrective operation on said first digital-to-analog means so as to form said error data informations. A digital-to-analog converting circuit as set forth in claim 1, in which said arithmetic means are formed by an adder-subtracter. A digital-to-analog converting circuit as set forth in claim 1, in which said arithmetic means are formed by an adder. A digital-to-analog converting circuit as set forth in claim 1, in which said analog adder is coupled to a level shifting circuit. A digital-to-analog converting circuit as set forth in claim 1, in which said error data information has a plurality of error data bits equal in number to said low-order bits, wherein said arithmetic means are formed by a full adder having a plurality of output nodes greater in number than input nodes thereof by one, said output nodes of said full adder being coupled in parallel to input nodes of said second digital-to-analog means. A digital-to-analog converting circuit as set forth in claim 1, in which each of said first and second analog signals is represented by a current signal.

Inventors: INAMASU NAMI C O NEC CORPORATI, SUGUWARA MITSUTOSHI C O NEC CO, INAMASU, NAMI C/O NEC CORPORATION, SUGUWARA, MITSUTOSHI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: H03M1
IPC codes: H03M1