CAVITY-UP-CAVITY-DOWN MULTICHIP INTEGRATED CIRCUIT PACKAGE

Abstract: A multichip integrated circuit comprising a thin planar body (10 and 20) which has top (20b) and bottom (10b) major surfaces. Conductors, (12a) for carrying electrical signals, are integrated into the body and include input/output terminals (12) on one portion of the bottom surface. Downward-facing cavities (11-1) for holding respective high power integrated circuit chips (30) extend from another portion of the bottom surface into the body, and upward-facing cavities (21-1 through 21-6) for holding respective low power integrated circuits (30) extend from the top surface into the body. Small thermal resistance for the high power chips is achieved, and footprint is simultaneously minimized by locating the upward-facing cavities over the terminals.

Description: CAVITY-UP-CAVITY-DOWN MULTICHIP INTEGRATED CIRCUIT PACKAGE This disclosure relates to integrated circuit packages; and more particularly, it relates to multichip packages which have a small footprint and provide thermal paths for cooling both high-power and low-power integrated circuit . Initially in the past , integrated circuit chips were packaged separately. Such single-chip packages encapsulated a chip to protect it from contamination, and to provide input/output terminals by which the chip could be soldered "into a printed circuit board. Typically, the packages were made of plastic or ceramic. Subsequently, multichip integrated packages were developed which encapsulated several chips. One attractive feature of multichip packages is that they provide low capacitance interconnections between the chips within tr package, and thus the delay of inter chip signal propagati is reduced. Usually, the number of chips which a encapsulated in a multichip package is between two a twenty. A problem, however, which is aggravated multichip packages is how to keep the package fr overheating. This is because all of the chips in a packa dissipate power which cause the package to heat up. resolve such a heat-dissipation problem, it is ve desirable to not compromise the size of the package' footprint. A package's footprint is the area which occupies on a printed circuit board, and it should be ke as small as possible so that more packages can be placed the board. In the past- > a cavity-down multichip pac a was often used whenever some of the chips to be packaged h a high power dissipation. Such a package is comprised of thin body having top and bottom major surfaces; chips a held in downward-facing cavities _which extend from t bottom surface into the body; and input/output pins a disposed in rows on the periphery of the bottom surfa around the cavities. This package will cool the high pow dissipating chips because it provides a small therm resistance path from the downward-facing cavity tσ the t surface. However, it has been determined by the prese inventor that the cavity-down package is very inadequate f handling the frequent situation where some but not all the chips have a high power dissipation. Specifically, such a case, the present inventor has found that t footprint of the package can be reduced by over 100% witho compromising the cooling for the high power chips. BRIEF DESCRIPTION OF THE DRAWINGS Various embodiments ar described in the Detailed Description in conjunction wit the accompanied drawings wherein: FIG. 1 is a top view of one embodiment- FIG. 2 is an enlarged sectional view taken alon lines 2-2 in FIG. 1; FIG. 3 is a set of equations which indicate ho the embodiment of FIGs. 1 and 2 has a reduced footprint; FIG. 4 compares an actua package that is constructed according to FIGs. 1 and 2 to prior art cavity down package; and FIG. 5 is an enlarged sectional view of anothe embodiment. DETAILED DESCRIPTION Referring now to FIGs. 1 and 2, a preferre embodiment of an integrated circuit package will be described i detail. This embodiment is comprised of two thin plana members 10 and 20 which are respectively made of alumin ceramic and- copper tungsten. Member 10 has major surface 10a and 10b, and member 20 has major surfaces 20a and 20b One aperture 11-1 passes through surfaces 10a and 10b o member 10 at its center; and six apertures 21-1 through 21- pass through surfaces 20a and 20b of member 20 around it periphery. Surfaces 10a and 20a are permanently joine together by brazing or by an epoxy. Surface 10a blocks al of the apertures 21-1 through 21-6 in member.20, and surfac 20a blocks aperture 11-1 in member 10. As a result oppositely facing cavities are formed for holding integrate circuit chips 30. Letters A through I in FIGs. 1 and identify corresponding points in these cavities. Letter indicates a pad for attaching the chips in the cavit letter E indicates a pad for bonding a signal-carrying wir to the chip, and all of the other letters simply indicat various edges. Thin flat lids (not shown) can be attache to the surfaces 10b and 20b to cover the cavities. Input/output pins (I/O pins) 12 extend fr surface 10b in a direction which is herein referred to a downward. That cavity which is formed by aperture 11-1 i also facing downward. By comparison, the cavities which a formed by apertures 21-1 through 21-6 are facing upwar All of the I/O pins 12 are arranged in four rows which ς around the periphery of surface 10b. Conductors, only on of which is shown as 12a, are integrated into member 10 ar connect the pins 12 to the wire bond pads. These I/O pins 12 lie beneath the aperture- 21-1 through 21-6 in member 20; and due to this arrangement, tnε footprint of the disclosed package is substantially reduced in comparison to the footprint of a conventional cavity-down package. High power integrated circuit chips are held in the downward-facing cavity since heat is conducted from them along a low thermal resistance path 31 to a heat sink (not shown) on surface 20b. Low power integrated circuit chips are held in the downward- acing cavities, and heat is conducted from them along a higher thermal resistance path 32. When member 10 is made of alumina ceramic and member 20 is made of copper tungsten, and surface 20b is air cooled, the thermal resistance of paths 31 and 32 respectively are about 4° C/watt and 25 C/watt. With those same materials and surface 20b being liquid cooled, the •thermal resistance of paths 31 and 32 respectively are about 1/2° C/watt and 6° C/watt. Thus, in the latter case for example, chip 30 in the downward-facing cavity could dissipate 15 watts; each chip in the upward-facing cavity could dissipate 1-1/4 watts; and the temperature of every chip would only be 7-1/2° C above the temperature of the coolant . Preferably, in the above cases, chips for the upward-facing cavities dissipate less than 2 watts. Such chips include bipolar static RAM chips, small scale integration logic chips, and CMOS dynamic RAMs . Also, preferably, chips for the downward- acing cavities dissipate more than 2 watts. Such chips include custom large scale bipolar chips, semicustom ECL gate arrays, and microcomputer chips . A numerical example which illustrates the degree to which the footprint is reduced by the above described integrated circuit package is given in FIG. 3. There, equation 1 states s condition wherein cavities 21-3 and 21-^ are each one-quarter-inch on a side, and the cavity 11-1 is one-half-inch on a side. Under this condition, the width of the disclosed package would be about 1/4" + 1/2" + 1/4" or one inch; and consequently its footprint would be about one square inch. This is stated by equation 2 . A-reasonable width of four rows of I/O pins 12 is about three-eighths of an inch. Thus, the width of a conventional cavity-down package which has cavities as given by equation 1 would be 3/8" +1/4" + 1/2" + 1/4" + 3/8" or one and three-quarters inches. This is stated by equations 3 and 4. Such a cavity-down package would have a footprint of 3.06 square inches. Thus, the percent area saved by the disclosed integrated circuit package is more than 200% " l Figure 4 compares an actual package that is constructed according to FIGs. 1 and 2 to the prior art cavity-down package. Both of these packages hold eight small low power chips, and one large high power chip. In the disclosed package, which is on the left, the eight small low power chips are positioned around the periphery of the top surface; the input/output pins are positioned below those eight chips on the bottom surface; and the one large high power chip is centrally located on the bottom surface. By comparison, in the prior art cavity- down package which is shown on the right, all of the high power and low power chips as well as the I/O pins are located on the bottom surface. Consequently, the footprint of the package on the right is more than 100% larger than the footprint of the package on the left. Turning now - FIG. 5, another embodiment of the invention will be described. This embodiment is comprised of a planar member 40 which has major surfaces 40a and 40b, and another planar member 50 which has major surfaces 50a and 50b. Input/output pins 41 extend in a downward irection from the periphery of surface 40b, and one or mer downward-facing cavities 42 also extend from that surfac partway through member 40. In other words, member 4 differs from the previously described member 10 of FIGs. and 2 in that no apertures completely penetrate member 40. By comparison, member 50 does contain apertures 5 which penetrate its major surfaces. Also, surface 50a i permanently joined to surface 40a, and surface 40a block the apertures 51. Thus upward-facing cavities are forme for holding respective integrated chips 60. Some of thes upward-facing cavities in member 50 partially overlie th downward-facing cavities 42 in member 40. Consequently, th number of chips which the FIG. 4 embodiment holds for given footprint size is increased over the previousl described embodiment. Heat is conducted from the chips 60 in th downward-facing cavities 42 along a thermal path 61, an heat is conducted from the chips 60 in the upward-facin cavities along a thermal path 62. By always providing solid portion of member 50 directly over each downward- facing cavity 42, path 61 will have a lower thermal resistance than path 62. For example, when member 40 i made of ceramic and member 50 is made of copper tungsten an surface 52b is liquid cooled, the thermal resistances 61 an 62 respectively are about 2° C/watt and 6 C/watt. Various embodiments have now been described in detail. In addition, however, many changes and modifications can be made to these details without departing from the nature and spirit of the disclosure. For example, the top member 20 in the FIG. 2 embodiment as well as the top member 40 in the FIG. 4 embodiment can be constructed of metals other than copper tungsten such as copper-molybdenum-copper, and they can also be constructed of ceramic. Further, if members 10 and 20, -3- r memDers 40 and 50, are both made of ceramic, then thev can be co-fired together as a single integrated body. Also, the input/output pins have the FIG. 2 and FIG. 4 embodiments can be replaced with other terminals such as those which are suitable for surface mounting.

Claims: WHAT IS CLAIMED IS: 1. A cavity-up-cavity-down integrated circuit package, comprising: top and bottom thin planar members having respective major surfaces which are joined together; each of said planar members having at least one aperture which penetrates that respective member; each aperture in said top planar member being blocked by the major surface of said bottom planar member, and vice versa, to form oppositely facing and misaligned cavities for holding integrated circuit chips; and conductors, integrated into said bottom member, for carrying electrical signals to said chips; said conductors including input/output t.erminals which are spaced from said cavities in said bottom member and aligned with said cavities in said top member. 2. An integrated circuit package according to claim 1 wherein said bottom member has just one cavity, and wherein said input/output terminals surround said one cavity. 3. An integrated circuit package according to claim 2 wherein said top member has multiple cavities which are aligned with said input/output terminals. 4. An integrated circuit package according to claim 3 wherein a high-power integrated circuit chip is in said one cavity and respective low-power integrated circuit chips are in said multiple cavities. 5. An integrated circuit package according to claim 4 wherein said bottom member is made of a material having one thermal conductivity, and said top member is made of material having a substantially higher thermal conductivity. - l i ¬ ft. A cavity-up-cavity-down integrated circui package, comprising: a thin planar body which has top and bottom majo surfaces; conductors, for carrying electrical signals integrated into said body and having input/output terminal on one portion of said bottom surface; cavities, which extend from said major surface into said body, and which are shaped to hold respectiv integrated circuit chips; a subset of said cavities being downward-facing i said bottom surface and spaced apart from said terminals: and . the remainder of said cavities being upward facin in said top surface and at least some of them bein positioned over said terminals. I . An integrated circuit package according to claim wherein said body is comprised of two thin pf'anar member which are joined together: each member having respectiv apertures that are blocked by the opposite member to thereb form said cavities. 8. An integrated circuit package according to claim wherein said body is comprised of two thin planar member which are joined together; one member having apertures tha are blocked by- the opposite member to thereby form upward facing cavities; said opposite member having downward-facin cavities which are self-contained in that member; and som of said upward-facing cavities overlie portions of sai downward-facing cavities. 9. An integrated circuit package according to claim wherein each downward-facing cavity contains a high-powe integrated circuit chip, and .each upward-facing cavit contains a low-power integrated circuit chip. 10. An integrated circuit package according to claim wherein said bottom surface has just one downward-facin cavity and said terminals surround that one cavity. II. An integrated circuit package according to claim wherein some of said cavities contain more than one chip.

Inventors: TUSTANIWSKYJ JERRY IHOR, TUSTANIWSKYJ, JERRY, IHOR
Applicants: UNISYS CORP, UNISYS CORPORATION
Application year: 1988
Main classification: H01L25
IPC codes: H01L23, H01L25