CENTRIFUGE CONTROL SYSTEM HAVING DUAL PROCESSORS

Abstract: The present invention relates to control architecture for a centrifuge motor speed control system having dual processors. The processors are configured in a master-slave relationship for some predetermined subset of instrument control functions during the execution of which the slave operates under the direction of the master to effect that subset of control functions. However, each of the processors is independently responsive to a speed signal from a tachometer and is indepenently capable of controlling the additional instrument control function of conditionally coupling the motor to a source of energy.

Description: This invention relates to a control system for a centrifuge instrument and, in particular, to a control system having a control architecture that utilizes two processors. A centrifuge rotor is a relatively massive member adapted to expose a sample of a liquid to a centrifugal force field. To create the force field the rotor is rotated to a relatively high rotational speed. However, if the rotational speed to which the rotor is accelerated is too high the possibility exists that the rotor may fail catastrophically. In order to prevent this failure from occurring most centrifuge instruments utilize a microprocessor-based speed control system having a single processor therein to limit the maximum rotational speed to which the rotor is subjected to a value which is well below the speed of catastrophic failure of the rotor. The possibility exists in a microprocessor-based control system that the processor way fail, thus vitiating the speed control function performed thereby. To guard against this deleterious consequence control schemes are known which monitor the operability of the processor. One example of a system with such a "watchdog" circuit is the RC-5C Centrifuge instrument manufactured and sold marketed by the Medical Products Department of E. I. du Pont de Nemours and Company. Inc. This system includes a capacitor which, under the control of the processor, is periodically discharged during the normal operation of the control system. The discharged capacitor prevents a system reset command from being issued. Should the processor fail the capacitor would not be discharged and a system reset would occur. One of the responses to a system reset is the interruption of power to the instrument, thus stopping rotor rotation. Other examples of microprocessor-based systems, though not specifically applied to a centrifuge instrument, are disclosed in the turbine control systems of United States Patents 4,635,209 (Hwang et al.), 4,494,207 (Chang et al.), 4,494,208 (Chang) and 4,319,320 (Sato et al.). A control system for a centrifuge instrument according the preamble of claim 1 is disclosed in WO-A-87/00 770. The control system comprises a processor operative to limit the maximum speed of the motor by coupling of the power source to the motor. The problem of the invention is to provide a control system for a centrifuge instrument having a high degree of safety and reliability. The problem is solved, according to the invention, with the features of the claim. The present invention relates to a control system for a centrifuge instrument having a motor with a shaft, the motor being connected to a source of energy. The motor is operative to rotate the shaft to a predetermined rotational speed. A tachometer is associated with the shaft and is operative to generate a signal representative of the actual rotational speed thereof. The control system includes a programmable controller operative to provide a predetermined set of instrument control functions including the function of conditionally coupling of the source to the motor. In accordance with the present invention the programmable controller has a first and a second processor therein, the processors being configured in a master-slave relationship for some predetermined subset of the instrument control functions during the execution of which the slave operates under the direction of the master to effect that subset of control functions. However, each of the processors is independently responsive to the speed signal from the tachometer and is independently capable of controlling the additional instrument control function of conditionally coupling the source to the motor. The invention will be more fully understood from the following detailed description thereof, taken in connection with the accompanying drawings, which form a part of this application, and in which: Figure 1 is a highly stylized pictorial representation of a centrifuge instrument with which a dual processor control system, shown in block diagram form, in accordance with the present invention may be used; Figure 2 is an overall functional diagram of the division of responsibility between the first and second processors used in the control system of the present invention; Figure 3A is a flow diagram of the subroutine used by one of the processors in the control system of the present invention to generate an enabling control signal to the motor power drive which conditionally couples the source to the motor while Figure 3B is a flow diagram of the subroutine used by the other of the processors for the same purpose. An Appendix of the listing for each of the processors used in the control system of the present invention is attached to and forms part of this application. The listing is set forth in MC6809 and MC6803 assembly languages. The listing, pages A-1 through A-15 inclusive, is appended to the application after the abstract. Throughout the following detailed description of the invention similar reference numerals refer to similar elements in all figures of the drawings and in the Appendix. Shown in Figure 1 is a stylized pictorial representation of a centrifuge instrument generally indicated by reference character 10 embodying the teachings of the present invention. The instrument 10 includes a framework schematically indicated at 12. The framework 12 supports a chamber, or bowl, 14. The interior of the bowl 14 defines a generally enclosed chamber 16 in which a rotating element, or rotor, 18 may be received. Access to the chamber 16 on the interior of the bowl 14 is afforded through a lid or door 20. The bowl 14 may be provided with suitable evaporator coils, not shown, in the event that it is desired to refrigerate the bowl 14 and the rotor 18 and its contents. One or more energy containment members, or guard rings, 22 is carried by the framework 12. The guard ring 22 is arranged concentrically with respect to the bowl 14 and serves to absorb the kinetic energy of the rotor 18 or fragments thereof should a catastrophic failure of the rotor 18 occur. The guard ring 22 is movably mounted within the framework 12, as schematically indicated by the rollers 24, to permit free rotation thereof to absorb the rotational component of the energy of the rotor fragments. It is important to absorb the energy of the rotor and to contain the possible fragments thereof which, if permitted to exit the instrument, may cause injury to an operator. A drive motor 30, such as a brushless DC electric motor, is mounted within the framework 12. The motor 30 is connected to a source of electrical energy through a DC power drive generally indicated by reference character 32. The motor 30 includes a drive shaft 34 that projects into the chamber 16. The upper end of the shaft 34 is provided with a mounting spud 36 which receives the rotor 18. In the preferred instance the motor 30 takes the form of a multiphase brushless DC motor such as that manufactured and sold by Electric Indicator Company Incorporated of Norwalk Connecticut. The power drive 32 is associated with the motor 30 provides a controlled electric current to the motor 32 over lines 44. The power drive 32 includes a variable voltage source 46, a switching matrix 48 and a commutation control 50. A typical example of a power drive for a brushless DC motor is illustrated in United States Patent 3,783,359 (Malkiel), which is hereby incorporated by reference. The motor 30 includes a plurality of Hall Effect sensors (not shown), the outputs of which are provided over the lines 51 to the commutation control 50 of the drive 32. A tachometer generally indicated by reference character 52 is arranged to monitor the rotational speed (i.e., angular velocity) of the shaft 34 and thereby the rotational speed (i.e., angular velocity) of the rotor 18. In the preferred case the tachometer 52 is implemented using the outputs of the Hall Effect sensors which are applied over the lines 51A to a logic network 52L. The Hall Effect outputs are exclusively OR-ed in the logic 52L. The electrical signal produced by the logic 52L is carried on a line 53. The signal on the line 53 provides an indication of the rotational speed (angular velocity) of the shaft 34 and the rotor 18 mounted thereon. This signal on the line 53 is referred to as the tachometer signal. The elements 46 and 50 of the power drive 32 are responsive to an enable signal derived in a manner to be described and applied to these elements over lines 54A and 54B respectively. The enable signal on the line 54A applies a voltage from the variable voltage source 46 to the switching matrix 48. The enable signal on the line 54B enables the normal commutation sequence of the switching matrix 48 via the commutation control 50. The signal applied over the lines 54A, 54B functions to conditionally coupled the source 46 to the motor 30. A programmable controller 60 having a control architecture in accordance with the present invention is responsive in a manner to be described to the tachometer signal on the line 53 representative of the rotor speed. The programmable controller 60 outputs a motor current control signal on a line 62 to the motor power drive 32. A status line 63 is provided between the motor power drive 32 and the programmable controller 60. The motor power drive 32 responds to the signal on the line 62 to modify appropriately the level of current applied to the motor 30 and thereby control the torque output of the motor 30 and thus the rotational speed of the shaft 34 and the rotor 18 thereon. The programmable controller 60 also generates the enable signal carried on the lines 54A and 54B to carry out the instrument control function of conditionally coupling the source 46 to the motor 30. An operator control panel 68 communicates with the programmable controller 60 over a line 70 and permits an operator to enter desired run parameters, including a requested rotational speed (angular velocity) for the rotor. The panel also displays the actual operating parameters. In the preferred instance the programmable controller 60 is implemented by an arrangement comprising a first and a second processor 72 and 74 respectively. As will be discussed the processors 72, 74 are arranged in a architecture believed best described as a hybrid distributed processing system. The first processor 72 is implemented by a device manufactured and sold by Motorola as model number MC6809 while the second processor is manufactured and sold by Motorola as model MC6803. The processors 72 and 74 communicate with each other over a multibit link 78. The overall task of controlling the centrifuge instrument 10 is divided between the first and second processors 72 and 74, respectively. As will be seen generating the enable signal on the line 54 requires both processors 72, 74. Removal of the enable signal can be accomplished independently by either processor. The first processor 72 is directly connected via a line 80 on the processor board to the line 70 from the operator panel 68. The first processor 72 is responsible to superintend the performance of the overall set of instrument control functions necessary to the operation of the instrument 10. In order for the processor 72 so to act it serves to receive the operator selected set points (including rotational speed) and outputs of this set point information in a suitable form to the second processor 74 over the link 78. The first processor 72 also receives control status information from the second processor 74 over the link 78 and also sends status information for display on the operator panel 68. In addition, information regarding the speed of the shaft 34 is input to the processor 72 on a line 82A on the processor board. The line 82A is connected to the line 53 carrying the tachometer signal. From the standpoint of instrument control functions the processor 72 also serves to remove the enable signal applied to the power drive 32 on the lines 54A and 54B whereby the source 46 is conditionally coupled to the motor 30. The second processor 74 is, in the normal operation of the instrument, connected in what may be described as a slave relationship to the first processor 72. As such the second processor 74 receives the set point information and executes the actions necessary to carry out some predetermined subset of the instrument control functions. In addition the second processor 74 acts independently of and co-equally with the first processor 72 to remove the enable signal on the lines 54A and 54B which effects the additional instrument control function of conditionally coupling the source 46 to the motor 30. To this end the second processor 74 is also supplied with the tachometer signal on the line 53. This information is applied to the second processor 74 via a line 82B connected to the line 53. This division of processor control responsibility for the instrument control functions needed to operate the centrifuge instrument 10 can be best understood with reference to the flow diagrams set forth in Figures 2, 3A and 3B hereof. As seen from Figure 2 the first processor 72 receives an operator input through the operator control panel 68 and operates on the same, as indicated at block 88. The block 88 receives the inputs and converts them to control setpoints. These control setpoints are passed by the first processor 72 over the multibit link 78 to the second processor 74 using suitable network software 90. The control setpoints are operated on by the second processor 74, as indicated at block 92, to effect a predetermined subset of the total set of appropriate instrument control functions. The subset of instrument control functions is indicated diagramatically by the blocks 94A, 94B ... 94N. The second processor 74 generates status information on each of the set of control functions 94A through 94N, as shown at the block 96, and reports the same to the first processor via the network software 90 and the link 78. For example, one of the set of instrument control functions is the instrument motor drive control function as indicated in the block 94A. This function 94A generates the motor current control signal to the power drive 32 over the line 62. Status information from the power drive 32 is provided to the second processor 74 on the status line 63. Similar (i.e., control and status lines) are provided for the others of the subset of instrument control functions, as indicated by the lines 62′, 63′, respectively. It may thus be appreciated that the processors 72 and 74 act substantially in a master/slave relationship for the implementation of the predetermined subset of the total set of the instrument control functions. In accordance with the present invention, both the first processor 72 and the second processor 74 are simultaneously active and each is independently able to execute the additional instrument control function of conditionally coupling the source 46 to the motor 30. In the case of the first processor 72 this instrument control function is carried out by the block 98. As seen in Figure 3A the block 98 uses the control set points derived from the block 88 to set a speed threshold in functional block 99. The threshold itself corresponds to the rotational speed as selected by an operator plus some predetermined margin (e.g., four hundred rpm). The speed threshold is used in a manner to be described. In addition the first processor 72, in the block 100, verifies whether the communication link 78 between the first and second processor is operative or, in one instance, whether the instrument is indeed decelerating the load when appropriate. With respect to the speed threshold the first processor 72 receives the tachometer signal on the lines 53, 82A. When a run start is requested by an operator from the panel 68 the processor 72, after verifying conditions are suitable for a run, asserts a logic true on its enable line 106. If the tachometer signal indicates a speed that exceeds the speed threshold, as determined in the block 102, a fault condition on the line 103 is established. In the block 100 a determination is made as to whether the appropriate deceleration is occurring or whether the communications system is operational. The results of the determinations made in the block 100 and the determinations made in the block 102 (applied over the lines 101 and 103, respectively) are logically OR-ed in the block 104 to produce a logical false on a line 106. The signal on line 106 is applied to a logic AND hardware network 108. The preferred implementation of these functions may be understood with reference to pages A-1 through A-11 of the attached Appendix. This portion of the Appendix is a listing of the appropriate portions of the program for the first processor, in MC6809 assembly language. The generation of the threshold value in the block 99 is set forth on page A-2 of the listing. Entry to the block 99 may be made from one of four routines (STrap5s, STrap5, STrap 67 or STrap8). In general these four routines are implemented when either a change of speed set point or a stop of rotor is requested. In any event, from whatever routine the threshold block 99 is entered, the listing on page A-2 generates the necessary threshold value. The block 102 basically performs a comparison (termed "HiTrap" in the listing) between the period of the tachometer signal on the line 53, 82A with the period of a reference signal that corresponds to the threshold signal. The comparison is actually performed in hardware, such as a timer (an MC6840 timer) that is set with a value corresponding to the period of the reference signal. Pages A-1, A-3, and A-4 set forth the code whereby the timer is loaded. The timer begins decrementing on each falling edge of the tachometer signal. The result of the comparison is insulated from transients by the portion of the code set out on pages A-10 and A-11 of the listing. This portion of the code requires that the fault be established under a predetermined number of times (eight, in the listing) before the fault is asserted on the line 103. The speed comparison is acceptable if the period of the tachometer signal is greater than the period of the reference signal. The setting of the fault condition on line 103 is accomplished at page A-9 of the listing. Among the determinations made in the block 100 is a determination that the rotor is indeed being braked when such a command is issued (termed "SpChang" in the listing) and the verification of the operability of the communications over the line 78 between the processors 72, 74 (termed the fault conditions of flags "ComOEr" and ComIEr" in the listing, page A-9). The full text of the listings needed to generate these flags is not included as being peripheral to the invention claimed herein. The logical OR of the flag "HiTrap" (generated by the block 102 in response to the tachometer signal as discussed above) and the flags generated by the block 100 is formed by the code set forth on page A-9 of the listing that actually implements the block 104. The setting of the logical false on the line 106 is accomplished by the code noted on that same page of the listing. In the case of the second processor 74 the instrument control function of conditionally coupling the source to the motor is executed by a subroutine 110 within the motor drive control block 94A. A listing of the relevant portions of the program for the second processor 74, in assembly language for an MC6903 processor, is attached as pages A-12 through A-15 of the Appendix. Similar to the processor 72, when a run start is requested the processor 74, after verifying that conditions are suitable for a run, asserts a logic true in its enable line 116. As seen in Figure 3B and at pages A-12 and A-13 of the listing the block 109 converts the tachometer signal on the lines 53, 82B provide a representation of the rotational speed of the shaft. The block 110 (page A-13) performs a comparison with a speed setpoint (as derived via the network) to determine whether the shaft speed is within acceptable control limits. If the speed is within the control limit the processor 74 continues with normal control. However, if the comparison indicates that the speed of the shaft is outside the control limit the line 111 is asserted. As seen at page A-13 of the listing, the actual code executed is a jump to a subroutine "sc-func 24." In Figure 3B, this is indicated by a signal on the line 111 to the network 114. The block 92 performs a similar determination in subroutine block 112 for each of the other instrument control functions 94B through 94N. If any one of the control functions is beyond the acceptable control range a particular bit in the byte "Faults" is set. The code on page A-15 of the listing implements an examination of the byte "Faults." If any flag bit in the byte has been set the branch to the subroutine "sc-func 24" is asserted on the line 113. If no flag is set, normal control continues. The results of the determinations made in the blocks 110, and 112 are logically OR-ed in the block 114 to produce a logical false on a line 116. Setting the logical false on the line 116 is accomplished by the subroutine "sc-func 24" set forth at page A-14. This code implements the block 114. The signal on the line 116 is applied to network 108. In the block 108 (Figures 2 and 3A) the motor drive enable signal carried on the 54 (which splits into lines 54A and 54B) is asserted only if the inputs on the lines 106 and 116 are logical true. If either of the lines 106 or 116 is logical false then the motor drive enablement signal is not asserted. In this sense both the first processor 72 and the second processor 74 are each responsive to the tachometer signal and both are simultaneously active and independently capable of removing the enable signal. Both the first processor and the second processor are thus each independently capable of carrying out the instrument control function of conditionally coupling the energy source 46 to the motor 30. So long as the states of the signals on the lines 106, 116 indicate that the instrument's operation is acceptable, energy is applied to the motor. If the state of either line changes the motor is decoupled from the source. The decoupling can be independently controlled by either processor. Those skilled in the art having the benefit of the teachings of the present invention as hereinabove set forth may effect numerous modifications thereto. It should be appreciated that these modifications lie within the contemplation of the present invention as defined by the appended claims.

Claims: A control system for a centrifuge instrument having a motor (30) with a shaft (34) and a source of energy for the motor, the motor (30) being operative to rotate the shaft (34) to a rotational speed, a tachometer (52) operative to generate a signal representative of the actual rotational speed of the shaft, the control system including a programmable controller (60) operative to provide a predetermined set of instrument control functions including the function of conditionally coupling of the source to the motor, characterized in that the programmable controller (60) having a first and a second processor (72,74) therein, the processors (72,74) being configured in a master-slave relationship for some predetermined subset of the instrument control functions during the execution of which the slave (74) operates under the direction of the master (72) to effect that subset of control functions, each of the processors (72,74) being independently responsive to the speed signal from the tachometer (52) and being independently capable of controlling the function of conditionally coupling of the source to the motor (30).

Inventors: FRIES, GERALD ELROY
Applicants: E.I. DU PONT DE NEMOURS AND COMPANY
Application year: 1988
Main classification: B04B9
IPC codes: B04B9, G05B19, H02P5, H02P29