COMMUNICATION SWITCHING ELEMENT

Abstract: Communication switching element (SE) with a plurality of input receiver circuits (RC01/16), a plurality of output transmitter circuits (TC01/17), and a plurality of control circuits (CMC01/08) each with a data write bus (DB01/08), with a plurality of data buffers (DB0101/1601; DB0108/1608) coupling the input circuits to the data bus, and with a plurality of RAMs (RAM0101/1701; RAM0108/1708) each with an input individually connected to the data write bus and with an output individually connected to a respective one of the output circuits.

Description: COMMUNICATION SWITCHING ELEMENT The present invention relates to a communication switching element- with 3 plurality of input circuits, a plurality of output circuits, at least one set of memory circuits allocated to respective ones of said output circuits and 3t least one control circuit with a data write bus to which data outputs of said input circuits as well as dat3 inputs of said set of memory circuits are coupled, said set of memory circuits having data outputs coupled to said output circuits * Such a communication switching element is already described in the international patent application No PCT/EP88/00212 * This known switch element includes a plurality of sets of memory circuits, the data inputs and outputs of each set of memory circuits being connected to a common output on the data write bus and to the output or transmitter circuits through a data read bus respectively * The input or receiver circuits are moreover coupled to a read and write control circuit which is provided in common for all the memory circuits snd which is coupled to these memory circuits through an address bus. As a consequence only one memory circuit of a set may be selected at a time to enter data from a receiver circuit or to output data to the allocated output or transmitter circuit * This means that the same data cannot be written in two or more transmitter circuits, as may be for instance required when a ρoint-to-multiρoint connection h3s to be established * Also because the reading operation of the various memory circuits has to be performed in succession for these circuits this operation is relatively time consuming * An object of the present invention is to provide a communication switching element of the above type, but which does not present these drawbacks * According to the invention this object is achieved due to the fact that said data inputs and outputs of said set of memory circuits are individually coupled to said dats write bus and to said respective output circuits * Data may thus be simultaneously written in two or more memory circuits by a same writing operation and data may be transferred to the associated output circuits by a same reading operation * In a paper presented at the International Symposium on Subscriber Loops " and Services. Boston, September 11-16, 1988, and entitled "A flexible customer premises network concept based on ATM principles", B♦ Pauwels has envisaged an Asynchronous Transfer Mode ttwo-coordinate switching element wherein the data inputs of each of a plurality of N sets of M memory circuits are coupled to a respective one of a plurality of N data write busses * However, the N input or receiver circuits are only coupled to respective ones of these busses * Moreover, the M sets of N memory circuits allocated to a respective one out of a plurality of M output circuits are coupled thereto through M data read busses so that the reading of the memory circuits in each of the M sets of N has to be performed in succession * Another characteristic feature of the present communication switching element is that the memory circuits of said set have a common write signal input as well as a common read signal input * Still another characte istic feature of the present communication switching element is that said input circuits are each coupled to S3id data bus via a dats buffer means and are able to store groups of data in said dats buffer means in a staggered fashion, each group being stored during a first time interval, said data buffer means being able to put their respective groups of dsta successively on said dsta bus during a second time interval which differs from the first time interval by a third time interval snd thst the switching element further includes a clock circuit providing write and read signals making said write and read signal inputs of said memory circuits operative during said second snd third time intervsls respectively * Yet another characteristic feature of the present communication switching element is that said memory circuits are Random Access Memories of the single port type * Random Access Memories (RAMs) sre preferred over FIFO's becsuse the latter introduce relstively large delays * On the other hand, RAMs of the single port type have the advsntsge, when integrsted on a chip, of occupying less surface than RAMs of the dual port type and are therefore also less expensive. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein ♦ Fig. 1 represents a communication switching element SE according to the invention. Fig * 2 shows a first embodiment of the data buffer DB0101 of Fig * 1 * Fig * 3 represents pulse waveforms illustrating the operation of the dats buffer DB0101 of Fig * 2, Fig * 4 shows a second embodiment of the data buffer DB0101 of Fig * 1» Fig * 5 represents pulse waveforms illυstrsting the operstion of the data buffer of Fig * 45 Fig * 6 shows the random access memory RAM0101 of Fig * 1 in more detail. Fig * 7 represents pulse waveforms illustrating the operation of the memory RAM0101 of Fig * 15 Fig * 8 shows the write pointer WP of Fig * 7 in more detail * The communication switching element SE shown in Fig * 1 forms part of a communication switching network wherein a plurality of such elements are interconnected in a modular way * The switching element SE is able to switch fixed length packets or cells of digital signals transmitted according to Asynchronous Transfer Mode (ATM) techniques, also called Asynchronous Time Division (ATD) techniques, from a plurality of 16 signal inputs R01 to R16 to a plurality of signal outputs T01 to T17 * Each cell comprises for instance 36 bytes of which 4 bytes are used 35 a header and of which the 32 remaining bytes are data. The switching element SE includes 16 receiver circuits RC01/16, 17 transmitter circuits TC01/17, 8 control or central memory circuits CMCOl/08, a switch element control circuit SEC and a clock circuit CLC * These circuits of which only CLC, SEC, RC01, RC16, TC01, TC16, TC17, CMC01 and CMC08 are shown are interconnected as indicated and as will become clear from the following * The receiver circuits RC01/16 are substsntially, but not completely, of the type described in the international patent application No PCT/EP88/00273 relating to the sbove mentioned two-coordinste switching element snd each hsve s respective single wire data input R01/16, s respective single wire sddress output AOl/16 snd a respective 8-wire data output D01/16 of which "the constituent wires are indicated by D0101 to D0108/D1601 to D1608 respectively * Each receiver circuit further has sn additional data input connected to a selection bus SB and two clock inputs CL1 snd CL2 which are common for all the receiver circuits * Supposing that data at 600 Megabits/sec are supplied to RC01/16 the clock signal CL1 has a byte frequency of 600/8 or 75 MHz, whilst the clock signal CL2 has a cell frequency equal to 600/288 MHz since each cell contains 36 bytes or 288 bits * Each of the central memory circuits CMCOi to CMC08 includes 16 address buffers AB0101/1601 to AB0108/1608 assigned to the receiver circuits RC01 to RC16 respectively, 16 data buffers DBOlOl/1601 to DB0108/1608 also allocated to these receiver circuits, 17 single port Random Acces Memories (or RAMs) RAM 0101/1701 to RAM0108/1708 allocated to the transmitter circuits TC01 to TC17 respectively, 17 multiplexers MUX0101/1701 to MUX 0108/1708 associated to these RAMs, 3 17-wire sddress bus AB01 to AB08 and a 36-wire data bus DB01 to DB08 * The 16 address outputs A01 to A16 of the respective receiver circuits RC01 to RC16 are connected to the parallel connected inputs of sets of 8 address buffers AB0101/0108 to AB1601/1608 respectively and the data outputs D0101/0108 to D1601/1608 of these receiver circuit are individually connected to the inputs of the data buffers DB0101/0108 to DB1601/1608 respectively. Each of the address buffers has a 17-wire address output and the outputs of the address buffers of a same central memory circuit are connected to the 17-wire addres bus allocated to this memory circuit * Likewise, each of the data buffers has a 36-wire data output and the outputs of the data buffers of a same central memory circuit are connected to the 36-wire data bus allocated to this memory circuit * For instance, the outputs of the address and dat buffers of CMCOl and CMC08 are connected to the address busses AB01 and AB08 and to the data busses DB01 and DB08 respectively * Each of the 17 RAMs RAMOlOl/1701 to RAM0108/1708 of the central memory circuits CMCOl to CMC08 has a single wire address input which is individually connected to a respective one of the 17 wires of the associated 3ddress bus, and has moreover a 36-wire data input which is connected to the associated d3ts bus * For instance, the sddress inputs of the RAMs RAM0101 to RAM1701 included in CMCOl are connected to respective wires of the 17-wire address bus AB01 and the data inputs of these RAMs are all connected in parallel to the 36-wire data bus DB01 * Each of the RAMs also hss a 36-wire output which is connected to the 36-wire input of the βssocisted multiplexer having s single wire output. All the RAMs of the switching element SE moreover have a common write signal input W and s common read signal input R * The outputs of the sets of 8 multiplexers DMUX0101/0108 to DMUX 1701/1708 are connected to the 8 inputs of the transmitter circuits TCOl to TC17 respectively * These transmitter circuits TCOl to TC17 have sign3l outputs T01 to T17 respectively. T01 to T16 are connected to 3 further switching element (not shown), whilst T17 is connected to the switch element control circuit SEC snd from there to a data input of each of the receiver circuits RC01 to RC16 through the selection bus SB, in the way described in the international PCT patent application No PCT/EP88/00482. Finslly, the clock circuit CLC in response to the clock signsls CL1 and CL2 being applied to it provides the following output signals shown in Figs. 3, 5 and 7 1 - a clock signal CL3 (Figs. 3, 5) which has a frequency of 37 * 5 MHz, i * e. half the frequency of CL1, and a period T35 - staggered clock signals CS01 to CS18 (Figs. 3, 5) which have each a frequency equal to 18 times that of CL3 and include each a negatively directed pulse also called CS01/18 having a duration equal to T35 - write and read signals W and P (Fig. 7). \A comprises a plurality of negatively directed pulses occurring during CS01/16, whilst R comprise a negatively directed pulse occurring during CS17. The write and read signals W and R are applied to the like named inputs of the RAMs. Because all the data buffers are identical only one of them, i.e. DBOIOI, is shown in detail in Fig. 2 * This data buffer circuit DBOIOI includes 4 D-flipflops DFl to DF4, 38 latch circuits L01 to L38, and 36 tristate buffers TB37/38/03/04/ * ♦ * /35/3ό * The data input D0101 of the buffer DBOIOI is connected to the D-input of DFl whose data output Ql is connected to the D-input of DF2 3nd DF3 respectively * The dats output Q2 of DF2 is connected to the D-input of DF4. The data outputs Q3 and Q4 of DF3 and DF4 sr e connected to the dats inputs of the latch circuits L02/04/ * ♦ ♦ * /36 and L01/03/. * ♦/35 respectively and the dats outputs of L01 and L02 are connected to the data inputs of L37 and L38 respectively * The dats outputs L37, L38, L03, L04, ♦♦♦, L35, L36 of the lstch circuits are connected to the inputs of the respective three-state buffers TB375 TB385 TB035 TB045 * ♦♦, TB355 TB36 whose outputs M37/38/03/ * ♦ * /35/36 constitute the 36-wire output of the buffer DBOIOI * The clock inputs of DF1/2, DF3/4, L01/02, L037/38/03/04, * * . ♦ , L35/36 are controlled by the clock signals CL1, CL3, CS01, CS02, ♦♦♦, CS18 respectively, whilst all the tristate buffers are controlled by CS01. It should be noted thst the tristste buffers of the other data buffers DB0201 to DB1601 of the central memory circuit CMCOl are likewise controlled by the clock signals CS02 to CS16 respectively * In general, the buffers DB0101/0108 to DB1601/1608 are controlled by the clock signals CS01 to CS16 respectively * Another embodiment of the dsta buffer DSB0101 is represented in Fig * 3 * It includes two D-flipflops DFl an DF2 and 35 lstch circuits L01 to L35 * The dats input D010 of the buffer DBOIOI is connected to the D-input of DFl whose data output Ql is connected to the data inputs of DF2 snd L35 * The dsta outputs Q3 and Q4 of DF2 and L35 sre connected to the dsts inputs of the lstch circuits L01/03/.../33 and L02/04/ * ♦ * /34 respectively * The data outputs L01, L02, * ♦ * L33, L34, Q3, Q4 of these circuits L01/35 and DF2 are connected to the inputs of respective three-state buffers (not shown) in 3 simil3r way as in Fig * 2 and the outputs of these tristate buffers constitute the 36-wire output MOIOI of the buffer DBOIOI * The clock input of DF15 DF2/L355 LOl/025 * * . and L33/34 3re controlled by the clock signals CL1, CL3, CS01, ... , CS17 respectively. Because all the random access memories RAMs ar alike only one of them, i.e. RAM0101, is shown in detsil in Fig. 6. This single port RAM hss an address input. AB01, s write signal input W, s read signal input R snd 3 dsts output MUX0101 and " includes a memory MEM, 3 write pointer WP» 3 resd pointer RP, a comparator COMP, a multiplexer MUX, a register REG, a tristate buffer TB and gsting circuits GCl and GC2. The 36-wire dats input DB01 is connected to the 36-wire data input/output DIO of the memory MEM as well -as to the 36-wire input of the register REG whose 36-wire output constitutes the output MUX0101 of the buffer. The write 3nd read pointers HP and RP have 6-wire sddress outputs which sre connected to corresponding inputs of the multiplexer MUX whose 6-wire output is connected to the sddress input Al of the memory MEM * The address outputs of WP and RP sre also connected to the compsrstor COMP having "full" and "empty" outputs F snd E which sre activated when the memory is full and empty respectively and which control the gating circuits GCl and GC2 respectively * Other inputs of GCl are W and AB01 and the output of GCl controls the tristate buffer TB as well as the write pointer WP and the comparator COMP * Another input of GC2 is R and the output of GC2 controls the register REG, the multiplexer MUX, the read pointer RP and the comparator COMP * The output signals GCl and GC2 provided by these gating circuits may be represented by the Boolean functions (1) and (2) given at the end of the description and wherein AB'01 is the complement of AB01 * The write and resd pointers of Fig * 6 are closed loop shift registers of the type shown in Fig. 8. The latter figure more particularly represents the write pointer WP in more detail. This write pointer comprises s closed loop shift register with 6 stages DAI to DA6 each constituted by a D-flipflop. The data outputs Al/5 of these flipflops DAI/5 are connected to the dats inputs of DA2/6 through first inputs of AND-gates GA2/6 and the outputs Al/6 ar e also connected to a gating circuit GC whose output is directly connected to s first input of an OR-gate OR and via an inverter INV to the second inputs of the AND-gates GA2/6. The data outputs A5 and A6 are connected to the second input of the OR-gate OR through an exclusive OR-gate. The gating circuit GC provides at its output s control signal GC which msy be represented by the Boolean function (3) given at the end of the description and wherein A'1/6 are the complements of Al/6. The clock inputs of the stsges DAI/6 sre connected to 3 common write signal input W. When the outputs of Al/6 are on 0 the output of the gating circuit GC is activated, as a consequence of which the stage DAI is brought in the 1-condition through the OR-gate OR. Each time the write signal W is then activated the closed loop shift register is stepped through one of 52 successive positions. When reaching the last position wherein the signals A'l, A2» A'3, A4, A'5 and Aό are all activated the output of GC is also activated, as a consequence of which the register is brought back in its initial condition. The above described switching element SE operates a follows, when it is for instance assumed that data cells o 288 bits or 36 bytes are supplied to the signal inputs R01/16 of the receiver circuits RC01/16 at a bit clock rate of 600 MHz. In these receiver circuits the processing of the cells is performed in a staggered way with a staggering delay equal to the period T3 of CL3. In a way similar to that described in the above international patent application No PCT/EP88/00273 each of the receiver circuits RCOl/16 successively provides on its 8-wire data output D01/16 the 36 bytes of an applied dats cell at the byte clock frequency CL1 = 75 MHz. This means thst the first, second, ♦♦ * , eighth bits of the 36 dats bytes of the cells applied to RCOl/16 successively appear on the respective wires D0101, ♦♦♦, D0108/D1601, .♦., D1608 of the outputs D01/D16. And due to the staggered operation of the receiver circuits RCOl/16 homologous bits of the cells applied to them are successively generated on homologous output wires with a staggering delay equal to T3 * For instance, in the receiver circuit RC01 the group of first bits, called B01, B02, ♦♦ * , B36 of the 36 bytes of each cell applied thereat sre successively generated on the output wire D0101 * And the group of first bits of the 36 bytes of each cell applied to RC16 are successively generated on the output wire D1601 a time interval equal to 15 staggering delays T3 after the generation of B01, B02, * ♦♦, B36 by RC01, as shown in Fig * 3 * The 17 address bits defining the one or more transmitter circuits TC01/17 to which a cell received in a receiver circuit RCOl/16 has to be transmitted, successively appear on the single sddress output AOl/16 of this receiver circuit RCOl/16 st the clock frequency CL3 i * e * with s period T3 * This is slightly different from what is described in the last mentioned PCT patent application where the address bits are provided in parallel. Again due to the staggered operation of the receiver circuits, homologous sddress bits sre successively generated on the outputs AOl/16 with a staggering delay equal to a period T3. In the same way as described in the sbove mentioned internstional patent application no. PCT/EP88/00212 the bytes of esch cell processed by RCOl/16 sre split up in 8 bits snd these are applied to respective ones of the 8 control or centrsl memory circuits. When only considering the centrsl memory circuit CMCOl it follows from the 3bove and from Fig. 1 that the group of first data bits of the 36 bytes of the cells supplied to RCOl/16 are successively applied to the dats buffer circuits DBOlOl/1601 at the byte clock rate CL1=75 MHz and in s staggered fashion, with a staggering delay equal to a period T3. In 3 similar way the groups of address bits generated by RCOl/16 are successively applied to the 3ddress buffer circuits AB0101/1601 at the rate of the clock CL3=37.5 MHz and also in a staggered way. Thus each data bit stream supplied to a memory circuit is accompanied by a corresponding address bit stream. For instance, the data bit stream applied to DBOIOI is accompanied by the address bit stream supplied to ABOIOI and the same is true for DB1601 and AB1601. The staggered data bit streams applied to DBOlOl/1601 and the staggered address bit streams applied to AB0101/1601 are entered therein and then applied in a staggered fsshion to the dsta bus DB01 and to the address bus AB01 respectively. This is described hereinafter for the address buffer ABOIOI and for the data buffer DBOIOI o Fig. 2. In the address buffer ABOIOI a series to parallel conversion is performed so that the group of 17 address bits associated to the data bits of a cell appear at the 17-wire output of this buffer and therefore also on the address bus AB01. As a consequence one or more of the address wires connecting the bus AB01 to the RAMs RAMOlOl/1701 are activated. In the data buffer DBOIOI of Fig. 2 the data bitstresrii D0101 comprising the date bits BOl to B36 of esch cell supplied to the buffer is processed in the way shown in Figs. 2 snd 3 to which reference is made. Under the control of the byte clock CL1 this data bit stream is entered in the flipflops DFl "and DF2 and appears at the outputs Ql and 02 thereof with 3 delay equal to ' Tl and T3 respectively, Tl being the period of CL1. These two mutually delayed data bitstreams are then sampled into the flipflops DF3 and DF5, which constitute sampling means, under the control of the slower clock CL3 so that tuo sampled dat3 bitstreams comprising the data bits B02, 804. ...» and B01, B03, ... each having a duration T3 appear on the outputs Q3 and C.4 of DF3 and DF4 espectively. Finally, under the control of clock pulses CS01 to CS18 the pairs of bits BOl, B025 ...5 B35, B36 are successively latched in the p3irs of latch circuits L01, L025 ... 5 L35, L36 respectively, and under the control of CS02 the bits BOl and B02 are latched in the latch circuits L37 and L38. In other words the 38 sampled bits 601/02/03/045 B05/B065 ...5 B37/38 are latched in the respective latch registers L37/38/03/0 5 L05/Q65 ...» L37/L38 by the clock signals CS025-CS035 ...5 CS1B respectively. This means that all these 38 bits are available on the latch outputs during the clock signal CS01 fαllo.wing CS18. This is the reason why these outputs are connected to the outputs M37/38/03/04/.. A35/36 of the buffer DBOIOI through tristate buffers TD'J7/UU/03/0'1/.. ι/35/.Jώ contrullud by GϋOl. Induudr in this way the output data, called M0101, available in DBOIOI is put on the bus DB01 during CS01. The necessity to provide the use of the additional latch circuits L37 and L38 appears from Fig. 3 where the portions marked NS represent time intervals during which the SUBSTITUTE SHEET information is not very stable. Hithout L37 and L38 the information would never be fully stable during CS01 to CS18, but by providing L37 and L38 the dsts cslled M0101 3vailable during CS01 becomes stable and may therefore be outputted on the data bus DB01 by CS01. Likewise the data called M0201 (Fig. 7) to M1601 (not shown) avsilsble in the dsta buffers DB0201 to DB1601 of the central memory circuit CMCOl is put on the data bus DB01 by the clock signals CSOi to CS16 (not shown) respectively. In general, the dat3 svailβble in the dsta buffers DBOlOl/1601 to DB0108/1608 is put on the respective dst3 busses DB01 to DB08 by the clock signals CSOI to CS16 respectively. In connection with Fig. 2 it should be noted that the buffer shown therein has a relatively low power consumption when compared with a solution similar to the one shown in the above mentioned international patent application No PCT/EP88/00212 snd which would comprise a 36-bit shift register clocked by CLl snd connected to a parallel 36-bit latch register. Indeed, instead of operating at the frequency CLl, in the circuit Fig. 2 only DF1/2 operate at this frequency, whilst DF3/4 operate at the lower frequency CL3 and the latch circuits are controlled by the lower frequency pulses CS01/18. Moreover, the same control pulses CLl, CL3 snd CSOl/18 sre used to control sll the buffer circuits. The operstion of the dsts buffer DBOIOI shown in Fig. 4 is slightly different but very similar to that just described for DBOIOI of Fig. 2. Indeed, as follows from Fig. 5 the input data bit stream D0101 is entered in the flipflop DFl under the control of the byte clock CLl and the bitstres thus generated at the output Ql of this flipflop is ssmpled in DF2 and L35 under the control of th clock CL3. Thus two sampled data bit streams Q3 and Q4 comprising the dsts bits B01/03/05, ... and B02/04/06 each having a duration T3 sppear on the like named outputs Q3 and Q4 of DF2 and L35 respectively. Finally, under the control of the clock pulses CS01 to CS17 the pairs of bits BOl, B02J ♦♦♦, B35, B36 are successively latched in the pairs of latch circuits L01, L02, ... * L33, L34 respectively. Because DF2 and L35 respectively store the bits B35 snd B36 3fter CS17 has elapsed their outputs Q3 and Q4 are connected together with the outputs of L01/.../L34 to the above mentioned tristate buffer circuits. The dats put on the last mentioned data bus DBOl in the way described above may be written in one or more of the associated RAMs depending on the condition of the output GCl of the gsting circuit GCl, i.e. of the write input W, the address input AB01 snd the "full" output F of the compsrator COMP. Conversely data stored in maximum 16 dats buffers sy be successively written in esch RAM, 3lso depending on the condition of the output of GCl. For instance, when W, AB01 and F are as shown in Fig. 7 then the output signal GCl hes two negatively directed write pulses 01 snd 16. By esch of these pulses the dsts M0101 and M1601 then present on the dsts input DBOl sre spplied to the dsts input/output DI0 of the memory MEM vis TB snd sre written therein st the sddress then spplied to the address input Al of this memory vis the multiplexer MUX. The sddress provided by WP snd not thst provided by RP is spplied to Al because the output of the gsting circuit GC2 is then sctiv3ted. By the trsiling edges of esch of the pulses 01 snd 16 the write pointer WP is stepped snd the compsrstor COMP is informed of the fsct thst s writing operstion hss taken place. This information is necessary when the comparator COMP detects that WP and RP are in the same position and has to decide whether this corresponds to a full or empty memory. Indeed, when in this case the last operation was 3 write operation the memory MEM is full, whereas the contrary is true if the last operstion wss a re3d operstion. From the sbove description of Fig. 2 it follows thst in esch dsts buffer data are stored under the control of 18 clock signals CS01 to CS1B, and dats stored in the 16 buffers associated to s same data bus sre successively put on this dat3 bus under the control of 16 clock signals CS01 to CS16 and may then be successively written in one or more RAMs. This means that 3 third time intervsl equal to 2T3 and corresponding to the clock signals CS17 and CS18 remains available to read dats from 3 RAM by means of a resd signal R. More particularly the data stored in the memory MEM of the RAM, shown in Fig. 6, at the address provided by the resd pointer RP may be resd depending on the condition of the output GC2 of the gating circuit GC2, i.e. of the read input R and of the 'empty* input E of the cαmparstor COMP. For instance, when R snd E sre shown in Fig. 7 then the output signal GC2 has a negatively directed read pulse during CS17. By this pulse the dats present in the memory MEM at the address then applied by the read pointer RP to the address input Al of this memory MEM via the multiplexer MUX are provided st the data input/output DIO of MEM and applied to the register REG. By the trailing edge of this pulse the dats resd is then entered in the register REG. From this register snd via the ouput MUX0101 these dats sr applied to the associated multiplexer MUX0101 which performs a psrsllel-to-series conversion of these data under the control of a 6-bit selection signal (not shown). The resultant series bitstream is applied to the associate transmitter circuit TCOl and is combined therein with the other bitstreams spplied therest from MUX0102 to MUX0108 and then generated at the output T01. It should be noted thst when data are transmitted t the transmitter circuit TC17, they 3re processed in the control circuit SEC and applied to the selection bus SB to one of the receiver circuits RC01/IC in the way described in the above mentioned internatiori3l pstent 3pplicstion PCT/EP88/00482. Due to the fsct that in each RAM the writing and reading operations ar e performed in sequence this RAM may be of the single port type instead of being of the dual port type. Te latter allows simultaneous reading and writing but on a chip it occupies a surface of about 1.6 times thst occupied by a single port RAM snd is therefore more expensive. Because the same write signals W as well as the same resd signsls R sre used by all the RAMs of the switching element SE the write and read control of these RAMs is simple. Moreover, because the read data are the simultaneously svsilsble on the outputs of these RAMs sll the demultiplexers connected to these outputs msy be controlled by the ssme selection signβls. In connection with the above described switching element SE, it may finally be noted that any loss of synchronisation of the oρer3tion of the RAMs, and more psrticularly of those processing the bits of a same cell, e.g. due to a non-permanent fsilure of the pointers, will 3utomsticslly be restored. Indeed, as the outgoing links connected to the outputs TOl/lό of the switching element SE are for instance only occupied during 80% of the time, the 20% remaining time will generally be sufficient to bring the non-synchronized write and r ead pointers of the above RAMs in a position indicating thst these RAMs are empty. From thst moment onwsrds the RAMs hsve s synchronized operstion. GCl = W + F + AB'01 (1) GC2 = R + E (2) GC = A* l.A2.A , 3.A4.A'5.A6+A , l.A*2.A , 3.A , 4.A , 5.A , ό (3) While the principles of the invention hsve been described 3bove in connection with specific apparstus, it is to be clesrly understood thst this description is made only by wsy of exsmple and not ss s limitstion on the scope of the invention.

Claims: CLAIMS 1. Communication switching element with a plurality of input circuits (RCOl/16) , s plurality of output circuits (TC01/17), at least one set of memory circuits (RAMOlOl/1701? RAMOlOl/1701) sllocsted to respective ones of ssid output circuits (TC01/17) 3nd at least one control circuit (CMCOl/08) with a dats write bus (DBOl/08) to which d3ts outputs of S3id input circuits (RCOl/16) 35 well as dsts inputs of said set of memory circuits (RAMOlOl/1701 ) are coupled, said set of memory circuits having data outputs coupled to said output circuits (TC01/17), characterized in that said dats inputs and outputs of said set of memory circuits (RAMOlOl/1701 > RAM0108/0708) are individually coupled to said dsts write bus (DBOl/08) snd to ssid respective output circuits (TC01/17). 2. Communication switching element according to claim 1, characterized in that said memory circuits are random access memories of the single port type. 3. Communication switching element according to claim 1, characterized in thst esch of said input circuits (RCOl/16) has a parallel data output (D01/16) the constituent wires of which are connected to respective ones of 3 plurality of said control circuits (CMCOl/08). 4. Communication switching element according to claim 1, characterized in that the memory circuits (RAMOlOl/1701, RAM0108/1708) of said set have a common write signal input (W) as well as 3 common resd signal i nput ( R ) ♦ 5. Communication switching element according to clsim 1, chsrscterized in thst it includes s plurslity of ssid sets of memory circuits sll having s common write εignsl input (W) ss well ss s common resd signsl input (R). 6. Communication switching element according to claim 4 or 5, characterized in that said input circuits (RCOl/16) are each coupled to said dats bus (DBOl/08) vis a data buffer means (DBOlOl/1601. DB0108/1608) and are able to store groups of data (B01/36) in said data buffer means in 3 staggered fashion, esch group being stored during 3 first time interval, said dat3 buffer means being able to put their respective groups of dats successively on ssid dsta bus during a second time interval which differs from the first time interval by a third time interval and that the switching element further includes a clock circuit (CLC) providing write (W) and read (R) signals making said write (W) and read (R) signal inputs of said memory circuits operative during said second and third time intervals respectively. 7. Communication switching element according to claim 6, characterized in thst the address outputs (AOl/16) of said input circuits are each coupled to an address bus (AB01/08) in ssid control circuit (CMCOl/08) through an address buffer means (AB0101/1601 , AB0108/1608) enabling memory circuit addresses provided by said input circuits (RCOl/16) to be successively put on said address bus in time coincidence with the corresponding groups of data put on said data bus (DBOl/08). 8. Communication switching element according to claim 7, chsrscterized in thst the constituent wires of ssid sddress bus (DBOl/08) are esch connected to an address input of 3 respective one of said memory circuits (RAM0101/1601, RAM 0108/1608) and that said address buffer means ( B0101/1601, AB0108/1608) are each able to simultaneously activate one or more of the address inputs of said memory circuits under the control of the address then put on said address bus (DBOl/08). 9. Communication switching element according to claim 6, characterized in that each of said dats buffer means (DBOIOI, Fig. 2, 3) includes delay means (DF1/2) subjecting an incoming dst3 bitstream (BOl, B02, ♦♦.), generated by an input circuit (RC01) at a first frequency (CLl), to a plurality of delays so 35 to provide m mutually delayed data bitstreams (Ql/2), sampling means (DF3/4) for sampling esch of S3id delayed dsts bitstresms (Ql/2) with a sampling frequency equal to 1/m th of said first frequency so ss to provide m ssmpled bitstresms containing different bits of said incoming data bitstream, and latching means for latching the bits of said m sampled bitstresms in respective ones of π_ lstch registers (L01/03, ... i L02/04, ♦♦.) operating at said sampling frequency, and output means (TB03/04....... ) to put the contents of said latch registers simultaneously on said data bus (DBOl). 10. Com unicstion switching element according to claim 9, charscterized in th3t said delay means (DF1/2) sre constituted by 3 first (DFl) snd 3 second (DF2) D-flipflops both controlled at said first frequency, the output (Ql) of said first flipflop (DF4) being connected to the data input of said second flipflop (DF2) and the outputs (Q3/4) of said first and second flipflops constituting the outputs of the delay means. 11. Communication switching element according to claim 10, characterized in that ssid sampling means are constituted by third (DF3) and fourth (DF4) D-flipflops both controlled 3t said second frequency <CL3) 3nd hsving dsts inputs to which the 3t3 outputs of ssid first (DFl) and second (DF2) flipflops are connected respectively, as well as dsta outputs (Q3/4) coupled to said latching means (L01/36). .1 - 12. Communication switching element according to claim 6, characterized in that each of said data buffer means (DBOIOI, Figs. 4, 5) includes sampling means (DF2/L35) for sampling 3n incoming dsts bitstresm (Ql), having a first frequency (CLl), at a sampling frequency equal to 1/mth of said first frequency so as to provide a plurality of bitstresms containing different bits of ssid incoming dsta bitstream, latching means (LOl/34) for latching the bits of 53id bitstresms in respective ones of a plurality of latch registers (L01/03/ ..A L02/04, ♦.♦) operating at said sampling frequency, and output means to put the contents of said latch registers simultaneously on • said dsts bus (DBOl). 13. Communication switching element according to claim 12, characterized in that said sampling means sre constituted by a first D-flipflop (DF2) and a latch circuit (L35) having a common d3ta input (Ql) to which said incoming data bitstream is applied as well as data outputs (Q3/4) coupled to said latching means (LOl/34), the outputs (LOl/34, Q3/4) of said latching means (LOl/34) and of said first flipflop (DF2) and said latch circuit (135) being coupled to the output (M0101) of the buffer means. 14. Communication switching element according to claim 1, characterized in that each of said memory circuits (RAM0101, Fig. 6) has an individual write and read control circuit. 15. Communication switching element according to claim 14, characterized in that said individual write and read control circuit includes a write pointer (WP) and a read pointer (RP) for a memory (MEM), at least one of said pointers being constituted by 3 closed loop shift register (Fig. 8). 16. Communication switching element 3ccording to claim 15, characterized in that in said closed loop shift register the outputs of the constituent stages (DAI/6) thereof are coupled to 3 gating circuit (GC) to detect 3t least one first predetermined position of ssid shift register snd to bring it then sccordingly into s second predetermined position. 17. Communication switching element according to claim 2, characterized in that said single port random access memory (RAMOIOI, Fig. 6) has 3 dsta input (DBOl), 3 data output (MUX0101), an 3ddress input (AB01), 3 write signal input (W) and a read signal input (R) and includes a memory (MEM) with a single data input/output (DIO) to which ssid data input (DBOl) is coupled via 3 switch (TB) and which is coupled to ssid dsta output (MUX0101) through a register (REG), a first gsting circuit (GCl) controlled st least by said write (W) and address (AB01) inputs and controlling S3id switch (TB), snd a second gating circuit (GC2) controlled st " least by ssid resd input (R) 3nd controlling ssid register (REG). 18. Communication switching element according to claim 17, characterized in that said rsndon access memory (RAMOIOI) further includes 3 write pointer (WP) snd 3 re3d pointer (RP) which are both coupled to an address input (Al) of said memory (MEM) as well as to a comparator (COMP) which provides a first output signal (F) when said memory (MEM1) is full and a second output signal (E) when said memory is empty, said first and second signals controlling said first (GCl) and second (GC2) gating circuits respectively.

Inventors: BARRI PETER IRMA AUGUST, DE GROOTE JAN LIEVEN BERT, BARRI, PETER, IRMA, AUGUST, DE GROOTE, JAN, LIEVEN, BERT
Applicants: ALCATEL NV, BELL TELEPHONE MFG, BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE VEN
Application year: 1988
Main classification: H04Q11
IPC codes: H04L12