Improved multilayer interconnection for integrated circuit structure having two or more conductive metal layers and method of making same

Abstract: Construction of a novel multilayer conductive in­ terconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer (40) which may be in contact with an underlying silicon substrate (10) and comprising a ma­ terial selected from the class consisting of TiW and TiN; an intermediate layer (50) of conductive metal such as an aluminum base metal; and an upper bar­ rier layer (60) which may be in contact with a second aluminum base metal layer (80) and which is selected from the class consisting of TiW, TiN, MoSi x and TaSi where x equals 2 or more.

Description: This invention relates to an improved interconnection for integrated circuit structures and a method of making same. More particularly, this invention relates to a multilayer interconnection for integrated circuit structures having more than one conductive metal layer. An integrated circuit structure according to the pre-characterising part of Claim 1 and a method of forming this structure comprising steps (a) and (e) to (i) are disclosed in Solid State Technology, Vol.29, No2, February 1986, pages 131-136. Conventionally, aluminum base metal, i.e., aluminum or an alloy of aluminum, is used to form the interconnections or "wiring" between components and devices in integrated circuit structures. Such uses of aluminum include the interconnections or vias used between different layers or levels of metal such as aluminum as well as for the contacts to individual elements of an active device in the integrated circuit structure such as the collector, base, and emitter contacts of a bipolar transistor or the source, drain, and gate electrodes of an MOS device. Aluminum is not the only metal which is or can be used for such purposes. Both platinum and gold metals have also been used in such applications. However, aluminum remains by far the most prevalently used metal in integrated circuit structures because of its superior combination of low cost, low weight, and good conductivity. However, the use of aluminum in integrated circuit structures for interconnections, contacts, and the like is not without its problems. When aluminum is used as an electrical contact to an electrode region of an active device formed in silicon, the aluminum and silicon may interdiffuse which can cause the aluminum to migrate down into the silicon substrate below the junction formed between the doped region and the substrate, e.g., below the source or drain regions, thereby shorting out the device. Furthermore, when a layer of aluminum is used as the horizontal interconnection between devices or elements of a device, some areas of the aluminum interconnect may form hillocks or spikes upon subsequent exposure to processing temperatures above 400°C which can, in turn, result in formation of an electrical short from the aluminum layer through an overlying insulating layer to another metal layer thereon. The use of a conductive material such as a titanium-tungsten alloy over an aluminum layer or between two aluminum layers is known. Lin et al, in an article entitled "Linewidth Control Using Anti-Reflective Coating for Optical Purposes", IEDM International Electron Device Meeting, San Francico, CA, December 13-15, 1982, at pp 399-402, discuss the use of various antireflective coatings such as titanium-tungsten, vanadium, and polysilicon on aluminum to lower the reflectivity of aluminum for photolithographic purposes. Harrison et al in an article entitled "The Use of Anti-Reflective Coatings for Photoresist Linewidth Control", Kodak Microelectronics Seminar, San Diego, CA, November, 1983 also discuss the use of anti-reflective coatings such as vanadium, titanium-tungsten, molybdenum, titanium, and polysilicon on aluminum-silicon materials. This latter reference also discloses the previous sue of titanium-tungsten under Al-Si as a barrier layer to prevent aluminum spiking in the silicon substrate. The use of a layer of titanium-tungsten between two aluminum layers in an integrated circuit structure as an etch stop is discussed in Pierce et al U.S. Patent 4,267,012. While the use of other materials such as titanium-tungsten between the adjoining layers of aluminum is, therefore, known, it has been found that problems such as the diffusion of aluminum into an underlying silicon substrate may actually be exacerbated by the presence of materials such as an alloy of titanium-tungsten over the aluminum. Apparently this is due to the fact that a titanium-tungsten alloy and aluminum can interact to form an intermetallic compound (Ti x Al y W z ) which actually has a higher solubility for silicon than the solubility of aluminum for silicon. It would, therefore, be desirable to provide an interconnection in integrated circuit structures having more than one conductive metal layer which would eliminate or at least mitigate some or all of the problems caused by the use of aluminum metal as the interconnection. The above problem is solved by the structure and method as claimed in Claims 1 and 5 respectively. Some embodiments of the invention will now be described by way of example only, with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a fragmentary vertical cross-sectional view of a preliminary construction step of another embodiment of a multilayer interconnection formed in accordance with the invention. Figure 2 is a fragmentary vertical cross-sectional view of the embodiment of Figure 1 after completion of the multilayer interconnection. Figure 3 is a flow sheet illustrating a process of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention provides a novel conductive interconnection for an integrated circuit structure in which more than one level of conductive metal is used to interconnect various elements and devices in the integrated circuit structure. First barrier layer 40 should comprise a material exhibiting good conductivity; good adherence, both to the exposed silicon where the electrical contact will be formed, and to the surrounding oxide; and sufficiently low porosity to inhibit diffusion of either silicon or aluminum therethrough to the adjoining layer. When barrier layer 40 comprises TiN, layer 40 may be formed in a two step process which comprises first sputtering a 20-80nm layer of titanium metal in a nonreactive argon atmosphere of about 5 to 15 milliTorr and a temperature of at least about 100°C and not exceeding 400°C followed by a second step of reactively sputtering the titanium nitride (TiN) barrier from an elemental titanium target onto the titanium layer in a 50-60% argon/nitrogen atmosphere at a temperature of from ambient to about 200°C. Alternatively, the TiN layer formed over the titanium metal layer may be formed by sputtering TiN directly from a composite TiN target. The term "nonreactive atmosphere" as used herein refers to the presence of a nonreactive gas such as argon to effect the sputtering process. TiN layer 40 may also be formed in a single step by sputtering TiN directly from a composite TiN target under the same temperature and pressure conditions again using a nonreactive argon atmosphere. However, the use of a metallic titanium underlayer in the first or lower barrier layer is preferred because the titanium metal layer below the titanium compound or alloy will adhere well to both the exposed silicon where the electrical contact is to be made as well as to the adjacent oxide layer. The use of TiN is preferred over other titanium compounds, such as, for example, titanium silicide, due to the superior barrier characteristics of the TiN materials which will inhibit the migration of silicon through the barrier layer from beneath or the migration of aluminum down through the barrier layer from above. In one embodiment of the invention, after the formation of the sputtered barrier layer TiN), the vacuum may be broken and the structure subjected to a rapid thermal anneal in the temperature range of 500-650°C for 30 seconds to 1 minute. The rapid anneal is carried out in a N 2 or Ar/N 2 atmosphere. The purpose of the anneal is to improve the electrical contact resistance of the barrier to the doped silicon regions by intimate mixing at the silicon-barrier interface and also formation of a primitive silicide (TiSi x , where x is greater than 1). The anneal also improves the barrier performance by forming a nitride-rich skin such as TiN X (where x is greater than 1) at the surface. In another embodiment of the invention, the TiN barrier layer itself may be formed by a rapid anneal process. In this embodiment, about 50-120nm of titanium is first deposited by sputtering, as before, in a nonreactive argon ambient. Next the structure is subjected to a rapid thermal annealing process wherein the temperature is rapidly raised to heat the structure to about 600-800°C, usually about 700°C, within a time period of about 10 seconds. The structure is then maintained at this temperature for a time period of about 30 seconds to 1 minute in a N 2 atmosphere. This rapid annealing may be carried out in special processing equipment known as a RAPID THERMAL ANNEALER which equipment has the ability to rapidly carry out TiSi x formation at the silicon level while forming a TiN barrier at the surface of the layer without oxidizing the titanium. The rapid anneal serves to form a silicide such as TiSi x (where x is greater than 1) which improves the contact resistance to N+, P+, or doped polysilicon regions. Concurrently, the unreacted titanium converts to a TiN barrier near the surface. After the formation and oxide exposure of lower barrier layer 40, from 250 to 400nm of a conductive metal layer 50 is then deposited over barrier layer 40. Conductive metal layer 50 may comprise a metal such as gold or platinum but will preferably comprise an aluminum base metal for reasons of process economics. The deposited aluminum base metal may be pure aluminum or, preferably an aluminum-copper alloy containing up to 2.0 wt.% copper. Optionally up to 2 wt.% silicon may also be present in the deposited aluminum alloy. The use of the term "aluminum base metal" as used herein, is intended to define pure aluminum as well as aluminum alloys containing at least about 90 wt.% aluminum. The aluminum base metal is preferably applied by sputtering in an argon atmosphere while maintaining a pressure of from about 5 to 15 milliTorr and a temperature of 300°C. After depositing the aluminum base metal and without breaking the vacuum to avoid formation of any undesirable aluminum oxide film on the surface of the newly deposited aluminum base metal, an upper barrier layer 60 is formed. Upper barrier layer 60 comprises from about 80 to 120nm of TiN. As TiN is used as the upper barrier layer, sputter etching must be subsequently usec to remove undesired oxide films from the upper surface to provide a good electrical contact with subsequently applied metal layers. The upper barrier layer 60 may be deposited sequentially by sputtering without breaking vacuum using the same techniques used in forming lower barrier layer 40. After formation of upper barrier layer 60, the formation of the multilayer lower metal layer, comprising lower barrier layer 40, aluminum base metal layer 50, and upper barrier layer 60, is complete and will hereinafter be referred to collectively as the interconnection layer and will function in the integrated circuit structure in place of what is normally referred to as the first metal layer. The interconnection layer may now be patterned to form the desired interconnects or wiring harness by applying a photoresist mask, and then patterning the mask using conventional photolithography techniques. The interconnection layer is then etched through the photoresist mask using conventional plasma/reactive ion etch chemistry such as CHCl 3 , Cl 2 , SiCl 4 , and CF 4 gas-mixtures to etch through the composite sandwich-metal sequentially. After patterning of the interconnection layer of the invention, the structure may be subjected to conventional processing to form a second oxide layer which will serve to separate the patterned portions of the interconnection layer of the invention from a subsequently applied metal layer which is usually referred to as the second metal layer. A second oxide layer 70 is, therefore, conventionally formed and patterned, as shown in Figure 1, and a second metal layer 80, e.g., an aluminum base metal layer, is then applied and patterned. As shown in Figure 1, second metal layer 80 forms a junction with the upper layer 60 of the interconnection at 86. Second metal layer 80 may also comprise either pure aluminum or, preferably an aluminum-copper alloy containing up to 0.5 wt.% copper. Optionally up to 2 wt.% silicon may also be present in the deposited aluminum base metal comprising metal layer 80. To provide a good connection between second metal layer 80 and the upper surface of upper barrier layer 60 at 86, it is necessary that the exposed portion of the upper surface of layer 60 be cleaned to remove oxides which would provide an undesirably high contact resistance at the junction 86 between the interconnection layer and the second metal layer. As previously discussed, the use of TiN in the formation of upper barrier layer 60 may necessitate the use of a conventional sputter etch to clean the surface prior to deposition of second metal layer 80 thereon. It perhaps should be noted in this regard that in the construction of the interconnection layer, formation of aluminum layer 50 over lower barrier layer 40 may proceed without such a cleaning step even though lower barrier layer 40 has been exposed to air because the thickness of the oxide layer formed over lower barrier layer 40 of about 2-5nm can be penetrated by the subsequently applied aluminum layer 50. However, the formation of upper oxide layer 70 will result in the exposure of the upper surface of upper barrier layer 60 to temperatures at which there will be sufficient growth of oxide to render such a cleaning step necessary to provide the desired low resistance contact at 86. Turning now to Figures 1 and 2, another embodiment of the invention is shown representing a variation of the basic process wherein a self-aligned metal silicide contact is formed over doped region 14 in silicon substrate 10 using oxide 30 as a mask prior to formation of first barrier layer 40 of the interconnection layer to achieve better contact between the interconnection layer and the silicon substrate. As shown in Figure 1, a layer 36 of a metal capable of reacting with silicon to form a metal silicide is applied over doped region 14 and oxide layer 30. Metal layer 36 may be formed by sputtering a 15-40nm layer of a metal such as titanium over the surface. The structure is then annealed at a temperature of about 500-700°C for up to about 30 minutes in a nonreactive atmosphere free of any oxygen such as an argon or nitrogen atmosphere to sinter the metal and form metal silicide wherever the metal is in contact with silicon. The result, as shown in Figure 2, is a self-aligned metal silicide layer 22 of TiSi 2 , formed selectively only in the doped silicon contact region 14 in silicon substrate 10. Alternatively, the structure may be subjected to the previously described rapid annealing process for a period of up to about 2 minutes at a temperature of about 700°C to form the metal silicide. In either process, the unreacted metal is then removed using an etchant selective to the unreacted metal such as an aqua regia etch for platinum or an ammonium hydroxide/peroxide etch for titanium. After removal of the unreacted metal from the structure, formation of lower barrier layer 40 of the interconnection layer may proceed as previously described resulting in the structure shown in Figure 2. The result, in the practice of either embodiment of the invention, is an improved, more reliable, integrated circuit structure having an interconnection layer wherein diffusion of either aluminum of silicon is prevented or inhibited and-the formation of aluminum spikes and hillocks is also prevented or inhibited. Due to the presence of the lower and upper barriers, the electromigration resistance of the metal 1 interconnect increase, thus rendering the integrated circuit more reliable. The interconnect layer of the invention also serves as an antireflective layer permitting enhanced photolithography in the printing of fine lines. The electrical connection between the interconnect layer and the metal 2 layer is enhanced without the necessity of sputter etching, if desired, resulting in a structure with excellent reliability.

Claims: An integrated circuit structure comprising a silicon substrate (10); a number of doped regions (14) in that substrate; a first oxide layer (30) on the substrate having a respective aperture to expose each said doped region (14); an electrically conductive interconnection layer (40,50,60) disposed to conductively contact at least one such doped region through its respective aperture and to overlie said first oxide layer; a second oxide layer disposed to overlie parts of said first oxide layer (30) not covered by said interconnect layer and the interconnection layer (40,50,60), the second oxide layer (70) being formed with at least one aperture exposing a selected portion of said interconnection layer (40,50,60); and a metal conduction layer (80) disposed to overlie said second oxide layer (70) and electrically contact said selected portion of said interconnecting layer (40,50,60) through said at least one aperture; characterised by: (a) a 250-350 nanometre thick intermediate layer (50) of aluminium base metal; (b) a lower conductive barrier layer (40) disposed between said intermediate layer (50) on the one hand and said doped region of the substrate and said first oxide layer on the other hand; said lower barrier layer including a layer comprising TiSi x , where x is greater than 1, in contact with said doped region, and a layer comprising TiN x , where x is greater than 1, in contact with said intermediate layer, and the remainder of said lower barrier layer comprising pure Ti or TiN apart from insignificant impurities; and (c) an upper conductive barrier layer (60) of TiN disposed between said intermediate layer and said second oxide layer (70); and in that said three layer structure extends between said first and second oxide layers. The structure of Claim 1, characterised in that said lower conductive barrier layer (40) comprises a 80-150 nanometres thick layer adapted to inhibit the diffusion of silicon therethrough into said intermediate conductive metal layer (50) and the diffusion of aluminum from said intermediate conductive metal layer therethrough into said silicon substrate (10). The structure of any preceding claim, characterised in that said upper conductive barrier layer (60) comprises a 80-120 nanometres thick layer adapted to inhibit the diffusion of aluminum therethrough from said intermediate conductive metal layer (50). The structure of any preceding claim, characterised in that said doped silicon region (14) in said substrate has a metal silicide layer formed in the surface thereof beneath said lower conductive barrier layer to enhance the conductivity between said doped region in said substrate and said interconnection layer. A method of forming an integrated circuit structure comprising a silicon substrate (10); a number of doped regions (14) in that substrate; a first oxide layer (30) on the substrate having a respective aperture to expose each said doped region (14); an electrically conductive interconnection layer (40,50,60) disposed to conductively contact at least one such doped region through its respective aperture and to overlie said first oxide layer; a second oxide layer disposed to overlie parts of said first oxide layer (30) not covered by said interconnect layer and the interconnection layer (40,50,60), the second oxide layer (70) being formed with at least one aperture exposing a selected portion of said interconnection layer (40,50,60); and a metal conduction layer (80) disposed to overlie said second oxide layer (70) and electrically contact said selected portion of said interconnecting layer (40,50,60) through said at least one aperture; comprising the successive steps of: (a) forming a first oxide layer (30) over a substrate (10) which includes said doped regions, the first oxide layer (30) having an opening therein to expose each said doped region (14) of said substrate; (b) forming a lower conductive barrier layer (40) of TiN over said first oxide layer (30) in electrical contact with said doped region (14) of said substrate (10) through said opening and subsequently rapidly annealing the lower barrier layer in a N 2 or Ar/N 2 atmosphere; (c) forming a 250-350 nanometre thick intermediate layer (50) of aluminium based metal over and in electrical contact with said lower conductive barrier layer; (d) forming an upper conductive barrier layer (60) of TiN on said intermediate layer; said lower layer, intermediate layer and upper layer forming together said interconnection layer; (e) patterning and etching said interconnection multilayer to form discrete interconnections and to expose said first oxide layer (30) therebetween; (f) forming a said second oxide layer (70) over said interconnections and the exposed first oxide layer; (g) patterning and etching said second oxide layer (70) down to said upper layer of said interconnection layer (40,50,60) to form said at least one aperture exposing selected said selected portion of said interconnection layer (40,50,60); (h) forming a second aluminium based metal layer over said second oxide layer and said exposed portion of said interconnections; and (i) patterning and etching said second metal layer to form discrete further interconnections therefrom. The method of Claim 5, characterised by the further steps of forming a layer (36) over said first oxide (30) and said exposed doped silicon substrate (14) of a metal capable of reacting with said silicon to form a metal silicide, heating said structure to a temperature of about 500-700°C to sinter said metal and form said metal silicide over and in the surface of said doped silicon substrate, and removing unreacted portions of said metal on said first oxide layer before said step (b) of forming said lower conductive barrier layer. The method of Claim 5 or 6, characterised in that said step b) of forming said lower conductive barrier layer (40) comprises sputtering from 80-150 nanometres of TiN onto said structure from a TiN composite target in an argon atmosphere of from about 5 to 15 milliTorr (0.66 to 2.0 Pa) while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C. The method of Claim 5 or 6, characterised in that said step b) of forming said lower conductive barrier layer comprises sputtering from 20-80 nanometres of titanium onto said structure from a titanium target in an argon atmosphere of from about 5 to 15 milliTorr (0.66 to 2.0 Pa) while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C and then reactively sputtering titanium nitride (TiN) onto said titanium layer under the same reaction conditions to form said TiN layer on said silicon substrate. The method of Claim 8, characterised in that said rapid annealing of step (b) comprises heating the structure up to a temperature of from about 600-800°C within a period of about 10 seconds and then maintaining the structure at this temperature for a period of from about 30 seconds to 1 minute in a nitrogen atmosphere to clean the silicon surface and cause at least a portion of said titanium to react with said silicon to form a titanium silicide thus enabling good electrical contact to silicon while forming a TiN barrier at the surface. The method of any one of Claims 5 to 9, characterised in that said step d) of forming said upper barrier layer (60) comprises sputtering from 80-120 nanometres of TiN over said intermediate layer (50) in an argon atmosphere of from about 5 to 15 milliTorr (0.66 to 2.0 Pa) while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C. The method of any one of Claims 5 to 10, characterised in that said step e) of forming a second oxide layer (70) over said interconnection layer (40,50,60), comprises patterning said second oxide layer to expose at least a portion of said interconnection layer, and cleaning the surface of said interconnection layer to remove oxides thereon before forming said metal conductor layer (80) thereover.

Inventors: RAMANI RAM, SHANKAR KRISHNA, RAMANI, RAM, SHANKAR, KRISHNA
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1988
Main classification: H01L23
IPC codes: H01L29, H01L21, H01L23