Photoelectric conversion apparatus

Abstract: A photoelectric conversion apparatus having an array of plural photoelectric conversion cells having semiconductor areas for accumulating photo­ induced carriers, in which a gate-insulated tran­ sistor is formed with main electrodes composed of the semiconductor areas of neighboring photoelectric conversion cells, for separating the cells and for collective refreshing of the cells.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion apparatus of the type accumulating the carriers generated by photoexcitation. Related Background Art Fig. 6A is a schematic cross-sectional view of a known photoelectric conversion apparatus and Fig. 6B is an equivalent circuit diagram of a photoelectric conversion cell thereof. As shown in these drawings, photoelectric conversion cells are arranged on an n-type silicon substrate 1, and each cell is electrically insulated from neighboring cells by separating areas 2 consisting of SiO 2 , Si 3 N 4 or polysilicon. Each photoelectric conversion cell is constructed in the following manner. On an n - -area 3 of a low impurity concentration formed for example by epitaxial technology, a p-area 4 is formed by doping of p-type impurity, and in said p-area 4 there is formed an n + -area 5 is formed by impurity diffusion or ion implantation. The p-area 4 and n + -area 5 constitute the base and emitter of a bipolar transistor. An oxide film 6 is formed on the n - -area 3 having the above-mentioned areas, and a capacitor electrode 7 of a predetermined area is formed on said oxide film 6. The capacitor electrode 7 is positioned opposite to the p-type base area 4 across the oxide film 6, and is given a pulse voltage to control the potential of the floating p-base area 4. An emitter electrode 8 is connected to the n + -emitter area 5. There are also formed, on the bottom face of the substrate 1, an n + -area 11 with a high impurity concentration, and a collector electrode 12 for giving a potential to the collector of the bipolar transistor. The basic function of the above-explained apparatus is as follows. In an initial state the p-type base area 4 of the bipolar transistor assumes a negative potential. Light 13 is introduced to said p-type base area 4 to generate electron-hole pairs, of which positive holes are accumulated in said p-type base area 4 to elevate the potential thereof in the positive direction (accumulating operation). Then a positive voltage pulse for signal reading is given to the capacitor electrode 7, and a read-out signal corresponding to the change in the base potential in the accumulating operation is released from the floating emitter electrode 8 (signal reading operation). This reading operation can be repeated, since the amount of accumulated charge in the p-type base area 4 scarcely changes. For eliminating the positive holes accumulated in the p-type base area 4, the emitter electrode 8 is grounded and a positive refreshing pulse is supplied to the capacitor electrode 7. Said pulse biases the p-type base area 4 in the forward direction with respect to the n + -type emitter area 5, thereby allowing elimination of the accumulated positive holes. The p-type base area 4 returns to the initial state at the end of said refreshing pulse (refreshing operation). The operations of accumulation, reading and refreshing can thereafter be repeated in the same manner. In summary, the above-explained process accumulates the photogenerated carriers in the p-type base area 4 and controls the current between the emitter electrode 8 and the collector electrode 12 by the amount of accumulated charge. Thus the amount of accumulated carriers is read after amplification by the amplifying function of each cell, so that the device can provide a high output, a high sensitivity and a low noise level. In this process the potential Vp generated in the base by the photoinduced carriers (positive holes in this case) accumulated therein is given by Q/C, wherein Q is the amount of charge of the positive holes accumulated in the base area and C is the capacitance connected to the base area. As will be apparent from this relation, at a higher degree of integration, the Q and C decrease together with the reduction in cell size, so that the potential Vp generated by photoexcitation is maintained almost constant. Consequently this proposed process is advantageous also for the future development toward a higher degree of resolution. However, in the known photoelectric conversion apparatus explained above, in which the refreshing operation for dissipating the carriers accumulated in the base area relies on the forward current between the emitter and the base, the base potential after the refreshing operation is inevitably related to that before the refreshing if the refreshing pulse is short, thus giving rise to drawbacks of a residual image and a non-linearity in the photoelectric conversion characteristic. Fig. 6C is a schematic plan view of another photoelectric conversion apparatus described in the above-mentioned patent references, and Figs. 6D and 6E are respectively a cross-sectional view along a line A - A' and an equivalent circuit diagram. As shown in these drawings, photoelectric conversion cells are arranged on an n-type silicon substrate 601, and each cell is electrically insulated from neighboring cells by separating areas 602 consisting of SiO 2 , Si 3 N 4 or polysilicon. Each cell is constructed in the following manner. On an n - -type area 603 of a low impurity concentration formed for example by an epitaxial process, a p-type base area 604 and a p-type area 605 are formed by doping a p-type impurity such as boron, and an n + -type emitter area 606 is formed in the p-type base area 604. Said p-type base area 604 and the p-type area 605 constitute source and drain areas of a p-channel MOS transistor to be explained later. An oxide film 607 is formed on the n - -type area 603 containing the above-mentioned areas, and a gate electrode 608 for said MOS transistor and a capacitor electrode 609 are formed on said oxide film 607. The capacitor electrode 609 is positioned opposite to the p-type base area 604 across the oxide film 607, thus constituting a capacitor for controlling the base potential. There are also provided an emitter electrode 610 connected to the n + -type emitter area 606 and an electrode 611 connected to the p-type area 605, and, on the bottom face of the substrate 601, a collector electrode 612 across an ohmic contact layer. In the following there will be explained the function of the above-explained photoelectric conversion cell. Light is introduced into the p-type base area 604 to accumulate the carriers (positive holes in this case) corresponding to the amount of incident light in the p-type base area 604 (accumulating operation). The accumulated carriers causes a change in the base potential, which is read from the emitter electrode 610. Thus an electric signal can be obtained corresponding to the amount of incident light (reading operation). In the following there will be explained a refreshing operation for dissipating the positive holes accumulated in the p-type base area 604. Figs. 6F and 6G are wave form charts showing the refreshing operation. As shown in Fig. 6F, the MOS transistor is turned on when a negative voltage exceeding a threshold value is applied to the gate electrode 608. For refreshing, as shown in Fig. 6G, the emitter electrode 610 is grounded, and the electrode 611 is also brought to the ground potential. Then a negative voltage is applied to the gate electrode 608 to turn on the p-channel MOS transistor, whereby the p-type base area 604 is brought to a constant potential regardless of the accumulated potential. Then a refreshing positive pulse is applied to the capacitor electrode 609 to bias the p-type base area 604 in the forward direction with respect to the n + -type emitter area 606, whereby the accumulated positive holes are eliminated through the grounded emitter electrode 610. The p-type base area 604 returns to the initial state of negative potential at the end of the refreshing pulse (refreshing operation). In this manner the remaining charge is dissipated by the refreshing pulse after the potential of the p-type base area 604 is brought to a constant value by the MOS transistor, so that the new accumulating operation can be conducted independently from the preceding accumulating operation. Also a high speed operation is possible since the residual charge can be rapidly dissipated. It is also possible to complete the refreshing operation by turning on the MOS transistor, through the application of a voltage for complete refreshing to the electrode 611. The operations of accumulation, reading and refreshing can thereafter be repeated in the same manner. However such known photoelectric conversion apparatus is still associated with a drawback of a low aperture ratio, due to the presence of the refreshing MOS transistor on the light-receiving surface, and the presence of wirings required for supplying a constant voltage to the electrode 611 and for supplying pulses to the gate of the refreshing MOS transistor, particularly in case of forming an area sensor. Also the structure is complicated by the increased number of driving pulses. Also in such known apparatus, the readout signal contains unnecessary signals such as driving noises and dark signals. The driving noises are generated in the read-out of the signal by driving the photosensor, and include noises resulting from fluctuations in the manufacture, for example in the shape of each element, and smears resulting from the separation of elements and depending on the amount of incident light. The dark signals are caused by dark current in the photosensor, and fluctuate mainly depending on the accumulating time of the photosensor and the ambient temperature. Such driving noises and dark signals become a problem particularly in image taking under a low luminosity, since, in such condition, the obtained signal level is inevitably low, so that such unnecessary signals reduce the S/N ratio and deteriorate the image quality. Such unnecessary signals have to be reduced in order to improve the image quality. However, as explained above, the dark signals depend significantly on the temperature and the accumulating time, while the driving noises are much less dependent on such factors. Consequently the elimination of such unnecessary signals require the separation of these signals and determination of independent correction coefficients, for which required is a large memory capacity, further leading to a complex signal processing, an increased cost and a large space required for the device. In order to avoid such drawbacks, the present applicant already proposed, in the Japanese Patent Application JP-A-63 086 471, a photoelectric conversion device capable of providing an output signal of a high S/N ratio with a simple structure, by subtracting, from the read-out signal of a photoelectric conversion element, the residual signal after refreshing thereof, thereby eliminating the unnecessary components such as dark signals and driving noises. However such structure is still unable to avoid the loss in the aperture ratio, caused by the presence of the separating areas and the refreshing transistors. It has been proposed, in DE-A-3529025 (and equivalent US-A-4586084) to provide a solid state image sensor comprising a matrix arrangement of n-channel normally-on type SITs, each with a gate region capacitively coupled to a row electrode. A control FET is formed vertically in an isolation recess surrounding an SIT, and connects the gate region to an overflow drain which is common to a plurality of SITs. SUMMARY OF THE INVENTION According to the present invention there is provided photoelectric conversion apparatus as set out in claim 1. The remaining claims set out optional features. When the transistors connect the accumulation regions of a pair of cells, a potential applied to one of the accumulation regions is transmitted to the other. In an embodiment of the present invention, the connecting transistor, when turned on, serves to regulate the accumulation semiconductor area of each cell at a constant potential regardless of the amount of accumulated carriers, and, when turned off, serves to electrically separate the photoelectric conversion cells. An embodiment of the present invention provides a photoelectric conversion apparatus capable of achieving a refreshing operation and element separation with a simple structure. An embodiment of the present invention provides a photoelectric conversion apparatus capable of a refreshing operation without the loss in the aperture ratio. An embodiment of the present invention provides a photoelectric conversion apparatus capable of providing an output signal with a high S/N ratio. An embodiment of the present invention provides a photoelectric conversion apparatus capable of reducing the driving system such as transistors, and reducing the size of the circuit thereof. Preferably each photoelectric conversion cell has a capacitor for controlling the potential of said accumulation semiconductor area, wherein the gate electrodes of a desired number of said connecting transistors are connected in common and said capacitors are connected in common to the wiring used for connecting said transistors. Thus, the connecting transistors, when turned on by a voltage applied to said gate electrodes, serve to regulate the potential of the accumulation semiconductor areas of a desired number of the cells to a constant value regardless of the amounts of accumulated carriers therein, and, when turned off, can electrically separate said photoelectric conversion cells. Consequently the aperture ratio can be made larger than in the known apparatus, since the dissipation of accumulated carriers does not require a particular wiring, and since the gate electrode is formed between the cells. Also the common connection of the capacitors and the gate electrodes makes it possible to achieve a highspeed operation, satisfactory residual image characteristic and photoelectric conversion characteristic. In another embodiment, the photoelectric conversion apparatus has first storage means for storing the read-out signals obtained by a reading operation of said photoelectric conversion elements, second storage means for storing residual signals after a refreshing operation of said photoelectric conversion cells, and difference calculating means for calculating the difference between the read-out signals and the residual signals stored in said first and second storage means thereby eliminating the residual signals from said read-out signal, wherein a larger forward bias is applied to said photoelectric conversion elements in said refreshing operation than in other operations. The subtraction of the residual signals after refreshing from the read-out signals makes it possible to remove, from the read-out signals, unnecessary components such as dark signals and driving noises of the photoelectric conversion elements, and the larger forward bias applied to the photoelectric conversion elements in the refreshing operation enables elimination of the unnecessary signals and the residual signals without extending the refreshing time. The refreshing of the photoelectric conversion elements means dissipation of the optical information, such as charges accumulated in said elements, and includes complete refreshing for completely dissipating the optical information and transient refreshing for dissipating said information by means of the transient characteristic of the photoelectric conversion element. In another embodiment, each photoelectric conversion cell has a capacitor for controlling the potential of said accumulation semiconductor area, and there are further provided a first line for applying a control voltage to the gate of said connecting transistor and a second line for applying a control voltage to said capacitor. Thus, said connecting transistors when turned on by a voltage supplied to said first line, serve to regulate the accumulation semiconductor areas simultaneously to a constant potential regardless of the amounts of accumulated carriers therein, and, when turned off, can electrically separate said cells. Also a control voltage supplied to the second line allows to control the potential of said accumulation semiconductor areas, thereby effecting for example a reading operation of the accumulated carriers. Since said second line can be given the control voltage independently from the first line, the voltage of the control line need not be varied by a large amount as in the known apparatus. It is therefore possible to reduce the load of the driving system and to decrease the circuit area. Embodiments of the invention, given by way of nonlimiting example, will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of an embodiment of the photoelectric conversion apparatus of the present invention; Fig. 2 is a partial equivalent circuit diagram of said embodiment; Figs. 3A, 3B and 3C are timing charts showing examples of the function of said embodiment; Fig. 4 is a schematic circuit diagram of a second embodiment of the present invention; Fig. 5 is a partial timing chart showing an example of function of said embodiment; Fig. 6A is a schematic cross-sectional view of a known photoelectric conversion device ; Fig. 6B is an equivalent circuit diagram of a photoelectric conversion cell thereof; Fig. 6C is a schematic plan view of a photoelectric conversion apparatus disclosed in said patent references; Fig. 6D is a cross-sectional view thereof along a line A - A'; Fig. 6E is an equivalent circuit diagram thereof; Figs. 6F and 6G are wave form charts explaining a refreshing operation; Fig. 7A is a schematic plan view of a third embodiment of the electrode pattern of the photoelectric conversion apparatus of the present invention; Fig. 7B is a cross-sectional view along a line I - I; Fig. 7C is a cross-sectional view along a line II - II; Fig. 8 is a circuit diagram of a fourth embodiment of the photoelectric conversion apparatus of the present invention; Fig. 9 is a timing chart showing the function of said embodiment shown in Fig. 8; Fig. 10 is a circuit diagram of a fifth embodiment of the photoelectric conversion apparatus of the present invention; Fig. 11 is a timing chart showing the function of said embodiment shown in Fig. 10; Fig. 12 is a circuit diagram of a sixth embodiment of the present invention; Fig. 13 is a timing chart showing the function of the circuit shown in Fig. 12; Fig. 14A is an equivalent circuit diagram of a seventh embodiment of the photoelectric conversion apparatus of the present invention; Fig. 14B is a timing chart showing the function thereof; and Figs. 15 to 17 are schematic plan views respectively showing eighth to tenth embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Now the present invention will be clarified in detail by embodiments thereof shown in the attached drawings. Fig. 1 is a schematic cross-sectional view of a photoelectric conversion apparatus embodying the present invention, wherein components corresponding to those in Figs. 6A to 6G are represented by corresponding numbers. As shown in Fig. 1, p-type base areas 4 of photoelectric conversion cells are formed at a predetermined pitch on an n - -area 3 constituting a collector area. An n + -type emitter area 5 is formed in each p-type base area 4. An electrode 101 is formed, on an oxide film 6, bridging each p-type base area 4 and a neighboring p-type base area 4. Said electrode 101 is opposed to the p-type base area 4, in a portion above said base area, to constitute a capacitor Cox for controlling the base potential, and, in a portion between the neighboring base areas, serves as a gate electrode for a MOS transistor Tr of which source and drain are composed by said neighboring p-type base areas. In the present embodiment, therefore, the capacitor electrode is connected to the gate electrode of said MOS transistor Tr. Said MOS transistor is constructed, in the present embodiment, as a normally-off p-channel transistor, so that it is turned off when the electrode 101 is at the ground potential or a positive potential. In this state the p-type base areas 4 of the neighboring cells are electrically separated. Conventional separating area is no longer necessary, and this fact is advantageous for compactization of the device. On the other hand, when the electrode 101 is given a negative potential exceeding a threshold value Vth, the MOS transistor Tr is turned on to mutually connect the p-type base areas 4 of the cells. Fig. 2 is a partial equivalent circuit diagram of the present embodiment, wherein a broken-lined area corresponds to a photoelectric conversion cell. As shown in Fig. 2, said cells Sl - Sn are arranged in a linear array and mutually connected. The electrodes 101 of said cells are commonly connected to a terminal 102 for receiving a pulse d. The MOS transistors Tr of the cells are series connected. Unrepresented p-type areas are formed at a predetermined distance from the p-type base areas 4 of the end cells Sl and Sn, and a normally-off p-channel MOS transistor Qx is formed next to the cell Sn. The gate electrode of said MOS transistor Qx receives the same pulse d as that supplied to the electrodes 101, and said unrepresented p-type area is maintained at a constant potential Vc. Also the unrepresented p-type area next to the MOS transistor Tr of the cell Sl is also maintained at the constant potential Vc. Consequently, when all the MOS transistors Tr and Qx are turned on, the p-type base areas 4 of the cells are regulated to the constant potential Vc. On the other hand, said cells are mutually separated electrically, when said transistors are turned off. The emitter electrodes 8 of the cells are grounded respectively through resetting transistors Qbl - Qbn, of which gate electrodes receive a common pulse r. The collector electrodes 12 receive a positive voltage Vcc. A control unit 107 releases the pulses d, r, and scanning pulses for successively scanning the emitter outputs of the cells Sl - Sn. Figs. 3A to 3C are timing charts showing examples of the function of the present embodiment. At first reference is made to Fig. 3A, in which the constant potential is assumed equal to the ground potential, and it is also assumed that the p-type base area of each cell stores carriers by the accumulating operation. At first the pulse d is shifted to a high level, for a duration T1, to supply a positive voltage to the electrodes 101 of the cells. As the pulse r is at the low level, the transistors Qbl - Qbn are turned off whereby the emitter electrodes 8 of the cells are in a floating state. The MOS transistors Tr are turned off in this state by the positive potential of the electrodes 101. Consequently the potential of the p-type base areas 4 is elevated through the capacitors Cox, whereby the reading operation explained before is conducted. The emitter outputs of all the cells Sl - Sn are stored in capacitors and are subsequently read in succession by scanning pulses from the control unit 107. Then the pulse r is shifted to the high level to turn on the transistors Qbl - Qbn, thus grounding the emitter electrodes 8 of the cells. Then the pulse d is shifted to a negative potential to turn on the MOS transistors Tr of the cells and the MOS transistor Qx, thereby mutually connecting all the p-type base areas 4. Thus, in a period T2, the base areas are uniformly shifted to the ground potential Vc regardless of the accumulated potentials therein. When the pulse d is shifted up to the ground potential after the period T2, the base potential is elevated to a positive value, by an amount determined by capacity division. Thus the carriers accumulated in the p-type base area 4 are dissipated in a period T3, but this refreshing operation does not restore the initial state with a negative base potential (inverse bias between base and emitter). The refreshing operation is in fact conducted by a subsequent shift of the pulse d to a positive potential, and the base potential assumes the initial negative state when the pulse d is lowered after a period T4. The accumulating operation is subsequently initiated, and the above-explained operations are thereafter repeated. Since the refreshing operation is conducted in the periods T3 and T4 after the base areas are controlled to the constant potential Vc by turning on the MOS transistors Tr by the pulse d, the base potential after refreshing can be securely brought to a constant level regardless of the potential before refreshing. Also except for the period T2, the cells are electrically separate as the MOS transistors are turned off. The electric separation of the cells can be achieved in this manner without the conventional separating areas, thus contributing to the miniatuarization of the cell structure. Fig. 3B shows a driving method in which the potential Vc is fixed at a negative value, and the refreshing pulse is not applied. In this method, the base areas are initialized to the negative potential Vc by shifting the pulse d to a negative potential in the period T2 when the MOS transistors Tr are turned on. Therefore the accumulating operation can be started without the application of the refreshing pulse. The reading operation can be conducted in the same manner as in Fig. 3A. Fig. 3C shows a driving method suitable for line sensor, in which the outputs are obtained by the function of phototransistors. At first the Vc is fixed at the ground potential, and pulse d is shifted to negative value to turn on the MOS transistors Tr, thereby bringing the base areas to the ground potential. The base potential is elevated to a positive value by the shift of the pulse d to the ground potential. The refreshing operation is conducted while the emitter electrodes 8 are grounded by the pulse r, and the accumulating and reading operations are initiated simultaneous with the shift of the emitter electrodes 8 to the floating state at the downshift of the pulse r. Fig. 4 is a schematic circuit diagram of a second embodiment of the present invention, consisting of an area sensor of m x n pixels, composed of an array of m lines of the line sensors shown in Fig. 2. Each line has a structure shown in Fig. 1, but the lines are electrically separated by ordinary separating areas. The electrodes 101 of the cells in each line are commonly connected, and those of different lines are connected, respectively through switches SWl - SWm, to a terminal 102 receiving a pulse d. The switches SWl - SWm, consisting of analog switches, have control terminals connected to output terminals of a vertical scanning circuit 103, of which output signals vl - vm control the on/off state of said switches. The emitter electrodes 8 of the cells are connected, column by column, to vertical lines Ll -Ln, which are grounded respectively through resetting transistors Qbl - Qbn having gate electrodes for receiving a pulse r. The vertical lines Ll - Ln are respectively connected, through transistors Qal - Qan, to storage capacitors Cl - Cn, which are connected to an output line 104 through transistors Ql - Qn. A pulse t is commonly supplied to the gate electrodes of the transistors Qal - Qan, and pulses hl - hn are respectively supplied from a horizontal scanning circuit 105 to the gate electrodes of the transistors Ql - Qn. The output line 104 is grounded through a transistor Qrh, and is connected to the input terminal of an amplifier 106. The gate electrode of said transistor Qrh receives a pulse rh. The above-mentioned pulses  are supplied by a control unit 107 - l. In the present embodiment, the constant potential Vc for setting the base potential of the cells is selected equal to the ground potential. In the following there will be briefly explained the function of the present embodiment. Fig. 5 is a partial timing chart showing an example of driving method of the present embodiment, according to the driving method shown in Fig. 3A. At first the vertical scanning circuit 103 shifts the pulse vl alone to the high level to turn on the switch SWl. Also the pulse t is shifted to the high level to turn on the transistors Qal - Qan. Then the pulse d is shifted to a positive potential during a period T1 to apply, through the switch SWl, a positive voltage to the electrodes 101 of the cells Sll - Sln of the first line, whereby a reading operation is conducted in the first line and the read-out signals of the first line are stored, respectively through the vertical lines Ll - Ln and the transistors Qal - Qan, in the capacitors Cl - Cn. Then the pulse t is shifted to the low level to turn off the transistors Qal - Qan. Then the horizontal scanning circuit 105 releases the pulses hl - hn in succession, whereby the read-out signals stored in the capacitors Cl - Cn are taken out in succession to the output line 104, and serially released to the outside as an output signal Vout through the amplifier 106. After the release of each read-out signal, the pulse rh is shifted to the high level to turn on the transistor Qrh, thereby eliminating the carriers in the output line 104. Simultaneous with this signal output operation, the pulse r is shifted to the high level to turn on the transistors Qbl - Qbn, thereby grounding the vertical lines Ll - Ln. Also the pulse d is shifted to a negative potential in the period T2, thereby turning on the MOS transistors Tr of the first line. Thus the p-type base areas 4 of the cells Sll - Sln are uniformly shifted to the ground potential as explained before, then returns to the initial negative potential by the refreshing operation in the periods T3 and T4, and start the accumulating operation. After the completion of the operation of the first line in this manner, the pulse vl is shifted to the low level to turn off the switch SWl. Subsequently the pulse t is shifted to the high level to turn on the transistors Qal - Qan, thereby eliminating the carriers remaining in the capacitors Cl - Cn, through the vertical lines Ll - Ln and the transistors Qal - Qan. The above-explained operation is repeated for each line to release the read-out signals from 2nd to m-th lines. Also in the present embodiment, the refreshing operation is conducted in the periods T3 and T4 after the base potential of the cells of different lines is brought to a constant value in the period T2, so that there can be obtained an image sensor device with satisfactory residual image characteristic and satisfactorily linear photoelectric conversion characteristic. In addition, the structure, not requiring the separating areas in the direction-of lines, is suitable for miniaturization of the cells, and is easily capable of achieving a high resolution. The photoelectric conversion apparatus of the foregoing embodiments have, as explained above, insulated-gate connecting transistors each having main electrodes composed of the semiconductor areas of neighboring cells, and are capable of shifting the semiconductor areas of said cells easily to a constant potential regardless of the amount of accumulated carriers, by turning on said insulated-gate connecting transistors, thereby resolving the drawback of residual image and improving the linearity of the photoelectric conversion characteristic. Also the photoelectric conversion cells can be electrically separated with the conventional separating areas by turning off said insulated-gate connecting transistors. The structure can therefore simplify the manufacturing process, and is suitable for the miniaturization of the device. In the following there will be explained a third embodiment of the electrode pattern of the present invention. Fig. 7A is a schematic plan view of a third embodiment of the electrode pattern of the photoelectric conversion apparatus of the present invention, and Figs. 7B and 7C are respectively cross-sectional views thereof along a line I - I and a line II - II. In these drawings, same components as those in Figs. 1 to 6 are represented by same numbers. In Figs. 7A to 7C, an n - -type layer 3 consti tuting a collector area is formed by epitaxial growth on an n-type silicon substrate 1, and p-type base areas 4 and n + -type emitter areas 5 are formed therein to constitute bipolar transistors. The p-type base areas 4 are two-dimensionally arranged as shown in Fig. 7A, and the cells in the horizontal line are separated from those in the upper and lower lines by separating areas, which are composed, as shown in Fig. 7C, of an oxide film 6' formed by LOCOS oxidation and an n + -type area 108 formed thereunder. Also bridging the p-type base areas 4 neighboring in the horizontal direction, a gate electrode 101 is formed on an oxide film 6 as shown in Fig. 7B. Consequently a p-channel MOS transistor is formed, with the source and drain composed of the neighboring p-type base areas 4. Said MOS transistor, being of normally-off type, is turned off when the gate electrode 101 is at the ground potential or a positive potential, thereby electrically separating the p-type base areas of the neighboring cells. On the other hand, if the gate electrode 101 is given a negative potential exceeding a threshold value Vth, said transistor is turned on to mutually connect the p-type base areas 4 of the cells. As shown in Fig. 7A, the gate electrodes 101 are commonly connected, in the unit of each line, to a driving line 101", to which likewise connected are capacitor electrodes 101' for controlling the potential of the p-type base areas 4. The driving line 101" extends horizontally over the oxide film 6' constituting the separating areas. After the formation of transparent insulating layers 9, there are formed emitter electrodes 8 which are connected, column by column, to vertical lines 8'. A collector electrode 12 is formed on the bottom face of the substrate 1, across an ohmic contact layer. The area sensor of the present embodiment does not require particular wirings for complete refreshing. Thus the area sensor requires, for driving, a vertical scanning pulse d and a resetting pulse r. Also the absence of the MOS transistor, for complete refreshing, on the light receiving surface enables a high speed operation without sacrificing the aperture ratio. Also the common connection of the gate electrodes and the capacitor electrodes makes it possible to achieve a high speed operation with a limited number of driving pulses. Fig. 8 is a circuit diagram of a fourth embodiment of the photoelectric conversion apparatus of the present invention. As shown in Fig. 8, the emitter electrodes 8 of cells Sl - Sn of the apparatus are respectively connected to vertical lines Ll - Ln which are respectively grounded through transistors Qr. Each of the vertical lines Ll - Ln is connected, respectively through transistors Qt1 and Qt2, to storage capacitors Ct1, Ct2, which are respectively connected, through transistors Qh1, Qh2, to output lines 203, 204. The gate electrodes of the transistors Qr receive a pulse r, while the gate electrodes of the transistors Qt1, Qt2 respective receive pulses t1, t2, and the gate electrodes of the transistors Qh1, Qh2 receive scanning pulses h1, h2 from a scanning circuit 201. The output lines 203, 204 are connected to a differential amplifier 202, and are grounded respectively through transistors Qrh1, Qrh2 receiving a resetting pulse rh at the gate electrodes thereof. Said pulses  are released by a control unit 107 - 2. Now reference is made to a timing chart in Fig. 9 for explaining the function of the above-explained photoelectric conversion device. At first the transistors Qtl Qr are turned on by the pulses tl, r in a period T1 to discharge the capacitors Ctl to the ground potential. Then the pulse d is supplied to the horizontal line HL while the transistors Qtl are turned on to bias the transistors of the photoelectric conversion cells Sl - Sn in the forward direction, whereby the read-out signals are stored in the capacitors Ctl (period T2). Subsequently the cells Sl - Sn are refreshed by turning on the transistors Qr with the pulse r while the pulse d is applied. Simultaneously the transistors Qt2 are turned on by the pulse t2 to discharge the capacitors Ct2 to the ground potential (period T3). Upon completion of the refreshing operation, the transistors Qr are turned off by the pulse r while the pulses d and t2 are applied, whereby the signals remaining in the cells Sl - Sn after refreshing are stored in the capacitors Ct2 (period T4). After the read-out signals and the residual signals of the cells Sl - Sn are stored in the capacitors Ct1, Ct2, the scanning circuit 201 supplies the pulse hl to the gate electrodes of the transistors Qh1, Qh2, whereby the read-out signal and the residual signal of the cell Sl, respectively stored in the capacitors Ct1, Ct2 appear on the output lines 203, 204 and are processed by the differential amplifier 202. The read-out signal appearing on the output line 203 contains unnecessary signals which however are removed in the process by the differential amplifier. After the release of the output of the cell Sl, the resetting pulse rh turns on the transistors Qrhl, Qrh2 to eliminate the charges remaining on the output lines 203, 204. Thereafter the pulses h2 - hn cause the read-out signals and residual signals of the cells S2 - Sn to be transferred from the capacitors Ctl, Ct2 to the output lines 203, 204, whereby output signals Sout are obtained in succession from the differential amplifier 202. At the same time the pulse r turns on the transistors Qr to ground the emitter electrodes 8 of the cells Sl - Sn, and the pulse d is shifted to a negative potential to turn on the MOS transistors Tr, thereby connecting the base areas of all the cells. Thus the base areas of the cells are uniformly brought to the ground potential regardless of the accumulated potentials thereof (period T5). Then by a shift of the pulse d to the ground potential, the base potential is elevated by the capacity division to assume a positive value. Consequently the carriers accumulated in the base area are dissipated, but this refreshing operation does not bring the base potential to the initial negative state (inverse bias between the base and the emitter) (period T6). Subsequently the refreshing operation is conducted by the shift of the pulse d to a positive potential, and the base potential returns to the initial negative state at the end of said pulse (period T7). Then the accumulating operation is started, and the above-explained steps are repeated. The present embodiment, in which the refreshing operation is conducted in the periods T5 to T7 in addition to the period T3, can achieve further elimination of the residual image and unnecessary signals, thereby providing an output signal of a high S/N ratio. In a photoelectric conversion apparatus, in order to completely eliminate the residual image and unnecessary signals and to obtain an output signal of a high S/N ratio, it is necessary to sufficiently conduct the refreshing operations before and after reading the residual image signal. Also in the above-explained apparatus it is desirable to conduct a refreshing operation in the periods T5 to T7 before the reading of the residual image signal, but an excessively long refreshing period before reading the residual signal is not desirable. Particularly when the apparatus is to be used as an area sensor for a video camera, the refreshing operation requires a horizontal scanning period, so that the read-out signal has to be delayed by said period. For this purpose a corresponding memory capacity has to be formed in the chip of the device, thus inevitably increasing the size of the chip. In addition the aforementioned driving method has a room for improvement in order to increase the correlation between the unnecessary signal and the residual signal contained in the read-out signal, thereby further improving the S/N ratio. Fig. 10 is a circuit diagram of a fifth embodiment of the present invention, wherein same components as those in Fig. 8 are represented by same numbers. In the present embodiment there is shown an area sensor of m × n pixels, composed of m lines of photoelectric conversion cells Sl - Sn as shown in Fig. 8. As shown in Fig. 10, in each of horizontal lines HL1 - HLm, electrodes 101 of the cells and the gate electrode of a transistor Qx are connected, through a transistor Qv, to a terminal 102 receiving a driving pulse d. The gate electrodes of said transistors Qv of the horizontal lines HLl - HLm are respectively connected to output terminals of a vertical scanning circuit 103, thus receiving vertical scanning pulses vl - vm. Said vertical scanning circuit 103 and the transistors Qv of the horizontal lines constitute a vertical scanning unit. The emitter electrodes 8 of the cells are connected, column by column, to vertical lines Ll - Ln, which are connected, respectively through transistors Qr, to a power source Vr. A photosensor unit 206 is composed of said transistors Qr, cells Sll - Smn, and transistors Qx connected to the horizontal lines. Also as shown in Fig. 8, each of the vertical lines Ll - Ln is connected, respectively through transistors Qt1, Qt2, to capacitors Ct1, Ct2, which are respectively connected to output lines 203, 204 through transistors Qh1, Qh2. The gate electrodes of the transistors Qh1, Qh2 of the vertical lines L1 - Ln respectively receive horizontal scanning pulses hl - hn from a horizontal scanning circuit 105. The output lines 203, 204 are connected to a differential amplifier 202, and are respectively connected, through transistors Qrh1, Qrh2, to the ground and to a power source Vrh2. The remaining structure is same as that shown in Fig. 8. The above-mentioned various pulses  are supplied by a control unit 107 - 3. Now reference is made to a timing chart shown in Fig. 11 for explaining the function of the present embodiment. Fig. 11 only shows the function of a first horizontal line HL1. In Fig. 11, 1H indicates the horizontal scanning period of a television signal, and a period T5 corresponds to the effective scanning period thereof. At first the vertical scanning circuit 103 releases the scanning pulse vl for a period 1H, thereby turning on the transistor Qv of the first horizontal line HLl. Then the transistors Qtl and Qr are turned on by the pulses tl, r to discharge the capacitors Ctl to the potential V A of the power source Vr (period T1). Then the pulse d is applied while the transistors Qtl are turned on to bias the cells S11 - Sln in the forward direction, whereby the read-out signals are stored in the capacitors Ctl (period T2). Subsequently the transistors Qtl are turned off while the pulse d is supplied, and the transistors Qr are turned on by the pulse r. If the potential of the power source Vr is reduced from V A to V B (V B < V A ), the cells Sll - Sln are subjected to a transient refreshing under a deeper forward biasing than in the period T2. Also the transistors Qt2 are turned on by the pulse t2 to discharge the capacitors Ct2 to the potential V B of the power source Vr (period T3). The operations in the subsequent periods T4 - T7 are same as those shown in Fig. 9. The resetting potential Vrh2 of the output line 204 is selected equal to K(V A - V B ), wherein K = Ct2/(Ct2 + Ch2) in which Ch2 is the line capacitance of the output line 204, in order to have a same reference potential for comparison, for the capacitors Ctl discharged to the potential V A in the period T1 and for the capacitors Ct2 discharged to the potential V B in the period T3. The foregoing operations are thereafter repeated for other lines to obtain the read-out signals for the horizontal lines HL2 - HLm in succession. As explained in the foregoing, it is rendered possible to eliminate the residual image component and the unnecessary signals in the cells and to improve the S/N ratio through a short refreshing operation, by reducing the potential of the power source Vr in the transient refreshing period T3 before reading the residual signal, thereby sufficiently biasing the photoelectric conversion cells in the forward direction. It is also possible to modify the forward bias state by varying the potential of the pulse d while maintaining the power source Vr at a constant value. Fig. 12 is a circuit diagram of a sixth embodiment of the present invention, wherein the vertical scanning unit and the photosensor unit 206 are omitted as they are same as those in Fig. 10. In the present embodiment, between the scanning transistors Qh1, Qh2 and the output lines 203, 204 there is provided a buffer amplifier 205, consisting of a bipolar transistor, for preventing the level loss of the signals of the capacitors Ct1, Ct2 caused by the line capacitances Ch1, Ch2 when said signals are read to the lines 203, 204, and for enabling a high-speed scanning. The base electrode of the amplifier 205 is commonly connected to the transistors Qh1, Qh2 and is grounded through a transistor Qbc driven by a pulse bc. The emitter of said amplifier is connected, respectively through second scanning transistors Qh1', Qh2', to the output lines 203, 204. Said transistors Qh1', Qh2' are driven, together with the transistors Qh1, Qh2, by two-phase horizontal scanning pulses a (al - an) and b (bl -bn). The collector of said amplifier receives a constant positive voltage. The output lines 203, 204 are respectively connected to the ground and to a power source Vrh2, respectively through transistors Qrh1, Qrh2, of which gate electrodes respectively receive resetting pulses rh1, rh2. The output terminal of the differential amplifier 202 is connected to a sample hold circuit 207 for sampling the input signal in response to a pulse sh. The remaining structure is same as that shown in Fig. 10. The various pulses  are supplied by a control unit 107 - 4. The function of the present embodiment will be explained in reference to Fig. 13 which shows the function in the period T5 only. Other periods are omitted as they are same as in Fig. 11. At first, at a time t 51 , the first pulse al of said two-phase scanning pulses turns on the transistors Qhl and Qhl', whereby the read-out signal stored in the capacitor Ctl is supplied to the output line 203 and stored in the line capacitance Chl. Then, at a time t 52 , the pulse bc turns on the transistor Qbc, thereby dissipating the charges remaining in the capacitor Ctl and the base electrode of the amplifier 205. The signal stored in the line 203 remains unchanged since, in this state, the amplifier 205 is inversely biased and is therefore non-conductive. Also the pulse rh2 turns on the transistor Qrh2, thereby clearing the output line 204 to the potential Vrh2. Said potential Vrh2 is selected equal to -(V A - V B ), in order to have a constant bias for the amplifier 205, in releasing the readout signal of the capacitor Ctl to the output line 203 and in releasing the readout signal of the capacitor Ct2 to the output line 204. Then, at a time t 53 , the second pulse b1 of the two-phase scanning pulses turns on the transistors Qh2 and Qh2', whereby the residual signal stored in the capacitor Ct2 is released to the output line 203 and accumulated in the line capacitance Ch2. Consequently the differential amplifier 202 receives the signals stored in the capacitors Ct1 and Ct2, and the output signal Sout of said amplifier is sampled in the sample hold circuit 206 by the pulse sh and released as an output signal Sout'. At a time t 54 , the pulse bc turns on the transistor Qbc to dissipate the charges remaining in the capacitor Ct2 and the base electrode of the amplifier 205. Also the pulse rh1 turns on the transistor Qrh1, thereby clearing the output 203 to the ground potential. Thereafter the signals of the capacitors Ct1, Ct2 are released in succession by the horizontal scanning pulses a2,b2 - an, bn from the horizontal scanning circuit 105. In the present embodiment, therefore, the presence of buffer amplifiers enable direct driving of the output lines and a high-speed transfer of the signals without level loss. The fifth and sixth embodiments of the present invention explained above are capable of providing an output signal of a high S/N ratio through a simple method of eliminating the dark signal and unnecessary signal such as driving noises of the photoelectric conversion elements from the read-out signal by subtracting the residual signal after refreshing from the read-out signal of the photoelectric conversion elements, and of eliminating the residual image component and unnecessary components in a short period by applying a deeper forward bias to said elements in the refreshing operation than in other process steps. Fig. 14A is an equivalent circuit diagram of a seventh embodiment of the present invention, and Fig. 14B is a timing chart showing the function thereof. The function of the present embodiment basically consists of the steps of accumulation, reading and refreshing as explained in relation to Fig. 3. In the foregoing photoelectric conversion apparatus, however, the driving line 102 has to be given pulses d for example of ± 5V. Consequently, the vertical shift register in an area sensor has to withstand a voltage swing of ± 10 V. The use of a thicker insulating film for withstanding inevitably increases the circuit area of said shift register. Particularly a shift register with a boost trap capacity requires a larger area in order to compensate the loss in capacity caused by the use of a thicker insulating film. The present embodiment is proposed for resolving this drawback. More specifically, as shown in Fig. 14A, the electrode 101' of a capacitor Cox is connected to a driving line 215 receiving a pulse d1, which is used for effecting the reading operation by applying a positive voltage to the capacitor Cox as explained before. Also the gate electrode 101 of a MOS transistor Qr is connected to a driving line 101" receiving a negative voltage pulse d2, which is for on/off control of the p-channel MOS transistor Qr and for resetting each p-type base area 4 to a constant potential in the refreshing operation, as explained before. The reading operation is conducted by applying a positive voltage pulse d1 to the driving line 215 as shown in Fig. 14B. Said positive voltage pulse d1 elevates the potential of the P-type base area 4, thereby applying a forward bias between the base and the emitter and releasing the accumulated voltage to a vertical line 8' through the emitter electrode 8, thus obtaining a read-out signal S. The threshold voltage Vth of said p-channel MOS transistor Qr is so determined that it is turned off with a gate potential of 0V. The refreshing operation is conducted in the following manner. A pulse vc turns on the transistor Qvc, thereby grounding the vertical line 8' and eliminating the retentive charge. Simultaneously the p-channel MOS transistor Qr is turned on by a negative voltage pulse d2, thereby completely refreshing the p-type base area 4. Upon completion of the refreshing operation, the p-type base areas 4 return to the initial potential and start an accumulating operation for accumulating the photoexcited carriers. Thereafter the photoelectric converted signals are obtained through repeated cycles of reading, refreshing and accumulation. In this manner, the use of a driving line 101" for applying the negative voltage pulse d2 and another line 215 for applying the positive voltage pulse d1 reduces the pulse amplitude in each line a half, thus reducing the burden of the driving system such as the shift register and avoiding the problem of voltage resistance. Fig. 15 is a schematic plan view of a eighth embodiment of the present invention, wherein components corresponding to those in Fig. 7A are represented by same numbers. The driving line 215 for applying the pulse d1 and the vertical lines 8' are composed of aluminum, while the driving line 101" for applying the pulse d2 and the gate electrodes 101 are composed of polysilicon. Fig. 16 is a schematic plan view of an ninth embodiment of the present invention. In the present embodiment the driving lines 101" and 215 are alternately provided on the separating areas, and the reading or refreshing operation is simultaneously conducted for two neighboring lines. This structure makes it possible to increase the aperture ratio, since the light-receiving area is not blocked by the driving line 215 as in the case of the eighth embodiment. Fig. 17 is a schematic plan view of a tenth embodiment of the present invention. In the present embodiment, the driving lines 101" and 215 are formed in plural layers on a separating area, thus improving the aperture ratio in comparison with the eighth embodiment. Though two lines are simultaneously read in the ninth embodiment, the tenth embodiment allows signal reading of each line or interlace scanning. The photoelectric conversion apparatus of the eighth to tenth embodiments of the present invention is provided, as detailedly explained in the foregoing, with a first line for driving insulated-gate connecting transistors and a second line for applying a control voltage to capacitors for controlling the potential of the semiconductor areas of the photoelectric conversion cells, so that the voltage range can be reduced in comparison with that in the conventional line for driving the photoelectric conversion cells. It is therefore rendered possible to resolve the problem of voltage resistance, and to reduce the burden of the driving system and the malfunctions. Also the circuit area, including the driving system, can be easily reduced since the insulating film need not be made thicker for withstanding a higher voltage.

Claims: Photoelectric conversion apparatus comprising an array of photoelectric conversion cells (S1, S2, ... Sn), each having an accumulation semiconductor region (4) for accumulating carriers in response to photoexcitation, characterised in that the apparatus comprises a plurality of connecting MOSFET transistors (Tr) each arranged to connect or disconnect a respective pair of adjacent said cells, each said transistor having a source region composed of the accumulation region (4) of one of said pair of cells, a drain region composed of the accumulation region (4) of the other of said pair of cells, and an insulated gate electrode (101) between the said pair of cells, for electrically connecting or disconnecting said source and drain regions. Apparatus according to claim 1 in which the insulated gate electrode (101) extends along a first part of the periphery of one of the said cells and a separation region (108) extends along a second part of the periphery of the cell. Apparatus according to claim 1 or claim 2 in which at the position of each said connecting transistor (Tr), there is no separation region in addition to the connecting transistor between the respective adjacent said cells. Apparatus according to any one of claims 1 to 3 in which each said cell (S1, S2, ... Sn) comprises a control electrode (101') capacitively coupled to the accumulation region (4) and electrically connected to the insulated gate electrode (101) of a said connecting transistor (Tr) arranged to connect the cell to or disconnect it from an adjacent cell. Apparatus according to any one of claims 1 to 3 in which each said cell (S1, S2, ... Sn) comprises a control electrode (101') capacitively coupled to the accumulation region (4) and electrically separate from the insulated gate electrode (101) of a said connecting transistor (Tr) arranged to connect the cell to or disconnect it from an adjacent cell. Apparatus according to claim 5 comprising control means (215, 101") for providing separate signals to the control electrode (101') and the insulated gate electrode (101). Apparatus according to any one of the preceding claims in which the accumulation region (4) of each cell (S1, S2, ... Sn) is the base region of a photo-sensitive transistor. Apparatus according to claim 7 in which adjacent cells share a common collector region (3) which also provides a channel region between the cells controlled by the insulated gate electrode (101). Apparatus according to any one of the preceding claims in which a plurality of said cells (S2, S3, ... Sn-1) are each provided with a first said connecting transistor (Tr) to connect the cell to or disconnect the cell from a first adjacent cell, and a second said connecting transistor (Tr) to connect the cell to or disconnect the cell from a second adjacent cell. Apparatus according to any one of the preceding claims which comprises means (Tr, Qx) to apply a predetermined potential (Vc) to the accumulation region (4) of a said cell while a said connecting transistor (Tr) connects the accumulation region of the cell to the accumulation region of an adjacent said cell, whereby the predetermined potential (Vc) is transmitted to the accumulation region of the adjacent cell. Apparatus according to any one of the preceding claims, further comprising accumulation means (Ct1, Ct2) respectively connected to the said photoelectric conversion cells for separately accumulating a noise signal and a photoelectrically converted signal. Apparatus according to claim 11, further comprising calculation means (202) for processing said noise signal and said photoelectrically converted signal accumulated in each of said accumulation means. A photoelectric conversion apparatus according to claim 12, wherein said calculation means comprises subtracting means. Apparatus according to any one of the preceding claims comprising control means (107,103) for applying a first voltage to the gate electrodes (101) of the said connecting transistors (Tr), to turn on the connecting transistors and connect said pairs of adjacent cells for resetting, and for applying a second voltage to the gate electrodes (101) of the said connecting transistors (Tr), to disconnect said pairs of adjacent cells from each other. Apparatus according to claim 7 or claim 8 comprising: first storage means (Qt1, Ct1) for effecting a reading operation on said photoelectric conversion cells and storing read-out signals therefrom; second storage means (Qt2, Ct2) for effecting a refreshing operation on said photoelectric conversion cells and storing signals remaining immediately after said refreshing operation; process means (202) for processing the read-out signal and the remaining signal respectively stored in said first and second storage means thereby eliminating the remaining signal from said read-out signal; and control means (107) for applying a deeper forward bias to the base regions (4) of said photoelectric conversion cells in said refreshing operation than in said reading operation.

Inventors: HASHIMOTO SEIJI, MIYAWAKI MAMORU, SHINOHARA MAHITO, SUGAWA SHIGETOSHI, HASHIMOTO, SEIJI, MIYAWAKI, MAMORU, SHINOHARA, MAHITO, SUGAWA, SHIGETOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1988
Main classification: H04N3
IPC codes: H04N3, H01L27