PROGRAMMABLE LOGIC DEVICE

Abstract: Selectors (4) for input signals into a flip-flop circuit (3) are provided, by which an output from a combinational logic circuit (2) of its own PLE and an output from another PLE are made selectable, and the output from the combinational logic circuit is output independently of an output from the flip-flop circuit, so that either one of the outputs can be utilizable by use of external programmable wiring. Further, by the selection of the respective input selectors of the flip-flop circuit, an output signal from the adjoining flip-flop circuits is inputtable, so that the flip-flop circuits can be serially connected to each other. Furthermore a last flip-flop circuit (3B) of one PLE (1′) supplies an output signal to a first flip-flop circuit (3A) of the adjoining PLE (1) by the selection of the input selector (4A) through connecting wiring for specialized use, so that PLEs adjoining to each other can be connected to each other without passing through the programmable wirings (8).

Description: The present invention relates to a programmable logic device (hereinafter referred to as "PLD") including a plurality of programmable logic elements (hereinafter referred to "PLE") having a plurality of flip-flop circuits. There has heretofore been known a PLD in which optional logic circuits are practicably arranged by a user who programs the device himself. For example, as an example, there is the one disclosed in JP-A-61 198 919 and JP-A-61 224 520. Fig. 5 is a block diagram of a PLD. In this PLD, a plurality of PLEs 101 are provided on a chip 100, and further, input terminals and output terminals of PLEs 101 can be desirably connected to each other by programmable wiring means 102 in vertical and horizontal directions between the terminals. The PLE 101 has a combinational logic circuit such as a programmable logic array (hereinafter referred to as "PLA") having a programmable AND plane or OR plane, and a table look-up type logic circuit, and may have one or a plurality of flip-flop circuits (hereinafter referred to as "F/F") as necessary. Figs. 6 and 7 are circuit diagrams showing the conventional examples of the PLE 101. In a PLE 101 shown in Fig. 6, output signals from a programmable combinational logic circuit 103 are connected to a plurality of D input terminals of a plurality of F/Fs 104 where the input signals are subjected to a sampling by a clock signal input into a clock input terminal 105, and output terminals 106 of the D-F/Fs 104 are formed to provide output terminals of the PLE 101. Another PLE 101' shown in Fig. 7 has substantially the same arrangement as that shown in Fig. 6. However, outputs from the programmable combinational logic circuit 103 and outputs from the D-F/F 104 are received by multiplexers 107 as their input signals and the multiplexers 107 selectively output either one of these input signals. Output terminals 108 of the multiplexers 107 are formed to provide output terminals of the PLE 101'. However, the PLD in the conventional techniques suffers from the following problems. (1) As shown in Fig. 6, when the outputs of the PLE 101 are obtainable only from the F/Fs 104, if it is desired to obtain outputs directly from the programmable combinational logic circuit 103, the only way do this is to omit the F/F 104. Accordingly, there occurs a case where the PLE 101 having the F/F 104 is not used or not usable. (2) As shown in Fig. 7, when the aforesaid two outputs are switched over, the problem of the aforesaid Item (1) can be solved, however, the F/F 104 can be used only alternatively, namely used or not used. Accordingly, when the F/F 104s are not used, wastage results. This becomes significant as the number of the F/Fs 104 in the PLE 101' is increased. Fig. 8 is a conventional circuit arrangement diagram of the PLD, in which the PLE 101' has a plurality of (two in the drawing) F/Fs 104A and 104B as shown in Fig. 7. This conventional PLD has a plurality of PLEs 101' and programmable wiring 102 disposed in both vertical and horizontal directions. Similarly to that shown in Fig. 7, the PLE 101' comprises: the programmable combinational logic circuit 103; the two F/Fs 104A and 104B which receive outputs from this programmable combinational circuit 103 as their inputs; and the multiplexers 107A and 107B which selectively output to the output terminals 108 either an output signal from outputs from the F/Fs 104A and 104B, or an output signal from the programmable combinational logic circuit 103. Furthermore, the programmable wirings 102 have; switch arrays 112 capable of freely connecting respective wirings with each other at points where wirings in vertical and horizontal directions intersect each other; and input/output switch arrays 113 capable of freely connecting the input terminals 110 and the output terminals 108 of the PLEs 101' to the respective wirings. Fig. 9 is a connection diagram of a four bit counter circuit formed by the conventional PLD as shown in Fig. 8. Respective output signals from the F/Fs 104A and 104B of the conventional PLE 101', together with output signals from the programmable combinational logic circuit 103, are passed through the multiplexers 107A and 107B and connected to the output terminals 108 of the PLE 101'. Accordingly, needless to say in a case where an output signal from one 104A of the F/Fs is input into another PLE 101', when it is desired to input the aforesaid output signal into the other 104B of the F/Fs of the same PLE 101', it is necessary to connect through the programmable wirings 102. For this reason, when four F/Fs were connected together to form a four bit counter circuit as shown in Fig. 3, in the past, the connections shown as solid lines in Fig. 9 were necessary. That is, by programming the respective switch arrays 112, the input/output arrays 103, the programmable combinational logic circuits 103 and the multiplexers 107A and 107B, the output terminals 108 of the PLE 101' were respectively connected to the input terminals 110 of the original or another PLE 101', that is, input terminals of the programmable combinational circuits 103. However, in the conventional PLD, when an output signal of a F/F of a PLE is connected to a F/F of the same or another PLE to form a counter circuit or the like, the output signal of the F/F has to be connected via programmable wirings 102 and the programmable combinational logic circuit 103, which have a relatively long delay time. Accordingly, there has been the problem that the operation frequency is restricted. An article in Elektronik, Vol. 36, No. 19, 18th September 1987, p.30 and 31 by H. Biebel discloses a programmable logic element having a combinational logic circuit and two flip-flop circuits each of which has a selecting means for switching either an output of the combinational logic circuit or a data input signal to an input terminal of the flip-flop circuit, the programmable logic element being provided with output terminals connected to outputs of the combinational logic circuit and to outputs of each of the flip-flops. The configuration of this programmable logic element is similar to that of Fig. 1. The present invention has been developed in view of the above-described disadvantages and embodiments thereof may provide a PLD capable of improving the use efficiencies of F/Fs and a combinational logic circuit included in a PLE. Embodiments of the present invention may also provide a PLD including a plurality of PLEs each having a plurality of F/Fs, wherein output and input signals of the respective F/Fs are connected to each other, to thereby raise the operation frequency of a realised circuit. According to the present invention, there is provided a programmable logic device having a plurality of programmable logic elements capable of forming an optional logic circuit by programming of programmable links connecting input terminals and output terminals of said programmable logic elements to each other, wherein:- said programmable logic elements have a combinational logic circuit; a number N of flip-flop circuits each of which has a selecting means for switching one of either an output of the said combinational logic circuits or an output from another programmable logic element or an output of another flip-flop circuit of the same programmable logic element, to an input terminal of said flip-flop circuit; and said programmable logic elements are provided with output terminals connected to outputs of said combinational logic circuit and output terminals connected to outputs of each of said flip-flops. In this way, by means of the section for switching inputs into the F/Fs, the output from the combinational logic circuit in one PLE and the output from another PLE can be selected, and the output from the combinational logic circuit is output independently of the outputs from the F/Fs. Either one of the output from the combinational logic circuit and the outputs from the F/Fs are made utilisable by means of external programmable wirings or the like. Therefore, by the selected input and the independent outputs, each of the plurality of F/Fs in the PLE and the combinational logic circuit can be used either independently of each other or interconnectively. Accordingly, in the use of the F/Fs and the combinational logic circuit, high freedom and flexibility are obtainable, thus improving the use efficiencies thereof. In the present invention, means for selecting one of the signals input into the respective F/Fs is provided, and, by the selection made by this selecting means, output signals from the adjoining F/Fs are input into each other, thus linking the F/Fs in a serial connection. The last F/F of one PLE inputs its output signal into the first F/F of the adjoining PLE through a connecting line specially used by the selecting means of the first F/F of the adjoining PLE, so that a mutual relationship therebetween can be established. As described above, the input and output signals of the F/Fs are directly connected to each other through the selecting means, rather than through programmable wirings or input terminals of the PLE, which introduce long delay times. With this arrangement, the connections between the F/Fs make it possible to raise the operation frequency of the realised counter circuit and the like to a high speed. Reference is made, by way of example, to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof and wherein:- Fig. 1 is a circuit diagram of a PLE which can be used in the present invention; Fig. 2 is a circuit arrangement diagram of a PLD showing an embodiment of the present invention; Fig. 3 is a circuit diagram of a counter circuit realised by use of the PLD of Fig. 2; Fig. 4 is a graph for comparing the effects of the Fig. 2 embodiment and a conventional example; Fig. 5 is an arrangement diagram of a PLD; Figs. 6 and 7 are circuit diagrams showing conventional examples; Fig. 8 is a circuit arrangement diagram of a conventional PLD; and Fig. 9 is a connection diagram in which the conventional PLD of Fig. 8 is used. An embodiment of the present invention will now be described in detail with reference to the accompanying drawings, beginning with a description of Fig. 1 by way of background explanation. Fig. 1 is a circuit diagram of a PLE which is similar to that shown in the above-mentioned Elektronik article and which can be adapted for use in the present invention. The PLE 1 includes a programmable combinational logic circuit 2, a plurality of D-type F/Fs 3 and selectors 4, and is assembled into a PLD as shown in Fig. 5. The programmable combinational logic circuit 2 has a programmable logic array (hereinafter referred to as "PLA") including an AND plane or an OR plane, which have programmable product term lines, or a combinational logic circuit including memory for storing a logic specification per combination of inputs of input terminals 2a, to thereby obtain a logic output by a table look-up system. Outputs from the combinational logic circuit 2 are connected to independent combinational logical output terminals 5 and to one input 4a of input terminals of the selectors 4. The selector 4 comprises two OR-connected n-channel MOS FETs, either one of which is programmed to be in an "on" state, so that an input into this one of the MOS FETs is selected as the output. This selected output is connected to a D input terminal of the F/Fs 3. Connected to one 4a of the input terminals of the selectors 4 is an output from the combinational logic circuit 2, the other 4b of the input terminals being used as a F/F input terminal, to which an external input is supplied. The F/Fs 3 each have clock input terminals (common or independent) 6 and F/F output terminals 7 which can output independently of each other. The F/Fs 3 are not limited to D types, and may be formed by other types. The operation of the above-described circuit arrangement is as follows. When inputs into the input terminals 4a on one side of the selectors 4, that is, outputs from the combinational logic circuit 2, are selected and applied to the D input terminals of the F/Fs 3, the outputs from the combinational logic circuit 2 are subjected to sampling by a clock and can be output from the output terminals 7 of the F/Fs 3. When the input terminals 4b on the other side of the selector 4 are selected, in the F/Fs 3, outputs externally input from other logic elements are subjected to sampling by the clock and can be output from the output terminals 7 of the F/Fs 3. At this time, the outputs from the combinational logic circuit 2 can be output from combinational logic output terminals 5 provided independently of the output terminals 7 of the F/Fs 3. Namely, the combinational logic outputs can be used for independent purposes. Of course, since there are a plurality of F/Fs 3, some of the F/Fs 3 can be used for independent purposes and others can be connected to the output terminals of the combinational logic circuit 2 for combinational use. Furthermore, in the present invention, a shift circuit and the like can be formed by connecting the output terminal or terminals of the F/Fs 3 to the input terminal or terminals 4b of other ones of the F/Fs 3. As described above, in using the F/Fs 3 and the combinational logic circuit 2, the freedom of connection is increased to allow greater flexibility, so that the remaining F/Fs in the PLE can be effectively utilised, thus improving the use efficiency. An embodiment of the present invention will now be described in detail. Fig. 2 is a circuit arrangement diagram of the PLD showing an embodiment of the present invention. This embodiment has a plurality of PLEs 1 and a plurality of programmable wirings 8 disposed in vertical and horizontal directions between the PLEs 1. The PLE 1 has:- a programmable combinational logic circuit 2 for producing optional combinational logic outputs in response to input signals 2a by programming; two D-type F/Fs 3A and 3B; input selectors 4A and 4B connected to the D input terminals of the two F/Fs 3A and 3B, respectively, providing selecting means for selecting input signals; and output selectors 18A and 18B for selecting either output signals from the F/Fs 3A and 3B or output signals from the programmable combinational logic circuit 2 to output the same to a plurality of (two in the drawing) output terminals 17, respectively. Here, separately connected to some of the input terminals of the input selector 4A of a first F/F 3A are a non-inverted output signal Q and an inverted output signal Q from a second (last) F/F 3B of an adjoining PLE 1', and connected to the other input terminals of PLE 1 are output signals from its own programmable combinational logic circuit 2. Furthermore, separately connected to some of the input terminals of the input selector 4B of the second F/F 3B are a non-inverted output signal Q and an inverted output signal Q from the first F/F 3A, and connected to the other input terminals are the other output signals from the programmable combinational logic circuit 2. The output signals Q and Q from the second F/F 3B are directly connected to input selectors of the first F/F of the further adjoining PLE, as necessary. In the programmable wirings 8, switch arrays 21 are provided at intersections of the wirings disposed in vertical and horizontal directions. Input/output switch arrays 22 are provided at the intersections, and the above-described members are programmed respectively, so that the input signals to and the output signals from the respective PLEs 1 can be wired mutually and freely. Clock signals to the clock input terminals C of the F/Fs 3A and 3B are connected to the programmable wirings 8 through input/output switches 22, whereby the clock signals are supplied from inside or outside of this PLD. The operation of this embodiment will now be described. Fig. 3 is a circuit diagram of a four-bit counter circuit which employs the Fig. 2 PLD. This counter circuit includes four D-type F/Fs 3A (3B), in which D input terminals are serially connected, an AND gate 30 and a NOR gate 34. When this counter circuit is programmed on the PLD in this embodiment, the portions where the output terminals and the D input terminals of the F/Fs 3A (3B) are serially connected are directly connected to each other through the respective selectors 4A as indicated by solid lines in Fig. 2. Fig. 4 is a graph comparing the effects of the above embodiment and the conventional example. An operation frequency A for the above circuit as implemented in CMOS, and an operation frequency B in a case where the above counter circuit is programmed on a PLD formed by CMOS in the conventional example as shown in Fig. 8, are plotted as a function of source voltage. In this embodiment, mutual connections between the input and output signals of the respective F/Fs can be made without passing through the programmable wirings or the programmable combinational logic circuit, which introduce relatively long delay times. As a result, an operation frequency of about 1.5 times that in the conventional example is obtained, as shown in the graph. Incidentally, in the above embodiment, the D-type F/Fs may be replaced with F/Fs of other types and the number of F/Fs is not limited to two. Furthermore, it is clear that the same effects can be achieved regardless of whether the non-inverted output signal or the inverted output signal is used as the output signal of the F/Fs.

Claims: A programmable logic device having a plurality of programmable logic elements (1, 1') capable of forming an optional logic circuit by programming of programmable links (8) connecting input terminals and output terminals of said programmable logic elements to each other, wherein:- said programmable logic elements have a combinational logic circuit (2); a number N of flip-flop circuits (3A, 3B ...) each of which has a selecting means (4A, 4B ...) for switching one of either (i) an output of the said combinational logic circuits (2) or (ii) an output from another programmable logic element (1') or (iii) an output of another flip-flop circuit (3B) of the same programmable logic element (1), to an input terminal of said flip-flop circuit (3A); and said programmable logic elements (1, 1') are provided with output terminals (5) connected to outputs of said combinational logic circuit (2) and output terminals (7) connected to outputs of each of said flip-flops (3A, 3B). The device as set forth in claim 1, wherein said flip-flop circuits (3) are D-type flip-flop circuits. The device as set forth in claim 1 or 2, wherein said combinational logic circuit (2) is a programmable combinational logic array including an AND plane and an OR plane, which has programmable product term lines. The device as set forth in claim 1, 2 or 3, wherein said combinational logic circuit (2) has a memory for storing a logic specification per combination of inputs of input terminals, to thereby obtain a logic output by a table look-up system. The device as set forth in any of claims 2 to 4, wherein said selecting means comprises a selector (4) comprising a plurality of OR-connected n-channel MOS FETs, any one of the MOS FETs being on-controlled programmably, so that an input to said one of the MOS FETs is alternatively selected to be output. The device as set forth in any preceding claim, wherein said combinational logic circuit (2) and at least one flip-flop circuit (3) are used independently of each other. The device as set forth in any preceding claim, wherein some of the input terminals of a preselecting means (4B) of the flip-flop circuit No. 1, where 2 ≦ I ≦ N, are connected to an output terminal of a flip-flop circuit No. I-1. The device as set forth in any preceding claim, wherein an output signal of the flip-flop circuit No. N is further directly connected to input signal selecting means (4A') of the flip-flop circuit No. 1 of another adjoining programmable logic element (1').

Inventors: KEIDA, HISAYA C/O TECHNICAL
Applicants: KAWASAKI STEEL CORPORATION
Application year: 1988
Main classification: H03K19
IPC codes: H03K19