AMPLIFIER ARRANGEMENT

Abstract: The first (T₁) and the second (T₂) output transistor of an amplifier arrangement are push-pull driven by means of a drive circuit (10) having two transistors (T₁₁, T₁₂) which are each loaded by a current source (T₁₃, T₁₄). Currents which are a measure of the currents flowing through the first (T₁) and the second (T₂) output transistor are generated by a first (20) and second (30) current measuring means. These currents are applied to a negative feedback means (40) which controls the current intensity of the current sources (T₁₃, T₁₄) in such a way that the harmonic mean value of the currents flowing through the first (T₁) and the second (T₂) output transistor is substantially equal to a reference value.

Description: The invention relates to an amplifier arrangement comprising a first and a second output transistor each having a first main terminal, a second main terminal and a control terminal, whose main current paths are arranged in series between two power supply terminals and are further coupled to an output connecting a load, drive means for driving the first and the second transistor, said drive means having a first input for applying an input signal, a second input, a first output which is coupled to the control terminal of the first transistor and a second output which is coupled to the control terminal of the second transistor, quiescent current means for causing a quiescent current to flow through the first and the second output transistor, said quiescent current means having first and second current measuring means for generating a first and a second measuring current which are a measure of the current flowing through the first and the second output transistor, respectively, and having feedback means for controlling the quiescent current flowing through the first and the second output transistor by way of the first and the second measuring current. In the description and the appendant Claims the first main terminal, the second main terminal and the control terminal are identical to the drain, the source and the gate, respectively, in the case of unipolar transistors, and to the collector, the emitter and the base, respectively, in the case of bipolar transistors. An amplifier arrangement of this type can be generally used as a power amplifier arrangement and is particularly suitable as an output amplifier in audio circuits. Such an amplifier arrangement is known from European Patent Application EP-A-0,217,431. The first and the second output transistor are push-pull driven by the non-inverting and the inverting output, respectively, of a voltage-to-current converter which has a non-inverting input to which the input voltage is applied and an inverting input which is connected to the output of the amplifier arrangement. The amplifier arrangement is of the class AB type because a given quiescent current flows through the two output transistors. The means for adjusting the value of this quiescent current comprise a measuring circuit for each of the two output transistors for measuring the current through the relevant output transistor. This measuring current is converted across a first diode into a voltage which is applied to the inverting input of an amplifier. A reference voltage generated across a second diode is applied to the non-inverting input thereof. In the absence of an input signal to drive the output transistors, the output of the amplifier controls the relevant output transistor in such a way that the voltage at the inverting input of this amplifier will become equal to the reference voltage. When driving one of the two output transistors, the current through the driven transistor increases and the quiescent current through the non-driven transistor decreases. The known arrangement is, however, adapted in such a way that the non-driven transistor is fully turned off. If the relevant transistor is subsequently driven, it should first be turned on, which causes cross-over distortion. It is therefore an object of the invention to provide an amplifier arrangement having an improved quiescent current control. According to the invention, an amplifier arrangement of a type described in the opening paragraph is characterized in that the feedback means comprise a first differential amplifier having a third and a fourth transistor each having a control terminal, a first main terminal and a second main terminal, the second main terminals being coupled to a common point which is coupled to a first current source, the control terminal of the third transistor being coupled to a first point for conveying a voltage which is proportional to the first measuring current and the control terminal of the fourth transistor being coupled to a second point for conveying a voltage which is proportional to the second measuring current, a reference circuit comprising a second current source and a fifth transistor having a first main terminal, a second main terminal and a control terminal which is coupled to the first main terminal, and a second differential amplifier having a sixth and a seventh transistor each having at least one first main terminal, at least one second main terminal and a control terminal, the control terminal of the sixth transistor being coupled to the second main terminal of the fifth transistor, the control terminal of the seventh transistor being coupled to the common point of the first differential amplifier, and two of the first main terminals of the sixth and the seventh transistor being coupled to the first and the second output of the drive means. The structure of the negative feedback means according to the invention causes the quiescent current through the non-driven output transistor to be controlled to a substantially constant value, which keeps this transistor conducting independent of the extent to which the other output transistor is driven. This prevents the one output transistor from being turned off when the other output transistor is fully turned on. Consequently, the cross-over distortion caused thereby is considerably reduced. The further structure of the negative feedback means is determined by the conductivity type of the first and the second output transistor. If the first and the second output transistor are of the same conductivity type, an embodiment of the amplifier arrangement may be further characterized in that the sixth and the seventh transistor each have two first main terminals, and in that the one first main terminal of the sixth transistor is coupled to the first output of the drive means and the other first main terminal of the sixth transistor is coupled to the second output of the drive means. A further embodiment of such an amplifier arrangement may be characterized in that the first current measuring means include an eighth transistor having a first main terminal, a second main terminal and a control terminal, the control terminal and the second main terminal being coupled to the control terminal and the second main terminal, respectively, of the first output transistor and in that the second current measuring means include a ninth transistor having a first main terminal, a second main terminal and a control terminal, the control terminal and the second main terminal being coupled to the control terminal and the second main terminal, respectively, of the second output transistor. This embodiment may be further characterized in that the second main terminal of the eighth transistor is coupled to the second main terminal of the first output transistor by means of a first resistor and in that the second main terminal of the ninth transistor is coupled to the second main terminal of the second output transistor by means of a second resistor. The first and the second resistor limit the maximum current through the eight and the ninth transistor, which prevents these transistors from damage when the output transistors are fully turned on. Another embodiment of such an amplifier arrangement may be characterized in that the first main terminal of the eighth transistor is coupled to a first power supply terminal by means of a tenth transistor having a first main terminal, a second main terminal and a control terminal, the first main terminal of the tenth transistor being coupled to its control terminal and the second main terminal constituting the first point for conveying a voltage which is proportional to the first measuring current, the first main terminal of the ninth transistor is coupled to the first power supply terminal by means for an eleventh transistor having a first main terminal, a second main terminal and a control terminal, the first main terminal of the eleventh transistor being coupled to its control terminal and the second main terminal constituting the second point for conveying a voltage which is proportional to the second measuring current, and in that the first main terminal of the fifth transistor is coupled to the first power supply terminal by means of a twelfth transistor having a first main terminal and a second main terminal and a control terminal, the first main terminal being coupled to its control terminal. The currents generated by the first and second current measuring means across the tenth and the eleventh transistor are converted into voltages which are proportional thereto and which are applied to the control terminals of the third and the fourth transistor. Yet a further embodiment of such an amplifier arrangement may be characterized in that the drive means include a third differential amplifier having a thirteenth and a fourteenth transistor each having a first main terminal, a second main terminal and a control terminal, the control terminal and the first main terminal of the thirteenth transistor being coupled to the first input and the first output, respectively, of the drive means and the control terminal and the second main terminal of the fourteenth transistor being coupled to the second input and the second output, respectively, of the drive means. This embodiment may be further characterized in that a first capacitor is arranged between the first input and the first output of the drive means and in that the first input of the drive means is coupled to an input of a fifteenth transistor arranged as a voltage follower, an output of which is coupled to the second output of the drive means by means of a second capacitor. The first capacitor ensures a frequency compensation for obtaining a stable gain and the second capacitor ensures a direct signal transmission to the control terminal of the second output transistor in the case of high frequencies. This results in the phase shifting being reduced, thus improving the stability of the amplifier arrangement. Yet another embodiment of such an amplifier arrangement may be characterized in that the first output of the drive means is coupled to a non-inverting input of an amplifier, an inverting input of which is coupled to the output of the amplifier arrangement and an output of which is coupled to the control terminal of the first output transistor. This amplifier constitutes a negative feedback from the output to the control terminal of the first output transistor so that the non-linearities caused by this transistor are reduced. This negative feedback is effective at all drive conditions because it is ensured that the first output transistor remains conducting in the amplifier arrangement according to the invention. In another embodiment this amplifier may be characterized in that it is constituted by a fourth differential amplifier having a sixteenth and a seventeenth transistor each having a control terminal and a first and a second main terminal, the control terminal of the sixteenth transistor being coupled to the non-inverting input and the control terminal of the seventeenth transistor being coupled to the inverting input, the first main terminal of the seventeenth transistor being coupled to the output of the amplifier and to a current source. yet another embodiment may be characterized in that the first output of the drive means is coupled to an input of a voltage follower circuit, an output of which is coupled to the control terminal of the first output transistor by means of a third capacitor. At high frequencies the third capacitor ensures a direct signal transmission from the drive means to the control terminal of the first output transistor and thereby eliminates the phase shift occurring in the amplifier at high frequencies. This improves the stability of the amplifier arrangement. The amplifier arrangement according to the invention may be suitably formed with bipolar transistors. In that case the negative feedback means control the current through the first and the second output transistor in such a way that the harmonic means value of these currents is maintained substantially constant. The amplifier arrangement may, however, also be formed with field-effect transistors. The negative feedback means then control the currents through the first and the second output transistor in such a way that a relationship which complies with the equation for a circle is present between these currents. In an amplifier arrangement according to the invention, the first and the second output transistor may be alternatively of the opposite conductivity type instead of the same conductivity type. The amplifier arrangement may then be further characterized in that the sixth and the seventh transistor each have a first main terminal and in that the first main terminal of the sixth transistor is coupled to the first output of the drive means and the first main terminal of the seventh transistor is coupled to the second output of the drive means. This embodiment is very suitable for low power supply voltages. A further embodiment of such an amplifier arrangement may be characterized in that the first current measuring means include an eighth transistor having a first main terminal, a second main terminal and a control terminal, the control terminal being coupled to the control terminal of the first output transistor and the second main terminal being coupled to the second main terminal of the first output transistor by means of a first resistor, said second main terminal of the eighth transistor constituting the first point for conveying a voltage which is proportional to the first measuring current, the second current measuring means include a ninth transistor having a first main terminal, a second main terminal and a control terminal, the control terminal being coupled to the control terminal of the second output transistor and the second main terminal being coupled to the second main terminal of the second output transistor by means of a second resistor, the first main terminal of the ninth transistor is coupled to a first power supply terminal by means of a third resistor, said first main terminal of the ninth transistor constituting the second point for conveying a voltage which is proportional fo the second measuring current, and in that the first main terminal of the fifth transistor is coupled to the first power supply terminal by means of a fourth resistor. The first measuring current flows through the first resistor and the voltage across this resistor is directly applied to the control terminal of the third transistor. The second measuring current is converted across the third resistor into a voltage which is proportional thereto and which is applied to the control terminal of the fourth transistor. Yet another embodiment of such an amplifier arrangement may be characterized in that the drive means include a third differential amplifier with a tenth transistor having a first main terminal, a second main terminal and a control terminal and an eleventh transistor having two first main terminals, two second main terminals and a control terminal, the control terminal of the tenth transistor being coupled to the first input of the drive means and the control terminal and the two first main terminals being coupled to the second input and the first and the second output, respectively, of the drive means. This embodiment may be further characterized in that a first capacitor is arranged between the first input and the first main terminal of the tenth transistor and in that a second capacitor is arranged between the control terminal of the first output transistor and the output, and in that a third capacitor is arranged between the control terminal of the second output transistor and the output. These capacitors enhance the stability of the amplifier arrangement. This amplifier arrangement may be suitably formed with bipolar transistors. The negative feedback means then control the currents through the first and the second output transistor in such a way that the harmonic mean value of these currents is maintained substantially constant. This amplifier arranged can of course also be formed with field-effect transistors instead of bipolar transistors. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings in which Fig. 1 shows a first embodiment of an amplifier arrangement according to the invention, Fig. 2a shows the relationship between the currents through the output transistors, Fig. 2b shows the waveforms of the currents through the output transistors as a function of the output voltage of the amplifier, Fig. 3 shows a second embodiment of an amplifier arrangement according to the invention, Fig. 4 shows a third embodiment of an amplifier arrangement according to the invention, Fig. 5 shows a fourth embodiment of an amplifier arangement according to the invention, Fig. 6a shows the relationship between the measuring currents in the circuit arrangment of Fig. 5, Fig. 6b shows the waveforms of the quiescent currents as a function of the output voltage for the amplifier arrangement of Fig. 5, Fig. 7 shows a fifth embodiment of an amplifier arrangement according to the invention, and Fig. 8 shows the waveforms of the currents through the output transistors as a function of the output voltage for the amplifier arrangement of Fig. 7. Fig. 1 shows a first embodiment of an amplifier arrangement according to the invention. The arrangement comprises a first output transistor T₁ and a second output transistor T₂ whose collector-emitter paths are arranged in series between a first power supply terminal 1 and a second power supply terminal 2. The emitter of transistor T₁ and the collector of transistor T₂ are connected to an output 3 of the amplifier arrangement to which a load Z₁ is connected. The amplifier arrangement also comprises drive means 10 for push-pull driving of the first and the second output transistor T₁, T₂. The drive means 10 comprise a differential amplifier having two transistors T₁₁ and T₁₂ whose emitters are connected to a common point which is connected to the power supply terminal 2 by means of a current source I₁ = I. The base of transistor T₁₁ is connected to a first input 4 to which an input voltage V in is applied. This signal originates from an input stage which may have a conventional structure such as that of a µA741-input stage. The base of transistor T₁₂ is connected to a second input 5 conveying a reference voltage V ref . The collector of transistor T₁₁ is connected to a first output 6 which is coupled to the base of transistor T₁ and to the collector of transistor T₁₃ constituting a variable current source I₅. Similarly, the collector of transistor T₁₂ is connected to a second output 7 which is coupled to the base of transistor T₂ and is connected to the collector of a transistor T₁₄ constituting a variable current source I₆. The current sources I₅ and I₆ form part of quiescent current means for causing a quiescent current to flow through the output transistors T₁ and T₂ in order to obtain a class AB adjustment of the amplifier arrangement. These quiescent current means have first current measuring means 20 which are constituted by a transistor T₃ whose base-emitter junction is arranged in series with a first resistor R₁ parallel to the base-emitter junction of transistor T₁. The collector current of transistor T₃ is a measure of the collector current of transistor T₁ and is determined by the ratio of the emitter surfaces of the transistors T₁ and T₃ and the resistance of resistor R₁. In order to minimize the dissipation of the arrangement, the emitter surface of transistor T₃ is preferably chosen to be much smaller than that of transistor T₁. The resistor R₁ limits the maximum current through transistor T₃ to a safe value so as to prevent this transistor from being damaged when transistor T₁ is fully turned on. It is to be noted that the resistor R₁ may in principle be dispensed with. The quiescent current means also have second current measuring means 30 which are similarly provided with a transistor T₄ whose base-emitter junction in series with a resistor R₂ is arranged parallel to the base-emitter junction of transistor T₂. The collector current of transistor T₄ is a measure of the current flowing through transistor T₂. The quiescent current means also comprise negative feedback means 40 which keep the harmonic mean value of the measuring currents supplied by the first and second measuring means 20 and 30 and hence the currents through the first and the second output transistor T₁ and T₂ substantially equal to a reference value. The negative feedback means 40 comprise a first differential amplifier having two transistors T₅ and T₆ whose emitters are connected to a common point 8 which is connected to the second power supply terminal 2 by means of a current source I₂ = 2I₀. The base 11 of transistor T₅ is connected to the first power supply terminal via a transistor T₇ arranged as a diode and to the collector of transistor T₃. Similarly, the base 12 of transistor T₆ is connected to the first power supply terminal 1 via a transistor T₈ arranged as a diode and to the collector of transistor T₄. The negative feedback means 40 also comprise a reference circuit which is constituted by a current source I₃ = I₀ whose output 9 is connected to the first power supply terminal 1 via two series-arranged transistors T₉ and T₁₀ arranged as diodes. The negative feedback means 40 also comprise a second differential amplifier having two transistors T₁₃ and T₁₄ whose base-emitter junctions are arranged in parallel and two transistors T₁₅ and T₁₆ whose base-emitter junctions are also arranged in parallel. The emitters of the transistors T₁₃-T₁₆ are connected to a common point which is connected to the positive power supply terminal 1 by means of a current source I₄= 2I. The common base of the transistors T₁₅ and T₁₆ is connected to the point 8 of the differential amplifier T₅, T₆. The collectors of the transistors T₁₅ and T₁₆ are connected to the second power supply terminal 2. The common base of the transistors T₁₃ and T₁₄ is connected to the output 9 of current source I₃. The collector of transistor T₁₃ is connected to the first output 6 and the collector of transistor T₁₄ is connected to the second output 7 of the drive means 10. Transistor T₁₃ constitutes a variable current source I₅ and transistor T₁₄ constitutes a variable current source I₆. It is to be noted that the transistors T₁₃ and T₁₄ as well as the transistors T₁₅ and T₁₆ may be replaced by one single transistor having a double collector. The operation of the arrangement may be explained as follows. The class AB adjustment affects the bases of the output transistors T₁ and T₂ as a common mode signal, whilst the signal to be amplified affects the bases of these transistors as a difference mode signal. In the means 40 a first translinear loop can be distinguished which is constituted by the transistors T₅-T₈. The following relation holds for this loop: V BET7 +V BET5 =V BET8 +V BET6 (1) in which V BE is the base-emitter voltage of the relevant transistor. By means of the known exponential relation between the base-emitter voltage and the collector current of a transistor and the assumption that the transistors T₅-T₈ have identical emitter surfaces, this equation results in : I S1 .I₀(1+a) = I S2 . I₀(1-a) (2) in which I S1 = the first measuring current flowing through transistor T₇ and being supplied by the first measuring means 20, I₂ = the second measuring current flowing through transistor T₈ and being supplied by the second measuring means 30 and aI₀ = the signal current through the transistors T₅ and T₆ determined by a difference in the first and the second measuring current I S1 and I S2 . It follows from this equation that In the means 40 a second translinear loop may also be distinguished which is constituted by the transistors T₈, T₆, T₁₆, T₁₃, T₁₀ and T₉. The following equation holds for this loop: V BET8 +V BET6 +V BET13 =V BET9 +V BET10 +V BET16 (4) By means of the known exponential transistor equation and again assuming that the transistors have identical emitter urfaces, this equation results in in which ZI = the signal current through the transistors T₁₃ and T₁₆ determined by a voltage difference between the bases 8 and 9. It follows that Filling in equation 3, this results in or The collector current of transistor T₁₃ is equal to Since transistor T₁₄ is arranged in parallel ith transistor T₁₃, the collector current of transistor T₁₄ is also equal to In the absence of an input voltage V in at the input 4 of the drive means 10 the current I of current source I₁ will be evenly distributed over the transistors T₁₁ and T₁₂ so that a direct current I / 2 flows through each of these transistors. These direct currents are compensated by the direct currents I / 2 which flow through the transistors T₁₃ and T₁₄. Consequently, a current ZI / 2 flows via output 6 to the base of transistor T₁ and an equally large current ZI / 2 flows via output 7 to the base of transistor T₂. A quiescent current resulting in a first and an equal second measuring current I S1 and I S2 will therefore flow through transistors T₁ and T₂. The transistors T₁ and T₂ are now driven in such a way that the voltage at the point 8 determined by these measuring currents is equal to the reference voltage at the point 9. For the value of the quiescent current flowing through transistors T₁ and T₂ the following applies. The current gain factors of the transistors T₁ and T₂ are very large. This means that the base currents ZI / 2 are very small and may be assumed to be approximately zero. With I S1 = I S2 it follws from equation 7 or 8 for the measuring currents flowing in the absence of an input voltage V₁ that: I S1 = I S2 = I₀ (9) For relatively small currents the voltage across the resistors R₁ and R₂ is small with respect to the base-emitter voltages of the transistors T₃ and T₄. For a ratio of base-emitter surfaces of the transistors T₁, T₃ and T₂, T₄ which is equal to N it holds for the value of the quiescent currents flowing through the transistors T₁ and T₂ that; I₁ = I₂ = N I₀ (10) In the case of an input voltage V in at the input 4 which is, for example, smaller than the reference voltage V ref at the input 5, the current through transistor T₁₂ increases and the current through transistor T₁₁ decreases. Consequently, the base current of transistor T₁ increases and that of transistor T₂ decreases so that transistor T₁ is further turned on and transistor T₂ is further turned off. As a result, the measuring current I S1 through transistor T₃ increases and the measuring current I S2 through transistor T₄ decreases. Consequently, the voltage across the base-emitter junction of transistor T₇ increases and the voltage across the base-emitter junction of transistor T₈ decreases. At already relatively small currents transistor T₅ will therefore be turned off so that transistor T₆ will start behaving as an emitter follower. The voltage at the common point 8 thus increases so that transistors T₁₅ and T₁₆ will convey less current and transistors T₁₃ and T₁₄ will convey more current. The base current of both transistor T₁ and of transistor T₂ consequently increases. In this way the measuring current I S2 and consequently the quiescent current through transistor T₂ is controlled to a well-defined residual value independent of the extent to which transistor T₁ is turned on. When driving transistor T₂, the quiescent current through transistor T₁ is similarly controlled to the same residual value. When ignoring the base currents of the transistors T₁ and T₂ it follows from equation 7 that the currents I₁ and I₂ are determined by the following equation: It is apparent from the equation above that the circuit 40 controls the harmonic mean value of the currents through the transistors T₁ and T₂ to a value which is equal to a reference value. In Fig. 2a the relationship between the currents I₁ and I₂ determined by means of equation 11 is shown graphically. Fig. 2b shows the waveforms of the currents I₁ and I₂ through the transistors T₁ and T₂ as a function of the voltage V out at the output 3 of the amplifier arrangement. For the sake of comparison the waveforms of these currents in the known circuit arrangement are shown in broken lines in this Figure. As is apparent from this Figure, the residual current of the non-driven output transistor is each time controlled to a constant value. It follows from equation 11 that this residual current is given by: In this embodiment the residual current is thus equal to half the quiescent current in the absence of an input signal. Due to this residual current the non-driven transistor is each time partly turned on and is prevented from being turned off. Consequently, the cross-over distortion is reduced. Since the base-emitter voltage variations of the output transistors are small, the distortion caused thereby is also small. Since the first output transistor T₁ is always turned on, the variation of the output impedance of this transistor and hence of the total amplifier arrangement is small so that the distortion of the output signal caused thereby is also small. Moreover, the dissipation in the non-driven output transistor is substantially constant because the residual current flowing therethrough is accurately fixed and is substantially constant. It is to be noted that the harmonic mean value of the currents through the output transistors and hence the residual current can be controlled to a different value in the case of a different choice of the ratio of the emitter surfaces and/or bias currents. Furthermore, the factor 1/2 in equation (12) can be modified by giving the transistors in the described translinear loops different emitter surfaces. Fig. 3 shows a second embodiment of an amplifier arrangement according to the invention in which the same components have the same reference numerals as in Fig. 1. The output transistor T₁ is arranged in a Darlington configuration with a transistor T₂₀, whilst the collector is connected to the collector of transistor T₁ and the emitter is connected to the base of transistor T₁ and to the second power supply terminal 2 by means of a current source I₇. The base of transistor T₂₀ is connected to the first output 6 of the drive means 10. Similarly, transistor T₂ is arranged in a Darlington configuration with a transistor T₂₂, whilst the emitter of transistor T₂₂ is connected to the second power supply terminal 2 by means of a current source I₉. The base of transistor T₂₂ is driven by a voltage follower with a transistor T₂₃ and a current source I₁₀. The base of transistor T₂₃ is connected to the second output 7 of the drive means 10. The Darlington configurations T₁, T₂₀ and T₂, T₂₂ ensure a very large current gain and consequently very small base currents in the transistors T₂₀ and T₂₃. In the embodiment of Fig. 3 the first output 6 of the drive means is connected to the non-inverting input of an amplifier 50 whose inverting output is connected to the output 3 of the amplifier arrangement. The output of the amplifier 50 is connected to the base of transistor T₂₀. The amplifier 50 ensures a negative feedback around the Darlington configuration T₁, T₂₀. This results in the distortion of the output voltage due to non-linearities of the output transistor T₁ being eliminated, so that the voltage V₀ at the output 3 accurately follows the voltage at the output 6 of the drive means 10. Since transistor T₁ is always turned on as a result of the quiescent current control according to the invention, it is ensured that this negative feedback continues to function correctly under all circumstances. Fig. 4 shows a third embodiment of an amplifier arrangement according to the invention in which the same components have the same reference numerals as in Fig. 3. A frequency compensation capacitor C₁ which, as is known, stabilizes the gain if the amplifier arrangement is driven by a conventional input amplifier, is arranged between the input 4 of the amplifier arrangement and the first output 6 of the drive means 10. The input 4 is also connected to the base of a transistor T₃₀ whose collector is connected to the power supply terminal 1 and whose emitter is connected to the power supply terminal 2 by means of a current source I₁₁ and to the second output 7 of the drive means 10 by means of a capacitor C₂. The capacitor C₂ ensures that the input voltage V in is directly applied to the base of transistor T₂₃ via voltage-follower transistor T₃₀ in the case of high frequencies. This enhances the phase margin and hence the stability of the amplifier arrangement. The capacitors C₁ and C₂ also stabilize the control loop which controls the quiescent current because they provide a dominant-pole in this loop. In this embodiment the amplifier 50 is constituted by a differential amplifier having two transistors T₄₀, T₄₁ whose emitters are connected to a common point which is connected to the power supply terminal 2 via a current source I₁₂. The base of transistor T₄₀ is connected to the first output 6 of the drive means 10 and the base of the transistor T₄₁ is connected to the output 3 of the amplifier arrangement. The collector of transistor T₄₀ is directly connected to the power supply terminal 1 and the collector of transistor T₄₁ is connected to the positive power supply terminal 1 by means of a current source I₁₃ and to an output 15 of the amplifier 30. This output 15 is connected to the base of transistor T₂₀. The first output 6 of the drive means 10 is also connected to the base of a transistor T₄₂ whose collector is connected to the first power supply terminal 1 and whose emitter is connected to the second power supply terminal 2 by means of a current source I₈ and to the output 15 of amplifier 30 by means of a capacitor C₃. In the region where amplifier 50 exhibits a large phase shift, capacitor C₃ ensures that the signal at the first output 6 is directly applied to the base of transistor T₂₀. A first diode D₁ is arranged between the base and the emitter of transistor T₄₀ and a second diode D₂ is arranged parallel to capacitor C₃. These diodes prevent the amplifier T₄₀, T₄₁ from being overdriven in the case of fast, step-wise signals (transients). Fig. 5 shows a fourth embodiment of an amplifier arrangement according to the invention in which the same components have the same reference numerals as in Fig. 1. The arrangement now comprises MOS field-effect transistors instead of bipolar transistors. In the negative feedback means 40 two translinear loops can be distinguished again. For the first loop with transistors T₅ - T₁₀ the following equation holds: V GST7 + V GST5 = V GST6 + V GST8 (13) in which V GS is the gate-source voltage of the relevant transistor. For the second loop with transistors T₈, T₆, T₁₆, T₁₃, T₁₀ and T₉ the following equation holds: V GST8 +V GST6 +V GST13 = V GST9 +V GST10 +V GST16 (14) Due to the strong negative feedback in the negative feedback loop it can be assumed that the second differential amplifier T₁₃-T₁₆ is always balanced, so that it holds that: V GST13 = V GST14 = V GST15 = V GST16 (14A) For the second translinear loop it thus holds that: V GST9 +V GST10 = V GST6 +V GST8 (15) For identical transistors and using the quadratic relationship between the drain source current I D and the gate source voltage V GS of a MOS transistor: I D = 1/2β(V GS -V T )² (16) in which β = a geometry factor and V T = the threshold voltage of the transistor, equations (13) and (15) can be written as follows 2√ I₀ = √ I S1 +√ I₀(1+a) = √ I S2 +√ I₀(1-a) (17) in which I₀(1+a) = the current through transistor T₅ and I₀(1-a) = the current through transistor T₆. Equation (17) can be rewritten as I₀(1+a) = (2√ I₀ - √ I S1 )² (18) I₀(1-a) = (2√ I₀ - √ I S2 )² (19) By addition of these equations and rewriting, it holds for the relationship between the measuring currents I S1 and I S2 that: (√ I S1 - 2√ I₀ )²+(√ I S2 - 2√ I₀ )²=2I₀ (20) This equation describes a locus of a circle a quarter of which is valid. Fig. 6a shows this relationship between the measuring currents I S1 and I S2 . With I S1 = I S2 it follows from equation 20 for the measuring currents flowing in the absence of an input voltage that: I S1 = I S2 = I₀ (21) For relatively small currents the voltage across resistors R₁ and R₂ is small with respect to the gate-source voltage of the transistors T₃ and T₄. In the case of a ratio of the length-width ratio of the transistors T₁ and T₃ and of the transistors T₂ and T₄ equal to N it holds for the quiescent currents flowing through transistors T₁ and T₂ that I₁ = I₂ = N I₀ (22) It follows from equation (20) that when driving, for example, transistor T₁ the quiescent current through transistor T₂ is controlled to a residual value which is given by I r = N I S2rest = N(2-√ 2 )²I₀≈0.35 N I₀ (23) When driving transistor T₁, the quiescent current through transistor T₂ is controlled in the same manner to the same residual value. The waveforms of the quiescent currents through the output transistors as a function of the output voltage of the amplifier is shown diagrammatically in Fig. 6b. The residual current in this embodiment is thus approximately equal to 0.35 times the quiescent current in the absence of an input signal. In the same way as in the bipolar embodiment, this prevents the non-driven output transistor from being turned off and thereby causing distortion. Fig. 7 shows a fifth embodiment of an amplifier arrangement according to the invention. Unlike the previous embodiments, the arrangement comprises output transistors of the opposite conductivity type instead of the same type. The arrangement comprises a PNP output transistor T₁ and an NPN output transistor T₂ whose collector-emitter paths are arranged in series between a first power supply terminal 1 and a second power supply terminal 2. The collectors of transistor T₁ and of transistor T₂ are connected to the output 3 of the amplifier arrangement. The transistors T₁ and T₂ are driven in phase by drive means 10. These means are provided with a differential amplifier having a transistor T₁₁ and two transistors T₁₂ and T₁₃ whose base-emitter junctions are arranged in parallel and whose emitters are connected to a common point which is connected to power supply terminal 2 by means of a current source I₁ = I. The base of transistor T₁ is connected to the input 5 to which an input voltage is applied which may originate from an input stage of the conventional type. The common base of the transistors T₁₂ and T₁₃ is connected to a second input 5 which conveys a reference voltage V ref . The collector of transistor T₁₂ is connected to a first output 6 of the drive means to which the base of transistor T₁ is connected and the collector of transistor T₁₃ is connected to a second output 7 to which the base of transistor T₂ is connected. The amplifier arrangement is provided with quiescent current means for controlling the quiescent currents through the transistors T₁ and T₂. These means comprise first current measuring means 20 which are constituted by a PNP transistor T₃ whose base-emitter junction in series with a resistor R₁ = R is arranged parallel to the base-emitter junction of transistor T₁. The current through transistor T₃ and resistor R₁ is a measure of the current through transistor T₁. To minimize the dissipation, the emitter surface of transistor T₃ is chosen to be much smaller than that of transistor T₁. The resistor R₁ also limits the maximum value of the current through transistor T₃ to prevent damage when transistor T₁ is fully turned on. The quiescent current means further comprise second current measuring means having a transistor T₄ whose base-emitter junction in series with a resistor R₂ = R is arranged parallel to the base-emitter junction of transistor T₂. The collector current of transistor T₄ is a measure of the current flowing through transistor T₂. This current is converted across a resistor R₃ = R into a voltage which is proportional thereto. The quiescent current means also comprise negative feedback means 40 which are provided with a first differential amplifier having two transistors T₅ and T₆ whose emitters are connected to a common point 8 which is connected to the second power supply terminal 2 by means of a current source I₂ = I₀. The base 11 of transistor T₅ is connected to the emitter of transistor T₃ and the base 12 of transistor T₆ is connected to the collector of transistor T₄. The negative feedback means also comprise a reference circuit which is constituted by the series arrangement of a transistor T₁₀ arranged as a diode and a resistor R₄ = R to which a current source I₃ = I₀ is connected. The negative feedback means 40 also comprise a second differential amplifier having two transistors T₁₅ and T₁₆ whose emitters are connected to a common point which is connected to the positive power supply terminal 2 by means of a current source I₄ =2I. The base of transistor T₁₅ is connected to the common point 8 of the differential amplifier T₅, T₆ and the base of the transistor T₁₆ is connected to the emitter of transistor T₁₀. The operation of the arrangement may be explained as follows. Two loops can be distinguished in the means 40. For the loop with resistors R₁, R₄ and transistors T₅, T₁₀, T₁₅ and T₁₆ and for the loop with resistors R₃, R₄, T₆, T₁₀, T₁₅ and T₁₆ the following equations hold, assuming that the differential amplifier T₁₅, T₁₆ will be balanced due to the negative feedback: I S1 .R + V BET5 = I₀.R + V BET10 (24) I S2 .R + V BET6 = I₀.R + V BET10 (25) in which I S1 = the current through resistor R₁ and I S2 = the current through resistor R₃. The relationship between the currents I₁ and I₂ through transistors T₁ and T₂ and the measuring currents I S1 and I S2 is given by and With the known relationship between the base-emitter voltage and the collector current of a transistor the following can be written for the equations 24 and 25 With these equations the following relations can be obtained by means of solution for the currents through transistors T₅ and T₆ en Furthermore it holds that I T5 +I T6 = I₀ (32) If equation (32) is combined with equations (30) and (31) the equation indicating the relationship between the measuring currents I S1 and I S2 is obtained: By filling in the equations (26) and (27) in this equation, the relationship between the output currents I₁ and I₂ is obtained. However, this equation does not give a simple analytic relationship. The waveform of the output currents as a function of the output voltage V₀ of the amplifier arrangement is shown in Fig. 8. In the absence of an input voltage the quiescent currents of transistors T₁ and T₂ will be equally large, so that it also holds that I S1 = I S2 . It follows from equation (32) that: I S1 =I S2 = I₀+V T /R . ln 2 (33) With the aid of equation (26) or (27) it follws for the value of the quiescent current of transistors T₁ and T₂ that: For calculating the residual current of an output transistor when the other output transistor is driven, the measuring current of the driven output transistor, for example, I S2 is assumed to be very large in equation (32). It follows for the measuring current that I S1 = I (35) With equation (26) it follows for the residual current through output transistor T₁ that If equation (36) is compared with equation (34), it appears that the residual current is substantially twice as large as the quiescent current in the absence of an input voltage if it holds that I₀R > V T . The control behaviour of the arrangement is then substantially equal to that of the arrangement of Fig. 1. In the arrangement of Fig. 7 a capacitor C₁ is arranged between the base and the collector of transistor T₁, a capacitor C₂ is arranged between the base and the collector of transistor T₂ and a capacitor C₃ is arranged between the base and the collector of transistor T₁. These capacitors fulfill the same functions as the capacitors C₁, C₂ and C₃ in the embodiment of Fig. 4. Also in this embodiment the quiescent current of the non-driven output transistor is controlled to a constant residual value, thus preventing the occurrence of harmonic distortion. It is evident that the arrangement of Fig. 7 may also comprise field-effect transistors instead of bipolar transistors. The invention is not limited to the embodiments shown. The first and the second current measuring means may be constituted in any other way, provided that they generate a current which is a measure of the current flowing through the first and the second output transistor. The drive means may also be constituted in any other way, provided that they drive the first and the second output transistor in the push-pull mode. The embodiments of the amplifier arrangement according to the invention are either completely built up with bipolar transistors or they are completely built up with unipolar transistors. It is of course also possible to build up the amplifier arrangement with both unipolar and bipolar transistors.

Claims: An amplifier arrangement comprising a first (T1) and second (T2) output transistor each having a first main terminal, a second main terminal and a control terminal, whose main current paths are arranged in series between two power supply terminals (1, 2) and are further coupled to an output (3) for connecting a load (ZL), drive means (10) for driving the first and the second transistor, said drive means having a first input (4) for applying an input signal, a second input (5), a first output (6) which is coupled to the control terminal of the first transistor and a second output (7) which is coupled to the control terminal of the second transistor, quiescent current means (20, 30) for causing a quiescent current to flow through the first and the second output transistor, said quiescent current means having first and second current measuring means for generating a first (IS1) and a second (IS2) measuring current which are a measure of the current flowing through the first and the second output transistor, respectively, and having feedback means (40) for controlling the quiescent current flowing through the first and the second output transistor by way of the first and the second measuring current, characterized in that the feedback means comprise a first differential amplifier having a third (T5) and a fourth (T6) transistor each having a control terminal, a first main terminal and a second main terminal, the second main terminals being coupled to a common point (8) which is coupled to a first current source (I2), the control terminal of the third transistor being coupled to a first point (11) for conveying a voltage which is proportional to the first measuring current and the control terminal of the fourth transistor being coupled to a second point (12) for conveying a voltage which is proportional to the second measuring current, a reference circuit comprising a second current source (I3) and a fifth transistor (T10) having a first main terminal, a second main terminal and a control terminal which is coupled to the first main terminal, and a second differential amplifier having a sixth (T13, T14) and a seventh (T15, T16) transistor each having at least one first main terminal, at least one second main terminal and a control terminal, the control terminal of the sixth transistor being coupled to the second main terminal of the fifth transistor, the control terminal of the seventh transistor being coupled to the common point (8) of the first differential amplifier, and two of the first main terminals of the sixth and the seventh transistor being coupled to the first and the second output of the drive means. An amplifier arrangement as claimed in Claim 1, characterized in that the first (T1) and the second (T2) output transistor are of the same conductivity type, the sixth (T13, T14) and the seventh (T15, T16) transistor each have two first main terminals, and in that the one first main terminal of the sixth transistor is coupled to the first output (6) of the drive means and the other first main terminal of the sixth transistor is coupled to the second output (7) of the drive means. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the first current measuring means include an eighth transistor (T3) having a first main terminal, a second main terminal and a control terminal, the control terminal and the second main terminal being coupled to the control terminal and the second main terminal, respectively, of the first output transistor and in that the second current measuring means include a ninth transistor (T4) having a first main terminal, a second main terminal and a control terminal, the control terminal and the second main terminal being coupled to the control terminal and the second main terminal, respectively, of the second output transistor. An amplifier arrangement as claimed in Claim 3, characterized in that the second main terminal of the eighth transistor (T3) is coupled to the second main terminal of the first output transistor by means of a first resistor (R1) and in that the second main terminal of the ninth (T4) transistor is coupled to the second main terminal of the second output transistor by means of a second resistor (R2). An amplifier arrangement as claimed in Claim 3 or 4, characterized in that the first main terminal of the eighth transistor is coupled to a first power supply terminal by means of a tenth transistor (T7) having a first main terminal, a second main terminal and a control terminal, the first main terminal of the tenth transistor being coupled to its control terminal and the second main terminal constituting the first point (11) for conveying a voltage which is proportional to the first measuring current, the first main terminal of the ninth transistor is coupled to the first power supply terminal by means of an eleventh transistor (T8) having a first main terminal, a second main terminal and a control terminal, the first main terminal of the eleventh transistor being coupled to its control terminal and the second main terminal constituting the second point (12) for conveying a voltage which is proportional to the second measuring current, and in that the first main terminal of the fifth transistor (T10) is coupled to the first power supply terminal by means of a twelfth (T9) transistor having a first main terminal and a second main terminal and a control terminal, the first main terminal being coupled to its control terminal. An amplifier arrangement as claimed in Claim 1, 2, 3, 4 or 5, characterized in that the drive means include a third differential amplifier having a thirteenth (T11) and a fourteenth transistor (T12) each having a first main terminal, a second main terminal and a control terminal, the control terminal and the first main terminal of the thirteenth transistor being coupled to the first input (4) and the first output (6) respectively, of the drive means and the control terminal and the first main terminal of the fourteenth transistor being coupled to the second input (5) and the second output (7), respectively, of the drive means. An amplifier arrangement as claimed in Claim 6, characterized in that a first capacitor (C1) is arranged between the first input (4) and the first output (6) of the drive means. An amplifier arrangement as claimed in Claim 6 or 7, characterized in that the first input (6) of the drive means is coupled to an input of a fifteenth transistor (T30) arranged as a voltage follower, an output of which is coupled to the second output (7) of the drive means by means of a second capacitor (C2). An amplifier arrangement as claimed in any one of Claims 2 to 8, characterized in that the first output of the drive means is coupled to a non-inverting input of an amplifier (50), an inverting input of which is coupled to the output of the amplifier arrangement and an output of which is coupled to the control terminal of the first output transistor. An amplifier arrangement as claimed in Claim 9, characterized in that the amplifier is constituted by a fourth differential amplifier having a sixteenth (T40) and a seventeenth (T41) transistor each having a control terminal and a first and a second main terminal, the control terminal of the sixteenth transistor being coupled to the non-inverting input and the control terminal of the seventeenth transistor being coupled to the inverting input, the first main terminal of the seventeenth transistor being coupled to the output of the amplifier and to a current source (I13). An amplifier arrangement as claimed in Claim 9 or 10, characterized in that the first output of the drive means (6) is coupled to an input of a voltage-follower circuit (T42), an output of which is coupled to the control terminal of the first output transistor by means of a third capacitor (C3). An amplifier arrangement as claimed in Claim 11, characterized in that a first diode (D2) is arranged in parallel with the third capacitor (C3) and in that a second diode (D1) is arranged between the second main terminal and the control terminal of the sixteenth transistor (T40). An amplifier arrangement as claimed in any one of the preceding Claims 2 to 12, characterized in that the transistors are bipolar transistors. An amplifier arrangement as claimed in any one of the preceding Claims 2 to 12, characterized in that the transistors are field-effect transistors. An amplifier arrangement as claimed in Claim 1, characterized in that the first (T1) and the second (T2) output transistor are of the opposite conductivity type, the sixth and the seventh transistor each have a first main terminal and in that the first main terminal of the sixth transistor is coupled to the first output (6) of the drive means and the first main terminal of the seventh transistor is coupled to the second output (7) of the drive means. An amplifier arrangement as claimed in Claim 15, characterized in that the first current measuring means include an eighth transistor (T3) having a first main terminal, a second main terminal and a control terminal, the control terminal being coupled to the control terminal of the first output transistor and the second main terminal being coupled to the second main terminal of the first output transistor by means of a first resistor (R1), said second main terminal of the eighth transistor constituting the first point for conveying a voltage which is proportional to the first measuring current, the second current measuring means include a ninth transistor (T4) having a first main terminal, a second main terminal and a control terminal, the control terminal being coupled to the control terminal of the second output transistor and the second main terminal being coupled to the second main terminal of the second output transistor by means of a second resistor (R2), the first main terminal of the ninth transistor is coupled to a first power supply terminal by means of a third resistor (R3), said first main terminal of the ninth transistor constituting the second point for conveying a voltage which is proportional to the second measuring current, and in that the first main terminal of the fifth transistor is coupled to the first power supply terminal by means of a fourth resistor. An amplifier arrangement as claimed in Claim 1, 15 or 16, characterized in that the drive means include a third differential amplifier with a tenth transistor (T11) having a first main terminal, a second main terminal and a control terminal and an eleventh transistor (T12, T13) having two first main terminals, two second main terminals and a control terminal, the control terminal of the tenth transistor being coupled to the first input of the drive means and the control terminal and the two first main terminals of the eleventh transistor being coupled to the second input and the first and the second output, respectively, of the drive means. An amplifier arrangement as claimed in Claim 17, characterized in that a first capacitor (C1) is arranged between the first input and the first main terminal of the tenth transistor. An amplifier arrangement as claimed in Claim 16, 17 or 18, characterized in that a second capacitor (C3) is arranged between the control terminal of the first output transistor and the output, and in that a third capacitor (C2) is arranged between the control terminal of the second output transistor and the output. An amplifier arrangement as claimed in anyone of the preceding Claims 15 to 19, characterized in that the transistors are bipolar transistors.

Inventors: BUITENDIJK, PIETER, DE JAGER, WILLEM, SEEVINCK, EVERT
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1988
Main classification: H03F3
IPC codes: H03F3, H03F1