Instruction decoder

Abstract: An instruction decoder for a variable byte processor, capable of making the variable byte processor operate at a high processing speed and high byte efficiency. The instruction decoder comprises: an instruction register which stores instrucitons applied to the internal data bus, a first instruciton decoding unit which provides a consecutive instruction execution mode signal specifying the repetitive execution of the instruction read from the instruction register for different operands stored at different addresses, a consecutive instruction execution cycle monitoring unit which counts the number of execution cycles of the instruction and provides a signal indicating the completion of the repetitive execution of the instruction, register/counters which count the number of execution cycles and provide operands of different addresses every time an execution cycle is completed, a second instruction decoding unit which sequentially specifies data stored at different operand addresses in response to the output signals of the register/counters, and a gate which inhibits the instruction register from reading a new instruction until the instruction is repeated by the specified number of execution cycles.

Description: The present invention relates to an instruction decoder for a processor for executing an instruction repetitively on a variable number of operand bytes, more particularly, to an instruction decoder for a processor for which an instruction contains the first byte representing an operation code, and the second and subsequent bytes represent operand addresses. In a conventional central processing unit (hereinafter abbreviated to "CPU"), an instruction which contains the first byte representing an operation code, and second and subsequent bytes representing operand addresses, is read into and decoded sequentially by an instruction decoder to execute a program operation. Intel's CPU 8051 uses, for example, an instruction "ADDC A, data address", in which "ADDC" (addition with carry) is an operation code, "A" is an operand address, and "data address" is another operand address. In this instruction, "A" is a fixed operand address exclusively specifying an accumulator, while "data address" is variable and specifies internal random access memories (RAMs) or a plurality of special registers. In such a conventional CPU, since one of the operand addresses, for example, the operand address "A", is fixed, a plurality of instructions are provided in combination to operate in accordance with a plurality of bytes. Accordingly, a long program including many steps is necessary and results in a long processing time. Also, the many instructions for the byte processing occupy many addresses in the read-only memory, thus degrading byte efficiency. It is known from DE-A-1 449 540 to provide an instruction decoder capable of performing sequential arithmetic operations for individual instruction words, comprising an instruction register for reading instructions, a data readout access control stage which reads an instruction from said instruction register to control the general operation of the processor and providing a consecutive execution mode signal upon the reception of a consecutive execution instruction specifying the repetition of the same instruction for operands stored at different operand addresses; an end check stage which is set to a set value indicating the number of consecutive instruction execution cycles when the consecutive execution mode signal is provided, counts the number of execution cycles and provides a count completion signal upon correspondence of the count of the execution cycles with the set value, the end check stage responding to completion of each execution cycle of the instruction to provide different addresses for data to be processed for successive execution cycles, respectively, and an address modification control stage which receives the outputs of end check stage means and addresses data at different operand addresses sequentially. The end check stage furthermore inhibits said instruction register from reading a new instruction during a period from when said consecutive execution mode signal is provided to when the count completion signal is provided. It is an object of the present invention to provide an improved instruction decoder which results in more efficient data processing wherein multiple bytes are utilised to generate respective sequential address. The present invention is characterised by control means operative to apply sequentially the values held in first and second address registers to an operand access control unit, and temporarily holding the value from one of said address registers whilst the value from the other thereof is applied to the operand access control unit. The above and other objects, features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein Fig. 1 is a block diagram of a CPU incorporating an instruction decoder according to the present invention; Fig. 2 is a block diagram of an instruction decoding and control included in the CPU of Fig. 1. Fig. 3 is an illustration of the data arrangement of an internal data memory (RAM) and a special register included in the CPU of Fig. 1; and Fig. 4 is a time chart explaining the operation of the CPU of Fig. 1. Referring to Fig. 1 showing a microprocessor (CPU) incorporating an instruction decoder according to the present invention having an improved PLA, a timing interface signal generating unit 1 generates basic timing signals for controlling various timing operations of the microprocessor, and interface signals for controlling the data communication between the microprocessor and the peripheral equipments. An inverter oscillator 2 generates clock signals to the unit 1. A program counter 3 specifies a program instruction and immediate data. An internal program data memory (ROM) 4 stores program instructions and immediate data. Temporary registers 20 and 21 store data temporarily during the execution of an instruction. A decoder 22 necessary for implementing instructions generates constants on the basis of program data. An arithmetic and logic unit (hereinafter abbreviated to "ALU") 23 processes addition (ADD), inclusive OR (OR), exclusive OR (EOR) and/or logical multiply (ADD) operations of the contents in the temprorary registers 20 and 21. A register 24 stores flags processed by the ALU 23. An internal data memory (RAM) 31 stores processed data. A register 30 stores the specified address data of the internal data memory 31. A working register 32 stores data temporarily during the implementation of an instruction. A special register group 40 has many functions and include indirect registers, data memories (RAMs), I/O ports, timer counters, timer counter control registers, interruption control registers and interruption flags. I/O ports 50 and 51 are used for sending out processed data, receiving data from external equipment, and sending out the output of the program counter for specifying an external program data and receiving external program data in an external ROM mode. I/O ports 52 to 55 are used for sending out processed data and receiving external data. Data processed in the CPU is transmitted through internal buses. Fig. 2 shows an instruction decoding and control unit 70 which generates control signals for controlling the general operation of the CPU. The control signals includes signals for controlling the internal data memory (RAM) and the special register 40 (@ARO, I/O, SMOD). A consecutive instruction execution cycle monitoring unit 100 counts and controls the number of instruction execution cycles in a consecutive execution mode. A register 101 stores consecutive execution frequency setting data applied to a data bus 700, when a gate 102 provides an output signal 103. A gate 106 gives the consecutive execution frequency setting data stored in the register 101 to the data bus 700, when a gate 104 provides an output signal 105. A flip-flop 109 receives a signal 108 from a gate 107 at the trailing edge of a clock signal to provide a write signal B to a register/counter 110. Upon the reception of the write signal B, the register counter 110 stores the consecutive execution number setting data in the register 101. The register counter 110 counts down the number of cycles of consecutive execution when a gate 112 provides a signal C. A gate 111 for detecting the completion of the consecutive execution provides a count completion signal A, when the contents of the counter110 becomes 00H. The count completion signal A is applied as a selection signal to gates 107, 112, 113, 202 and 310. A flip-flop 116, when a MEND S6 signal is applied thereto, receives a signal 114 from a gate 113 and then gives a write control signal D to registers 401 and 404. An instruction decoding unit 200 decodes an instruction code and provides signals to control the general operation of the CPU. An instruction register 201 stores program instruction data. When a gate 202 provides an output signal 203, the instruction register 201 reads in and stores instruction data applied to the data bus 700. A first PLA 205 decodes the contents of the instruction register 201 and generates a control signal for controlling the general operation of the CPU through an AND operation using a timing signal 204. A register unit 300 stores data for specifying operand addresses, namely, the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). The register unit 300 specifies the internal data memory and the special register by instruction mnemonics. A register 301 stores data applied to the data bus 700 for specifying the internal data memory (RAM) and the special register(@ARO, I/O, SMOD) when a gate 302 provides a signal 303. A gate 307 applies the data for specifying the internal data memory (RAM) and the special registers (@ARO, I/O, SMOD) stored in the register 301 to the data bus 700 when a gate 304 provides an output signal 305. A register/counter 306 stores the data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD) stored in the register 301, when an instruction mnemonic mode is selected and a gate 310 provides an output signal 311. The register/counter 306 carries out its incrementing operation every time a signal C is provided. The data in the register/counter 306 specifies the internal data memory (RAM) and the special register. The data for specifying th internal data memory (RAM) and the special register (@ARO, I/O, SMOD) in the register/counter 306 is applied to the data bus 700 through a gate 309, when the gate 307 provides a signal 308. A memory unit 400 stores data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). The memory unit 400 stores data in the second and third bytes succeeding an instruction code. A register/counter 401 stores data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD) in the second byte succeeding an instruction code and applied to the data bus 700, when a gate 402 provides a signal 403. the register/counter 401 also serves as an up-counter which counts up by one every time the signal C is provided. A register/counter 404 specifies the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). The register/counter 404 stores data on the data bus 700, that is , the data in the third byte succeeding an instruction code, when a gate 405 provides a signal 406. The register/counter 404 serves also as an up-counter which counts up by one every time the signal C is provided. In repeating an instruction (operation between data in arbitrary regions) represented by instruction mnemonics capable of addressing two operand addresses, such as ADDC data address 1 and data address 2, the register/counter 404 is set for the data address 2 and counts up by one every time the instruction is executed. A memory unit 500 stores data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD) stored in the register/counters 401 and 404, and selected data. A signal WIR3 makes a gate 502 select the data stored in register/counters 401 and 404. When a gate 503 provides a signal 504, a register 501 stores data selected by a gate 502 among the data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD) stored in the register/counters 401 and 404. A decoding unit 600 generates signals (R/W) for controlling the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). A selecting circuit 601 selects the contents of the register/counter 306 or the data for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD) according to a selection signal 604 and transmits the selected data to a second PLA 602. The second PLA 602 decodes data transferred from the register 501 and the register/counter 306 and generates control signals for operating the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). The second PLA 602 decodes data stored in the register 501 and the counter 306, namely, data selected by the selecting circuit 601 among those for specifying the internal data memory (RAM) and the special register (@ARO, I/O, SMOD), provides the logical product (AND) of the decoded data and a timing signal 603, and generates control signals for controlling the internal data memory (RAM) and the special register (@ARO, I/O, SMOD). The respective constitutions of the internal data memory (RAM) and the special register 40 (@ARO, I/O, SMOD) will be described hereinafter with reference to Fig. 3. The internal data memory (RAM) 31 of the CPU is divided into banks. Each bank comprises eight registers R0 to R7, which are specified by data addresses 00H to 07H, respectively. The RAMDPL register 30 (Fig. 1) specifies the banks of the internal data memory (RAM). The areas of the special register (@ARO, I/O, SMOD) 40 is assigned to data addresses 08H to FFH. The areas assigned to data addresses 08H to 0FH, namely, areas @AR0 to @AR7, among the areas of the special register 40 are indirect data address specifying registers. When the areas 08H to 0FH are specified, the contents of the areas @AR0 to @AR7 specify the internal data memory and the special register 40. Areas 10H to 3FH are data memories (RAMs) within the special register. Areas 40H to FFH are special function registers, such as I/O ports and timer counters, which are assigned to data addresses. The manner of operation of the instruction decoder thus constructed will be described with reference to Fig. 4. In Fig. 4, a signal OSC1 is a clock signal generated by the internal oscillator of the CPU, and a signal CLOCK is a synchronizing clock for controlling the timing of writing data in the internal data register and the special register of the CPU. BUS7 to BUS0 are signals applied to the data bus 700. A signal 203 (WIR1) corresponds to the signal 203 (Fig. 2). An indication 201 (REGISTER) indicates the mode of the instruction register 201 (Fig. 2). An indication 101 (REGISTER) indicates the mode of the register 101 (Fig. 2) for setting the number of execution cycles of an instruction. An indication 110 (COUNTER) indicates the mode of the counter 110 for counting the number of execution cycles. Signals A, B, C and D corresponds to the signals A, B, C and D in Fig. 2. An indication 301 (REGISTER) indicates the mode of the register 301 (Fig. 2). An indication 306 (COUNTER) indicates the mode of the register/counter 306 (Fig. 2). A signal 403 (WIR2) corresponds to the signal 403 in Fig. 2. An indication 401 (COUNTER) indicates the mode of the register/counter 401 (Fig. 2). A signal 406 (WIR3) corresponds to the signal 406 in Fig. 2. An indication 404 (COUNTER) indicates the mode of the register/counter 404 (Fig. 2). Signals WIR2 and WIR3 corresponds to the signals WIR2 and WIR3 in Fig. 2. An indication 501 (REGISTER) indicates the mode of the register 501 (Fig. 2). A signal 604 (SEL DAR) corresponds to the signal 604 in Fig. 2. An indication 601OUT indicates the output mode of the selecting circuit 601. Signals ENABLE SFR and ENABLE RAM are read signals provided by the PLA2 (Fig. 2) to request reading data from the internal data memory and the special register. Signals WRITE SFR and WRITE RAM are write signals provided by the PLA 602 (Fig. 2) to request writing data in the internal data memory and the special register. A signal WRPR1 is a signal to request writing data in the TPR1 register 20 (Fig. 1). An indication TPR1 indicates the mode of the temporary register 20. A signal WTPR2 to request writing data in the temporary register 21 (Fig. 1). An indication TPR2 indicates the mode of the temporary register 21. An indication ALU MODE indicates the mode of operation of the ALU 23 (Fig. 1) A signal ENABLE ALU is the output signal of the ALU 23 (Fig. 1). A signal WPSW is a signal to request writing data in the register 24 (flag status register) (Fig. 1). A signal CARRY indicates a carry provided when the eighth bit of the ALU 23 is specified by a main carry flag stored in the temporary register 24. A signal AC is an auxiliary flag stored in the temporary register 24 and specifying a carry in the fourth bit of the ALU 23. A signal ALU CARRY IN indicates a carry input to the ALU 23 (Fig. 1). A signal SELECT is a control signal to request consecutive execution, which is provided by the PLA 205 (Fig. 2) when an ADDC A, data address instruction is given to the instruction register 201 (Fig. 2). An indication OP MODE indicates the execution of a consecutive execution instruction. The time chart of Fig. 4 shows, by way of example, the mode of an operation specified by an instruction mnemonic ADDC A, data address for repeating an ADDC A, data address instruction three times. Prior to the execution of the ADDC A, data address instruction, the consecutive execution frequency setting register 101 (Fig. 2) is set for "03H" to repeat the instruction three times. The register 301 (Fig. 2) specified by an instruction mnemonic A is set for 00H to specify an address "00H" in the internal data memory (RAM). The data address starts from an address "30H". Table 1 shows data mnemonics A and the status of data assigned to data addresses. When an EROM signal is provided in the first period M1-S1, an instruction code "35H" at the address ADDC A, data address is read from the program data memory (ROM) 4 (Fig. 1), the buses 7 to 0 become "00110101". When the signal WIR1 203 is provided, "35H" is stored in the instruction register 201. At the same time, the contents of the register 301 are transferred to the counter 306 and thereby the counter 306 becomes "00H". Since the signal SEL DAR 604 provided by the selecting circuit 601 remains "1" in M1-S1 through the middle of M1-S3, the contents of the counter 306 are given to the PLA 602. In M1-S3, the data "50H" at the address 00H in the PLA 602 specified by the contents of the counter 306 are read and the status of the buses 7 to 0 becomes "0101000". At this moment, the PLA 205 provides the signal WTPR2 to store the data "50H" in the TPR2. When the gate 107 provides the signal 108 in the first M1-S3, the flip-flop 109 provides the signal B which has been fetched at the trailing edge of M1-S3. Then, the register 110 fetches consecutive execution frequency setting data 03H from the register 101. After the data 03H has been registered in the register 110, the output signal A of the gate 110 becomes "0" to inhibit the operation of the gates 107, 113, 202 and 310. In M1-S4, the EROM signal is provided to read the data "30H" of the second byte of the instruction code from the ROM 4, and then the status of the buses 7 to 0 becomes 00110000. At this moment, the PLA 205 provides the signal WIR2 to store the data "30H" in the register/counter 401 and the register 501. Since the signal 604 (SEL DAR) applied to the selecting circuit 601 remains "0" during a period M1-S4 through the middle of M2-S3, the contents of the register 501 are applied to the PLA 602. In M1-S5, the PLA 602 provides a read signal to read the data "22H" of address "30H" and the status of the buses 7 to 0 becomes "00100010". At this moment, the PLA 205 provides the signal WTPR1 to store the data "22H" in the temporary register 20 (TPR1). Since the ALU 23 is in the ADD instruction execution mode, the PLA 205 provides the ADD signal to add the contents of the temporary registers 20 and 21. Since the signal 604 (SEL DAR) applied to the selecting circuit 601 remains "1" during M2-S4 to the middle of the next M1-S3, the contents of the register/counter 306 are given to the PLA 602. In M2-S5, PLA 205 provides the signal ENABLE ALU, and then the ALU 23 provides the result of addition, namely, the addition of the contents of the temporary registers 20 and 21 and a carry (22H + 50H + 0 = 72H), and the status of the buses becomes "01110010". At this moment, the PLA 602 provides the write signal WRITE RAM to write data "72H" at an address "00H" as specified by the register/counter 306. The PLA 205 then provides a write signal WPSW to write the main carry and the secondary carry in the register 24. Since the main carry and the secondary carry are not provided after the first cycle of ADD operation, the result of the first cycle of ADD operation is "0". In M2-S5, when the gate 112 provides the signal C, namely, a count clock, the contents of the register/counters 110, 306 and 401 are renewed at the trailing edge of M2-S5 to change the contents of the register/counter 110 from "03H" to "02H", those of the register/counter 306 from "00H" to "01H", and those of the register/counter 401 from "30H" to "31H". In M2-S6, since the signal A applied to the gate 113 is "0", the output signal D of the flip-flop 116 is "0". Consequently, the operation of the gates 402 and 405 is interrupted. After M2-S6 has been completed, the second execution cycle of the instruction is started. In the second M1-S1, since the signal A applied to the gate 202 which generates a write signal specifying write operation in the instruction register 201 is "0", the write signal 203 specifying write operation in the instruction register 201 is not provided, and hence the instruction code "35H" stored in the instruction register 201 for the first M1-S1 remains in the instruction register 201. Accordingly, the instruction stored in the first execution cycle is executed. In M1-S3, the PLA 602 provides the signal ENABLE RAM specifying reading data from address "01H" in the register/counter 306, and thereby the contents OAAH of the address "01H" is provided on the bus and the buses 7 to 0 becomes "10101010". At this moment, the PLA 205 provides the signal WTPR2 and the temporary register 21 stores "OAAH". Although the PLA 205 provides the signal WIR2 in M1-S4, the signal 403 specifying writing data in the register/counter 401 is not provided because the signal D applied to the gate 402 is "0". Accordingly, the contents of the register/counter 401 are not changed. The signal WIR2 is used for specifying writing data in the register 501. Since the signal WIR3 applied to the selecting circuit 502 before the register 501 is "0", the register 501 stores the contents "31H" of the register/counter 401. In M1-S5, the PLA 602 provides the signal ENABLE SFR to read data from address "31H" specified by the contents of the register 501, and thereby the contents "OBCH" of the address "31H" is provided on the bus and the buses 7 to 0 becomes "10111100". At this moment, the PLA 205 provides the signal WTPR1 to store the data "OBCH" in the temporary register 20. Since the ALU is in the ADD instruction execution mode, the PLA 205 provides an ADD signal. In M2-S5, the PLA 205 provides the signal ENABLE ALU and thereby the result of addition of the data of the temporary registers 20 and 21, and the main carry, namely, (BC + AA + 0 = 66), is provided on the bus, and the buses 7 to 0 becomes "01100110". At this moment, the PLA 602 provides the write signal WRITE RAM specifying writing data "66H" at address "01H" specified by the registe 306. Also, the PLA 205 provides the write signal WPSW to write the main carry and the secondary carry in the register 24. The main carry and the secondary carry provided after the second cycle of the addition instruction are "1". In M2-S5, the gate 112 provides signal C and the contents of the register/conters 110, 306 and 401 are renewed at the trailing edge of the M2-S5 to change the contents of the register/counters 110, 306 and 401 from "02H" to "01H", from "01H" to "02H", and from "31H" to "32H", respectively. In M2-S6, since the data input gate 113 applies the signal A = "0" to the flip-flop 116, the output signal of the flip-flop 116 continues being "0". Upon the end of M2-S6, the third execution cycle is started. In the third M1-S1, since the signal D = "0" is applied to the input AND gate 202 which generates a write signal specifying writing data in the instruction register 201, the write signal 203 is not provided. Accordingly, the instruction code "35H" stored in the instruction register 201 in M1-S1 of the first execution cycle remains in the instruction register 201, and hence the instruction stored in the first execution cycle is executed. In M1-S3, the PLA 602 provides the write signal ENABLE RAM specifying reading data from address "02H" specified by the register 306, and thereby the data "33H" of the address "02H" is provided on the bus and the buses 7 to 0 becomes "00110011". At this moment, the PLA 205 provides the signal WTPR2, and the temporary register 21 stores the data "33H". In M1-S4, although the PLA 205 provides the signal WIR2, the signal 403 specifying writing data in the register 401 is not provided because the signal D applied to the input AND gate 402 is "0", and hence the contents of the register 401 are not changed. The signal WIR2 serves as a write signal for the register 501. Since the signal WIR3 applied to the selecting circuit 502 before the register 501 is "0", the contents "32H" of the register 401 are stored in the register 501. In M1-S5, the PLA 602 provides the signal ENABLE SFR specifying reading data from address "32H" specified by the contents of the register 501. Then, the contents "55H" of the address "32H" are provided on the bus, and the buses 7 to 0 becomes "01010101". At this moment, the PLA 205 provides the signal WTPR1 to store the data "55H" in the temporary register 20. Since the ALU is in the ADD instruction execution mode, the PLA 205 continues providing the signal ADD. In M2-S5, the PLA 205 provides the signal ENABLE ALU, and thereby the addition (33H = 55H + + 1) of the contents of the temporary registers 20 and 21, and the main carry is provided, and the buses 7 to 0 becomes "10001001". At this moment, the PLA 602 provides the write signal WRITE RAM specifying writing data in address "02H" specified by the register 306 to store "89H" at the address "02H". Also, the PLA 205 provides the write signal WPSW to write the main carry and the secondary carry in the register 24. Since the main carry and the secondary carry are not provided at the end of the addition, both the crries are "0". In M2-S5, the signal C, namely, the count clock for the register/counters 110, 306 and 401, is provided to change the contents of the register/counters 110, 306 and 401 from "01H" to "00H", from "02H" to "03H", and from "32H" to "33H", respectively. In M2-S6, the contents of the register/counter becomes "00H", and hence the output count completion signal A of the gate 111 changes from "0" to "1". The output count completion signal A = "1" is applied to the gate 113 and thereby the output signal D of the flip-flop 116 changes from "0" to "1". The three-cycle consecutive execution mode is ended at the end of M1-S6. In the next M1-S1, since the signal A = "1" is applied to the gate 202 which gives a write signal to the instruction register 201, the gate 202 gives the signal 203 to the instruciton register 201. Then, the instruction register 201 stores the next instruction. Consecutive add operation for processing data shown in Table 2 by a conventional data processing system and by a data processing system according to the present invention will be compared hereinafter. Conventional Data Processing System (1) CLR C Clear main carry (2) MOV A, 00 Move data at 00H to A (3) ADDC A, 30 Add A and data at 30H (4) MOV 00, A Store result of addition at 00H (5) MOV A, 01 Move data at 01H to A (6) ADDC A, 31 Add A and data at 31H (7) MOV 01, A Store result of addition at 01H (8) MOV A, 02 Move data at 02H to A (9) ADDC A, 32 Add A and data at 32H (10) MOV 02, A Store result of addition at 02H Data Processing System of the Present Invention (1) CLR C Clear main carry (2) MOV DAR, #00 Set DAR for data at 00H (3) MOVMOD, #03 Set MOD for consecutive execution frequency data 03H (4) ADDC A, 30 Execute A and instruction at 30H Thus, the conventional data processing system executes ten instructions, whereas the data processing system of the present invention executes only four instructions for the same purpose. The instruciton decoder of the present invention has high ROM byte efficiency and operates at a high processing speed. Particularly, when a data transfer instruction (MOV data address 1, data address 2) is given, data can easily be transferred in blocks between optional areas, and hence a subroutine can easily be constructed without using any stack in an interruption process and an ordinary process. As apparent from the foregoing description, according to the present invention, the operation of optional successive bytes can be carried out by counting the contents of a register for counting the number of cycles of instruction execution, a register for specifying data address, and a register specified by an instruction mnemonic A every time one cycle of instruction execution is completed. Furthermore, registers 401 and 404 are used for repeatedly executing an instruction denoted by an instruction mnemonic ADDC data address 1, data address 2 for successive operand addresses, and the contents of the registers 401 and 404 are counted up by "1" every time one cycle of the instruction is executed in a manner similar to that described with the registers 306 and 401 to form addresses continuously. Thus, according to the present invention, in processing different data (operands) stored at different addresses, for example, in a data memory and a special register by repeating the same operation, the instruction of the operation is held in an instruction register and the different operand addresses are specified sequentially, so that the data is processed at a high processing speed and at a high byte efficiency.

Claims: An instruction decoder for a processor for executing an instruction repetitively on a variable number of operand bytes, which comprises: an instruction register (201) for reading instructions, connected to a data bus; an instruction decoding unit (205) which reads an instruction from said instruction register (201) to control the general operation of the processor and provides a consecutive execution mode signal upon the reception of a consecutive execution instruction specifying the repetition of the same instruction for operands stored at different operand addresses; a consecutive instruction execution cycle monitoring unit (100) which is set to a set value indicating the number of consecutive instruction execution cycles when the consecutive execution mode signal is provided, counts the number of execution cycles and provides a count completion signal upon correspondence of the count of the execution cycles with the set value; address register/counters (306, 401) to receive concurrently respective bytes of the instruction from the data bus and which change their count in response to completion of each execution cycle of the instruction and thereby each provide different addresses for data to be processed for successive execution cycles, respectively; an operand access control unit (602) which receives the outputs of said address register-counters (306, 401) and addresses data at different operand addresses sequentially; a read inhibiting means (202) which inhibits said instruction register (201) from reading a new instruction from the data bus during a period from when said consecutive execution mode signal is provided to when the count completion signal is provided; and control means (501, 502, 601) operative to apply sequentially the value from first and second of said address register-counters (306, 401) to said operand access control unit (602), and temporarily holding the value from one of said address register whilst the value from the other thereof is applied to said operand access control unit (602). An instruction decoder according to claim 1, wherein said consecutive instruction execution cycle monitoring unit (100) comprises: a register (101) which receives the set value indicating the number of execution cycles from the data bus and stores the set value; a register/counter (110) which is set for the set value stored in said register (101) and counts down by one every time an execution cycle is completed; and a gate means (111) which provides the count completion signal upon the reduction of the count of said register/counter (110) to zero. A instruction decoder according to claim 1 or 2 including a third address register/counter (404) to receive a third byte of the instruction from the data bus concurrently with the first and second bytes, and thereafter to change the count thereof in response to completion of each said execution cycle to produce said different addresses for the successive execution cycles.

Inventors: YOKOUCHI HIROSHI OKI ELECTRIC, YOKOUCHI, HIROSHI OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1988
Main classification: G06F9
IPC codes: G06F9