Non-volatile memory cell

Abstract: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Description: The present invention relates generally to integrated circuit memory cells, and more particularly to non-volatile, programmable memory cells. Reference is made to co-pending U.S. Patent Application S.N. 869,469, entitled "Dual Gate EEPROM Cell," filed May 28, 1986, continuation of U.S. Patent Application S.N. 655,175, filed September 27, 1984, now abandoned. The invention relates to an EEPROM cell wherein first and second dual electron injector structure (DEIS) control gates overlay a single polysilicon floating gate, and are coupled to separate control voltages so as to write to and read from the cell without an intervening erase cycle. Electrically erasable programmable read only memories (EEPROM) have gained widespread acceptance in the industry. EEPROM cells do not require the periodic refresh pulses needed by the capacitive storage elements of conventional one-device dynamic random access memory (DRAM) cells. This presents an appreciable power savings. Because they rely upon charge injection/removal to establish the stored logic state, the write cycles of EEPROM cells are appreciably longer than those of DRAM's. Several exemplary EEPROM technologies will now be discussed. U.S.P. 3,500,142 (issued March 10, 1972, to Kahng and assigned to AT&T) describes a programmable field effect transistor (FET) wherein the gate electrode is defined by a layer of silicon oxide disposed over a portion of the silicon substrate between two P-type diffusion regions, a layer of zirconium on the oxide layer, a layer of zirconium oxide on the zirconium layer, and a control electrode on the zirconium oxide layer. The zirconium layer serves as a "floating gate" structure. That is, the zirconium layer is not directly coupled to a source of applied potential. Rather, it is allowed to assume its own voltage state (i.e., "float") as a function of the capacitive coupling between it and the overlying control electrode. To program the cell, a high bias is applied to the control electrode. The capacitive coupling between the control electrode and the floating gate is such that a channel region is induced in the underlying portion of the silicon substrate between the two P-type diffusion regions. At this high bias potential, some carriers will have sufficient energy to be injected through the silicon oxide layer into the floating gate. This injection of carriers (by avalanche breakdown or by hot electron effects) will provide an amount of charge to the floating gate that is determined by the applied bias. To erase the cell, a negative bias is supplied to the control electrode such that the charge carriers previously accumulated in the floating gate are injected through the oxide layer into the silicon substrate. In other EEPROM cells, a non-conductive charge trapping layer is used in place of the above zirconium floating gate. In U.S.P. 3,878,549 (issued April 15, 1975, to Yamazaki et al) the FET gate electrode is comprised of a layer of silicon oxide contacting the silicon substrate, a thin layer of silicon nitride over the silicon oxide, a plurality of silicon clusters disposed on the nitride layer, a second layer of silicon nitride overlying the silicon clusters, and a control electrode. At high applied bias, electrons will be injected through the silicon oxide layer and the first silicon nitride layer, where they will be trapped by the silicon clusters overlying the silicon nitride layer. In Japanese Published Patent Application J55-87490-A (filed December 25, 1978 by Endou and assigned to Toshiba), a plurality of interposed silicon oxide and silicon nitride layers are provided. Charge injected from the substrate is trapped by one or more of the silicon nitride films depending on the magnitude of the applied bias. PCT Application 80-01179 (filed September 13, 1979, by Trudel et al and assigned to NCR) discloses a non-volatile memory cell in which charge injected from the silicon substrate passes through a silicon oxide layer where it is trapped by a layer of silicon nitride. U.S.P. 3,649,884 (issued March 14, 1972, to Haneta and assigned to NEC) discloses a field effect transistor with a gate assembly that includes an intervening layer of silicon rich silicon oxide that traps charge injected from the silicon substrate through an intervening layer of stoichiometric silicon oxide. In the references discussed above, the memory cell is programmed by charge injection from the induced channel region of the substrate, through an intervening insulating layer, into a conductive or non-conductive charge trapping layer. In practice, it is difficult to precisely control the extent of charge injection from the induced channel region. The silicon oxide layer separating the channel region from the overlying charge trapping layer must be thin enough to allow charge transfer and yet thick enough to allow the charge trapping layer to retain the stored charge. These characteristics are very sensitive to changes in the thickness and/or stoichiometry of the oxide film. In order to surmount these difficulties, researchers have attempted to construct EEPROM cells that do not rely upon charge injection from an induced channel regio. In U.S.P. 4,104,675 (issued August 5, 1978, to DiMaria et al and assigned to the assignee of the present invention), the silicon substrate is covered with a thick layer of thermal silicon oxide and thin layers of pyrolytic silicon oxide. A layer of aluminum is disposed above the pyrolytic SiO₂ layers. As shown in Fig. 7 of the patent, the aluminum layer serves as the gate electrode of an FET storage device with the pyrolytic SiO₂ layers and the thermal SiO₂ layer serving as the gate dielectric. The pyrolytic SiO₂ layers have excess silicon incorporated in them. The amount of excess silicon is increased as a function of distance from the thermal SiO₂-silicon substrate interface. This increase in silicon concentration produces a graded band gap structure that is conducive to injection of holes and electrons from the aluminum electrode to the SiO₂-substrate interface. Thus, rather than relying on surface tunneling, the DiMaria patent shows a structure in which charge injection/removal takes place between a trapping center and an overlying charge injection structure. In practice, it would be difficult to construct a memory cell based upon the teachings of this patent, in that the thick silicon oxide layer is a poor trapping layer. That is, not enough charge would be trapped, and the charge which is trapped would be non-uniformily dispersed within the silicon oxide layer. As such, the effect of a given quantity of the trapped charge upon the threshold of EEPROM cell the device will vary from device to device. Some of the above-noted shortcomings were recognized by DiMaria in his later work. See for example an article by DiMaria et al, entitled "Electrically-Alterable Read-Only-Memory Using Silicon-Rich SiO₂ Injectors and a Floating Polycrystaline Silicon Storage Layer," Journal of Applied Physics , Vol. 52, No. 7, July 1981, pp. 4825-4842. As shown in Fig. 2 of this paper, a stoichiometric silicon oxide layer is sandwiched between two silicon-rich silicon oxide layers. The lower silicon-rich silicon oxide layer is disposed on a first polysilicon electrode, and the upper silicon-rich silicon oxide layer is disposed below a second polysilicon electrode. Charge transfer is effected between the two polysilicon electrodes through the two silicon-rich silicon oxide layers. The dual silicon-rich silicon oxide layers, in conjunction with the central stoichiometric silicon oxide layer, is commonly referred to as a dual electron injector structure (or DEIS). Note first that the lower polysilicon electrode serves as a floating gate that stores injected charge. Such a structure will store more charge than the thick oxide layer of the above-described patent, while storing the injected charge in a more uniform manner. Moreover, as opposed to the patent, the amount of silicon in the lower and upper silicon rich silicon oxide layers is relatively similar, and the intervening silicon oxide layer does not have any excess silicon. However, the above-described memory cell suffers from still another problem. In order to provide a reliable charge storage structure, a conductive layer is used. Thus, similarly to the Kahng '142 patent previously cited, reliance is placed upon the capacitive coupling between the floating gate and the control gate to program and/or erase the cell. This situation is incompatible with current device technologies which rely on lower applied voltages. Moreover, because it is difficult to precisely control the characteristics of the oxide layer between the two polysilicon layers, the capacitive characteristics must be compensated by increasing the size of the lower polysilicon electrode relatively to the upper polysilicon electrode. This is also incompatible with current device scaling trends. EP-A-0 166 208 discloses a four layer charge storage structure comprising alternate layers of silicon-rich silicon dioxide and silicon dioxide with electrode layers on top and bottom. The upper and middle silicon-rich layers act as injectors and the middle silicon-rich layer also stores charges since the silicon particles act as deep traps. The charge storage properties of silicon-rich layers have proven to be not fully satisfactory, especially, if applied to nonvolatile memories. Accordingly, there is a need in the art for an EEPROM storage cell that incorporates a non-conducting charge trapping structure that is not programmed by hot carrier injection and which is compatible with current device scaling trends. Thus, it is an object of the invention to provide a non-conductive charge trapping structure. It is another object of the invention to provide a charge trapping structure that does not rely on hot carrier injection. It is yet another object of the invention to provide a charge trapping structure that is not overly sensitive to small variations in thickness and/or stoichiometry. It is a further object of the invention to provide a charge trapping structure that can be utilized in dense EEPROM arrays. The foregoing and other objects of the invention are realized by a charge trapping structure that is comprised of a layer of silicon-rich silicon nitride. The silicon content of the silicon-rich silicon nitride layer is controlled such that the layer provides appreciable charge storage enhancement, without providing appreciable charge conduction enhancement, as compared to stoichiometric silicon nitride. In one particular aspect of the invention, a charge trapping injection structure is provided by the above layer of silicon-rich silicon nitride, a barrier layer, and a second layer of silicon-rich silicon nitride that provides appreciable charge conductance enhancement, without providing appreciable charge storage enhancement, as compared to stoichiometric silicon nitride. In another particular aspect of the invention, the above-described charge trapping/injection structure is provided between the gate dielectric and the control electrode to define the gate electrode of an FET EEPROM cell. The cells are disposed in a series of substrate portions isolated from one another by deep, isolation trenches. The substrate portions can be individually biased by respective substrate bias generators. This allows erasure of individual cells, to provide an overwriteable EEPROM array. A memory cell incorporating the above structures eliminates the scaling constraints provided by conductive trapping layers, while avoiding hot carrier injection as a charge injection mechanism. The foregoing and other structures and teachings of the present invention will become more apparent upon a description of the best mode for carrying out the invention as rendered below. In the description to follow, reference will be made to the accompanying drawing, in which: Fig. 1 (Prior Art) is a graph showing refractive index of silicon-rich silicon nitride films versus SiH₂Cl₂/NH₃ flow rate ratio; Fig. 2 is a graph showing current density versus applied field for silicon-rich silicon nitride films having different percentages of excess silicon; Fig. 3 is a graph showing flat band shift versus time at an applied field of 4x10⁶ volts/cm for silicon-rich silicon nitride films having varying percentages of excess silicon; Fig. 4 is a graph showing flat band shift versus time at a applied field of 7x10⁶ volts/cm for silicon-rich silicon nitride films having varying percentages of excess silicon; Fig. 5 is a graph showing flat band shift versus applied fields of different polarity for stoichiometric silicon nitride and silicon-rich silicon nitride at R=5; Fig. 6 is a cross-sectional view illustrating a memory cell constructed in accordance with the teachings of the present invention; Fig. 7 is a top view of an array of the memory cells shown in Fig. 6; Fig. 8 is a cross-sectional view taken along lines 8-8 of Fig. 7; Fig. 9 is a cross-sectional view taken along lines 9-9 of Fig. 7; Fig. 10 is a cross-sectional view of one method of providing isolated substrate portions so as to practice the invention; Fig. 11 is a cross-sectional view of another method of providing isolated substrate portions so as to practice the invention; and Fig. 12 is a cross-sectional view illustrating another embodiment of the gate stack of the memory cell of the present invention. In attempting to provide a non-conductive charge trapping structure, the inventors considered a number of alternatives. Each of these alternatives are discussed below. Stoichiometric SiO₂ has been shown to have charge trapping properties. These charge trapping properties vary greatly as a function of processing. In an article by Gdula, "The Effects of Processing on Hot Electron Trapping SiO₂," J. Electrochem. Soc. , January 1976, pp. 42-47, boron-doped CVD SiO₂ was shown as having a charge trapping efficiency that is three orders of magnitude greater than that of SiO₂ thermally grown in a dry O₂ ambient. In an article by Young, "Electron Trapping in SiO₂," Inst. Phy. Conf. , S.N. 50, 1980, pp. 28-39, the trap density was also shown to vary by one order of magnitude as a function of post-deposition anneal time, temperature, and ambient. The optimum trap density for SiO₂ has been shown to be on the order of 10¹⁷-10¹⁸/cm³. This is at least three orders of magnitude less than what is needed to control the channel region of an FET. Moreover, because of the high diffusivity of silicon within SiO₂, the actual trap locations vary in distance from the substrate surface. This produces variations in the effect of the stored charge on the threshold voltage of the storage cell. Silicon-rich SiO₂ has been shown to have a greater amount of traps than does stoichiometric SiO₂. In an article by DiMaria et al, "Charge Transport and Trapping Phenomena in Off-Stoichiometric Silicon Dioxide Films," J. Appl. Phy. , Vol. 54, No. 10, October 1983, pp. 5801-5827, Si-rich SiO₂ (1%-6% excess Si) was shown as having approximately 10²⁰ traps/cm³. In addition to the -OH functional groups and the physical discontinuities that provide the major trap centers in stoichiometric SiO₂, silicon-rich SiO₂ has clusters of silicon atoms that provide extra traps. However, as pointed out in the DiMaria paper, the presence of the Si clusters presents a new mechanism for electron transport (i.e., Fowler-Norheim tunneling between the cluster-cluster energy bands). This enhances the conductivity of the film to the point where the 1%-6% Si-rich SiO₂ films store less charge than do stoichiometric SiO₂ films. As the silicon content of the SiO₂ film increases, the above conductivity characteristics increase exponentially due to the combined efforts of increased silicon cluster size and decreased inter-cluster distance. It has been shown that a highly Si-rich SiO₂ layer (Si=13% above stoichiometric) on top of a stoichiometric SiO₂ layer produces an electron current ≈ 10⁵ greater than that provided by SiO₂ alone at the same applied bias. See DiMaria et al, "High Current Injection Into SiO₂ From Si-Rich SiO₂ Films and Experimental Applications," J. Appl. Phy. , Vol. 51, No. 5, May 1980, pp. 2722-2735. As shown in the DEIS EEPROM patents previously cited, this injection characteristic has been used in many EEPROM applications. However, since Si-rich SiO₂ functions as a charge injector rather than a charge trap, it cannot be used to provide a charge retention function. It is known to use silicon nitride as a charge trapping structure. In the metal-silicon nitride-oxide-silicon (MNOS) PROMs, electrons injected from the substrate by avalanche breakdown pass through the oxide layer and are trapped by the silicon nitride layer. However, these devices suffer from several problems. "Charge stored in the Si₃N₄ layer will rearrange itself and leak off in time due to the conductivity and bulk trapping properties of the Si₃N₄. Trapped charges can also back-tunnel from near the Si₃N₄-SiO₂ interface to the Si substrate through the thin (≊ 0.5-3nm) SiO₂ layer." DiMaria et al, "Electrically - Alterable Read-Only-Memory Using Si-Rich SiO₂ Injectors and a Floating Polycrystalline Silicon Storage Layer," J. Appl. Phy. , Vol. 52, No. 7, July 1981, pp. 4825-4842, 4826. In conducting experiments on silicon-rich Si₃N₄, the inventors found that the bulk conductivity characteristics agreed with DiMaria's findings regarding Si-rich SiO₂. As the silicon content was increased, the conductivity of the films also increased. The net effect was to decrease trapping at low Si percentages and to substantially eliminate trapping at higher Si percentages. These results were presented at the 166th Meeting of the Electrochemical Society (New Orleans, LA, Oct. 7-12, 1984) in a presentation entitled "Physical and Electrical Characteristics of LPCVD Si-Rich-Nitride Films" by A. Bhattacharyya et al. See also Tanabashi et al, "Properties of Vapor Deposited Silicon Nitride Films with Varying Excess Si Content," Japan J. Appl. Phy. , Vol. 12, No. 5, May 1973 pp. 641-647. However, when stressing thin films (10nm) at constant voltage versus the thick films (≧ 0.1 µm) stressed at constant current as discussed in the above references, the inventors found that at small percentages of additional Si in the Si₃N₄, the additional trap center density was not offset by enhanced conductance as it is in low percentage Si-rich SiO₂. In other words, low percentage Si-rich Si₃N₄ films effectively store more charge than does stoichiometric Si₃N₄. For higher silicon percentages, the enhanced conductance effect began to increase. Eventually, the observed thin film properties were in agreement with those previously reported for the bulk film. The above experimental results are shown in Figs. 1-3. A capacitor structure from which these results were obtained consisted of a 4,5 nm SiO₂ layer thermally grown on a p-type silicon substrate, a 7,5 nm Si₃N₄ layer deposited by LPCVD (0.25 Torr, 770°C) using dichlorosilane and ammonia at varying ratios (from R=0.1 for stoichiometric Si₃N₄ to R=31 for heavily Si-rich Si₃N₄), and a one micron layer of aluminum. Fig. 1 (Prior Art) is a graph of SiH₂Cl₂/NH₃ flow rate ratio R versus the index of refraction of the Si₃N₄ films. as shown at the 1984 ECS presentation. The index of refraction increases linearly with increasing silicon content. Fig. 2 shows a plot of log J (current density in amperes/cm²) versus electric field E (volts/cm) for Si₃N₄ layers having an R of 0.1, 3, 5, 10, 15, and 31. In general, the plot show that the Si₃N₄ layers having small additions of silicon (R=3 and 5) exhibit a relatively small conductivity increase over stoichiometric Si₃N₄. Conductivity enhancement substantially increases with increasing silicon content at or above R=10. Fig. 3 is a plot of flatband shift versus time at an applied electric field of 4x10⁶ v/cm. Notice that for R=3, the flatband shift is greater than the shifts produced by films having an R of 0.1, 10 or 15. Notice also that the film having an R of 10 provides a greater flatband shift than does a film having an R of 15. When the applied field is raised to 7x10⁶ v/cm (Fig. 4), the flatband shift produced by the R=3 film is even greater, while the shifts produced by the R=10 and R=15 films do not appreciably change. The above-described experimental results indicate that at low additional silicon content, silicon-rich Si₃N₄ films exhibit appreciably enhanced trapping characteristics (as shown by the high flatband shifts at moderate and high applied electric fields in Figs. 3 and 4, respectively) without exhibiting appreciably enhanced conductivity characteristics (as shown in Fig. 1). This is the opposite of what was previously reported for low percentage silicon-rich silicon oxide films. A further experiment was conducted in attempting to characterize the charge trapping properties of silicon-rich Si₃N₄. Fig. 5 shows a plot of the flatband shift produced at an applied electric field (in MV/cm) of either polarity when stressed for a fixed time duration at any field strength. The test structure consisted of 7,0 nm of thermal silicon oxide grown on a p-type silicon substrate, 10 nm of deposited nitride or silicon-rich Si₃N₄ (R=0.1 and 5), 4,5 nm of oxide thermally grown on the Si₃N₄ or silicon rich Si₃N₄ layer, and a one micron layer of aluminum. Note that the stoichiometric Si₃N₄ (solid line) exhibits a positive flatband shift for E-fields of either polarity, and that the difference between the two shifts is only approximately 1.5 volts at E= ± 7.5x10⁶ v/cm. However, the Si-rich Si₃N₄ film of R=5 exhibits positive and negative flatband shifts as a function of E field polarity. Thus, both holes and electrons are being trapped. The difference between the two voltage shifts is approximately 3.5 volts at E=7.5x10⁶ v/cm. This difference in flatband voltage shift is sufficient to provide a manufacturable EEPROM storage cell. As shown by the experiments discussed above, silicon-rich silicon nitride films deposited at an R of 3 or 5 (for a refractive index of 2.10 and 2.17, respectively) will provide the charge storage function normally provided by a polysilicon floating gate of a EEPROM cell. In general, silicon-rich nitride films having an R greater than 0.1 and less than 10 (or, more specifically, having an index of refraction between approximately 2.10 and 2.30) will provide appreciably enhanced charge trapping without providing appreciably enhanced charge conduction. Fig. 6 presents a cross-sectional view of a EEPROM cell having the above-described silicon-rich silicon nitride layer as a charge trapping structure. A gate structure 50 is provided on the surface of a silicon substrate 10. The substrate 10 is a 〈100〉 oriented, N+ type monocrystalline silicon wafer having a P-surface region 12 formed by epitaxial deposition or by implantation. A 10 nm silicon oxide layer 20 is thermally grown on the substrate 10. In practice, the insulator 20 could also be comprised of a plurality of silicon oxide - silicon nitride or silicon oxide-silicon oxynitride layers. A silicon-rich silicon nitride film 30 deposited at R > 10 is provided on top of the silicon oxide layer 20. This layer should be approximately 1,5 nm to 10 nm in thickness. It is preferred that the silicon-rich silicon nitride film be deposited at an R in the range of equals 3 to 5. Then a 4 to 10 nm barrier layer 25 is formed on the silicon-rich silicon nitride film 30. It is preferable that this barrier layer be formed by thermal growth of an oxide layer on the silicon-rich silicon nitride layer, by exposure to a wet O₂ ambient held at high temperatures. In providing the EEPROM cell of the invention, the inventors wanted to maximize the charge stored at a given bias. Due to the sensitivities resulting from dense device geometries, the inventors wanted to utilize control voltages in the 10-12 volt range or less. As is known in the art, one method of increasing the amount of charge trapped by a charge trapping structure (while also eliminating tunnelling from the substrate as the charge injection mechanism) is to form a charge injecting structure above the charge trapping structure. Accordingly, a charge injection structure 35 is deposited on the barrier layer 25. In general, silicon oxide electron injector structures (consisting of a silicon-rich SiO₂ layer atop a stoichiometric SiO₂ layer) provide good charge injecting properties, and as such they can be utilized to provide a charge injection in the invention. However, in the present invention it is preferred to form the charge injector structure from a layer of silicon-rich silicon nitride (R > 10) atop an insulator such as stoichiometric SiO₂. Silicon nitride injectors are preferred over silicon oxide injectors for the following reasons. The interface between the silicon-rich SiO₂ film and the stoichiometric SiO₂ film provides enhanced injection. "The high current is believed to be caused by a localized electric field distortion at the Si-rich-SiO₂ - SiO₂ interface due to the two-phase (Si and SiO₂) nature of this material..". DiMaria et al, "Charge Trapping Studies In SiO₂ Using High Current Injection From Si-Rich SiO₂ Films," J. Appl. Phy. , Vol. 51, No. 9, September 1980, pp. 4830-4841. Studies have shown that silicon readily diffuses within silicon oxide. As shown in Tables II and III of an article by Nesbit entitled "Annealing Characteristics of Si-Rich SiO₂ Films," Appl. Phy. Lett. , Vol. 46, No. 1, January 1985, pp. 38-40, both the size of the silicon clusters in Si-rich SiO₂ and their diffusivity increases with increasing anneal time/temperature. Since high anneal time/temperatures are used in most post-gate electrode process sequences. The silicon clusters that provide the enhanced silicon oxide injection characteristics will diffuse into the adjoining SiO₂, disrupting the injection threshold by reducing the localized field distortions. Since silicon has a much smaller degree of diffusivity within Si₃N₄, the Si₃N₄/SiO₂ interface will be much more resistant to subsequent hot process steps. The resulting Si-rich Si₃N₄ injector (index of refraction equal to or greater than approximately 2.35, preferably 2.50 for an R of 15) will provide appreciably enhanced charge conductance (Fig. 2) without providing appreciably enhanced charge trapping (Figs. 3 and 4) over stoichiometric Si₃N₄. The conductive material defines a control electrode 40 in the form of an elongated line that interconnects a plurality of the gates. In this sense, the control electrode 40 is similar to the word lines commonly used to interconnect the transfer gate FETs of one-device dynamic random access memory cells. While the control electrode 40 can be made from a host of conductive materials (e.g., aluminum, aluminum alloys, refractory metals, refractory metal silicides, it is preferred that it be formed from doped polysilicon or a composite of a doped polysilicon and a refractory metal silicide such as tungsten silicide or titanium silicide. After the control electrode 40 is formed, a 50 to 200 nm layer of silicon oxide is deposited on the substrate, and is directionally etched in a CF₄/O₂ plasma to provide spacers 45 disposed on the sidewalls of the composite gate stack 50. To the extent that dielectric layer 20 was not patterned during the definition of the gate stack 50, remaining portions will be removed during definition of the spacers 45. N+ type diffusion regions 60, 65 are then defined by phosphorous ion implantation on either side of the composite gate electrode, and a passivation layer 80 (made up of a high dielectric reflowable material such as phosphosilicate glass, borophososilicate glass, or organic resins such as polyimide) is deposited on the wafer. A conventional photoresist is then deposited, exposed, and developed to expose portions of the passivation layer 80 lying above the diffusion regions 60, 65, and these portions are removed by etching in a CHF₃/O₂ RIE to define vias. A metal layer is then deposited and patterned to fill the vias and to thus establish contact to the diffusion regions. Finally, the metal layer is patterned so that selected ones of the diffusion regions are interconnected, as described in more detail below. Fig. 7 is a top view of an array of memory cells constructed in accordance with the present invention. A plurality of isolation regions 100A-100D are disposed in a serpentine fashion parallel to one another, so as to define isolated substrate portions. These isolation regions 100 will be described in more detail below. The wordlines 40A-40C are disposed in a direction orthogonal to the isolation regions 100A-100D. The portions of the wordlines 40A-40C that provide the control electrodes 40 atop the gate stacks 50 are designated by the reference letters G-O. Thus, for example, wordline 40A provides the control electrode 40 for a first gate stack G, a second gate stack H, and a third gate stack I. The metal lines 70A-70C and 75A-75C are disposed in an alternating manner in a direction parallel to that of the isolation regions 100A-100D. The metal lines interconnect alternating ones of the diffusion regions on each side of the wordlines. More specifically, referring back to Fig. 6, the metal lines 70A-70C are connected through the vias in the passivation layer 80 to the diffusion region 60. Metal lines 70A-70C will be biased such that the diffusion regions 60 act as the FET source electrodes. Thus, lines 70A-70C will be referred to as "source lines." Similarly, metal lines 75A-75C are coupled to the diffusion regions 65. Since the diffusion regions 65 will act as the FET drain electrodes, lines 75A-75C will be referred to as "drain lines." The contacts between the metal lines and the diffusion regions are depicted in Fig. 7 by the cross hatched boxes. Thus, adjacent memory cells disposed between the same isolation regions 100A-100D share a common diffusion region. For example, the memory cell defined by the gate stack G and the memory cell defined by the gate stack J share a common source diffusion region 60 coupled to the source line 70A. Similarly, the memory cell defined by gate stack J and the memory cell defined by gate stack M share a common drain diffusion region 65 coupled to drain line 75A. Fig. 8 presents a cross-sectional view taken along lines 8-8 of Fig. 7. As shown in Fig. 8, adjacent silicon portions (having e.g., diffusion regions 65A formed therein) are laterally separated by the isolation regions 100. The isolation regions 100 can be formed by etching portions of the silicon substrate exposed by a conventional photoresist atop a non-erodible mask (e.g., a layer of silicon oxide on the substrate and a layer of silicon nitride on the silicon oxide). The exposed substrate portions may be anisotropically etched in a chlorine-based gaseous plasma. A thick layer of silicon oxide may then be deposited on the sidewalls and bottom of the trenches, and the trenches may be filled with polysilicon. Portions of the polysilicon and thick silicon oxide that lie outside the trenches are then removed. Alternatively, the trenches can be filled with a thick layer of silicon oxide or other insulative material (e.g., polyimide). Either way, the trenches must be deep enough to extend through the P- type surface region 12 into the N+ type bulk substrate 10. In this manner, the isolation regions separate the substrate into discreet portions that can be independently biased. Thus, referring back to Fig. 7, the substrate portion upon which memory cells G, J and M are formed can be set at a first potential, while the remaining substrate portions are set at a second potential. In practice, any one of a number of known substrate bias circuits could be used to independently set the bias on the respective substrate portions. The outputs of these circuits are fed through contacts S1, S2, etc., to the individual substrate portions. The contacts are surrounded by the trenches so that adjacent portions of the substrate are not affected. The significance of this capability will be discussed in more detail below. Fig. 9 is a cross-sectional view taken along lines 9-9 of Fig. 7. Note again that adjacent memory cells share a common diffusion region. The operation of the array of memory cells as shown in Figs. 7-9 will now be described. To read data from one of the cells, the wordline 40A-40C associated with the desired cell is raised from 0 volts to +5 volts, and all of the drain lines 75A-75C are also raised from 0 volts to +5 volts. The source lines 70A-70C are held at 0 volts. The drain line voltage is monitored by any one of the known differential latch sense amplifier circuits utilized in one-device dynamic random access memory technology. If the silicon-rich silicon nitride layer 30 of the gate stack 50 of the accessed cell is storing charge, the channel region associated with that device will not be able to invert such that the device will not turn on and the drain line voltage will not change. The presence of stored charge indicates a "low" logic state. If the silicon-rich silicon nitride layer 30 of the gate stack 50 of the accessed cell is not storing charge, the high voltage on the control electrode 40 will cause the device to turn on, such that the coupled drain line 75A-75C loses a small amount of charge that is detected by the sense amp. The lack of stored charge indicates a "high" logic state. To write a "high" logic state into one of the cells, the wordline 40A-C associated with the desired cell is raised from 0 volts to +10 volts. All of the drain lines 75A-75C and source lines 70A-70C are raised to a potential of +5 volts except for the source line - drain line pair associated with the desired cell, which is kept at 0 volts. As a consequence, the gate stack 50 of the desired cell has a potential of +10 volts across it, which produces an electric field from the control electrode 40 to the substrate 12 that is sufficient to cause charge injection from the silicon-rich silicon nitride layer 30 through the charge injecting structure 35 to the control electrode 40. These control voltages are maintained long enough to allow complete depopulation of the charge traps in the Si-rich silicon nitride charge storage layer 30. A feature of the applied control voltages is that the maximum differential potential applied to an unselected cell is +5 volts, which is insufficient to cause detrapping of stored charge. To write a "low" logic state into one of the cells, the wordline 40A-40C associated with the desired cell is held at 0 volts, and the other wordlines are held at +5 volts. The unselected source lines 70A-70C and drain lines 75A-75C are raised to +5 volts, while the lines associated with the selected cell are allowed to float (i.e., they are not coupled to a source of potential). At the same time, the substrate portion within which the desired memory cell is formed is pumped up to +10 volts. The remaining substrate portions are retained at ground potential. Consequently, an electric field is provided from the substrate to the control electrode 40, such that charge will be injected from the control electrode through the charge injection structure, into the silicon-rich silicon nitride layer 30. Again, the applied control voltages supply a differential voltage of +5 volts to unselected cells, thus preventing undesired programming. Thus, as shown above, an individual cell may be overwritten with successive opposing logic states without erasing an entire line or array of cells. The above operations will now be illustrated by the following Examples, illustrating sequential operational cycles carried out on one of the memory cells in the array shown in Fig. 7. Example 1 - Write "O" Into Cell K Wordline 40B remains at 0 V, while wordlines 40A and 40C are raised to +5 V. Lines 70A, 75A and 70C, 75C are raised to +5V, while lines 70B, 75B are allowed to float. The substrate portion between isolation regions 100B and 100C is pumped up to +10V, while the remaining substrate portions are kept at 0 V. Thus the gate stack K has -10V across it, and electrons will be injected from the control electrode 40 into and trapped by the silicon-rich Si₃N₄ layer 30 of the gate stack 50 of cell K. Example 2 - Write "1" Into Cell K Wordline 40B is raised to +10V, while wordlines 40A and 40C remain at 0 V. Lines 70A, 75A and 70C, 75C are raised to +5V, while lines 70B, 75B remain at 0 V. The substrate is at ground potential. Thus the gate stack has +10V across it, and the charge trapped in Example 1 will be removed from the trapping layer 30 and injected into the control electrode 40 of the gate stack 50 of cell K. Example 3 - Read Cell K Wordline 40B is raised to +5V, while wordlines 40A, 40C remain at ground. The drain lines 75A-C are raised to +5V, and the source lines 70A-C remain at ground. Since the cell K is not storing any charge, the device will turn on and the sense amp will detect the slight fall in the drain line voltage. The above-described memory cell array present a host of advantages. By eliminating polysilicon as the charge trapping structure of an injector-type EEPROM, the memory cell of the invention can be scaled without concern for preserving capacitive ratios. By utilizing silicon-rich silicon nitride as the injector material, the manufacturable problems associated with silicon-rich SiO₂ may be greatly reduced. Finally, the use of trench-isolated substrate regions provides an overwriteable EEPROM cell that does not rely on high control voltages or large cell structures. While the memory cell of the invention is shown in Figs. 6-9 as being formed on an n+ substrate 10 having a p- epitaxial layer 12 thereon, in practice this would result in a larger capacitance for write "low" than a write "high." In Example 1, when the local substrate is biased to +10V, the diode at the bottom of the structure (p-n+) is forward biased allowing the n+p- capacitance of adjacent pockets to be seen. This difference in capacitance could be eliminated by several techniques resulting in improved write "low" performance and associated power saving if desired. One such technique would be a deep implanted n+ subcollector layer 14 as shown in Fig. 10. In addition a p+ implant above the n+ subcollector could be added if a lower substrate resistivity is desired. Such a p+ implant, while not requried, may also be beneficial from a device design perspective. Another technique, as shown in Fig. 11, consists of an isolation structure 16 below the silicon region 12. In practice, this structure could be provided by utilizing any one of a number of known silicon-on-insulator processes, e.g., see U.S.P. 4,601,779. While the memory cell and array have been described with reference to a particular embodiment, many modifications may be made. For example, if higher control voltages can be tolerated, the charge injector structure can be deleted from the gate stack. Moreover, if there is a concern that programming of unselected cells may occur during writing a "1" state into the desired cell, the structure shown in Fig. 12 can be used. Note that the charge storage - injection layers are disposed over one half the channel length. The remainder of the channel is covered by a conventional polysilicon-dielectric gate structure. Thus, even if an excessive amount of charge is removed, the resulting inversion region would only extend halfway into the channel region. The oxide spacers 45 would be formed after depositing and patterning 25, 30, and 35, and layer 40. Although the invention has been described with reference to control voltages in the 10-12 volt range, these control voltages may be reduced as the cell is further reduced in size consistent with device scaling. Finally, while Figs. 6-12 show the invention with reference to an EEPROM cell, the teachings of the invention could be applied to non-volatile DRAM cells, etc.

Claims: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes, said gate electrode (50) comprising a dielectric structure (20), a charge storage structure (30), a charge injection means (35), and a control electrode (40) for effecting charge transfer to and from said charge storage means (30) through said charge injection means (35), characterized in that said charge storage means (30) comprises a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage, without providing appreciable charge conductance, as compared to stoichiometric silicon nitride. A memory cell as recited in claim 1 further comprising: a barrier structure (25) disposed on said first silicon-rich silicon nitride layer (30), a second layer of silicon-rich silicon nitride disposed on said barrier structure, said second silicon-rich silicon nitride layer forming said charge injection means (35) and having an index of refraction of at least 2.35, said second silicon-rich silicon nitride layer having sufficient excess silicon to provide appreciable charge injection as compared to stoichiometric silicon nitride; and said control electrode (40) being disposed on said second layer of silicon-rich silicon nitride. The memory cell as recited in claim 2, wherein said first layer (30) of silicon-rich silicon nitride, said barrier structure (25), and said second layer (35) of silicon-rich silicon nitride are formed on only a first portion of said dielectric structure (50), and wherein said control electrode (40) is formed over both said second layer (35) of silicon-rich silicon nitride and remaining portions of said dielectric structure (20). The memory cell as recited in claims 1, 2 or 3, comprising first and second diffusion regions (60, 65) formed in said substrate (10, 12) abutting said gate electrode structure (50); first means for biasing said first diffusion region; and second means independent of said first means for biasing said second diffusion region. The memory cell as recited in claim 4, wherein said first means comprises a first metal line that contacts said first diffusion region through a first via formed in a passivation layer coated on the substrate, and wherein said second means comprises a second metal line that contacts said second diffusion region through a second via formed in a passivation layer coated on the substrate. The memory cell as recited in claims 1 to 5, wherein said dielectric structure (20) is comprised of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The memory cell as recited in claims 1 to 5, wherein said barrier structure (25) comprises a layer of thermally grown silicon oxide. The memory cell as recited in claims 1 to 5, wherein said control electrode (40) is comprised of a material selected from the group consisting of doped polysilicon, aluminum, aluminum alloys, refractory metals, refractory metal silicides, and combinations thereof. An array of memory cells as claimed in claims 1 to 8, comprising: isolation means formed in the substrate for defining discrete portions of the substrate that are isolated from remaining portions of the substrate; a plurality of cells being formed in each of said isolated discrete portions of the substrate, each of said cells comprising an FET having source and drain diffusions formed in the substrate and a gate electrode formed on a portion of the substrate between said source and drain diffusions; first means for biasing said source diffusions; second means for biasing said drain diffusions; and third means for biasing each of said isolated discrete portions of said substrate separately from others of said isolated discrete portions of said substrate. The array as recited in claim 9, wherein said first means for biasing comprises a first series of conductive lines coupled to a first series of voltage sources, respectively, each one of said first conductive lines being coupled to respective source diffusions of said cells formed in a respective one of said isolated discrete portion of said substrate. The array as recited in claim 9, wherein said second means for biasing comprises a second series of conductive lines coupled to a second series of voltage sources, respectively, each one of said second conductive lines being coupled to respective drain diffusions of said cells formed in a respective one of said isolated discrete portions of said substrate. The array as recited in claim 9, wherein said third means for biasing comprises respective substrate bias generators coupled to respective ones of said isolated discrete portions of said substrate.

Inventors: BASS ROY S JR, BHATTACHARYYA ARUP, GRISE GARY D, BASS, ROY S., JR., BHATTACHARYYA, ARUP, GRISE, GARY D.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H01L29
IPC codes: G11C16, H01L29, H01L27, H01L21