DECODING EQUALIZER

Abstract: Disclosed is a decoding equalizer of high definition television signal transmission mode, such as MUSE, and a subrange-type A/D converter suitable for the equalizer. The decoding equalizer samples input data in equalization at a frequency twice the sampling frequency of the trunk system, with the equalizing A/D conveter (1, 9) operating at a lower reduction and higher speed than the A/D converter (1,8) for the trunk system. The subrange-type A/D converter includes A/D converters in multiple stages (204, 212), with their driving clock frequencies being in certain relationship so that they are used commonly for the A/D conversion of the high definition television signal and the A/D conversion of a test signal for detecting the transmission character­ istics.

Description: This invention relates to a decoding equalizer for a sampled value transmission system of high definition television signal, such as MUSE (Multiple Sub-Nyquist Sampling Encoding) system. The conventional technique for equalizing the transmission path characteristics for the transmission of sampled values produced by offset sampling, such as in the MUSE system, employs standard receivers on the part of the receiver and implements pre-equalization by an encoder on the part of the transmitter so that the receivers have satisfactory reproduction characteristics. However, this technique fails in the achievement of effective pre-equalization if there exists the variability of characteristics among the standard receivers. Another problem is that it necessitates distinct equalization when supplying a signal to different information media such as a BS (broadcasting satellite) system and a 22 GHz ground system. In the technique of automatic equalization of transmission characteristics for the analog signal transmission of high definition television signal, in which a certain unit impulse signal is inserted as a test signal in the television signal and the characteristics of the transmission path is detected through the subsequent signal processing as disclosed in JP-A-62-172826, it necessitates an A/D converter of 16.2 MHz clock rate for the trunk system and an A/D converter of 32.4 MHz clock rate for the equalizing system. An object of this invention is to provide a decoding equalizer capable of equalizing an offset sampled signal to meet invariably satisfactory characteristics on the part of the receiver. Another object of this invention is to provide a decoding equalizer which is simple in circuit arrangement and easy in circuit design. These objects are achieved according to the invention by the features of claim 1. Fig. 1 is a block diagram showing the first embodiment of the inventive decoding equalizer; Fig. 2 is a block diagram showing the second embodiment of the inventive decoding equalizer; Fig. 3 is a flowchart showing the operation of the CPU shown in Figs. 1 and 2; Fig. 4 is a diagram explaining the sampling rate required for the equalization of MUSE system; Fig. 5 is a waveform diagram showing, as an example, the test signal; Figs. 6A and 6B are block diagrams showing, as examples, the arrangement of the equalizing filter. Embodiments of this invention will be described in detail with reference to the drawings. The embodiments will be described by taking an example of the MUSE transmission system developed for the high definition television signal, which is an analog signal transmission system for transmitting the analog signal obtained by offset sampling between frames, fields and lines. Fig. 1 is a block diagram showing an embodiment of the inventive decoding equalizer. In Fig. 1, indicated by 1 is an A/D converter which samples the input analog signal in MUSE system at a frequency of 32.4 MHz. 2 is a sub-sampling circuit which converts the output signal of the A/D ocnverter 1 into a signal of a trunk sampling clock rate of 16.2 MHz (or Ms/s: mega-samples per second). 3 is a delay circuit, and 4 is an adder. 5 is an equalizing filter with a variable tap, and is used to produce an equalization correction value. 6 is a VIT signal extraction circuit which extracts the VIT (Vertical Interval Test) signal with an impulse response waveform for measuring the distortion of the transmission path by being inserted in advance in the trunk system signal. 7 is a CPU which receives signal waveform data provided by the signal extraction circuit 6 and compares it with stored ideal waveform data to evaluate the distortion, and controls the variable tap of the equalizing filter 5 so that it produces the equalization correction value. The correction value is added to the trunk system signal by the adder 4, and the transmission characterictics of the transmission line are equalized. The trunk system of MUSE system has a sampling clock rate of 16.2 MHz, while the equalization system operates at a sampling clock rate of 32.4 MHz. Fig. 4 is a diagram explaining the sampling clock rate necessary for the equalization of MUSE mode. As shown in Fig. 4, sampling at 16.2 MHz with the intention of producing the 8.1 MHz roll-off characteristics (a) will result in a fold-over of the higher range above the cutoff frequency 8.1 MHz on the characteristics (b) as shown by hatching. This fold-over can be avoided by the sampling at 32.4 MHz which is twice the 16.2 MHz, and the sampling rate required for equalization is accomplished. Fig. 2 is a block diagram showing another embodiment of the inventive decoding equalizer. In Fig. 2, components identical to those of Fig. 1 are referred to by the same symbols, and their explanation will not be repeated. Indicated by 8 is an A/D converter which samples the input signal at 16.2 MHz, and its output signal is used for the trunk system. 9 is an A/D converter which samples the input signal at 32.4 MHz, and it is used as a circuit component of the equalization system. The arrangement shown in Fig. 2 allows the A/D converter 9 for the equalization system, which is formed as a branch path of the trunk system, to have a resolution of 6 bits at most. The equalization filter 5 is conceivably required to have the ability for processing a 6-bit signal at most, provided that it does not conduct a d.c. component. A problem seems to arise in the phase difference between the A/D converter 9 for the equalization system having a 6-bit resolution and the A/D converter 8 for the trunk system, but it is avoided completely through the adoption of the iterative correcting operation in the equalization system loop and by suppressing the phase difference below 1/5 of clock period. The above-mentioned iterative method enables equalization on the part of the decoder to have less equalization volume, and provides the characteristics of digital circuit after equalization that are deemed ideal, whereby the arrangement is simplified considerably. Fig. 3 is a flowchart showing the process carried out by the CPU shown in Figs. 1 and 2. In the flowchart of Fig. 3, step S1 reads data in the VIT signal by means of the VIT signal extraction circuit 6, and the data is delivered to the CPU 7. Step S2 subtracts the extracted data from data of ideal impulse response, which has been stored in advance in the CPU 7, to evaluate the error. Step S3 causes the variable-tapped equalizing filter 5 to have a center-tap coefficient equal to the sum of errors of other than the center tap. Step S4 multiplies -1 to the errors of these taps. Consequently, the equalizing filter 5 has a zero gain, and it does not make a d.c. variation in the trunk system. Step S5 multiplies α (α<1) to the error values for obviating the possibility of oscillation in the equalizing operation. Step S6 subtracts the error from the filter coefficient which has been evaluated previously. Step S7 sends the error data to the variable tap of equalizing filter to control the filter. At step S8, the above operations are repeated until the error value is smaller than the predetermined value β. The state of convergence is determined solely on the basis of the error of the 16.2 MHz data, as indicated in the step S8, i.e., the sampled value which is read originally as a signal of MUSE mode. The VIT signal will be described in more detail. Fig. 5 is a waveform diagram showing, as an example, the VIT signal of MUSE signal. Shown by (A) in Fig. 5 is the impulse response waveform for the n-th frame, while (B) is that for the n+1 th frame. The waveform of (A) has a peak (marked by x) at the center point M, and the amplitude of oscillation decreases progressively as the position goes right or left away from the M point. The response characteristics have zero-cross point at a constant interval on the horizontal axis as indicated by marks "x". The waveform of (B) has maximum values at two positions in the central portion in correspondence to the "x" positions of (A) and has peaks of amplitude for the remaining "x" positions, as indicated by marks "o". Accordingly, by combining the waveforms of (A) and (B) in Fig. 5, data which is sampled at 32.4 MHz is obtained. A signal with a completely equal waveform is reproduced if the transmission system has no distortion. The presence of distortion in the transmission system creates a distortion in the impulse response waveform and creates error in the values at the "x" and "o" positions. The VIT signal extraction circuit 6 in Figs. 1 and 2 supplies the impulse response waveform data to the CPU 7, which controls the equalizing filter 5 for the waveform equalization. By the way, in the embodiment shown in Fig. 2 for example for implementing the equalization on the part of the decoder, the following two points of practical problem must be overcome. (1) Conflict in equalization between the decoder and the encoder when it is carried out on the part of the encoder (2) Creation of flaw in the trunk system signal when loading data from CPU 7 into equalizing filter 5 As regards item (1), an iteration flag indicative of equalization in progress on the part of the encoder is provided so that the equalizing operation does not take place on the part of the decoder while it is in progress on the part of the encoder. As regards item (2), there are two possible methods. One is that two sets of equalizing filters 5 are prepared, with data being preloaded to the one unused for the trunk system, and the filters are switched such that the loaded equalizing filter is inserted in the trunk system. The other is that the output of the equalizing filter is made zero and equalization is inhibited while data is being loaded. Although the latter method involves a momentary period in which equalization is suspended during data loading, this does not cause the d.c. level to vary and therefore it is virtually unnoticeable. Figs. 6A and 6B are block diagrams showing, as an example, the arrangement of the variable-tap equalizing filter 5 shown in Figs. 1 and 2. The circuits of both figures in unison form a single circuit by being connected through terminals 1 ○ to 7 ○ . In Figs. 6A and 6B, indicated by 101 is an input terminal and 102 is a line receiver. 103-106, 113, 114, 131-146, 154 and 157 are flip-flops each used to delay the signal by one 32 MHz clock period. 107-110 and 123-130 are 3-state buffers, providing the output of "0", "1" or "open". 111 and 112 are delay circuits used to delay the signal by three 16 MHz clock periods. 115-122 are 11-bit RAMs, 147-153 and 156 are adders, and 155 is a delay circuit for delaying the signal by n 16 MHz clock periods (n ≦ 128). 158 is an AND gate and 159 is an output terminal. 160 is a counter which generates the write address for the RAMs 115-122. The RAMs, 3-state buffers, flip-flops and adders are combined in groups, e.g., 121, 129, 137, 145 and 151, and connected in series to form a basic structure of a variable-tap equalizing filter as the whole. The filtering characteristics are determined by the coefficients of the RAMs 118-122, and the variable-tap filter has its characteristics variable by changing the RAM coefficients with the CPU 7. Through the retardation for one 32 MHz clock period by the flip-flop 104 in Fig. 6A, taps T2, T4, T6, T8, T10, T12, T14 and T16 on the upper section are separated from taps T1, T3, T5, T9. T11, T13 and T15 on the lower section, and they operate at a 16 MHz clock. The delay circuit 155 and adder 156 are combined to produce a delay of n 16 MHz clock periods (n ≦ 128), and the timing relation between the trunk system and equalizing filter system can be adjusted. Namely, the CPU 7 controls such that the center tap (T8 or T9) of the filter is placed at the point where the VIT signal waveform has a maximum ringing. The counter 150 generates the address for loading data from the CPU 7 into the RAMs 115-122. When the CPU 7 is loading data into the RAMs, the AND gate 158 produces a low output to invalidate the outout of the equalizing filter 5, and equalization for the trunk system is inhibited temporarily. As described above, the equalizing filter of this embodiment has less number of bits (6 bits) for the input, and therefore it is relatively simple. A 11-bit RAM is used for two taps, and the filter having a total of 16 taps is formed. Taps dealing with the central portion of the VIT signal have 6-bit inputs, while taps for the remote portions have 5-bit inputs. In this embodiment, it is possible to choose the tap positions for the central portion of the equalizing filter, allowing the use by setting the tap position to be corrected.

Claims: A decoding equalizer used for a transmission system, said transmission system comprising: a sampling means for sampling a high definition analog video signal at a first sampling frequency, a transmitter to transmit a sampled value signal and a test signal which is time-multiplexed in the sampled value signal for detecting the transmission characteristics of a transmission path, a receiver to receive the sampled value signal and the test signal, a decoder to decode the sampled value signal, and an equalizer to equalize the transmission characteristics of the transmission path using said test signal; the decoding equalizer characterized by first sampling means which samples the received sampled value signal at a second sampling frequency twice the first sampling frequency, an A/D converter (1, 9) connected to the first sampling means, second sampling means (2, 8) which samples the received sampled value signal at the first sampling frequency, equalizing filter means (5) providing tapped sections for equalizing the transmission characteristics of the transmission path, adding means (4) for adding a delayed version of the output signal of said second sampling means (2, 8) to the output signal of said filter means (5), a vertical interval test signal extracting circuit (6) for extracting said time-multiplexed test signal from the output signal of said adding means (4), and a CPU (7) which receives data pertinent to the test signal provided by said extracting circuit (6), calculates the error caused in the transmission path by subtracting the extracted data from data of an ideal impulse response, which has been stored in advance in the CPU (7), determines respective taps of said filter means (5) based on the calculated error caused in the transmission path, and repeats the operations of data reception, error calculation and determination of respective filter taps until the error in the transmission path becomes smaller than a predetermined value. A decoding equalizer according to claim 1, wherein the second sampling means (2) is formed as a subsampling circuit and located at the following stage of the first sampling means (1). A decoding equalizer according to claim 1, wherein the first sampling means (9) and the second sampling means (8) are arranged in parallel. A decoding equalizer according to claim 1, wherein the filter means (5) does not conduct a d.c. component. A decoding equalizer according to claim 1, wherein the second sampling means (2, 8) and the filter means (5) are supplied with sampled value data of the same resolution, the filter means (5) neglecting a low-order bit of the sampled value data. A decoding equalizer according to claim 1, wherein data provided by the first sampling means has a less number of bits than data provided by the second sampling means (2, 8). A decoding equalizer according to claim 1, wherein the output signal of said equalizing filter means (5) is zero during its adjustment for equalization the transmission characteristics. A decoding equalizer according to claim 1, wherein the filter means (5) comprises two sets of filter means, which are used alternately by switching such that while one of the filter means is in filtering operation, the other is loaded with data. A decoding equalizer according to claim 1. wherein the equalizing operation on the part of the decoder is stopped by setting an iteration flag, indicating that equalization on the part of the decoder is under way.

Inventors: IWADATE, YUICHI, NINOMIYA, YUICHI
Applicants: NIPPON HOSO KYOKAI
Application year: 1988
Main classification: H04N7
IPC codes: H04N5, H04N7