Data processing system with means for contiguously addressing memory

Abstract: A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.

Description: This invention relates in general data processing systems including memory systems which employ replaceable memory modules and, in particular, to automatically assigning a plurality of memory modules which can have different predetermined address capacities to contiguous segments of a the address range. The prior art discloses various memory arrangements for storing data in an information handling system. In general, these memory arrangements include a memory controller function and a plurality of memory modules which are manufactured in the form of semiconductor chips having a predetermined number of memory cells. The chips are often referred to as RAM memory, Random Access Memory, in that each storage location is directly addressable as distinguished from other type of memory devices such as magnetic tape where a number of storage locations must be scanned before reaching the desired addressed location. The number of addressable storage locations on a RAM chip is determined by the physical size of the chip and the size of each individual memory cell with some consideration for the area needed for various signal paths. The physical size of chips has been constrained more by de facto industry standards than by technology. Increases in storage capacity, however, have occurred quite rapidly over the years, primarily due to improved semiconductor material and manufacturing process techniques. RAM memory chips or modules are currently being produced and marketed in three popular capacities, 64K, 256K, and 1 Meg. Many older personal computers still in use employ RAM memory chips of 16K and 32K capacities while 2 Meg and 4 Meg capacities are available in limited supply for prototype development. A 64K memory chip, for example, has 2 to the power 16 addressable storage locations. Each storage location contains one memory cell and can store one binary bit. In most data processing systems, data is handled in "bytes" each of which consist of eight data bits and one parity bit. Data is transferred throughout the system serial by byte on a data bus consisting of eight data lines and one parity line. In such a system, a memory bank would include nine chips or modules which store 64K bytes of data at 64K addressable storage locations. Any type of binary data may be stored in RAM memory, i.e., it may be an operating system program, an application program or user data. The transfer of data to and from the memory involves first addressing a specific location and second, writing a byte of data or reading a byte of data from the addressed location at a particular clock time of the memory cycle. Therefore, in addition to address lines, a number of control lines are associated with each cell. The address range of the computing system and, in turn, its maximum memory capacity is determined primarily by the the number of address lines that are provided in the system architecture. An address range of 0-64K requires 2 to the power 16 permutations of 16 binary bits. A 16 bit address is therefore needed and a 16 bit address bus must be provided if a 64K system memory is desired. Increasing the address bus by one line effectively doubles the previous range or capacity of the system. As shown in the following table, for every address line added to the address bus, the available addressable locations double. It should be noted that memory capacity is not the same as address range. Memory capacity is generally expressed as byte capacity such as a 1 megabyte memory. Since some memory banks store two bytes or four bytes at an addressable location, the address range and memory capacity are only the same if the memory stores one byte of data per location. Since a reasonable amount of increase in memory chip capacity is always anticipated by the system designer, many new systems are provided with more address lines than are necessary to support the current need. Also, since at any one time, three or four different capacity memory chips are available, the designer needs to provide some way to increase memory capacity above what might be marketed as a minimum system capacity. Since the chips are replaceable easily, the user may purchase a system with minimal memory and add additional memory at a later time. If the system is designed so that only one type of memory chip may be added to the remaining empty memory banks, the problem of advising the system of the available memory installed is straightforward, provided the added memory is inserted in the correct memory banks. If not, a "hole" would exist in the address range which the operating system of the microprocessor cannot tolerate. If the system is designed to accommodate memory chips of varying different capacities such as 64K, 256K and 1 Meg, then the problem of identifying what capacity modules are in each bank becomes somewhat more complicated. For example, assume the system is designed with a memory address range of 0 to 4 megabytes or 2 to the power 22 addressable storage locations that encompass four separate memory banks. The minimum memory capacity would be 64K bytes obtained by one bank of nine 64K modules. As the three empty banks are filled with modules, the system must be capable of identifying what capacity modules have been installed in what bank in order to select the correct memory bank and to gate the correct number of address lines to that bank, since a 64K module needs 16 lines, a 256K module needs 18 lines, and a 1 Meg module need 20 address lines. In addition to selecting the correct number of lines, the addresses of the memory banks in the overall range must be contiguous. Thus, if all four banks had 64K modules and the first bank of 64K modules were replaced with 256K modules, the previous addressing line assignments to the other three banks would have to be altered. The prior art has disclosed a number of memory system organizations which employ replaceable memory modules. These systems were faced with the problem of assigning memory banks to form a linear address range without any holes. In these systems, the memory address range was predetermined since the number of memory banks was set and only one memory module of one capacity was available. Systems were subsequently developed that could detect a faulty module or memory bank and either reconfigure the remaining good modules to avoid any gaps in the address range or insert a spare module in place of the faulty module. These systems employed both manual and automatic arrangements in which the address range was divided into equal segments, each having a range corresponding to the number of address storage locations in each module or bank. Since the address capacity of all range segments and modules were the same and pre-established, the reconfiguration process was relatively straightforward and simple to implement, either on a manual basis or on an automatic basis. The U.S. Patent 3,803,560 shows a typical example of a memory system employing an automatic reconfiguration process for memory modules of the same capacity when one of those modules failed. A memory system which employs modules of different sizes is disclosed in U.S. 3,813,652. The address transformation system translates an input address into a set of memory module select signals and a set of address signals. The individual modules which may have different capacities supply size type signals to hardware type adders which produce sets of composite size signals. These composite size signals are processed mathematically by hardware comparators supplied with the high order address signals in true and complimented form and by subtracters to develop a transformed address. The system requires serial processing of signals which increases processing time as the number of modules is increased in addition to requiring a relatively large number of complex circuit structures. Systems have been developed which permit replacement of the original modules with different capacity modules, but these systems require the user to reset several switches, which basically set the address range assigned to each memory bank. This provides greater flexibility in the use of memory modules, but is subject to error. Some systems employ a program to effectively set switches which may be more convenient, but is also subject to introduction of the wrong information and, as module sizes change, requires reprogramming. U.S. re-issue Patent 31,318 does disclose a memory system which can accommodate memory modules of different sizes and can automatically adjust the assignment of these modules to provide a linear address range when a module is replaced with a module of a different capacity. In that system each module has a signal source which indicates the capacity of the module. A hardware adder is also associated with each memory module. One input to the adder is from the capacity signal source of the memory module. The other input to the adder is from the output of the adder of the previous memory module. The output of the adder of the instant module is feed to one input of the adder of the succeeding memory module. The output of each adder represents the cumulative capacity of all modules up to that point in the sequence. Each module has a range detector which sets the address range for the module from the input of the previous module and the output of the adder. The range detector employs two hardware comparators. One comparator determines if the input address is above the beginning address of the module and the second comparator determines if the input address is below the ending address of the module. If the comparators provide a true output, the module is selected. While the above system operates satisfactorily, the nature of the mathematical operations, and the comparison of the input address by the range detectors requires a relatively long memory cycle in order for signals to propagate through the comparator logic and indicate a selection of the correct memory bank. In addition, the adder circuits require additional pins on the memory modules and the high order bit processing becomes quite complex. US-A-4281392 discloses a memory circuit which receives memory modules which may vary in their size and their type. The memory circuit includes a decoder circuit which connects to selected leads in the address bus and which connects to size feedback lines that connect to the memory modules and which indicate to the decoder circuit the size of the memory modules being used. The decoder circuit is responsive to signals on the address bus to provide signals which enable the memory modules in such manner that they occupy a contiguous address space regardless of the size of the memory devices employed in them. US-A- 4234934 discloses a memory module which scales the address received to a smaller size depending on the capacity of the memory itself. The memory module knows its own capacity and utilizes this information to strip off the upper address bits of the address supplied to the memory to scale the address down to the size needed to address the populated memory locations. It is an object of the present invention to provide a memory system which may employ a plurality of different capacity modules which are assigned to the correct segment of the system address range automatically by logic cells. According to the invention, there is provided a digital data processing system including a memory address bus and an addressing system for addressing a memory means in response to address signals on said address bus, said memory means comprising a plurality of memory banks each for receiving one or more memory modules having up to a predetermined fixed capacity of memory, or no module, characterised in that: (i) a module capacity logic is associated with the banks for generating capacity signals indicating the memory capacity, including zero, of the module or modules currently held in each bank; (ii) the maximum address range of the memory means is divided into 2 H consecutive fixed size segments, whereby each segment has a size corresponding to a minimum capacity module; and (iii) said addressing system includes a segment decoder responsive to H higher order bits of said address signals to select one of 2 H segment lines corresponding to said consecutive fixed size segments into which the maximum address range is divided, and a segment selector logic for automatically assigning segment lines to the respective banks in accordance with said capacity signals, said segment selector logic comprising an interconnected plurality of logic cells arranged in a matrix of columns and rows, wherein the cells in each one of said columns are coupled to receive capacity signals of the capacity of a specific one of said banks from said module capacity logic and the cells of each one of said rows are coupled to receive segment signals associated with particular segment lines from said segment decoder, each cell including a combinatorial logic for determining whether to assign said particular segment lines to a particular memory bank in dependence on said capacity signals, for logically passing to each subsequent cell in the column a signal representing the remaining capacity of the particular memory bank, and for logically passing signals along the row indicating whether said particular segment lines have been assigned to provide a corresponding output segment signal, thereby to automatically provide, in combination with low order address bits of said address signals, contiguous addressing for the memory irrespective of the capacity of the memory modules in each of said banks. In a preferred embodiment of the invention, to be described in detail later, a, memory system includes four memory banks where each memory bank has an array of single bit memory modules, e.g., nine modules that are of the same capacity, e.g., 256K. Each bank accepts either a 256K module or a 1 Meg module so that the minimum memory configuration for the system is 256K, while the maximum memory configuration is 4 Megs. The address bus includes 22 lines, 20 of which address each memory bank simultaneously. The high order address lines H, 22-19 are used to select the correct bank. A H-to-2 to the power H (4-16) decoder or converter is provided in which 2 to the power H is equal to the number of segments in the maximum address range, where each segment has a size corresponding to a minimum capacity module. Under the previous assumption of four memory banks and module capacities of 256K and 1 Meg, a 4-16 decoder is provided. The number 4 is determined by the number of high order address bits required to select the 16 segments into which the maximum address range is divided. The input to the segment decoder is the four higher order address bits which are converted to 16 segment lines that are supplied to the segment selector logic arrangement. The function of the selector logic is to assign the sequential segment lines 1-16 to the respective banks in accordance with signals received from each installed module indicating the capacity of the array of memory modules in that bank. If, for example, memory banks 1 and 2 each have memory modules of 256K capacity and banks 3 and 4 have memory modules of 1 Meg capacity, the 2.5 Meg system address range is assigned as follows. Since each segment line involves 256K addresses, the low order address requires 18 address lines to create 2 to the power 18 permutations to address one 256K module. The four high order address bits permit selecting one of 16 segments, resulting in an address bus of 22 lines for addressing the maximum memory capacity. The segment selector logic comprises a matrix of substantially identical logic cells arranged in columns and rows. The columns of the matrix correspond to banks, while the rows are associated with segment lines. The function of the cells is to decide if a segment line should be selected, depending on the size signal of the module currently assigned to the bank. If the size signal is 0, the first segment line is not taken by the first cell and the cell effectively transfers segment line 1 to the first cell in column 2 associated with bank 2. If the size input is 1, indicating a 256 K module, the first cell selects segment 1 and outputs a Taken signal to cell 1 in column 2 indicating that the line is taken. The Taken signal is effectively propagated through cells in columns 2, 3 and 4. Cell 1 in column 1 further functions to supply to cell 2 in row 2, column 1, a module size signal indicating the amount of storage capacity remaining in the module after segment 1 has been assigned. Since the bank then has no unassigned capacity, a 0 size signal is supplied to cell 2 in the column and then propagated to cells 3 and 4. Segment lines 2,3 and 4 are therefore passed through to column 2. If instead an initial size signal of 4, indicating a 1 Meg module had been applied to cell 1 in column 1, the size signal supplied to each of the cells 2,3 and 4 in column 1 would have been reduced by 1 by each cell. In addition cell 2,3 and 4 would select segment lines 2,3 and 4 respectively. The logic in each cell is substantially identical except the cells in the first bank do not require inputs from a previous cell indicating that a segment line has been taken by the previous cell. The various output signals are developed through processing the input signals with combinatorial logic that produces the correct output for various input signals. The embodiment of the invention will now be detailed, by way of example, with reference to the accompanying drawings, in which: Fig. 1 illustrates the relationship of a microprocessor to the memory system and other I/O devices in the typical data processing system; Fig. 2 illustrates in block diagram form, the memory bank selector control logic which is employed advantageously in the memory controller shown in Fig. 1; Fig. 3 illustrates in detail the logic of the module capacity logic block shown in Fig. 2; Fig. 4 illustrates in detail the cell relationships of the four cell stage one decoder shown in Fig. 2; Fig. 5 illustrates in detail the cell relationships of the four cell stage two decoder shown in Fig. 2; Fig. 6 illustrates one of the combinatorial logic cells of Fig. 4 in detail; Fig. 7 illustrates one of the stage two cells shown in Fig. 5 in detail; Fig. 8 illustrates a modification of the low order addressing operation to accommodate the use of dynamic RAMS in the memory blocks shown in Fig. 1; Figs. 9A and 9B illustrate the logic for developing bank selection/control signals for the dynamic RAMS; Fig 10 illustrates 1 dynamic memory module with the RAS and CAS inputs; and Fig 11 shows the basic memory bank selection logic controlled by the Fig 2 control logic. Fig. 1 is a functional block diagram of a typical data processing system in which the present invention may be advantageously employed. As shown, the system comprises a microprocessor 10, a memory controller 12 and 4 memory banks 14A-14D. The memory controller 12 is interconnected to the microprocessor 10 by a data bus 16, an address bus 18 and a control bus 20. As is conventional, other units (not shown) such as a printer, storage and tape file units, and a display may also be connected to bus 16, 18 and 20 or directly to the microprocessor. Each of the 4 memory banks 14A-14D may consist of nine separate sockets mounted on a printed circuit board. Each socket is adapted to receive a memory module that has a predetermined address capacity. The term "address capacity" is used to describe the total number of addressable locations for the module. A memory module referred to in the art as a 64K memory module, has a nominal 64K individual storage locations, each of which can store one binary bit. It assumed that the system shown in Fig. 1 transfers and stores data in memory as nine bit bytes comprising eight data bits and one parity bit. If the system employs 32 data bits, then each memory bank would consist of 32, 64K modules for data and 4, 64K modules for parity bits. The address capacity is still a nominal 64K, but total storage capacity of the memory bank in terms of bytes would be a nominal 256K bytes. A brief review of the various numerical relationships that will be discussed in connection with the description of the memory addressing arrangement that follows is appropriate. A nominal 64K module actually has 65,136 individual storage locations. It takes 16 binary bits to define 65,136 different 16 bit permutations, each of which corresponds to one address location of a 64K module. The maximum number of storage locations for a data processing system is determined by the number of address lines in the address bus of the system. A nominal 4 Meg memory system requires 22 address lines. It can be assumed for the purpose of this description that address bus 18 shown in Fig. 1 consists of 24 address lines and, hence, the maximum address capability of the system shown in Fig. 1 is 8 megabytes. However since there are only 4 memory banks and the maximum module size is 1 Meg. only 22 lines are used. It should also be assumed that each bank 14-A through 14-D is supplied with 20 address lines so that a 1 megabyte memory module is the maximum permissible capacity under these assumptions for each bank. For purposes of illustration, it will also be assumed that the minimum capacity memory module to be employed is a nominal 256K module which requires 18 address lines. The lower order 20 bits of a 22 bit system address are referred to as the low order address bits of the memory, while bits 22-19 are referred to as the higher order address bits. Bits 19 and 20 serve a dual purpose. With the above assumption in mind, it will be seen that the system of Fig. 1 can operate with the minimum system address range of 0-256K, or a maximum system address range of 0-4 megabytes. The system will also operate at modulo 256K capacities in between. The specific capacity will depend on the mix of the memory modules in the four banks. The manner in which the contiguous 256K segments of the system address range are assigned to the banks 14A-14D for the various mix of capacity modules will now be described in connection with Fig. 2. The memory bank selector control logic 26 shown in Fig. 2 comprises an H by 2 to the power H signal converter 28. In the embodiment shown, a 4 x 16 convertor is depicted in block form without any detail since any prior art converter that can perform this function may be employed for the block 28. The selection of the numbers 4 and 16 is based on the number of higher order address bits H, the maximum memory capacity, and the minimum capacity selected for the modules such that the maximum memory capacity is equal to 2 to the power times the minimum capacity. The logic of Fig. 2 further includes the module capacity logic block 30. The function of block 30 is to provide a signal indicative of the capacity of the modules in each memory bank. The details of block 30 are shown in Fig. 3. In the preferred embodiment, the memory modules in memory banks 14A-14D are equipped to provide this data automatically in any suitable prior art arrangement, for example, one in which each memory module supplies two bits representing it's size. In such a system a 1 Meg. module supplies a "00" output, a 256K module supplies a "01" OUTPUT, a 512K supplies a "10" output, and no plugged in module results in a "11" output. The specification of these two bits would come from the manufacturer of the memory modules. At system initialization, either at power up, or during a reset, these bits are loaded into an internal register, called the type register, which supplies the ty reg bits 0 to 7 shown in Fig. 3. Here, bits 0 and 1 indicate the capacity of memory bank 1, bits 2 and 3, bank 2, bits 4 and 5, bank 3, and bits 6 and 7, bank 4. In Fig. 3, the more conventional memory bank labelling of 0 to 3 is used to indicate the Fig. 1 banks 1 to 4. The logic for all the banks is identical, so a discussion of that shown at the bottom of Fig 1, measure bank will suffice. The output lines for this logic are BANK 0 TY (0) and TY (2), which represent, respectively, a 256K and a 1 Meg. module. As indicated above a 256K module will place a "0" bit on the BIT 0 input and a "1" bit on the BIT 1 input resulting in a "0" output from the inverter and a "1" output from the NOR gate. Similarly, a "00" input representing a 1 MEG. module will result in a "1" output from the inverter and a "0" output from the NOR gate. A "11" input will generate a "00" output from this circuit. What this means is that a "1" output on the TY (0) line indicates a 256K module and a "1" output on the TY (2) line indicates a 1 Meg. module. It is clear that the circuitry could be expanded to include a TY (1) output line on which a "1" signal indicates a 512K module, but this is not shown as, for simplicity, the present embodiment does not use such a memory module. The logic of Fig. 2 also includes a plurality of first stage segment line selection logic blocks 32 and a second plurality of second stage segment line selection logic blocks 34. Logic blocks 32 and 34 are substantially identical from a functional standpoint in that they develop Bank selection signals from selected input signals. Their differences will be discussed in connection with Figs. 4 and 6 which illustrate the detail logic. As shown in Fig. 4, a first stage block consists of four separate decoders cells 32-1 to 32-4. Each cell has two inputs. Cell 32-1 has one input connected to receive segment line 1 of translator 28. Cells 32-2 to 32-4 each have an input connected to receive segment lines 2-4 respectively of translator 28. The other input to cell 32-1 is connected to the output of the module capacity logic 30 of Fig. 2 and receives a 3 bit signal indicating the module capacity for the module in bank one. In the preferred embodiment, three size signals are developed; a 0 signal indicating that no modules are installed, a 1 signal indicating a 256K module is installed, and a 4 signal indicating that a 1 Meg module is installed. The function of cell in 32-1A is to first develop by combinatorial logic, two output signals to indicate if the segment line is selected by this cell or not. The second function is to provide a signal to cell 32-2 in row 2 which in effect indicates if any capacity is left in the module installed in bank 1. If a module is installed in bank 1, the capacity signal is either 1 or 4. The logic, therefore, indicates that segment one is taken and the valid line selects bank one. If a 1 MEG. module is installed, the logic supplies a 0 value signal to stage 32-2, indicating that all the address range of bank one has been assigned. If, on the other hand, a 256K module is installed, the logic supplies a 3 size signal to stage 32-2, indicating there are 3 more segments of memory in bank 14A to be assigned. Cell 32-2 selects segment line 2 and passes a value of 2 to cell 32-3. Cell 32-3 selects segment 3 and passes a value of 1 to cell 32-4, which selects the segment 4 line. The Valid lines designated VI1, VI2, VI3 and VI4 are activated if a 1 Meg module is installed. Output line VI1 is active if a 256K module is installed. If the Valid line is active, the associated Taken line TI is inactive. If the Valid line is inactive, the Taken line is active, indicating that the segment line is available for the next memory bank. Fig. 5 shows the arrangement of the four cells 34-1 through 34-4 of a stage 2 decoder 34. The function of a stage 2 cell is substantially identical to the stage 1 cell. Cell 34-1 has three inputs, the VI1 and the TI1 signals from cell 32-1 plus the input from the capacity logic 30 of Fig. 2. The output of cell 34-2 is identical to 32-1 in that Valid, Taken, and size signals are developed by the combinatorial logic employing the same basic algorithms of the stage 1 cells. If segment line 1 was not taken by stage 1, i.e., no modules are installed in bank 14A, then cell 34-1 for bank 14B selects segment line 1 when a 256K module is installed. If a 1 Meg module is installed, then stage 2 cells 34-1 through 34-4 select segment lines 1-4 in the same manner as described in connection with stage 1. The negative AND gate logic in Fig. 4 consists of negative AND gates 36-1 to 36-5 which develop the bank select signals which are used to select one memory bank for the read and write memory operation at the 20 bit low order address signal supplied to banks 14A-14D. The specific combinatorial logic arrangement for a stage 1 cell such as 32-1 is shown in Fig. 6. This includes BANK TYPE (0), TYPE (1) and TYPE (2) input lines from Fig. 3. It will be recalled that Fig. 3 did not show the TYPE (1) output line, on which a "1" signal represented a 512K module, but this line is shown in Fig. 6 for completeness. Without 512K modules in the system, this line will always carry a"0" bit. The Fig. 6 logic comprises three inverters 40-42, a pair of negative AND gates 43-44, three negative OR gates 45-47, a negative AND gate 48 and an inverter 49. The truth table for the logic is as follows. The size signals to inverters 40-42 indicating that either a 1 Meg module, a 256K module or no modules respectively are installed, are translated by inverters 40-42 and NAND gates 43 and 45 and NOR gates 45-46 to a select Type 1 signal or a select Type 0 signal. The output of NOR gate 47 will indicate that the segment line is taken by the cell and the signal to inverter 42 is not active. Negative AND gate 48 and inverter 49 produce the Valid signal, signalling that bank 14A is to be selected. The combinatorial logic for a stage 2 logic cell 34-1 is shown in Fig. 7. The logic added to the stage 2 cell 34 involves the function of converting the capacity size signals TY1-(2), TY1-(1) and TY1-(0) from Fig. 3, remembering that in the present embodiment, TYI (1) will always be "0", to signals which indicate to the remaining cells in the bank whether the cell should select its segment line. If the module still has some unassigned address capacity, the output of negative AND gates 70, 71 and 72 forward the capacity information to the following cell in the same column. The selection of one or more of the memory banks in Fig. 1 is achieved by the bank select logic of Fig. 11 in response to outputs from the Fig. 2 control logic. These outputs comprise the select outputs BS1 (Bank Select 1) from Fig. 4, and the BANK2, BANK 3 and BANK 4 outputs from selection logic blocks 32, shown in more detail in Fig. 4 as the outputs of negative AND gate 36-5, together with the select outputs 21, 31, 35, 41, 45, and 49 from selection decoder. Bank 1 is selected directly by the BANK SELECT 1 output from logic block 32 1A in Fig. 2. Bank 2 is selected by the NOR combination of output 21 from block 34 1B and the inverse of the BANK 2 output of block 32 2B. Similarly , memory bank 3 is selected by the NOR combination of the inverted BANK 3 and the 31 and 35 outputs of the Fig. 2 logic, and bank 4 by the combination of outputs 41, 45, and 49, together with the inverted BANK 4 output of Fig. 2. The overall operation of the segment line selection arrangement of Fig. 2 will now be detailed. The segment selection logic blocks 32 or 34, select 1 of the 4 possible segment lines depending on the capacity information supplied specifying the type (i.e., size) of the module installed in the associated memory bank. Under the previous assumptions of 256K and 1 Meg size modules, the blocks will select 1 or 4 of the segment lines. If 1 or 4 lines is selected, the block provides a Bank 1 select signal. If no line is selected, than the bank is empty and the 4 segment lines are effectively passed through to cell block 34 associated with bank 2. If bank 2, 14B in Fig 1 has a type one module, i.e., 256K installed, then segment line 1 is selected and segment lines 2, 3 and 4 are effectively passed to block 34 in column 3, which is associated with bank 14C. Bank select line 21 causes bank 14B to be selected for the segment 1 line. Assuming bank three has a 1 Meg module, then lines 2, 3 and 4 will be selected by bank 3 and bank select line 3-1 is activated. Since all four segment lines 1-4 have been selected, 1 by block 34-1b and three by a block 34-1c, block 34-1d is never given the opportunity to select any of the segment lines. 1-4. However, since bank 14C contains a 1 Meg module, it has the capability of supporting one more segment line. That selection is achieved by block 34-2c. The fact that bank 14C still has a 256K segment unassigned was indicated by block 34-1c, transferring the type 1 size signal to block 34-2c which allowed the first cell 32-5 to select segment line 5 since all four segment lines, 5-8, were passed through the logic of block 32-2b. This occurred because bank 14B had used up all of its capacity when signal line 1 was selected by cell 34-1b. Since block 32-2B received a type 0 size signal lines 5-8 were passed through to block 34-2C. A Bank 3 select signal is developed by blocks 34-1C and 34-2C. Since memory bank 3 has no further capacity, block 34-2c does two things; first, it advises block 32-3c by sending a type 0 size signal so that bank 3 does not select any more lines. Block 32-3c therefore effectively passes segment lines 9-12 to block 34-3d associated with bank 4. Simultaneously, segment lines 6-8 are passed to block 34-2D from block 32-3D. On the assumption that bank 4 has a 1 Meg module, segment lines 6, 7, and 8 are selected by block 34-2d. A Bank 4 select signal is developed by block 34-2d to select segment 6, 7 and 8 by bank 14D. In addition, a type 1 size signal is developed by the logic of 34-2d since a type 4 size signal was supplied by block 34-1d. Block 34-3d selects segment line 9 and also provides a Bank 4 select signal, indicating that segment line 9 is assigned to bank 4. No further signal lines are selected by block 34-3d or block 32-4d. By converting the 4 high order bits,22-19, to 16 separate signal lines, one of four memory banks is selected to perform a memory operation in the modules installed in that bank. The segment assignment logic allows modules of different capacities to be used in any bank and in any combination including leaving the banks empty. In the event dynamic memory modules are employed rather than static memory modules, a slight modification of the system occurs due to the fact that dynamic RAM modules, DRAMS, require extra control lines for supplying a Row Address Select (RAS) signal and a Column Address Select (CAS) signal to the module. Also DRAMS are addressed by multiplexing the row address lines and the column address lines to a set of common pins on the memory bank. If the memory bank is able to support DRAM modules of different capacities, then a different group of address lines must be available for each module type and multiplexed into the bank Fig 8 illustrates a set of logic for controlling a multiplexor 80 on the assumption that the banks can support a 256K DRAM module and a 1 Meg. DRAM module. Since a 256K DRAM module requires 18 address lines, 9 of which are connected to the bank at any one time, lines 1-9 and 10-18 are alternately connected to the bank. However, a 1 Meg. module requires 20 address lines, 10 of which are connected to the bank at any one time. Thus lines 1-10 and 11-18 are connected alternately to the bank at any one time. Address line 10 is therefore switched between the different groups depending on which Dram module is installed in the bank. The multiplexors 80 and 81 are under the control of the negative OR gates 82-86 of Fig 8. Gates 82-84 receive size signals from each bank in the same manner described in connection with Fig 1. Fig 10 illustrates the RAS and the CAS input terminal of a DRAM module. Fig 9 illustrates the gating Bank select signals by a RAS and CAS strobe signal to develop the RAS1- RAS4 and CAS1-CAS4 signals. RAS1 and CAS1 lines are connected respectively to the RAS and CAS input terminals of the modules installed in bank 1(14A). the remaining lines are similarly connected to input terminals of the modules in banks 2, 3 and 4.

Claims: A digital data processing system including a memory address bus (18) and an addressing system (12) for addressing a memory means (14A - 14D) in response to address signals on said address bus, said memory means comprising a plurality of memory banks each for receiving one or more memory modules having up to a predetermined fixed capacity of memory, or no module, characterized in that: (i) a module capacity logic (30) is associated with the banks for generating capacity signals indicating the memory capacity, including zero, of the module or modules currently held in each bank; (ii) the maximum address range of the memory means is divided into 2 H consecutive fixed size segments, whereby each segment has a size corresponding to a minimum capacity module; and (iii) said addressing system includes a segment decoder (28) responsive to H higher order bits of said address signals to select one of 2 H segment lines corresponding to said consecutive fixed size segments into which the maximum address range is divided, and a segment selector logic for automatically assigning segment lines to the respective banks in accordance with said capacity signals, said segment selector logic comprising an interconnected plurality of logic cells arranged in a matrix of columns and rows, wherein the cells in each one of said columns are coupled to receive capacity signals of the capacity of a specific one of said banks from said module capacity logic and the cells of each one of said rows are coupled to receive segment signals associated with particular segment lines from said segment decoder, each cell including a combinatorial logic for determining whether to assign said particular segment lines to a particular memory bank in dependence on said capacity signals, for logically passing to each subsequent cell in the column a signal representing the remaining capacity of the particular memory bank, and for logically passing signals along the row indicating whether said particular segment lines have been assigned to provide a corresponding output segment signal, thereby to automatically provide, in combination with low order address bits of said address signals, contiguous addressing for the memory irrespective of the capacity of the memory modules in each of said banks. A digital data processing system according to claim 1, in which there are P banks of memory, each said predetermined fixed maximum memory capacity of each memory bank comprises a fixed number, N,of said segments of memory (where N and P are integers greater than 1), and said logic cells are arranged in a matrix of P columns and 2 H /N rows, each row receiving N consecutive segment signals, with adjacent rows receiving consecutive groups of segment signals, and each column receiving said capacity signals from corresponding memory banks. A digital data processing system according to claim 2 in which each column of the matrix is arranged to direct the capacity signals logically through each cell in the column to control selection of said segment signals for addressing the memory, and, when the capacity signals indicate a capacity greater than zero in the corresponding memory bank, to generate a bank select signal for selecting the bank for memory access therein. A digital data processing system according to claim 2 or claim 3 in which the columns each have a number of logic cells from 1 to 2 H /N, the number increasing by one for each consecutive column corresponding to memory banks containing consectively higher orders of addresses. A digital data processing system according to any one of claims 2 to 4, in which the rows each have a number of logic cells from P to 1, the number decreasing by one for each set of segment signals corresponding to memory segments with consecutively higher ordered memory addresses therein. A digital data processing system according to any of the previous claims, in which said memory is a dynamic random access memory, and said logic cells provide signals controlling different Row Address Select and Column Address Select signals to access different memory areas

Inventors: BLOKKUM DAG REIDAR, JOHNS CHARLES RAY, MOROZINK LEE JACK, PETERSON DAVID LAWRENCE, BLOKKUM, DAG REIDAR, JOHNS, CHARLES RAY, MOROZINK, LEE JACK, PETERSON, DAVID LAWRENCE
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: G06F12
IPC codes: G06F12