SENSE AMPLIFIER

Abstract: A sense amplifier of the invention includes a PMOS transistor (7), the source and the drain of which are respectively connected to a power source (S) and an EP-ROM as a signal source to be detected, and the gate and the drain of which are controlled to be at the same potential, a PMOS transistor (8) connected to the power source (5) and the EP-ROM (5) in parallel with the PMOS transistor (7), and a ratio circuit in which the gate of one PMOS transistor (9) and an NMOS transistor (10) constituting a CMOS transistor is connected to the signal source. This arrangement of the invention enables a high speed operation.

Description: The present invention relates to a sense amplifier and, more particularly, to a sense amplifier used in an EP-ROM (Erasable Programmable ROM) and a logic MOS IC incorporating an EP-ROM. Fig. 1 shows a conventional sense amplifier using an EP-ROM as a signal source to be detected. Referring to Fig. 1, the source of EP-ROM 1 as the signal source to be detected is grounded, and its drain is connected to the source of n-channel MOS transistor 2 (to be simply referred to as an NMOS transistor hereinafter). The drain of NMOS transistor 2 is connected to the drain of p-channel MOS transistor 3 (to be simply referred to as a PMOS transistor hereinafter) and the input terminal of CMOS two-stage inverter 4. Power source S is connected to the source of PMOS transistor 3, whose gate is grounded. Voltage Via is applied to the gate of NMOS transistor 2 so as to turn on NMOS transistor 2. Note that the ON resistance of PMOS transistor 3 is set to be sufficiently larger than the sum of the ON resistances of EP-ROM 1 and NMOS transistor 2. An operation principle of the conventional sense amplifier will be described below. When EP-ROM 1 is ON, both NMOS transistor 2 and PMOS transistor 3 are rendered conductive. As a result, current flows from power source S to ground E through PMOS transistor 3, NMOS transistor 2, and EP-ROM 1. When the current flows in this manner, since the ON resistance of PMOS transistor 3 is set to be sufficiently larger than the sum of the ON resistances of EP-ROM 1 and NMOS transistor 2, a great voltage drop occurs across PMOS transistor 3, and the potential at drain (point A) of PMOS transistor 3 becomes substantially 0 V. Since the potential at point A becomes close to 0 V, output OUT is set to 0 V through two-stage inverter 4. On the other hand, when EP-ROM 1 is OFF, NMOS transistor 2 is rendered nonconductive, and PMOS transistor 3 is rendered conductive. As a result, the potential at point A is pulled up to power source voltage V DD by PMOS transistor 3. When the potential at point A is set to power source voltage V DD , output OUT is set to power source voltage V DD through inverter 4. Note that NMOS transistor 2 is a transistor for voltage control, and is used to prevent a high voltage from being applied to the sense amplifier when data is written in an EP-ROM cell. A drawback of the above-described prior art is that the operation speed of the sense amplifier is low. That is, a considerably long period of time is required to cause the potential at the drain (point A) of PMOS transistor 3 to rise from 0 V to V DD when EP-ROM 1 is turned off. This is because charging speeds of circuit capacitances such as a wiring capacitance and capacitances of the diffusion layers of NMOS and PMOS transistors 2 and 3 are slow. The charging speeds are slow because the ON resistance of PMOS transistor 3 is large. In order to increase the charging speeds, the ON resistance of PMOS transistor 3 may be decreased. If, however, the ON resistance of PMOS transistor 3 is set to be smaller than the sum of ON resistances of EP-ROM, 1 and NMOS transistor 2, a voltage drop across PMOS transistor 3 is small and the potential at point A becomes higher than V DD /2 when EP-ROM 1 is turned on. It is very difficult to set the threshold of the first-stage inverter of two-stage inverter 4 to a value between potential V DD /2 and power source voltage V DD because of variations in actual transistor characteristics. Therefore, the ON resistance of PMOS transistor 3 must be set to be large, resulting in a decrease in operation speed of the sense amplifier. As described above, the operation speed of the conventional sense amplifier is low, and hence is not suitable for a circuit requiring a high speed operation. For this reason, a circuit employing the conventional sense amplifier cannot be operated in higher frequency regions or cannot process a large amount of data, and has significant drawbacks in terms of cost, reliability, and performance. It is an object of the present invention to provide a sense amplifier capable of increasing the operation speed. To solve this object the present invention provides a sense amplifier as specifed in claim 1. According to a first embodiment, the signal line of the signal source to be detected is connected to the gate and one end of a channel conductive path of the fourth MOS transistor of the first channel type, one end of a channel conductive path of the first MOS transistor of the first channel type, and the gate of the third MOS transistor of the second channel type constituting a CMOS ratio circuit. One end of a channel conductive path of the second MOS transistor of the first channel type also constituting the CMOS ratio circuit is connected to one end of the channel conductive path of the third MOS transistor of the second channel type. A first potential applying terminal is connected to the other end of each of the channel conductive paths of the first, second, and fourth MOS transistors of the first channel type. A second potential applying terminal is connected to the other end of the channel conductive path of the third MOS transistor of the second channel type. A voltage is applied to the gates of the first and second MOS transistors of the first channel type so as to turn them on. According to a second embodiment, the signal line of the signal source to be detected is connected to the gate and one end of a channel conductive path of the fourth MOS transistor of the first channel type, one end of a channel conductive path of the first MOS transistor of the first channel type, and the gate of the second MOS transistor of the first channel type constituting a CMOS ratio circuit. A channel conductive path of the second MOS transistor of the first channel type is connected to one end of a channel conductive path of the third MOS transistor of the second channel type also constituting the CMOS ratio circuit. A first potential applying terminal is connected to the other end of each of the channel conductive paths of the first, second, and fourth MOS transistors of the first channel type. A second potential applying terminal is connected to the other end of the channel conductive path of the third MOS transistor of the second channel type, and a voltage is applied to the gate of the first MOS transistor of the first channel type and the third MOS transistor of the second channel type so as to turn them on. According to the above embodiments of the present invention, in a sense amplifier, a PMOS transistor whose gate and drain are set to the same potential and a PMOS transistor having a gate to which a certain voltage is applied are connected to a signal line of a signal source to be detected in parallel, and the signal source is connected to one of the gates of a PMOS transistor and an NMOS transistor of CMOS transistors constituting a ratio circuit. With this circuit arrangement, the operation speed of the sense amplifier can be greatly increased, and hence the sense amplifier can be applied to a circuit requiring a high speed operation. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is circuit diagram of conventional sense amplifier; Fig. 2 is a circuit diagram of a sense amplifier according to an embodiment of the present invention; and Fig. 3 is a circuit diagram of a sense amplifier according to another embodiment of the present invention. Figs. 2 and 3 show sense amplifiers according to embodiments of the present invention. Both the sense amplifiers shown in Figs. 2 and 3 use an EP-ROM as a signal source to be detected. The sense amplifier shown in Fig. 2 will be described first. The source of EP-ROM 5 as the signal source to be detected is grounded, and its drain is connected to the source of n-channel MOS transistor 6 (to be referred to as a NMOS transistor hereinafter). The drain of NMOS transistor 6 is connected to the gate and drain of p-channel MOS transistor 7 (to be referred to as a PMOS transistor hereinafter). The drain of NMOS transistor 6 is connected to the drain of p-channel MOS transistor 8 and the gate of n-channel MOS transistor 10 constituting a ratio circuit. The drains of p-channel MOS transistor 9 and NMOS transistor 10 constituting the ratio circuit are connected to each other, and a node of the drains of PMOS and NMOS transistors 9 and 10 is connected to second-stage inverter 11. Power source S is connected to the sources of PMOS transistors 7, 8, and 9. The gates of PMOS transistors 8 and 9 are set to 0 V. The source of NMOS transistors 10 is set to 0 V. Voltage Via having a predetermined level which turns on NMOS transistor 6 is applied to its gate. An operation of the sense amplifier shown in Fig. 2 will be described below. The operation includes two cases wherein EP-ROM 5 as the signal source to be detected is ON and OFF. When EP-ROM 5 is ON, all of EP-ROM 5, NMOS transistors 5 and 6, and PMOS transistor 8 are rendered conductive. Therefore, a current flows from power source S to ground E through PMOS transistors 7 and 8, NMOS transistor 6, and EP-ROM 5. The potential at point B is set to power source voltage V DD while EP-ROM 5 is OFF. When EP-ROM 5 is turned on, however, the potential begins to drop. When the potential at point B drops below V DD - |Vthp| (Vthp is the threshold voltage of PMOS transistor 7), PMOS transistor 7 is rendered conductive. Subsequently, a current also flows from power source S on the side of the source of PMOS transistor 7. The potential at point B is then set to voltage V ON which is the value obtained by dividing source voltage V DD by the parallel ON resistance of PMOS transistors 7 and 8, and the ON resistance of NMOS transistor 6, and EP-ROM 5. When EP-ROM 5 is turned off, circuit capacitances such as a wiring capacitance and capacitances of the diffusion layers of NMOS transistor 6 and PMOS transistors 7 and 8 connected to point B are charged by PMOS transistors 7 and 8 from V ON to power source voltage V DD . In the conventional sense amplifier, since the circuit capacitances connected to point B are charged only through PMOS transistor 8 having a high ON resistance, the charging speeds are low. In contrast to this, in the sense amplifier shown in Fig. 2, since the drain and gate of PMOS transistor 7 are connected to each other and the ON resistance of transistor 7 is very small, the circuit capacitances connected to point B can be charged at a speed much higher than that in the conventional sense amplifier until the potential at point B reaches V DD - |Vthp|. When the potential at point B exceeds V DD - |Vthp|, PMOS transistor 7 is rendered nonconductive. While the potential at point B reaches from V DD - |Vthp| to V DD , the circuit capacitances connected to point B are charged by power source S only through PMOS transistor 8. An operation of the ratio circuit constituted by PMOS transistor 9 and NMOS transistor 10 will be described below. PMOS transistor 9 is always set in a conductive state because 0 V is applied to its gate. Power source voltage V DD or voltage V ON is applied to the gate of NMOS transistor 10. Consequently, NMOS transistor 10 is always set in a conductive state. When a voltage applied to the gate of NMOS transistor 10 is changed, its ON resistance is changed. When the ON resistance of NMOS transistor 10 is changed, the potential at the output portion (point C) of the ratio circuit is changed. In order to operate inverter 11 of the next stage, the voltage applied to point C must be either higher or lower than threshold value Vth. The voltage applied to point C is determined by the ratio of the ON resistance of PMOS transistor 9 to the ON resistance of NMOS transistor 10. In addition, since the gate of PMOS transistor 9 is grounded, the ON resistance of PMOS transistor 9 is kept unchanged. Therefore, the voltage applied to point C is adjusted by the ON resistance ratio of PMOS and NMOS transistors 9 and 10 which is changed by changing the ON resistance of NMOS transistor 10. If the potential at point B is power source voltage V DD , the ON resistance of NMOS transistor 10 is decreased, and the voltage applied to point C drops below threshold voltage Vth of inverter 11 in accordance with the ON resistance ratio of NMOS transistor 10 to PMOS transistor 9. If the potential at point B is V ON , the ON resistance of NMOS transistor 10 is increased, and the voltage applied to point C exceeds threshold voltage Vth of inverter 11 in accordance with the ON resistance ratio of NMOS transistor 10 to PMOS transistor 9. Since the voltage applied to point C is set to be either higher or lower than threshold voltage Vth of inverter 11, inverter 11 is normally operated. As a result, the potential at output OUT is set to either V DD or 0 V. The sense amplifier shown in Fig. 3 will be described below. The circuit shown in Fig. 3 is different from the circuit in Fig. 2 only in the ratio circuit. Therefore, only an arrangement of the ratio circuit will be described. In the circuit shown in Fig. 2, the drain of NMOS transistor 6 is connected to the gate of NMOS transistor 10 of the ratio circuit. However, in the circuit shown in Fig. 3, the drain of NMOS transistor 6 is connected to the gate of PMOS transistor 9. Furthermore, in the circuit shown in Fig. 3, power source voltage V DD is applied to the gate of NMOS transistor 10. The drains of PMOS and NMOS transistors 9 and 10 are connected to each other, and node E thereof is connected to inverter 11 of the next stage. An operation of the circuit in Fig. 3 will be described below. The voltage applied to node D of the drain of PMOS transistor 8 and the gate of PMOS transistor 9 in the circuit shown in Fig. 3, and the voltage applied to point B in the circuit shown in Fig. 2 are the same, which is either power source voltage V DD or voltage V ON , i.e., the voltage obtained by dividing power source voltage V DD by the parallel ON resistance of PMOS transistors 7 and 8, and the ON resistances of NMOS transistor 6 and EP-ROM 5. Each of the two voltages is applied to the gate of PMOS transistor 9. NMOS transistor 10 is always set in a conductive state because power source voltage V DD is applied to its gate. Since PMOS transistor 9 is rendered nonconductive when power source voltage V DD is applied to the gate of PMOS transistor 9, the voltage applied to point E becomes 0 V. As a result, output OUT of inverter 11 is set to power source voltage V DD . When voltage V ON is applied to the gate of PMOS transistor 9, transistor 9 is rendered conductive. Subsequently, point E is set to a potential higher than threshold voltage Vth of inverter 11 of the next stage in accordance with the ON resistance ratio of NMOS transistor 10 to PMOS transistor 9. As a result, output OUT of inverter 11 is set to 0 V. Accordingly, even if the ratio circuit is modified, the circuits shown in Figs. 2 and 3 are operated in the same manner. As has been described above, by adding PMOS transistor 7 whose gate and drain are set at the same potential to a sense amplifier, the operation speed of the sense amplifier is greatly increased especially when an EP-ROM cell is turned off. Note that NMOS transistor 6 is a transistor for voltage control, and is used to prevent a high voltage from being applied to the sense amplifier when the EP-ROM cell is written.

Claims: A sense amplifier for detecting a voltage of a signal source (5) to be detected, comprising: a first MOS transistor (8), one end of a channel conductive path of which is connected at a node (A,B) to one end of said signal source (5), and a gate of which is grounded, for causing a current from a power source (S) to flow toward said signal source (5) when said signal source (5) is turned on; second and third MOS transistors (9, 10) connected in a series connection between the power source (S) and ground, said series connection being controlled by the voltage of said node (A,B) and delivering an output at the connection point (C,E) of said second and third MOS transistors (9, 10), and an inverter (11) connected to said connection point (C,E), characterized by a fourth MOS transistor (7), a gate and one end of a channel conductive path of which are connected to said one end of said signal source (5), for quickly increasing the potential at said node (B) between said signal source (5) and said first MOS transistor (8) to V DD - |Vthp| after said signal source (5) is switched from ON to an OFF state; V DD being a power source voltage and, Vthp a threshold value of said fourth MOS transistor wherein: a ratio circuit, is constituted by one of said second and third MOS transistors (9, 10) having a constant ON resistance and the other of said second and third MOS transistors (9, 10) having an ON resistance changed in accordance with a change in potential at said node (B), for changing the output in accordance with a change in ON resistance of said other MOS transistor. A sense amplifier according to claim 1 characterized in that: said first (8), second (9) and fourth (7) MOS transistors are of a first channel type. said third MOS transistor (10) is of a second channel type, and a gate of said third MOS transistor (10) is connected to the node (B) between said signal source (5) and said first MOS transistor (8). A sense amplifier according to claim 1, characterized in that: said first, second and fourth MOS transistors (8, 9, 7) are of a first channel type, said third MOS transistor (10) is of a second channel type, and a gate of said second MOS transistor (9) is connected to the node (D) between said signal source (5) and said fourth MOS transistor (7). A sense amplifier according to anyone of claims 1 to 3, characterized in that signal source (5) comprises an EP-ROM. A sense amplifier according to anyone of claims 1 to 4, characterized in that said inverter (11) comprises a CMOS inverter.

Inventors: ABE, ISAO C/O PATENT DIVISION, MATSUMOTO, OSAMU C/O PATENT DIVISION, NAKASHIRO, TAKESHI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION
Application year: 1988
Main classification: G11C7
IPC codes: G11C16, G11C7, G11C17, H03K5