EXCLUSIVE-OR GATE CIRCUIT

Abstract: A 3-input Exclusive-OR gate circuit includes first, second and third inverters (M1, M2; M3, M4; M5, M6) having inputs adapted to receive first, second and third input signals, with the first and third inverters (M1, M2; M5, M6) having outputs coupled to first and second pairs of MOS gates (M11, M12; M7, M8) and the second inverter having an output coupled to an inverting means (M9, M10) which controls a pair of transmission gates (M14, M15; M16, M17) arranged to be alternatively operable. The current paths of the transmission gates (M14, M15; M16, M17) are coupled to outputs of the pairs of MOS gates (M11, M12; M7, M8) and have a common node (NB) which is coupled to a fourth inverter (M19, M20) which provides the circuit output.

Description: EXC USIVE-OR GATE CIRCUIT Technical Field This invention relates to 3-input Exclusive- OR gate circuits. Such circuits find a particular application in parity circuits. Background Art UoS. Patent No. 4,533,841 discloses in Fig. 16 a circuit which is stated to be operable as a 3- input Exclusive-OR circuit, which includes a first stack of three n-channel MOS transistors connected in series and having the three input signals applied to their respective gates. The three input signals are also applied via respective inverters to the gates of a second stack of three n-channel MOS transistors connected in series. The known circuit utilizes a small number of devices and hence has a small amount of signal delay. However, because of the stacked configurations, a relatively large physical width is required at the gates and drains of the stacked transistors. Also, the transistors driving the stacked transistors require a relatively large width because of the increased capacitance of the stacked transistors resulting from the aforementioned large physical width. Thus the known circuit has the disadvantage of being of an unduly large size. For example, when the circuit is implemented in an integrated circuit chip, an unduly large area is needed on the chip to accommodate the circuit. Disclosure of the Invention It is the object of the present invention to provide a 3-input Exclusive-OR gate circuit which has a small amount of delay, and wherein the aforementioned disadvantage is alleviated. Therefore, according to the present invention, there is provided a 3-input Exclusive-OR gate circuit, characterized byt first, second and third inverters having inputs adapted * to receive respective first, second and third input signals, and outputs adapted to provide respective first, second and third inverted input signals; first and second current switches serially connected together at a junction point defining a first node, said first current switch being connected to a second node and said second current switch being connected to a third node; inverting means adapted to receive said second inverted input signal and to provide control signals to said first and second current switches, corresponding to said second inverted input signal and the complement thereof, such that only one of said current switches is turned on at any time; a fourth inverter having an input coupled to said first node and an output adapted to provide the output signal of the Exclusive-OR circuit; first gating means responsive to said first and third inverted input signals and having an output connected to said third node; and second gating means responsive to said first and third inverted input signals and having an output connected to said second node. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a schematic diagram of the preferred embodiment of the present invention; and Fig. 2 is a block logic diagram illustrating the configuration of a parity checking circuit incorporating four of the circuits shown in Fig. 1. Best Mode for Carrying Out the Invention Referring to Fig. 1, the Exclusive-OR gate circuit embodiment of the present invention is shown having three inputs labeled A, B and C, and one output labeled D. Three pairs of CMOS transistors, M1-M2, . M3-M4 and M5-M6, form first, second and third inverters, respectively. Each of the inverters is connected to one of the labeled inputs. The inverters function to invert the logic level of the signals on their inputs. The inverted signals are taken from the juncture of the respective pairs of CMOS transistors. Each of the inverters is connected between a power potential terminal labeled VDD and a reference potential terminal which in the preferred embodiment is ground. The output from the first inverter is connected to a first pair of MOS gates of first channel type, M11-M12, and to a second pair of MOS gates, M7-M8, of second channel type. In a like manner, the output signal from the third inverter is connected to the first pair and the second pair of MOS gates, Mil-Ml2 and M7-M8, respectively. The gates are formed of MOS transistors each having a source, drain and gate electrode. The source and drain electrodes constitute a current path which path is controlled by the potential on the gate electrode. A circle on the gate electrode of the MOS devices, shown in the drawings, indicates a P-channel device and the absence of a circle indicates an N-channel device. The first pair of MOS gates, being of the P-channel type, and the second pair of MOS gates, being of the N-channel type, makes the first pair of MOS gates responsive to signals which are complementary to those to which the second pair of MOS gates would be responsive. In the preferred embodiment, there is a cross coupling such that the gate electrode of M7 is connected to the output of the third inverter while the gate electrode of M8 is connected to the output of the first inverter. In a like manner, the gate electrode of Mil is connected to the output of the third inverter and the gate electrode of M12 is connected to the output of the first inverter. The first and second pair of MOS gates connect to the remainder of the circuit via their current paths at nodal points NA and NC, respectively. A first P- channel, MOS gate M13, connects the nodal point NA to a power potential terminal denoted VDD. The gate electrode of MOS device M13 is connected to the reference potential. A second N-channel, MOS gate M18, connects the nodal point NC to the reference potential and has its gate electrode connected to the power potential terminal VDD. A first pair of parallel connected complementary MOS gates, M14 and M15 (commonly called a transmission gate), is connected between the nodal point NA and a nodal point NB. In a like manner, a second pair of parallel connected complementary MOS gates, M16 and M17, are connected between the nodal point NB and NC. These transmission gates operate as current switches in response to the signals appearing on their gate electrodes. These signals are generated by a modified inverter circuit comprised of complementary MOS transistors M9 and M10. The gate electrodes of devices M9 and M10 are coupled to the output of the second inverter circuit formed from devices M3 and M4. The first output is taken from the junction point of devices M3 and M4 and is directed to the gate electrode of device M9 and to the gate electrode of device M10 and to the gate electrode of device M17 and to the gate electrode of device M14. The second output, which is complementary to the first output, is taken from the junction point of devices M9 and M10 and is directed to the gate electrode of device M15 and to the gate electrode of device M16. The signal resulting at the node NB is directed to a fourth inverter circuit formed from the MOS devices M19 and M20. The circuit output is taken from the juncture of the devices M19 and M20. In the following truth table, labeled TABLE 1, there is disclosed the relationship between the .. logic level of the signals on the inputs labeled A, B and C and the logic level of the signals on the internal nodes NA, NB and NC, and finally their relationship to the logic level of the signal on the output labeled D. In the nomenclature used in Table 1, L stands for a low level signal and H stands for a high level signal. For those knowledgeable in this art, it can be quickly deduced that the logic level of the signal on the output D is an Exclusive-OR function of the logic level of the signals on the inputs A, B and C. Input Internal Nodes Output A B C NA NB NC D L L L H H L L L L H L L H H L H L H L L H L H H L H H L H L L L L H H H L H H H L L H H L L H H L H H H H L L H TABLE 1 Truth Table for 3-Input Exclusive OR In the following state table, labeled TABLE 2, there is disclosed the "ON" and "OFF" states for each of the MOS gates labeled Ml-20 for the full range of logic possibilities for the signals applied to the inputs A, B and C. & B C Ml M2 M3 M4 M5 M6 M7 M8 M9 M10 Mil L L L ON OFF ON OFF ON OFF ON ON OFF, ON. OFF L L H ON OFF ON OFF OFF ON OFF ON OFF ON ON L H L ON OFF OFF ON ON OFF ON ON ON OFF OFF L H H ON OFF OFF ON OFF ON OFF ON ON OFF ON H L L OFF ON ON OFF ON OFF ON OFF OFF ON OFF H L H OFF ON ON OFF OFF ON OFF OFF OFF ON ON H H L OFF ON OFF ON ON OFF ON OFF ON OFF OFF K H H OFF ON OFF ON OFF ON OFF OFF ON OFF ON AB C M12 M13 M14 M15 M16 M17 M18 M19 M20 L L L OFF ON ON ON OFF OFF ON OFF ON L L H OFF ON ON ON OFF OFF ON ON OFF L H L OFF ON OFF OFF ON ON ON ON OFF L H H OFF ON OFF OFF ON ON ON OFF ON H L L ON ON ON ON OFF OFF ON ON OFF H L H ON ON ON ON OFF OFF ON OFF ON H H L ON ON OFF OFF ON ON ON OFF ON H H H ON ON OFF OFF ON ON ON ON OFF TABLE : 2 MOS States for 3-Input Exclusive OR The circuit of Fig. 1, thus far described, finds particular utility as a building block for a parity circuit. Referring to Fig. 2, four of the Exclusive-OR gates of Fig. 1 are shown interconnected so as to form a parity checking circuit which circuit receives as inputs 8-bits (byte) of data with the ninth input being the parity check bit. The output of the parity checking circuit will be of a first logic level when the 8 bits and the check bit are in a correct relationship and will be of a second logic level when any of the 8 bits are in error. , - . ..

Claims: Claims t 1. A 3-input Exclusive-OR gate circuit, characterized by: first, second and third inverters (Ml, M2; M3, M4; M5, M6) having inputs adapted to receive respective first, second and third input signals, and outputs adapted to provide respective first, second and third inverted input signals; first and second current switches (M14, M15; M16, M17) serially connected together at a junctioa point . - ..- defining a first node (NB), said first current switch ( IA M15) being connected to a second node (NA) and said second current switch (M16, M17) being connected to a third node NC) ; inverting means (M9 f M10) adapted to receive said second inverted input signal and to provide control signals to said first and second current switches (M14, M15; M16, M17), corresponding to said second inverted input signal and the complement thereof, such that only one of said current switches (M14, M15; M16, M17) is turned on at any time; a fourth inverter (M19, M20) having an input coupled to said first node (NB) and an output adapted to provide the output signal of the Exclusive-OR circuit; first gating means (Mil, M12) responsive to said first and third inverted input signals and having an output connected to said third node (NC) ; and second gating means (M7, M8) responsive to said first and third inverted input signals and having an output connected to said second node (NA) . 2. The 3-input Exclusive-OR gate circuit according to claim 1, characterized in that said first gating means includes a first pair of MOS gates (Mil, M12) of first channel type, each gate having a source, drain, and gate electrode, with said drain electrodes being connected to the third node (NC) , the source electrode of one of said first pair of MOS gates (Mil, M12) being connected to the output of said first inverter (Ml, M2) and the source electrode of the other of said first pair of MOS gates (Mil, M12) being connected to the output of said third inverter (M5, M6), the gate electrode of one of said first pair of MOS gates (Mil, M12) being connected to the source electrode of the other of said first pair of MOS gates (Mil, M12) and the gate electrode of the other of said first pair of MOS gates (Mil, M12) being connected to the source electrode of. the .one of said.first pair of - MOS gates (Mil, M12); and in that said second gating .means includes a second pair of MOS gates (M7, M8) of second channel type, each gate having a source, drain, and gate electrode, with said source electrodes being connected to the second node (NA) , the drain electrode of one of said second pair of MOS gates (M7, M8) being connected to the output of said first inverter (Ml, M2) and the drain electrode of the other of said second pair of MOS gates (M7, M8) being connected to the output of said third inverter (M5, M6), the gate electrode of one of said second pair of MOS gates (M7, M8) being connected to the drain electrode of the other of said second pair of MOS gates (M7, M8) and the gate electrode of the other of said second pair of MOS gates (M7, M8) being connected to the drain electrode of the one of said second pair of MOS gates M7, M8) . 3. A 3-input Exclusive-OR gate circuit according to claim 2, characterized in that first and second current switches include respective first and second pairs of parallel connected CMOS gates (M14, Ml5; M16, M17) . 4. The 3-input Exclusive-OR gate circuit according to claim 3, characterized in that said inverting means includes a first MOS transistor (M9), of said first channel type, having a gate electrode and a first current path, said gate electrode being connected to the output of said second inverter (M3, M4) and said first current path being connected between a power supply and one gate electrode of each of said first and second pair of parallel connected CMOS gates (M14, M15; M16, M17) and a second MOS transistor (M10), of said second channel type, having a gate electrode and a second current path, said gate electrode being connected to the other gate of ~ each * of said first and second pair of parallel connected CMOS gates (M14, M15; M16, M17) and to the output of said second inverrter (M3, M4), said second current path being connected between a reference potential and said one gate of each of said first and second pair of parallel connected CMOS gates (M14, M15; M16 r M17). 5. A 3-input Exclusive-OR gate circuit according to claim 4, characterized in that said first, second, third and fourth inverters (Ml, M2; M3, M4; M5, M6; M19, M20) each include a pair of complementary MOS transistors connected in series between said power supply and said reference potential. 6. A 3-input Exclusive-OR gate circuit according to claim 3, characterized in that said first and said second pair of parallel connected CMOS gates (M14, M15; M16, M17) each includes a pair of complementary channel type MOS transistors each having a gate electrode and a current path, with the current paths connected in parallel and with the gate electrodes, of one channel type, of said first and said second pair of parallel connected CMOS gates connected to the gate electrodes of opposite channel type. 7. A 3-input Exclusive-OR gate circuit according to claim 6, characterized in that a further MOS gate (M13) is connected between said second node (NA) and said power supply, and in that an additional MOS gate (M18) is connected between said third node (NC) and said reference potential with said further and said additional MOS gates (M13, M18) being maintained in an on condition by connection to said reference potential-and. said, power -supply, . respectively.

Inventors: SANWO IKUO JIMMY, SUTHAR MUKESH BHOGILAL, SANWO, IKUO, JIMMY, SUTHAR, MUKESH, BHOGILAL
Applicants: NCR CO, NCR CORPORATION
Application year: 1988
Main classification: H03K19
IPC codes: H03K19