SELECTIVE RECEIVER FOR EACH PROCESSOR IN A MULTIPLE PROCESSOR SYSTEM

Abstract: Circuitry, and associated methodology, in a parallel processing system (50) for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with buffer means (e.g. 140) for storing data received off the bus, and means (e.g. 120, 130) for selectively enabling the buffer means to accept those segments of data having addresses allocated to the given processor. To avoid overwriting of data during bus conflicts, the buffer means are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondance to respective bus and processor states.

Description: SELECTIVE RECEIVER FOR EACH PROCESSOR IN A MULTIPLE PROCESSOR SYSTEM Field of the Invention This invention relates generally to multiple processor configurations and, more particularly, to circuitry and associated methodology for enabling each processor to receive selectively only pertinent portions of data that is broadcast to the processor over a communication bus interconnecting the processors. Background of the Invention A programmable digital computer provides a readily adaptable environment to simulate physical systems such as a communication network or a multi-layer protocol. However, in order to make simulations tractable for complex systems, oftentimes it is necessary that parallel processing be utilized. With parallel processing, system computations are subdivided into tasks that are suitable for execution in parallel. The tasks are then distributed among a plurality of synchronized processors for autonomous execution. Conventionally, computation results are stored in a single memory which is common to or shared among the several processors via a multiple access memory bus interconnecting the memory with the processors. Traditional methods for accessing and then storing computational data into the single memory possess inherent deficiencies. Two prime areas of difficulty are excessive loading of the memory bus and high overhead manifested by extra, unproductive processor cycles. Both of these factors may lead to unsuccessful access to the memory because of busy or blocking conditions exhibited by either the bus or the memory, or both simultaneously. The main cause of these difficulties is the constraint induced by the architectural arrangement, namely, the need to request and then acquire two shared resources in series with some probability that access to each resource may fail. In the case of a failure because of a busy condition, the entire access process must be continually repeated until access succeeds. The failure rate is exacerbated whenever the demand for memory access increases. A so-called conflict, that is, a simultaneous update of the same memory location by two or more processors, is another situation that is difficult to handle in shared memory systems. Multiple processors sharing the same data are called overlapping processes and the prevention of other processors from accessing shared data while one processor is doing so is called mutual exclusion. Several conventional techniques for implementing mutual exclusion, such as semaphores and test and set instructions, are detailed in the text entitled An Introduction to Operating Systems, by H- M. Ditel, Addison-Wesley, 1983, Chapter 4. These techniques also suffer from similar performance and overhead problems discussed above and, moreover, and extremely error-prone when handled by user-written software. Finally, standard shared memory systems employ a destructive write process. Thus, when a memory location is modified, the contents of that location are replaced with the modified data and the original data is destroyed. This process, when combined with traditional conflict resolution techniques, basically obliterates the data history of each memory location, thereby either limiting the processor to using only the single data value presently stored in the memory location at the end of each computational phase or requiring elaborate recomputation procedures to reconstruct overwritten data. Summary of the Invention The above-identified shortcomings and limitations of the conventional methods and associated circuitry for storing data propagating on a bus interconnecting the processors in a multiple processor system are obviated, in accordance with the present invention, by providing each autonomous processor with an arrangement to receive selectively only pertinent segments of data propagating over the bus. Illustratively, this is achieved by providing each processor with both buffer memory means and means for selectively enabling the buffer means to accept data on a first-in, first-out basis off the bus. The means for enabling stores information which is indicative of those segments of data that are required by the associated processor. The organization and operation of this invention will be better understood from a consideration of the detailed description of the illustrative embodiment thereof, which follows, when taken in conjunction with the accompanying drawing. Brief Description of the Drawing FIG. 1 is a block diagram depicting three processors, and their associated shared address space circuits, from a multiple processor system configured in accordance with one aspect of the present invention; FIG. 2 depicts, in block diagram form, one processor and its associated shared address space circuitry from FIG. 1, wherein the circuitry is shown to further comprise a control arrangement for conflict resolution and flow control; and FIG. 3 is a timing diagram for the embodiment in accordance with FIGS. 1 and 2. In the FIGS., reference numerals of like elements are incremented by 100, 200 and so forth depending upon the particular processor under consideration in the multiple processor system. Detailed Description With reference to FIG. 1, three autonomous processing entities 100, 200 and 300 in a multiple processor system 50 are interconnected via common communication bus 60, which is illustratively the VME-type bus well-known in the computer art. All other processing entities not shown are connected to bus 60 in the same multiple-access manner. Each processing unit 100, 200 or 300 includes stand-alone processors 110, 210 or 310, and each of these processors is coupled to shared address space circuitry. With reference to processor 110, for example, mask memory 120, first-in, first-out (FIFO) buffer 140 and AND gate 130 are circuits comprising the shared address space circuitry of processor 110. Moreover, memory 120, gate 130 and FIFO 140 each are coupled to bus 60. In particular, memory 120 is coupled to parallel address (ADD) sub-bus 61, whereas gate 130 is connected to STROBE lead 63 and FIFO 140 has parallel DATA sub-bus 62 as input. All other shared address space circuitry associated with the remaining processors are configured in essentially the same manner. In addition, each processor 110, 210 and 310 operates in essentially an autonomous mode, that is, in the sense that each processor is composed of an internal clock (not shown) which is independent of the clocks in all other processors. Although the processors operate autonomously, the processors form a parallel processing system having a need to interact such as, for example, by transmitting information generated by or stored in one processor to certain other processors requiring that information; computational data from executed tasks is one form of the information requiring transmission. This is effected over bus 60 in the conventional manner; for the VME-type arrangement, an interrupt signal is the indicator of a transmit ready condition for the broadcasting of information by one or more processors. Broadly, as is indicated in FIG. 1, a separate copy of the data broadcast over bus 62 may be stored by FIFO's 140, 240 and 340. When data is written on bus 62, the data is registered simultaneously in each enabled FIFO. Hence, in contrast to the conventional single memory implementation, the arrangement in accordance with the present invention utilizes replicated, distributed FIFO buffers that are selectively enabled to receive data on bus 62. This makes it possible for each processor to accept only the data that is pertinent to its tasks from what is broadcast over bus 62. Once copied, reading of the data by any particular processor 110, 210 or 310 may occur asynchronously from its associated private copy. In particular, by way of a combined circuit and operational description, the arrangement exemplified by processing unit 100 is now considered. Other processing units behave similarly. Mask memory 120 is illustratively a one bit wide memory having its address input (A) connected to bus 61. Memory 120 stores an enable bit at each address which is pertinent to its associated processor 110. The output (Q) of memory 120 serves as one input to AND gate 130 via lead 121. The other input to gate 130 is STROBE lead 63 of bus 60. The STROBE signal indicates when data is stabilized and may be read off bus 60. The output of gate 130, on lead 131, serves to enable the SHIFT-IN input of FIFO 140. With this coupling arrangement, the one bit of mask memory 120, when ANDed with the FIFO write signal, allows FIFO 140 to receive selectively the data presented to its DATA IN port. Since -a,-g-iven " processor usually requires only a limited portion of the br-oadcast data, the AND operation effectively filters unwanted data under control of the contents of memory 120. Moreover, this arrangement of FIFO 140 effects non-destruct write operations. Since every data update is stored when received on a first-in, first-out basis, processor 110 has available a history of variable changes. For instance, it is supposed that there are two successive writes to an enabled memory location by processing units 200 and 300, respectively. Because of interposed FIFO 140, the two data segments are stacked in FIFO 140. Now, if a conflict is detected (as discussed shortly) , the fact that successive segments of data have been written to the same address and, consequently, are stored serially in FIFO 140, allows for conflict resolution according to an algorithm that is appropriate to the process being executed. In discussing conflict resolution, reference is made to FIG. 2. In FIG. 2, processor 110 and its associated shared address space circuitry are shown together with circuitry to control conflict resolution and flow control. Conflicts are detected by supplying "PENDING" lead 72 and connecting lead 72 to all processors of processor system 50. Lead 72 is arranged to have a "wired OR" characteristic, that is, one or more processors can force PENDING to its dominant or asserted state. In FIG. 2, the PENDING signal is transmitted from the P-OUT port of processor 110 via inverter 154, and PENDING is received at the P-IN port via inverter 156. PENDING is asserted by any processor 110, 210 or 310 at the start of a standard contention cycle on bus 60, and PENDING is released upon the release of bus 60 after the update process is complete. If multiple processors are queued and waiting to use bus 60, PENDING is asserted from the beginning of the first bus request until the completion of the last update; FIG. 3, discussed below, presents timing information. By way of an illustrative operational description, the simple case of two processors both scheduled to modify the same- ariable simultaneously is considered. Both processors assert PENDING and contend for bus 60. The processor that gains control of bus 60 through a standard bus contention mechanism then transmits its data. The receiving processor receives an interrupt from its associated FIFO and proceeds to process the data. This occurs since an interrupt is issued by any FIFO whenever data is entered. Thus, in FIG. 2, FIFO 140 issuses an interrupt signal on lead 142 via the DATA READY port whenever data is entered into FIFO 140. Upon completion of processing by receiving processor 110, it checks the state of lead 72. This lead is still in the asserted state since the second processor has data to transmit. Receiving processor 110 remains in the receive mode until PENDING is cleared after completion of the next data transmission. Finally, when lead 72 is unasserted, « the receiving processor may begin an appropriate conflict resolution routine, being assured that all possible 5 conflicting data has been received. The conflict resolution scheme, since it is not hard-wired, may be implemented as appropriate to each simulation application. For instance, one resolution scheme may deal with the conflict by taking the first update and discarding all 10 others; another scheme may be to average the data. In any simulation wherein the FIFO buffers may be filled at a faster rate than they are emptied, a flow control mechanism is provided to preclude FIFO overflow. The FIFO's are configured to provide a signal on their 15 FLOW port (FIG. 2) whenever they are filled to a predetermined threshold. The FLOW port is connected to FLOW lead 71 via, for example, inverter 150 for FIFO 140. In turn, lead 71 connects to all other processors via, for example, the F port through inverter 152. Lead 71 is also 20 arranged to have a "wired OR" characteristic. Whenever any FLOW port is asserted, all processors receive an interrupt through the F port. With lead 71 asserted, the current transmission is completed and then all processors process the contents of their associated FIFOs before 25 allowing additional data input. To exemplify the timing required of the various components comprising processing system 50, FIG. 3 is considered. It is presumed that processors 210 and 310 are propagating variable changes to processor 110 30 simultaneously. On line (i) of FIG. 3, bus 60 transmits an INITIATE transfer of data signal to processors 210 and 310. This is shown as TIME POSITION 1 and line (i) . Both processors 210 and 310 assert PENDING on lead 72, as shown as TIME POSITION 2 on line (ii) ; also, these processors 35 request use of bus 60 in order to transmit their data information. If it is assumed that processor 210 acquires bus 60 first, then processor 210 begins to transmit its data; this is depicted as beginning at TIME POSITION 3 on line (iii) . The data is received by processor 110 through its shared address space circuitry; in particular, since FIFO 140 receives data, an INTERRUPT is issued to processor 110 via the DATA READY port of FIFO 140. This INTERRUPT signal is shown as commencing at TIME POSITION 4 of line (v) . In response to the INTERRUPT signal, processor 110 begins to read the data. TIME POSITION 5 on line (vi) depicts the start of the read phase. At TIME POSITION 6 on line (iii) , processor 210 has completed its write operation. As then indicated by TIME POSITION 7 on line (vi) , processor 110 completes its read phase and checks the PENDING lead. Since it is still asserted by processor 310, processor 110 awaits more data. Processor 310 now acquires bus 60 and my begin to write the data onto bus 60; TIME POSITION 8 on line (iv) indicates the time that processor 310 begins data transmission. When data transmission is complete, PENDING is unasserted, as per TIME POSITION 9 on line (ii) . When data processor 110 detects that PENDING is released, it may begin to process the total data now in its local storage. TIME POSITION 10 on live (vii) depicts the start of the processing by processor 110 and TIME POSITION 11 shows the completion time. Processors 110, 210 and 310 are now prepared to proceed with the next phase in the simulation process. It is to be understood that the above-identified arrangements are simply illustrative of the application of the principles in accordance with the present invention. Other arrangements may be readily devised by those skilled in the art which embody the principles of the present invention and fall within its spirit and scope. Thus, for example, it is possible to configure each shared address space circuitry (e.g., elements 120, 130 and 140 of FIG. 1) so that an address translation may be effected between addresses on bus 60 and local memory in processor 110. In this situation, mask memory 120 is an N+l bit wide memory wherein one of the bits is used in conjunction with gate 130 for activating data copying and the remaining N bits indicate the address in local memory allocated to store the data. Also, whereas the contents of mask memory 120 as described are static, it is possible to alter dynamically- its contents by also arranging memory 120 with an enable input so as to receive data off bus 60 to alter its contents. Therefore, it is to be further understood that the circuitry and methodology described herein is not limited to specific forms disclosed by way of illustration, but may assume other embodiments limited only by the scope of the appended claims.

Claims: What is claimed is: 1. In combination with a processor and a bus, circuitry comprising buffer means, connected to the processor and the - bus, for selectively storing data propagating on the bus and for interrupting the processor to extract said data whenever said data is registered in said buffer means, and means, connected to the bus and said buffer means, for receiving information from the bus and, in response to said information, for selectively enabling said buffer means to store segments of data propagating on the bus only during the intervals that said buffer means is enabled. 2. The circuitry as recited in claim 1 further comprising flow means for controlling the transfer of said data between said buffer means and the processor in relation to the contents of said buffer means. 3. The circuitry as recited in claim 1 wherein the bus includes an ADFNESS bus, a DATA bus and a STROBE lead and wherein said buffer means is a first-in, first-out shift register having a DATA IN port connected to the DATA bus, a DATA OUT port connected to the processor, and a SHIFT-IN port, and said means for receiving and for selectively enabling includes a mask memory having an ADFNESS port connected to the ADDRESS bus, and an OUTPUT port, and an AND gate having the STROBE lead and said OUTPUT port as its inputs and its output connected to said SHIFT-IN port. 4. The circuitry as recited in claim 3 wherein said mask memory is a 1-bit wide memory that stores a logic one bit only at each address allocated to the processor. 5. The circuitry as recited in claim 3 wherein said buffer means and the processor each have a flow Ϊ control port and wherein the circuitry further comprises means connected to said each flow port for controlling the 5 flow of the data contents between said buffer means and the processor in proportion to the said contents. 6. In combination with a plurality of processors and a bus interconnecting the processors, circuitry associated with each of the processors 10 comprising buffer means, connected to its associated processor and the bus, for selectively storing data propagating on the bus and for interrupting the associated processor to extract said data whenever said data is 15 registered in said buffer means, and means, connected to the bus and said buffer means, for receiving information from the bus and, in response to said information, for selectively enabling said buffer means to store segments of data propagating on 20 the bus only during the intervals that said buffer means is enabled. 7. The circuitry as recited in claim 6 further comprising means, coupled to the processors, for controlling the processing state of each of the processors 25 in response to each data transfer signal issued on the bus by any of the processors. 8. The circuitry as recited in claim 7 further comprising means, connected to the processors and each said buffer means, for controlling the flow of data to the 30 processors from each corresponding buffer means in correspondence to the amount of data stored by each said buffer means. 9. The circuitry as recited in claim 6 wherein the bus includes an ADFNESS bus, a DATA bus and a STROBE 35 lead and wherein each said buffer means is a first-in, first-out shift register having a DATA IN port connected to the DATA bus, a DATA OUT port connected to the associated processor, and a SHIFT-IN port, and each said means for receiving and for selectively enabling includes a mask memory having an ADFNESS port connected to the ADFNESS bus, and an OUTPUT port, and an AND gate having the STROBE lead and said OUTPUT port as its inputs and its output connected to said SHIFT-IN port. 10. Circuitry associated with each autonomous processor in a multiple processor system wherein the processors are interconnected by a common communication bus having an ADFNESS bus, a DATA bus and a STROBE lead, said circuitry comprising a FIFO memory having a SHIFT-IN port, a DATA IN port connected to the DATA bus, a DATA OUT port connected to the DATA INPUT port of the associated processor, and a DATA READY port connected to an operationally equivalent port of the associated processor, a mask memory having an output lead and an address port connected to the address bus, and an AND gate having as inputs the signals on the STROBE lead and said output lead and having its output connected to said SHIFT-IN port, wherein said mask memory stores bits indicative of the addresses which enable data broadcast on the bus to be received selectively and stored by the associated FIFO. 11. A method in a multiple processor system for providing dedicated memory space to each of the processors in the system, the processors being interconnected by a common address bus and a common data bus, the method comprising the steps of associating with each processor buffer storage means coupling the processor with the data bus and memory means interposed between said buffer means and the address bus, : storing in said memory means information indicative of addresses allocated to each processor, and 5 selectively enabling said buffer means by activating said memory means so that said storage means receives and stores data from the data bus whenever one of said allocated addresses appears on the address bus. 12. The method as recited in claim 11 wherein 10 the bus further comprises a data transfer signal lead and wherein the method further comprises the step of controlling the processing state of each of the processors in response to each data transfer signal issued on said transfer lead by any of the processors. 15 13. The method as recited in claim 12 further comprises the step of controlling the transfer of the data contents of each said buffer means with its associated processor in correspondence to the quantity of data in each said buffer means.

Inventors: COHEN DAVID MORDECAI, GOPINATH BHASKARPILLAI, VOLLARO JOHN RICHARD, COHEN, DAVID, MORDECAI, GOPINATH, BHASKARPILLAI, VOLLARO, JOHN, RICHARD
Applicants: BELL COMMUNICATIONS RES, BELL COMMUNICATIONS RESEARCH, INC.
Application year: 1988
Main classification: G06F15
IPC codes: G06F13, G06F15