Output stage for solid-state image pick-up device

Abstract: An output stage of a solid-state image pick-up device, such as CCD solid-state image pick-up device is accurately operable even under lower power source voltage and is easy to design and does not require substantial precision in production. The improved output stage construction of a solid-state image pick-up device, according to the present invention, has at least one buffer circuit (20, 40, 60), connected to at least one of input side or output side of an output stage circuit component, such as an amplifier circuit (10), a low-pass filter (50) and/or a sample/hold circuit (30). The buffer circuit (20, 40, 60) is so designed as to have a constant DC level and a gain about 1.

Description: The present invention relates generally to an improvement in and relating to an output stage of a solid-state image pick-up device , such as a charge-coupled device (CCD). More specifically, the invention relates to an output stage for a solid-state image pick-up device which is operable even at low voltage. In the past, the image pick-up device, such as a CCD, is provided with a higher power source voltage in comparison with that in other semiconductor devices, such as a memory composed of a plurality of MOS transistors. As a typical output stage construction of the image pick-up device, an inverter circuit or a source follower circuit are employed. In the former case, the inverter circuit comprises a pair of first and second MOS transistors. The first MOS transistor has a gate to receive an output signal. The second transistor has a gate and drain connected to each other for forming an active load. An output signal is output between a drain of the first MOS transistor and the second MOS transistor. In the inverter circuit as set forth above, the output level may not coincide with the input level. Therefore, when such an inverter circuit is combined with a low-pass filter, a sample/hold circuit and so forth, the source voltage has to be sufficiently high so as to avoid an influence by fluctuation of the output level. In addition, in such an inverter circuit, the circuit design becomes complicated which makes it difficult to design. On the other hand, the conventional source follower circuit may comprise a pair of first and second MOS transistors. The first MOS transistor receives the input signal at its gate and outputs the output signal from its source. Such source follower circuit has a substantially small gain, e. g. less than or equal to 0dB. Therefore, when a plurality of source followers are connected to form multi-state source follower circuit the gain of such circuit becomes unacceptably small. An output circuit according to the preamble of claim 1 is known from EP-A-0169740. The known circuit comprises a source follower circuit connected to the output of a charge-detect circuit and to the output of a clamp circuit which consists of a AC-coupled clamp capacitor, a clamp switch and a buffer amplifier. The buffer amplifier is shown as operational amplifier not being fed back. The clamp circuit is not very suitable for an improved output stage for a solid-state image pick-up because of varying voltage levels. On the other hand, recently, there is a tendency to require an image pick-up device which is active at a lower power source voltage. If the image pick-up device for low power source voltage operation is designed employing the conventional inverter circuit or the source follower circuit, the level margin becomes substantially small to cause malfunction when fluctuation in DC the level occurs. Therefore, it is the object of the present invention to provide an improved output stage for a solid-state image pick-up device, such as a CCD, which is accurately operable even under a lower power source voltage. The object is solved by the features of claim 1. The dependent claims comprise further developments of the invention. The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiment but are for explanation and understanding only. In the drawings: Fig. 1 is a schematic and explanatory diagram showing the first embodiment of an output stage construction for a solid-state image pick-up device according to the invention; Fig. 2 is a schematic circuit diagram of a Burton circuit to be employed in the output stage circuit construction of Fig. 1; Fig. 3 is a detailed circuit diagram of the first embodiment of the output stage construction for the solid-state image pick-up device, of Fig. 1; Fig. 4 is a schematic and explanatory diagram showing the second embodiment of an output stage construction for a solid-state image pick-up device according to the invention; Fig. 5 is a detailed circuit diagram of the second embodiment of the output stage construction for the solid-state image pick-up device, of Fig 4; Fig. 6 is a schematic and explanatory diagramm showing the third embodiment of an output stage construction for a solid-state image pick-up device according to the invention; and Fig. 7 is a detailed circuit diagramm of the third embodiment of the output stage construction for the solid-state image pick-up device, of Fig. 6. Referring now to the drawings, particularly to Figs. 1 to 3, the first embodiment of an output stage construction, according to the present invention, is composed of a source follower circuit 10 which serves as an amplifier circuit and a Burton circuit 20 as a buffer circuit. The source follower circuit 10 and the Burton circuit 20 are connected in series to form the output stage of the solid-state image pick-up device, i.e. a CCD. The source follower circuit 10 is connected to a floating gate of a CCD image pick-up device. The output section of the source follower circuit 10 is connected to the input section of the Burton circuit 20. The Burton circuit 20 is designed to output a constant DC level. The circuit layout of the source follower circuit 10 and the Burton circuit 20 as a series circuit makes it possible to suppress fluctuation of the DC level at the output. Fig. 2 shows the Burton circuit 20. As seen from Fig. 2, the Burton circuit 20 comprises an operational amplifier 20A and a source follower 20B. The output of the source follower 20B is connected to the negative input terminal of the operational amplifier 20A to form a negative feedback circuit. With this construction, the Burton circuit 20 serves as a voltage follower having high input impedance and low output impedance. This suppresses fluctuation of the output DC level of the output stage of the CCD solid-state image pick-up device. With a fluctuation-suppressed output DC level, it becomes possible for a drive signal processing circuit to be connected to the next stage. Fig. 3 shows practical circuit construction of the first embodiment of the output circuit of the solid-state image pick-up device, according to the invention. In the shown circuit construction, NMOS transistors 11 and 12 are arranged to form the source follower circuit 10. The NMOS transistors 11 and 12 are connected in series between the power source and the ground. The NMOS transistor 11 has a gate which forms an input section of the source follower circuit 10. Therefore, the gate of the NMOS transistor 11 is connected to the output section, such as a floating gate FG of the CCD solid-state image pick-up device in order to receive therefrom the input signal. The NMOS transistor 11 also has a source which forms the output section of the source follower circuit 10. Therefore, the source of the NMOS transistor 11 is connected to the Burton circuit 20. As seen from Fig. 3, in the practical construction, the Burton circuit 20 has a NMOS transistor 21 having a gate connected to the source of the NMOS transistor 11. In this circuit layout, the NMOS transistor 12 serves as load. The Burton circuit 20 serves as the buffer circuit as set forth above and has an differential stage serving as the operational amplifier 20A, and the source follower stage 20B. The arithmetic stage 20A comprises a pair of NMOS transistors 21 and 22 forming differential amplifier, a pair of PMOS transistor 23 and 24 connected to the pair of NMOS transistors 21 and 22 in current mirror fashion, and a NMOS transistor 25 which serves for supplying constant voltage. The source follower stage 20B is composed of a pair of NMOS transistor 26 and 27 connected between the power source and the ground. The NMOS transistors 21 and 22 are active as the differential amplifier as set forth above, for the input on the gate of the NMOS transistor 21 to output an output signal from the drain of the NMOS transistor 22. The drain of the NMOS transistor 22 is connected to the gate of the NMOS transistor 26. The NMOS transistor 26 is responsive to the input through the gate to output the output signal from the source. The source of the NMOS transistor 26 is also connected to the gate of the NMOS transistor 22 as a negative feedback input. This source of the NMOS transistor 26 and the gate of the NMOS transistor 22 form the negative feedback loop. With the circuit construction set forth above, the operational amplifier stage constituted of the NMOS transistors 21 and 22, PMOS transistors 23 and 24 and NMOS transistor 25, is formed as a voltage follower circuit or as an impedance converter circuit. Therefore, the gain at this operational amplifier stage becomes 1. Furthermore, because the operational amplifier serves as the voltage follower or the impedance converter, the output voltage becomes constant. With this construction, the output impedance of the output circuit of the CCD solid-state image pick-up device can be successfully lowered since the Burton circuit 20 serving as a buffer amplifier can avoid the influence of the voltage fluctuation. Furthermore, as the nature of the buffer amplifier employed in the shown circuit construction which allows to regulate the output voltage, greater level margin can be given for the CCD solid-state image pick-up device. In other words, because a greater level margin can be given, lowering of the operation voltage level of the CCD solid-state image pick-up device becomes possible. Furthermore, since the output DC level can be held constant, circuit design with a fixed output voltage becomes possible to make designing easier. In addition, such circuit construction may give a wider signal dynamic range. Figs. 4 and 5 show the second embodiment of the output stage construction of the CCD solid state image pick-up device, according to the present invention. In the shown circuit construction, an active low-pass filter 50 and a Burton circuit 60 are connected in series to the series circuit of the source follower circuit 10 and Burton circuit 20. Therefore, the output of the CCD solid-state image pick-up device is received by the source follower circuit 10. The Burton circuit 20 is responsive to the output signal from the source follower circuit 10 to output the constant DC level output signal. The active low-pass filter circuit 50 filters out the high-frequency component of the output signal from the Burton circuit 20 and feeds to the Burton circuit 60 which serves as another buffer amplifier. Namely, in the shown embodiment, the buffer amplifiers 20 and 60 which hold the output DC level constant and have a gain of precisely 1, are provided for suppressing fluctuation in the input and output DC level at the active low-pass filter circuit 50. Fig. 5 shows the practical construction of the circuit in the second embodiment of the output stage for the CCD solid-state image pick-up device of Fig. 4. In the shown circuit construction of Fig. 5, the source follower circuit 10 and the Burton circuit 20 have sustantially identical circuit constructions to that discussed with respect to the foregoing first embodiment. Therefore, the discusssion of the circuit constructions and components in the source follower circuit 10 and Burton circuit 20 will be neglected and will be simply identified by the common reference numerals to that of the first embodiment, in order to avoid unnecessary redundancy in discussion and confusion in understanding. The output of the Burton circuit 20, i.e. the source of the NMOS transistor 26, is connected to the active low-pass filter circuit 50. The active low-pass filter circuit 50 has the source of a MOS transistor 51a which serves as a resistor. The drain of the MOS transistor 51a is connected to the source of a MOS transistor 51b. The drain of the MOS transistor 51a is also connected to a capacitor 52a. The MOS transistor 51b and the capacitor 52a form a positive feedback loop. The drain of the MOS transistor 51b is connected to a capacitor 52b. As will be appreciated, these MOS transistors 51a and 51b and the capacitors 52a and 52b form a time constant circuit for determining the time constant characteristics of the active low-pass filter circuit 50. The drain of the MOS transistor 51b is also connected to the gate of the NMOS transistor 53 of an operational amplifier circuit in the active low-pass filter circuit 50. The operational amplifier circuit comprises a pair of NMOS transistors 53 and 54 forming a differential amplifier, a pair of PMOS transistor 55 and 56 connected to the pair of NMOS transistors 53 and 54 in a current mirror fashion, and a NMOS transistor 57 which serves for supplying constant voltage. The source follower stage is composed of a pair of NMOS transistors 58 and 59 connected between the power source and the ground. The NMOS transistors 53 and 54 are active as the differential amplifier as set forth above, on the input on the gate of the NMOS transistor 53 to output an output signal from the drain of the NMOS transistor 54. The drain of the NMOS transistor 54 is connected to the gate of the NMOS transistor 58. The NMOS transistor 58 is responsive to the input through the gate to output the ouput signal from the source. The source of the NMOS transistor 58 is also connected to the gate of the NMOS transistor 54 as negative feedback input. This source of the NMOS transistor 58 and the gate of the NMOS transistor 54 form the negative feedback loop. With the circuit construction set forth above, the operational amplifier stage constituted of the NMOS transistors 53 and 54, PMOS transistors 55 and 56 and NMOS transistor 57, is formed as a voltage follower circuit or as an impedance converter circuit. Therefore, the gain at this operational amplifier stage becomes 1. Furthermore, because of the operational amplifier serves as the voltage follower or the impedance converter, the output voltage becomes constant. As shown in Fig. 5, a practical circuit construction of the Burton circuit 60 has substantially the same circuit construction as that of the foregoing Burton circuit 20 discussed in the foregoing first embodiment of Fig. 3. A NMOS transistor 61 having a gate connected to the source of the NMOS transistor 58 of the active low-pass filter circuit 50. Similarly to the Burton circuit 20, the Burton circuit 60 serves as the buffer circuit as set forth above and has an arithmetic stage serving as the operational amplifier, and the source follower stage. The arithmetic stage comprises a pair of NMOS transistors 61 and 62 forming a differential amplifier, a pair of PMOS transistor 63 and 64 connected to the pair of NMOS transistors 61 and 62 in a current mirror fashion, and a NMOS transistor 65 which serves for supplying constant voltage. The source follower stage is composed of a pair of NMOS transistor 66 and 67 connected between the power source and the ground. The NMOS transistors 61 and 62 are active as the differential amplifier as set forth above, on the input on the gate of the NMOS transistor 61 to output an output signal from the drain of the NMOS transistor 62. The drain of the NMOS transistor 62 is connected to the gate of the NMOS transistor 66. The NMOS transistor 66 is responsive to the input through the gate to output the output signal from the source. The source of the NMOS transistor 66 is also connected to the gate of the NMOS transistor 62 as negative feedback input. This source of the NMOS transistor 66 and the gate of the NMOS transistor 62 forms the negative feedback loop. With the circuit construction set forth above, the operational amplifier stage constituted of the NMOS transistors 61 and 62, PMOS transistors 63 and 64 and NMOS transistor 65, is formed as voltage follower circuit or as an impedance converter circuit. Therefore, the gain at this operational amplifier stage becomes 1. Furthermore, because of the operational amplifier serves as the voltage follower or the impedance converter, the output voltage becomes constant. With this construction, the output impedance of the output circuit of the CCD solid-state image pick-up device can be successfully lowered since the Burton circuit 60 serving as a buffer amplifier can avoid the influence of the voltage fluctuation. Furthermore, as the nature of the buffer amplifier employed in the shown circuit construction which allows to regulate the output voltage, a greater level margin can be given for the CCD solid-state image pick-up device. In other words, because the greater level margin can be given, lowering of the operation voltage level of the CCD solid-state image pick-up device becomes possible. Furthermore, since the output DC level can be held constant, circuit design with a fixed output voltage becomes possible to make designing easier. In addition, such circuit construction may give a wider signal dynamic range. Figs. 6 and 7 show the third embodiment of the output stage of the CCD solid-state image pick-up device according to the invention. In this embodiment, a sample/hold circuit 30 is interposed between the Burton circuits 20 and 40. Namely, the source follower circuit 10, the Burton circuit 20, the sample/hold circuit 30, Burton circuit 40, the active low-pass filter circuit 50 and the Burton circuit 60 form a series circuit serving as the output state of the CCD solid-state image pick-up device, as shown in Fig. 6. Fig. 7 shows the detailed circuit construction of the third embodiment of the circuit construction of the third embodiment of the circuit construction of the output stage of the CCD solid-state image pick-up device, according to the invention. The shown circuit construction is substantially the same as that of the foregoing second embodiment except for the sample hold circuit 30. Therefore, the following disclosure will be concentrated to the sample/hold circuit 30 and the associated circuit components in the already disclosed circuits in order to avoid unnecessary redundancy in recitation and to avoid possibility of confusion. The sample/hold circuit 30 comprises a switching transistor 31 and a sample/holding capacitor 32. The switching transistor 31 has a gate connected to a sample/hold signal source to receive a sample/hold pulse. The source of the switching transistor 31 is connected to the output of the Burton circuit 20 to receive therefrom the output signal. The switching transistor 31 is turned ON and OFF by the sample/hold pulse for controlling charge and discharge of the capacitor 32. In this case, the Burton circuit 20 provided at an input side of the switching transistor 31 of the sample/hold circuit 30 supplies a constant DC level of the output signal to the sample/hold circuit. On the other hand, the Burton circuit 40 provided at output side of the sample/hold circuit 30 regulates the output DC level of the output signal of the sample/hold circuit. Therefore, the operation of the active low-pass filter circuit 50 becomes stable. While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modifications to the shown embodiments which can be embodied without departing from the principle of the invention set out in the appended claims.

Claims: An output circuit for a solid-state image pick-up device comprising: an amplifier circuit (10) connected to the output of said solid-state image pick-up device for amplifying the output signal of said solid-state image pick-up device and a first buffer amplifier circuit (20) in voltage follower construction connected to the output of said amplifier circuit (10) characterized in that said first buffer amplifier circuit (20) has a gain substantially 1 and includes an operational amplifier (20A) with a positive and a negative input terminal, and a source follower circuit (20B) connected to the output of the operational amplifier (20A), whereby the positive input terminal of the operational amplifier (20A) is connected to the output of said amplifier circuit (10) and the output signal from the source follower circuit (20B) is applied to the negative input terminal of the operational amplifier (20A) as a negative input so as to form a negative feedback loop. An output circuit for a solid state image pick-up device as set forth in claim 1, characterized by further comprising a filter circuit (50) forming a series circuit with said amplifier (10). An output circuit for a solid-state image pick-up device as set forth in claim 2, characterized in that said filter circuit (50) is an active low-pass filter. An output circuit for a solid-state image pick-up device as set forth in any one of claims 1 to 3, characterized by further comprising a sample/hold circuit (30). An output circuit for a solid-state image pick-up device as set forth in claim 2 or 3 which provides a second buffer amplifier circuit (60), which is connected to the output of said filter circuit (50), said first buffer amplifier circuit being connected between the output of said amplifier (10) and the input of said filter circuit (50). An output circuit for a solid-state image pick-up device as set forth in claim 4, which provides a second buffer amplifier circuit (40), which is connected to the output side of said sample/hold circuit (30), said first buffer amplifier circuit being connected between the output of said amplifier (10) and the input of said sample/hold circuit (30). An output circuit for a solid-state image pick-up device as set forth in claim 4, which provides a second and third buffer amplifier (40, 60), said first buffer amplifier circuit (20) being connected between the output of said amplifier (10) and the input of said sample/hold circuit (30), the input of said second buffer amplifier circuit (40) being connected to the output of said sample/hold circuit (30), and the output thereof being connected to said filter circuit (50), and input of said third buffer amplifier circuit (60) being connected to the output of said filter circuit (50). An output circuit for a solid-state image pick-up device according to claim 1 characterized in that said amplifier circuit (10) includes a NMOS transistor (11) having a gate connected to the output of said solid-state image pick-up device, and a drain connected to a power source, said NMOS transistor is switched between conductive state and non-conductive state by said output signal of said solid-state image pick-up device applied to said gate for outputting an output signal from the source of said NMOS transistor (11); and said buffer amplifier circuit (20) includes first, second and third NMOS transistors (21, 22, 26) and first and second PMOS transistors (23, 24), said first NMOS transistor (21) has a gate connected to said source of said NMOS transistor (11) of said amplifier circuit (10), said first and second NMOS transistors (21, 22) and said first and second PMOS transistors (23, 24) are cooperative to each other for forming the operational amplifier (21-25) to output an output signal from the drain of said second NMOS transistor (22), said third NMOS transistor (26) has a gate connected to said drain of said second NMOS transistor (22) and a drain connected to the power source for outputting the output signal of said buffer amplifier (20) from the source thereof. An output circuit for a solid-state image pick-up device as set forth in claim 8, characterized by further comprising an active low-pass filter circuit (50) forming a series circuit with said amplifier circuit (10), which active low-pass filter (50) includes first and second MOS transistors (51a, 51b) and first and second capacitors (52a, 52b), said first MOS transistor (51a) having a source connected to output of said buffer amplifier circuit (20) and a gate connected to the power source for controlling charging and discharging of said first capacitor (52a), said second MOS transistor (51b) having a source connected to a drain of said first MOS transistor (51a) and a gate connected to the power source for controlling charging and discharging of said second capacitor (52b), and said first and second MOS transistors (51a, 51b) and said first and second capacitors (52a, 52b) forming a time constant circuit. An output circuit for a solid-state image pick-up device as set forth in claim 9, characterized by further comprising a second buffer amplifier circuit (40) connected to the input of said active low-pass filter circuit (50), said second buffer amplifier circuit (40) including fifth, sixth and seventh NMOS transistors (41, 42, 46) and third and forth PMOS transistors (43, 44), said fifth NMOS transistor (41) having a gate connected to receive output of said amplifier circuit (10), said fifth and sixth NMOS transistors (41, 42) and said third and fourth PMOS transistors (43, 44) being cooperative to each other for forming an operational amplifier to output an output signal from drain of said sixth NMOS transistor (42), said seventh NMOS transistor (46) having a gate connected to said drain of said sixth NMOS transistor (42) and a drain connected to the power source for outputting the output signal of said buffer amplifier (40) from the source thereof. An output circuit for a solid-state image pick-up device as set forth in claim 9 or 10, characterized by futher comprising a third buffer amplifier circuit (60) provided at the output of said active low-pass filter circuit (50), said third buffer amplifier circuit (60) including eighth, nineth and tenth NMOS transistors (61, 62, 66) and fifth and sixth PMOS transistors (63, 64), said eighth NMOS transistor (61) having a gate connected to drain of said second MOS transistor (51b), said eighth and nineth NMOS transistors (61, 62) and said fifth and sixth PMOS transistors (63, 64) being cooperative to each other for forming an operational amplifier to output an output signal from drain of said nineth NMOS transistor (62), said tenth NMOS transistor (66) having a gate connected to said drain of said nineth NMOS transistor (62) and a drain connected to the power source for outputting the output signal of said third buffer amplifier (60) from the source thereof. An output circuit for a solid-state image pick-up device as set fourth in anyone of claims 8 to 11, characterized by further comprising a sample/hold circuit (30) including a switching transistor (31) and a sample/hold capacitor (32), said switching transistor (31) having a source connected to output of said first buffer amplifier circuit (20) and a gate connected to a sample/hold pulse source.

Inventors: KONDA TETSUYA, MAKI YASUHITO, NARABU TADAKUNI, KONDA, TETSUYA, MAKI, YASUHITO, NARABU, TADAKUNI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1988
Main classification: H04N3
IPC codes: H04N5, G11C27