Phase shift circuit

Abstract: A phase shift circuit used in a regenerating repeater, comprising; a separating unit (31) for separating an input signal into two separate signals having a phase difference of a phase angle of 90° therebetween, one separated signal having a "0" phase and the other separated signal having a "π/2" phase; a distributing unit (32) for distributing the "0" phase separated signal and "π/2" phase separated signal as three distributed signals having phase difference of phase angles of 90° and 180° therebetween, one distributed signal having a "0" phase and the others being a "π/2" phase distributed signal and a "π" phase distributed signal; and a weight­ ing/compounding unit (33) for analyzing the "0" phase dis­ tributed signal, "π/2" phase distributed signal, and "π" phase distributed signal regarding a plurality of phase signals each having a phase shift extent, for com­ pounding each of the phase signals after being weighted by each amplitude, the weighting being performed by an weight control signal applied from an external stage, and for generating an output signal adding a phase shift proportional to the weight to the input signal.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift circuit, more particularly, it relates to a phase shift circuit enabling an arbitrary phase shift of an input signal of from 0° to 360°, to obtain a phase-shifted output signal. The phase shift circuit according to the present invention is constituted by a plurality of semiconductor elements, and filters consisting of variable L, C, R elements are not employed, and thus it is possible to easily and arbitrarily realize a phase shift of the input signal in a wide band and high frequency area. 2. Description of the Related Art Various types of phase shift circuits for shifting the phase of the input signal to an arbitrary phase are widely used in the electronics field. Two well-known types of phase shift circuits are an LCR-circuit using inductors, capacitors and resistors by which the desired phase is obtained by adjusting the inductance, capacitance, and resistance, and a delay line by which the desired phase is obtained by adjusting the length thereof. Almost all phase shift circuits are directed to an input signal having a relatively low frequency area, for example, under several tens of mega hertz (MHz), and very few phase shift circuits are directed to an input signal having a high frequency area, for example, several hundreds of MHz, and enabling a phase shift of the input signal of from 0° to 360°. JP-A-52 30 362 shows a controllable phase shifter having a separator and a weighter/compounder, and means for combining weighted phase shifted signals to give an output signal. SUMMARY OF THE INVENTION The object of the present invention is to provide a phase shift circuit enabling a phase shift of from 0° to 360° of an input signal having a relatively high frequency, using a plurality of semiconductor elements. In accordance with one aspect of the present invention, there is provided a phase shift circuit having a phase shift extent of from 0° to 90° x n° comprising a separating unit for inputting an input signal and outputting 0° and 90°d-signals, a first distributing unit for inputting 0°s-signals and outputting 0° and 180°d-signals, a second distributing unit for inputting 90°s-signals, "n-1" pairs of weighting/compounding units inputting 0°, 90°, 180°d-signals and outputting phase signals having phase shift extents of from 0° to 90 x (n-1) ° and from 90° to 90 x n°, and an n'th weightin/compounding unit inputting phase signals having phase shift extents of from 0° to 90 x (n-1) ° and from 90° t0 90 x n° and outputting a phase signal having a phase shift extent of from 0° to 90 x n°. Other aspects of the invention are set out in claims 14 and 16. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Fig. 1 is a schematic block diagram of a regenerating repeater provided midway in a transmission line ; Fig. 2 is a block diagram of a phase shift circuit using a filter consisting of inductors, capaCitors and resistors, Fig. 3 is a graph for explaining a phase shift of the filter shown in Fig. 2; Fig. 4 is a graph for explaining waveforms of the input signal and the output signal; Fig. 5 is a view for explaining the principle of the present invention; Fig. 6 shows a basic structures of the phase shift circuit according to the present invention; Fig. 7 is a schematic block diagram of the phase shift circuit according to an embodiment of the present invention; Fig. 8 is one example of a circuit of the separating unit shown in Fig. 7; Fig. 9 is a plan view of a complex number of explaining the phase difference between the first and second signals; Fig. 10 is one example of the distributing circuit shown in Fig. 7; Fig. 11 is another example of the distributing circuit shown in Fig. 7; Fig. 12 is one example of the weighting/compounding circuit shown in Fig. 7; Fig. 13 is another example of the weighting/compounding circuit shown in Fig. 7; Fig. 14 is one example of the weighting/compounding circuit having an amplitude fluctuation compensating circuit; Fig. 15 is a graph for explaining the amplitude fluctuation; Fig. 16 is a graph for explaining the relationship between the amplitude and the sum of the weight currents; Fig. 17 is a graph for explaining the relationship between the voltage of the weight control signal and the sum of the weight currents; Fig. 18 is one example of the amplitude fluctuation compensating circuit; Fig. 19 is one example of the compensation control circuit; Fig. 20 is a graph for explaining each voltage in the compensation control circuit shown in Fig. 19; Fig. 21 is a partial block diagram of the regenerating repeater including the phase shift circuit according to the present invention; Fig. 22 is a basic structure of another example of the separating unit according to the present invention; Fig. 23 is a detailed structure of the phase shift circuit shown in Fig. 22; Fig. 24 is a block diagram of another embodiment of the phase shift circuit according to the present invention; Fig. 25 is a block diagram of still another embodiment of the phase shift circuit according to the present invention; Figs. 26 and 27 are block diagrams for explaining the general form of the phase shift circuit according to the present invention; Fig. 28 is a still another embodiment of the phase shift circuit according to the present invention; and Fig. 29 is a block diagram of an automatic phase control circuit to which the present invention is applied. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the preferred embodiments, an explanation will be given of a conventional phase shift circuit. Figure 1 is a schematic block diagram of a regenerating repeater provided midway in a transmission line and mainly carrying out a correction of the distortion of the waveform and amplification of the attenuated signal. In Fig. 1, 11 denotes an equalizing amplification circuit, 12 a timing extraction circuit, 13 a phase adjusting means, 14 a discriminating circuit, and 15 a regenerating circuit. The equalizing amplification circuit 11 is provided for compensating the attenuation of an input signal IN and the delay of the propagation time at each frequency, and outputting a compensated signal DT. The timing extraction circuit 12 extracts a clock signal CK based on the signal DT and outputs the clock signal CK to the discriminating circuit 14 through the phase adjusting means 13. The discriminating circuit 14 detects a high level "1" and a low level "0" of the signal DT based on a predetermined threshold level to eliminate noise in the signal DT. The regenerating circuit 15 regenerates the input signal based on the discriminating signal "1" and "0", and outputs an output signal OUT to the transmission line. In the discriminating circuit 14, when the sampling of the signal DT is performed by the clock signal CK, the sampling is performed in the vicinity of the central portion of each signal DT, to eliminate noise, and the signal DT is discriminating at every one bit of the clock signal CK. This sampling can be precisely performed when the speed of the signal DT is relatively low, but sometimes, this sampling fails when the speed of the signal DT is very high because of a narrow pulse width of each bit and jitter of the signal DT. For example, when the transmission line is an fiber, the speed of the signal DT is several hundred mega bits per second (Mb/s). In this case, it is necessary to the phase of the signal DT must be precisely synchronized with that of the clock signal CK at the vicinity of the central portion of the signal DT in the regenerating circuit 15. Therefore, the shift angle of the clock signal CK must be adjusted to be positioned at the vicinity of the center. Note, an optical-to-electric transducer must be provided at the input side, and an electric-to-optical transducer at the output side, in the regenerating repeater 10. Conventionally, when the phase adjusting means 13 is constituted by a delay line, the above phase synchronization between the signal DT and the clock signal CK is performed by slightly advancing or delaying the phase of the clock signal CK in such a manner that the delay line (cable) 13 is gradually and manually cut, by observing the waveforms displayed on the oscilloscope. It is, however, troublesome to adjust the phase, and further, it is difficult to obtain a precise result because the operation is manually conducted. An explanation is given hereinafter of a phase adjusting means 13 constituted by a filter consisting of an inductor, a capacitor, and a resistor. Figure 2 is a block of a phase shift circuit using a filter consisting of inductors (L), capacitors (C), and resistors (R). This phase shift circuit 20 is provided in the phase adjusting means 13. The input signal S in and the output signal S out have a frequency f 0 , but the phase of the output signal S out is different from that of the input signal S in . To adjust the phase difference, the phase control signal S c is applied from an external stage (not shown) to the phase shift circuit, and the center frequency f c of the filter is shifted by the phase control signal S c . Figure 3 is a graph for explaining the phase shift of the filter shown in Fig. 2. In Fig. 3, the ordinate is a gain, and the abscissa is a frequency. The center frequency f c is shifted to the frequency f ca by changing the phase control signal S c so that the phase difference Δ is added to the input signal S in . Figure 4 is a graph for explaining the waveforms of the input signal S in and the output signal S out . In Fig. 4, the dotted line denotes the output signal shifted by the phase difference Δ. As explained above, the phase shift circuit 20 is constituted by a filter consisting of the inductor L, capacitor C, and resistor R, and accordingly, a variable inductor and variable capacitor must be provided for adjusting the center frequency, and therefore, it is difficult to obtain a wide band filter. Further, it is difficult to adjust the variable inductor and the variable capacitor when the frequency of the input signal becomes high, and still further, these elements are too large to enable a miniaturization of the phase shift circuit. Therefore, the object of the present is to provide a phase shift circuit constituted by a plurality of semiconductors, enabling an integration circuit and an adjustment of the phase shift of the input signal of from 0° to 360°. Figure 5 is a view for explaining the principle of the present invention. In Fig. 5, SU is a separating unit. When a waveform of the input signal S in is expressed by "cos", the signal having the phase difference 90° is given by "sin". Accordingly, the combined signal cos and sin is given by the formula, √ a 2 + b 2 cos( - ) Where, "a" and "b" are an amplitude of the signal, "" is a shift angle and expressed by tan -1 (b/a). Accordingly, the shift angle  can be adjusted by controlling both amplitudes "a" and "b" of the signals cos and sin, as explained in detail hereinafter. As is obvious, since the maximum shift angle  is 90°, the shift angle of from 0° to 360° can be obtained by combining a plurality of sets of the shift angle from 0° to 90°. Figure 6 is a basic structure of the phase shift circuit according to the present invention. In Fig. 6, 31 denotes a separating unit, 32 a distributing unit, and 33 a weighting/compounding unit. The separating unit 31 receives the input signal S in and generates the first signals S s0 and the second signal S s90 . The first signal S s0 has the same phase as that of the input signal S in , and the second signal S s90 has a phase difference of 90° (π/2) from the first signal S s0 . The distributing unit 32 receives the signal S s0 and the signal S s90 and generates the "0" phase distributed signal S d0 , "π/2" phase distributed signal S d90 , and "π" phase distributed signal S d180 . The distributing unit 32 is basically provided for obtaining a phase difference of 180° between two output signals. The weight/compounding unit 33 receives the signals S d0 , S d90 , S d180 , analyzes these signals regarding various kinds of the phase signals each having a predetermined phase shift extent, and compounds the phase signals after weighting the amplitude. In this case, a weight control signal S w is applied to the weighting/compounding unit 33 for deciding the above weight of the amplitude. The phase shift angle  of the output signal S out to the input signal S in is based on the weighted amplitude. As shown in Fig. 5, the signal S s0 is expressed by "cos " and the signal S d90 is expressed by "sin", accordingly, the weighting/compounding unit 33 calculates the following formula, a cos + b sin = a 2 + b 2 cos( - ), and controls the ratio "a : b" of the amplitude "a" and "b" based on the weight control signal S w . Therefore, various kinds phase shift signals each having a separated phase shift extent must be provided to cover the shift angle  from 0° to 360°, as explained in detail hereinafter. As is obvious from the above explanation, since the phase shift circuit according to the present invention can control the phase shift angle  based on the typical phase shift signals of 0°, 90° and 360°, the variable inductor and capacitor are not needed for adjusting the shift angle and it is possible to realize the adjustment by using only a plurality of semiconductors. Figure 7 is a schematic block diagram of the phase shift circuit according to an embodiment of the present invention. In Fig. 7, the distributing unit 32 comprises a first distributing unit (FDU) 321 and a second distributing unit (SDU) 322. The FDU 321 receives the signal S s0 , and the SDU 322 receives the signal S s90 . The FDU 321 generates two distributed signals S d0 and S d180 having the phase difference 180° therebetween, and the SDU 322 generates two distributed signals S d90 and a 3π/2 phase distributed signal, but the 3π/2 phase distributed signal is not used in this circuit. The weighting/compounding unit 33 comprises seven weighting/compounding units 331 to 337 (WCU 1 to WCU 7) each having the same structure. Each of the WCU's receives the weight control signal S w in common. If the weight control signal is different at each WCU, the phase shift extent as shown in the drawing can not be always obtained. The phase signals, each of which is received and output by each of the WCU's, are denoted by S P1 to S P7 . The phase signal S P7 is similar to the output signal S out . Each phase signal comprises the phase shift extent shown by 0° to 90°, 90° to 180°, 90° to 270°, etc., in the drawing. Various transmission routes of the phase signal are formed from the separating unit 31 to the WCU 7 and the output signal S out is generated from the WCU 7. Figure 8 is one example of a circuit of the separating unit shown in Fig. 7. In Fig. 8, the separating unit 31 is constituted by resistors R 1 , R 2 and capacitors C 1 , C 2 , to obtain a constant amplitude. The input signal S in is input to the common connection point P. The first output signal S s0 45° advanced in phase to the input signal is output from the common connection point P 1 and the second output signal S s90 45° delayed in phase to the input signal is output from the common connection point P 2 . Figure 9 is a plan view of a complex number for explaining the phase between the first and the second signal. The ordinate is an imaginary number axis and the abscissa is a real number axis. The conditions for obtaining the phase difference 90° between the input and the output signal are explained in detail as follows: V out1 = R 1 R 1 - j/ωC 1 ·V in V out2 = -j/ωC 2 R 2 - j/ωC 2 ·V in Where, V in is the voltage of the input signal, and V out1, 2 are the voltages of each output signal. Accordingly, when R 1 and R 2 are given by R 1 = 1/ωC 1 R 2 = 1/ωC 2 and as a result, V out1 = (1 + j) V in /2 V out2 = (1 - j) V in /2 Therefore, the phase difference 90° between the output signals is obvious from the above formulae (5) and (6). Figure 10 is one example of the distributing circuit shown in Fig. 7. This circuit is constituted by a differential amplifier. In Fig. 10, V ref denotes a reference voltage, I denotes a constant current source, and V cc denotes a power source. When the voltage of the input signal S s0 is higher than the reference voltage V ref , the output signal S d180 is output from the point P 3 . When the voltage of the input signal is lower than the reference voltage V ref , the output signal S d0 is output from the point P 4 . This circuit can obtain a phase difference of 180° between two output signals. Figure 11 is another example of the distributing circuit shown in Fig. 7. This circuit is constituted by only one NPN-type or PNP-type transistor 61. In Fig. 11, the transistor 61 is an NPN-type. When the input signal S s0 is input to the base of the transistor, the output signal S d0 having a phase "0°" is output from the emitter when the input signal is high, and the output signal S d180 having a phase of "180°" therefrom is output from the collector when the input signal is low. When a PNP-type transistor is used, the above output signal is inverted. Figure 12 is one example of the weighting/compounding circuit shown in Fig. 7. This circuit is constituted by a first differential amplifier 71, a second differential amplifier 72 and a third differential amplifier 73. I denotes a constant current source. V ref1 , V ref2 , and V ref3 are references voltage, and I a and I b are emitter currents (below, weight currents). The distributed signal S d0 is input to the first differential amplifier 71, the signal S d90 is input to the second differential amplifier 72, and the weight control signal S w is input to the third differential amplifier. The phase signals S P1 and S P1a are output from the collectors of the differential amplifiers 71 and 72. The third differential amplifier 73 takes the weight currents I a and I b from common emitters of the first and second differential amplifiers 71 and 72. This type is advantageous when forming an integrated circuit, and a stable operation can be obtained by the differential input. The current ratio between the weight currents I a and I b depends on the voltage balance between the voltage of the weight control signal S w and the reference voltage V ref , as explained in detail hereinafter. The current ratio I a : I b is equivalent to the amplitude ratio "a : b" at the formula of the shift angle  (= tan -1 (b/a)), and accordingly, the shift angle  can be arbitrarily adjusted based on the control of the weight currents I a and I b . For example, when the reference voltage V ref3 is 0 (v) and the voltage of the weight control signal is changed between ±3 (v), the weight currents I a and I b can be changed between a maximum value and a minimum value. In this case, since the sum of the current I a and I b becomes a constant current value I R , the current I a is maximum when the current I b is minimum, and the current I a is minimum when the current I b is maximum. When the amplitude ratio "a : b" is changed from "1 : 0" to "0 : 1", the shift angle  can be changed from 0° to 90°. Accordingly, since the phase shift extent of the phase signal S p1 is from 0°to 90°, as shown in Fig. 7, the current I a is minimum and the current I b is maximum when the phase signal S p1 is set to 0°, and the current I a is maximum and the current I b is minimum when the phase signal S p1 is set to 90°. Further, the current I a is equal to the current I b (i.e., a half of the current I R ) when the phase signal S p1 is set to 45°. As explained above, the level of the current depends on the voltage of the weight control signal. For example, when the voltage of the weight control signal is ± (v), the current I a is maximum (current I b is minimum), and when the voltage of the weight control signal is -3 (v), the current I a is minimum (current I b is maximum). The phase signals S p1 and S p1a can be obtained by compounding each distributed signal S d0 and S d90 , since the load resistors 74 and 75 are common thereto. Namely, the phase signal S p1 can be obtained because the load resistor 74 is common to the transistors 711 and 721. Similarly, the phase signal S p1a can be obtained became the load resistor 75 is common to the transistors 712 and 722. Figure 13 is another example of the weighting/compounding circuit shown in Fig. 7. In Fig. 13, 81 and 82 are NPN-type transistors and 83 and 84 are variable resistors. The phase signal S p1 is output from the collector of the transistors 81 and 82. The distributed signal S d0 is input to the base of the transistor 81, and the distributed signal S d90 is input to the base of the transistor 82. The semifixed variable resistors 83 and 84 can adjust the value of the weight currents I a and I b by rotating an arm therein. In this case, the semifixed variable resistor 83 is linked with the resistor 84 and these resistors are wired to obtain an inverse value between these currents. Namely, when the current I a is large, the current I b becomes small. The weight control signal S w is not necessary in this type circuit because the semifixed resistor is previously adjusted. In general, such a semifixed variable resistor can be used in the regenerating repeater because, once the phase of the clock signal is adjusted by the semifixed variable resistor, the phase adjustment is not frequently performed after the initially adjustment. Figure 14 is one example of the weighting/compounding circuit having an amplitude fluctuation compensating circuit. The amplitude fluctuation compensating circuit 90 is provided instead of the constant current source I shown in Fig. 12: I c is a sum of the weight current I a and I b . An explanation of why such a compensating circuit is necessary is given hereinafter. When each gain of the first and second differential amplifiers 71 and 72 is G 1 and G 2 , the formula, a 2 + b 2 cos( - ) can be expressed by, ± G 1 2 + G 2 2 cos( - ) Since the weight currents of the these amplifiers are I a and I b , the gains G 1 and G 2 are expressed by, G 1 = R L ÷ (V T /I a + R e ) G 2 = R L ÷ (V T /I b + R e ) Where, R L is a resistance value of each of the load resistors 74 and 75, and R e is a resistance value of each of the emitter resistors 76 to 79 of the transistors 711, 712, 721, and 722. Further, V T is expressed by the formula, V T = kt/q Where, k is Bolzman constant, T is an absolute temperature, q is a charge quantity, and V T /I a and V T /I b are emitter resistance values of the transistor. From the above formulae (6) to (8), since the gain is decided by the ratio of the load resistance value R L and the emitter resistance value R e , which changes in accordance with the emitter current, it is obvious that the gains G 1 and G 2 change in response to the fluctuation of the weight currents I a , I b . This fluctuation is not preferable when performing a more precise phase shift operation, and therefore, the amplitude fluctuation compensating circuit must be provided in the weighting/compositing circuit. The fluctuation of the amplitude is explained hereinafter. Figure 15 is a graph for explaining the amplitude fluctuation. In Fig. 15, the ordinate is an amplitude of the phase signal S p1 , S p1a , and the abscissa is a voltage of the weight control signal S w . As is obvious from the drawing, the amplitude becomes maximum when the voltage of the weight control signal is equal to the reference voltage V ref3 . Figure 16 is a graph for explaining the relationship between the amplitude and the sum of the weight currents. The ordinate is an amplitude of the phase signal, and the abscissa is a sum of the weight currents. In Fig. 16, the current I c is equal to the sum of the weight current I a and I b . As is obvious from the graph, the relationship between the amplitude and the current is approximately linear, and the greater the amplitude, the smaller the current. Figure 17 is a graph for explaining the relationship between the voltage of the weight control signal and the sum of the weight currents. As is obvious from the graph, the current I c becomes minimum when the voltage of the weight control signal is equal to the reference voltage V ref3 . Figure 18 is one example of the amplitude fluctuation compensating circuit. This circuit is constituted by a compensation control circuit 91 and a current source circuit 92. The current source circuit 92 is controlled by a compensation control voltage V c . The relationship between the voltage V c and the voltage V w is shown in Fig. 17. The compensation control circuit is described in detail hereinafter. Figure 19 is one example of the compensation control circuit. In Fig. 19, 100 denotes a differential amplifier, 101 denotes a voltage compositing circuit. 102 is a level shifter for adjusting the compensation control voltage V c to drive the current source circuit 92. This circuit 102 is constituted by a plurality of diodes for obtaining a voltage drop. The compensation control voltage V c is obtained from output voltages V 1 and V 2 of the differential amplifier 100. The voltage V w is the voltage of the weight control signal S w . Figure 20 is a graph for explaining each voltage in the compensation control circuit shown in Fig. 19. Namely, this graph shows the relationship between the compensation control voltage V c and the weight control signal voltage V w . The dotted line V c is defined by the curves of the voltage V 1 and V 2 . The curve of the voltage V c corresponds to the curve shown in Fig. 17, and accordingly, the weight current I c is controlled in response to the control voltage V c . Figure 21 is a partial block diagram of the regenerating repeater including the phase shift circuit according to the present invention. In Fig. 21, reference number 111 denotes a filter and 112 denotes a limiting amplifier. The phase shift circuit 30 according to the present invention is provided between the filter 111 and the limiting amplifier 112. The clock signal CK is output from the limiting amplifier 112. 110 is a timing circuit and is constituted by the timing extraction circuit 12, the filter 111, the phase circuit 30, and the limiting amplifier 112. Since the phase shift circuit 30 is provided between the filter 111 and the limiting amplifier 112, it is possible to eliminate the jitter in the clock signal CK. This is because the gain of the limiting amplifier 112 is very high, and thus it is possible to shape the waveform of the clock signal CK. Figure 22 is a basic structure of another example of the separating unit according to the present invention. This circuit can compensate a frequency change of the input signal and maintain the phase shift quantity of the output signal at a constant value. As explained above, the separating circuit shown in Fig. 8 is constituted by resistors and capacitors, so that the output signals are given by the formulae (5) and (6). Accordingly, it is necessary to satisfy the formulae (3) and (4) to obtain the precise phase difference 90° between the output signal V out1 and the output signal V out2 . In this case, when the resistance R 1 is equal to R 2 and the capacitance C 1 is equal to C 2 , the resistance R is given by 1/ωC from the formulae (3) and (4). Therefore, the frequency of the input signal f 0 is given by, f 0 = ω/2π = 1/2πCR Accordingly, the frequency f 0 can be obtained from the values of the resistor and capacitor. Therefore, when the frequency f 0 changes, the phase difference between the output signals also changes from 90°, and thus it is difficult to maintain the phase difference between the output signals for the change of the frequency of the input signal V in . To solve the above problem, there is provided a phase shift circuit enabling a compensation of a change of the input frequency shown in Fig. 22. In Fig. 22, 120 denotes a RC phase shift circuit, 121 a comparison circuit, and V cnt a control signal. The RC phase shift circuit 120 is constituted by variable capacitors and resistors, or by variable resistors and capacitors. The comparison circuit 121 compares the voltage of the input signal V in with the voltage of the output signals V out1 or V out2 and outputs the control signal V cnt to obtain a predetermined ratio between the input signal and the output signal. Figure 23 is a detailed structure of the phase shift circuit shown in Fig. 23. In Fig. 23, 1 denotes a phase circuit, 2 a peak detecting circuit, 3 an error detecting circuit, and 4 a coefficient circuit. The phase circuit 1 is constituted by resistors 130 and 131, and voltage control type variable capacitors 140 and 141. The resistor 130 and the variable capacitor 140 constitute a low pass filter, and the output signal V out1 is controlled to be advanced by the phase difference of 45° to the input signal. The resistor 131 and the variable capacitor 141 constitute a high pass filter, and the output signal V out2 is controlled to be delayed by the phase difference of 45° to the input signal. Accordingly, it is possible to obtain a phase difference of 90° between the output signals. The peak detecting circuit 2 detects a peak value of the output signal V out1 and a detected peak value is input to one input terminal of the error detecting circuit 3. The coefficient circuit 4 multiplies the input signal V in by the coefficient 1/2, and the multiplied output is input to the other input terminal of the error detecting circuit 3. The output of the error detecting circuit 3 is input to a voltage control terminal T c of the variable capacitors 140 and 141. The operation of the phase shift circuit is explained as follows. As explained above, the following relationship must be established to maintain the phase difference of 90° between the output signals R 1 = 1/ωC v1 R 2 = 1/ωC v2 When the above formulae are satisfied, the output signal V out1 has the phase angle of 45° to the input signal V in and the amplitude of the output signal V out1 is expressed as follows from the formula (5). |V out1 | = V in / 2 The same relationship as in formula (9) is given to the output signal V out2 . To maintain the phase difference of 90° between the output signals V out1 and V out2 on a change of the frequency of the input signal V in , the formulae (7) and (8) must be satisfied. To satisfy the formulae (7) and (8) on a change of the input frequency f 0 , it is necessary to change the capacitances C v1 and C v2 of the capacitors 140 and 141. Accordingly, the peak detecting circuit 2 detects the peak value of the amplitude of the output signal V out1 , and the error detecting circuit 3 compares the peak value with the output signal V in / 2 and outputs the control signal V cnt to adjust the capacitance of the capacitors 140 and 141 so that the peak value becomes equal to the V in / 2 . As a result, it is possible to maintain a precise phase difference of 90° between the output signals and the input signal V in . Although the above embodiment uses variable capacitors and fixed resistors, it is possible to provide variable resistors and fixed capacitors to the extent that fluctuation of the input impedance is negligible. Figure 24 is a block diagram of another embodiment of the phase shift circuit according to the present invention. This phase shift circuit can shift the phase shift angle from 0° to 90°. As is obvious from the drawing, this circuit is only constituted by the separating unit 31 and the weighting/compounding unit 331, and the distributing unit 32 for obtaining the phase difference of 180° therebetween is not provided. A detailed circuit diagram can be obtained by combining the circuits shown in Figs. 8 and 12. Although the 0° to 90° phase shift circuit is explained in this embodiment, it is possible to obtain other variations by changing the setting of the weighting/compounding circuit as explained hereinafter. Figure 25 is a block diagram of another embodiment of the phase shift circuit according to the present invention. This circuit can shift the phase shift angle from 0° to 180°. This circuit is constituted by the separating unit, two distributing units, and three weighting/compounding units, so that it is possible to obtain a phase shift angle of from 0° to 180° from the final stage. Figures 26 and 27 are block diagrams for explaining a general form of the phase shift circuit according to the present invention. In the circuit shown in Fig. 26, "n-1" pairs of the WCU's and one WCU are provided for obtaining the phase shift angles of from 0° to 90 x n°. Where, "n" is 1, 2, .... In the circuit shown in Fig. 27, each stage is constituted by the phase shift circuit shown in Fig. 24. Figure 28 is still another embodiment of the phase shift circuit according to the present invention. In Fig. 28, SA is a surface acoustic waves (SAW) filter constituted by an input transducer D in and two output transducers D out1 and D out2 . In general, the SAW filter is able to change the phase difference between the input signal and the output signal. The phase difference can be obtained by changing the distance between the input transducer and the output transducer. Accordingly, it is possible to obtain the output signals OUT1 and OUT2 each having phase differences 0° and 90° to the input signal IN by providing two output transducers D out1 and D out2 . The delay times t 1 and t 2 of the output signals OUT1 and OUT2 to the input signal are given by the following formulae. t 1 = (L 1 + PK)/v s t 2 = (L 2 + PK)/v s Where, P is a pitch between each of comb line type electrodes, K is a number of pairs of comb line type electrodes, and L 1 and L 2 are distances between the input transducer and the output transducer. Figure 29 is a block diagram of an automatic phase control circuit to which the present invention is applied. In Fig. 29, 151 denotes a discriminating circuit, 152 a phase comparing circuit, 153 a reference voltage generating circuit, 154 a phase difference detecting circuit, 155 a phase shift circuit according to the present invention, and 156 an amplifier. The feature of this automatic phase control circuit 150 lies in the use of the phase shift circuit 155 for changing the phase of the input signal. In this circuit, the phase comparing circuit 152 compares an input data D in with the phase of the clock signal (output data) D out and outputs a phase detecting signal V s as the resultant data. Although the phase comparing circuit compares the input data with the output data, this is equivalent to a comparison with the phase of the input clock signal since the output data is synchronized with the input clock signal. The reference voltage generating circuit 153 generates the reference voltage V ref when the phase relationship between the input data and the input clock signal becomes optimal. The phase difference detecting circuit 154 detects the difference between the phase detecting signal V s and reference signal V ref , and generates a control voltage signal V CONT . For example, when the phase is slipped between the input data and the input clock signal, the level of the phase detecting signal V s changes and a difference between the signal V s and the signal V ref arises. This difference is detected by the phase difference detecting circuit 154, and the phase control voltage V CONT is changed. The phase utilizes the phase control voltage signal V CONT as the weight control signal S w . As explained above, the phase of the input clock signal can be adjusted based on the weight control signal S w through the amplifier 156. The amplifier 156 amplifies the amplitude of an output clock signal C from the phase shift circuit 155 and shapes the waveform of the output clock signal C.

Claims: A phase shift circuit having a phase shift extent of from 0° to 90° x n° comprising a separating unit for inputting an input signal and outputting 0° and 90°d-signals, a first distributing unit for inputting 0°s-signals and outputting 0° and 180°d-signals, a second distributing unit for inputting 90°s-signals, "n-1" pairs of weighting/compounding units inputting 0°, 90°, 180°d-signals and outputting phase signals having phase shift extents of from 0° to 90 x (n-1) ° and from 90° to 90 x n°, and an n'th weighting/compounding unit inputting phase signals having phase shift extents of from 0° to 90 x (n-1) ° and from 90° t0 90 x n° and outputting a phase signal having a phase shift extent of from 0° to 90 x n°. A phase shift circuit as claimed in claim 1, where said distributing means comprising a first (321) and a second (322) distributing units inputting the "0" phase separated signal and the "π/2" phase separated signal ; and said weighting/compounding means comprises a first weighting/compounding unit (331) inputting an "0" phase distributed signal and a "π/2" phase distributed signal and outputting two phase signals having a phase shift extent of from 0° to 90° and from 180° to 270°, a second weighting/compounding unit (332) inputting a "π/2" phase distributed signal and a "π" phase distributed signal and outputting a phase signal having a phase shift extent of from 90° to 180°, a third weighting/compounding unit (333) inputting two phase signals having a phase shift extent of from 0° to 90° and from 90° to 180° and outputting two phase signals having a phase shift extent of from 0° to 180° and from 180° to 360°, a fourth weighting/compounding unit (334) inputting two phase signals having a phase shift extent of from 90° to 180° and from 180° to 270° and outputting a phase signal having a phase shift extent of from 90° to 270°, a fifth weighting/compounding unit (335) inputting two phase signals having a phase shift extent of from 0° to 180° and from 90° to 270° and outputting a phase signal having a phase shift extent of from 0° to 270°, a sixth weighting/compounding unit (336) inputting two phase signals having a phase shift extent of from 90° to 270° and from 180° to 360° and outputting a phase signal having a phase shift extent of from 90° to 360°, and a seventh weighting/compounding unit (337) inputting two phase signals having a phase shift extent of from 0° to 270° and from 90° to 360° and outputting a phase signal having a phase shift extent of from 0° to 360°. A phase shift circuit as claimed in claim 2, wherein said separating means comprising a first CR circuit consisting of a series-connected resistor R 1 and capacitor, C v1 and a second CR circuit consisting of a series-connected resistor R 2 and capacitor, C v2 said first and second CR circuit being connected in series, said input signal being input to a common connection point of said first CR circuit and second CR circuit, said "0" phase separated signal being output from a common connection point of said resistor and capacitor in the first CR circuit, and said "π/2" phase separated signal being output from a common connection point of said resistor and capacitor in the second CR circuit. a phase shift circuit as claimed in claim 2, wherein each of said first and second distributing units comprises a differential amplifier having a pair of transistors, said separating signal being input to a base of one transistor, a reference voltage being to a base of the other transistor, and said distributing signal being output from any collector of said pair of transistor. A phase shift circuit as claimed in claim 2, wherein each of said first and second distributing units comprises a transistor, said said separating signal being input to a base of said transistor, and said distributing signal being output from either a collector or an emitter of said transistor. A phase shift circuit as claimed in claim 2, wherein each of said first to seventh weighting/compounding units comprises a first differential amplifier, a second differential amplifier connected in parallel to said first differential amplifier through each collector, and a third differential amplifier connected to said first differential amplifier and second differential amplifier for taking weight currents through each of emitters of said first differential amplifier and second differential amplifier, said distributing signal being input to each base of said first differential amplifier and second differential amplifier, said reference voltage being applied to the other of each base of said first differential amplifier and second differential amplifier, said weight control signal being input to a base of third differential amplifier, the other reference voltage being applied to the other base of said third differential amplifier, and said phase signal being output from each collector of said first differential amplifier and second differential amplifier. A phase shift circuit as claimed in claim 2, wherein each of said first to seventh weighting/compounding units comprises, a pair of transistor inputting said distributing signal to each base of said transistor and outputting said phase signal from each collector of said transistor, and semifixed-resistors each connected to each emitter of said transistor for adjusting said weight current passing through said transistor. A phase shift circuit as claimed in claim 6, wherein an amplitude fluctuation compensating unit (90) for suppressing the amplitude fluctuation of said phase signal is provided to a common emitter of said third differential amplifier. A phase shift circuit as claimed in claim 8, wherein said amplitude fluctuation compensating unit comprising a current source circuit connected to said common emitter of said third differential amplifier, and a compensation control circuit (91) connected to said current source circuit and outputting a compensation control voltage to said current source circuit for controlling said weight current based on a voltage of said weight control signal and a reference voltage. A phase shift circuit as claimed in claim 9, wherein said compensation control circuit (91) comprises a differential amplifier (100) constituted by a pair of transistors, and inputting said weight control signal to a base of one of said transistors and inputting said reference voltage to a base of the other of said transistors, and a voltage combining circuit (101) constituted by two transistors for receiving each collector voltage of said differential amplifier and for outputting said compensation control voltage. A phase shift circuit as claimed in claim 3, wherein said separating means comprises, an RC phase circuit constituted by variable capacitors and fixed resistors, or by fixed capacitors and variable resistors, for inputting said input signal and outputting said separated signals; and a comparing circuit (3) inputting said input signal and said separated signals comparing these signals, and outputting a control voltage to said RC phase circuit to obtain a predetermined ratio between said input signal and said separated signal. A phase shift circuit as claimed in claim 11, wherein said RC phase circuit comprises a first RC circuit having a resistor and a variable capacitor connected in series to said resistor, and a second RC circuit having a resistor and a variable capacitor connected in series to said resistor, said first RC circuit and second RC circuit being connected in series, said input signal being input to a common connection point of said first RC circuit and second RC circuit, one separating signal being output from said first RC circuit, and the other separating signal being output from said second RC circuit; and said comparing circuit having a peak detecting circuit (2) for detecting said separating signal and outputting a peak voltage, a coefficient circuit (4) for inputting said input signal and outputting a 1/ 2 voltage of said input signal, and an error detecting circuit for inputting said peak voltage and 1/ 2 voltage and outputting said control signal to said variable capacitors in common. A phase shift circuit as claimed in claim 1, having a phase shift extent of from 0° to 180° wherein the separating unit is for separating an input signal into two separate signals having a phase difference of 90° therebetween, the first distributing unit is for inputting a "0" phase separated signal (0°s-signal) and outputting a "0" phase distributed signal (0°d-signal) and 180°d-signal, the second distributing unit is for inputting a 90°s-signal and outputting a 90°d-signal, and the circuit comprises a first weighting/compounding unit inputting a 0° to 90°d-signals and outputting a phase signal having a phase shift extent of from 0° to 90°, a second weighting/compounding unit inputting 90° and 180°d-signals and outputting a phase signal having a phase shift extent of from 90° to 180°, and a third weighting/compounding unit inputting one phase signal having a phase shift extent of from 0° to 90° and another phase signal having a phase shift extent of from 90° to 180°, and outputting a phase signal having a phase shift extent of from 90° to 180°, and said weight control signal is input to said first, second and third weighting/compounding unit for controlling said weight current. A phase shift circuit having a phase shift extent of from 0° to 90 x n° comprising "n" pairs of a separating unit and weighting/compounding unit, each pair being connected in series, and an input signal being input to a first separating unit and a phase signal having a phase shift extent of from 0° to 90 x n° being output from said n'th weighting/compounding unit.

Inventors: KAWAI MASAAKI, OHTSUKA TOMOYUKI, WATANABE HISAKO, YAMASHITA HARUO, KAWAI, MASAAKI, OHTSUKA, TOMOYUKI, WATANABE, HISAKO, YAMASHITA, HARUO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H03H11
IPC codes: H03H11