Method and apparatus for interrupt processing

Abstract: An interrupt processing method and an interrupt processing apparatus provides end indicative information, indicating the end of a daisy chain, and a storing unit (R₁-R n ) for storing the end indicative information in at least one (e.g. U n ) of a plurality of peripheral units (U₁-U n ). When the peripheral unit (e.g. U n ) storing the end indicative information, receives an acknowledge signal (D in ) but does not output a request signal (IRR), the peripheral unit (U n ) outputs a specific chain end state signal (D end ) to the central processing unit (CPU), so that the central processing unit (CPU) is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit (CPU) is reduced. Further,the daisy chain connection can be cut at an optional portion and a request signal from an irrelevant peripheral unit (U₁-U n ) thereby ignored, so that the efficiency of the processing is improved.

Description: The present invention relates to a processing method and a processing apparatus for a computer system, more particularly, to an interrupt processing method and an interrupt processing apparatus for a computer system having a central processing unit and a plurality of peripheral units (peripheral equipment), wherein an interrupt request signal is transferred from each peripheral unit to the central processing unit, and an interrupt acknowledge signal in response to the interrupt request signal is successively propagated from the central processing unit to each peripheral unit by a daisy chain connection. The present invention also relates to an interrupt controller. At present, interrupt processing is carried out, for example, by using a daisy chain connection constructed by a plurality of peripheral units. An interrupt request signal is output from each peripheral unit to a central processing unit through a signal conductor, and when the central processing unit receives the interrupt request signal and an interrupt processing is enabled, the central processing unit outputs an interrupt acknowledge signal to the peripheral unit by using a daisy chain connection. Namely, the central processing unit first outputs the interrupt acknowledge signal to a first step peripheral unit, and if the first step peripheral unit does not output the interrupt request signal, the interrupt acknowledge signal is propagated to a second step peripheral unit, i.e., a next step peripheral unit. Therefore, as described above, the interrupt acknowledge signal is successively propagated to each peripheral unit. When the interrupt acknowledge signal is propagated to the specific peripheral unit which has output the interrupt request signal, the specific peripheral unit outputs a vector address to the central processing unit through a data bus, so that an interrupt processing routine for the specific peripheral unit is started. Note, the above peripheral units may be not only input-output devices or auxiliary storages, but also interrupt controllers. The input-output device or auxiliary storage is, for example, a cathode ray tube display, an optical mark reader, and a hard disk drive device, etc. The interrupt controller, which is used as an interrupt handler or an interrupt generator, controls a plurality of input-output devices or auxiliary storages. Note, if noise exists in the signal conductor in which the interrupt request signal is transferred, this noise may be taken as the interrupt request signal by the central processing unit. In this case, the central processing unit outputs an error interrupt acknowledge signal, without receiving a correct interrupt request signal. Therefore, none of the peripheral units outputs a response signal to the central processing unit, and thus the central processing unit is held in a response waiting state and the processing is unnecessarily delayed. "Computer Architecture and Organization" by John P. Hayes, McGraw-Hill, Int. Edition, pages 518-519, discloses a method and apparatus according to the preambles of each of accompanying claims 1, 10, and 21. In consideration of the above-mentioned problems when an error interrupt request signal is propagated to a central processing unit, it is desirable to reduce a delay in a return from a response waiting state of the central processing unit, to avoid an unnecessary waste of time. According to one aspect of the present invention, there is provided a processing method for a computer system having a central processing unit and a plurality of peripheral units, wherein a request signal is transferred from each peripheral unit to the central processing unit, and an acknowledge signal in response to the request signal is successively propagated from the central processing unit to each peripheral unit by a daisy chain connection, characterised in that the method comprises: a step for setting indicative information to an end indicative information storing means of at least one of the peripheral units; a step for outputting a specific signal notifying the central processing unit of a chain end state, from the peripheral unit at which the indicative information is set to the end indicative information storing means thereof, when the peripheral unit receives the acknowledge signal and does not output the request signal; and a step for returning the central processing unit from a response waiting state by receiving a specific signal. According to a second aspect of the present invention, there is provided a processing apparatus having a central processing unit and a plurality of peripheral units, wherein a request signal is transferred from each of said plurality of peripheral units to said central processing unit, and an acknowledge signal in response to said request signal is successively propagated from said central processing unit to each of said plurality of peripheral units by a daisy chain connection, wherein each of said plurality of peripheral units comprises a request signal output means and input-output terminals, characterised in that at least one peripheral unit of said plurality of peripheral units comprises an end indicative information storing means storing end indicative information indicative of the end of the daisy chain, and a chain end state notification means, and said central processing unit comprises means for returning from a response waiting state; said chain end state notification means being operatively connected to said central processing unit and arranged to notify said central processing unit of a chain end state, when said peripheral unit receives said acknowledge signal and does not output said request signal and when said end indicative information is set in the end indicative information storing means thereof. According to a third aspect of the present invention, there is provided an interrupt controller comprising: an interrupt request signal output means, operatively connected to a central processing unit, for outputting an interrupt request signal to said central processing unit; and input-output terminals, operatively connected to said central processing unit or a neighbour interrupt controller, for constructing a daisy chain connection; characterised by: an end indicative information storing means for storing end indicative information of said daisy chain; and a chain end state notification means, operatively connected to said central processing unit and said end indicative information storing means, for notifying a chain end state to said central processing unit, when an interrupt acknowledge signal output from said central processing unit is propagated to said interrupt controller, said end indicative information being set in said end indicative information means thereof and said interrupt request signal being not output, so that said central processing unit is returned from a response waiting state by receiving a chain end state notification from said chain end state notification means. The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: Fig.1 is a block diagram illustrating an example of a prior-proposed interrupt processing apparatus; Fig.2 is a block diagram illustrating an embodiment of an interrupt processing apparatus according to the present invention; Fig.3 is a circuit diagram of an example of a control portion shown in Fig.2; Fig.4 is a timing chart of a register shown in Fig.2 when not set; Fig.5 is a timing chart of a register shown in Fig.2 when set; Fig.6 is a block diagram illustrating another embodiment of an interrupt processing apparatus according to the present invention; Fig.7 is a block diagram of an interrupt processing apparatus using interrupt controllers; Fig.8 is a block diagram illustrating an example of an interrupt controller applied to the interrupt processing apparatus shown in Fig. 2; and, Fig. 9 is a block diagram illustrating an example of an interrupt controller applied to the interrupt processing apparatus shown in Fig. 3. For a better understanding of the preferred embodiments, the problems of a prior proposal will be first explained. Figure 1 is a block diagram illustrating an example of a proposed interrupt processing apparatus. In this drawing, reference CPU denotes a central processing unit, U₁ - U n denote peripheral units, DB denotes a data bus, IRR denotes a interrupt request signal, D in denotes an interrupt acknowledge signal from the central processing unit or an immediately prior step, D out denotes an interrupt acknowledge signal to be output to a next step, and C₁′ - C n ′ denote control portions. In Fig. 1, an interrupt request signal IRR of each peripheral unit U₁ - U n is output to a central processing unit CPU through a common signal conductor. For example, when the peripheral unit U n outputs an interrupt request signal IRR, the central processing unit CPU receives the interrupt request signal IRR and an interrupt processing is enabled, and the central processing unit CPU outputs an interrupt acknowledge signal D in . A control portion C₁′ of the peripheral unit U₁ receives the interrupt acknowledge signal D in and outputs an interrupt acknowledge signal D out to the next peripheral unit U₂ as an interrupt acknowledge signal D in thereof, since the peripheral unit U₁ has not output an interrupt request signal. Thus, as described above, the interrupt acknowledge signal is successively propagated to each peripheral unit. When the interrupt acknowledge signal D in is propagated to the peripheral unit U n which has output an interrupt request signal IRR, a control portion C n ′ of the peripheral unit U n outputs a vector address to the central processing unit CPU through a data bus DB, and thus an interrupt processing routine for the peripheral unit U n is started. In Fig. 1, when noise exists in a signal conductor in which the interrupt request signal IRR is propagated, the noise may be taken as the interrupt request signal IRR in the central processing unit CPU. In this case, the central processing unit CPU outputs an interrupt acknowledge signal D in , but none of the peripheral units U₁ - U n outputs a response signal to the central processing unit CPU. Therefore, an interrupt acknowledge signal D in is propagated to the final step peripheral unit U n but the central processing unit CPU does not receive a vector address of an interrupt processing routine, and therefore, the central processing unit CPU is held in a response waiting state and a long and unnecessary delay occurs. To solve the above described problem, a timer is provided, and when the response waiting state of the central processing unit CPU continues for longer than a specific time, the central processing unit CPU is returned to the normal state from the response waiting state. In this case, however, if the time elapsed is not sufficient, an obstacle is formed by a normal operating state; and therefore, the time elapsed is made long, and thus an unnecessary delay occurs. In consideration of the above, the present invention may reduce a time elapsed before a return from a response waiting state of a central processing unit without a long and unnecessary delay, when an error interrupt request signal is to be propagated to the central processing unit. Below, an interrupt processing method and an interrupt processing apparatus of the present invention will be explained in detail with reference to the drawings. Figure 2 is a block diagram illustrating an embodiment of an interrupt processing apparatus according to the present invention. In Fig. 2, reference R₁ - R n denote registers, C₁ - C n denote control portions, SET denotes an end indicative information, IRR₁ - IRR n denote an interrupt request signal generated from each peripheral unit U₁ - U n , and D end denotes an end notice signal. Note, the peripheral units U₁ - U n are input-output devices or auxiliary storages, i.e., each peripheral unit U₁ - U n is, for example, a cathode ray tube display, an optical mark reader, and a hard disk drive device, etc. Note, the same portions of Figs. 1 and 2 are indicated by the same references. An interrupt processing using a daisy chain connection in a normal state, is the same as that of the apparatus of Fig. 1, and thus only the case where an error interrupt request signal is generated by noise, etc., will be explained below. Each register R₁ - R n is a one-bit register and stores an end indicative information corresponding to one kind of flag. The end indicative information is output from a central processing unit CPU to an optional one of the peripheral units through a data bus DB and is set to a register of the one of the peripheral units. For example, assuming that an end indicative information is set to a register R n of a peripheral unit U n , and none of the peripheral units U₁ - U n generates an interrupt request signal IRR₁ - IRR n , in this state, when the central processing unit takes a noise signal as an interrupt request signal and starts an interrupt acceptance processing, i.e., the central processing unit CPU outputs an interrupt acknowledge signal D in to a control portion C₁ of a first step peripheral unit U₁ , an interrupt request signal IRR is not output from the peripheral unit U₁ and an end indicative information is not set to a register R₁ of the control portion C₁ , so that an interrupt acknowledge signal D out is transferred to a control portion C₂ of a second step peripheral unit U₂ as an interrupt acknowledge signal D in thereof. Similarly, in the second step peripheral unit U₂ , an interrupt request signal IRR is not output from the peripheral unit U₂ and an end indicative information is not set to a register R₂ of the control portion C₂ , so that an interrupt acknowledge signal D out is transferred to the next control portion of the next step peripheral unit through the control portion C₂. As described above, an interrupt acknowledge signal D out is successively transferred to a control portion C n of the peripheral unit U n as an interrupt acknowledge signal D in thereof, in the same manner. In the peripheral unit U n , an end indicative information is set in the register R n of the peripheral unit U n but an interrupt request IRR n is not received, i.e., an end indicative information SET is output from the register R n to the control portion C n ; an interrupt request IRR is not output to the central processing unit CPU; a one-bit end notice signal D end is instead output from the control portion C n to the central processing unit CPU through a signal conductor. The central processing unit CPU receives the end notice signal D end and confirms a chain end state, and then the central processing unit CPU is returned from a response waiting state and carries out a predetermined error processing, etc. In the above example , the end indicative information is set to the final step of the daisy chain connection . If the end indicative information is set to an optional step peripheral unit within the daisy chain connection, an end portion of the daisy chain connection can be determined by the optional step peripheral unit. This is preferable since the interrupt requests output from low priority peripheral units connected to the daisy chain connection are disregarded, and a specific processing is carried out on a temporary basis. In the above embodiment, registers R₁ - R n are provided for all peripheral units U₁ - U n , but a register can be provided at only one of the peripheral units U₁ - U n ; for example, only the register R n and the control portion C n as described above can be provided at the final peripheral unit. Figure 3 is a circuit diagram of an example of a control portion shown in Fig. 2. As shown in Fig. 3, the control portion C₁ comprises two inverter circuits I₁ , I₂ and two three-input AND gate circuits G₁ , G₂. An input terminal of the inverter circuit I₁ is connected to an interrupt request output unit (not shown) included in each peripheral unit and receives an interrupt request signal IRR₁. Note, the interrupt request output unit is a signal output means or a signal output function in the peripheral unit, and a reference IRR substantially denotes the same signal as the interrupt request signal IRR₁. An input terminal of the inverter circuit I₂ is connected to the register R₁ and receives an end indicative signal SET from the register R₁. A first input of the AND gate circuits G₁ is connected to the central processing unit CPU and receives an interrupt acknowledge signal D in . When the AND gate circuit G₁ is provided for a post control portion of the first step peripheral unit U₁ , the first input of the AND gate circuit G₁ is connected to a control portion of an immediately prior peripheral unit, for example, the AND gate circuit G₁ is provided for the control portion C₂ of the second step peripheral unit U₂ and the first input of the AND gate circuits G₁ is connected to an immediately prior control portion C₁. A second input of the AND gate circuits G₁ is connected to the first inverter circuit I₁ and receives an inverted signal of the interrupt request signal IRR, a third input thereof is connected to the second inverter circuit I₂ and receives an inverted signal of the end indicative signal SET, and an output thereof is connected to an immediately adjacent equipment, i.e., a second peripheral unit U₂ , and outputs an interrupt acknowledge signal D out to the second peripheral unit U₂. When the AND gate circuits G₁ is provided for a control portion C n of the final step peripheral unit U n , the output of the AND gate circuit G₁ is not connected. A first input of the AND gate circuit G₂ is connected to the first input of the AND gate circuit G₁ and receives the interrupt acknowledge signal D in . When the AND gate circuits G₂ is provided for a post control portion of the first step peripheral unit U₁ , the first input of the AND gate circuit G₂ is connected to a control portion of an immediately prior peripheral unit, as for the AND gate circuit G₁. A second input of the AND gate circuit G₂ is connected to the second input of the AND gate circuit G₁ and receives the inverted signal of the interrupt request signal IRR, a third input thereof is connected to the register R₁ and receives the end indicative signal SET, and an output thereof is connected to the central processing unit CPU and transfers an end notice signal D end to the central processing unit CPU through a signal conductor. The operation of this circuit will be explained with reference to the timing charts of Figs. 4, 5 and the following truth table. TRUTH TABLE D in IRR SET D out D end 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 ○ 1 0 0 1 0 2 ○ 1 0 1 0 1 3 ○ 1 1 0 0 0 4 ○ 1 1 1 0 0 Note, in Figs. 4 and 5, reference H corresponds to "1", and reference L corresponds to "0". In the above table, a line of 1 ○ corresponds to a state of Fig. 4 (a timing chart when not setting a register), a line of 2 ○ corresponds to a state of Fig. 5 (a timing chart when setting a register). First, when the interrupt acknowledge signal D in is at "0", both an interrupt acknowledge signal D out which is an output of an AND-gate G₁ and an end notice signal D end which is an output of an AND-gate G₂ are "0", regardless of the state of an interrupt request signal IRR and an end indicative signal SET. The line 1 of the truth table indicates that the interrupt acknowledge signal D in is at "1" when the end indicative information signal SET is "0" and the interrupt request signal IRR is also "0". As shown in Fig. 4, the interrupt acknowledge signal D in is transferred to the next step as the interrupt acknowledge signal D out , and the end notice signal D end , which is an output signal of the AND-gate G₂ , is maintained at "0". Therefore, the central processing unit CPU is held in a response waiting state. The line 2 ○ of the truth table indicates that the interrupt acknowledge signal D in is "1" when the end indicative signal SET is "0", i.e., an end of the daisy chain is indicated, and the interrupt request signal IRR is also "0". As shown in Fig. 5, the interrupt acknowledge signal D out is brought to "0", and the interrupt acknowledge signal D in is not transferred to the next step, but the end notice signal D end is brought to "1" and the central processing unit CPU is notified of a chain end state. As the result, the central processing unit CPU rapidly returns from the response waiting state, and carries out a specific error processing, etc. As shown in the lines 3 ○ and 4 ○ of the truth table, the interrupt request signal IRR is "1", i.e., the interrupt request is output from the peripheral unit by itself, the interrupt acknowledge signal D in is not transferred to the next step, and the end notice signal D end is maintained at "0". Therefore, a vector address is output from the peripheral unit to the central processing unit CPU, so that an interrupt processing routine is carried out. Next, another embodiment of an interrupt processing apparatus according to the present invention will be explained. Figure 6 is a block diagram illustrating another embodiment of an interrupt processing apparatus according to the present invention. This embodiment corresponds to the embodiment of Fig. 2, and the same portions and same signals shown in Figs. 2 and 6 are indicated by the same references. The difference between these two embodiments is a propagation of the end notice signal D end . In the first embodiment of Fig. 2, the end notice signal D end from each peripheral unit is transferred to the central processing unit CPU through an exclusive signal conductor, and the central processing unit is returned from the response waiting state to a normal state. In the second embodiment of Fig. 6, however, an end notice signal D end is transferred through a data bus DB, for example, which end notice signal D end is a signal indicating a vector address of an error processing subroutine. When the central processing unit CPU receives the vector address signal D end , the central processing unit CPU is returned from the response waiting state and the error processing subroutine corresponding to the vector address signal D end is carried out. In this embodiment, the exclusive signal conductor for transferring the end notice signal D end from each peripheral unit to the central processing unit CPU can be omitted. Figure 7 is a block diagram of an interrupt processing apparatus using interrupt controllers. In the above described embodiments, each peripheral unit U₁ - U n comprises an input-output device or an auxiliary storage, for example, a cathode ray tube display, an optical mark reader, and a hard disk drive device, etc., but in the interrupt processing apparatus of Fig. 7, each peripheral unit U₁ - U n comprises an interrupt controller. Note, in Fig. 7, only three peripheral units U₁ - U₃ are indicated. The interrupt controller, which is used as an interrupt handler or an interrupt generator, controls a plurality of, for example, seven, input-output devices or auxiliary storages. As shown in Fig. 7, the peripheral unit U₁ is used as an interrupt handler by applying a power supply potential to a function select terminal FSEL of an interrupt controller, and each peripheral unit U₂ and U₃ is used as an interrupt generator by applying an earth potential to a function select terminal FSEL of an interrupt controller. For example, seven input-output devices (or auxiliary storages) IOD₀ - IOD₆ are connected to each interrupt handler or interrupt generator U₁ - U₃ through I/O ports respectively. The seven input-output devices IOD₀ - IOD₆ output a local interrupt request signal LIR0# - LIR6# to each peripheral unit U₁ - U₃ of an interrupt handler or an interrupt generator, respectively. Each peripheral unit U₁ - U₃ outputs local interrupt acknowledge signals LIK0 - LIK2 and local interrupt acknowledge strobe signal LIKSTB# to each decoder DE₁ - DE₃ , and each decoder DE₁ - DE₃ outputs an interrupt acknowledge signal to each input-output device IOD₀ - IOD₆ , respectively. The peripheral unit of the interrupt handler U₁ is controlled by the central processing unit CPU through an address bus (A1 - 5), a data bus (D24 - 31), and a control bus. The peripheral unit U₁ is connected to the central processing unit CPU by interrupt request signal conductors IRL0 - IRL2, and an interrupt request signal from the peripheral unit U₁ is transferred to the central processing unit CPU and an interrupt acknowledge signal ACKIN# from the central processing unit is transferred to the peripheral unit U₁ , through the system bus. Similarly, the peripheral units of the interrupt generators U₂ , U₃ are controlled by the central processing unit CPU by an address bus (A1 - 5), a data bus (D24 - 31), and a control bus, through a system bus. The peripheral units U₂ , U₃ output bus interrupt signals BIR0# - BIR6# to the peripheral unit U₁ through the system bus, and an interrupt acknowledge signal ACKOUT# of the peripheral unit U₁ is transferred to the peripheral unit U₂ as an interrupt acknowledge signal ACKIN# and an interrupt acknowledge signal ACKOUT# of the peripheral unit U₂ is transferred to the peripheral unit U₃ , respectively. In the above description, reference # indicates an inverted signal. Figure 8 is a block diagram illustrating an example of an interrupt controller applied to the interrupt processing apparatus shown in Fig. 2. In Fig. 8, reference IR denotes an interrupt control portion and reference ir denotes an interrupt request from a plurality of peripheral units. Note the same portions as shown in Figs. 2 and 8 are indicated by same reference. An interrupt controller, which is used as an interrupt handler or an interrupt generator of the peripheral units U₁ - U n in Fig. 2, comprises an interrupt control portion IR which groups the interrupt requests output from a plurality of, for example, seven input-output devices or auxiliary storages, on a priority basis, and controls a ranking of the interrupt requests. The interrupt control portion IR is connected to the central processing unit CPU through a data bus DB, and outputs a vector address corresponding to the peripheral unit outputting the interrupt request, when the interrupt control portion IR receives the interrupt acknowledge signal D in . A setting processing for setting the end indicative information to the register R₁ is also carried out through the data bus DB and the interrupt control portion IR. A daisy chain connection is constructed by using interrupt controllers IRC as described in Fig. 7, and thus an optional portion of the daisy chain connection by software can be omitted. Figure 9 is block diagram illustrating an example of an interrupt controller applied to the interrupt processing apparatus shown in Fig. 3. In Fig. 9, reference IR denotes an interrupt control portion and reference ir denotes an interrupt request from a plurality of input-output devices or auxiliary storages. Note, the same portions as shown in Figs. 3 and 9 are indicated by same references. As described above, in Fig. 8, the end notice signal D end is transferred to the central processing unit by a one-bit signal conductor, but as shown in Fig. 9, a vector address for starting an error processing subroutine can be transferred, instead of the end notice signal D end , to the central processing unit CPU through the data bus DB. The difference of the configurations of the interrupt controllers of Figs. 8 and 9 is that a register RV which sets a vector address for error processing and a three state buffer BF are provided, and the three states buffer is controlled by the end notice signal D end . An operation of a control portion C₁ is same as that of Figs. 2 and 8. The vector address for error processing is previously set through the data bus DB by the central processing unit CPU. When the end notice signal D end is "0", the three states buffer BF is disabled and an output of the three states buffer BF is brought to a high impedance state. When the end notice signal D end is "1", the three states buffer BF is enabled and the vector address stored in the register RV is output to the central processing unit CPU through the data bus DB. As described above, in embodiments of the present invention, when an error interrupt request is generated by noise, etc., a delay for the central processing unit CPU is reduced. Further, a daisy chain connection may be cut at an optional portion and an interrupt request from an irrelevant peripheral unit can be ignored so that the efficiency of the processing is improved.

Claims: A processing method for a computer system having a central processing unit (CPU) and a plurality of peripheral units (U₁- U n ), wherein a request signal (IRR) is transferred from each of said plurality of peripheral units (U₁ - U n ) to said central processing unit (CPU), and an acknowledge signal (D in , D out ) in response to said request signal (IRR) is successively propagated from said central processing unit (CPU) to each of said plurality of peripheral units (U₁ - U n ) by a daisy chain connection, characterised in that said processing method comprises: a step of setting indicative information in an end indicative information storing means (R₁ - R n ) of at least one of said plurality of peripheral units (U₁ - U n ); a step for outputting a specific signal (D end ) notifying said central processing unit (CPU) of a chain end state from said peripheral unit (U₁ - U n ) at which said indicative information is set in said end indicative information storing means (R₁ - R n ) thereof, when said peripheral unit (U₁ - U n ) receives said acknowledge signal (D in ) and does not output said request signal (IRR); and a step for returning said central processing unit (CPU) from a response waiting state on receipt of said specific signal (D end ). A processing method according to claim 1, wherein said request signal (IRR) is an interrupt request signal, and said acknowledge signal (D in , D out ) is an interrupt acknowledge signal. A processing method according to claim 1 or 2, wherein said indicative information is set in end indicative information storing means (R n ) of a final step peripheral unit (U n ) of said daisy chain connection, so that when said acknowledge signal (D in ) is propagated to said final step peripheral unit (U n ) and said request signal (IRR) is not output from said final step peripheral unit (U n ), said central processing unit (CPU) is notified of a chain end state. A processing method according to claim 1 or 2, wherein each of said plurality of peripheral units (U₁ - U n ) includes said end indicative information storing means (R₁ - R n ), said end indicative information being set to an optional one of said plurality of peripheral units (U₁ - U n ) by said central processing unit (CPU), so that a propagation of said acknowledge signal (D out ) is stopped and said specific signal (D end ) is output from said optional one of said plurality of peripheral units (U₁ - U n ). A processing method according to claim 1,2,3,or 4, wherein said specific signal (D end ) is an end notice signal, said end notice signal (D end ) being transferred to said central processing unit (CPU) by a one-bit signal conductor, so that said central processing unit (CPU) is returned from said response waiting state to a normal state. A processing method according to claim 1,2,3,or 4, wherein said specific signal (D end ) is a vector address which indicates a start address of an error processing subroutine, said vector address (D end ) being transferred to said central processing unit (CPU) by a data bus, so that said central processing unit (CPU) is returned from a response waiting state and carries out said error processing subroutine. A processing method according to any preceding claim, wherein said plurality of peripheral units (U₁ - U n ) include an input-output device or an auxiliary storage. A processing method according to any preceding claim, wherein said plurality of peripheral units (U₁ - U n ) include an interrupt controller which controls a plurality of input-output devices or auxiliary storages. A processing method according to any preceding claim, wherein said end indicative information storing means (R₁ - R n ) comprises a one-bit register. A processing apparatus having a central processing unit (CPU) and a plurality of peripheral units (U₁ - U n ), wherein a request signal (IRR) is transferred from each of said plurality of peripheral units (U₁ - U n ) to said central processing unit (CPU), and an acknowledge signal (D in ,D out ) in response to said request signal (IRR) is successively propagated from said central processing unit (CPU) to each of said plurality of peripheral units (U₁-U n ) by a daisy chain connection, wherein each of said plurality of peripheral units (U₁-U n ) comprises a request signal output means (IRR₁-IRR n )and input-output terminals (D in ,D out ), characterised in that at least one peripheral unit (e.g. U n ) of said plurality of peripheral units (U₁-U n ) comprises an end indicative information storing means (R₁-R n ) storing end indicative information indicative of the end of the daisy chain, and a chain end state notification means (C₁-C n ), and said central processing unit (CPU) comprises means for returning from a response waiting state; said chain end state notification means (C₁-C n ) being operatively connected to said central processing unit (CPU) and arranged to notify said central processing unit (CPU) of a chain end state, when said peripheral unit (e.g. U n ) receives said acknowledge signal (D in ) and does not output said request signal (IRR) and when said end indicative information is set in the end indicative information storing means (R₁-R n ) thereof. A processing apparatus according to claim 10, wherein: said request signal output means (IRR₁-IRR n ) is operatively connected to said central processing unit (CPU) and outputs a request signal (IRR) from each of said plurality of peripheral units (U₁-U n ) to said central processing unit (CPU); said input-output terminals (D in -D out ) are operatively connected to said central processing unit (CPU) or an adjacent peripheral unit (U₁-U n ) to construct said daisy chain connection among said central processing unit (CPU) and said plurality of peripheral units (U₁-U n ); said end indicative information storing means (R₁-R n ) are operatively connected to said chain end state notification means (C₁-C n ); and said returning means is operatively connected to said chain end state notification means (C₁-C n ), and is operable to return said central processing unit (CPU) from said response waiting state on receipt of a specific signal (D end ) from said chain end state notification means (C₁-C n ). A processing apparatus according to claim 10 or 11, wherein said request signal (IRR) is an interrupt request signal, and said acknowledge signal (D in ,D out ) is an interrupt acknowledge signal. A processing apparatus according to claim 10, 11 or 12, wherein said end indicative information storing means (R n ) is included in a final step peripheral unit (U n ) of said daisy chain connection, so that when said acknowledge signal (D in ) is propagated to said final step peripheral unit (U n ) and said request signal (IRR) is not output from said final step peripheral unit (U n ), said central processing unit (CPU) is notified of a chain end state. A processing apparatus according to claim 10, 11, 12 or 13, wherein each of said plurality of peripheral units (U₁-U n ) includes said end indicative information storing means (R₁-R n ), said end indicative information being set to an optional one of said plurality of peripheral units (U₁-U n ) by said central processing unit (CPU), so that a propagation of said acknowledge signal (D in ) is stopped and said specific signal (D end ) is output from said optional one of said plurality of peripheral units (U₁-U n ). A processing apparatus according to any one of claims 10 to 14, wherein said chain end state notification means (C₁-C n ) outputs an end notice signal (D end ), said end notice signal (D end ) being transferred to said central processing unit (CPU) by a one-bit signal conductor, so that said central processing unit (CPU) is returned from said response waiting state to a normal state. A processing apparatus according to any one of claims 10 to 14, wherein said chain end state notification means (C₁-C n ) outputs a vector address (D end ) indicating a start address of an error processing subroutine, said vector address (D end ) being transferred to said central processing unit (CPU) by a data bus, so that said central processing unit (CPU) is returned from a response waiting state and carries out said error processing subroutine. A processing apparatus according to any one of claims 10 to 16, wherein said plurality of peripheral units (U₁-U n ) includes an input-output device or an auxiliary storage. A processing apparatus according to any one of claims 10 to 17, wherein said plurality of peripheral units (U₁-U n ) includes an interrupt controller which controls a plurality of input-output devices or auxiliary storages. A processing apparatus according to any one of claims 10 to 18, wherein said end indicative information storing means (R₁-R n ) comprises a one-bit register. A processing apparatus according to any one of claims 10 to 19, wherein said chain end state notification means (C₁-C n ) comprises first and second inverter circuits (I₁,I₂) and first and second three-input AND gate circuits (G₁,G₂); an input terminal of said first inverter circuit (I₁) being operatively connected to said request signal output means (IRR₁-IRR n ) for receiving said request signal (IRR); an input terminal of said second inverter (I₂) circuit being operatively connected to said end indicative information storing means (R₁ - R n ) for receiving an end indicative signal (SET) from said end indicative information storing means (R₁ - R n ); a first input of said first AND gate circuit (G₁) being operatively connected to an immediately prior peripheral unit (U₁ - U n ) or said central processing unit (CPU) for receiving said acknowledge signal (D in ), a second input thereof being operatively connected to said first inverter circuit (I₁) for receiving an inverted signal of said request signal (IRR), a third input thereof being operatively connected to said second inverter circuit (I₂) for receiving an inverted signal of said end indicative signal (SET), and an output thereof being operatively connected to an immediately peripheral unit (U₂ - U n ) for transferring said acknowledge signal (D out ); a first input of said second AND gate circuit (G₂) being operatively connected to said first input of said first AND gate circuit (G₁) for receiving said acknowledge signal (D in ), a second input thereof being operatively connected to said second input of said first AND gate circuit (G₁) for receiving an inverted signal of said request signal (IRR), a third input thereof being operatively connected to said end indicative information storing means (R₁ - R n ) for receiving said end indicative signal (SET), and an output thereof being operatively connected to said central processing unit (CPU) for transferring said specific signal (D end ) in order to notify said central processing unit (CPU) of a chain end state. An interrupt controller comprising: an interrupt request signal output means, (IRR₁-IRR n ), operatively connected to a central processing unit (CPU), for outputting an interrupt request signal (IRR) to said central processing unit (CPU); input-output terminals (Din, Dout), operatively connected to said central processing unit (CPU) or a neighbor interrupt controller (U₁ - U n ), for constructing a daisy chain connection; characterised by: an end indicative information storing means (R₁ - R n ) for storing end indicative information of said daisy chain; and a chain end state notification means (C₁ - C n ), operatively connected to said central processing unit (CPU) and said end indicative information storing means (R₁ - R n ), for notifying a chain end state to said central processing unit (CPU), when an interrupt acknowledge signal (Din) output from said central processing unit (CPU) is propagated to said interrupt controller, said end indicative information being set in said end indicative information means (R₁ - R n ) thereof and said interrupt request signal (IRR) being not output, so that said central processing unit (CPU) is returned from a response waiting state by receiving a chain end state notification from said chain end state notification means (C₁ - C n ). An interrupt controller according to claim 21, wherein said chain end state notification means (C₁ - C n ) outputs an end notice signal (Dend), said end notice signal (Dend) being transferred to said central processing unit (CPU) by a one-bit signal conductor, so that said central processing unit (CPU) is returned from said response waiting state to a normal state. An interrupt controller according to claim 21, wherein said chain end state notification means (C₁ - C n ) outputs a vector address (Dend) indicating a start address of an error processing subroutine, said vector address (Dend) being transferred to said central processing unit (CPU) by a data bus, so that said central processing unit (CPU) returns from a response waiting state and carries out said error processing subroutine. An interrupt controller according to claim 21,22 or 23, wherein said end indicative information storing means (R₁ - R n ) comprises a one-bit register. An interrupt controller according to claim 21,22,23 or 24, wherein said chain end state notification means (C₁ - C n ) comprises first and second inverter circuits (I₁ - I₂) and first and second three-input AND gate circuits (G₁ , G₂): an input terminal of said first inverter circuit (I₁) being operatively connected to said interrupt request signal output means (IRR₁ - IRR n ) for receiving said interrupt request signal (IRR); an input terminal of said second inverter (I₂) circuit being operatively connected to said end indicative information storing means (R₁ - R n ) for receiving an end indicative signal (SET) from said end indicative information storing means (R₁ - R n ); a first input of said first AND gate circuit (G₁) being operatively connected to an immediately prior interrupt controller (U₁ - U n ) or said central processing unit (CPU) for receiving said interrupt acknowledge signal (Din), a second input thereof being operatively connected to said first inverter circuit (I₁) for receiving an inverted signal of said interrupt request signal (IRR), a third input thereof being operatively connected to said second inverter circuit (I₂) for receiving an inverted signal of said end indicative signal (SET), and an output thereof being operatively connected to an immediately interrupt controller (U₂ - U n ) for transferring said interrupt acknowledge signal (Dout); a first input of said second AND gate circuit (G₂) being operatively connected to said first input of said first AND gate circuit (G₁) for receiving said interrupt acknowledge signal (Din), a second input thereof being operatively connected to said second input of said first AND gate circuit (G₁) for receiving an inverted signal of said interrupt request signal (IRR), a third input thereof being operatively connected to said end indicative information storing means (R₁ - R n ) for receiving said end indicative signal (SET), and an output thereof being operatively connected to said central processing unit (CPU) for transferring said specific signal (Dend) in order to notify said central processing unit (CPU) of a chain end state.

Inventors: FUJIYAMA HIROYUKI, KUROIWA KOUICHI FUJITSU DAIICH, NISHIKAWA SINJI LIONS MANSION, OYAMADA SHINJI FUJITSU DAIICHI, SHIMURA HIDETOSHI YURI HAITSU, FUJIYAMA, HIROYUKI, KUROIWA, KOUICHI FUJITSU DAIICHI EDA RYO, NISHIKAWA, SINJI LIONS MANSION HISASUE 206, OYAMADA, SHINJI FUJITSU DAIICHI FUJIGAOKA RYO, SHIMURA, HIDETOSHI YURI HAITSU A-103
Applicants: FUJITSU DEVICES INC, FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G06F13
IPC codes: G06F13