Semiconductor device having a side wall film and method of producing the same

Abstract: A semiconductor device includes a semiconductor substrate (21), an insulation film (22, 23) formed on the semiconductor substrate, a film (24₁ - 24₃) formed on the insulation film having a side wall, and a side wall film (22A) formed on the insulation film so as to surround the side wall of the film (24₁ - 24₃). The side wall film (22A) has a slope and satisfies a condition a > d where a is a width of a bottom surface of the side wall film which is in contact with the insulation film and d is a thickness of the film.

Description: The present invention generally relates to a semiconductor device having a smoothed edge of a layer and a method of producing the same. Currently, a need exists for finer patterns for fabricating a semiconductor device. Anisotropic etching is suitable for forming finer patterns. For example, a polysilicon film is patterned by anisotropic etching in which an etching gas containing CCl₄/O₂ is used. An edge a side wall of the pattern thus formed is like a sheer cliff. In other words, an edge of the pattern rises sheer from an underlying layer. It is known that overhang portions are sometimes formed at side walls of patterns. As the height of the side wall of a lower layer increases, it becomes difficult to pattern an upper layer which covers the lower layer. It is known that almost vertical side walls of layers can be coated with spin on glass, or an etch-back process can be employed, in order to eliminate the above-mentioned problem. However, such methods lead to an increased number of manufacturing steps. Particularly, it is very difficult to control the etch-back process. In a dynamic random access memory device (hereinafter simply referred to as a DRAM), reduction in size of a projected area of a memory cell projected on a flat surface is desired. It is known that with a conventional stacked capacitor structure formed in a memory cell area equal to or less than 10 µm² , it is very difficult to obtain a sufficient value of capacitance of a memory cell capacitor. In order to increase capacitance of the memory cell capacitor, it is conceivable to form a thicker storage electrode of polysilicon to thereby increase an area of a side surface of the storage electrode. With this structure, the total surface area of the memory cell capacitor can be maintained. However, patterning of a polysilicon film to obtain the storage electrode is greatly affected by the surface roughness of an underlying film on which the above polysilicon film is formed. The polysilicon film used for forming the storage electrode is deposited on an interlayer insulation film which covers gate electrodes. Generally, the surface of the interlayer insulation film has step portions, or convex and recess portions due to the presence of the gate electrodes. The presence of large convex and recess portions makes it difficult to pattern the polysilicon film deposited on the interlayer insulation film. As a result, a fine patterning of the storage capacitors cannot be obtained. EP-A-0 164 186 by Monolithic Memories Inc. discloses a semiconductor device, and a process of producing a semiconductor device, according to the preambles of accompanying claims 1 and 7 respectively. EP-A-0 191 612 by the present applicant discloses a stacked-capacitor DRAM in which gate electrodes of the memory cell transistors have their sides covered by insulating layers. These insulation layers contribute to the capacitance of the stacked capacitor. According to a first aspect of the invention, there is provided a semiconductor device comprising:- a semiconductor substrate; an insulation film formed on the semiconductor substrate; a film formed on the insulation film having a side wall; and a side wall film formed on the insulation film so as to surround the side wall of the film; characterised in that:- the device further comprises a patterned film formed over the insulation film and side wall film; and in that the side wall film satisfies the condition a > d where a is the width of a bottom surface of the side wall film which is in contact with the insulation film and d is the thickness of the film. According to a second aspect of the invention, there is provided a process of producing a semiconductor device comprising the steps of:- forming a first insulation film on the semiconductor substrate; forming a film on the first insulation film; patterning the film; depositing a second insulation film of silicon dioxide on the entire surface of the substrate; and etching the second insulation film by anisotropic etching until a portion of the second insulation film on a flat surface of the first insulation film is completely removed; so that a side wall film of a remaining portion of the second insulation film is formed on the insulation film surrounding the side wall of said patterned film; characterised in that:- the side wall film is formed so as to satisfy the condition a > d where a is the width of a bottom surface of the side wall film which is in contact with the insulation film and d is the thickness of the film; and in that the method comprises the further step of forming and patterning a further film over the insulation film and the side wall film. The present invention provides a semiconductor device in which a side wall film is formed around an edge or side wall of a lower film on which an upper film to be patterned is formed. The presence of the side wall film enables formation of a smoothed edge of the film or a smooth surface of the lower film. Reference is made, by way of example, to the accompanying drawings in which: Figs. 1 and 2 illustrate problems in conventional semiconductor devices; Fig. 3 illustrates the principle of the present invention; FIGS.4 through 10 are cross sectional views of a DRAM device embodying the present invention at essential manufacturing steps; and FIG.11 is a cross sectional view of the finished device. To facilitate the understanding of the present invention, a description is first given of problems caused by the presence of step portions of an underlying layer on which a storage capacitor electrode of a DRAM device is formed, with reference to FIGS.1 and 2. FIG.1 shows a cross section of an essential part of a conventional DRAM device. As shown, the DRAM device has a silicon semiconductor substrate 11, a field insulation film 12 formed on top of the substrate 11, gate electrodes 14₁, 14₂ and 14₃, and an interlayer insulation film 17 formed so as to cover the gate electrodes 14₁, 14₂ and 14₃. An n⁺-type diffusion region 16₁, which is a storage capacitor contact region, is formed in the substrate 11. A storage electrode 18 1A is formed on the interlayer insulation film 17 having a contact hole through which the storage electrode 18 1A is in contact with the n⁺-type diffusion region 16₁. The storage electrode 18 1A is one electrode out of paired electrodes of a memory cell capacitor. A dielectric film 19 1A such as a silicon dioxide film is formed so as to surround an exposed surface of the storage electrode 18 1A . The other electrode (not shown) out of the paired electrodes (called an opposed electrode or cell plate) is formed on the dielectric film 19 1A . As described hereinbefore, as the projected area of the surface of the memory cell projected onto a flat surface decreases, the projected area of the surface of the memory cell capacitor decreases. Thereby capacitance of the memory cell capacitor also decreases. In order to compensate the decrease of capacitance, it is conceivable to approximately double the thickness S of the storage electrode 18 1A (about 0.5 µm ). Thereby the area of a side wall of the storage electrode 18 1A increases, and a decrease of the entire surface of the storage electrode 18 1A can be prevented. However, the thick storage electrode 18 1A produces a great step portion as indicated by an arrow A. As shown, between the gate electrodes 18 1A and 18 1B , there is formed a deep recess due to the presence of the gate electrodes 14₂ and 14₃ which have side walls rising sheer. Therefore, it is difficult to pattern the polysilicon film by photolithography technology to form the storage electrodes 18 1A and 18 1B . In addition, as shown in FIG.2, an overhang portion 14p is often formed at the edge of the gate electrode 14₂. In this case, the interlayer insulation film 17 deposited on the gate electrode 14₂ has a shape shown in FIG.2. It is noted that a concave portion 17a is formed on the side surface of the interlayer insulation film 17. The presence of overhang portion at the edge of the gate electrode 14₂ also prevents fine patterning of the polysilicon film for the storage electrode 18 1A . The present invention intends to form a side wall film so as to surround an edge or a side wall of a film such as a gate electrode film and provide a smoothed edge or side wall of the film. With the side wall film, it becomes possible to pattern a thick film by the conventional photolithography technology. A description is given of an essential feature of the present invention with reference to FIG.3. A field insulation film 22 is formed on a silicon semiconductor substrate 21. Gate electrodes 24₂ and 24₃ which function as word lines are formed on the field insulation film 22. Side walls of the gate electrodes 24₂ and 24₃ rise sheer from the field insulation film 22. Side wall films 22A are formed so as to surround the edges of the gate electrodes 24₂ and 24₃. The side wall films 22A provide slopes between top surfaces of the gate electrodes 24₂ and 24₃ and the field insulation film 22. An interlayer insulation film 27 is formed so as to cover the gate electrodes 24₂ and 24₃, the side wall films 22A, and an exposed surface on the field insulation film 22. A storage electrode 28 of a polysilicon film is formed on the interlayer insulation film 27. The present inventor found from many experiments that a particular condition on size of the side wall film 22A providing a slope is required to pattern the polysilicon film 28 by the conventional photolithography technology even if it is thick (0.5 µm for example). The particular condition found by the experiments is that the width a of a bottom surface of the side wall film 22A which is in contact with the surface of the field insulation film 22, must be greater than the thickness d of the gate electrode 24₂. In the experiments, the side wall film 22A in conformity of the above condition was formed. Next the interlayer insulation film 27 was deposited to a thickness of about 100 nm (1000 Å), which is enough to withstand a voltage required in conventional DRAM devices. Then the thick polysilicon film 28 having a thickness of about 0.5 µm was formed. Finally, the thick polysilicon film 28 was subjected to patterning. The inventor found that a fine polysilicon pattern can be formed with a high accuracy by the conventional photolithography technology. It was also found from the experiments that in addition to the aforementioned condition, namely a > d, the following condition is advantageous particularly to a thicker polysilicon film having a thickness of more than around 0.5 µm . In FIG.3, an angle ϑ is defined at which a lower end portion of the side wall film 22A and the surface of the field insulation film meet. It was found that in a case when the angle ϑ is equal to or less than 60°, the thicker polysilicon film can be well patterned by the conventional photolithography technology to thereby form fine polysilicon film. A description is given of a preferred embodiment of the present invention with reference to FIGS.4 through 11, which show cross sections of a portion of a DRAM device at respective essential manufacturing steps. Referring to FIG.4, the field insulation film 22 of silicon dioxide is formed on a surface of the p-type silicon semiconductor substrate 21 by selective thermal oxidation such as the local oxidation technique (LOCOS process). In the selective thermal oxidation process, a heat-resistant mask film is used which consists of a silicon dioxide film and a silicon nitride film which are stacked in this sequence. Next the heat-resistant mask film is removed so that a portion of the silicon substrate 21, or an active region is exposed. Then the silicon substrate 21 is subjected to thermal oxidation. Thereby a gate insulation film 23 having a thickness of approximately 20 nm (200 Å) is formed as shown in FIG.4. After that, a polysilicon film is grown to a thickness of about 200 nm (2000 Å) by chemical vapor deposition (CVD). Then a mask film is deposited by a resist process in the photolithography technology, and the polysilicon film is patterned by reactive ion etching in which an etching gas of CCl₄/O₂ is used. Thereby, gate electrodes 24₁, 24₂ and 24₃ are formed as shown in FIG.4. Then arsenic (As) ions are implanted in the silicon substrate 21 by ion implantation based on a self-alignment process in which the gate electrodes 24₁ - 24₃ are used as mask films. Thereby an n⁺-type source region (not shown) and an n⁺-type drain region 26 1A are formed in the substrate 21. At this time, the gate electrodes 24₁ - 24₃ and other metallization films (not shown) are also doped with arsenic ions. Referring to FIG.5, a silicon dioxide film is grown to a thickness of approximately 300 nm (3000 Å) by chemical vapor deposition. Then the silicon dioxide film is subjected to anisotropic etching by using reactive ion etching in which an etching gas of CHF₃ + H₂ is used. This anisotropic etching process is carried out until portions of the silicon dioxide film formed on flat surfaces of the gate insulation film 23 and the field insulation film 22, are completely removed. Even after etching, side wall films 22A remain which surround side walls of the gate electrodes 24₁ - 24₃ and which have slopes like arcs. Each side wall film 22A satisfies the aforementioned condition, a > d. The side wall films 22A are approximately 240 nm (2400 Å) wide, and approximately 200 nm (2000 Å) thick. Referring to FIG. 6, the interlayer insulation film 27 of silicon dioxide is grown to a thickness of approximately 100 nm (1000 Å) by chemical vapor deposition. Referring to FIG.7, the interlayer insulation film 27 and the gate insulation film 23 are subjected to selective etching by the conventional photolithography technology. Thereby a contact window 27A is formed so as to expose a portion of the drain region 26 1A in the silicon substrate 21. Referring to FIG.8, the polysilicon film 28 is grown to a thickness of about 0.5 µm by chemical vapor deposition. Then arsenic ions are implanted into the polysilicon film 28 by the ion implantation process. With the ion implantation, the polysilicon film 28 is changed to an n⁺-type conductive film. Referring to FIG.9, a mask film is deposited by the conventional resist process, and the polysilicon film 28 is subjected to the patterning process based on reactive ion etching in which an etching gas of CCl₄/O₂ is used. Thereby, storage electrodes 28 1A and 28 1B are formed. Each of the storage electrodes thus formed is one electrode out of paired electrodes of a memory cell capacitor. The projected area of the surface of each storage electrode projected onto a flat surface is almost identical to the total area of the side surfaces thereof. In a case where the projected area of the memory cell is equal to or less than 10 µm² , the store electrode 28 1A having the entire surface equal to or greater than 7 µm² is obtainable. Referring to FIG.10, dielectric films 29 1A and 29 1B each having a thickness of approximately 10 nm (100 Å) are formed on exposed surfaces of the storage electrodes 28 1A and 28 1B , respectively by the thermal oxidation process in which the silicon substrate 21 is placed in a wet atmosphere. Referring to FIG.11, by any suitable technique, opposed electrodes 30₁ of polysilicon (called cell plates), an interlayer insulation film 31 of silicon dioxide, bit lines 32 of polycide, a passivation film 33 of phosphosilicate glass (PSG), and metallization films 34 which function as word lines are formed. In the DRAM device thus formed, a transfer gate transistor of one memory cell is formed by the gate electrode 24₁, the source region 25 1A and the drain region 26 1A . A memory cell capacitor is formed by the storage electrode 28 1A , the dielectric film 29 1A and the opposed electrode 30₁. The storage electrode 28 1A is in contact with the drain region 26 1A , and thereby the transfer gate transistor and the memory cell capacitor are mutually connected. An information charge is written into and read out from the memory cell and is stored by controlling the ON/OFF state of the transfer gate.

Claims: A semiconductor device comprising:- a semiconductor substrate (21); an insulation film (22, 23) formed on the semiconductor substrate; a film (24₁, 24₂, 24₃) formed on the insulation film (22, 23) having a side wall; and a side wall film (22A) formed on the insulation film (22, 23) so as to surround the side wall of the film (24₁, 24₂, 24₃); characterised in that:- the device further comprises a patterned film (28) formed over the insulation film (22, 23) and side wall film (22A); and in that the side wall film (22A) satisfies the condition a > d where a is the width of a bottom surface of the side wall film (22A) which is in contact with the insulation film (22, 23) and d is the thickness of the film (24₁, 24₂, 24₃). A semiconductor device as claimed in claim 1, wherein an angle of inclination of the slope of the side wall film (22A) in the vicinity of the insulation film is equal to or less than 60°. A semiconductor device as claimed in claim 1, wherein the semiconductor device is a dynamic random access memory, and said film (24₁, 24₂, 24₃) is a gate electrode film, and wherein the semiconductor device further comprises an interlayer insulation film (27) formed so as to cover the gate electrode film (24₁, 24₂, 24₃), a memory cell capacitor (28 1A , 29 1A , 30₁) formed using said patterned film (28) on the interlayer insulation film (27) being in contact with the semiconductor substrate (21) through a contact hole which penetrates the insulation film (23) and interlayer insulation film (27), another interlayer insulation film (31) formed so as to cover the memory cell capacitor (28 1A , 29 1A , 30₁); and a bit line (32₁) formed on said other interlayer insulation film (31). A semiconductor device as claimed in claim 1, wherein said side wall film (22A) comprises silicon dioxide. A semiconductor device as claimed in claim 1, wherein the side wall film (22A) slopes from a top surface of the film (24₁, 24₂, 24₃) to the insulation film (22, 23). A process of producing a semiconductor device comprising the steps of:- forming a first insulation film (22, 23) on the semiconductor substrate (21); forming a film (24₁, 24₂, 24₃) on the first insulation film; patterning the film (24₁, 24₂, 24₃); depositing a second insulation film of silicon dioxide on the entire surface of the substrate (21); and etching the second insulation film by anisotropic etching until a portion of the second insulation film on a flat surface of the first insulation film (22, 23) is completely removed; so that a side wall film (22A) of a remaining portion of the second insulation film is formed on the insulation film (22, 23) surrounding the side wall of said patterned film (24₁, 24₂, 24₃); characterised in that:- the side wall film (22A) is formed so as to satisfy the condition a > d where a is the width of a bottom surface of the side wall film (22A) which is in contact with the insulation film and d is the thickness of the film; and in that the method comprises the further step of forming and patterning a further film (28) over the insulation film (22, 23) and the side wall film (22A). A process as claimed in claim 6, further comprising steps of: forming a third insulation film (27) to cover said patterned film (24₁, 24₂, 24₃) and the side wall film (22A); and forming a conductive film (28) as said further film, over the third insulation film. A process as claimed in claim 7, applied to manufacturing a DRAM, wherein said step of patterning the film (24₁, 24₂, 24₃) defines gate electrodes of memory cell transistors, and further comprising a step of patterning the conductive film (28) to define storage electrodes (28 1A , 28 1B ) of memory cell capacitors.

Inventors: EMA TAIJI, EMA, TAIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L27