MULTI-PLANE VIDEO RAM

Abstract: A multi-plane video RAM for displaying a color image on a display apparatus, including: a multi-plane bit operation unit (MBO) for performing calculations on input data from an external stage based on a predetermined rule corre­ sponding to an information applied from the external stage; and memory arrays (MA₀...MA₃) operatively connected to the multi-plane bit operation unit for storing resultant data calculated by the multi-plane bit operation unit, and each having three-dimensionally arranged k sets of memory planes each consisting of m (rows) x n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit oper­ ation unit are also simultaneously written thereto.

Description: The present invention relates to a multi-plane video random access memory (multi-plane video RAM), more particularly it relates to the structure of the multi-plane video RAM for displaying various color images on a display apparatus. Recently, a video RAM is widely used in the field of image processing apparatus, and this video RAM usually has a two dimensional logical structure consisting of a plane having X-Y directions. In this case, when displaying a color image on a display apparatus, it is necessary to form a three dimensional logical structure by adding a color element. That is, the third dimension having the color element is used for determining the color and intensity thereof. In general, the multi-plane video RAM for displaying a color image is provided in parallel in order to form the three dimensional structure. Such a structure, however, becomes very complex and the manufacturing cost is increased. The problems of the structure of the existing video RAM will be explained hereinafter. According to the present invention, there is provided a multi-plane video RAM for storing data of a color image to be displayed on a display apparatus, comprising:- a bit operation means for performing calculations on input data from an external stage, based on a predetermined rule corresponding to information applied from the external stage; and a plurality of memory arrays operatively connected to said bit operation means for storing resultant data calculated by said bit operation means, each memory array being logically arranged as k memory planes each consisting of m rows and n columns; characterised in that:- said bit operation means is a multi-plane bit operation means which processes k bits of data simultaneously to produce k bits of resultant data; and in that, in use, the same positions in each of said k memory planes are simultaneously accessed and said resultant data calculated by said multi-plane bit operation means are simultaneously written thereto. An embodiment of the present invention may provide a multi-plane video RAM having an improved three-dimensional structure and enabling three-dimensional access to memory arrays constituting the multi-plane video RAM. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a schematic view of an existing video RAM for explaining an existing access method; Figs. 2 and 3 are schematic block diagrams of an existing video RAM structure; Fig. 4 is a detailed block diagram of the bit operation unit (BO) shown in Fig. 3; Fig. 5 is a schematic view of a multi-plane video RAM for explaining a three-dimensional access method according to the present invention; Fig. 6 is a schematic block diagram of a multi-plane video RAM according to an embodiment of the present invention; Fig. 7 is a detailed circuit diagram of the memory plane bit operation unit (MBO) shown in Fig. 6; Fig. 8 is a detailed circuit diagram of the data concentration/distribution unit (DAD) shown in Fig. 7; Fig. 9 is a detailed circuit diagram of the column decoder amplifier (CDA) shown in Fig. 6; Fig. 10 is a signal timing chart for explaining the operation of the present invention; and Fig. 11 shows the content of the data stored in the fourth register (4R) shown in Fig. 7. Before describing the preferred embodiments, an explanation will be given of an existing video RAM structure. Figure 1 shows a schematic video RAM structure in an IC package, as a brief explanation of an existing access method. The video RAM includes four memory array blocks each having corresponding color memory planes. That is, for example, the memory chip (array) (R) comprises four red (R) memory planes for storing the red information. Similarly, the memory chip (G) comprises four green (G) memory planes and the memory chip (B) comprises four blue memory planes. Further, the memory chip (I) comprises four intensity memory planes used for adjusting the intensity of a pixel. The color signals are input from the external stage to a corresponding memory chip through a four terminal input/output port (not shown). For example, the R signals D₀₀ to D₀₃ are input to the four bits area 1 to 4 of the memory chip (R) based on an address ADD destinated by the external stage. Similarly, the G signals are input to the four bits area 1 to 4 of the memory chip (G), the B signals to the four bits area 1 to 4 of chip (B) and the I signal to the four bits area 1 to 4 of chip (I). The color of the pixel is determined based on these sixteen signals acces sed by the address signal ADD on the display apparatus (for example, CRT display). When the color of a next pixel is to be determined, the same access is repeated so that the display speed becomes slow. Therefore, the color display speed on the CRT is relatively slow, particularly, when displaying the same color over a predetermined area of the CRT. The structure of an existing multi-plane video RAM having dual ports and the problems thereof will be explained in detail hereinafter with reference to Figs. 2, 3, and 4. In Figs. 2 and 3, CC represents a clock generator, RC a refresh control unit, AB an address buffer, IOB an input/output buffer, BO a bit operation unit (Fig.3), CDAx a column decoder amplifier, RAD a row address decoder, MAx a memory array, RPx a register pointer, WCG a write clock generator, TC a transfer control unit, RAS a row address strobe signal, CAS a column address strobe signal, Ax an address signal, SAS a serial access memory strobe signal, MDx/Dx a mask data/parallel input output data signal, SDx a series input output data signal, ME/WE a mask enable/write enable signal, TR/OE a transfer enable/output enable signal, and SE a serial enable signal. In Fig. 2, the video RAM is divided into four memory array blocks MA₀ to MA₃ and each of the blocks MA₀ to MA₃ has an input/output terminal MDx/Dx (below, x = 0 to 3) for parallel access and the input/output terminal SDx (x = 0 to 3) for series access. When accessing the memory array in parallel, mask data is input to the buffer IOB through the terminal MDx/Dx in response to the various control signals RAS, CAS, ME/WE, TR/OE and the address signal Ax. Also, the write data is input from the terminal MDx/Dx and the data Dx is written to the memory array MAx. When accessing is in series, the stored data is read out from the memory array MAx to the pointer RPx in response to the above control and address signals and the read data is serially output from the buffer IOB to the terminal SDx in response to the strobe signal SAS. In Fig. 3, BO represents a bit operation unit. The unit BO is added to the structure shown in Fig. 2 and is provided for determining the content of the calculated (data) based on the data previously input from the address terminal Ax and for performing the logic calculation with the data input from the external stage through the terminal MDx/Dx. The resultant data is written to the memory array MAX. In Fig. 4, the bit operation unit BO shown in Fig. 3 is constituted by four blocks BOU₀ to BOU₃ each having the same structure. Each block comprises a mask register MR for storing the mask data, a source register SR for storing the source data, a destination register DR for storing the destination data and a raster operation block ROP for performing the logic calculation based on the source data and destination data corresponding to the mask data. Resultant data calculated by the block ROP is output to the column decoder amplifier CDA₀. In this case, each block is accessed one bit at a time as shown by "1". In these types of video RAM structure , the memory array units are arranged in a two dimensional physical structure. Therefore, when a three dimensional logical structure is required for displaying the color image, it is necessary to independently provide the memory arrays in parallel. Accordingly, it is necessary to access each memory array many times in order to obtain the required color pixel when displaying at the CRT displayer. Further, since in a memory IC the number of terminals cannot be increased in view of the space factor, the IC package is limited, and thus the number of data to be written is also limited. A multi-plane video RAM according to an embodiment of the present invention will be explained in detail hereinafter. Figure 5 shows a schematic multi-plane video RAM structure for briefly explaining an access method of the present invention. The video RAM includes four memory array blocks each having the same structure. Each memory array comprises the same number of memory planes each having four bits areas a to d enabling a read/write operation by one access. That is, each of bit areas a to d comprises four pixel data of the R signal. The signal D₀ is simultaneously input to all areas D₀₀ to D₀₃. Similarly, the signal D₁ is simultaneously input to all areas D₁₀ to D₁₃, the signal D₂ to all areas D₂₀ to D₂₃ and the signal D₃ to all areas D₃₀ to D₃₃, in each memory array. In this structure, since four pixels data can be read or written by one access, the color displaying speed on the CRT is considerably improved, particularly when displaying areas of the same color. In Fig. 6, MBO represents a memory plane bit operation unit for performing a logic calculation corresponding to the input data from the external stage based on a predetermined rule corresponding to the input information applied from the external stage. Each memory array MA₀ to MA₃ comprises four ( k = 4) memory planes, each of which is constituted by a one bit structure consisting of m (rows) x n (columns). Bits in the same corresponding positions of each of the four memory planes can be simultaneously accessed by one access operation. The column decoder amplifiers CDA₀ to CDA₃ are provided for decoding the column address and accessing the memory arrays MA₀ to MA₃. The register pointers RP₀ to RP₃ are provided for converting the parallel data read out from the memory arrays MA₀ to MA₃ to the serial data and outputting the serial data from the input/output buffer IOB. The basic operation of this circuit will be explained briefly hereinafter. The mask data MDx is input from the input/output terminal for parallel access MDx/Dx to the unit MBO through the buffer IOB, then the mask data MDx is held in the unit MBO. Further, the image data Dx to be displayed is input from the terminal MDx/Dx to the unit MBO through the buffer IOB. The unit MBO performs the calculation of the rule corresponding to the input mask data MDx with the input data Dx and the resultant data are simultaneously written to the position having the same address in the memory array MA₀ to MA₃ each having k memory planes. In this case, as can be understood, each memory array comprises k memory planes each having an m (rows) x n (columns) area. In Fig. 7, the multi-plane bit operation unit MBO comprises a data concentration/distribution unit DAD, a bit operation controller BCT, and four bit operation blocks BOU₀ to BOU₃. Each of the blocks BOU₀ to BOU₃ has the same structure and comprises a mask data generator MG, a source data multiplexer SMX, an SMX input data controller SIC, and a raster operation block ROP. The bit operation block BOU performs the calculation of the logic operation based on the rule corresponding to the input mask data MDx from the external stage with the input data Dx from the external stage, and the resultant data are written to the memory arrays MA₀ to MA₃ through the decoder amplifiers CDA₀ to CDA₃. 1R to 4R represent registers for holding various information. The unit DAD is provided for concentrating and distributing the data as explained in Fig. 8. The controller BCT is provided for generating various timing signals T₁ to T₄ to control the operation of the bit operation block BOU₀ to BOU₃ as shown in Fig. 11. An explanation will be given of the calculation of the logic operation based on the rule corresponding to the input mask data MDx from the buffer IOB. [First Step] The mode terminal MOD is set to the register mode RM. The strobe signals RAS and CAS are input to the clock generator CG. The generator CG generates a bit timing signal BT and this signal BT is input to the controller BCT in the unit MBO. The mask enable/write enable signal ME/WE is input to the buffer IOB through the write clock generator WCG. The transfer enable/output enable signal TR/OE is input to the buffer IOB. The address signal Ax is input to the address buffer AB and the buffer AB generates a bit address signal BA. The address signal BA is input to the controller BCT and the register pointer PRx. The data Dx is set to the registers 1R to 4R based on the timing signals T₁ to T₄ through the buffer IOB and the unit DAD. In this case, the first register 1R stores the data Fx of the multiplexer SMX. The second register 2R stores the data Bx also of the multiplexer SMX. The third register 3R stores the mask data MDx of the mask data generator MG. The fourth register 4R stores the calculation data of the raster operation block ROP. For example, when a dotted-line is displayed on the CRT, the fourth register 4R stores the data "1010" as shown in Fig. 11. [Second Step] The mask data MDx is input to the mask generator MG through the buffer IOB and the unit DAD. The data stored in the register 3R is read out and, further, input to the mask generator MG. The mask generator MG performs the OR logic calculation regarding both mask data, and the resultant data is applied to the block ROP. The logic calculation of the corresponding bit is inhibited by this operation. [Third Step] The four bits data Dx (below, line data) is input to the input data controller SIC. The controller SIC outputs the input line data Dx to the selection terminal of the multiplexer SMX. The multiplexer SMX selects one of three data among the one bit data Fx from the register 1R, the one bit data Bx from the register 2R, and the line data Dx from the external stage based on the selection signal from the multiplexer SMX. The data selected by the multiplexer SMX is input to the block ROP. For example, when the line data Dx "1101" is input from the external stage, the line data Dx "1101" is input to the selection terminal of the multiplexer SMX through the controller SIC. The multiplexer SMX outputs source data S "Fx, Fx, Bx, Fx" to the block ROP. In this case, the source data S "F₀ , F₀ , B₀ , F₀" is input to the block ROP in the bit operation block BOU₀ , the source data S "F₁ , F₁ , B₁ , F₁" is input to the block ROP in the block BOU₁. Similarly, the source data S "F₂ , F₂ , B₂ , F₂" is input to the BOU₂ and the source data S "F₃ , F₃ , B₃ , F₃" to the BOU₃. [Fourth Step] The source data S "Fx, Fx, Bx, Fx" from the multiplexer SMX and the destination data Dx from the memory array MAx are input to the block ROP. Since the fourth register 4R stores the calculation information "1010", the source data Sx is output from the block ROP for the non-inhibited bit by the input mask data M from the generator MG. The block ROP outputs the destination data Dx for the inhibited bit. Based on the above operation, only the non-inhibited data by the mask data M is replaced by the source data Sx, and then the desired line can be displayed at the CRT. [Fifth Step] The data output from the block ROP are written to the memory array MAx through the decoder amplifier CDAx. In Fig. 8, the data concentration/distribution unit DAD comprises four data concentration/distribution blocks B₀ to B₃ , each having the same structure. Each block comprises eight drivers D₀ to D₇. The lines L₀ to L₃ are connected to the buffer IOB. One bit line L₀ is distributed to four bit lines ℓ₀ to ℓ₃ through the drivers D₀ to D₇. The sixteen output lines ℓ₀ to ℓ₁₅ are connected to the data bus line DB shown in Fig. 7. Each driver is constituted by, for example, a tri-state element, and controlled by the read/write signal R/W from the bit operation controller BCT through the decoder. That is, the input/output operation of the driver is selected by the signal R/W. One line in four bits lines from the memory array is selected by the two bits decode signal of the address ADD. In Fig. 9, the column decode amplifier CDA comprises a plurality of drivers (D₀ , D₁ , D₂ ...). Four bits lines L₀ to L₃ are connected to the data bus DB and 512 bits lines (ℓ₀ , ℓ₁ , ℓ₂ ...) are connected to the memory array MAx. The driver is selected by the read/write signal R/W from the bit operation controller BCT. Four lines in 512 lines are selected by the seven bits decode signals in the nine bits address ADD. In Fig. 10, the timing signals T₁ to T₄ are output from the bit operation controller BCT. The mode RM corresponds to the procedures described in the above first step. 1GD to 4GD represent the four bits parallel data input from the external stage. 1GA to 4GA represent the address signals and W or R represents memory cycle. The parallel data 1GD to 4GD are written to the register 1R to 4R accessed by the address signal 1GA to 4GA through the buffer IOB and the unit DAD. Each of the memory cycles W corresponds to each access to the register 1R to 4R. The data, the mask data, and the calculation information are set to the register 1R to 4R by the above write operation. The mode MM corresponds to the procedures described in the above second to fifth steps. The logic calculation operations, which are designated by the contents stored in the register 4R, are performed for the source data Sx from the external stage based on the destination data Dx read out from the memory array MAx, and the resultant data are written in the corresponding memory array MAx. In Fig. 11, the fourth register 4R stores the four bits of data indicated to the left side. These four bits of data are set to the register 4R by the first step. D represents the destination data read out from the memory array Max. S represents the source data. Further, D and S are inverted signals. Based on the first to fifth steps, the logic calculation operations, which are designated by the contents stored in the register 4R for the non-inhibited bit by the mask data M, are performed for the source data Sx in the block ROP based on the destination data Dx from the memory array MAx. The resultant data is written to the corresponding memory array MAx. In this case, four bit operation blocks BOU₀ to BOU₃ are provided for enlarging the display area. Further, since the structure having, for example, color information indicated by the depth direction bit (information of k = 4 bits) is provided in each of bit operation blocks BOU₀ to BOU₃ , it is possible to achieve a high speed video RAM access by arranging this structure on the same IC chip. In an embodiment of the present invention, the numbers of k and n of the memory planes are given by a power of two.

Claims: A multi-plane video RAM for storing data of a color image to be displayed on a display apparatus, comprising:- a bit operation means (MBO) for performing calculations on input data from an external stage, based on a predetermined rule corresponding to information applied from the external stage; and a plurality of memory arrays (MA₀, ... MA₃) operatively connected to said bit operation means for storing resultant data calculated by said bit operation means, each memory array being logically arranged as k memory planes each consisting of m rows and n columns; characterised in that:- said bit operation means (MBO) is a multi-plane bit operation means which processes k bits of data simultaneously to produce k bits of resultant data; and in that, in use, the same positions (a ... d) in each of said k memory planes are simultaneously accessed and said resultant data calculated by said multi-plane bit operation means (MBO) are simultaneously written thereto. A multi-plane video RAM as claimed in claim 1, wherein k and n are each a power of two. A multi-plane video RAM as claimed in claim 1 or 2, wherein said bit operation means (MBO) includes first and second k-bit registers (1R, 2R) for storing predetermined data (Fx, Bx), wherein, in use, the predetermined data from one of said first and second registers is selected and written to said k memory planes on the basis of one-bit input data from the external stage. A multi-plane video RAM as claimed in claim 3, wherein said bit operation means (MBO) further comprises a third k-bit register, (3R) and in use, the predetermined data stored in said first or second register (1R, 2R) is written to a selected one of the k bits in said k memory planes, said selected bit being set to a write enable state by said third register (3R), and other bits except for said bit being maintained in a previous state. A multi-plane video RAM as claimed in claim 3 or 4, wherein said bit operation means (MBO) performs corresponding logic calculations on k-bit destination data read from said memory planes and on predetermined data stored in said first or second register (1R, 2R) as selected by one-bit data input from the external stage, and the resultant k bits of data from said logic calculation are written to corresponding areas of said memory planes.

Inventors: ANDO, HISASHIGE, SAKURABA, TAKAHIRO, SASANUMA, SABURO
Applicants: FUJITSU LIMITED
Application year: 1988
Main classification: G09G1
IPC codes: G06F12, G09G5, G11C11, G06T1