Switched-capacitor network

Abstract: Switched capacitor network (10), comprising an input terminal (1), an output terminal (2), a series arrangement of a first (T₁) and a second (T₂) switching transistor, each having a control electrode (6 and 7, respectively) for receiving a first (S₁) and a second (S₂) switching signal, respectively, and a capacitance (C s ) between the junction point of the two switching transistors and a point of constant potential. The two switching transistors (T₁, T₂) have a zone (17) in common and the capacitance (C s ) is exclusively constituted by the parasitic capacitance of the zone (17).

Description: The invention relates to a switched capacitor network, arranged in integrated form in a substrate of a semiconductor body, comprising an input terminal and an output terminal, a series arrangement of at least a first and a second successive switching transistor arranged between the input terminal and the output terminal, each switching transistor having a control electrode for receiving a switching signal, and a capacitance between the junction point of the first and the second switching transistor in the series arrangement and a point of constant potential, the control electrodes of the first and the second switching transistor being adapted to receive a first and a second switching signal, respectively, each of the two switching signals being in the form of a number of one or more successive pulses, which number is equal for both switching signals, the pulse(s) of the first switching signal not overlapping those of the second switching signal with respect to time and the frequencies of occurrence of the pulses in the two switching signals being substantially equal if said number of pulses is two or more. A capacitor network of this type is known, for example, from Philips Technisch Tijdschrift 41, 1983, no. 4, pages 109-129. The Article in this Journal relates to the use of a switched capacitor network in a switched capacitor integrator. The time constant of this switched capacitor integrator is too small for some applications. It is an object of the invention to provide a switched capacitor network which, when applied in a switched capacitor integrator, provides the possibility of realizing larger time constants. To this end, the switched capacitor network is characterized in that the two successive first and second switching transistors each have a first semiconductor zone of a first conductivity type separated by a channel region of a second conductivity type from a second semiconductor zone of said first conductivity type, in that the first and second switching transistors have the second zone in common, in that the control electrode of each switching transistor overlies the associated channel region, in that the control electrode at least substantially does not extend over the area of the first and second semiconductor zone and in that the capacitance is exclusively constituted by the parasitic capacitance of the common zone. The time constant of the switched capacitor integrator is proportional to C f /C s in which C s is the aforementioned capacitance arranged between the junction point of the two switching transistors and the point of constant potential (ground) and C f is the value of the negative feedback capacitor arranged between the output and the inverting input of the operational amplifier arranged behind the capacitor network. The maximum value of C f /C s depends on the minimum value of C s and on the value which, within certain economic and technological limits, can be given to C f . Due to limitations at the level of the integration of C f in an integrated circuit, C f cannot be chosen to be too large. The minimum value of C s is limited by the parasitic capacitances of the switching transistors. According to the invention this knowledge is utilized by effectively determining the capacitance C s by means of the parasitic capacitances of the two switching transistors. This means that no capacitor is required between the junction point of the two switching transistors and the point of constant potential. However, provided that it is ensured that two successive switching transistors in the series arrangement have a (semiconductor) zone in common, the afore-mentioned capacitance, which is equal to the parasitic capacitance of this common zone, will have a sufficiently low capacitance to realize a desired, sufficiently large time constant in the switched capacitor integrator. Dependent on the technology and the type of switching transistor a capacitance of approximately 5 to 25 fF (1fF = 10⁻¹⁵F) can be realized. Moreover, the realization of a (semiconductor) zone which is common for two successive switching transistors results in an economy of space on the substrate, which leads to smaller circuits. The negative feedback capacitor may also be much smaller, which leads to a considerably larger economy of space on the substrate. EDN, Vol. 25, No. 6, March 20, 1980, pages 49-73, figure 1 discloses a charge transfer device comprising two successive transistors having a zone in common and using a series of capacitances for transfer of charge from the first transistor to the second transistor. These capacitances, however, are formed by a deliberate overlap of the respective control electrode with the associated common zone to provide a sufficient amount of charge transfer handling capacity. In this known device the control electrode essentially extends over the area of the common zone. The switched capacitor network comprising a series arrangement of a first and a second switching transistor may be further characterized in that the network also comprises a second series arrangement of a third and a fourth switching transistor each having a control electrode for receiving a switching signal, in that the third and the fourth switching transistor have a zone in common and in that the second series arrangement is arranged in parallel with the series arrangement of the first and the second switching transistor. This provides the possibility of compensating for the offset voltage which is present due to asymmetry in the switching transistors. Different specific layout configurations can now be proposed to reduce the offset voltage. US-A-4 344 050, figure 5 discloses a switched capacitor network also having two series arrangements of two switching transistors in parallel. In this known network the switching transistors have no zone in common. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings in which Fig. 1 shows a first embodiment, Fig. 1a shows the two switching signals for the switching transistors in the first embodiment, Fig. 2 shows the parasitic capacitances of a switching transistor, Fig. 3 shows the structure of the network of Fig. 1 in a vertical cross-section through the substrate of the circuit, Fig. 4 shows the network of Fig. 1 in a more diagrammatical form, Fig. 5 shows two different layout configurations of a second embodiment in Figs. 5a and 5b, Fig. 6 shows two different layout configurations of a third embodiment in Figs. 6a and 6b, Fig. 7 shows the electrical circuit diagram of the embodiments of Figs. 5 and 6, Fig. 8 shows a series arrangement of nine switching transistors in Fig. 8a and the layout configuration of the circuit of Fig. 8a in Fig. 8b, and Fig. 9 shows a layout configuration of a series arrangement of eight switching transistors. Fig. 1 shows an embodiment of a switched capacitor network 10 comprising a series arrangement of a first and a second switching transistor T₁ and T₂, respectively, between an input terminal 1 and an output terminal 2. Fig. 1 shows the use of the capacitor network in a switched capacitor integrator. To this end the output terminal 2 is coupled to the inverting input (-) of an operational amplifier 3. Its output 4 is coupled to the inverting input via a negative feedback capacitor C f . The non-inverting input (+) of the amplifier 3 is coupled to a point of constant potential (ground). The two switching transistors T₁ and T₂ have a zone in common. For the (MOS) transistor T₁ this is the zone on which normally the drain electrode is arranged and for the (MOS) transistor T₂ this is the zone on which normally the source electrode is arranged. This will be explained in greater detail with reference to Fig. 3. The two switching transistors T₁ and T₂ have a control electrode (the gate electrode) which is electrically coupled to terminals 6 and 7, respectively. A first and a second switching signal S₁ and S₂ can be applied to the terminals 6 and 7, respectively. See Fig. 1a which shows the two switching signals as a function of time. In the absence of a switching signal, i.e. the switching signal is low, the switching transistors are turned off. This means that they represent an open switch. Under the influence of the switching signal, or in other words, the switching signal is "high", the switching transistors are turned on, that is to say, they constitute a switch in the closed position. It is evident that the switching transistors are N-MOS transistors in this case. If the switching transistors are P-MOS transistors, the switching signals should of course be applied in an inverted form to the terminals 6 and 7. The capacitance between the junction point 5 of the two switching transistors T₁ and T₂ and the point of constant potential (ground) is determined and solely formed by the parasitic capacitances of the two switching transistors. Thus no separate capacitor is arranged between the point 5 and "ground". Fig. 2 shows the parasitic capacitances of a MOS switching transistor T i , in which i in accordance with Fig. 1 may be equal to 1 or 2. A parasitic capacitance C 1i is present between the source electrode s and the gate electrode g, a parasitic capacitance C 2i is present between the gate electrode g and the drain electrode d, and parasitic capacitances C 3i and C 4i are present between the source electrode and the bulk terminal b and between the drain electrode and the bulk terminal b, respectively. Fig. 3 is a cross-section of the switched capacitor network of Fig. 1 as arranged in an integrated form in the substrate. In this case an N-MOS design is used. Fig 3 shows a p-doped substrate 15 in which n-doped zones 16, 17 and 18 are provided. Insulating oxide layers 19, 20, 21 and 22 are provided on the substrate. These layers in turn carry conducting layers in the form of conducting silicon layers 23, 24, 25 and 26. The conducting layer 23 constitutes the source electrode of switching transistor T₁ and is electrically coupled to the input terminal 1. The conducting layer 24 constitutes the gate electrode of switching transistor T₁ and is coupled to the control signal input 6. The conducting layer 25 constitutes the gate electrode of switching transistor T₂ which is coupled to the control signal input 7. The conducting layer 26 constitutes the drain electrode of the switching transistor T₂ which is electrically coupled to the output terminal 2. The switching transistor T₁ and the switching transistor T₂ have the zone 17 in common. Consequently, this common zone is the n-zone 17. Thus there is no drain electrode of the switching transistor T₁ and no source electrode of the switching transistor T₂ physically present on the substrate. At the area of the zone 17 there is neither an external capacitor which could serve as a capacitance between the junction point of the two switching transistors and the point of constant potential (ground). Only the parasitic capacitance of the common zone 17 is present. This parasitic capacitance C s (see Fig. 1) is actually constituted by the sum of the parasitic capacitances C₂₁ and C₄₁ of switching transistor T₁ and the parasitic capacitances C₁₂ and C₃₂ of the switching transistor T₂, see Fig. 2. The operation of the switched capacitor integrator of Fig. 1 will hereinafter be described in greater detail with reference to the switching signals of Fig. 1a. Fig. 1a show the first switching signal S₁ which is applied to the control electrode 6 of the first switching transistor T₁ and the second switching S₂ which is applied to the control electrode 7 of the second transistor T₂. Both switching signals are in the form of pulse series. The pulses have a frequency f n of occurrence for which it holds that f n = 1/T in which T is the period in a pulse series. The pulses of the second switching signal S₂ are shifted with respect to time over T₂ with respect to the pulses in the first switching signal S₁. The pulses in the first and the second switching signal do not overlap one another with respect to time. Under the influence of the pulse at the instant t = t₀ in the switching signal S₁, the switching transistor T₁ is turned on for a short period from the instant t₀. The parasitic capacitance C s is now charged to the voltage Vref which is present at the input 1 of the integrator. It is assumed that the capacitor C f is discharged in advance by a reset signal which is applied to a switch (not shown) arranged parallel to the capacitor C f , which switch closes for a short period for this purpose. Under the influence of signal S₂ the switching transistor T₂ will subsequently be turned on for a short period from the instant t₀ + T/2. As a result, the capacitance C s is discharged and the capacitor C f is charged. A voltage which is equal to -Vref.C s /C f =α.Vref is then produced at the output 4. Subsequently a pulse is applied to the switching transistor T₁ at the instant t = t₀ + T and a pulse is applied to the switching transistor T₂ at the instant t = t₀ + 3T/2 . A voltage which is equal to 2.α.Vref. is then produced at the output 4. After each subsequent combination of a pulse in the switching signal S₁ and a pulse in the switching signal S₂ the output voltage will have increased each time by α.Vref. The time constant τ of the integrator of Fig. 1 is given by τ = C f /C s .f n The parasitic capacitance C s , together with the pulse frequency f n , defines an effective resistance R. This effective resistance, together with C f , defines the time constant τ and is equal to R = 1/C s .f n . A large time constant is produced by choosing f n to be low and C f /C s to be large. In practice the lower limit for f n is determined by the bandwidth of the input signal and the sampling theorem and by the technological limitations resulting in leakage currents. The maximum value of C f /C s depends on the minimum value of C s and the value which can be given to C f within certain economic and technological limits. In practice C f will be chosen to be not larger than 50-100pF. The minimum value of C s is limited by the parasitic capacitances of the two switching transistors. By having the capacitance C s determined solely by the parasitic capacitances of the switching transistors, a very low capacitance can be realized. Dependent on the technology and the type of switching transistor the switched capacitance C s will have a value of approximately 5-25 fF. With C f of 50 pF and C s of 5 fF, a time constant of 0.1 s. can be realized at a clock frequency f n of 100 kHz. Practical tests on the circuit of Fig. 1 have proved that it is realizable and usable. It has also been found that the offset voltage, which results from the asymmetry in the switching transistor, plays an important role. Particularly the gate-source and gate-drain overlap capacitances C₁₁ and C₂₂ are concerned. For this reason specific layout configurations are proposed for the relevant input circuit 10 with the switched parasitic capacitance C s to reduce the offset voltage. The indication of a switched capacitor network such as the network 10 in Fig. 1 will hereinafter be given in the form as shown in Fig. 4. Fig. 5 shows the switched capacitor network 10 in Fig. 5a with which a second switched capacitor network 10′ comprising a series arrangement of a third and a fourth switching transistor T₃ and T₄ is arranged in parallel. The control electrodes of the switching transistors T₁ and T₃ are coupled together. Similarly, the control electrodes of the switching transistors T₂ and T₄ are coupled together. This compensates for the geometrical asymmetry of the switching transistors, which is the result of limitations in the manufacturing process, so that a reduced offset voltage is obtained. Fig. 5b shows an alternative layout; the switching transistors are slightly further apart and are aligned. It is true that the compensation will usually be reduced thereby, but the circuit has the advantage that the various connection leads do not cross one another so that parasitic coupling capacitances are not produced. Figs. 6a and 6b show two alternatives, be it that the associated circuit diagram is now slightly modified: the two parallel capacitor networks are now switched out of phase (see Fig. 7). This has the additional advantage that clock asymmetry is also compensated for. In addition it provides the possibility of realizing the layout of Fig. 6a in which the gate structures of the compensating switches are uninterrupted. This may further reduce the sensitivity to geometrical errors (notably mask errors). Fig. 7 shows the electrical circuit diagram of the two parallel-arranged capacitor networks 10 and 10'. The switching transistors T₁ to T₄ are shown as switches. C s ' is the parasitic capacitance of the zone which is common to the switching transistors T₃ and T₄. In the networks according to Figs. 5a and 5b the switches T₁ and T₃ are firstly closed simultaneously. This means that the two parasitic capacitances C s and C s ' are charged to the voltage Vref₁ which is present at the input terminal 1. After the switches T₁ and T₃ have been opened, the switches T₂ and T₄ close simultaneously and the two capacitances are discharged via the output terminal 2. In the networks according to Figs. 6a and 6b the switches T₁ and T₄ are closed simultaneously. This means that the capacitance C s is charged to the voltage Vref and the capacitance C s ' is discharged via the output terminal 2. Subsequently, the switches T₁ and T₄ are opened and then the switches T₂ and T₃ close simultaneously. This means that the capacitance C s is discharged via the output terminal 2, whilst the capacitance C s ' is charged to the voltage Vref. A further reduction of the (effectively) switched capacitance may be obtained by arranging a larger number of switches in series, as in Fig. 8a. The network comprises nine series-arranged switching transistors T₁ to T₉ in which each time two successive switching transistors T i and T i+1 have a zone in common. The common zone then has a parasitic capacitance C si . A compensation is also possible for such a network, see Fig. 8b. The nine switching transistors are to this end arranged along a U-shaped line on the substrate. Fig. 9 shows an embodiment in which eight series-arranged switching transistors T₁ to T₈ are arranged along a U-shaped line on the substrate. It is to be noted that the invention is not limited to the embodiments shown. The invention may also be used for those embodiments which differ from the embodiments shown in aspects not relating to the invention. For example, the networks are not limited to their use in a switched capacitor network, but they can generally be used where (parasitic) capacitances are switched.

Claims: A switched capacitor network arranged in integrated form in a substrate of a semiconductor body, comprising an input terminal (1) and an output terminal (2), a series arrangement of at least a first (T₁) and a second (T₂) successive switching transistor arranged between the input terminal (1) and the output terminal (2), each switching transistor having a control electrode (6, 7) for receiving a switching signal (S₁, S₂), and a capacitance (C s ) between the junction point (5) of the first (T₁) and the second (T₂) switching transistor in the series arrangement and a point of constant potential, the control electrodes (6,7) of the first (T₁) and the second (T₂) switching transistor being adapted to receive a first (S₁) and a second (S₂) switching signal, respectively, each of the two switching signals being in the form of a number of one or more successive pulses, which number is equal for both switching signals, the pulse(s) of the first switching signal not overlapping those of the second switching signal with respect to time and the frequencies of occurrence of the pulses in the two switching signals being substantially equal if said number of pulses is two or more, characterized in that the two successive first (T₁) and second (T₂) switching transistors each have a first semiconductor zone (16, 18) of a first conductivity type separated by a channel region of a second conductivity type from a second semiconductor zone (17) of said first conductivity type, in that the first (T₁) and second (T₂) switching transistors have the second zone (17) in common, in that the control electrode (6, 7) of each switching transistor overlies the associated channel region, in that the control electrode (6, 7) at least substantially does not extend over the area of the first (16, 18) and second (17) semiconductor zone and in that the capacitance (C s ) is exclusively constituted by the parasitic capacitance of the common zone (17). A switched capacitor network as claimed in Claim 1, comprising a series arrangement of a first (T₁) and a second (T₂) switching transistor, characterized in that the network also comprises a second series arrangement of a third (T₃) and a fourth (T₄) switching transistor each having a control electrode for receiving a switching signal, in that the third (T₃) and the fourth (T₄) switching transistor have a zone in common and in that the second series arrangement is arranged in parallel with the series arrangement of the first (T₁) and the second (T₂) switching transistor. A switched capacitor network as claimed in Claim 2, characterized in that the control electrodes of the first (T₁) and the third (T₃) switching transistor are coupled together and in that the control electrodes of the second (T₂) and the fourth (T₄) switching transistor are coupled together. A switched capacitor network as claimed in Claim 2, characterized in that the control electrodes of the first (T₁) and the fourth (T₄) switching transistor are coupled together and in that the control electrodes of the second (T₂) and the third (T₃) switching transistor are coupled together. A switched capacitor network as claimed in Claim 3 or 4, characterized in that the four switching transistors are arranged on the substrate along a straight line. A switched capacitor network as claimed in Claim 3 or 4, characterized in that the two series arrangements of two transistors are arranged parallel and adjacent to each other on the substrate. A switched capacitor network as claimed in Claim 1, comprising n series-arranged switching transistors (T₁, ..., T₉) characterized in that for each set of two successive switching transistors it holds that they have a zone in common, in that the switching transistors with an ordinal number i (i odd and larger than zero) have control electrodes which are electrically coupled together for receiving the first switching signal, and in that the switching transistors with ordinal number i+1 have control electrodes which are also electrically coupled together for receiving the second switching signal. A switched capacitor network as claimed in Claim 7, characterized in that the n switching transistors are arranged along a U-shaped line on the substrate, in that for n being odd the switching transistors 1 to (n-1)/2 are arranged along the one leg of the U on the substrate, in that the switching transistors (n+3)/2 to n are arranged along the other leg of the U on the substrate and in that the (n+1)/2nd switching transistor is arranged on the remaining part of the U, and in that for n being even the switching transistors 1 to n/2 are arranged along the one leg of the U on the substrate and the switching transistors (n+2)/2 to n are arranged along the other leg of the U on the substrate.

Inventors: KAMP PETRUS JOHANNES MARIA, VAN ROERMUND ARTHUR HERMANUS M, KAMP, PETRUS JOHANNES MARIA, VAN ROERMUND, ARTHUR HERMANUS MARIA
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1988
Main classification: H03H19
IPC codes: H03H19