Method for forming uniform layers of material

Abstract: The method comprises the steps of providing a layer of material on portions of the surface of a support structure; providing a polishing stop layer of substantially uniform thickness on different portions of the surface of said support structure, such that a first surface of said layer of material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of material; polishing the second surface of said layer of material to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness. In particular the method is used for forming improved silicon-on-insulator structures.

Description: The present invention relates to a method of providing a uniform and/or planarized layer of material. Reference is made to the following European patent applications, forming part of the state of the art in accordance with Article 54(3)EPC: European Patent Application EP-A-0 223 920, entitled "Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films On A Substrate," with priority of October 28, 1985 by Beyer et al, and assigned to the assignee of the present application. This application is directed to forming apertures in an insulator layer, overfilling these apertures with metal, and polishing the metal back so that portions above the surface of the insulator layer are removed. European Patent Application EP-A-0 224 646, entitled "Method For Removing Protuberances At The Surface Of A Semiconductor Wafer Using A Chem-Mech Polishing Technique," with priority of October 28, 1985 by Beyer et al, and assigned to the assignee of the present application. This application is directed to planarizing oxide protuberances by using a silicon nitride layer as an etch-stop. European Patent Application EP-A-0 224 013, entitled "Method For Producing Coplanar Multi-Level Metal/Insulator Films On A Substrate And For Forming Patterned Conductive Lines Simultaneously With Stud Vias," with priority of October 28, 1985 by Chow et al, and assigned to the assignee of the present application-. This application is directed to patterning a glass layer so that it simultaneously defines a wiring plane and an interconnection stud, filling the patterned glass with metal so as to form the structures, and polishing portions of the metal above the surface of the glass layer so that the metal is coplanar with the glass. BACKGROUND ART In the present era of very large scale integrated (VLSI) circuits, there has been a trend toward shrinking the dimensions of transistors and other semiconductor structures to facilitate greater packing densities. With this shrinkage and denser packing of semiconductor devices, substrate leakage currents and device interactions have become a concern which require some form of isolation between devices. A number of approaches has been proposed to provide this isolation. For example, U.S. Patent No. 3,979,237, issued to Marcom et al, discloses a method of forming grooves in a semiconductor body, coating the grooves with an insulating layer, refilling the grooves with a silicon material, and then planarizing the top of the refilled grooves to ensure that the top of the silicon areas is planar. As a result, there are provided insulated grooves filled with semiconductor material. A recent technology which appears to be particularly promising in providing greater isolation is that of a silicon-on-insulator (SOI) approach. For example, IBM Technical Disclosure Bulletin , Volume 24, No. 9, February 1982, authored by Chu, Tsang, and Joy, discloses a method whereby isolated silicon regions are embedded in indentations in a dielectric substrate. Similarly, IBM Technical Disclosure Bulletin , Volume 27, No. 8, January 1985, authored by Silvestri, discloses a method of forming fully isolated epitaxial silicon growth regions on an insulator, which are then used to facilitate the construction of fully isolated FET, Bipolar, and MOSFET integrated circuits. Often in achieving the desired SOI structure, bonding methods are applied to fuse one silicon wafer to a second "Handle" wafer. Examples of these bonding methods can be seen in Laskey, "Wafer Bonding for Silicon-On-Insulator Technologies", Appl. Phys. Lett. , 48(1), 6 January, 1986; and Laskey, Stiffer, White, Abernathey, "Silicon-On-Insulator (SOI) By Bonding and Etch-Back", IEDM 28.4, 1-4 December, 1985. One type of silicon-on-insulator construction with which the present invention is concerned is illustrated in, and will be described with reference to, Figures 1A and 1B. In Figure 1A, a thin silicon layer 104 is on top of a thin insulator 102. The insulator layer 102 can be formed of any insulating material, and typically is silicon dioxide. Mechanical support and integrity are also provided by formation on a support body 100, which is typically a silicon wafer. In Figure 1B, the silicon-on-insulator layer of Figure 1A has been masked, etched, and otherwise processed to provide isolated devices 110, 112, 114, and 116 formed on silicon islands 120, 122, 124, and 126, respectively. These silicon islands can be doped or otherwise treated to fabricate any of a multitude of semiconductor devices, for example, FET amplifiers, bipolar amplifiers, MOSFETs, etc. Note that the devices are totally isolated from one another, thereby preventing stray substrate leakage currents, and also preventing undesirable interactions between devices. Also, note that the height of the device 112 is different from the height of devices 110, 114 and 116. This non-uniformity is due to the localized planar non-uniformity 106 indicated in Figure 1A. As the device 112 has a shorter silicon island 122 than the silicon islands 120, 124 and 126 of the devices 110, 114, and 116, respectively, the device 112 effectively has a smaller silicon substrate area which produces a device 112 having operational parameters different from those of the devices 110, 114, and 116. In order to facilitate construction of semiconductor devices having substantially the same operational parameters, it would be desirable to have an SOI layer which has a planar top surface and is of uniform thickness. It is also desirable to have an SOI layer with a planar top surface and a body of uniform thickness for several other reasons. First, projected photomask exposures may be slightly out of focus at localized planar non-uniformities. Second, if the tops of the resultant devices are planar, metalization wiring structure mask tolerances are somewhat relieved, and etch times to form stud-down structures to connect to the devices can be more accurately predicted. Figure 2A illustrates a silicon-on-insulator (SOI) having the desired characteristics of a planar top surface and a body of uniform thickness. In particular, a silicon layer 204 is on top of the insulator layer 102 which, in turn, is provided on top of the support body 100. In Figure 2B, the silicon-on-insulator layer of Figure 2A has been masked, etched, and otherwise processed to provide isolated devices 210, 212, 214 and 216 constructed on uniform silicon islands 220, 222, 224, and 226, respectively. Since the silicon islands 220, 222, 224, and 226 are uniform in thickness, the devices 210, 212, 214 and 216, respectively, have substantially similar operating parameters. Also, as the tops of the resultant devices are substantially planar, tolerance requirements in the end of the line processing to add a metalization wiring structure will be somewhat relaxed. One prior art teaching which has achieved excellent results in producing a substantially uniform and planar SOI layer is that of U.S. Patent No. 4,601,779, assigned to the present assignee, and issued to Abernathey et al (EP-A-0 207 272). The resultant SOI structures by Abernathey et al serve as a preferred starting structure for the present invention, and as such, the teachings of Abernathey et al are incorporated herein by reference. However, there exists a need for a method which produces still greater planarity and thickness uniformity for silicon-on-insulator layers. Thus, the broad object of the present invention is to provide an improved process for providing a planar and/or uniform layer of material. A second object of this invention is to provide a fabrication process whereby the top surface of a layer of material can be polished to a surface which is substantially planar. It is another object of this invention to provide a fabrication process whereby a layer of material can be constructed to have a substantially uniform thickness. These objects are achieved by methods as disclosed in claims 1 to 11. The polishing stop layer has a first surface which is coplanar with the first surface of a thicker layer of material. The second surface of the thicker layer of material is then polished, such as by chemically-mechanically polishing, in a planar mode to a point where the second surface of the thinner polishing stop layer is encountered. As a result, the substantially uniform thickness of the thinner stop layer is used to define the thicker layer of a material to a layer of uniform thickness or with other words said uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness. In particular a silicon-on-insulator structure having improved planarity and thickness uniformity is produced by the inventive methods. Other advantageous embodiments of the inventive methods are disclosed in the subclaims. The foregoing and other advantages, structures, and teachings of the present invention will become more apparent from the following detailed description of the preferred embodiment of the present invention. In the description to follow, reference will be made to the accompanying drawings, wherein: Figure 1A is a simplified cross-sectional view of a prior art silicon-on-insulator structure having a localized planar non-uniformity. Figure 1B is a simplified cross-sectional view of semiconductor devices formed from the silicon-on-insulator structure of Figure 1. Figure 2A is a simplified cross-sectional view of silicon-on-insulator structure having a top surface which is substantially planar, and a body which is of substantially uniform thickness. Figure 2B is a simplified cross-sectional view of semiconductor devices formed from the silicon-on-insulator structure of Figure 2A. Figures 3A-3F are simplified cross-sectional views of a silicon-on-insulator structure being fabricated by a preferred embodiment of the process of the present invention. Description of the Preferred Embodiment Turning now to a description of the present invention, Figures 3A and 3F will be used to illustrate and describe the processing steps in a preferred embodiment. It should be understood that the height, width and thickness dimensions shown in Figures 3A-3F are for the sake of example and clarity only, and are not intended to designate relative or actual dimensions; i.e., some dimensions may be exaggerated to improve the clarity of the illustrations. Typical dimensions, which are known, will be revealed in the written description. Referring now to Figure 3A, a simplified cross-section of an unprocessed prior art silicon-on-insulator structure is shown. More particularly, a silicon layer 304 is shown on an insulator layer 302 which, in turn, is on a support body 300. The insulator layer 302 is typically an oxide layer, and in a preferred embodiment is a silicon dioxide layer. The support body 300 provides support and integrity to the silicon-on-insulator layer, and is typically a silicon wafer. U.S. Patent No. 4,601,779, referenced previously, discloses a preferred method of forming the SOI structure illustrated in Figure 3A. Note that the silicon layer 304 has a localized planar non-uniformity 306. A typical thickness non-uniformity achievable by the forming method of this prior patent would be about a 0.2 micrometer variation. Also, note that the bottom or first surface of the silicon layer 304 is in contact with the top surface of the insulator layer 302. As will become more apparent in the following discussion, the top surface of the insulator layer 302 is, in effect, used as a reference plane. Figure 3B is a simplified cross-sectional view of the silicon-on-insulator layer of Figure 3A after it has been subjected to a first preferred processing step. More particularly, the silicon layer 304 has been processed by applying a resist layer 310 which is then masked and etched to define locations where isolated silicon bodies for device constructions are desired. Once the resist layer has been masked and defined, the silicon layer 304 is then directionally etched down to the underlying insulator layer 302 to define the isolated silicon studs 320, 322, and 324. Any method of directionally etching the silicon layer 304 without disturbing the underlying insulator layer 302 can be used, for example, any well known RIE etch which provides a high etching selectivity between the silicon and the underlying oxide layer. An etchant providing this high etching selectivity is, in a preferred embodiment, a chlorine-based etchant. After the etching of the silicon layer 304, the isolation regions formed between the silicon studs function as apertures to the underlying insulator layer 302. This function is important to the present invention in that the exposed portions of the top surface of the insulator layer 302 are again available to be used as a reference plane. At this point, it should be noted that the processing steps described thus far are not critical to the present invention. They are merely meant to be exemplary of a preferred processing embodiment, and any method defining silicon bodies and apertures registered to the insulating layer 302 could easily be substituted to achieve excellent uniformity with the use of the present invention. Examples of alternative embodiments would include silicon strips separated by etched grooves, and a silicon plane bordered by an etched moat. Returning to the illustrated embodiment and Figure 3C, a thin insulator film 329 is then provided to coat the silicon studs, 320, 322, and 324. This insulator film 329 is important in protecting the exposed silicon stud sidewalls from chemical reactions in the processing steps to follow. An example of a suitable insulator film 329 would be a deposit of 20 nm of plasma enhanced chemical-vapor-deposited (PECVD) oxide. Once the insulator film insulator 329 has been provided, a uniform layer 330 is directionally deposited to coat the tops of the silicon studs and the apertures therebetween. This layer 330 should be of uniform thickness on all horizontal surfaces which are exposed. The uniform thickness of the layer within the isolation regions is important in that it will be used as a polishing stop layer to stop a polishing process. As the polishing process will effectively be stopped at this uniform polishing stop layer, the polished silicon layer will effectively be defined to a layer of uniform thickness. Any method of directional deposition which results in a layer of uniform thickness on the horizontal surface can be used, for example, an evaporation process. There are two additional constraints which must be applied to layer 330. First, as the layer 330 will be used as a polishing stop layer with which to define the polished silicon layer to a layer of uniform thickness, the conformal layer must be thinner than the thinnest portion of the silicon layer. The second constraint is that, in order to provide an etch stop to the polishing process, the layer 330 must be of a material which has a polishing rate which is substantially slower than that of silicon. Examples of materials which would provide a lower polishing rate would include refractory metals such as tungsten, molybdenum, titanium, tantalum, platinum, palladium, nickel and cobalt. In a preferred embodiment, a good material is tungsten which has a polishing rate ratio of approximately 200:1 when compared with silicon. As an example of an appropriate layer, good results have been achieved by depositing 0.2 µm of tungsten via an evaporation process. Once the layer 330 has been provided as illustrated in Figure 3C, note that the bottom surfaces of the layer 330 within the apertures or isolation regions are in contact with the top surface of the insulator layer 302. In effect, the bottom or first surfaces of the remaining silicon layer portions and the bottom or first surfaces of the conformal layer 330 lying within the isolation regions are made coplanar. Thus, as mentioned previously, the underlying insulator layer 302 is, in effect, used as a reference plane with which to register the bottom or first surfaces of the remaining silicon layer and conformal layer 330 to one another. Then, the caps of the layer 330 which cover the silicon studs are removed along with the resist layer portions 310. In a preferred embodiment, the caps are removed because, as was mentioned above, the conformal layer 330 is a material which has a slow polishing rate. Since the next processing step to be applied is a polishing process, unnecessary time and wear to the polishing apparatus would be encountered if the polishing process were used to polish away the caps. In the preferred embodiment, the removal of the caps is accomplished via lift-off (e.g. stripping in n-methyl pyrollidone) of the resist layer 310. Note that, in order for this lift-off method to be effective, resist 310 must be thicker than material 326. The resultant silicon-on-insulator structure having the caps removed is illustrated in Figure 3D. Note in Figure 3D that the silicon stud 322 is slightly shorter than the silicon studs 320 and 324. This height variation is due to the original localized planar non-uniformity 306 which was described with reference to Figure 3A. Also, note that the conformal layer 330 lying within the insulation regions is thinner than the shorter silicon stud 322. Before a polishing process is applied, experience has shown the need for further treatment of the layer 330. During experimentations using a tungsten layer 330, it was found that, unless the tungsten was annealed to improve adhesion, large pieces of the tungsten layer would be torn off during the polishing process. Thus, in a preferred embodiment, the semiconductor structure is annealed for 5 minutes at 900°C in a wet forming gas anneal. In addition, during subsequent experimentations applying an annealing process, it was found that, unless an insulator film (329 in Figure 3C) was provided between the tungsten conformal layer 330 and the silicon studs, undesirable tungsten silicide would be formed. Thus, as described above, the insulator film 329 is required to protect the exposed silicon sidewalls of the silicon studs from undesirable chemical reactions. Once the annealing process is completed, a polishing process is applied in a planar mode to the tops of the silicon studs until, in effect, an etch stop is encountered when the polishing apparatus reaches a point where it encounters the larger surface areas of layer 330 in the isolation regions. In general, the polishing process is a physical abrasion process carried out in the presence of a slurry. As an example of a suitable polishing apparatus and method, during experimentations a Rodel IC40 Polishing Pad (at a pressure of approximately 68,9 m bar (1 PSI)) was used to polish the wafers in the presence of a Cabosil slurry at a pH of 10.8. "Cabosil" is the tradename of a fumed silica slurry sold by the Cabot Corp. In practice, any slurry having a high pH and having silicon, aluminium or other similar particulates should provide the general results described below. By using resistivity measurements during experimentations, it was found that 50 nm of tungsten was removed during 7 minutes of polishing for a polishing rate of 7,1 nm per minute. The same polishing procedure removes 0.4 µm of polysilicon in 20 seconds, for a polishing rate of 1.33 µm per minute. These data support the calculation of a polishing rate of 200:1 for tungsten to silicon. Once the etch-stop layer 330 is encountered and the polishing process stopped, the result is that the previous silicon studs 320, 322, and 324 have been polished down to silicon islands 370, 372, and 374 (Figure 3E). These silicon islands 370, 372 and 374 are of uniform thicknesses which correspond to the uniform thickness of layer 330 provided in the isolation regions. Thus, it can be seen that the uniform thickness of layer 330, which was provided in the isolation regions, is used as an exclusive function with which to define the thickness uniformity of the remaining silicon layer. As the thickness of layer 330 can be highly controlled during the deposition process, the thickness of the polished silicon layers can, therefore, also be highly controlled. Thus, there is provided a method whereby a uniform layer of slow polishing material can be used to mechanically stop a polishing process, such that thicker silicon layers can be polished to a layer of uniform thickness. Once the silicon studs 320, 322, and 324 have been polished down to silicon islands 370, 372, and 374 respectively, the remaining conformal layer 330 in the isolation regions, and the insulator films 329, are removed, thereby leaving isolated silicon islands with exposed sidewalls, thus facilitating sidewall implantation, passivation, and processing in the usual manner. In the final Figure 3F, the conformal layer 330 and the insulator films 329 are shown removed, and the silicon islands 370, 372, and 374 have been further processed to provide the devices 390, 392, and 394, respectively.

Claims: A method of planarizing a layer of material, comprising the steps of: applying a layer of material on a support structure; patterning said layer of material to form apertures therein, extending through said layer of material; forming in each of said apertures a polishing stop layer of uniform thickness which is thinner than said layer of material; polishing with a physical abrasive polishing process, such as chemical-mechanical polishing, said layer of material to a point where its surfaces are substantially coplanar with the surfaces of said polishing stop layer and optionally removing the remaining portions of said polishing stop layer. A method of providing a layer of material of uniform thickness, comprising the steps of: providing a support structure; applying a layer of material on portions of said support structure, providing a polishing stop layer of substantially uniform thickness on different portions of the surface of said support structure such that a first surface of said layer of material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of semiconductor material; polishing with a physical abrasive polishing process, such as chemical-mechanical polishing, the second surface of said layer of material in a planar mode to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness and optionally removing the remaining portion of said polishing stop layer. A method according to claim 2 further comprising a step of removing portions of said conformal polishing stop layer from the second surface of said layer of material. A method according to any one of claims 1 to 3, wherein said material is a semiconductor material, preferably silicon. A method according to any one of claims 1 to 4, wherein said support structure has an insulator layer, consisting e.g. of silicon dioxide, deposited thereon, having a planar surface and being used as a reference plane. A method as claimed in claim 5, wherein said polishing stop layer, preferably applied by evaporation, is selected from the group consisting of tungsten, molybdenum, titanium, tantalum, platinum, palladium, nickel and cobalt, with tungsten being preferred. A method according to claim 6, wherein said polishing stop layer is subject to an annealing process prior to said polishing step. A method according to any one of claims 4 to 7, comprising the step of providing an insulator film on exposed portions of said semiconductor material before said applying step, such as depositing about 20 nm of plasma enhanced chemical-vapor-deposited (PECVD) oxide, to prevent chemical reaction between said semiconductor material and material of said polishing stop layer. A method according to any one of claims 4 to 8, wherein said layer of semiconductor material is provided in the form of semiconductor bodies separated by isolation regions. A method according to any one of claims 4 to 9, wherein said physical abrasive polishing process is carried out in the presence of a slurry having preferably a pH value of greater than 7 and also preferably silicon particulates. A method according to any one of the claims 3 to 10, wherein said step of removing comprises a step of lifting-off a resist layer on the upper surface of said layer of material, such as stripping in n-methyl pyrollidone.

Inventors: LASKY JEROME BRETT, LASKY, JEROME BRETT
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1988
Main classification: H01L21
IPC codes: H01L21, H01L27