Microcode reading control system

Abstract: A microcode reading control system in an information processing equipment wherein a machine instruction is divided into microcodes as a plurality of steps, each step is further divided into a plurality of stages, and the stages of the microcodes are processed in parallel with advanced control, a first aspect of which provides duplexed control storages storing the microcodes read at a first step of the machine instruction, one of the control storages being read only at the first step of a branch target instruction of a branch instruction, and a second aspect of which provides a first control storage storing microcodes to control the first steps of the machine instructions and a second control storage storing microcodes to control the second steps and thereafter of the machine instructions, the first control storage reading the stored microcode at the second stage of the first step of the machine instruction, and the second control storage reading at the first stage of the second step and thereafter of the machine instructions. Thus, in a process of the branch instruction, the prior control can be accelerated.

Description: BACKGROUND OF THE INVENTION 1) Field of the Invention The present invention relates to an instruction executing control system controlled by a microprogram in an information processing equipment, particularly to a microcode reading control system with an advanced control. 2) Description of the Related Art A machine instruction in an information processing equipment is usually executed by the following steps. Namely, the machine instruction is read from a main storage in response to an address indicated by an instruction counter, the machine instruction is decoded, various controls are executed corresponding to the decoded instruction, and the instruction counter is increased by a length of the machine instruction. Since the machine instructions are stored in the main storage device in the processing sequence, when the machine instructions are read, an address of the next machine instruction to be read is anticipated. Therefore, while the equipment is decoding and processing, at the same time the equipment can read the next machine instruction. That is, an advanced control is possible. However, if a branch instruction is executed, since the content of the instruction counter is refreshed, a problem arises in that the fetch of the instruction in the advanced control becomes difficult. The branch instruction is important and occurs frequently in the information processing equipment, and therefore, a high speed processing of the branch instruction would greatly contribute to an improvement of equipment performance. Further, in the information processing equipment wherein a process of a machine instruction is divided into steps, each to be executed by a microcode, and the process in each step is carried out by a pipeline process in a multi-stage manner, an advanced reading of the microcode corresponding to the advanced reading of the machine instruction can be made. Therefore, an effective microcode reading control system must be provided in the advanced reading control when a branch instruction is processed. According to one prior art architecture disclosed in IBM Technical Disclosure Bulletin, vol. 22, No. 12, May 1980, pages 5536-5538, New York, US; J.J. Losq : "Asymmetric double decode computer", the computer has a pipelined structure with an instruction pre-fetch portion that looks ahead of the execution part and pre-fetches instructions related to branch portions of the instruction code. The pre-fetch portion has two decoders for going along respective conditional branches, with a fast decoder assigned to the most likely branch to be executed. SUMMARY OF THE INVENTION An object of the present invention is to provide a microcode reading control system utilizing an advanced control wherein a process at a first stage in a microcode of a first step of a general instruction which is first read does not interfere with that of a first stage in a microcode of a branch target instruction, the microcode reading of the first step in the branch target instruction is accelerated, and the processing speed of the system is thus improved. In accordance with the present invention the foregoing object, there is met by a microcode reading control system as defined in claim 1. By using the above concept, in the advanced control in the pipeline process, a process time is shortened by the time corresponding to a processing time for one stage when the branch instruction is executed. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a drawing showing an example of the process at each stage in a process of a microcode; Fig. 2A is a schematic block diagram showing a microcode reading control system according to a first embodiment; Fig. 2B is a schematic block diagram showing a modification of the system in Fig. 2A; Fig. 3 is a detailed block diagram of the system in Fig. 2B; Fig. 4A is a diagram explaining a microcode reading control in a general instruction in the system in Fig. 3; Fig. 4B is a diagram explaining the similar microcode reading control in a branch instruction; Fig. 5 is a detailed block diagram of a microcode reading control system according to an embodiment of the invention; Fig. 6A, 6B, and 6C are diagrams explaining a microcode reading control in the system in Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the explanation of embodiment of the invention, the related arts are explained in detail with reference to Fig. 1, Fig. 4A, and Fig. 4B. Figure 1 shows an example of a process in each stage of a microcode. Figures 4A and 4B are diagrams explaining a microcode reading control with an advanced control. Figure 4A shows the processes when executing a general machine instruction and Fig. 4B shows the processes when executing a branch instruction. It is assumed that, as shown in Fig. 1, Figs. 4A and 4B, each microcode is processed by a four stage pipeline. Figure 1 shows the operations in each stage, i.e., D, A, M, and E, of the microcode. Figure 4A shows the processes for executing the general machine instruction (hereinafter referred to only as instruction) using this microcode. In Fig. 4A, an instruction 1 (Inst. 1) comprises one microcode, i.e., the instruction 1 is ended by the execution of one microcode, an instruction 2 comprises three microcodes, and an instruction 3 comprises two microcodes. In the above case, the branch instruction is processed as shown in Fig. 4B. Namely, as is clear from the operation in each stage shown in Fig. 1, the branch instruction process reads a microcode corresponding to the branch instruction from the control storage at the stage D1, calculates an address of the branch target instruction at the next stage A1, fetches the branch target instruction at the stage M1, and decides a branch condition at the stage E1. When the branch target instruction is selected by the decision of the branch condition in stage E1, the next instructions 1, 2, and 3 (NEXT INST. 1, 2, and 3) which are prepared for processing after execution of the branch instruction is stopped at the stages M2, A3, and D4, respectively. Then, the process in a stage Dt, which is a reading process of the microcode in the branch target instruction, is initiated. It is assumed, in Fig. 4B, that all instructions comprise only one microcode, respectively. In addition, since the branch target instruction is fetched at the stage M1 of the branch instruction from the main storage, a read of the control storage at the time T4, simultaneously with the process of stage E1, is proposed before the decision by the branch condition. This is shown in the stage Dt′ in Fig. 4B. By this control, the start of the branch target instruction is accelerated, and therefore, the process time in the branch instruction is shortened. Nevertheless, the read from the control storage at the stage D4 in the next instruction 3 interferes with the stage Dt′, and as a result, it is difficult to avoid errors in the process. If the stage D4 does not belong to a first step of the machine instruction, the interference between the stages D4 and Dt′ does not occur because the control storage from which a microcode of the first step of the instruction is read is provided separetely from another control storage from which the second step and thereafter is read, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 60-103452 entitled "Microprogram Control System" by the same applicant. But, if the stage D4 belongs to the first step in the machine instruction, interference will occur. Embodiments are now explained with reference to the drawings. Note, in the figures, the same reference numerals denote the same objects. A first embodiment is shown in Figs. 2A, 2B, and 3. In Fig. 2A, the apparatus comprises a control storage 2′, another control storage 11, a general instruction register 4, and a branch target instruction register 3. The control storage 2′ is the same as the conventional control storage. In this control storage 2′, microcodes addressed at a first step in an instruction are collected in a portion 2′-1, and the other microcodes are collected in a portion 2′-2. Further, in this embodiment, the same microcodes collected in the control storage 2′-1 are stored in the control storage 11, which is read only at a first step of a branch target instruction. On the other hand, as disclosed by Japanese Unexamined Patent Publication (Kokai) No. 60-103452, another system is provided wherein a control storage 12 for a first step is prepared separately from a control storage 2 for a second step and thereafter. Namely, as shown in a schematic block diagram of Fig. 2B, a control storage 11 is provided which is the same as the control storage 12 for the first step, and is read only at the first step of a branch target instruction. As mentioned above, the control storage for the first step of the instruction is duplexed and one of the control storages is controlled to be read only in the first step of the branch target instruction. The operation of the above system is explained by an example shown in Fig. 3, with reference to Fig. 4A and Fig. 4B. A general instruction 1 is read from a main storage (not shown), the read information is then set to an instruction register 4, a stage D11 is executed at a time T1, a microcode of the first step of the instruction 1 is read from the control storage 12, and the microcode is set to a register A (60) through selectors 50 and 51. At the next time T2, a stage A11 of the instruction 1, which includes the address calculation or the like for memory accessing, is executed, a stage D21 of the next instruction 2 is executed according to the contents of the register A(60), in the same way, the microcode of the above-mentioned instruction 1 is shifted to a register M (61), and a microcode of a first step of the instruction 2 is set to the register A (60). The instruction 2 is executed by processing the three microcodes as mentioned above, and therefore, at a time T2, a micro-address generator 6 generates an address of the microcode of the second step of the instruction 2 and the address is set to an address register 7. At a time T3, according to the contents of the register M(61), a stage M11 of the instruction 1 is executed, which includes memory accessing or the like, a stage A21 of the first step of the instruction 2 is executed, a microcode of the instruction 1 is shifted to a register E (62), a microcode of the first step of the instruction 2 is shifted to a register M(61), a microcode of the second step of the instruction 2 is read from the control storage 2, i.e., execution of the stage D22, and the microcode is set to the register A(60) through the selector 51. An address of a microcode of a third step of the instruction 2 is then generated in the address generator 6 and is set to the address register 7. At a time T4, a stage E11 of the instruction 1, a stage M21 of the first step of the instruction 2, and a stage A22 of the second step of the instruction 2 are executed in parallel, a microcode of the third step of the instruction 2 is read from the control storage 2, i.e., execution of stage D23, and the microcode is set to the microcode register A(60). Thereafter, the advanced control of the instruction is performed in the same way. The operation when a branch instruction is set to the instruction register 3 from the main storage device is now explained with reference to Fig. 4B. Since the advanced control operation of the branch instruction, the next instruction 1, 2, 3, and the like, is carried out by the above-mentioned process, an explanation thereof is eliminated. The present explanation concerns the execution of a branch target instruction in the branch instruction at a time T4, as shown by Dt′. Namely, at the time T4, a stage D4 of the first step of the next instruction 3 is executed and the microcode is read from the control storage 12. But , in the branch instruction, at a time T3, a stage M1 is executed and the branch target instruction is set to the instruction register 3, and at the time T4, the microcode is read from the control storage 11, i.e., a stage Dt′ is executed. But, at the time T4, a branch condition is decided, and thus the selector 50 selects the information in the control storage 11 when executing the branch process and selects the information in the control storage 12 when no executing the branch process. Therefore, interference between the first steps of the general instruction and the branch target instruction as in the prior system does not occur. Note, if the stage D4 of the instruction 3 belongs to a microcode which has completed the second step, the microcode of the step is read from the control storage 2. Then, the selector 51 selects the outputs of the control storage 2 and the reading of the microcode of the first step of the branch target instruction, i.e., stage Dt′, does not interfere with the stage D4. As described above, the first mentioned embodiment has the following features. Namely, the microcodes of the first steps of the machine instruction are stored in the duplexed first and second control storages, the microcodes of the second step and thereafter are stored in a simplexed control storage, and the microcodes of the first step of the branch target instruction are read from only the first control storage in the duplexed storage. Moreover, the microcodes of the first steps of the machine instruction are stored in the fist control storage, the microcodes of the second step and thereafter are stored in the second control storage, the first control storage is read at the second stage of the first step of the machine instruction, and the second control storage is controlled to read at the first stage of the second step and thereafter of the machine instruction. Then, at the time a decision is made about the branch condition of the branch instruction, the results of the reading of the microcodes of the first steps of the branch target instruction and the general instruction are selected, or the addresses of the microcodes of the first steps of the branch instruction and the general instruction are selected. Further, the readings from the control storages of the microcode of the first step of the branch target instruction and the microcode of the general instruction do not occur simultaneously. An embodiment of the present invention is now explained, with reference to Fig. 5, Figs. 6A, 6B, and 6C, with regard to the reading process of the microcodes. In this embodiment, the system comprises a general instruction register 4, a branch target instruction register 3, selectors 52, an address generator 6, address registers 70 and 71, control storages 11 and 2, registers A(60), M(61), and E(62). The control storage 11 is a first control storage and reads the stored information at a first step of the instruction, and the control storage 2 is a second control storage and reads the stored information at the second step and thereafter (conf. Japanese Unexamined Patent Publication (Kokai) No. 60-103452). The first control storage 11 is read at the second stage and thereafter of the first step, as shown by a bold line, and the second control storage 2 is read at the first stage of each step, as shown by a wavy line. When the general instruction 1 is set to the instruction register 4, the stage D11 of the first step of the instruction 1 is executed (conf. time T1 in Fig. 6A). In this stage, the instruction 1 is decoded, (in practice, an address of the first control storage 11 is generated). Namely, an address for reading the microcode of the first step of the instruction 1 from the control storage 11 is set to an address register 71, and an address for reading the microcode of the second step from the control storage 2 is generated by the address generator 6 and the set to the address register 70. An address generator is not provided at an input of the address register 71, since the first control storage 11 is read only at the first step of the instruction and thus the address is replaced by an operation code of the instruction. At the next time T2, the stage A (stage A11) of the first step and the stage D (stage D12) of the second step are executed. In the stage A11, a microcode (1-1) is read from the the first control storage 11, as shown by a bold line, and the microcode is set to the microcode register M (61) to control the next stage. In the above process, the address calculation, which essentially belongs to a stage A, may be controlled, for example, by using hardware instead of a microcode. In the process of the stage D12, a microcode (1-2) of the second step of the instruction 1 is read from the second control storage 2, as shown by a wavy line, and the microcode is set to the microcode register A(60). This process is a feature of the invention. Subsequently, microcodes (1-1, 1-2), respectively set on the registers A(60) and M(61) are shifted to E(62) and M(61), and the process in each stage is executed. Namely, at the next time T3, processes in stages A12 and M11 are executed in correspondence to the contents of the microcodes registers A(60) and M(61), and simultaneously, stage D13 of the third step of the instruction 1 is executed. Then, a microcode (1-3) is read from the second control storage 2, as shown by a wavy line, and is set to the microcode register A(60). At the time T4, the stage D, i.e., stage D21, of the next instruction 2 is initiated and the stages A13, M12, and E11 are executed in correspondence to the contents of the microcode registers A(60), M(61), and E(62). The following is an explanation with reference to Fig. 5, Figs. 6B, and 6C of an operation of the system when processing the branch instruction (instruction B). In this case, the operations at times T1 and T2 are the same as that of an ordinary instruction. Namely, in the branch instruction, only a microcode (B-1) of the first step is executed. At the time T1, a stage DB of the branch instruction set in the instruction register 3 is executed. Concretely, an operation code of the branch instruction is set in the address register 71 to generate an address for the first control storage 11. At the next time T2, a stage AB of the branch instruction and the stage D (stage D21) of the first step of the next instruction 2 set in the instruction register 4 are executed. In addition, in the stage AB, the microcode (B-1) is read from the first control storage 11, as shown by a bold line, and the microcode is then set to the microcode registor M(61) to control the next stage. Further, the stage D (stage D21) of the first step of the instruction 2 is executed, i.e., an operation code of the instruction 2 is set to the address register 71, and simultaneously, an address of the control storage for the second step is generated at the address generator 6 and is set to the address register 70. At the time T3, in a stage MB of the branch instruction, the branch target instruction (hereinafter referred as an instruction t) is picked up from the main storage device and is set to the instruction register 3. In stage A (stage A21) of the instruction 2, the microcode (2-1) of the first step of the instruction 2 is read from the first control storage 11, as shown by a bold line, and is set to the microcode register M(61) to control the next stage. Further, in stage D22 of the instruction 2, the microcode (2-2) of the second step is read from the second control storage 2, as shown by a wavy line, and is set to the microcode register A(60) to control the next stage. At the next time T4, a stage EB of the branch instruction is executed and the result of the branch condition decision is sent to the selector 52. At this time, the stage D31 of the instruction 3 previously set in the instruction register 4 is executed and the operation code of the instruction 3 is prepared for setting in the address register 71. If the branch is executed, the information (instruction t) in the instruction register 3 is sent to the address register 71 and the address generator 6, and if the branch is not executed, the information (instruction 3) in the instruction register 4 is sent thereto. Thus, the branch target instruction (instruction t) does not interfere with the instruction 3. The execution of the instruction t is initiated from the stage EB of the branch instruction. The above explanation concerns an operation when the instruction 3 is set in the instruction register 4 at the time T3 at which the instruction t is set in the instruction register 3. On the other hand, an operation when, for example, the address of the control storage in the third step of the instruction 2 is set at the same time T3 to the address register 70 through the address generator 6, is shown in Fig. 6C. As shown in Fig. 6C, a read (stage D23) of a microcode (2-3) of the third step of the instruction 2 from the second control storage 2 and a set of an address for the control storage 11 in a microcode (t-1) of the first step of the instruction t to the address register 71, are initiated at the same time T4. The microcode (2-3) of the third step of the instruction 2 is read at the time T4, as shown by a wavy line, and is set to the microcode register A(60). On the other hand, the microcode (t-1) of the first step of the instruction t sets the address of the control storage to the address register 71 at the stage Dt1, and simultaneously, the address of the control storage of the second step (if any) is set to the address register 70 through the address generator 6. If an address of a microcode (2-4) of the fourth step of the instruction 2 is generated, interference. occurs in the address generator 6. Nevertheless, at the time T4, since the branch condition is decided, either the second step of the branch instruction (instruction t) or the fourth step of the instruction 2 is supplied to the address generator in response to the branch condition decision, and thus interference is avoided. Therefore, if the branch is decided, at the time T5, the microcode (t-1) of the first step of the instruction t is read from the first control storage 11 and is set to the microcode register M (61), and the microcode (t-2) of the second step is read from the second control storage 2 and is set to the microcode register A(60). Subsequently, the respective microcodes (t-1, t-2) are shifted to the microcode registers M(61) and E(62), and the stages M and E are executed. As a result, the branch target instruction (instruction t) does not interfere with the general instruction (instruction 2), and the instruction t initiates the execution of the branch instruction from the stage EB thereof.

Claims: A microcode reading control system comprising : a first instruction register (4) for storing a machine instruction, a second instruction register (3) for storing a branch target instruction, a selection means (52) for selecting one output from either of the first and second instruction registers, a first control storage device (11) receiving an output of the selection means (52) as an address and supplying stored microcodes corresponding to first steps of the machine instructions, a second control storage device (2) receiving the output of the selection means (52) as an address and supplying stored microcodes corresponding to steps other than the first steps of the machine instructions, a pipeline processor having a first register (60), a second register (61), and a third register (62) connected in cascade, the first register (60) receiving an output of the second control storage device (2), the second register (61) receiving an output of the first control storage device (11) and of the first register (60), each microcode comprising a first, a second, a third, and a fourth stage, where, in the first stage of the first step of an instruction the microcode address is given by the output of the selection means, and supplied to the first control storage device (11), while the address of the following microcode is supplied by the second control storage device (2), in the second stage of the first microcode, the address is given by the output of the first control storage device (11), while the address of the following microcode is stored in the first register (60), in the third stage the microcode is given by an output of the second register, and in the fourth stage the microcode is given by an output of the third register, wherein, when a branch instruction is processed, in the second stage, an address of the machine branch target instruction is calculated, in the third stage, the machine branch target instruction is fetched to the second instruction register, in the fourth stage, the branch condition is decided and this decision causes the selector to select the output of either of the first instruction register and the second instruction register, so that, when the output of the second instruction register is selected, the first microcode of the branch target machine instruction is executed instead of the microcode stored in the second control storage device (2).

Inventors: MORI TSUYOSHI, OKADA SEISHI, MORI, TSUYOSHI, OKADA, SEISHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: G06F9
IPC codes: G06F9