HIGH-SPEED ELECTRONIC CIRCUIT HAVING A CASCODE CONFIGURATION

Abstract: Disclosed is a high-speed electronic circuit having a cascode congfiguration and provided with a bias current source (CS₀) between an emitter and a base of a load transistor (Q) in the cascode circuit configuration for compensating a base-emitter voltage (V BE ) of the transistor to eliminate an adverse effect of a charging and discharging at a stray capacitor (C) which can be connected between the base and the emitter of the transistor. An interface circuit, a level shift circuit, a level shift discrimination circuit, a signal distribution circuit, a signal synthesization circuit and a frequency band control circuit, which are applied by the high speed electronic circuit, are also disclosed.

Description: High-speed Electronic Circuit Having a Cascode Configuration Technical Field The present invention relates to an electronic circuit having a cascode configuration. More particularly, it relates to an electronic circuit able to operate at a high speed and/or having a wide frequency band. Background Art Recent technology advances in data processing systems, such as high speed data communication systems, require improved electronic circuits able to process data at a high speed and/or at a wide frequency band. In particular, for example, in an optical-fiber data communication system, a very high speed data transmission of more than 1.6 giba-bits per second (Gbs) has been attempted, to increase a transmission rate to a propagation speed limit of an optical fiber cable which has a very wide frequency range. To achieve a high speed operation, a wide frequency margin, and a high stability, a variety of consideration, such as a careful selection of circuit elements applied to such electronic circuits, a design of a best circuit arrangement, a rejection of adverse affects by, for example, a stray capacitance and a stray inductance, must be taken into account. Various types of electronic circuits have been applied to such high speed data transmission systems, as an interface circuit, a level shift circuit, a discrimination circuit, etc. However, these prior art electronic circuits still do not provide a satisfactory performance. The prior art electronic circuits will be described with reference to specific examples. JP-A-6059813 describes a latched comparator including a voltage comparator having two input transistors whose emitters are commonly connected and operatively grounded. The collectors of the transistors are connected to load resistors respectively via switching transistors. The emitters of switching transistors are connected to the collectors of the input transistors and the collectors of the switching transistors are connected to the load transistors. DISCLOSURE OF THE INVENTION An object of the present invention is to provide an improved electronic circuit having a high speed operation time, a wide frequency range and/or a great stability. Another object of the present invention is to provide an improved level shift circuit able to operate at a high speed. Still another object of the present invention is to provide an improved level shift circuit having a great stability at a high frequency range. Yet another object of the present invention is to provide an improved discrimination circuit able to discriminate a signal level with a high accuracy. Another object of the present invention is to provide an improved signal synthesization circuit having many fan-ins. The objects of the invention are solved by a level shift circuit comprising: a current drive circuit including at least one input transistor, the emitter thereof being operatively grounded and a base thereof receiving a respective input signal; a load transistor circuit including at least one load transistor, the base of each load transistor being operatively grounded, the emitter of each load transistor being connected to the collector of a respective input transistor; a bias current source connected between said emitter of said load transistor and ground, a respective current generated by said bias current source being supplied to each load transistor to maintain a forward base emitter voltage of each load transistor; and a load resistor circuit including at least one load resistor connected between the collector of a respective load transistor in said load transistor circuit and a power supply voltage, an output signal being provided at the collector of each load transistor; characterized in that said bias current source comprises a current mirror circuit for each current to be provided, at least one of said current mirror circuits being connected to a control voltage source to shift the level of said output signal by a value defined by the control voltage source. In a preferred embodiment of the invention said current drive circuit includes first and second input transistors connected in parallel to differentially operate in response to two input signals connected to bases thereof and a current source connected between emitters of said first and second input transistors and ground, said load transistor circuit includes first and second load transistors, the emitter of said first load transistor being connected to the collector of said first input transistor, the emitter of said second load transistor being connected to the collector of said second input transistor and bases of said first and second load transistors being commonly connected and operatively grounded, said load resistor circuit includes two load resistors connected to collectors of said first and second load transistors, respectively, to output two output signals from points at which said collectors and said load resistors are commonly connected, and said current-mirror circuit includes first to third current source transistors connected in parallel, collectors of said first and second current source transistors being respectively connected to said emitters of said first and second load transistors, the control voltage source being connected to a collector of said third current source transistor, the collector of said third current source transistor being connected to a base thereof which is commonly connected to the base of said second current source transistor and second to fourth current source resistors respectively connected between emitters of said first to third current source transistors and ground. In a modification to the preferred embodiment a latch circuit (FF) is connected to said load resistor circuit. Such a circuit can operate as a signal discrimination circuit. In a further preferred embodiment said current drive circuit includes first and second input transistors connected in parallel to differentially operate in response to two input signals connected to bases thereof and a current source connected between emitters of said first and second input transistors and ground, said load transistor circuit includes first and second load transistors, the emitter of said first load transistor being connected to the collector of said first input transistor, the emitter of said second load transistor being connected to the collector of said second input transistor and bases of said first and second load transistors being commonly connected and operatively grounded, said load resistor circuit includes two load resistors connected to collectors of said first and second load transistors, respectively, to output two output signals from points at which said collectors and said load resistors are commonly connected, and said bias current source includes the first and a second current mirror circuit connected to said first and second load transistors, respectively. In still a further embodiment a plurality of said current drive circuits are connected in parallel, each current drive circuit receiving a said input signal to be synthesized, said bias current source and said emitter of said at least one load transistor in said load transistor circuit are connected to the commonly connected collectors of said parallel current drive circuits. Such a circuit can be used as a signal synthesizing circuit. Brief Description of Drawings Figures 1a to 1d are circuit diagrams of prior art interface circuits; Figs. 2a and 2b are graphs representing frequency characteristics of the interface circuits shown in Figs. 1a to 1d; Fig. 3 is a principle circuit diagram of an interface circuit; Fig. 4 is a graph representing a frequency characteristic of the interface circuit shown in Fig. 3; Figs. 5a and 5b are specific circuit diagram of the interface circuit shown in Fig. 3; Figs.6a and 6b are graphs representing rising and trailing wave forms of an output signal in Fig. 3; Figs. 7a and 7b are circuit diagrams explaining the rising and trailing operation of the interface circuit shown in Fig. 3; Figs. 8a and 8b are circuit diagrams showing the principle of an interface circuit; Figs. 9a and 9b are graphs representing rising and trailing wave forms of an output signal in Figs. 8a and 8b; Figs. 10a to 10d are circuit diagrams of interface circuits; Figs. 11 and 12 are circuit diagrams of prior art level shift circuits; Fig. 13 is a graph representing the frequency characteristic of the level shift circuit shown in Fig. 11; Fig. 14 is a circuit diagram showing the principle of a level shift circuit; Figs. 15 and 18 are circuit diagrams of conventional level shift circuits; Figs.16 and 17 are circuit diagrams of embodiments of a level shift circuit in accordance with the present invention; Figs.19 to 23a and 23b are views representing a signal discrimination circuit; Fig. 24 is a circuit diagram showing the principle of a signal discrimination circuit; Figs. 25 to 27 are circuit diagrams of embodiments of the signal discrimination circuit in accordance with the present invention; Figs. 28 and 29 are circuit diagrams of prior art signal distribution circuits; Figs. 30 and 31 are circuit diagrams showing the principle of signal distribution circuits; Figs. 32 to 37 are circuit diagrams of signal distribution circuits; Figs. 38 and 39 are circuit diagrams of prior art signal synthesization circuits; Figs. 40 to 42 are circuit diagrams showing the principle of signal synthesization circuits; Fig. 43 is a circuit diagram of an embodiment of a signal synthesization circuit in accordance with the present invention. Best Mode for Carrying Out the Invention First, an interface circuit, will be described. Prior art interface circuits will be described with reference to the drawings. Figures 1a to 1d show prior art interface circuits. Figure 1a shows an open-emitter type interface circuit, Fig. 1b shows an emitter-follower type interface circuit, Fig. 1c shows an open-collector type interface circuit, and Fig. 1d shows a differential-operation and open-collector type interface circuit. In the drawings, reference CH1 denotes a transmission side integrated circuit (IC) chip, CH2 denotes a reception side IC chip, Q, Q₁ and Q₂ denote npn-type transistors, R, R₁₁ and R₁₂ denote resistors, CS denotes a constant current source, ℓ, ℓ₁ and ℓ₂ denote data transmission lines, and C, C₁ and C₂ denote stray capacitors. The IC chip CH1 is provided at a data transmission side, the IC chip CH2 is provided at a data reception side, and the data transmission line(s) ℓ or ℓ₁ and ℓ₂ is (are) provided therebetween. The stray capacitor(s) C or C₁ and C₂ may be connected to the data transmission line(s) ℓ or ℓ₁ and ℓ₂. The open-emitter type interface circuit shown in Fig. 1a is a voltage signal propagation type interface circuit. An input impedance of the transmission side IC chip CH1 is low, and an input impedance of the reception side IC chip IC2 is high. A frequency band f -3dB at which a gain is lowered by 3 dB is expressed by the following formula: f -3dB = 1 2 C S ·r E where, C S represents a capacitance of the stray capacitor(s) C or C₁ and C₂ , and r e represents an emitter resistance of the transistor(s) Q or Q₁ and Q₂. Figure 2a shows a frequency characteristic of the open-type interface circuit shown in Fig. 1a. In the drawing, curve CV1 a shows a frequency characteristic when the stray capacitance C S is 0.5 pF, and curve CV1 b shows a frequency characteristic when the stray capacitance C S is 5 pF. Since the emitter resistance r E is small, an affect due to the stray capacitor is reduced and a frequency band where a gain is lowered by 3 dB is broad, but a distortion, such as peaking occurs. The emitter-follower type interface circuit shown in Fig. 1b also suffers from the above defect. In Figs. 1c and 1d, since the load resistor(s) R₁ or R₁₁ and R₁₂ is (are) connected to the stray capacitor(s) in parallel, the frequency f -3dB is expressed as follows: f -3dB = 1 2 R L ·C S where, R L represents a resistance of the load resistor(s) R₁ or R₁₁ and R₁₂. Figure 2b shows a frequency characteristic of the interface circuits shown in Figs. 1c and 1d. In Figs. 2b, curves CV2 a , CV2 b , and CV2 c show frequency characteristics where the stray capacitance C S are 0.1 pF, 0.5 pF and 1.0 pF, respectively. The resistance R L of the load resistor(s) R₁ or R₁₁ and R₁₂ can not be made too small because an output signal(s) S OUT or S OUT1 and S OUT2 having a predetermined amplitude must be provided, an affect due to the stray capacitance C S can not be eliminated, as shown in Fig. 2b. The inventors of the present application devised a novel interface circuit which definitely eliminates the above adverse affect due to the stray capacitance ("Interface circuit", filed on June 20, 1986 at Japan P.O. and published on January 6, 1988, as JPA 63-1211). Figure 3 shows a principle interface circuit, which comprises a current drive source ID in a transmission side IC chip CH1, and, an npn-type transistor Q in which a base is grounded and an emitter is connected to the current drive source ID through a transfer line ℓ, and a load resistor R in a reception side IC chip CH2. A stray capacitor C may be connected to the transfer line ℓ. A current I d which is extracted from the current drive source ID is defined by the following formula: I d = I c + I gm where, I c is a current supplied by the stray capacitor C, and I gm is a current supplied by the transistor Q. An output voltage V OUT of an output signal S OUT is expressed as follows: V OUT = R L ·I gm where, R L is a resistance of the load resistor R. A voltage V C generated at the stray capacitor C is expressed by V C = I c jwC S = I gm g m where, C S is a capacitance of the stray capacitor C, and g m is a mutual conductance of the transistor Q. Accordingly, from the above formulas (3) to (5), the output voltage V OUT of the output signal S OUT is expressed by the following formula: V OUT = R L · 1 1 + jwC S g m I d As a result, a frequency f -3dB , a gain which is lowered by 3 dB, is expressed by the following formula: f -3dB = g m 2πC S Figure 4 shows a graph of a frequency characteristic of the interface circuit shown in Fig 3. In the drawing, curves CV3 a and CV3 b show the frequency characteristics when the stray capacitances C S are 1 pF and 5 pF, respectively. More concretely, when a DC current component of the current drive source ID is 2 mA, a resistance: 1/g m is 13 Ω and, when the stray capacitance C S is 1 pF, the frequency f -3dB is 12 Giga-Hertz (GHz). Apparently, this interface circuit shown in Fig. 3 is not substantially affected by the stray capacitance C S of approximately 1 pF on s signal transfer at approximately 10 GHz. Figures 5a and 5b show specific circuits of the interface circuit of shown in Fig. 3. The circuit shown in Fig. 5a comprises the current drive source ID consisting of an npn-type transistor Q₁ and an emitter resistor R₁ having a terminal connected to an emitter of the transistor Q₁ and another terminal connected to a low voltage supply V EE which may be ground. The circuit also comprises an npn-type transistor Q₂ having an emitter connected to a collector of the transistor Q₁ through the transfer line ℓ and a base supplied with a bias voltage supply V B , and a load resistor R₂ connected between a high voltage supply V CC and a collector of the transistor Q₂. At the IC chip CH1, an input signal S IN is supplied to a base of the transistor Q₁ , and at the IC chip CH2, an output signal S OUT is output from a point at which the load resistor R₂ and the collector of the transistor Q₂ are commonly connected. The stray capacitor C is connected to the transfer line ℓ. Note that the interface circuit shown in Fig. 5a is formed by a "cascode configuration", since the emitter of the transistor Q₁ is grounded through the resistor R₁ , the collector of the transistor Q₁ and the emitter of the transistor Q₂ are connected, and the base of the transistor Q₂ is grounded through the bias voltage supply V B . In general, a cascode amplifier having the above configuration is used for a high frequency amplification, because an input signal side and a load side are separated and an internal feedback is small, and thus a high speed operation can be established. A total gain of the cascode amplifier is equal to a gain of a load transistor, because a load at a first step is a resistor of an input transistor in the second step, i.e., an emitter resistance r E of the input transistor which is very small. In JPA 63-1211, the above high speed operation feature of the cascode configuration, and the elimination of the affection due to the stray capacitor by a Miller effect, obtained by grounding the base of the load transistor are used for an interface are used for an interface circuit operable at a high frequency. In Fig. 5b, the current drive source ID is constructed by differential operation transistor pair Q₁₁ and Q₁₂ and a constant current source CS. The load (output) circuit also includes a pair of transistors Q₂₁ and Q₂₂ , a pair of load resistors R₂₁ and R₂₂ , and the bias voltage supply V B . Emitters of the transistors Q₁₁ and Q₁₂ are grounded through the constant current source CS, and bases of the transistors Q₂₁ and Q₂₂ are grounded through the bias voltage supply V B . Accordingly, this interface circuit shown in Fig. 5b has a cascode configuration. Nevertheless, the interface circuit described in JPA 63-1211 still suffers from the affect of a large stray capacitance at a high frequency when the input signal S IN has a large amplitude, for example, 800 mV or more. Figures 6a and 6b show graphs of response characteristics of the interface circuit shown in Fig 3, obtained by simulation. Figure 6a shows rising wave forms of the output signal S OUT to a drive signal, i.e., the input signal S IN , represented by curve DW, and Fig. 6b shows trailing (falling) wave forms to the drive signal. In Fig. 6a, curves CV4 a to CV4 d show rising wave forms of the output signal S OUT when the stray capacitances are 0.1 pF, 0.5 pF, 1.0 pF and 5.0 pF, respectively. The variation of rising times is small, but a large ringing appears due to the stray capacitance. In Fig. 6b, curves CV5 a to CV5 d show trailing wave forms of the output signal S OUT when the stray capacitance are 0.0 pF, 0.1 pF, 0.5 pF and 1.0 pF, respectively. The start points of the trailing are greatly varied due to the stray capacitance, and the ringing is also large. The above defects will be discussed with reference to the circuits shown in Figs. 7a and 7b, corresponding to the interface circuit shown in Fig. 3. First, an operation when the input signal S IN having a large amplitude and changed from low level to high level is supplied to the current drive source ID will be described with reference to Fig. 7a. Upon receipt of the high level input signal S IN , the current drive source ID, more specifically the transistor in the current drive source, is turned ON. As a result, the load transistor Q is also turned ON, and supplies an on current I ON to the current drive source ID. A voltage V BE between the base and the emitter of the transistor Q is varied in response to a current flowing through the base and the emitter, i.e., the on current I ON . When the current is equal to or higher than 0.1 mA, the base·emitter voltage V BE of the load transistor Q is approximately 0.8 V. A voltage V ℓ between the transfer line ℓ and ground is V ℓ = V B - V BE , where V B denotes a base voltage of the transistor Q. When the flow of the on-current I ON occurs, the stray capacitor C is discharged until the voltage V ℓ becomes V B - V BE , and this distorts the rising wave form as shown in Fig. 6a. Second, an operation when the input signal S IN is changed from high level to low level will be described with reference to Fig. 7b. The input transistor in the current drive source ID is turned OFF, and the load transistor Q is turned OFF. As a result, an off current I OFF supplied from the load transistor Q to the current drive source ID becomes approximately 0 mA, and the voltage V BE becomes 0 V. Consequently, the voltage V ℓ on the transfer line ℓ becomes V B . The stray capacitor C is charged until the voltage (V B - V BE ) becomes V B . This distorts the trailing wave form as shown in Fig. 6b. Namely, the voltage V ℓ on the transfer line ℓ is varied by the voltage V BE ≒ 0.8 V, and the stray capacitor C is discharged or charged in response to the change of the transfer line voltage V ℓ . A delay time t d of the trailing edge and the rising edge can be expressed by the following formula: t d = C S V BE I d where, I d represents a current passing through the current drive source ID. Now, a principle of an interface circuit will be described with reference to Figs. 8a and 8b. The interface circuits shown in Figs. 8a and 8b eliminate the change of the transfer line voltage V ℓ , and thus eliminate the charging and discharging of the stray capacitor C, to shorten the rising time and the trailing time. In Fig. 8a, the interface circuit includes a current drive source ID in a transmission side IC chip CH1. The interface circuit also includes, at a reception side IC chip CH2, a load (output) transistor Q and a load resistor R. Between the chips CH1 and CH2, a transfer line ℓ is provided, and a stray capacitor C can be connected to the transfer line ℓ. The current drive circuit ID includes an input transistor (not shown), an emitter thereof being grounded. A base of the load transistor Q is connected to a collector of the input transistor, and a base thereof is grounded. The above circuit construction is substantially the same as that of the interface circuit shown in Fig. 3, and thus the interface circuit shown in Fig. 8a has a cascode configuration. In addition to the above circuit configuration, the interface circuit shown in Fig. 8a includes a bias current source CS₀ connected between the emitter and the base of the load transistor Q in the reception side IC chip CH2. The bias current source CS₀ provides a constant current I CS corresponding to a current I BE flowing through the base and the emitter of the load transistor, i.e., the above on-current I ON , Q when the transistor Q is turned ON, for cancelling the current I BE . Namely, the constant current I CS has an amplitude sufficient to prevent the change of the voltage V ℓ on the transfer line ℓ, i.e., to prevent the change of the base-emitter voltage V BE of the load transistor and has a polarity which is the reserve of a polarity of the on current I ON . In other words, the constant current I CS generates a voltage between the base and the emitter of the transistor Q opposite to the base-emitter voltage V BE of the load transistor Q when the load transistor Q is turned ON. In general, the constant current I CS may be 0.5 mA or higher. Taking a margin into consideration, the constant current I CS may be 0.5 mA. The bias current source CS₀ always provides the constant current I CS to the load transistor Q to suppress the change of the base-emitter voltage V BE , so that the voltage V ℓ on the transfer line ℓ is not changed regardless of the change of the status of the load transistor Q, i.e., the change between the ON state and the OFF state, of the load transistor Q. Accordingly, the charging and discharging of the stray capacitor C are avoided, and generation of the distortion of the rising signal and the trailing signal is prevented. As shown in Fig. 8b, the bias current source CS₀ can be provided at the transmission side IC chip CH1. Since the bias current source CS₀ is connected between the base and the emitter of the load transistor Q, the operation is same to that described above. In Figs. 8a and 8b, by providing the bias current source CS₀ , a DC level of the output signal S OUT can be made low than that of the interface circuit shown in Fig. 3, and thus the resistance R L of the load resistor R should be greater than that of the load resistor shown in Fig. 3. In addition, a current flowing through the load transistor Q may be increased, and a capacity of the load transistor Q may become larger than that of the transistor shown in Fig. 3. However, note that an amplitude of the output signal S OUT , per se, is not changed, regardless of the provision of the bias current source CS₀. Figures 9a and 9b show the characteristic curves of the interface circuits shown in Figs. 8a and 8b obtained by simulation. Figure 9a shows a rising characteristic. In Fig. 9a, curves CV6 a to CV6 d represent the rising characteristics corresponding to the change of the drive signal, i.e., the input signal S IN , represented by curve DW, when the stray capacitances C S are 0.1 pF, 0.5 pF, 1.0 pF, and 5.0 pF. These curves CV6 a to CV6 d correspond to the curves CV4 a to CV4 d in Fig. 6a. Compared with these, as shown in Fig. 6a, the characteristics shown by the curves CV4 a to CV4 c when the stray capacitances are 0.1 pF, 0.5 pF, and 1.0 pF are greatly varied therebetween, but on the other hand, as shown in Fig. 9a, the characteristics shown by the curves CV6 a to CV6 c are not varied each other. This means that the transfer line ℓ in the interface circuit shown in Fig. 8a can install at a short distance or a long distance without any circuit adjustment. The characteristics shown by the curves CV7 a to CV7 c mean the same thing. Figures 10a to 10d show circuit diagrams of an interface circuit. The interface circuits shown in Figs. 10a and 10b are the open-collector type interface circuits corresponding to the interface circuit shown in Fig. 5a. In Fig. 10a, the bias current source CS₀ is formed by a current-mirror type current source composed of npn-type transistor Q₃ and Q₄ , resistors R₃ and R₄, and a resistor R₅. The current-mirror type current source, per se, is well known. In Fig. 10b, the bias current source CS₀ is formed by a resistor R₆. The interface circuits shown in Figs. 10c and 10d are differential-operation and open-collector type interface circuits corresponding to the interface circuit shown in Fig. 5b. In Fig. 10c, the bias current source CS₀ is formed by a current-mirror type constant current source composed of npn-type transistor Q₃₁ , Q₃₂ and Q₄ , and resistors R₃₁ , R₃₂ , R₄ and R₅. In Fig. 10d, the bias current source CS₀ is formed by two resistors R₆₁ and R₆₂. The interface circuits shown in Figs. 10a to 10d can be provided with the bias current source CS₀ at the transmission side IC chip CH1. When the input signal S IN is a high frequency repetition signal, such as a clock signal, in the base-grounded interface circuit shown in Fig. 3, a wave form distortion may not occur, since a charge accumulated in the stray capacitor is not fully discharged, and the base emitter voltage V BE is not substantially changed. But, when the input signal S IN is a data signal which may be formed by continuous one's data or continuous zero's data, a wave form distortion can occur at a transient state where an end of the continuous one's data is followed by a first of the continuous zero's data, or vice versa. In particular, such interface circuits are very useful when forming interfaces, such as an interface between circuits in a gate array integrated circuit chip wherein a wiring pattern capacitance is considerably large, and an interface between chips wherein a bonding pad capacitance can not be neglected. According to the above interface circuits since the frequency characteristic and the wave response characteristic are not affected by the stray capacitor, a high speed data transmission can be achieved. Second, a level shift circuit will be described. In the case of a data processing at a high speed, a level shift of a DC bias level of a signal by a predetermined voltage is required. For example, in an amplification circuit, a DC level of an input signal can be shifted to a level equal to a reference voltage by using the level shift circuit. Figure 11 shows a prior art differential-operation type level shift circuit. In the drawing, the level shift circuit includes a pair of differential-operation transistors Q₁ and Q₂ , a first current source CS₁ consisting of a transistor Q₃ and a resistor R₃ , a second current source CS₂ consisting of a transistor Q₄ and a resistor R₄ , a third current source CS₃ consisting of a transistor Q₅ and a resistor R₅ , output emitter follower transistors Q₆ and Q₇ , and resistors R₁ , R₂ , R₆ and R₇. Upon receipt of input signals S IN1 and S IN2 at bases of the transistors Q₁ and Q₂ , a pair of differential-operated output voltages V₁ and V₂ are respectively extracted from points at which collectors of the transistors Q₁ and Q₂ and the load resistors R₁ and R₂ are commonly connected, and supplied to bases of the transistors Q₆ and Q₇. Output signals S OUT1 and S OUT2 having voltages V₃ and V₄ , respectively, are output from points collectors of the transistors Q₄ and Q₅ and the resistors R₆ and R₇ are commonly connected. The voltages V₁ and V₃ , and the voltage V₂ and V₄ have the following relationships: V₁ = V BE + I₁R₆ + V₃ V₂ = V BE + I₂R₇ + V₄ where, V BE is a base-emitter voltage of the transistors Q₄ and Q₅ , R₆ and R₇ are resistances of the resistors R₆ and R₇ , I₁ is a current passing through the transistor Q₄ , and I₂ is a current passing through the transistor Q₅. Namely, the output voltages V₃ and V₄ are shifted from the voltage V₁ and V₂ by (V BE + I₁R₆) and (V BE + I₂R₇). In this level shift circuit, the levels to be shifted can be easily changed continuously by changing the currents I₁ and I₂ of the current sources CS₂ and CS₃. Figure 12 shows a prior art diode-type level shift circuit. In the drawing, n-series connected transistors, for example, Q₁₁ , each connected between a collector and a base and functioning as a diode, are connected between transistors Q₆ and Q₄. Similarly, n-series connected transistors, for example, Q₂₁ , each connected between a collector and a base and functioning as a diode, are connected between transistors Q₇ and Q₅. In the drawing, the following relationships stand: V₁ = (n+1)V BE + V₃ V₂ = (n+1)V BE + V₄ where, V BE is a base-emitter voltage of the diode-functioning transistor. Namely, by changing the number of the diode-changing transistors, a level shift voltage (n+1)V BE can be stepwisely changed. Figure 13 shows a graph of frequency characteristics of the level shift circuits shown in Figs. 11 and 12. In the level shift circuit shown in Fig. 11, due to the resistors R₆ and R₇ at the emitter follower circuits and stray capacitors which can be connected to the emitter follower circuits, as shown in Fig. 13, the frequency characteristic is reduced, and accordingly, a wave response characteristic is reduced. As a result, the level shift circuit in Fig. 11 can not be applied to a high speed circuit. The level shift circuit shown in Fig. 12 has the same problem as that described above. In general, in order to realize a high speed operation level shift circuit without a distortion of a wave form, several design techniques can be utilized, for example, reducing the resistances of the series-connected resistors R₆ and R₇ , reducing capacitances of the stray capacitors, and arranging a circuit construction in which the stray capacitors are replaced by other portions directly affecting the characteristic. Nevertheless, these countermeasures are limited in practice. Conversely, a circuit providing a bias current source CS₀ in addition to the cascode configuration as shown in Figs. 8a and 8b prevents a distortion of a wave form of a output signal and the reduction of a variety of characteristics, due to the stray capacitance. In this invention, the above feature is included to form a high speed level shift circuit without the reduction of the frequency characteristic and the wave response characteristic. Figure 14 shows a principle circuit diagram of a level shift circuit. The level shift circuit includes a pair of differential-operation transistors Q₁₁ and Q₁₂ , and a constant current source CS₁ connected between collectors of the transistors Q₁₁ and Q₁₂ and a low voltage line V EE which may be ground. The level shift circuit also includes load resistors R₂₁ and R₂₂ , load transistors Q₂₁ and Q₂₂ , a bias voltage supply V B , and level shift current sources CS₂ and CS₃. The emitters of the transistors Q₁₁ and Q₁₂ are grounded through the constant current source CS₁ , collectors of the transistors Q₁₁ and Q₁₂ are connected to emitters of the transistors Q₂₁ and Q₂₂ , and bases of the transistors Q₂₁ and Q₂₂ are grounded through the bias voltage supply V B . Accordingly, the above circuit has a cascode configuration. In addition, the variable current sources CS₂ and CS₂ corresponding to the bias current source CS₀ shown in Fig. 8a are connected between the emitters of the transistors Q₂₁ and Q₂₂ and the low voltage line V EE , which is ground. A differential-operation pair circuit, corresponding to the current drive circuit ID in Fig. 8a, consisting of the transistors Q₁₁ and Q₁₂ and the constant current sources CS₁ receives voltage input signals S IN1 and S IN2 , and changes to currents I₃ and I₄ flowing therethrough. The currents I₃ and I₄ are varied in response to the voltages of the input signals S IN1 and S IN2 . The constant current source CS₁ supplies a current of a sum of I₃ and I₄. The above currents I₃ and I₄ are made flow through the load resistors R₂₁ and R₂₁ , resulting in voltage drops V₂₁ = I₃·R₂₁ and V₂₂ = I₄·R₂₂ which are output signals S OUT1 and S OUT2 . In addition, currents I₁ and I₂ supplied by the level shift current sources CS₂ and CS₃ are made flow through the load resistors R₂₁ and R₂₂ , resulting in further voltage drops V L1 = I₁·R₂₁ and V₂₂ = I₂·R₂₂. These voltage drops V L1 and V L2 are level-shifted values. Since the currents I₁ and I₂ can be changed by adjusting the current sources CS₂ and CS₃ , the level shift voltages V L1 and V L2 can be continuously changed. The basic condition of the interface circuits shown in Figs. 8a and 8b and Figs. 10a to 10d can be applied to the level shift circuit shown in Fig. 14, except for the variable level shift current sources CS₂ and CS₃. Therefore, the features of the interface circuit are maintained in the level shift circuit. A basic difference between the interface circuit and the level shift circuit is the provision of the constant bias current source CS₀ and the variable level shift current sources CS₂ and CS₃. However, if the level shift circuit can be used for shifting at a constant level, the current sources CS₂ and CS₃ can be formed as constant current sources. Figure 15 shows a further circuit diagram of a level shift circuit; In Fig. 15, the constant current source CS₁ is composed of an npn-transistor Q₃ and a resistor R₃ , and supplies a current corresponding to (I₃ + I₄). The current sources CS₂ and CS₃ are formed by a current-mirror type current source circuit consisting of npn-type transistors Q₄ , Q₅ , and Q₁₀ , and resistors R₄ , R₅ , R₁₀ , and R₁₁. The transistors Q₄ and Q₅ and the transistors R₄ and R₅ are defined to supply the current I₁ and I₂. In this circuit, the current sources CS₂ and CS₃ are constant current sources, and the level shift is fixed. In Fig. 16 a first embodiment of a level shift circuit in accordance with the present invention is shown, in which the current source CS₁ consists of a transistor Q₃ and a resistor R₃ , the current source CS₂ consists of a resistor R₁₀ , a transistor Q₁₀ , a resistor R₁₁ , a transistor Q₄ , and a resistor R₄ , and the current source CS₃ consists of a transistors Q₅ and Q₁₄ , and resistors R₅ and R₁₂. The current source CS₂ and the current source CS₃ are current-mirror type current sources. By changing a control voltage V C supplied to the current source CS₃ , a level of an output signal S OUT2 can be continuously changed. But, since the current source CS₂ is a constant current source, a level-shift of an output signal S OUT1 is fixed. The level shift circuit in accordance with the second embodiment of the present invention is shown in Fig. 17 and is a modification of the level shift circuit shown in Fig. 16. In the drawing the constant current source CS₁ is formed by a current-mirror type current source consisting of a resistor R₁₀ , transistors Q₁₀ and Q₃ , and resistors R₁₁ and R₃. The current sources CS₂ and CS₃ are formed by a variable current-mirror type current source consisting of transistors Q₄ , Q₅ , and Q₁₄ , and resistors R₄ , R₅ and R₁₂. By changing a control voltage V C supplied to the current sources CS₂ and CS₃ , the levels of both of the output signals S OUT1 and S OUT2 can be continuously shifted. In Fig. 18, which shows a conventional device the constant current source CS₁ is formed by a current-mirror type current source consisting of transistors Q₃ and Q₁₀, and resistors R₁₀, R₃, and R₁₁. The current sources CS₂ and CS₃ are variable resistors R₄ and R₅. The levels of both of the output signals S OUT1 and S OUT2 can be freely shifted by adjusting the resistances of the resistors R₄ and R₅. Third, a signal discrimination circuit will be described. The signal discrimination circuit can be applied, for example, to a repeater in an optical data transmission system. In the repeater, as shown in Fig. 19, an optical to electrical (OE) converted signal is equalized and amplified at an equalizing amplifier 10, and a clock signal is extracted at a timing circuit 14. The equalized signal is discriminated by a timing signal from the timing circuit 14 at a signal discriminal circuit 12, and the discriminated signal is reproduced at a reproduction circuit 16. As shown in Fig. 20, a discriminating level can be varied by adjusting a variable resistor R VR . The equalizing amplifier 10 outputs an equalized signal S10A and a discriminating threshold voltage signal S10B. As shown in Fig. 21, the equalized signal S10A, having a distorted eye-pattern by an optical shock and a shifted timing, is discriminated by a threshold level L at the discrimination circuit 12, and a high level signal is output when the equalized signal is higher than the threshold level L at a clock timing, and alternatively, a low level signal is output. In order to adjust the threshold level to a maximum level in response to variations, such as a drift of the circuit, or noise, the threshold level L is adjusted by the variable resistor R VR , and the discrimination circuit 12 discriminates the equalized signal S10A by using the adjusted threshold level signal S10B. In the optical transmission system, a very high speed signal processing is required. Such a high speed signal processing requires an improvement of a wave form response and a prevention of cross-talk. The improvement and the prevention, in general, require to reduce a gain at the equalizing amplifier, and to reduce an amplitude of the equalized signal. This amplitude reduction lowers the discrimination sensitivity. In general, when an amplitude is small, and thus the discrimination sensitivity is low, the differential-operation type discrimination is preferable, but is difficult to adjust the discrimination level. Namely, since a normal polarity signal shown in Fig. 22a and an inverted polarity signal shown in Fig. 22b are used in the differential-operation discrimination, the discrimination threshold level L is determined at a center level. In the optical transmission system, a center of the eye-pattern tends to be shifted to a low level, and a free level shifting is required in the discrimination used by the differential-operation type circuit. In addition, the differential-operation type circuit has an advantage in that a deadband of the discrimination defined by a low limit LL and a upper limit UL shown in Fig. 21 is reduced by a half. A signal discrimination circuit can be formed by a differential-operation type circuit, and operates at a high speed, has a high discrimination sensitivity, and can adjust the discrimination threshold level. Figure 24 shows a principle of a signal discrimination circuit. A basic circuit configuration of the signal discrimination circuit shown in Fig. 24 is similar to the level shift circuit shown in Fig. 14, except that a flip-flop FF is provided. Accordingly, a description of the basic circuit configuration and operation thereof is omitted. Currents I₄ and I₅, which are made to flow through load resistors R₂₁ and R₂₂ , load transistors Q₂₁ and Q₂₂ , a pair of differential-operation transistors Q₁₁ and Q₁₂ and a current source CS₁ , respectively, are varied in response to input signals S IN1 and S IN2 . These currents I₄ and I₅ generate voltage drops defined by (R₂₁ I₄) and (R₂₂ I₅) at the load resistors R₂₁ and R₂₂. In addition, currents I₂ and I₃ , which respectively flow through the load resistors R₂₁ and R₂₂ , the load transistors Q₂₁ and Q₂₂ , and current sources CS₂ and CS₃ , are defined by only the current sources CS₂ and CS₃ and generate voltage drops defined by (R₂₁ I₂) and (R₂₂ I₃). These voltage drops (R₂₁ I₂) and (R₂₂ I₃) indicate shift levels. Referring to Figs. 23a and 23b, a level SL L or a level SL U is shifted by (R₂₁ I₂ - R₂₂ I₃)/2 from the discrimination threshold level L. The level shifted output signals S OUT1 and S OUT2 are output to the flip-flop FF. The current sources CS₂ and/or CS₃ are formed to supply variable currents I₂ and I₃ in response to a level shift value. In the signal discrimination circuit shown in Fig. 24, all of the features of the level shift circuit shown in Fig. 14 are maintained. Figure 25 shows a specific circuit diagram of an embodiment of the signal discrimination circuit in accordance with the present invention. In Fig. 25, emitter-follower transistors Q₅ and Q₆ are provided to output signals S₃ and S₄ therethrough. The constant current source CS₁ is formed by a current-mirror type current source circuit consisting of transistors Q₁₅ and Q₇ and resistors R₈ , R₉ and R₃. The current source CS₂ is formed by a current-mirror type current source circuit consisting of a transistor Q₈ , a resistor R₄ , the common resistors R₈ and R₉ , and the common transistor Q₁₅. The current source CS₃ is formed by a current-mirror type current source circuit consisting of transistors Q₉ and Q₁₃ and resistors R₅ and R₁₀. A current source CS₄ for the emitter-follower transistors Q₅ and Q₆ is formed by a current-mirror type current source circuit consisting of transistors Q₁₀ and Q₁₄ , resistors R₆ and R₇ , the common resistor R₈ , the common transistor Q₁₅ and the common resistor R₉. In the drawing, the current source CS₃ can change the current I₃ by adjusting a control voltage V C , and can shift the level of the signal S₄. The current source CS₃ supplies a constant current I₂ , and accordingly, the shift level of the signal S₃ is constant. Figures 23a and 23b show the level shift by the circuit shown in Fig. 25, and the signal discrimination therefor. Figure 26 shows a block diagram of an embodiment of the flip-flop FF shown in Fig. 24. The flip-flop FF includes a master latch circuit ML driven, by a clock CLK and a slave latch circuit SL driven by an inverted clock CLK. Figure 27 shows a specific circuit diagram of the flip-flop FF shown in Fig. 26. In the drawing, reference V S denotes a reference voltage supply, CS₄ to CS₆ denote current sources. The operation will be briefly described. When the signal S₃ is higher than the signal S₄ , and when the clock CLK is at a high level higher than a voltage from the reference voltage supply V S , a transistor Q₄₀ is turned ON, a transistor Q₄₁ is turned OFF, a transistor Q₄₆ is turned OFF and a transistor Q₄₇ is turned ON, thus outputting a signal S₅ having a low level and a signal S₆ having a high level. Also, a transistor Q₄₃ is turned ON, a transistor Q₄₄ is turned OFF, and a transistor Q₄₅ is turned OFF. When the clock CLK becomes low level, the transistor Q₄₂ is turned OFF, the transistor Q₄₅ is turned ON, the transistor Q₄₃ is turned ON, and the transistor Q₄₄ is turned OFF, and thus the signal S₅ is maintained at a high level and the signal S₆ at a low level. That is, a latch function is achieved. The above latched statuses are updated in response to the levels of the input signals S₃ and S₄ when the clock CLK becomes high level. Accordingly, the flip-flop FF shown in Fig. 27 functions as a discrimination circuit which reads data in response to the levels of the input signals S₃ and S₄ at a change time of the clock CLK, with a narrow pulse width of the clock CLK. Referring to Fig. 25, since the level shift of the signal S₃ is constant and the level of the signal S₄ is shifted, the discrimination threshold level L is shifted by a half (1/2) of the level shift of the signal S₄. Also, the dead band of the discrimination shown in Fig. 21 is narrowed by a half. Referring to Figs. 19, 20 and 25, the signals S10A and S10B correspond to the input signals S IN1 and S IN2 , and the circuit shown in Fig. 25 including the flip-flop FF corresponds to the signal discrimination circuit 12. The clock CLK in Fig. 27 is supplied from the timing circuit 14 shown in Fig. 19. As described above, the signal discrimination circuit of the present invention is formed by a combination of the level shift circuit, which is differential-operated and can shift the levels of the differential-input signals S IN1 and S IN2 , and a latch circuit, such as the flip-flop FF, latching the level-shifted output signals S OUT1 and S OUT2 . The signal discrimination circuit of the present invention can adjust the discrimination threshold level L and has a narrow dead band. The narrow dead band brings a reduction of an amplitude of the equalized signal, resulting in a prevention of cross-talk. In addition, since all of the features of the level shift circuit shown in Fig. 14 are maintained, the signal discrimination circuit of the present invention can operate at a high speed will improving the frequency characteristic and the wave form response characteristic. In particular, the signal discrimination circuit is preferably used for discriminating the OE converted signal because the free level shift is effective for discriminating a center eye-pattern lowered due to an optical shock. Fourth, a signal distribution circuit will be described. Figure 28 shows a prior art signal distribution circuit. In the drawing, a signal sending circuit 10 is a differential-operation pair type circuit consisting of resistors R₅₁ and R₅₂ , transistors Q₅₁ and Q₅₂ and a constant current source CS₅₁. Two parallel-connected emitter-follower circuits, which consist of a transistor Q₁₀₁ and a constant current source CS₁₀₁ , and a transistor Q₁₀₂ and a constant current source CS₁₀₂ , respectively, are connected to a collector of the transistor Q₅₂. Two circuits 20A and 20B, which receive distributed signals follow the emitter-follower circuits. When receipt of two input signals S IN1 and S IN2 , one of which may be a reference signal, a difference between the two input signals S IN1 and S IN2 is amplified and output as an output signal S₃. The output signal S₃ is supplied to bases of the transistors Q₁₀₁ and Q₁₀₂ , and output signals, each of which is lowered by a base-emitter voltage V BE of each of the transistors Q₁₀₁ and Q₁₀₂ , are supplied to the circuits 20A and 20B. In Fig. 28, since the base-emitter capacitors (not shown) are connected to the resistor R₅₂ in parallel, a frequency characteristic of the signal distribution circuit is distorted. In addition, the input impedance of the circuits 20A and 20B adversely affects a voltage drop at the resistor R₅₂. As a result, the signal distribution circuit does not have sufficient fan-outs. Figure 29 also shows a prior art signal distribution circuit. In the drawing, a single emitter-follower circuit consisting of the transistor Q₁₀₁ and the constant current source CS₁₀₁ is provided to supply two distributed signals to the circuits 20A and 20B. Since the input impedance of the circuits 20A and 20B are connected to an output terminal of the emitter-follower transistor Q₁₀₁ , the frequency characteristic often may be fluctuated. In addition, the mutual status change of the circuits 20A and 20B adversely affects the signal distribution circuit. Also, this signal distribution circuit does not provide sufficient fan-outs. Figures 30 and 31 are circuit diagrams showing the principle of a signal distribution circuit. The signal distribution circuit shown in Fig. 30 includes a current drive source ID having at least one transistor, an emitter of which is operatively grounded and a base of which receives an input signal S IN , and series-connected base-grounded transistor circuits, for example, a base-grounded transistor circuit composed of a base-grounded transistor Q₂₁ and a resistor R₂₁. An emitter of each base-grounded transistor circuit is operatively connected to a collector of the transistor in the current drive source ID. Accordingly, the above circuit configuration is formed as a cascode configuration. In addition, a bias current source BC is connected between each emitter of the base-grounded transistor, for example, Q₂₇ and ground. In addition, as an option, a plurality of emitter-follower circuits, each, for example, an emitter-follower circuit composed of an emitter-follower transistor Q₁₀₁ and a current source CS₁₀₁ , can be connected to collectors of the base-grounded transistors. The circuits 20A to 20G are also connected to the emitter-follower circuits. The signal distribution circuit shown in Fig. 30 changes the voltage input signal S IN to a current signal I passing through the series-connected base-grounded transistor circuits. Each voltage drop generated at each load resistor, for example, R₂₁ , is supplied to the base of a corresponding emitter-follower transistor, for example, Q₁₀₁ , to distribute the input signal S IN . In the drawing, since the emitter-follower circuits and the circuits 20A to 20G do not distribute the signals, the frequency characteristic is not distorted and the adverse affect due to the circuits 20A to 20G is avoided. In addition, the load resistors are separated by the base-grounded transistors, and thus the frequency characteristic is not adversely affected by the stray capacitors. Furthermore, by providing the bias current source BC, the adverse affect due the stray capacitance superimposed on the voltage of the transfer lines ℓ is fully eliminated. As a result, the signal distribution circuit shown in Fig. 30 operates at a high speed without a distortion of the frequency characteristic and the wave form response characteristic, and can provide many fan-outs regardless of the superimposition of the stray capacitance. The signal distribution circuit shown in Fig. 31 includes the current drive source ID, parallel-connected base-grounded transistor circuits, and the bias current source BC. Optionally, a plurality of emitter-follower circuits and the circuits 20A to 20C are provided. The operation of the signal distribution circuit is similar to that of the signal distribution circuit shown in Fig. 30. The features of the signal distribution circuit shown in Fig. 31 are also similar to those of the signal distribution circuit shown in Fig. 30. Comparing the signal distribution circuits shown in Figs. 30 and 31, in the signal distribution circuit shown in Fig. 30, a high voltage V CC is higher than that of the signal distribution circuit shown in Fig. 31, and the amplitudes of the distributed signals are the same. Conversely, in the signal distribution circuit shown in Fig. 31, each amplitude of the distributed signals is 1/n, where n represents the number of base-grounded transistor circuits. Figures 32 to 37 show circuit diagrams of the signal distribution circuits shown in Figs. 30 and 31. The signal distribution circuits shown in Figs. 32 and 33 correspond to the signal distribution circuit shown in Fig. 30. The bases of base-grounded transistors Q₂₁ , Q₂₂ , Q 21a , Q 21b , Q 22a and Q 22b are grounded through bias voltage supply circuits V B1 and V B2 . Emitters of transistors Q₃₁ , Q₁₁ , and Q₁₂ are grounded through a resistor R₅₁ functioning as the current source and a current source CS₁₁. In Fig. 32, the bias current source BC is formed by a resistor R₄₁. Since the signal distribution circuit shown in Fig. 33 is differentially operated, two bias current sources BC a and BC b are provided. The signal distribution circuits shown in Figs. 36 to 37 correspond to the signal distribution circuit shown in Fig. 31. In Figs. 34 and 35, the bias current source BC is formed by a current-mirror type current source circuit. The signal distribution circuit shown in Fig. 37 is differentially operated. A signal synthesization circuit will be described. Figures 38 and 39 show prior art signal synthesization circuits. The operation of these signal synthesization circuits is well known, and thus a description thereof is omitted. In the signal synthesization circuit shown in Fig. 38, emitter-follower outputs of transistors Q₃₀ and Q₄₀ are connected to a circuit 40. The signal synthesization circuit shown in Fig. 38 suffers from the same defects as those of the signal distribution shown in Fig. 29. Also, the signal synthesization circuit shown in Fig. 39 suffers from defects similar to those of the signal distribution circuit shown in Fig. 28, since base-collector capacitors of transistors Q₃₀ and Q₄₀ are connected to a load resistor R in parallel. Figure 40 shows a circuit diagram showing the principle of a signal synthesization circuit. The signal synthesization circuit includes a plurality current drive sources ID₁ to ID n provided in correspondance to the number of input signals S IN1 to S INn to be synthesized, a base-grounded transistor Q, a load resistor R, and a bias current source BC. Each current drive source ID includes a transistor, an emitter thereof being operatively grounded, and a base thereof receiving the input signal S IN . As is apparent, the signal synthesization circuit is basically formed by a combination of the cascode configuration circuit and the current source BC. In the Fig. 40, the current drive circuits ID₁ to ID n change the voltage input signals S IN1 to S INn to current signals I₁ to I n , and the current signals I₁ to I n are synthesized at a common connected point as I₀ = I₁ + I₂ + ... + I n . The synthesized current signal I₀ is changed to a voltage V₀ at the load resistor R. This voltage V₀ is supplied to a circuit 40. Since the base-grounded transistor Q separates a connection between the current drive sources ID₁ to ID n and the load resistor R, the adverse affect due to a stray capacitance on the current drive sources ID₁ to ID n is prevented. In addition, since output impedances of the current drive sources ID₁ to ID n are high, a mutual interface between the current drive sources ID₁ to ID n is substantially avoided. Furthermore, the provision of the bias current source BC eliminates the adverse affect due to the stray capacitor connected to the transfer line ℓ. As a result, the signal synthesization circuit shown in Fig. 40 provide many fan-ins, and operates at a high speed without a distortion of the frequency characteristic. Figures 41 and 42 show further signal synthesization circuits. Figure 43 shows circuit diagram of an embodiment of the signal synthesization circuit in accordance with present invention. The configuration and the operation of these signal synthesization circuits are apparent from the above description. In particular, a signal synthesization circuit of the present invention overcomes the above defects of the load resistor commonly used type signal synthesization circuit shown in Fig. 39.

Claims: A level shift circuit comprising: a current drive circuit (ID) including at least one input transistor (Q₁₁,Q₁₂;Q₃₀,Q₄₀), the emitter thereof being operatively grounded and a base thereof receiving a respective input signal (S IN1 ;S IN2 ); a load transistor circuit including at least one load transistor (Q; Q₂₁; Q₂₂), the base of each load transistor being operatively grounded, the emitter of each load transistor being connected to the collector of a respective input transistor (Q₁₁,Q₁₂;Q₃₀,Q₄₀); a bias current source connected between said emitter of said load transistor and ground, a respective current generated by said bias current source being supplied to each load transistor to maintain a forward base emitter voltage (VBE) of each load transistor; and a load resistor circuit including at least one load resistor (R; R₂₁, R₂₂) connected between the collector of a respective load transistor (Q;Q₂₁,Q₂₂) in said load transistor circuit and a power supply voltage (V CC ), an output signal (S OUT1 , S OUT2 ) being provided at the collector of each load transistor; characterized in that said bias current source comprises a current mirror circuit (CS₂, CS₃) for each current to be provided, at least one of said current mirror circuits being connected to a control voltage source (V c ) to shift the level of said output signal by a value defined by the control voltage source (V c ). A level shift circuit according to claim 1, characterized in that said current drive circuit (ID) includes first and second input transistors (Q₁₁ and Q₁₂) connected in parallel to differentially operate in response to two input signals (S IN1 and S IN2 ) connected to bases thereof and a current source (CS₁) connected between emitters of said first and second input transistors (Q₁₁,Q₁₂) and ground, said load transistor circuit includes first and second load transistors (Q₂₁ and Q₂₂), the emitter of said first load transistor being connected to the collector of said first input transistor, the emitter of said second load transistor being connected to the collector of said second input transistor and bases of said first and second load transistors being commonly connected and operatively grounded, said load resistor circuit includes two load resistors (R₂₁ and R₂₂) connected to collectors of said first and second load transistors, respectively, to output two output signals (S OUT1 and S OUT2 ) from points at which said collectors and said load resistors are commonly connected, and said current-mirror circuit includes first to third current source transistors (Q₄, Q₅ and Q₁₄;Q₈, Q₉ and Q₁₃) connected in parallel, collectors of said first and second current source transistors (Q₄,Q₅;Q₈,Q₉) being respectively connected to said emitters of said first and second load transistors, the control voltage source (V C ) being connected to a collector of said third current source transistor (Q₁₄), the collector of said third current source transistor (Q₁₄;Q₁₃) being connected to a base thereof which is commonly connected to the base of said second current source transistor (Q₅;Q₉) and second to fourth current source resistors (R₄, R₅ and R₁₂;R₄,R₅ and R₁₀) respectively connected between emitters of said first to third current source transistors and ground. A level shift circuit according to claim 1, characterized in that said current drive circuit (ID) includes first and second input transistors (Q₁₁ and Q₁₂) connected in parallel to differentially operate in response to two input signals (S IN1 and S IN2 ) connected to bases thereof and a current source (CS₁) connected between emitters of said first and second input transistors and ground, said load transistor circuit includes first and second load transistors (Q₂₁ and Q₂₂), the emitter of said first load transistor being connected to the collector of said first input transistor, the emitter of said second load transistor being connected to the collector of said second input transistor and bases of said first and second load transistors being commonly connected and operatively grounded, said load resistor includes two load resistors (R₂₁ and R₂₂) connected to collectors of said first and second load transistors, respectively, to output two output signals (S OUT1 and S OUT2 ) from points at which said collectors and said load resistors are commonly connected, and said current-mirror circuit includes first to third current source transistors (Q₄, Q₅ and Q₁₄), connected in parallel, collectors of said first and second current source transistors (Q₄,Q₅) being respectively connected to said emitters of said first and second load transistors, the control voltage source (V C ) being connected to a collector of said third current source transistor (Q₁₄), the collector of said third current source transistor being connected to a base thereof which is commonly connected to bases of said first and second current source transistors and second to fourth current source resistors (R₄, R₅ and R₁₂) are respectively connected between emitters of said first to third current source transistors and ground. A level shift circuit according to claim 2, characterized in that a latch circuit (FF) is connected with its inputs to said load resistor circuit. A level shift circuit according to claim 1, characterized in that said current drive circuit (ID) includes first and second input transistors (Q₁₁ and Q₁₂) connected in parallel to differentially operate in response to two input signals (S IN1 and S IN2 ) connected to bases thereof and a current source (CS₁) connected between emitters of said first and second input transistors (Q₁₁,Q₁₂) and ground, said load transistor circuit includes first and second load transistors (Q₂₁ and Q₂₂), the emitter of said first load transistor being connected to the collector of said first input transistor, the emitter of said second load transistor being connected to the collector of said second input transistor and bases of said first and second load transistors being commonly connected and operatively grounded, said load resistor circuit includes two load resistors (R₂₁ and R₂₂) connected to collectors of said first and second load transistors, respectively, to output two output signals (S OUT1 and S OUT2 ) from points at which said collectors and said load resistors are commonly connected, and said bias current source includes the first and a second current mirror circuit (CS₂,CS₃) connected to said first and second load transistors, respectively. A level shift circuit according to claim 5, characterized in that said first current-mirror circuit is connected to the control voltage source (V C ) to change a current supplied therefrom. A level shift circuit according to claim 5, characterized in that said second current-mirror circuit is connected to the control voltage source (V C ) to change a current supplied therefrom. A level shift circuit according to claim 1, characterized in that a plurality of said current drive circuits (ID₁ to ID n ) are connected in parallel, each current drive circuit receiving a said input signal (S IN ) to be synthesized, said bias current source and said emitter of said at least one load transistor (Q) in said load transistor circuit are connected to the commonly connected collectors of said parallel current drive circuits. A level shift circuit according to claim 4, characterized in that said latch circuit (FF) includes a master latch circuit (ML) driven by a clock (CLK) and a slave latch circuit (SL) driven by an inverted clock (CLK). A level shift circuit according to claim 9, characterized in that said master latch circuit (ML) comprises: a first pair of emitter follower transistors (Q40, Q41) connected in parallel, having their bases connected to said load resistor circuit, their collectors connected to a power supply voltage (V cc ) via respective load resistors (R₄₁, R₄₂), and their emitters connected to a transistor (Q₄₂) which receives said clock (CLK) at its base; and a second pair of emitter follower transistors (Q₄₃, Q₄₄) connected in parallel, having their bases connected to the respective collectors of the first pair of emitter follower transistors (Q₄₀, Q₄₁) and having their emitters connected to a transistor (Q₄₅) which receives a reference voltage (V S ) at its base; wherein the emitters of said transistors (Q₄₂, Q₄₅) are connected to a constant current source (CS₄).

Inventors: AMEMIYA IZUMI BAMUHAITSU KIKUN, HAMANO HIROSHI MIYOSHI-SO, IHARA TAKESHI SANRAIZU SHINJO, KITASAGAMI HIROO SHINTAMAGAWA, YAMAMOTO TAKUJI - - MASUGATA, AMEMIYA, IZUMI BAMUHAITSU KIKUNA 3-306, HAMANO, HIROSHI MIYOSHI-SO, 864, IHARA, TAKESHI SANRAIZU SHINJO 204, KITASAGAMI, HIROO SHINTAMAGAWA HAIMU 2-208, YAMAMOTO, TAKUJI 6-22-24, MASUGATA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1988
Main classification: H03K19
IPC codes: H03F1, H03F3, H03K19, H03K5