Memory control apparatus for use in a data processing system

Abstract: Method and apparatus are disclosed for use in a digital computer system having a system bus (10) for interconnecting together various agents (12,14,16). A page mode type of memory access provides for the rapid transmission of a block of data across the bus. Blocked refresh means (83) is also employed which disables, if possible, the burst refresh of the memory (60) until a data transfer is completed. A local processor (86) upon an agent having a memory controlled in such manner is provided a high priority (HD) signal line for overriding a current bus transfer for gaining access to the memory. During such a high priority access the blocked refresh means operates in a manner somewhat similar to its operation during the sequential bus transfer, however fewer rows are refreshed during the burst refresh.

Description: This invention relates generally to digital computers and, in particular, relates to a digital computer system having a system bus for interconnecting various agents and a page mode memory access for transferring blocks of data between agents. This invention provides a computer bus having page mode memory access. Modern computer systems are often characterized by a plurality of functionally differenct types of circuit cards, or agents, which are interconnected by means of a system bus. In order to facilitate the design of such circuit cards and the implementation of software routines necessary to utilize these cards such computer buses are typically standardized. One such bus is a 32-bit high performance synchronous bus known as the P1296, which is also commonly known as Multibus II. Such a bus typically comprises a plurality of predefined signal lines which are utilized for the transfer of memory addresses and data between two or more circuit boards which are interconnected to the bus. Other signal lines are defined for regulating the transfer of data over the bus, for interrupt events, and for error conditions. Also, one or more clocks are provided by the bus for synchronizing the flow of data between agents. Typically, such a bus will have interconnected thereto at least one circuit card having a data processor contained thereon, such as a microprocessor device. Other circuit cards may comprise input/output (I/O) circuitry for interfacing to external devices such as mass storage devices, CRTs and printers. Other cards interconnected to the bus may be high capacity memory cards which comprise a plurality of read/write memories such as dynamic random access memories (DRAM) which are operable for the storage and retrieval of data. Additionally, a circuit card such as a card adapted for control of a mass storage device may also have a relatively large amount of DRAM for local buffering of data going to and coming from the mass storage device and may also have a local microprocessor device for controlling the mass storage device. A problem arises when it is desired to transfer relatively large blocks of data betwen circuit cards on such bus. Inasmuch as the bus may be considered to be a shared resource which is common to all of the circuit cards which are interconnected to the bus, it is desirable that such data transfers occur in a rapid manner to avoid a reduction in the bandwidth of the bus. In order to achieve an increased bus bandwidth it has been known to provide a first in/first out (FIFO) buffer upon both a requesting agent and a relying agent. For example, the requesting agent may notify the relying agent that it desires a block of data to be read from a local memory on the replying agent and thereafter transmitted to the requesting agent over the bus. In response thereto the replying agent accesses the desired memory locations and loads the data contained therein into the replying angent's FIFO, the data thereafter being transmitted from the FIFO across the bus to a FIFO on the requesting agent from where the requesting agent may extract and store the data in a local memory. As can be appreciated, the use of such FIFO buffers may result in the system incurring additional costs and complexity. Furthermore, the storage capacity of available FIFO buffers may be insufficient to transfer a desired block size of data, resulting in the requirement that the FIFO be fully loaded two or more times with data. In other systems it has been known to utilize memory interleaving in order to increase the data transfer speed of the bus. Memory interleaving however may also result in an increased system cost. Also, memory interleaving may increase the speed of only certain types of data transfers. From UK patent application print GB 2 093 236A a quasi-floppy disk memory using DRAMs to simulate the magnetic diskette, and a memory controller which simulates the operation of a floppy disk controller are known. The CPU sends a request to read a (simulated) sector to timing and refresh controller as if it were a standard floppy disk controller. The timing and refresh controller controls the registers receiving the data and the desired track and sector, then performs the access to the DRAMs to either store or retrieve sequential bytes of data. When 128 bytes have been transferred the timing and refresh controller terminates the transfer process. Hence, the timing and refresh controller controls the termination of access to the DRAMs only. The problem of achieving or maintaining a high bus bandwidth is also related to a requirement that the memory devices, if they are DRAM devices, be periodically refreshed. This refresh requirement may result in the need to interrupt a block data transfer in order to accomplish the refresh. Also, if a local processor is included on the agent, the local processor may also require access to the memory, thereby also interfering with the transfer of data between agents. SUMMARY OF THE INVENTION The foregoing problems are overcome and the advantages are realized by a memory control apparatus in a data processing system having at least a requesting agent and a replying agent electrically coupled together by a system bus, the requesting agent requesting access to a memory on the replying agent for storing and retrieving data therein over the system bus. The claimed memory control apparatus comprises means for detecting a request for initiating an access cycle to a memory on the replying agent; means, responsive to the request detecting means, for asserting a plurality of memory address control signals for successively accessing the memory on the replying agent, the control signals comprising at least a row address strobe associated with a row address and a column address strobe associated with a column address; and means for detecting a completion of the access cycle to the memory, the completion detecting means being responsive to a logic state of an end of cycle control signal generated by the requesting agent. In accordance with the invention the asserting means asserts the memory address control signals by asserting the row address strobe signal a plurality of times in conjunction with a row address being indicative of a page of data within the memory, and thereafter asserts and deasserts the column address strobe signal in conjunction with a plurality of column addresses for performing a page mode type of memory access. In accordance with a method of the invention there is disclosed a method for controlling a memory for use in a data processing system having at least a requesting agent and a replying agent electrically coupled together by a system bus, the requesting agent requesting access to a memory on the replying agent for storing and retrieving data therein over the system bus, the method comprising the steps of detecting a request for initiating an access cycle to a memory on the replying agent; asserting a plurality of memory address control signals for sequentially accessing the memory on the replying agent, the control signals comprising at least a row address strobe associated with a row address and a column address strobe associated with a column address; detecting a completion of the accesss cycle to the memory, the completion detecting means being responsive to a logic state of an end of cycle control signal generated by the requesting agent; and wherein the step of asserting is accomplished by asserting the row address strobe signal in conjunction with a row address being indicative of a page of data within the memory, and thereafter asserting and deasserting the column address strobe signal in conjunction with a plurality of column addresses for performing a page mode type of memory access. The foregoing aspects of the invention will be more fully described below in the detailed description of the invention, the description being read in conjuntion with the drawings wherein: Fig. 1 is a block diagram of a system bus 10 having a plurality of agents coupled thereto illustrating various types of signal groups which comprise the bus 10; Fig. 2 is a block diagram of a typical DRAM which may be employed upon an agent coupled to the bus 10; Fig. 3 is a simplified timing diagram showing typical Ras* - Cas* memory access cycles which may be employed to access the DRAM of Fig. 2; Fig 4. is a simplified timing diagram showing page mode memory access cycles which are one feature of the invention; Fig. 5 is a block diagram which illustrates a memory controller 66 and other circuitry coupled to a memory 60; Fig. 6 is a timing diagram which shows the result of the detection of a page crossing signal; Fig. 7 is a timing diagram which shows a burst refresh of the memory 60; and Fig. 8 is a timing diagram which shows the refresh of the memory 60 during a high priority local processor access. Although the method and apparatus of the invention will be described herein in the context of a Multibus II environment, it should be appreciated that the invention may be practiced in many digital computer systems having a bus for transferring data between at least two agents interconnected upon the bus. The operating characteristics of the Multibus II are described in a document entitled "High Performance 32-Bit Bus Standard P1296" which was produced by the IEEE microprocessor standards committee P1296 working group, June 20, 1986, draft 2.0. Referring now to Fig. 1 there is shown in block diagram form a portion of a digital computer system 1 comprising a bus 10 and a plurality of agents 12-14 connected thereto. As shown in Fig. 1 a requesting agent 12 and replying agents 14 and 16 are bidirectionally coupled to the bus 10. The requesting agent 12 may have a local memory 18 which may be comprised of dynamic random access memories (DRAM). The replying agent 16 is also shown to have a local memory 20 which may be similarly comprised of DRAM. Also coupled to replying agent 16 is a mass storage device 22 which may comprise a familiar Winchester or floppy magnetic disk for the mass storage of data and program information. Although one requesting agent 12 and two replying agents 14 and 16 are shown in Fig. 1, it should be realized that such a digital computer system may have a plurality of requesting agents and a plurality of replying agents coupled to the bus. It should further be realized that at one time in the operation of the system 1 that the requesting agent 12 may be a replying agent, and that the replying agent 16 may at that time be a requesting agent. The characterization of an agent as being either a replying agent or a requesting agent is accomplished by means of certain bus signals which will be described below. As an example of the operation of such a system, if the system 1 is a word processing system the requesting agent 12 may be a central computer board and the replying agent 16 may be a disk controlling board which stores and retrieves document data from the mass storage device 22. In such a system an operator may interact via a keyboard or some other means with a program on the central computer board, the program embodying a word processing program wherein the operator enters document data which is stored on mass storage 22. Inasmuch as such document data may be organized as pages of data it can be appreciated that a certain block size of data may be utilized to represent a visually displayed page of a document, such as 2K bytes of data. Thus, it can still further be appreciated that it may be desirable in such a system to transfer blocks of data across the bus 10 as 2K byte blocks thereby facilitating the transfer of pages of document data in the system. Bus 10 may comprise 96 conductor lines, which are subdivided into groups having different functionality. A central control signal group 24 provides system-wide signals such as reset and initialization control signals. In the Multibus II ther are defined eight central control signals, some of which are a reset signal for initializing the system and two clock signals, namely a bus clock (BCLK*) and a central clock (CCLK*). However, it may be desirable in some systems to provide a third clock signal, such as a system clock (SCLK*) 24a (shown in Fig. 5). For example, the Multibuss II specifies that CCLK* should be twice the frequency of BCLK*, with data transfers across the bus requiring one BCLK* cycle. Thus, if BCLK* is 10 MZH then CCLK* is 20 MHZ and a bus data transfer requires 200 nanoseconds. However, in some systems it may be desirable to operate BCLK* at 5 MHZ, CCLK* at 10 MHZ while still requiring one BCLK* cycle to accomplish a bus data transfer. In such a system it may further be desirable to provide a higher frequency clock signal, such as SCLK* 24a operating at 20 MHZ, for generating high frequency bus timing and other signals on the plurality of agents coupled to the bus. The arbitration cycle signal group 26 is comprised of seven signal lines, one being a bus request (BREQ*) which is wire ORED between each of the agents on the bus. Any agent requiring access to the bus 10 must assert BREQ* in order to be granted access, the access typically being granted by an arbitration logic circuit chich is not shown in Fig. 1. Six arbitration identification signals, ARBO*-ARB5*, are driven by an agent or agents which require access to the bus, these signals being inputs to the arbitration controller. The address/data bus signal group 28 provides address, data and parity signals for data read and write bus transfers. There are a total of 36 address/data bus signals, characterized as 32 multiplexed address/data bus signals (AD0*-AD31*) and four parity signals associated with bytes of data, namely PAR0*-PAR3*. The exception cycle signal group 30 provides error detection which is utilized to terminate a bus transfer cycle. There are two exception cycle signals, a bus error signal (BUSERR*) and a time out signal (TIMOUT*). A system control signal group 32 provides control signals which are utilized to transfer addresses and data over the bus. In the Multibus II there are 10 system control signals SC0*-SC9*. During a request phase of a bus transfer cycle the requesting agent 12 drives SC0* through SC9* to provide command information to the replying agent, such as a the replying agent 16. During the reply phase of the bus transfer cycle the requesting agent drives SC9* and SC0*-Sc3* while the replying agent drives SC8* and SC4*-SC7* in order to provide handshaking and status information between the requesting and replying agents. In general, the Multibus II supports a plurality of different types of data transfers such as message types. These message types may be a plurality of unsolicited message type. Additionally, memory space data transfers may occur. Data transfers of up to 64K bytes are supported by the bus. However, in many conventional systems bus data transfers are limited to 32 byte packets. A first in/first out (FIFO) buffer is typically utilized on each agent, the FIFO buffer being fully loaded with data on the replying agent, the data thereafter being transferred to the bus 10 where it is received by a FIFO buffer on the requesting agent. As has been previously described, the use of such FIFO buffers may result in increased system cost and complexity. Additionally, a significant amount of time is required to fully load and unload the FIFO buffers. Referring now to Figs. 2, 3 and 4 there is shown a well known DRAM having a Data In and a Data Out signal line and a plurality of address lines AD0 through AD8. The DRAM 40 also has a Ras*, CAS*, and a R/W signal control line. In order to achieve a large data storage device with a minimum of input signal pins and, hence a small package size, such DRAMs typically multiplex the address lines such that at one time in the operation of the device the address lines are characterized as row address lines under the control of Ras* and at another time in th cycle are characteized as column address lines under the conrol of Cas*. The device shown in Fig. 2 has nine address signal pins and, thus, has a total of 18 address inputs which yield a device having a total of 256K bit storage locations. Of course, other DRAMs may have more or less than nine address inputs such as 64K and 1M bit devices and other devices may store more than one bit of data, such as devices adapted to simultaniously store and retrieve four bits of data. As shown in Fig. 3 the conventional addressing mode for such a DRAM results in Ras* being asserted 42 for latching within the RAM the row address lines appearing on AD0-AD8. Subsequent to the assertion of Ras* the state ofthe address lines AD0-AD8 are switched to the desired column address and Cas* is asserted 44. The assertion of Cas* also typically either stores within the device or reads from the device, depending upon the state of R/W*, a bit of data at the specified row and column address. In Fig. 4 there is shown another type of addressing mode known as a page mode type of access wherein Ras* is asserted once at 46 to latch the row address within the device. Thereafter, the column address may be repeatedly varied and Cas* may be asserted a plurality of times (48-58) in order to store or retrieve data. Inasmuch as the row address lines can be considered to define a page of data bits within the device, multiple assertions of Cas* can be utilized to Scroll" through the page of data in a significantly more rapid manner than the conventional Ras*-Cas* type of cycle. Such a page mode access is made especially convenient if the data is accessed sequentially, that is, if the column address is incremented or decremented by one for each access. Of course, non-sequential page mode access is also possible and may be desirable for some applications. In accordance with the method and apparatus of the invention this page mode type of access cycle is advantageously employed to increase the bandwidth of the system bus for at least the memory space type of data transfer. Inasmuch as it has been known to utilize the conventional Ras*-Cas* type of cycle for transferring data to and from the bus, the delays incurred by the assertion of Ras* for each memory access often require that the aforementioned FIFO buffer be utilized to temporarily buffer data. In accordance with the invention, a much faster memory access cycle is achieved by employing the page mode type of access, thereby eliminating the need for local buffer storage of incoming or outgoing data in order to maintain a desired bus bandwidth. Referring now to Fig. 5 there is shown an illustrative emodiment of the invention. A memory 60 is comprised of two banks of memory devices, such as DRAM devices, organized as a Bank 1 62 and a Bank 2 64. Selection between banks is made by Ras0* and Ras1* signal lines which are inputs to Bank 1 and Bank 2, respectively. Each of the Banks 62 and 64 is comprised of four subbanks of memory devices organized as bytes. Selection of a particular byte within a Bank is made by the state of the Cas0*-Cas3* signal lines. The particular mode of addressing is determined by the state of the A0, A1, W0 and W1 signal lines which are inputs to a memory controller 66, these signal lines being, for example, various address signals of the Memory Address Bus 68 and control signals of the system control signal group 32. The states of the aforementioned signals are decoded by a decoder 70 associated with memory controller 66 to select both the width of the memory transfer and also th columns of memory devices which are selected. Truth tables which describe the operation of decoder 70 are given below. WD1 WD0 Width of Memory Transfer 0 0 32 Bits 0 1 24 Bits 1 0 16 Bits 1 1 8 Bits WD1 WD0 A1 A0 CAS3* CAS2* CAS1* CAS0* 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 An R0 input to memory controller 66 may also be an address line, the state of which selects either Bank 1 or Bank 2 for access via Ras0* or Ras1*. A request/acknowledge (R/A) input signal is a bidirectional signal which is normally an input to memory controller 66 when the controller 66 is in a quiescent operating state. When a request for access to memory 60 is made by a requesting agent during the request phase of a sequential data transfer the R/A signal line may be pulsed low by external logic (not shown). After making such a request for memory access the R/A signal line may be released by the external logic such that it may be driven by controller 66 during the memory request acknowledge cycle. In response to the request memory controller 66 accesses the memory 60 in accordance with the states of the A0, A1, W0, W1 and R0 lines in conjunction with the state of the Read/Write (RW) input. Memory controller 66 then drives R/A to a logic low signal level to acknowledge the memory access. After initiating a memory access the memory controller 66 accesses the memory repeatedly until an EOC signal line (bus signal SC2*) is asserted for indicating an End of Cycle condition. When EOC is asserted the memory controller 66 is informed that the current memory access is the final memory access of the reply phase of the sequential data transfer. Referring now to Fig. 6 there is shown a timing diagram which illustrates a portion of consecutive memory accesses made by controller 66 to memory 60 during the reply phase of a sequential data transfer. As can be seen, for each access the R/A signal line is driven low by controller 66 and therafter released. During these memory cycles, and in accordance with the invention, the Ras* line is maintained in an asserted, or low state, and the Cas* line is repeatedly toggled to achieve a page mode memory access cycle. During consecutive page mode access cycles the SC4* signal line is asserted by memory controller 66 for notifying the requesting agent that the replier ready condition exists, that is, that the memory controller 66 is accessing data for the requester. A DENO signal line output by the memory controller may be utilized, when data is being read from memory 60, to enable a buffer 72 for placing the data from the Memory Data Bus 74 onto the system bus 10. In reference to Fig. 6 it can be appreciated that the page mode type of memory access, which is a feature of the invention, advantageously provides for a high bus bandwidth. Inasmuch as the Ras* signal line is not required to be driven for each memory access, the additional delay incurred by the assertion of Ras* in conjunction with each Cas* is eliminated, thereby increasing the speed of the overall transfer of a block of data to or from the memory 60. For the DRAM shown in Fig. 2 a given page of data is characterized by the nine row address lines associated with the Ras* signal. Thus, the DRAM can be seen to comprise 512 pages of data. Also, each page has 512 storage locations, due to the nine column address lines associated with the Cas* signal. If a desired block size of data exceeds 512 bytes it is necessary to access more than one page of data within the device. In accordance with the invention, this is accomplished by a memory column address decoder 76 which may be a nand gate having nine inputs for detecting when the column address lines are each at a logic one condition. Thus, the output of the decoder 76 is a Page Crossing Detect (PC) signal which is an input to the memory controller 66. This is illustrated in Fig. 6 at time T1 where PC* is driven low by the decoder 76. In response thereto the current memory access is completed and the Ras* signal line is driven high by memory controller 66 in conjunction with the R/A signal and also SC4*. This operation of memory controller 66 notifies the agent receiving data, via the deassertion of the replier ready handshaking signal SC4*, that the replier is no longer in a ready condition. While Ras* is deasserted the row address whithin address latch 77 is, for example, incremented by 1 to select the next consecutive page of data within the memory devices. Thereafter at time T3 RAS* is asserted, thereby latching the new row address into the memory devices and the page mode memory access cycles begin as before, the SC4* line being once more asserted and R/A being once more driven to a low state. In accordance with the invention the refresh of DRAM within the memory 60 may be accomplished by a blocked refresh technique. A timer 78 generates refresh requests at predetermined intervals, such as a refresh request every 13.8 microseconds. The refresh requests are counted by a refresh request counter 80 and a comparator 82 determines when the number of counted refresh requests equal or exceed a predetermined threshold value, such as 24. As this time controller 66 will attempt to burst refresh all of the 24 pending requests. If, however, there is a bus transfer in progress the memory controller 66 will not per form the burst refresh. The memory controller 66 will attempt to wait until the bus transfer is completed, that is, a transfer has occurred wherein EOC is asserted. If, however, the counter 80 indicates that some maximum number of refresh requests are pending, such as 41, the bus transfer is interrupted and the burst refresh is performed. When the bus transfer is interrupted all of the pending refreshes are performed. The particular numbers chosen as the pending refresh threshold and the maximum number of pending refreshes are determined such that the amount of time represented by the difference between the threshold and the maximum values is a sufficient amount of time within which to transfer some predetermined block size of data. For example, for a refresh request made every 13.8 microseconds the difference between 24 and 41 refresh requests is approximately 234.5 microseconds which, it has been found, is a sufficient amount of time to complete a 2K byte (2048 bytes) bus transfer operation. Thus, if a 2K byte sequential bus transfer operation is initiated just prior to the time when 24 pending refresh requests are accumulated the bus transfer will run to completion before the memories are refreshed. Preferrably, an even number of rows are refreshed during the burst, such as 42 rows if the maximum value is indicated by counter 80. In order to burst refresh the memories a refresh acknowledge (RACK) signal is generated by a refresh controller 83, the RACK signal enabling a refresh row counter 84 to place the refresh row addresses on the memory address bus. RACK is subsequently toggled between a high and a low state under the control of controller 83 for, as an example, 24 cycles in order to burst refresh 24 row addresses. During refresh the RAS0* and RAS1* signals are preferably both asserted to refresh simultaneously both banks of memory. The refresh row counter 84 may be incremented by the rising edge of th RACK signal such that at the completion of each refresh cycle counter 84 has a value corresponding to the next row address to be refreshed. A local processor 86, may also have access to the memory 60 via separate address and data latches 88 and 90, respectively. Local processor 86 may also be serviced by a dedicated memory controller (not shown) operable for generating memory access signals. When the local processor is granted access to the memory 60 the AEN1 signal is driven to enable the address and data latches of the local processor onto the memory address and memory data buses 68 and 70, respectively. In accordandce with the invention, the local processor is also proved with a High Priority (HP) signal which is an input to the memory controller 66 to interrupt, if necessary, a current bus transfer. The HP signal therefore allows the local processor to gain access to the memories by overriding a current bus transfer. The HP signal will override the current bus transfer for as long as it is asserted, thereby allowing the local processor 86 to make a number of consecutive high priority accesses to the memory 60. The aforedescribed blocked refresh operates somewhat differently if a series of high priority local processor memory accesses are in progress. As described previously, the memory controller 66 will accumulate pending refresh requests up to a maximum number of 41. If a high priority access is in progress at this time, the high priority access will be temporarily overridden but only two memory refreshes will take place. Thus, the high priority access by the local processor is suspended for only a relatively brief period of time before the local processor is once again granted access to the memory 60. Of course, after the two refreshes are accomplished the counter 80 will continue to accumulate refresh requests such that when the counter once again reaches 41 and, if the high priority access is still in progress, the memory controller will once again suspend the high priority access and burst refresh to the next consecutive two row addresses. The operation of the aforedescribed blocked burst refresh and high priority request are shown in the waveforms of Figs. 7 and 8. It can be appreciated that the foregoing description of the memory controller 66 and the associated circuitry is illustrative and that a number of different embodiments may occur to those skilled in this art. For example, the aforedescribed functions of the memory controller 66 may be accomplished by a plurality of discrete logic devices or, prefereably, may be embodied within a LSI semiconductor device. Similarly, the various elements associated with memory controller 66 may or may not be included within such an LSI device. For example, the timer 78 may be external to the device as may be the refresh request counter 80. It should be further realized that the memory controller 66 may operate with still other devices which are adapted for monitoring and controlling the system bus 10 activity, such as a device operable for asserting R/A when a request is made by another agent on the bus 10 for access to the memory 60. Also, and by example, the SC3* and SC4* signal lines may not be tied directly from the bus 10 to the memory controller but may be buffered or otherwise modified by other logic devices. Therefore, the present invention is not to be considered to be limited to the embodiment described herein, the invention is instead meant to be limited only as defined by the appended claims.

Claims: Memory control apparatus in a data processing system having at least a requesting agent (16) and a replying agent (14) electrically coupled together by a system bus (10), the requesting agent requesting access to a memory (60) on the replying agent (14) for storing and retrieving data therein over the system bus (10), the apparatus*characterized by: *being means (66) for detecting a request (R/A) for initiating an access cycle to the memory (60) on the replying agent (14); means (66), responsive to the request detecting means (66), for asserting a plurality of memory address control signals (RAS0, RAS1, CAS0, CAS1, CAS2, CAS4) for sequentially accessing the memory (60) on the replying agent (14), the control signals (RAS0, RAS1, CAS0, CAS1, CAS2, CAS4) comprising at least a row address strobe (RAS0, RAS1) associated with a row address and a column address strobe (CAS0, CAS1, CAS2, CAS3) associated with a column address; means (66) for detecting a completion of the access cycle to the memory, the completion detecting means (66) being responsive to a logic state of an end of cycle control signal (EOC) generated by the requesting agent (16); and wherein the asserting means (66) asserts the memory address control signals (RAS0, RAS1, CAS0, CAS1, CAS2, CAS4) by asserting the row address strobe (RAS0, RAS1) in conjunction with a row address being indicative of a page of data within the memory, and thereafter asserts and deasserts the column address strobe signal (CAS0, CAS1, CAS2, CAS3) in conjunction with a plurality of column addresses for performing a page mode type of memory access. The memory control apparatus of claim 1 further characterized by: means (78) for generating a memory refresh request signal at predetermined intervals; means (80) for counting each of the refresh request signals; means (82) for comparing a value of the counted refresh request signals to a predetermined threshold value for determining when the number of counted refresh request signals equals or exceeds the threshold value; and means (83), responsive to the comparing means (82), for refreshing a plurality of memory rows, the number of rows being refreshed being substantially equal to the counted value. The memory control apparatus of claim 2 further characterized in that: the refreshing means (83) is coupled to the asserting means (66) and is responsive to the operation of the asserting means (66) for disabling the refresh of the memory (60) during the operation of the asserting means (66). The memory control apparatus of claim 3 further characterized in that the comparing means (82) further comprises means for comparing the value of the counted signals to a predetermined maximum value for determining when the number of counter refresh request signals equals the maximum value, and wherein the refreshing means (83) is further responsive to the operation of the maximum value comparing means (82) for determining when the counted value equals the maximum value for suspending the operation of the asserting means (66) and of refreshing a predetermined number of rows of the memory (60). The memory control apparatus of claim 4 further characterized in that: the predetermined interval is approximately 13.8 microseconds, wherein the threshold value and the maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is an even number of rows. The memory control apparatus of claim 1 further characterized by: means (76) for detecting a memory page boundary having inputs coupled to the column address lines and an output expressive of a state of the column address which is indicative of a memory page boundary; and means (66), responsive to the output of the page boundary detecting means (76), for deasserting the row address strobe signal, providing a row address expressive of another page of data, and asserting the row address strobe signal. The memory control apparatus of claim 4 further characterized in that the replying agent further has a local data processing means (86) coupled to the memory (60) and the memory control apparatus is further characterized by: means (66), responsive to a state of a high priority memory access request (HP) from the local data processing means (86), for suspending the operation of the asserting means (66) for accessing the memory (60) in response to the request from the requesting agent (16); and means (66), responsive to the high priority request (HP), for enabling the accessing of the memory (60) by the local data processing means (86). The memory control apparatus of claim 7 further characterized in that: the refreshing means (83) is coupled to the asserting means (66) and is responsive to the state of the high priority request (HP) for disabling the refresh of the memory during the operation of the local data processing means (86) access enabling means (66). The memory control apparatus of claim 8 further characterized in that: the predetermined interval is approximately 13.8 microseconds, wherein the threshold value and the maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is two.

Inventors: LAGOY BRIAN E J JR, LAGOY, BRIAN E. J. , JR.
Applicants: WANG LABORATORIES, WANG LABORATORIES INC.
Application year: 1988
Main classification: G11C8
IPC codes: G11C8, G06F12, G11C7, G06F13, G11C11