Semiconductor memory device with improved redundant scheme

Abstract: A semiconductor memory device provided with improved redundant scheme is disclosed. The memory device comprises a plurality of sub-arrays each having a plurality of normal segment word lines and at least one redundant segment word line arranged in rows common with other sub-arrays, a plurality of control normal word lines in the rows extending through the plurality of sub-arrays, at least one control redundant word line extending in the row through the sub-arrays, a plurality of first block control lines and second block control lines, each first and second block control lines being provided for each sub-array, a plurality of first selecting means each coupled to one of the control normal word lines the one of the first block control line and one of the normal segment word lines for selecting the one normal segment word lines in response to the selection levels of the one control normal word line and the one first block control line, a plurality of second selecting means coupled to the control redundant word line, one of the second block control lines and the one redundant segment word line, a plurality of normal decoders provided for the control normal words lines, at least one redundant decoder provided for the control redundant word line, means for selecting one of the first block control lines when the at least one control redundant word line is not selected, means for making all the first block control lines at the non-selection level when the at least one control redundant word line is selected, and means for selecting one of the second block control lines upon the selection of the control redundant word line.

Description: The present invention relates to a semiconductor memory device fabricated on a semiconductor substrate, and more particularly to a semiconductor memory device having a redundant array of memory cells. In order to save a semiconductor memory having a small number of defective memory cells thereby to improve yields of production, the redundant technique has been proposed. This redundant technique is such that a redundant memory cell array is provided to a normal memory cell array and a defective memory cell or cells in the normal memory cell array are substituted by good memory cells in the redundant memory cell array. For substituting the defective memory cell in the normal memory cell array by the good cell in the redundant memory cell array, the operation of normal address decoders is inhibited when a redundant address decoder selects or designates a good cell in the redundant memory cell array. The above inhibition of operation of the normal address decoders is achieved by applying the selection output signal of the redundant address decoder to the normal address decoders as an inhibition signal. However, the number of the normal address decoders such as row decoders is very large in the recent large capacity semiconductor memory device and the above selection output must be applied to such large number of address decoders. Therefore, load capacitance of the selection output signal of the redundant address decoder is very large, and therefore the normal address decoders cannot recognize the occurrence of the selection output signal of the redundant address decoder at a high speed but have to wait for a certain delay time. Thus, the normal address decoders are controlled to be enabled a predetermined time after the operation of the redundant address decoder. Accordingly, the conventional semiconductor memory device provided with the redundant scheme is not suitable for high speed utilization. EP-A-096 359 discloses a semiconductor memory device in which a memory cell array is divided into plural sub-array blocks each of which including a plurality of sub-word line, a plurality of gate each having an output node connected to an associated one of the sub-word lines, a first input node connected to an associated one of the block selection lines and a second input note. The memory further includes a plurality of main word lines each extending through the sub-array blocks to be coupled to the second input node of an associated one of the gates. One of the main word lines and one of the block selection lines take an active level in response to address information so that one of the sub-word lines is selected. However, this document is quiet about a redundant memory circuit. US-A-4 051 354 discloses a semiconductor memory device having a redundant memory circuit. It is an object of the present invention to provide a semiconductor memory device of the redundant type which can operate at a high speed. This object is achieved by a semiconductor memory device as defined in claim 1; the dependent claims are related to further developments of the invention. According to the present invention, the conventional lengthy normal and redundant word lines are splitted into a plurality of short normal and redundant segment word lines and the first normal word line decoders for selecting one of the first control word lines operate simultaneously with the second, redundant word line decoder. As a result, the memory device according to the invention can operate at a high speed. Fig. 1 is a schematic block diagram of a conventional semiconductor memory device; Fig. 2 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention; Fig. 3 is a schematic block diagram of a semiconductor memory device according to a second embodiment of the present invention; and Fig. 4 is a schematic circuit diagram of block gated amplifiers employed in the memory devices in Figs. 2 and 3. With reference to Fig. 1, a conventional redundant type semiconductor memory device will be explained. A normal memory cell array 10 includes a plurality of static type memory cells MC each made of flip-flop coupled to normal word lines NW-1 to NW-m in rows and a plurality pairs of bit lines BL1, B L1 to BLn, B Ln in columns. A redundant memory cell array 16 includes a plurality of memory cells MC coupled to redundant word lines RW1, RW2 arranged in rows and the pairs of bit lines shared with the normal array 10. The normal word lines NW-1 to NW-m are connected to normal word line decoders ND-1 to ND-m, respectively. The redundant word lines RW1, RW2 are connected to redundant word line decoders RD1, RD2, respectively. Each of the normal decoders and the redundant decoders includes a NAND gate receiving row address signals AR in a predetermined combination and an inverter 12. The outputs of the redundant decoders RD-1 and RD-2 are applied to inputs of a NOR gate 13 whose output is applied, as an inhibition signal  R , to the inputs of the NAND gates 11 of the respective normal decoder ND-1 to ND-m. When one of the redundant word lines is selected, the NOR gate produces a low level of the signal  R so that the outputs of all the normal decoders are forcibly set at a low, non-selection level. While, when the redundant word lines RW-1 and RW-2 are all in a non-select state, all the redundant word lines RW-1 and RW-2 are at a low non-selection level, while the signal  R is at a high level, so that the normal word line decoders ND-1 to ND-m are enabled to select in accordance with the row address signals. On the other hand, when one of the redundant word lines RW-1 and RW-2 is selected, the signal  R is shifted to a low level to cause all the normal word line decoders ND-1 to ND-m are inactivated, so that all the normal word lines NW-1 to NW-m are brought into a non-select state. A column decoder receives column address signals AC and select one pair of column selection transistors QY 11 , QY 12 - QY n1 , QY n2 in a known manner so that a selected pair of bit lines are electrically connected to a pair of data lines DL, DL which are connected to a pair of input terminals of a data output amplifier 15. In the above-described conventional word line substitution type redundant circuit, the signal  R is input to all the normal word line decoders ND-1 to ND-m and therefore the load which must be driven by the signal  R is large. Accordingly, when a redundant word line is selected, a normal word line may be undesirably selected before the normal word line decoders are inactivated in response to the signal  R , resulting in multi-selection of both a redundant and a normal word line. Referring to Fig. 2, a semiconductor memory device according to a first embodiment of the present invention will be explained. The normal memory cell array 10 in Fig. 1 is divided into a plurality of normal sub-arrays 10-1 to 10-K (K being favorably smaller than m) and the redundant array 16 in Fig. 1 is also divided into a plurality of redundant sub-arrays 16-1 to 16-K. Normal segment word lines BW11 to BW m1 are arranged in rows and j pairs of bit lines BL1, BL1 to BLj, BL j are arranged in columns in the normal sub-array 10-1. The numbers "j" and "K" have the relation of "j" × "K" = "n" (n is the number of the bit line pairs in Fig. 1). Other normal sub-arrays 10-2 to 10-K have the same arrangement of memory cells MC, "m" of normal segment word lines and "j" pairs of bit lines. The redundant sub-array 16-1 includes redundant segment word lines RW11 and RW12, "j" pairs of bit lines BL1, B L1 ― BLj, BLj and memory cells. Other redundant sub-arrays 16-2 to 16-K have the same arrangement as the redundant sub-array 16-1. The normal segment word lines BW11 to BWm1 in the sub-array 10-1 are connected to outputs of NOR gates NG11 to NG1m, respectively. The NOR gates NG11 ― NG1m have their first inputs connected to control normal word lines NW-1 to NW-m connected to normal word line decoders ND′-1 to ND′-m, respectively while second inputs of the NOR gates NG11 to NG1m receive a block enable signal  N1 generated from a block decoder BD-1. The redundant segment word lines RW11 and RW21 in the redundant sub-array 10-1 are connected to outputs of NOR gates RG11 and RG21. First inputs of the NOR gates RG11 and RG21 are connected to control redundant word lines RW-1 and RW-2 which are driven by the redundant word line decoders RD′-1 and RD′-2, respectively. Second inputs of the NOR gates RG11 and RG21 are supplied with a block redundant enable signal  R1 from the block decoder BD-1. Other normal segment word lines and the redundant word lines in other sub-arrays are similarly arranged, as illustrated. The block decoder BD-1 includes a NAND gate receiving a first part of column address signals (AC1) in a predetermined combination, a NOR gate 23 receiving the output signal of the NAND gate 22 and a control signal  R ′ generated from a NAND gate 21, inverters 24 to 26. The block decoder BD-1 operatively determines whether either the normal sub-array 10-1 or the redundant sub-array 16-1 is to be selected or not. In this embodiment, the selection level of the control normal word lines NW-1 to NW-m and the control redundant word lines is the low (ground) level. Also, the active, selection levels of the signals  N1 -  NK ,  R1 -  RK are the low level. The block decoders BD-1 to BD-K also produce sense control signals  S1 to  SK which are applied to block sense amplifiers 20-1 to 20-K. The active level of the sense control signal is the high (V DD ) level and one of the block sense amplifiers provided for the selected sub-array is enabled by the active level of the sense control signal thereto so that the read-out data from the selected sub-array is produced on the data lines DL′ and DL′ . The column decoder 14′ receives a second part of the column address signals (AC2) and produces "j" column decode signals Y1 - Yj. The column decode signals Y1 - Yj are applied to the pairs of transfer gates QY11, QY12 ― QY j1 , QY j2 for the respective sub-arrays so that the selected pair of bit lines are electrically connected to a pair of block data lines BDL 1 , B DL 1 . Since the number of transfer gates QY i1 , QY i2 connected to the respective block data lines is made small by the factor of "K" as compared to the case of Fig. 1, a read-out signal on the selected pair of bit lines is rapidly transferred to the data output amplifier 15. An example of the arrangement of the block. sense amplifier is shown in Fig. 4. The amplifier 20-1 includes a pair of input transistors Q 11 and Q 12 having gates coupled to BDL1 and B DL1 , respectively and an enabling transistor Q10 having a gate receiving  S1 . A pair of depletion transistors Q13 and Q14 serve as common load elements for the amplifiers 20-1 to 20-K. When the signal  S1 is at the high level, the amplifier 20-1 is enabled and the state of DL′ and DL′ is determined by the levels of BDL1 and B DL1 . Next, operations of the device of Fig. 2 will be explained. First, the explanation will be made on the case where a memory cell in one of the normal sub-arrays is selected for reading, particularly the case where the memory cell connected to the segment normal word line BW11 and the pair of bit lines BL1, BL1 is selected. The row address signals applied to the NAND gate 11 of the normal word line decoder ND′-1 are all at a high level so that the control word line NW-1 is made at the selective, low level while the outputs of other normal word line decoders and the redundant word line decoders are at the non-selection, high level. While, the column address signals (AC1) inputted to the NAND gate 22 of the block decoder BD-1 are all at the high level and the NAND gate 22 of the block decoder BD-1 produces the low level output. In this instance, all the redundant word line decoders RD′-1 and RD′-2 are in the non-selection state to produce the high, non-selection level. Therefore, the NAND gate 21 generates the low level of the control signal R′. As a result, both inputs of the NOR gate 23 of the block decoder BD-1 are at the low level and the signal  N1 is rendered the active, low level. The signals  R1 and  S1 are at the low level and the high level, respectively. Therefore, the normal segment word line BW11 is selected by the NOR gate NG11. While other normal segment word lines and the redundant segment word lines are non-selected. Thus, data stored in the memory cells coupled to BW11 appear at the bit lines in the sub-array 10-1. While, in response to the column address signals (AC2) the column decoder 14′ makes the output Y1 at the selective, high level with others Y2 - Yj non-selection, low level. Accordingly, the pair of bit lines BL1, BL 1 are electrically connected to the pair of block data lines BDL 1 , B DL 1 and the data at BL 1 , BL 1 is transferred to the inputs of the amplifier 20-1 enabled by the high level of  S1 . Thus, the read-out signal is amplified by the amplifier 20-1 and further amplified by the data output amplifier 15 for external read-out at the output terminal OUT. Second, the explanation will be made on the case where a memory cell in one of the redundant sub-arrays, particularly the memory cell connected to the redundant segment word line RW21 and the pair of bit line BL1, BL 1 in the redundant sub-array 16-1 is selected. The row address input signals applied to the NAND gate of the redundant word line decoder RD′-2 are all at the high level so that the control redundant word line RW-2 is made at the selection, low level. While the non-selected normal word line decoders ND′-1 to ND′-m and the other non-selected redundant word line decoder RD′-1 produce the non-selection, high level outputs. In this instance, one of the normal word line decoders ND′-1 to ND′-m produces the low, selection level of output. Since the output of the NAND gate 11 of RD′-2 is at the low level, the NAND gate 21 produces the high level output so that the selected block decoder BD-1 produces the high level of the signal  N1 with the low, active level of  R1 and the high, active level of  S1 . Therefore, the outputs of the NOR gates NG 11 - NG m1 for the normal sub-array 10-1 are forcibly set at the non-selection, high level. Therefore, only the NOR gate RG21 produces the high, selection output signal so that the memory cells coupled to the redundant segment word line RW21 are addressed. Then, the signal between the pair of bit lines BL 1 , BL 1 is transferred to BDL 1 , BDL 1 via QY 11 and QY 12 and amplified by the enabled amplifier 20-1 in the similar manner as the above explained operation. According to this embodiment, in place of lengthy conventional word lines, normal and redundant segment word lines are employed and therefore the capacitance loaded to the respective segment word lines are made small. Also, the pair of block data lines are provided for the respective sub-arrays and therefore, the read-out signal between the selected pair of bit lines is amplified at a high speed via the block amplifier. When the redundant word line decoder is selected, any selection of the outputs of the NOR gates such as NG11 - NG1m is inhibited by the output such as  N1 of the block decoder, in place of inhibiting the normal word line decoder. As a result, the normal word line decoders can operate simultaneously with the redundant word line decoder without waiting the operation of the redundant decoders. Thus, the selection of the memory cell can be achieved at a high speed. Referring to Fig. 3, a memory device according to a second embodiment of the invention is explained. In Fig. 3, the portions or elements corresponding to those in Fig. 2 are designated by the same or similar references. The memory device of the second embodiment is featured in that the normal word line decoders ND"-1 to ND"-m and the redundant word line decoders RD"-1, RD"-2 produce the selection outputs of the high level and the non-selection level of the low level and the block decoders BD'-1 to BD'-K produce the active, high level of the signals ' N1 - ' NK and ' R1 - ' RK . Thus, the phase relation of the outputs of the respective word line decoders and the block decoders is opposite with respect to the embodiment of Fig. 2. Accordingly, in place of NOR gates NG 11 - NG mK , RG 21 - RG 2K , in Fig. 2, AND gates AG 11 - AG mK , RG' 21 - RG' 2K are employed in the present invention. As has been described above, unlike the conventional redundant memory wherein the inhibition control signal which is generated when a redundant word line is selected is input to normal word line decoders, the present invention is arranged such that the control signal is input to block decoders for selecting sub-arrays which are formed by dividing memory cells into two or more memory cell groups and further the number of block decoders is made smaller than the number of normal word line decoders to thereby reduce the load which must be driven by the control signal. Accordingly, the time required to generate a control signal when a redundant word line is selected is reduced, so that it is advantageously possible to prevent the occurrence of the erroneous operation wherein both a normal block word line and a redundant block word line are undesirably selected.

Claims: A semiconductor memory device comprising: a plurality of memory blocks (10-1 to 10-k) each having a plurality of normal segment word lines (BW), at least one redundant segment word line (RW11), a plurality of normal memory cells (MC) each coupled to one of said normal segment word lines, and a plurality of redundant memory cells (MC) each coupled to said redundant segment word line; a plurality of first control word lines (NW) extending through said memory blocks; at least one second control word line (RW-1) extending through said memory blocks; a plurality of first decoders (ND') provided for said first control word lines; at least one second decoder (RD'-1) provided for said second control word line; a plurality of first block control lines (ΦN) provided correspondingly to said memory blocks; a plurality of second block control lines (ΦR) provided correspondingly to said memory blocks; a plurality of first selection circuits (NG) each coupled to an associated one of said first control word lines, an associated one of said first block control lines and an associated one of said normal segment word lines, each of said first selection circuits selecting the associated normal segment word line when both of the associated first control word line and the associated first block control line take an active level; a plurality of second selection circuits (RG) provided correspondingly to said memory blocks, each of said second selection circuits being coupled to said second control word line, an associated one of said second block control lines and said redundant segment word line of an associated one of said memory blocks and selecting said redundant segment word line of the associated memory block when both of said second control word line and the associated second block control line take an active level; and a control circuit (21, BD) coupled to said first and second block control lines for activating one of said first block control lines while deactivating all of said second block control lines when said second control word line takes an inactive level and for activating one of said second block control lines while deactivating all of said first block control lines when said second control word line takes said active level. The memory device according to claim 1, in which each of said memory blocks (10-1 to 10-k) includes a plurality of bit lines arranged (BL1, BL1 to BLj, BLj ) in columns, a block data line (BDL1, BDLK); and a plurality of transfer gates (QY11,QY12 - QYj1,QYj2) coupled between said bit lines and said block data line. The memory device according to claim 1, in which each of said first and second selection circuits includes a NOR gate. The memory device according to claim 1, in which each of said first and second selection circuits includes a NAND gate. The memory device according to claim 1, in which said selection circuit includes a plurality of block decoders (BD-1 to BD3) each provided for one of said memory blocks, and a detection circuit (21) for detecting the activation of said at least one second control word line, each of said block decoders including a multi-input first gate (22) receiving a part (AC1) of column address signals, a second gate (23) receiving the outputs of said detection circuit and said first gate for generating the first block control signal.

Inventors: KONDO KENJI, KONDO, KENJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1988
Main classification: G06F11
IPC codes: G11C29, G11C11