Ferroelectric retention method

Abstract: Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

Description: This invention relates to ferroelectric materials, and particularly to a method to improve the data retention properties of such materials. Ferroelectric materials are dielectrics which can be used in memory circuits. One physical property useful in this regard relates to a hysteresis curve concerning the applied field and the polarization of the ferroelectric material. As described in U.S. Patent 3,728,694, for example, a capacitor can be formed having a ferroelectric material between the electrodes to serve as the dielectric. Because of the hysteresis curve, when an applied voltage is removed, the polarization of the ferroelectric material will be in one of two distinct states. These states can be determined in various fashions, typically by applying a pulse and determining the amount of current passing through the capacitor. Data retention refers to maintaining the physical phenomenon or property by which binary data is stored, such as ferroelectric polarization, without applied voltage. While ferroelectric materials are useful in non-volatile memory, it is desirable and important that the non-volatile memory be able to maintain the data stored therein for long periods of time, such as years. That is to say, the objective with a ferroelectric, non-volatile memory is to keep the dipoles oriented properly, without changing direction. This has been a problem in using ferroelectric materials. Consequently, an important object of this invention is to provide a way to preserve the polarization of ferroelectric materials after it has been set, without providing further power to the material, i.e. by an applied voltage. Another problem with ferroelectric materials relates to dipole relaxation. If the material has been in one of its two different polarization states for a relatively long time, one nevertheless wants to be able to change the polarization with a relatively short voltage pulse. For example, if a capacitor using ferroelectric material as dielectric has been in one state for a relatively long time, such as one year, and then a 100 nanosecond pulse is applied to the capacitor plates in such a direction as to change the orientation of the dipoles, then after the pulse is terminated, the dipoles may relax back to the original orientation. Problems of this nature are greater when the ferroelectric material is in a relatively thin film of below about one micron. Therefore, a further object of this invention is to provide a way to overcome the relaxation problem of ferroelectric materials. Reference is made to EP-A-0293798 which forms part of the state of the art under Article 54(3) of the European Patent Convention and which describes a memory array of ferroelectric capacitors. In EP-A-0293798, an electrode of a ferroelectric capacitor is open circuited after a write pulse applied to said capacitor has terminated. According to the present invention there is provided a method of operating a ferroelectric capacitor having first and second electrodes with a ferroelectric dielectric therebetween to improve data retention therein comprising the steps of: generating a write pulse; coupling said write pulse to said first electrode of said capacitor, thereby applying a write voltage across the ferroelectric material; and open circuiting said first electrode prior to terminating said write pulse, thereby allowing at least a portion of the write voltage to decay through the ferroelectric material. According to a further aspect of the present invention, there is provided a circuit defined by claim 6 for operating a ferroelectric capacitor. Ferroelectric material is used as a dielectric between two conductive plates, thus forming a ferroelectric capacitor. The capacitor is used to store data by using the polarization state of the ferroelectric material, as in EP-A-0293798. However, after the commencement of a write pulse applied to a capacitor plate, an open circuit condition deliberately is created so that from the perspective of the ferroelectric material, a pulse of long duration is being applied. Preferably, the ferroelectric capacitor receives its write pulse through the source-drain path of a field effect transistor (FET). Preferably, the gate electrode of the FET is pulsed so that the gate closes before the drain voltage drops to zero. Other methods can be used to leave a charge on one plate of the capacitor so that it will dissipate mainly through the ferroelectric material. In describing a preferred embodiment of the present invention, reference is made to accompanying drawings wherein: Figure 1 is a schematic diagram useful in explaining the present invention; Figure 2 shows waveforms used in Fig. 1; and Figure 3 represents further waveforms for Fig. 1. We have found that data retention can be improved in ferroelectric materials by providing uniform polarization throughout the ferroelectric material. Deviations which are relatively small compared to the total thickness appear not to cause a great problem, but when the film becomes increasingly thinner, interface effects can present large problems. Thus, if the material is not homogeneous in polarization for a depth of 200 angstroms at each of the interfaces to the electrodes, then this may present no problem if the total thickness of ferroelectric material is 20 microns, but could present a tremendous difficulty if the thickness is below 1000 angstroms. Thus, data retention appears to be a function of polarization uniformity. According to the present invention, this condition of improved data retention is brought about by creating an open circuit during the write operation. This causes charge to move through the ferroelectric material thereby tending to stabilize the polarization. The invention can be practiced with a variety of devices, and one circuit is shown in Figure 1 suitable for such use. Referring to Figure 1, a ferroelectric capacitor 20 has a plate 20 a coupled to a line 22, sometimes called a plate line, which is usually coupled to a reference potential, preferably ground, but which can have non-zero voltage pulses impressed thereon. The other capacitor plate 20 b is coupled to a second line 24, which can be called a bit line, via the source-drain path of a field effect transistor (FET) 26. Illustratively FET 26 is an N-channel device, and so the drain electrode D of FET 26 is coupled to second line 24, whereas the source electrode S of the transistor is coupled to the top electrode of capacitor 20. The gate electrode G is coupled to a third line 28 (sometimes called a word line) which is separately controlled. It will be understood that the present invention does not require the use of N-channel FETS. Other switching devices can be used. Signals for write operations are shown in Figures 2 and 3. In Figure 2, it will be seen that illustratively the voltage on bit line 24 (and thus on drain D) is brought from zero volts to 5 volts for a write pulse 30 of a known duration. When the method of this invention is used in the Figure 1 circuit arrangement, at some time a control pulse 32 is applied on line 28 to the gate electrode G to open the gate between the drain and source. As shown in Figure 2, pulse 32 terminates prior to the trailing edge of pulse 30. It should be noted that this write voltage creates an electric field. When the write voltage is applied in one direction, the ferroelectric material polarizes in one state, and when the opposite voltage is applied, or the field is otherwise reversed, the polarization also changes. Thus, the polarization of the ferroelectric material in the capacitor is the mechanism by which data is stored in a non-volatile fashion. This effect is caused simply by the write voltage or pulse. But beyond that, in the present invention an open circuit condition is established on the top electrode 20 b of ferroelectric capacitor 20. Line 22 is held at zero volts illustratively, as shown in Fig. 2. Capacitor 20 "sees" a 5 volt signal when the gate opens, beginning with the rising edge of pulse 32, but after the gate closes, the 5 volt signal remains at the source electrode S and therefore at the top electrode 20 b of capacitor 20. This voltage, represented as signal 34, will dissipate as shown in Figure 2, moving charge through the ferroelectric material. This charge movement prevents the creation of depolarization fields, and dipole relaxation which leads to ultimate loss of data is thereby dissuaded. Preferably the leakage or charge transport through the ferroelectric material exceeds the leakage through the transistor junction. Thus, by requiring the drain voltage to drop later than the gate voltage drops, this effect can be achieved when "writing" into the ferroelectric capacitor in this direction. Before describing how the ferroelectric is "written" to the opposite direction, a better understanding of the physics should be gained. In particular, it is important to appreciate the existence and manner of controlling the depolarization field in the ferroelectric material. A discussion is now given of the depolarization field and how the open circuit method minimizes or causes the depolarization field not to occur. Inside a ferroelectric material, the dipoles can be presumed initially (with no applied field) to be oriented in a random state. When a switching voltage is applied across the material, the dipoles align in one direction or the other, depending upon the direction of the voltage applied. For a high enough voltage, virtually all of the dipoles inside the ferroelectric will align in one direction. For a lower voltage, perhaps fewer than all of the dipoles will align, but the majority of them should align in one direction. In order to sense the stored information later, a logic one is defined to mean more dipoles are oriented in one direction than the other, and a logic zero is defined to mean more dipoles are oriented in the opposite direction. During the presence of a switching voltage, the dipoles are generally aligned in one direction corresponding to the polarity of the voltage, but when the voltage is removed, some of the dipoles normally relax back in the opposite direction. This is due to depolarization fields caused by lack of appropriate compensation charge. When all the dipoles are oriented or aligned in one direction, the polarization is stable only if there is an equal and opposite compensation charge inside the ferroelectric material to offset that value of polarization. When the polarization is switched by a write pulse, that compensation charge moves much more slowly through the ferroelectric material than the speed with which the dipoles can be realigned by the write pulse. Because of this slow movement of compensation charge, if the write pulse is applied to the ferroelectric material for a long enough period, then during that time, the internal compensation charge can move through the ferroelectric film to become again equal and opposite to the intended dipole polarization. Then when the write pulse ends, the ferroelectric material will be stable, with all of the dipoles aligned in the proper direction to indicate the data stored in the capacitor. But suppose that the write pulse that is applied to the ferroelectric capacitor is very short in duration compared to the amount of time that it takes the compensation charge to move to the position where stability is achieved. The compensation charge is very slow-moving. When the write pulse returns to zero volts, because the compensation charge has not moved adequately, many of those internal dipoles then want to switch back into the previous state. If more than 50% of them switch back, the data is lost. The reason that the compensation charge is slow-moving is twofold. First, the charge resides in the ferroelectric material, and second, the ferroelectric material typically has a high resistance. It therefore takes a long time, as mentioned, to move this compensation charge completely into that area of the ferroelectric film that needs it. According to our invention, even if the data being written into the capacitor is opposite to the former data, the depolarization field caused by compensation charge in its former location does not occur. We allow the write pulse voltage (or a portion of it) to decay naturally - through the natural resistance of the ferroelectric material itself. In order to do that, we switch the write voltage onto the plates of the ferroelectric capacitor and then open that switch (FET) so that the write voltage returns to zero only as fast as the ferroelectric material will allow through its own resistance. It is not necessary to open circuit the entire write voltage. The voltage which must be open circuited to achieve this effect sometimes will be the full supply voltage, but sometimes can be on the order of a few tenths of a volt. The important point is not to bring the write pulse back to zero volts, as in the prior art, but rather to bring it to a voltage sufficient to prevent or minimize the continuance of the depolarization field. The effect of the open circuiting is to allow a polarizing voltage to remain across the ferroelectric material for a long enough period of time such that the resulting field inside the ferroelectric is a polarizing field, which is in a direction so that none of the dipoles want to relax back to the prior state. The polarizing voltage, in the same direction as the write pulse, applies a polarization field which cancels or negates the depolarization field which results if the write pulse is terminated too quickly. As the polarizing charge dissipates, the field which moves the compensation charge is also the same field that dissipates the voltage across the ferroelectric, so the rate at which the compensation charge moves is also the same rate at which the voltage dissipates. For this reason, it is preferred to create a good open circuit thereby to guarantee that the rate at which the compensation charge moves, which is essentially due to the resistance of the ferroelectric, is also the same rate at which the write voltage decays. If those rates are equal, then there can be no depolarization field built up and there can be no relaxation of dipoles. Consequently, it is preferred that the resistance of the ferroelectric material is lower than the resistance on any of the other nodes around the ferroelectric. Typically in an MOS circuit there is a junction. Preferably the leakage of that junction is less than the leakage of the ferroelectric. For example, assume that 5 volts is put across the ferroelectric, and assume also that in order for this invention to work, then 5 volts needs to decay or dissipate itself mostly through the ferroelectric film itself. If there is a lower resistance path somewhere else, for example, in an MOS junction, leakage from that junction may decay the polarizing voltage quicker than the ferroelectric material would. The ideal situation therefore is to have a perfect open circuit so that the discharge path for those electrons would be only through the ferroelectric film itself. However, one can anticipate that there will be a number of parallel leakage paths around the ferroelectric. Those parallel leakage paths should be of a value that is less than that of the ferroelectric so that most of the charge is dissipated through the ferroelectric, and only a small amount of charge is dissipated through the parallel paths. If the resistance of the parallel paths is low enough, such that the voltage across the ferroelectric decayed to zero very quickly, then that in effect is just like bringing the write pulse to zero very quickly, with no open circuit. With the present PZT ferroelectric films in current use, there is little problem in this regard. The leakage of MOS junctions is extremely small, and the leakage of the ferroelectric material appears to be comparable to or greater than the MOS junction leakage. Figure 3 illustrates waveforms when writing the opposite state into the ferroelectric material than the Figure 2 drawings represent. Line 22 goes to 5 volts which is coupled to electrode 20 a of ferroelectric capacitor 20. Bit line 24 remains at zero volts such that the source S of FET 26 will be at zero volts. This would provide 5 volts in the opposite direction as before across the ferroelectric. One way to open circuit this logic state would be simply to turn off FET 26 prior to changing the potential of bit line 24. However, in a commercial memory circuit, line 22 would generally be coupled to other similar lines 22. This coupling effectively precludes maintaining a given line 22 at 5 volts. So, another circuit approach can be used to return plate line 22 to zero volts and still have the logic state open circuited. One way in which to achieve this is to put a substrate bias on the chip, such that the source S in Fig. 1 can be driven below ground. If the bit line 24 is at zero volts and the gate G of FET 26 is also at zero volts, then the voltage at the source S can be below ground by one threshold voltage, typically one volt. When plate line 22 drops from 5 volts to zero volts, electrode 20 b of the ferroelectric capacitor 20 will drop from zero volts to about minus one threshold voltage or about minus one volt. That voltage is still in a polarizing direction, and should be permitted to dissipate mainly through the ferroelectric material. Another approach uses two ferroelectric capacitors per memory cell, as described with respect to Figure 4 in U.S. Patent No. 4,873,664 of S. Eaton, Jr. entitled "Self-Restoring Ferroelectric Memory," filed February 12, 1987 (RAM 302). In that case we need to open circuit only one logic state because with two complementary ferroelectric capacitors per bit, one or the other of those capacitors will always be written in a condition which can be open circuited in the manner first described above, i.e. where 5 volts is coupled to the top plate of the capacitor 20, and then line 22 is grounded. One of the two capacitors in this alternate embodiment would always have that condition, and one of those two capacitors could always be open circuited effectively. It will be appreciated that modifications within the scope of this invention, defined by the claims, can be made, and that this description is to be taken as illustrative.

Claims: A method of operating a ferroelectric capacitor having first and second electrodes (20a, 20b) with a ferroelectric dielectric therebetween to improve data retention therein comprising the steps of: generating a write pulse; coupling said write pulse to said first electrode (20b) of said capacitor, thereby applying a write voltage across the ferroelectric material; and open circuiting said first electrode prior to terminating said write pulse, thereby allowing at least a portion of the write voltage to decay through the ferroelectric material. A method according to claim 1 wherein said open circuiting step is controlled to disconnect said first electrode so as to leave at least a portion of said write voltage on said first electrode. A method according to claim 1 or 2 including, after the step of applying said write pulse to said first electrode, dropping the voltage of said write pulse; then open circuiting said first electrode before the voltage of said write pulse reaches zero volts. A method according to claim 1, 2 or 3 comprising the steps of: coupling said write pulse to said first electrode via a switching device (26) coupled to said first electrode; and disconnecting the write pulse from said first electrode by opening said switching device prior to terminating said write pulse. A method according to claim 4 wherein said switching device comprises a transistor having a control electrode and operating selectively to apply high or low impedances along a path in response to voltage applied to said control electrode, said path coupling said first electrode to a voltage source, and wherein said open-circuiting step comprises operating said transistor to interpose a high impedance between said first electrode and said voltage source. A circuit for operating a ferroelectric capacitor in accordance with the method of any of claims 1 to 5 to improve data retention therein, the circuit comprising: means for generating a write pulse; means for coupling said write pulse to a first electrode (20b) of said capacitor (20), thereby to apply a write voltage across ferroelectric material of the capacitor, said coupling means comprising a switching device (26) comprising a transistor having a control electrode and operating selectively to apply high or low impedances along a path in response to voltage applied to said control electrode, said path coupling said first electrode to a voltage source, said transistor being operable to interpose a high impedance between said first electrode and said voltage source thereby to open circuit said first electrode prior to terminating said write pulse.

Inventors: BUTLER DOUGLAS, EATON SHEFFIELD S JR, PARRIS MICHAEL, BUTLER, DOUGLAS, EATON, SHEFFIELD S., JR., PARRIS, MICHAEL
Applicants: RAMTRON INT CORP, RAMTRON INTERNATIONAL CORPORATION
Application year: 1988
Main classification: G11C11
IPC codes: H01L27, G11C11, H01L21, G11C14, H01L29