Integrated transistor and manufacturing process therefor

Abstract: A transistor has a base region in a column (42) of selectively grown epitaxial silicon isolated from adjacent structures in a field of oxide. A layer of doped polysilicon which is embedded in the insulating material surrounding the column of epitaxial silicon forms a sidewall base contact. The collector contact is formed of another column (38) of selectively grown epitaxial silicon grown over and in electrical contact with a buried layer (34) underlying the first column of epitaxial silicon. The emitter region (56) is implanted into the top of column doped as the base region. The base contact can be a buried polysilicon layer or epitaxial silicon which is grown over oxide by uncontrolled growth following controlled selective growth. The transistor can be made by forming a layer of oxide, etching two holes in it and growing the epitaxial silicon in the holes. Thereafter, in one embodiment, the oxide is etched back to expose the sidewalls of the columns and polysilicon is deposited, doped and etched to form the sidewall base contacts. In another embodiment, the base contact is formed by allowing the selectively grown epitaxial silicon to grow laterally out over the top of the oxide layer in the columns of epi are grown. The structure is then planarized, the emitter region is formed, and the contact holes are etched and contacts are formed.

Description: The invention pertains to the field of integrated bipolar transistor construction, and, more particularly, to the field of bipolar transistors which have a base area with reduced size and the concomitant reduction in the parasitic capacitances and resistance. Workers in the art of integrated bipolar transistor design have long known that a reduced base area is desirable for several reasons. First, transistors with reduced base area have less parasitic junction capacitance associated with the base-collector junction because there is less area of the junction and the parasitic capacitance of this junction is proportional to the area of the junction. Second, the smaller base area means the overall size of the transistor is reduced, and, therefore, more transistors may be put on a single die. Smaller parasitic capacitances coupled to the base means faster switching operation for such transistors. Since computers typically employ millions of switching transistors and perform millions of operations involving switching by these transistor every second, faster switching transistors mean that more operations per second may be performed. This translates to faster data processing and more output per unit of time. Smaller transistors means more functions may be put on a single integrated circuit die. This translates into cost savings because fewer connections need be formed by soldering because fewer integrated circuits are used to accomplish any given function. Thus, smaller transistors means lower cost electronic products. Further, reliability of such products is increased because a connection made internally on an integrated circuit is far more reliable than a soldered connection made in the external world. The problem with prior art bipolar transistors is that the base area can only be made as small as the minimum linewidth, D, permits. The minimum linewidth, as those skilled in the art appreciate, defines the size of the smallest geometric feature which may be formed on the surface of an integrated circuit for a given photolithography system. In the prior art, the base area surrounds the emitter region. The base area needs at least one electrical contact formed thereon, and since the minimum dimension on each side of the emitter region is one D. Since the design rules require a certain clearance around the emitter which the base contact may not encroach upon, and since the base contact must be at least one D wide, the minimum size of the base area may not be smaller than the above criteria permit. Thus, the performance levels of prior art transistors have been limited, and improvements, at least in part, have been linked to reductions in minimum obtainable linewidth. Thus, a need has long existed for an improved bipolar transistor with a smaller base area than is possible with conventional construction. There is known from EP 0 189 136 A2 a bipolar semiconductor device or transistor of the kind comprising a buried layer of a first conductivity type in a substrate, first and second columns of epitaxial mono-crystalline silicon on the buried layer, a first insulating layer of silicon dioxide on the buried layer and surrounding the first and second columns, a conducting layer on the first insulating layer and laterally contacting an upper portion of the first epitaxial column, the upper portion being of a second conductivity type, and a region of the first conductivity type formed at the top of the first epitaxial column, the buried layer, the upper portion and the region respectively forming portions of a collector, a base and an emitter of the bipolar transistor. In contrast, the present invention provides a bipolar transistor of this kind in which the conducting layer is a portion of the first epitaxial column. The invention also provides a process of forming a bipolar transistor of the kind comprising the steps of forming in a substrate a buried layer of the first conductivity type, forming a first insulating layer of silicon dioxide on the buried layer, forming first and second openings in the first insulating layer exposing the buried layer, forming first and second columns of epitaxial mono-crystalline silicon in the first and second openings, respectively, on the buried layer, forming a conducting layer on the first insulating layer and laterally contacting an upper portion of the first epitaxial column, the upper portion being of a second conductivity type, and forming a region of the first conductivity type formed at the top of the first epitaxial column, the buried layer, the upper portion and the region respectively forming portions of a collector, a base and an emitter of the bipolar transistor. In accordance with the invention, the conducting layer is formed by lateral spread of the epitaxial mono-crystalline silicon of the first column over the first insulating layer. There is also known from US-A-3 600 651 a bipolar transistor device in which a single crystalline layer on a semi-conductor substrate provides the active regions of the device. Lateral contacts to the active regions are provided by adjacent polycrystalline layers. Thus, in accordance with the invention, a sidewall contact transistor is made by use of controlled lateral growth of epitaxial silicon over the top of an insulating layer of oxide. The epitaxial silicon is selectively grown in holes in an oxide layer cut down to a buried layer in an underlying substrate. When the epitaxial silicon growth reaches the surface of the oxide, the reaction conditions are changed so that non-selective growth occurs so that the epitaxial silicon grows out over the oxide layer covering the buried layer by 1 or 2 micrometers (microns). These extensions of epitaxial silicon are covered with silicide as are polysilicon contacts covering the epitaxial silicon and metal contacts are then formed in contact windows which are cut over the emitter and collector polysilicon contacts and over the lateral extensions of the epitaxial silicon serving as the base contact. The process of forming the controlled lateral growth embodiment is as follows. 1. Form a buried layer in a p⁻ substrate for NPN. 2. Form a layer of oxide overlying the buried layer. 3. Form two holes in the oxide overlying the buried layer and selectively grow epitaxial silicon in the holes. A. When the selective growth reaches the top of the oxide layer (400 to 800 nm.) (4000 to 8000 angstroms thick), change the reaction conditions by altering the amount of HCl vapor present to create non-selective growth of epitaxial silicon out over the oxide. 4. Implant the column of epitaxial silicon to be the base with P type impurities (N type if PNP devices are to be formed. 5. Implant the column of epitaxial silicon to be the collector with N type impurities. 6. Deposit a layer of polysilicon over the entire structure, dope it N type and etch the emitter and collector contacts. 7. Using the photoresist mask used to define the polysilicon contacts and the polysilicon so etched as a mask, implant the lateral extensions of the epitaxial silicon with P type impurities. 8. Heat treat the structure at a temperature and for a time sufficient to drive N type impurities out of the emitter polysilicon contact into the base epitaxial silicon so as to form an emitter region. 9. Form a layer of oxide or nitride insulating material over the entire structure by chemical vapor deposition and anisotropically etch the oxide to form insulating shoulders around the outside edges of the polysilicon contacts. 10. Form a layer of silicide over the exposed surfaces of the polysilicon contacts and the exposed surfaces of the lateral extensions of the epitaxial silicon. 11. Form a planarized layer of insulating material over the structure and etch contact holes therein over the emitter, collector and base contacts. 12. Form conductive contacts in said contact holes. The invention is further described below, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a cross sectional view of sidewall contact transistor which does not form part of the present invention. Figure 2 is a plan view of the transistor of Figure 1 looking straight down along the y axis from above the emitter contact, Figure 3 is a cross sectional view of the transistor of Figure 1 at an early stage in the process after the buried layer has been formed, Figure 4 shows the transistor structure after a layer of grown and deposited oxide is formed and holes have been etched therein in which selectively grown epitaxial silicon is grown and during an N type implant to convert the collector column to N type, Figure 5 shows the transistor structure after the epitaxial single crystal silicon has been selectively grown in the holes and after the oxide layer has been etched back to expose the top portions of each column, Figure 6 is a view of the transistor structure after the polysilicon layer from which the sidewall base contact will be formed is deposited, Figure 7 is a view of the transistor after a layer of nitride or oxide and a layer of photoresist have been deposited over the doped polysilicon layer, Figure 8 shows the transistor structure after etchback of the photoresist to expose the tops of the epitaxial silicon columns, Figure 9 shows the P type base implant which is used to dope the base region and the base sidewall contact polysilicon to the proper conductivity level, Figure 10 shows the structure in cross section after a planarization step has been performed to add an insulating layer over the top of the polysilicon layer and after the protective oxide layer has been formed and etched, Figure 11 shows the finished transistor structure after the metal contacts used in the preferred embodiment of the method have been formed, Figure 12 shows a refractory metal-silicide contact structure, Figure 13 shows another type of contact structure which may be employed in the transistor of the invention using polysilicon and silicide, Figure 14 shows the structure of an embodiment of the invention during a base implant step, Figures 15A and 15B show the relationships between reaction condition for selective and non selective growth for various HCl flow rates, Figure 16 shows the structure of the device during the N type sink implant to dope the collector region, Figure 17 shows the structure after the emitter and collector polysilicon contacts have been doped and etched and during an implant of lateral epitaxial silicon, Figure 18 shows the structure during the steps of forming the insulating oxide spacers, Figure 19 shows the structure of the device after the silicide layers have been formed, Figure 20 shows a cross section of the completed device, and Figure 21 shows a top view of the completed device. Figure 1 is a cross sectional view of the sidewall contact transistor. The transistor shown is an NPN device, but the method of making it work also for PNP type devices. The transistor is formed on a P- type substrate 30 having a conventional doping level. At the surface 32 of the substrate there is formed a heavily doped N+ type buried layer 34. This buried layer serves the conventional purpose of reducing the collector contact resistance along the path from a collector contact 36, through an N type selectively grown column of single crystal silicon 38, and the buried layer 34 to the base-collector junction 40. A base region 42 is formed of P type selectively grown epitaxial single crystal silicon. Both columns of selectively grown epitaxial single crystal silicon 38 and 42 are grown in holes etched in a field of grown and deposited silicon dioxide 44 underlying a field of deposited PVX glass 46. The manner in which this is done will become clear from the discussion below giving the method of manufacture of the device. At the intersection of the PVX glass 46 and the oxide 44 there is formed a sidewall base contact 48 around the selectively grown epitaxial single crystal silicon column 42 only. The base contact is formed of P doped polysilicon, and is coupled to a highly conductive base contact 50. The base contact may be metal, silicide, heavily doped polysilicon or some other highly conductive material as will be understood by those skilled in the art. The base contact 50 overlaps the edges of a base contact window 52 by an alignment tolerance distance. The base contact polysilicon 48 extends laterally in the x direction far enough that the contact hole 52 having at least the minimum linewidth dimension plus an alignment tolerance for the overlap of the base contact 50 plus an alignment tolerance defined by the design rules for the spacing between the base contact 50 and an emitter contact 54 may be maintained. An emitter region 56 of N+ doped selectively grown epitaxial single crystal silicon is formed at the top of the column 42. Overlying the emitter region 56 is the emitter contact 54. It may be made of the same material as the base contact. The same is true for the collector contact 36. Figure 2 is a plan view of the transistor of Figure 1 looking straight down along the y axis from above the emitter contact. The relative sizes of the base contact 50, the emitter contact 54 and the collector contact 36 and the spacing between these contacts is exemplary only. Those skilled in the art will appreciate that any of these factors may be changed to suit individual user process parameters. The Process of Manufacture Figure 3 is a cross sectional view of the transistor of Figure 1 at an early stage in the process after the buried layer has been formed. The stage of Figure 3 is reached by conventional methods of forming the buried layer 34. Starting with a P- substrate doped to about 5 x 10 to the 14th power impurity atoms per square centimeter, a layer of photoresist is deposited and developed to expose the portion of the substrate 30 where the buried layer 34 is to be formed. An N type implant is then performed to dope the exposed portion of the substrate N+ in conductivity to form the buried layer 34. Next, a layer of oxide (0.3 micrometers (microns) thick) is grown on the wafer and a layer of photoresist (not shown) is deposited, masked, and developed to expose small channel stopper regions 60 and 62 (they are actually part of a ring surrounding the entire buried layer 34). After the holes for the channel stoppers 60 and 62 are formed in the photoresist, a heavy dose of P type impurities is implanted or diffused into the substrate at the locations 60 and 62 to form the channel stoppers. The doping levels and implant energies if the channel stoppers are implanted are well known in the art. The ultimate conductivity desired for these channel stoppers is usually around 5 x 10 to the 16th power to 5 x 10 to the 17th power. The doping of the substrate 30 should be kept as low as possible to minimize the collector to substrate capacitance. Figure 4 shows the transistor structure after a layer of grown and deposited oxide is formed and holes have been etched therein in which selectively grown epitaxial silicon is grown and during an N type implant to convert the collector column to N type. After the buried layer has been formed, the photoresist layer 64 is removed, and a layer of silicon dioxide 66 (hereafter sometimes referred to as oxide) is formed. This layer 66 is formed by thermally growing a first layer of oxide, and then depositing another layer of oxide on top of the first layer by chemical vapor deposition, low pressure chemical vapor deposition or some other technique. The manner of depositing oxide is well known to those skilled in the art. In alternative embodiments, the deposited oxide layer may be eliminated and the thermally grown oxide layer may be grown to the desired thickness. The thickness of the composite layer of oxide is determined by the desired base width (dimension in the y axis) of the base region. Generally, the desired thickness of the composite oxide layer is about 0.5 to 2 micrometers (microns), but other thicknesses will work for some applications. Those skilled in the art appreciate that the base width is critical to the performance of the transistor, and is an important parameter in determining the gain and high frequency cutoff/switching speed of the transistor. Thus, the thickness of the oxide layer 66 should be chosen according to the desired base width and balanced with the other parameters of the process such as the implant energy for the emitter formation step to get the desired transistor characteristics. The first layer of oxide is to provide good electrical integrity for the insulation layer since thermally grown oxide has fewer pin holes than deposited oxide. In the preferred embodiment, the first layer of thermal oxide is grown to a thickness of 100 nm. (1000 angstroms). The composite layer of oxide 66 will serve as the field oxide in which the individual transistors are isolated from one another. After the layer of oxide 66 is formed, two holes 68 and 70 are etched therein. These holes essentially will act as the isolation islands for the base-emitter junction and the collector contact when they are later filled with selectively grown epitaxial single crystal silicon. In the preferred embodiment, these holes are formed by anisotropic, reactive ion etching ("plasma etching") so that the walls are vertical. Single layer or multiple layer resist may be used to define the location of the holes 68 and 70. Wet etching may also be used, but this is not preferred because wet etching is generally isotropic and laterally etches while vertical etching is occurring. Because it is generally desirable to keep the emitter junction at the smallest possible area to minimize the parasitic junction capacitances which afflict the transistor, it is desirable to make the hole 68 one D plus two times the alignment tolerance of D/4 on a side. The same is true for the hole 70, except, for the collector contact, the reason for minimizing the size of the hole is to save space since the base collector junction 40 is in the other column of silicon formed in hole 68. Thus wet etching is not preferred because the walls will not be vertical and the size of the resulting hole will not be as well controlled. The single crystal silicon columns 42 and 38 are grown using a known process using a conventional low pressure epitaxial growth reactor. The selective deposition of the epitaxial single crystal silicon occurs when dichlorosilane mixed with hydrogen is caused to flow through the reactor with hydrochloric acid vapor present. This process is described in an article by John O. Borland and Clifford I. Drowley, entitled "Advanced Dielectric Isolation Through Selective Epitaxial Growth Techniques", Solid State Technology, August 1985, pp. 141-148. Other articles describing the process include: Jastrzebski, "Silicon CVD for SOI: Principles and Possible Applications", Solid State Technology, September 1984, pp. 239-243; Jastrzebski, "Device Characterization on Monocrystalline Silicon Grown Over SiO2 by ELO (Epitaxial Lateral Overgrowth) Process", IEEE Electron Device Letters, Vol. EDL-4, No. 2, February 1983; and Jastrzebski et. al, "Growth Process of Silicon Over SiO2 by CVD: Epitaxial Lateral Overgrowth Technique", J. Electrochem. Soc.: Solid State Science and Technology, July 1983, Vol 130, No. 7, pp. 1571-1580. All of these articles are hereby incorporated by reference. In the article from Solid State Technology from August 1985, the authors teach use of a P type substrate having <100> crystal orientation and a resistivity of from 15 to 25 ohm-centimeters. A two micron oxide layer was grown on the substrate and a tri-layer resist mask process was used to provide vertical resist sidewalls with an anisotropic etch in plasma to attain near vertical sidewalls. Selective epitaxial growth was then performed under a wide range of conditions in a radiantly heated barrel reactor. SiH2Cl2 was used as the silicon source gas. It was found that temperatures of deposition from 1100 to 826°C. (degrees centrigrade) worked at pressures ranging from atmospheric down to 2′666 Pa. (20 torr). It was also found that the amount of HCl required for good selectivity decreased as the deposition temperature decreased. In the preferred embodiment a deposition temperature of 1000°C. (degrees centigrade) and a pressure of 5′998.5 Pa. (45 torr) was used. Generally, a deposition pressure of from 3′332.5-10,664 Pa. (25-80 torr) is preferred. After the selective growth of the epitaxial silicon in the holes 68 and 70, the wafer is heated at 800 to 1000°C. (degrees centigrade) for 30 minutes in dry oxygen to eliminate "sidewall leakage", i.e., leakage or conduction along the interface between the homoepitaxy and the field oxide. Next, a layer of photoresist 69 is put on the wafer to mask off the epi in the hole 68. Then an N type implant is performed to dope the epi in the collector column N+. The energy of this implant should be such as to cause the N type dopants to reach the buried layer 34 or to get close enough that the N type dopants will reach the buried layer later in the process during high temperature steps. Figure 5 shows the transistor structure after the epitaxial single crystal silicon has been selectively grown in the holes and after the oxide layer has been etched back to expose the top portions of each column. After the epitaxial silicon 42 and 38 is grown, the oxide layer 66 is etched back to expose the sidewalls of the epitaxial silicon. This etch is a conventional wet etch using hydrofluoric acid diluted with water. Other well known non selective etch processes may also be used which do not attack epitaxial silicon. The purpose of this etch is to expose the sides of the columns so that the sidewall base contact may be formed. The thickness of the exposed column after the etch is .2 to .5 micrometers. Figure 6 is a view of the transistor structure after the polysilicon layer from which the sidewall base contact will be formed is deposited. The polysilicon layer is conventionally deposited using low pressure chemical vapor deposition. The thickness of the polysilicon layer 70 is less than the height of the exposed column of silicon (.15 to .3 micrometers). The thickness of the polysilicon layer 70 should be sufficient so as to not unduly increase the base series resistance of the contact structure. Figure 6 also shows a P type implant to convert the polysilicon layer 70 to P type conductivity. The polysilicon layer should be doped to an impurity level of approximately 10¹⁵ atoms per square centimeter (implant dose level). The implant energy should be about 20 to 60 KEV, but the energy level should not be substantially higher than this range lest the implant impurities pass completely through the polysilicon and enter the region which is later to be converted to the emitter region. Figure 7 is a view of the transistor after a layer of nitride or oxide and a layer of photoresist have been deposited over the doped polysilicon layer. A protective layer 72 of some material must be deposited over the polysilicon layer 70 to prevent any impurities in the photoresist from entering the polysilicon layer 70 and altering the characteristics of the transistor. In the preferred embodiment, this protective layer 72 is nitride, but in alternative embodiments, the protective layer 72 may be silicon dioxide. After the protective layer 72 is deposited or otherwise formed, a layer of photoresist 74 is spun on over the protective layer 72 to planarize the structure. Any planarization technique will work at this point in the process. Several such processes are known. Any of them which can form a substantially planar surface 76 will suffice for purposes of practicing the invention. In the preferred embodiment, the planarization is carried out by spinning on a first layer of photoresist or TEOS 74. This layer is then baked to drive off the solvents. Next, part of the layer 74 is etched away, and another layer of photoresist or TEOS is spun on and baked to drive off the solvents. Figure 8 shows the transistor structure after etchback of the photoresist to expose the tops of the epitaxial silicon columns. An isotropic ion etch is used for this step such that photoresist, nitride and polysilicon may all be etched at the same rate. Such an etch is conventional using CHF3 gas, but any etch which can etch photoresist, nitride and polysilicon at the same rate will suffice for purposes of practicing the invention. The etch should be stopped when the top surface of the epitaxial columns is exposed. In alternative embodiments, this etchback step may be two etch steps. The first etch will remove the photoresist until the top of the nitride is exposed. Then a different etchant may be used to remove the nitride and polysilicon to expose the tops of the epitaxial silicon. The etch step or steps should be timed such that the etching is stopped when the tops of the columns of epitaxial silicon are exposed without the etch step removing substantial amounts of the epitaxial silicon columns. Control of the etching to within plus or minus 1000 angstroms will be adequate at this point in the process, because the emitter and base structures have not yet been formed. Thus there is less need to precisely control the etching rate and time. The reason that the foregoing steps of putting on the protective layer and photoresist and etching back to expose the tops of the epitaxial silicon columns are performed is to get the polysilicon off the tops of the columns after forming the sidewall base contacts. Any process which can get the polysilicon from the layer 70 off the tops of the columns of epitaxial silicon 42 and 38 without removing the polysilicon from the sides of the epitaxial silicon will suffice for purposes of practicing the invention. The reason the photoresist layer is needed in the preferred embodiment of the process is because of its property to form a thinner layer of material on the top of projecting portions of the topography than on flat portions. Polysilicon, on the other hand deposits in a manner which conforms to the topography such that, roughly speaking, the polysilicon that forms over the projecting portions of the epitaxial silicon columns 42 and 38 forms at approximately the same thickness on the tops and on the sides. Thus, if an attempt was made to etch the polysilicon off the top of the columns 42 and 38 without the use of the photoresist layer 74, the isotropic etch would remove the polysilicon from the sides of the columns 42 and 38 at the same rate as it was removed from the top. The result would be that by the time all the polysilicon was removed from the tops of the columns 42 and 38, it would also have been removed from the sides. Thus no polysilicon would remain in contact with the sides of the epitaxial silicon columns from which the sidewall contacts could be formed. Because the photoresist forms a thicker layer over the polysilicon contacting the sides of the columns 42 and 38 than over the polysilicon in contact with the tops of the columns, the etch reaches the top of the columns 42 and 38 before it removes all the polysilicon in contact with the sides of the columns 42 and 38. Any other method which accomplishes this function will suffice so long as it is otherwise compatible with the process and the structure being formed. Figure 9 shows the P type base implant which is used to dope the base region and the base sidewall contact polysilicon to the proper conductivity level. Before this base doping implant, the remaining photoresist and protective layer 72 left over from the steps of Figure 8 are removed. There is no need to form a protective photoresist layer over the collector epi 38, because the dosage level of the base doping implant is not so heavy as to significantly change the heavy N+ doping of the collector epi. The additional P type impurities entering the P+ polysilicon will improve its conductivity. In alternative embodiments, the P type base implant of the base epi 42 may be performed before the remaining photoresist 74 and the remaining protective layer 72 are removed. The base implant is performed at 15 to 40 KEV in the preferred embodiment with a dosage level of approximately 5 to 20 x 10¹² atoms per square centimeter. The reason this relatively low energy and light doping is used is to maintain good control over the base width. It is important for the high frequency performance of the transistor to maintain a shallow base width. Further the doping should be light to minimize the base-emitter and base-collector junction capacitances which slow down switching of the transistor. However, the doping should not be so light and the base width so narrow as to adversely affect the reverse bias breakdown voltage. This causes increased probability of punch through which could ruin the transistor. Those skilled in the art will appreciate how the base width may be controlled precisely using the implant energy and dosage level. Higher doping levels or higher energy will result in greater base width and a lower high frequency cutoff point. The doping level of the base also affects the current gain beta of the transistor. After the base epi 42 is doped P type, a new layer of photoresist (not shown) is deposited and developed to define the sidewall base contacts in the polysilicon layer 70. This photoresist pattern will prevent the portion of the polysilicon layer 70 which will be the sidewall base contact from being etched away. This pattern includes the base sidewall contacts, and can include resistors in the polysilicon layer 70 and interconnections between the bases of various transistors in a circuit being formed and other nodes or elements in the circuit. Either before or after the etch of the polysilicon, a thin layer of oxide 71 is grown over the exposed polysilicon 70 and epitaxial silicon 42 and 38. The purpose of this thin layer of oxide is to prevent a base emitter short from occurring. Because the etchback step of Figure 8 leaves the polysilicon layer 70 even with the top of the epitaxial silicon columns 42 and 38, there would be a possibility of a short between the emitter contact when it is later formed and the sidewall base contact. The oxide layer 71 prevents this short from occurring. In alternative embodiments, some other method of preventing this possible short from occurring may be used. Any method which prevents the short will suffice. The etchback of the polysilicon layer 70 also leaves small sections of the polysilicon layer 70 surrounding the collector contact 38 as seen in Figures 10 and 11. The layer of oxide 71 also forms on top of these layers. These polysilicon shoulders are irrelevant to the invention in that they are not necessary to the functioning of the device. Figure 10 shows the structure in cross section after a planarization step has been performed to add an insulating layer over the top of the polysilicon layer and after the protective oxide layer has been formed and etched. In the preferred embodiment, a layer of PVX II glass 78 is deposited over the entire structure and reflowed at a temperature of between 800 to 1000 degrees centigrade to planarize the topography of the wafer. This reflow step also has the effect of annealing any damage caused by the base implant. PVX II is a well known material in the prior art. Typically, PVX II is deposited using low pressure chemical vapor deposition at approximately 400 to 450 degrees centigrade. Other planarization methods and compositions will work equally well. Such planarization methods and compositions include but are not limited to the disclosure of U.S. patent application entitled "German silicate Spin-On Glasses", serial number 747,470, filed June 21, 1985 by Bill Lehrer which is hereby incorporated by reference. The planarization step represented by Figure 10 may be omitted in some embodiments, but its presence is preferred because it reduces step coverage problems with later metallization layers. Further, flat surfaces give better linewidth control in photolithography systems than do surfaces with topographical variations in the distance of points on the surface from the lens of the optical system used to project the image of the mask. The temperature of the reflow step is not critical to the invention. The base implant anneal step and the reflow step may be combined into one heat step. In alternative embodiments, these two heat steps may performed separately. If spin on TEOS is used for planarization, a separate anneal heat step must be used to repair the damage from the base implant because the TEOS bake to drive off the solvents is not of a high enough temperature to anneal implant damage. This anneal step is typically performed at 900 to 950 degrees centigrade. Alternatively, a layer of oxide may be deposited by CVD and planarized by a suitable method. After the planarized insulating layer is deposited, it is etched back using a plasma etch until the top of the silicon dioxide layer 71 is exposed. The etch time should be controlled so that there remains some insulating material over the top of the resistors and sidewall base contacts in the poly layer 70 and over the epi columns 42 and 38, but the timing is not otherwise critical. Some insulating material in the layer 71 must be maintained after the etchback step to prevent a short between the base contact polysilicon and the emitter when the emitter contact metal 84 is deposited as shown in Figure 11. Figure 10 also shows an N type emitter forming implant step. Before this implant may be performed, a window must be cut in the protective oxide layer 71 which lies over the tops of the epitaxial silicon columns 42 and 38. To form these windows, an etch mask of photoresist (not shown) is deposited and developed so as to expose for etching two windows. These windows in the photoresist lie within the perimeters of the tops of the epitaxial silicon columns 42 and 38. To maintain high yield, these windows should be aligned so that protective oxide 71 always remains over the edges of the polysilicon layer 70 in contact with the edges of the epitaxial silicon 42 and 38. Accordingly, the dimensions of the epitaxial silicon layer 42 and 38 should be large enough to insure the ability to accurately align the etch mask for the oxide layer 71 to meet the above criteria. In alternative embodiments, the implant shown in Figure 10 (or the alternative emitter region formation step described below) may be done after the step of forming the PVX II layer 78 shown in Figure 11 and after the contact windows are cut therein for the emitter and collector contacts. In this alternative embodiment, the emitter implant impurities must not go through the base contact window which will be exposed when the base contact and emitter contact windows are etched in the PVX II layer 78. Thus, some method of blocking the implant from passing through the base contact hole in which the contact 80 is formed must be used. There are two ways at least of forming the emitter region 56 in the base epitaxial silicon column 42. The first way is by way of an implant of N type impurities. The dosage of this emitter implant is approximately 5 x 10¹⁵, and the implant energy is approximately 60 to 80 KEV. In alternative embodiments, the emitter 56 may be formed by depositing a layer of N doped polysilicon (not shown) over the column 42 of epitaxial silicon. The dopants are then driven into the epitaxial silicon by a heat step. The timing of the diffusion should be controlled to get the desired emitter depth from the top surface of the column 42 down along the y axis into the epitaxial silicon. For a deposited poly emitter formation method, the polysilicon should be doped N+ to about 1 x 10¹⁶ atoms per square centimeter. The thermal drive in step is then performed at approximately 900 to 950°C. (degrees centigrade) for 10 to 30 minutes. Then the poly is etched off except for the location over the emitter region 56 and over the collector column 38 of epitaxial silicon thereby forming the emitter contact and the collector contact. If desired, the poly layer may also be left intact at the locations of any resistors or conductor lines which are desired at the level in the circuit above the planarized PVX II layer 78. This alternative embodiment has the added advantage that the emitter and collector contacts are formed without a separate step being needed to deposit some conductive material over the columns 42 and 38. Figure 11 shows the finished transistor structure after the metal contacts used in the preferred embodiment of the method have been formed. To form the metal contacts, a layer of aluminum or some other metal is deposited over the wafer. Then a layer of photoresist is deposited and developed to form an etch mask for the metal layer. Thereafter, the metal layer is etched to form the resistor contact 80, the base contact 82, the emitter contact 84 and the collector contact 86. In alternative embodiments, the layer of metal deposited to make the contacts may be a refractory metal and a heat treatment may be conducted either before or after etching of the metal to convert any metal in contact with epitaxial silicon or poly to silicide at least partially. This has the added advantage of preventing any metal spiking which might cause the base-emitter junction to be shorted. Figure 12 shows a refractory metal-silicide contact structure. Figure 13 shows another type of contact structure which may be employed in the transistor of the invention using polysilicon and silicide. This type of contact may be employed where the polysilicon and drive in method is used to form the emitter region 56. To form the contact structure of Figure 13, the polysilicon contacts are first formed, and then a layer of refractory metal is deposited over the entire wafer. A heat treatment then is used to convert the refractory metal in contact with the polysilicon to silicide. Any refractory metal in contact with oxide or some other insulator will not be converted to silicide, and may be selectively etched away to leave the structure shown in Figure 13. In the illustrated embodiment of the invention a controlled lateral growth or spread of the selectively grown epitaxial layer over the top of an oxide layer is used as a sidewall base contact. The process to make this device starts out the same as the process to make the oxide etchback structure described above for the first few steps. That is, an N+ buried layer and channel stoppers are formed in the same manner as described with reference to Figure 3. Next, a layer of oxide is grown over the surface of the wafer and two holes are etched in it over the buried layer as was done for the oxide etch back embodiment. Two epitaxially grown, monocrystalline silicon columns will be grown in these holes to serve as the emitter, base and collector regions of the transistor. The steps to form the oxide layer and the holes are the same as the steps used to form the oxide etched back transistor and the same considerations apply, e.g., the thickness of the oxide layer will be set in accordance with the desired base width. Generally, the thickness of the composite oxide layer is about 0.5 to 2 micrometers (microns). Figure 14 shows the structure of the lateral growth embodiment in an early stage of the process of manufacture after the selectively grown epitaxial silicon is grown and allowed to laterally spread over the top of the oxide layer. To reach the stage shown in Figure 14, epitaxial silicon columns 42 and 38 are grown in the holes 68 and 70, respectively, formed in the oxide layer 66 as described above. After the epitaxial silicon columns are grown, the structure is oxidized at 850 to 1000 degrees centigrade in dry oxygen for 30 minutes. This prevents leakage along the interface between the epitaxial silicon and the field oxide. Throughout the discussion of this lateral spread embodiment, the same reference numerals will be used for structures which are the same or close to the same as the corresponding structures in the oxide etch back embodiment described above. Any differences in the structures or the methods of fabrication of same will be described here. The difference over the oxide etch back embodiment described above is that the amount of hydrochloric acid (HCl) vapor present during the epitaxial growth is reduced in the lateral growth embodiment. This allows the selectively grown epitaxial silicon columns 42 and 38 to grow laterally out over the top of the oxide layer as shown at 100 and 102. Generally, the right level for HCl vapor depends upon the temperature and pressure at which the reaction is carried out. The reaction should be carried at a temperature somewhere between 800 and 1100 degrees Celsius and at a pressure between 3′332.5 and 10′664 Pa. (25 and 80 torr). A temperature of 1000 degrees Celsius and a pressure of 5′998.5 Pa. (45 torr) are preferred. The relationship between the proper amount of HCl vapor and the temperature and pressure of the reaction is given in the paper by Borland and Drowley cited above which is incorporated by reference herein. Specifically, at page 146 of that article, graphs are given of the required HCl flow rate versus pressure and temperature at various flow rates of hydrogen gas. Figure 15A is the relationship of the HCl flow rate necessary to achieve selective epitaxial silicon growth at 25 torr and various temperatures. Figure 15B is the relationship of the HCl flow rate necessary to achieve selective epitaxial silicon growth at 10′664 Pa. (80 torr) and various temperature. It can be seen from these figures that selective growth of epitaxial silicon occurs at lower HCl flow rates at lower temperatures. Lower temperatures of reaction are preferred to minimize donor concentrations in the epitaxial silicon grown using this method. The HCl rate should be selected for the reaction conditions chosen so that growth as opposed to etching occurs and so that the operating point, i.e., the point representing all the operating conditions is below line 104 in Figure 15A or line 106 in Figure 15B so that selective growth occurs during the phase when the holes 68 and 70 are being filled. After the holes are filled however, the HCl flow rate is changed, in the preferred embodiment, so that non selective growth occurs, i.e., the operating point is shifted to a point above line 104 in Figure 15A or line 106 in Figure 15B. This allows the epitaxial silicon to spread out over the oxide layer 66 as shown at 100 and 102. In alternative embodiments, the HCl rate does not have to be changed since the growth of epitaxial silicon over the oxide will occur anyway even if the HCl rate is not changed. The growth rate will be slower, but since not much overgrowth is necessary, the slow growth is acceptable. Care should be taken to insure that the reaction temperature does not drop so low as to cause formation of polysilicon as opposed to epitaxial, single crystal silicon. Selective growth of epitaxial silicon can occur at temperatures as low as 800°C. (degrees centigrade) but the deposition rate at these temperatures is very low. The temperature should be kept below 1100°C. (degrees centigrade) however so as to minimize outdiffusion of dopants from the buried layer 34 into the epitaxial silicon in the holes 68 and 70 and into the substrate 30. For the oxide etchback embodiment described above, the HCl flow rate should be selected to cause selective growth only so as to prevent any lateral spreading. The processes described herein can also be used to make CMOS or PMOS or NMOS transistors. The techniques described herein allow CMOS devices to be made without the use of P well isolation. This eliminates the parasitic devices which result from the presence of the P well thereby reducing latchup problems and increasing the device operating speed. Further, NMOS devices could be made on the laterally spread portions of the epitaxial silicon at 100 and 102 if the lateral spread can be made large enough to fit the devices on the laterally spread portions. In the bipolar devices taught herein, there is no need to grow the epitaxial silicon more than 2 microns laterally beyond the edges of the holes 68 and 70 assuming a 1 micron lithography design rule. The extent of the lateral growth, i.e., the dimension A in Figure 14, need be no more than the minimum linewidth of the process being used plus adequate alignment tolerances. This is necessary to allow a contact window to be formed over the laterally spread portion of each base region epitaxial silicon column, i.e., the column 42. Figure 14 also shows a P type base implant to lightly dope the two columns 42 and 38 of epitaxial silicon P type. Typically, this implant will have a dosage of 5 to 20 x 10¹² atoms per square centimeter at an energy of 15 - 40 KEV. Figure 16 shows the structure of during the N type implant used to dope the collector column of silicon N type. During this implant, the column of epitaxial silicon 42 is protected from the ions by a layer of photoresist 108, but the ions are free to enter the epitaxial silicon column 38 which will form the collector contact. This implant is normally done at 80 - 150 KEV and a dosage of 5 x 10¹⁵ atoms per square centimeter for a column height, i.e., the dimension B in Figure 15 of 400 to 800 nm. (4000 to 8000 angstroms). After this implant, the photoresist is removed. Figure 17 shows the structure after the polysilicon layer which will form the emitter and collector contact structures has been deposited, doped N+ and etched and during a boron implant to decrease the resistance of the laterally spread portions of the epitaxial silicon. The first step is to deposit a layer of polysilicon over the laterally spread epitaxial silicon to a thickness of 100-300 nm. (1000-3000 angstroms). Then this polysilicon is doped N+ with an arsenic implant or other N type dopant. The polysilicon layer is then masked with a layer of photoresist which is exposed and developed to leave two portions 110 and 112 of photoresist over the columns as etch masks. The polysilicon is then etched with a plasma or other etch to leave the emitter contact portion 114 and the collector contact portion 116. Finally, the structure as thus configured is subjected to a boron implant at 15 to 40 KEV with a dosage of from 1 x 10¹³ to 1 x 10¹⁵ to reduce the resistivity of the laterally spread portion of the epitaxial silicon. Figure 18 shows the process step of forming oxide sidewall spacers on the polysilicon electrodes using a plasma etch. The purpose of this step is to create a layer of electrically insulating material on the sidewalls of the polysilicon electrodes 114 and 116 which are perpendicular to the surface of the substrate, i.e., in the y-z plane. To do this using an anisotropic etch, the first step is to deposit a layer of oxide 118. In alternative embodiments, a layer of silicon nitride may be used. The layer of insulating material 118 may be deposited in any known manner, and the manner of deposit is not critical to the invention. The thickness of this layer 118 of insulating material is 150-400 nm. (1500 to 4000 angstroms in the preferred embodiment. This thickness is selected to provide sufficient electrical integrity between the base contact and the emitter contact. However, it should not be so thick as to prevent sufficient alignment tolerance for formation of the base contact windows over the laterally grown epitaxial silicon. The alignment tolerance mentioned here is distance from the lateral extent on the x axis of the spacer shoulder formed in the step shown in Figure 18 and the most lateral extent along the x axis of the laterally grown epitaxial silicon. After depositing the layer 118, an anisotropic plasma etch (or reactive ion etch) is performed of sufficient duration to remove all portions of the insulating layer 118 lying in the x-y plane, i.e., parallel to the surface of the substrate. Either before, after or during formation of the oxide layer 118, a drive in step is performed to form the emitter region 119 in the base epitaxial silicon 42. This drive in step is a heat treatment in a diffusion furnace which causes the N+ impurities from the emitter poly 114 to diffuse into the base epitaxial silicon and convert the region 119 from P- doping to N+ doping. The time and temperature of this drive in step depends upon the desired base width from the emitter-base junction to the base-collector junction, upon the height (dimension A in Figure 18) and upon the doping level of the base epitaxial silicon 42. In the preferred embodiment with the dimension A of 400 to 800 nm. (4000 to 8000 angstroms) and a base width of 100 to 200 nm. (1000 to 2000 angstroms) and a base doping of 2 to 20 x 10¹² atoms per square centimeter, the drive in step should be performed at between 800 and 1000°C. (degrees centigrade) for between 15 and 45 minutes. The preferred embodiment uses temperatures between 850 and 950 degrees centigrade. The correct time and temperature for the emitter drive in must be experimentally determined given the parameters for desired base width, base doping and epitaxial silicon height the user is using. Any oxide that is inadvertently formed during this step should be removed before the next step. Preferably, the emitter drive in step is performed in a nitrogen ambient to prevent any oxide from forming. Figure 19 shows the structure after the insulating spacers have been formed on the sides and layers of silicide have been formed on the tops of the polysilicon contacts. The insulating spacers formed in the step shown in Figure 18 are shown at 120 and 122 for the emitter contact 114 and at 124 and 126 for the collector contact. Actually, the spacers are continuous around the edges of the polysilicon contacts 114 and 116, The silicide layers on top of the polysilicon contacts are shown at 128 and 130. Silicide is also formed on top of the laterally grown portions of the epitaxial silicon as shown at 132, 134, 136 and 138. These layers are formed by depositing a layer of refractory metal over the structure and heat treating it in known fashion to form silicide everywhere the refractory metal is in contact with silicon. The silicide formation reaction is done at approximately 700°C. (degrees centigrade) for approximately 30 seconds in a rapid thermal anneal process at atmospheric pressure in nitrogen ambient. After the silicide if formed, the unreacted refractory metal is removed to leave the structure as shown in Figure 19. The presence of the silicide reduces the sheet resistance of the contact structures from about 200 ohms per square for doped polysilicon to 2 ohms per square for silicide coated polysilicon and silicide coated doped epitaxial silicon. The silicide layer does not have to be formed, but if it is not formed, a higher base resistance and series resistance with the emitter and collector contacts will result. By virtue of the contact to the base from the sidewall instead of having to have an extended path through the epi to the surface from the emitter-base junction in the epitaxial silicon, the extrinsic base resistance, i.e., the resistance of the path from the base-emitter junction to the surface contact, is reduced substantially. Figure 20 shows a cross sectional view of the finished structure after metal contacts have be formed in contact windows in an overlying insulating layer. To reach the stage shown in Figure 20, a layer 140 of insulating material capable of being reflowed is deposited over the structure. Such materials are well known in the art and include PVX II. Further, the layer 140 might actually be comprised of two or more layers of material. The layer 140 could be deposited by chemical vapor deposition or could be spun on depending upon the choice of materials. Any known method of forming a planarized layer of insulating material which is compatible with the underlying structures thermally and electrically will suffice. It is generally good practice to choose a material which will not crack as temperatures change due to differences in coefficients of thermal expansion. Further, it is good practice to choose a material which can be planarized at temperatures which will not cause outdiffusion of the impurities in the poly into the silicide or excessive diffusion of doped areas in the epitaxial silicon. Also, it is good practice to choose materials which do not have excessive impurities which will diffuse into the underlying structure and change its electrical characteristics. PVX II or known types of spun on gels which can be heat treated to turn them into binary glasses such as are known in the art will suffice for purposes of practicing the invention. After the layer 140 is formed, contact holes are cut over the locations of the emitter contact, the base contacts and the collector contact. The sizes of the emitter contact and collector contact should be such that a contact hole of at least the minimum linewidth on a side may be formed over the contacts with adequate alignment tolerances on each side of the contact hole. In some embodiments, the cross sectional area of the epitaxial silicon columns is the minimum obtainable area, i.e., the minimum linewidth on a side. The emitter contact may then be formed slightly larger than this minimum area such that a contact hole having the minimum obtainable cross sectional area may fit within the perimeter of the polysilicon contact. In other embodiments, the polysilicon of the emitter and base contacts may be extended out over the oxide field and expanded into a contact pad of sufficient dimension to fit a contact hole. The lateral extents of the epitaxial silicon should be sufficient to allow a contact hole to be at least partially formed over the portion of the epitaxial silicon that extends past the insulating shoulder. After all the contact holes are formed, a layer (not shown) of metal such as aluminum, a refractory metal such as titanium or tungsten or any other suitable metal or combination of metals or other conductive materials is deposited over the surface of the layer 140. This metal or other conductive material enters the contact holes and makes contact with the underlying emitter, collector and base contacts. The metal layer may then be patterned using photolithography and etching techniques to form a first layer metal interconnection pattern connecting the nodes of the transistor to other nodes in the circuit. As shown in Figure 20, the emitter contact 142, the collector contact 144 and the base contacts 146 are shown as metal. These contacts may also be made in the manner described with reference to Figure 13. Figure 21 shows a top view of the finished device. The advantages of the transistor structures taught herein include vastly improved speed bipolar transistors coupled with high density comparable with CMOS and NMOS. The size of the active region is the same as the size of the isolation island. Since the area of the base-emitter and collector-base junctions can be equal to the minimum linewidth, the parasitic junction capacitances associated with these junctions is much less. Further, since the base current path from the base contact to the base-emitter junction is shorter, the extrinsic base resistance is less. This also improves the transistor speed.

Claims: A bipolar transistor comprising: a buried layer (34) of a first conductivity type in a substrate (30), first (42) and second (38) columns of epitaxial mono-crystalline silicon on the buried layer, a first insulating layer (66) of silicon dioxide on the buried layer and surrounding the first and second columns, a conducting layer on the first insulating layer and laterally contacting an upper portion of the first epitaxial column, the upper portion being of a second conductivity type, and a region (119) of the first conductivity type formed at the top of the first epitaxial column, the buried layer (34), the upper portion and the region (119) respectively forming portions of a collector, a base and an emitter of the bipolar transistor, characterised in that the conducting layer is a portion of the first epitaxial column (42). A bipolar transistor as claimed in claim 1 comprising a polysilicon layer (114) of the first conductivity type in contact with the emitter region, the polysilicon layer exposing the epitaxial material extending laterally from the first epitaxial column (42). A bipolar transistor as claimed in claim 2 comprising a metal silicide layer (128,132) defined coextensively with the polysilicon layer (114) to provide an emitter contact and with the epitaxial material laterally extending from the first epitaxial column (42) to provide a base contact. A bipolar transistor as claimed in claim 3 wherein an insulating layer (120,122) at the sides of the defined polysilicon layer (114) separates the metal silicide emitter contact layer and the metal silicide base contact. A bipolar transistor as claimed in claim 1, 2, 3 or 4 wherein each column (42,38) has a top surface having a predetermined height above the buried layer (34), and the first insulating layer (66) of silicon dioxide surrounds the first and second columns to a distance below the predetermined height. A bipolar transistor as claimed in any preceding claim comprising a second insulating layer (140) over the conducting layer and having varying thicknesses so that the upper surface of the second insulating layer is substantially planar. A bipolar transistor as claimed in any preceding claim wherein the emitter region (119) is located within the cross-section of the first column (42). A bipolar transistor as claimed in any preceding claim wherein the first and second columns (42,38) are of constant cross-section. A bipolar transistor as claimed in any preceding claim wherein the second column is of the first conductivity type and forms a contact to the buried layer. A process of forming a bipolar transistor comprising the steps of: forming in a substrate (30) a buried layer (34) of a first conductivity type, forming a first insulating layer (66) of silicon dioxide on the buried layer, forming first and second openings in the first insulating layer exposing the buried layer, forming first (42) and second (38) columns of epitaxial mono-crystalline silicon in the first and second openings, respectively, on the buried layer, forming a conducting layer on the first insulating layer and laterally contacting an upper portion of the first epitaxial column, the upper portion being of a second conductivity type, and forming a region (56) of the first conductivity type formed at the top of the first epitaxial column, the buried layer (34), the upper portion and the region (56) respectively forming portions of a collector, a base and an emitter of the bipolar transistor, characterised in that the conducting layer is formed by lateral spread of the epitaxial mono-crystalline silicon of the first column (42) over the first insulating layer (66).

Inventors: CIACCHELLA FRANK J, KAPOOR ASHOK K, CIACCHELLA, FRANK J., KAPOOR, ASHOK K.
Applicants: FAIRCHILD SEMICONDUCTOR, FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1988
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27